•1200 baud Bell 202 and CCITT V.23 Frequency
Shift Keying (FSK) demodulation
•Compatible with Bellcore GR-30-CORE,
SR-TSV-002476, TIA/EIA-716 and
ETSI 300 778-1
•High input sensitivity
•Dual mode 3-wire data interface (Serial FSK
data stream or MT88E43 compatible 1 byte
buffer)
•Internal gain adjustable amplifier
•Carrier detect status output
•Uses 3.579545 MHz crystal or ceramic
resonator
•3 to 5V ±10% supply voltage
•Low power CMOS with power down mode
•Direct pin to pin replacement of MT8841 and
MT88E41
Applications
•Global (North America, Japan, Europe) FSK
based CID (Calling Identity Delivery) / CLIP
(Calling Line Identity Presentation)
•Feature phones, adjunct boxes
•FAX machines
•Telephone answering machines
•Computer Telephony Integration (CTI)
•Battery powered applications
DS5035ISSUE 3November 1998
Ordering Information
MT88E39AS16 Pin SOIC
-40 to +85 °C
Description
The MT88E39 Calling Number Identification Circuit
(CNIC1.1) is a CMOS integrated circuit which
provides an interface to calling line information
delivery services that utilize 1200 baud Bell 202 or
CCITT V.23 FSK data transmission schemes. The
MT88E39 receives and demodulates the FSK signal
and outputs the data into a simple dual mode 3-wire
serial interface which eliminates the need for an
UART.
The MT88E39 is Bellcore, ETSI and NTT compatible
and can operate in 3V and 5V applications. It is a pin
to pin replacement of the MT8841 and MT88E41 by
operating in the MT88E41 FSK interface mode
(mode 0) when placed in a MT88E41 socket. New
designs may also choose the MT88E43 compatible
interface (mode 1) where the microcontroller reads
the FSK byte from a 1 byte buffer.
GS
IN-
IN+
CAP
V
Ref
-
+
Bias
Generator
PWDNOSC1 OSC2V
Receive
Bandpass
Filter
Clock
Generator
Figure 1 - Functional Block Diagram
FSK
Demodulator
Carrier
Detector
to other
circuits
SSVDD
Data and Timing
Recovery
MODEIC
DATA
DR
DCLK
CD
5-1
Page 2
MT88E39Advance Information
IN+
IN-
GS
VRef
CAP
OSC1
OSC2
VSS
1
2
3
4
5
6
7
8
16 PIN SOIC
16
15
14
13
12
11
10
9
VDD
IC**
MODE*
PWDN
CD
DR
DATA
DCLK
* Was IC1 in MT88E41
** Was IC2 in MT88E41
Figure 2 - Pin Connections
Pin Description
Pin #NameDescription
1IN+Non-inverting Op-Amp (Input).
2IN-Inverting Op-Amp (Input).
3GSGain Select (Output). Gives access to op-amp output for connection of feedback resistor.
4V
5CAPCapacitor. Connect a 0.1µF capacitor to VSS.
6OSC1 Oscillator (Input). Crystal connection. This pin can be driven directly from an external
7OSC2 Oscillator (Output). Crystal connection. When OSC1 is driven by an external clock, this pin
8VSSPower supply ground.
9DCLK 3-wire FSK Interface: Data Clock (CMOS Output/Schmitt Input). In mode 0 (MT88E41
10DATA3-wire FSK Interface: Data (CMOS Output). In mode 0 (MT88E41 compatible mode - when
11DR3-wire FSK Interface: Data Ready (Open Drain/CMOS Output). Active low. In mode 0
12CDCarrier Detect (Open Drain/CMOS Output). Active low. In mode 0 (MT88E41 compatible
13PWDN Power Down (Schmitt Input). Active high. Powers down the device including the input
Voltage Reference (Output). Nominally V
Ref
/2. This is used to bias the op-amp inputs.
DD
clocking source.
should be left open.
compatible mode - when the MODE pin is logic low) this is a CMOS output which denotes the
nominal mid-point of a FSK data bit.
In mode 1 (when the MODE pin is logic high) this is a Schmitt trigger input used to shift the
FSK data byte out to the DATA pin.
the MODE pin is logic low) the FSK serial bit stream is output to DATA as demodulated. Mark
frequency corresponds to logical 1. Space frequency corresponds to logical 0.
In mode 1 (when the MODE pin is logic high) the start and stop bits are stripped off and only
the data byte is stored in a 1 byte buffer. At the end of each word signalled by the DR pin, the
microcontroller should shift the byte out to DATA pin by applying 8 read pulses at the DCLK pin.
(MT88E41 compatible mode - when the MODE pin is logic low) this is an open drain output. In
mode 1 (when the MODE pin is logic high) this is a CMOS output.
This pin denotes the end of a word. Typically, DR is used to interrupt the microcontroller. It is
normally hi-Z or high (modes 0 and 1 respectively) and goes low for half a bit time at the end of
a word. But in mode 1 if DCLK begins during DR low, the first rising edge of the DCLK input
will return DR to high. This feature allows an interrupt requested by DR to be cleared upon
reading the first DATA bit.
mode - when the MODE pin is logic low) this is an open drain output. In mode 1 (when the
MODE pin is logic high) this is a CMOS output.
A logic low indicates that a carrier has been present for a specified time on the line. A time
hysteresis is provided to allow for momentary discontinuity of carrier. The demodulated FSK
data is inhibited until the carrier has been detected.
op-amp and the oscillator. Must be low for operation.
5-2
Page 3
Advance InformationMT88E39
Pin Description
Pin #NameDescription
14MODE Mode select (Input). This pin selects the 3-wire FSK interface mode. To select mode 0
(MT88E41 compatible mode) this pin should be logic low. To select mode 1 this pin should be
logic high.
Because this pin is already connected to Vss in ’E41 applications, the MT88E39 can replace
the ’E41 without any circuit or software change.
15ICInternal Connection. Internal connection. Leave open circuit. In MT88E41, this was IC2
which was also left open in the application circuit.
16V
Positive power supply voltage.
DD
Functional Description
The MT88E39 is a FSK demodulator compatible with
FSK based Caller ID services around the world, such
as in North America, France, Germany, and Japan.
Caller ID is the generic term for a group of services
offered by telephone operating companies whereby
information about the calling party is delivered to the
subscriber. In the FSK based methods, the
information is modulated in either Bell 202 (in North
America) or CCITT V.23 (in Europe) FSK format and
transmitted at 1200 baud from the serving end office
to the subscriber’s terminal.
In North America, Caller ID uses the voiceband data
transmission interface defined in the Bellcore
document GR-30-CORE. The terminal or CPE
(Customer Premises Equipment) requirements are
defined in Bellcore document SR-TSV-002476.
Typical services are CND (Calling Number Delivery),
CNAM (Calling Name Delivery), VMWI (Visual
Message Waiting Indicator) and CIDCW (Calling
Identity Delivery on Call Waiting).
The MT88E39 provides an interface to the Caller ID
physical layer. It bandpass filters and demodulates
the 1200 baud FSK signal. It also provides a
convenient interface to extract the demodulated FSK
data. Although the main application of the MT88E39
is Caller ID, it can also be used wherever 1200 baud
Bell 202 and/or CCITT V.23 FSK reception is
required.
3 to 5V operation
The MT88E39 can operate from 5.5V down to 2.7V,
but the FSK reject level will change with Vdd. In a
battery powered CPE, the FSK accept level will
become lower as the batteries are run down. If the
CPE is designed for 4.5V, the accept level will be
lowered when the batteries drain to 3V. In North
America there is a requirement for rejecting FSK
signals which are below 3 mVrms when data is not
preceded by ringing, such as VMWI (Visual Message
Waiting Indicator) applications. When the batteries
are drained, the CPE will not meet the reject level.
For on-hook Caller ID, there is no reject level and the
CPE will meet all requirements.
In on-hook Caller ID, such as CND and CNAM, the
information is typically transmitted from the end
office before the subscriber picks up the phone.
There are various methods such as between the first
and second rings (North America), between an
abbreviated ring and the first true ring (Japan,
France and Germany). On-hook Caller ID can also
occur without ringing for services such as VMWI.
The MT88E39 is suitable for these for ms of alerting.
In off-hook Caller ID, such as CIDCW, information
about a new calling party is sent to the subscriber
who is already engaged in a call. Bellcore’s method
uses a special dual tone known as CAS (CPE
Alerting Signal) which should be detected by the
CPE. After the CPE has acknowledged with a DTMF
digit, the end office will send the FSK data. The
MT88E39 is suitable for receiving the FSK data but a
separate CAS detector is required.
Input Configuration
The input arrangement of the MT88E39 provides an
operational amplifier, as well as a bias source (V
which is used to bias the inputs at V
/2. Provision is
DD
Ref
made for connection of a feedback resistor to the
op-amp output (GS) for adjustment of gain.
Figure 3 shows the necessary connections for a
differential input configuration. In a single-ended
configuration, the input pins are connected as shown
in Figure 4.
5-3
)
Page 4
MT88E39Advance Information
Mode 0
R1
C1
R4
C2
R3
DIFFERENTIAL INPUT AMPLIFIER
C1 = C2
R1 = R4
R3 = (R2 x R5) / (R2 + R5)
For unity gain, R5 = R1
VOLTAGE GAIN
(AVdiff) = R5/R1
R2
INPUT IMPEDANCE
(ZINdiff) = 2
R5
IN+
IN-
GS
V
Ref
MT88E39
R1
Figure 3 - Differential Input Configuration
IN+
R
C
IN
R
F
IN-
GS
2
+ (1/ωC)
This mode is selected when the MODE pin is low. It
is the MT88E41 compatible mode where the FSK
data stream is output as demodulated. Since the
MODE pin was IC1 in MT88E41 and connected to
Vss, the MT88E39 will work in mode 0 when placed
in a MT88E41 socket.
In this mode, the MT88E39 receives the FSK signal,
demodulates it, and outputs the data directly to the
DATA pin (see Figure 11). For each received stop
and start bit sequence, the MT88E39 outputs a fixed
frequency clock string of 8 pulses at the DCLK pin.
Each DCLK rising edge occurs in the nominal centre
2
of a data bit. DCLK is not generated for the stop and
start bits. Consequently, DCLK will clock only valid
data into a peripheral device such as a serial to
parallel shift register or a microcontroller. The
MT88E39 also outputs an end of word pulse (Data
Ready) on the DR pin, which indicates the reception
of every 10-bit word (counting the start and stop bits)
sent from the end office. DR can be used to interrupt
a microcontroller or cause a serial to parallel
converter to parallel load its data into a
microcontroller. The mode 0 DATA pin can also be
connected to a personal computer’s serial
communication port after converting from CMOS to
RS-232 voltage levels.
V
VOLTAGE GAIN
) = RF / R
(A
V
IN
Ref
MT88E39
Figure 4 - Single-Ended Input
Configuration
3-wire FSK Data Interface
The MT88E39 provides a powerful dual mode 3-wire
interface so that the 8-bit data words in the
demodulated FSK bit stream can be extracted
without the need either for an external UART or for
the microcontroller to perform the UART function in
software. The interface is specifically designed for
the 1200 baud rate and is comprised of the DATA,
DCLK (data clock) and DR (data ready) pins. Two
modes (0 and 1) are selectable via control of the
device’s MODE pin. In mode 0 the FSK bit stream is
output as demodulated. In mode 1 the FSK data byte
is store in a 1 byte buffer. Note that in mode 0 DR
and CD are open drain outputs; in mode 1 they are
CMOS outputs. DCLK is an output in mode 0, an
input in mode 1.
Mode 1
This mode is selected when the MODE pin is high. In
this mode, the microcontroller supplies read pulses
at the DCLK pin (which is now an input) to shift the
8-bit data words out of the MT88E39, onto the DATA
pin. The MT88E39 asserts DR to denote the word
boundary and indicate to the microprocessor that a
new word has become available (see Figure 12).
Internal to the MT88E39, the demodulated data bits
are sampled and stored. The start and stop bits are
stripped off. After the 8th bit, the data byte is parallel
loaded into an 8 bit shift register and DR goes low.
The shift register’s contents are shifted out to the
DATA pin on the supplied DCLK’s rising edge in the
order they were received.
If DCLK begins while DR is low, DR will return to high
upon the first DCLK. This feature allows the
associated interrupt to be cleared by the first read
pulse. Otherwise DR is low for half a nominal bit time
(1/2400 sec). After the last bit has been read,
additional DCLKs are ignored.
5-4
Note that in both modes, the 3-pin interface may also
output data generated by speech or other voiceband
Page 5
Advance InformationMT88E39
signals. The user may choose to ignore these
outputs when FSK data is not expected, or force the
MT88E39 into its power down mode.
Power Down Mode
For applications requiring reduced power
consumption, the MT88E39 can be forced into power
down when it is not needed. This is done by pulling
the PWDN pin high. In power down mode, the
oscillator, op-amp and internal circuitry are all
disabled and the MT88E39 will not react to the input
signal. DR and CD are at high impedance or at logic
high (modes 0 and 1 respectively). In mode 0, DATA
and DCLK are at logic high. The MT88E39 can be
awakened for reception of the FSK signal by pulling
the PWDN pin low.
Carrier Detect
The carrier detector provides an indication of the
presence of a signal in the FSK frequency band. It
detects the presence of a signal of sufficient
amplitude at the output of the FSK bandpass filter.
The signal is qualified by a digital algorithm before
the CD output is set low to indicate carrier detection.
A 10ms hysteresis is provided to allow for
momentary signal drop out once CD has been
activated. CD is released when there is no activity at
the FSK bandpass filter output for 10 ms.
When CD is inactive (high), the raw output of the
demodulator is ignored by the data timing recovery
circuit (see Figure 1). In mode 0, the DATA pin is
forced high. No DCLK or DR signal is generated. In
mode 1, the internal shift register is not updated and
no DR is generated. If DCLK is clocked (in mode 1),
DATA is undefined.
The crystal specification is as follows:
Frequency:
Frequency tolerance:
Resonance mode
:Parallel
Load capacitance:
Maximum series resistance
Maximum drive level (mW):
3.579545 MHz
±0.2%(-40°C+85°C)
18 pF
:150 ohms
2 mW
e.g. CTS MP036S
MT88E39MT88E39MT88E39
OSC1 OSC2OSC1 OSC2
3.579545 MHz
OSC1 OSC2
to the
next MT88E39
(For 5V application only)
Figure 5 - Common Crystal Connection
For 5V applications any number of MT88E39 devices
can be connected as shown in Figure 5 such that
only one crystal is required. The connection between
OSC2 and OSC1 can be DC coupled as shown, or
the OSC1 input on all devices can be driven from a
CMOS buffer (dc coupled) with the OSC2 outputs left
unconnected.
V
and CAP Inputs
Ref
V
is the output of a low impedance voltage source
Ref
equal to V
A 0.1µF capacitor is required between CAP and V
to suppress noise on V
/2 and is used to bias the input op-amp.
DD
Ref.
SS
Applications
Note that signals such as CAS, speech and DTMF
tones also lie in the FSK frequency band and the
carrier detector may be activated by these signals.
They will be demodulated and presented as data. To
avoid false data, the PWDN pin should be used to
disable the FSK demodulator when no FSK signal is
expected.
Ringing, on the other hand, does not pose a problem
as it is ignored by the carrier detector.
Crystal Oscillator
The MT88E39 uses either a 3.579545MHz ceramic
resonator or crystal oscillator as the master timing
source.
Table 1 shows the Bellcore and ETSI FSK signal
characteristics. The application circuit in Figure 6 will
meet these requirements.
For 5V designs the input op-amp should be set to
unity gain to meet the Bellcore requirements and
-2.5 dB gain for ETSI requirements.
As supply voltage (VDD) is decreased, the FSK
detect threshold will be lowered. Therefore for
designs operating at other than 5V nominal voltage,
to meet the FSK reject level requirement the gain of
the op-amp should be reduced accordingly.
For 3V designs the gain settings for Bellcore and
ETSI should be -3dB and -5.5dB respectively.
5-5
Page 6
MT88E39Advance Information
For applications requiring detection of lower FSK
signal level, the input op-amp may be configured to
provide adequate gain. However, too much gain will
cause noise tolerance to fail the TIA requirements
because the FSK signal will be clipped at GS when
the single tone noise is added.
TIP
RING
100nF
10%
50V
330nF
10%
250V
Note:
*1R8 and R9 not required when FSK interface mode 1 is selected.
For Bellcore applications, set input gain = 0dB:For ETSI applications, set input gain = -2.5dB:
For Bellcore applications, set input gain = -3 dB:For ETSI applications, set input gain = -5.5dB:
Example of component values for Vdd = 5V +/- 10%
R5 = 53K6R5 = 53K6
R6 = 60K4R6 = 63K4
R7 = 464KR7 = 348K
Example of component values for Vdd = 3V +/- 10%
R5 = 44K2R5 = 44K2
R6 = 51K1R6 = 53K6
R7 = 332KR7 = 249K
Figure 6 - Application Circuit
5-6
Page 7
Advance InformationMT88E39
ParameterNorth America: Bellcore
*1
Europe: ETSI
*2
Mark (logical 1) frequency1200 Hz +/- 1%1300 Hz +/- 1.5%
Space (logical 0) frequency2200 Hz +/- 1%2100 Hz +/- 1.5%
Received signal level-36.20 to -4.23 dBm
(12 to 476 mVrms)
Reject signal level-48.23 dBm (3 mVrms)
*3
-33.78 to -5.78 dBm
(-36 to -8 dBV*4)
-47.78 dBm (-50 dBV)
(VMWI only)
Transmission rate1200 baud +/- 1%1200 baud +/- 1%
Twist-6 to +10 dB-6 to +6 dB
Signal to noise ratioSingle tone (f):
-18 dB (f<=60Hz)
-12 dB (60<f<=120Hz)
-6 dB (120<f<=200Hz)
>= 25 db
(300 to 3400 Hz)
+25 dB (200<f<3200Hz)
+6 dB (f>=3200Hz)
MT88E39 FSK input gain
0 dB-2.5 dB
for Vdd=5V +/-10%
Table 1 - FSK signal characteristics specified by some standard bodies
Notes:
*1: Recommended by TIA/EIA-716. Bellcore has agreed to the values and will incorporate them into its future standards.
*2: ETS 300 778-1 (On-hook) Sep 97, ETS 300 778-2 (Off-hook) Jan 97.
*3: dBm = Decibels above or below a reference power of 1mW into 600 ohms. 0dBm=0.7746Vrms.
*4: dBV = Decibels above or below a reference voltage of 1Vrms. 0dBV=1Vrms.
*5: On-hook signal range. The Off-hook signal levels are inside this range: -30.78 to -7.78 dBm.
*5
Interrupt Source 1
INT1
(open drain)
Interrupt Source 2
INT2
(CMOS)
MT88E39
DR
(Mode 0: Open Drain)
(Mode 1: CMOS
Vdd
R1
D1
R1 can be opened and
D1 shorted if the
microcontroller does not
read the
Absolute Maximum Ratings* - Voltages are with respect to V
unless otherwise stated.
SS
ParameterSymbolMinMaxUnits
1DC Power Supply Voltage VDD to V
SS
2Voltage on any pinV
3Current at any pin (except VDD and VSS)I
4Storage TemperatureT
5Package Power DissipationP
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (V
V
DD
P
I/O
ST
D
-0.36V
-0.3VDD+0.3V
-65+150°C
) unless otherwise stated
SS
CharacteristicsSymMinTypMaxUnitsTest Conditions
1DC Power Supply VoltageV
2Clock Frequencyf
DD
OSC
2.75.5V
3.579545
MHz
3Tolerance on Clock Frequency∆fc±0.2%
4Operating Temperature-40+85°C
DC Electrical Characteristics
†
±10mA
500mW
CharacteristicsSymMinTyp*MaxUnits
S
1
2Operating Supply Current
3
DATA,
4Source current
DCLK
Standby Supply Current I
U
P
P
L
Y
DR,
Sink CurrentI
CD,
VDD=3.0V, 25oC
VDD=5.0V, 25oC
DATA
DCLK (in mode 0)
DR, CD (in mode 1)
DR, CD
5
Output hi-Z current
(in mode 0)
6
PWDN,
DCLK
mode 1)
7Schmitt HysteresisV
8
MODE
PWDN,
9
DCLK,
MODE
Schmitt Input High Threshold
Schmitt Input Low Threshold
(in
CMOS Input High Voltage
CMOS Input Low Voltage
Input CurrentI
DDQ
I
I
OH
I
V
V
HYS
V
V
DD
OL
OZ
IN
T+
Test
Conditions
0.115µANotes* 1
Notes* 2
1.2
1.9
2.5mAVOL=0.1V
0.8mAVOH=0.9V
0.48*V
0.28*V
T-
DD
DD
2.0
3.0
mA
mA
10µAVOZ=VSS to V
0.68*V
0.48*V
DD
DD
V
V
DD
DD
DD
0.2V
IH
IL
0.7*V
V
DD
SS
V
DD
0.3*V
DD
V
10µAVSS ≤ VIN≤ V
DD
10
11Output ResistanceR
† DC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
* Typical figures are at 25°C and are for design aid only.
Notes*:1.PWDN=Vdd. FSK input = 0 mVrms. Digital inputs at either Vdd or Vss. No current drawn from output pins.
5-8
Output VoltageV
VRef
2.PWDN=Vss. FSK input = 0 mVrms. With no current drawn from Vref, OSC2 and all digital pins.
0.5*VDD- 0.10.5*VDD + 0.1VNo Load
Ref
Ref
2kΩ
Page 9
Advance InformationMT88E39
Electrical Characteristics† - Gain Setting Amplifier
25mV
4Power Supply Rejection RatioPSRR30dB1kHz ripple on V
5Common Mode RejectionCMRR30dBV
6DC Open Loop Voltage GainA
7Unity Gain Bandwidthf
8Output Voltage SwingV
9Capacitive Load (GS)C
10 Resistive Load (GS)R
11 Common Mode Voltage RangeV
† Electrical characteristics are over recommended operating conditions, unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
VOL
C
O
L
L
CM
40dB
0.2MHz
0.5
VDD-0.7
VLoad ≥ 100kΩ
50pF
100kΩ
1.0
VDD-1.0
V
CMmin
≤ VIN ≤ V
AC Electrical Characteristics† - FSK
CharacteristicsSymMinTyp‡MaxUnitsNotes*
DD
DD
CMmax
1Input Detection Level-37.78
-40
10
-1.78
-4
631
dBm
dBV
mVrms
1, 2, 3, 4
2Input Baud Rate118812001212baud6
3Input Frequency Detection
Bell 202 1 (Mark)
Bell 202 0 (Space)
CCITT V.23 1 (Mark)
CCITT V.23 0 (Space)
4Input Noise Tolerance 20 logSNR20dB3, 4, 5
5Twist=20 log-610dB
† AC Electrical Characteristics are over recommended operating conditions, unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Notes*:
1. dBm = Decibels above or below a reference power of 1mW into 600Ω. 0dBm=0.7746Vrms.
2. dBV = Decibels above or below a reference voltage of 1Vrms. 0dBV=1Vr ms.
3. Input op-amp configured to 0dB gain at Vdd=5V+/-10%, -3dB at Vdd=3V+/-10%.
4. Mark and Space frequencies have the same amplitude.
5. Band limited random noise (200-3400Hz). Present when FSK signal present.
6. OSC1 at 3.579545 MHz ±0.2%.
V
Mark
()
V
Space
signal
()
noise
1188
2178
1280.5
2068.5
1200
2200
1300
2100
1212
2222
1319.5
2131.5
Hz
}6 BELL 202 Frequencies
Hz
Hz
}6 CCITT V.23 Frequencies
Hz
5-9
Page 10
MT88E39Advance Information
AC Electrical Characteristics† - Timing
CharacteristicsSymMinTyp
‡
MaxUnitsNotes*
1
PWDN
OSC1
2Power-down timet
3
4Input FSK to CD high delayt
Power-up time t
Input FSK to CD low delayt
CD
PU
PD
IAL
IAH
50ms
1001000µs1
25ms
10ms
5Hysteresis10ms
† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only, not guaranteed and not subject to production testing.
Notes*:
1. The device will stop functioning within this time, but more time may be required to reach I
DDQ
.
AC Electrical Characteristics† - 3-Wire FSK Interface Timing (Mode 0)
CharacteristicsSymMinTyp
DATA
1
Rate118812001212bps1, 6
2Input FSK to DATA delayt
3
4Fall timet
DATA
DCLK
5DATA to DCLK delayt
Rise timet
6DCLK to DATA delayt
7
Frequency1200.41202.81205.2Hz2
IDD
R
F
DCD
CDD
6416µs1, 2, 5, 6
6416µs1, 2, 5, 6
‡
MaxUnitsNotes*
15ms
200ns3
200ns3
DCLK
8High timet
9Low timet
DCLK
10
11
12Fall timet
DCLK to DR delayt
DR
Rise timet
DR
13Low timet
† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only, not guaranteed and not subject to production testing.
Notes*:
1. FSK input data at 1200 ±12 baud.
2. OSC1 at 3.579545 MHz ±0.2%.
3. 10k to VSS, 50pF to V
4. 10k to VDD, 50pF to VSS.
5. Function of signal condition.
6. For a repeating mark space sequence, the data stream will typically have equal 1 and 0 bit durations.
SS.
CH
CL
CRD
RR
FF
RL
415416417µs2
415416417µs2
415416417µs2
10µs4
200ns4
415416417µs2
AC Electrical Characteristics† - 3-Wire FSK Interface Timing (Mode 1)
CharacteristicsSymMinTyp
1
DCLK
2Duty Cycle3070%
Frequencyf
DCLK1
3Rise Time100ns
‡
MaxUnitsNotes*
1MHzSee Fig. 12
4
DCLK
5DCLK low hold time to DRt
† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only, not guaranteed and not subject to production testing.
5-10
DCLK low setup time to DRt
DR
DDS
DDH
500nsSee Fig. 12
500nsSee Fig. 12
Page 11
Advance InformationMT88E39
DATA
DCLK
t
t
R
DCD
t
CL
t
R
t
CDD
t
CH
t
F
t
F
Figure 8 - DATA and DCLK Output Timing (Mode 0)
t
DR
FF
t
RL
t
RR
Figure 9 - DR Output Timing (Mode 0)
2 sec
channel seizure
Mark state
checksum
TIP/RING
PWDN
OSC2
CD *
DATA
DCLK
(mode 0)
First Ring
High (Input Idle)
t
PU
500ms
(min)
t
IAL
Input FSK
Data
200ms
(min)
t
IAH
Second
Ring
t
PD
High (Input Idle)
DR *
* with pull-up resistor in mode 0
Figure 10 - Input and Output Timing (Bellcore CND Service)
5-11
Page 12
MT88E39Advance Information
start
stop
TIP/RING
DAT A
DCLK
DR *
* with external pull-up resistor
Demodulated
Data
(Internal Signal)
DR (Data Ready)
CMOS
Output
DCLK (Data Clock)*
Schmitt Input
t
DDS
b7
10
t
IDD
b7b0 b1 b2 b3 b4 b5
word N
7
t
DDH
b0 b1 b2 b3 b4 b5
start
stop
Figure 11 - Serial Data Interface Timing (Mode 0)
stop
start
➀
1/f
DCLK1
start
stop
b6
b7
10
b6
b7b0 b1 b2 b3 b4 b5
0
1
b0 b1 b2 b3 b4 b5
start
stop
t
CRD
word N+1
234
b6
5
start
stop
b0 b1 b2
10
b7
start
b6
b7
stop
67
t
RL
b0 b1 b2
stop
➁
DATA Output
*
The DCLK input must be low before and after
DCLK clears DR
➀
➁
DCLK does not clear DR, so DR is low for maximum time (1/2 bit time)
6
word N-1
01234567
7
word N
DR falling edge
Figure 12 - Serial Data Interface Timing (Mode 1)
0
5-12
Page 13
Pin 1
Package Outlines
E
A
A
1
16-Pin18-Pin20-Pin24-Pin28-Pin
DIM
MinMaxMinMaxMinMax
A0.093
A
B0.013
C0.009
D0.398
E0.291
e0.050 BSC
H0.394
L0.016
(2.35)
1
0.004
(0.10)
(0.33)
(0.231)
(10.1)
(7.40)
(1.27 BSC)
(10.00)
(0.40)
0.104
(2.65)
0.012
(0.30)
0.020
(0.51)
0.013
(0.318)
0.413
(10.5)
0.299
(7.40)
0.419
(10.65)
0.050
(1.27)
D
0.093
(2.35)
0.004
(0.10)
0.013
(0.33)
0.009
(0.231)
0.447
(11.35)
0.291
(7.40)
0.050 BSC
(1.27 BSC)
0.394
(10.00)
0.016
(0.40)
L
e
4 mils (lead coplanarity)
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
4) A & B Maximum dimensions include allowable mold flash
B
0.104
(2.65)
0.012
(0.30)
0.030
(0.51)
0.013
(0.318)
0.4625
(11.75)
0.299
(7.40)
0.419
(10.65)
0.050
(1.27)
0.093
(2.35)
0.004
(0.10)
0.013
(0.33)
0.009
(0.231)
0.496
(12.60)
0.291
(7.40)
0.050 BSC
(1.27 BSC)
0.394
(10.00)
0.016
(0.40)
0.104
(2.65)
0.012
(0.30)
0.020
(0.51)
0.013
(0.318)
0.512
(13.00)
0.299
(7.40)
0.419
(10.65)
0.050
(1.27)
Lead SOIC Package - S Suffix
C
H
L
MinMaxMinMax
0.093
(2.35)
0.004
(0.10)
0.013
(0.33)
0.009
(0.231)
0.5985
(15.2)
0.291
(7.40)
0.050 BSC
(1.27 BSC)
0.394
(10.00)
0.016
(0.40)
0.104
(2.65)
0.012
(0.30)
0.020
(0.51)
0.013
(0.318)
0.614
(15.6)
0.299
(7.40)
0.419
(10.65)
0.050
(1.27)
0.093
(2.35)
0.004
(0.10)
0.013
(0.33)
0.009
(0.231)
0.697
(17.7)
0.291
(7.40)
0.050 BSC
(1.27 BSC)
0.394
(10.00)
0.016
(0.40)
(0.318)
0.7125
(10.65)
0.104
(2.65)
0.012
(0.30)
0.020
(0.51)
0.013
(18.1)
0.299
(7.40)
0.419
0.050
(1.27)
NOTES: 1. Controlling dimensions in parenthesis ( ) are in millimeters.
2. Converted inch dimensions are not necessarily exact.
General-7
Page 14
http://www.mitelsemi.com
World Headquarters - Canada
Tel: +1 (613) 592 2122
Fax: +1 (613) 592 6909
North AmericaAsia/PacificEurope, Middle East,
Tel: +1 (770) 486 0194Tel: +65 333 6193and Africa (EMEA)
Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively “Mitel”) is believed to be reliable. However, Mitel assumes no
liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of
patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or
service conveys any license, either express or implied, under patents or other intellectual property rights owned by Mitel or licensed from third parties by Mitel, whatsoever.
Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Mitel, or non-Mitel furnished goods or services may infringe patents or
other intellectual property rights owned by Mitel.
This publication is issued to provide information only and (unless agreed by Mitel in writing) may not be used, applied or reproduced for any pur pose nor form part of any order or
contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this
publication are subject to change by Mitel without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or
service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific
piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or
data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in
any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Mitel’s
conditions of sale which are available on request.
M Mitel (design) and ST-BUS are registered trademarks of MITEL Corporation
Mitel Semiconductor is an ISO 9001 Registered Company
Copyright 1999 MITEL Corporation
All Rights Reserved
Printed in CANADA
TECHNICAL DOCUMENTATION - NOT FOR RESALE
Loading...
+ hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.