Datasheet MT8889CS-1, MT8889CE-1, MT8889CN, MT8889CN-1, MT8889CC Datasheet (MITEL)

MT8889C/MT8889C-1



Integrated DTMFTransceiver

with Adaptive Micro Interface

Features

• Central office quality DTMF transmitter/
receiver

• Low power c onsu mpt ion

• High speed ada ptiv e micr o interf ace

• Adjustable guard time

• Automat ic ton e burst mode

• Call prog ress ton e det ection t o -30dBm

Applications

• Credit card systems

• Paging systems

• Repeater systems/mobile radio

• Interconn ect di alers

• Persona l comp uters

Description

The MT8889C is a monolithic DTMF transceiver with
call progress filter. It is fabricated in CMOS
technology offering low power consumption and high
reliability.

ISSUE 2 May 1995

Ordering Information

MT8889CE/CE- 1 20 Pin Plast ic D IP
MT8889CC/CC-1 20 Pin Ceramic DIP
MT8889CS/CS- 1 20 Pin SOI C
MT8889CN/C N-1 24 Pin SSOP

-40°C to +85°C

The receiver section is based upon the industry
standard MT8870 DTMF receiver while the
transmitter utilizes a switched capacitor D/A
converter for low distortion, high accuracy DTMF
signalling. Internal counters provide a burst mode
such that tone bursts can be transmitted with precise
timing. A call progress filter can be selected allowing
a microprocessor to analyze call progress tones.

The MT8889C utilizes an adaptive micro interface,
which allows the device to be connected to a number
of popular microcontrollers with minimal external
logic. The MT8889C-1 is functionally identical to the
MT8889C except the receiver is enhanced to accept
lower level signals, and also has a specified low
signal rejection level.

TONE

IN+

IN­GS

OSC1
OSC2

∑

Tone Burst
Gating Cct.

+

-

V

DDVRefVSS

Tone
Filter

Oscillator

Circuit

Bias

Circuit

Dial

D/A

Converters

Control

Logic

High Group

Filter

Low Group

Filter

Control

Logic

Row and

Column

Counters

Digital

Algorithm
and Code
Converter

Steerin g

Logic

ESt St/GT

Transmit Data

Register

Status

Register

Control

Register

A

Control

Register

B

Receive Data

Register

Figure 1 - Functional Block Diagram

Data

Bus

Buffer

Interrupt

Logic

I/O

Control

D0
D1
D2
D3

IRQ

/CP

DS/RD
CS
R/W/WR
RS0

4-107

MT8889C/MT8889C-1

1

IN+

2

IN-

3

GS

CS

4
5

6
7
8
9

10

VRef

VSS
OSC1
OSC2

TONE

/WR

R/W

20 PIN CERDIP/PLASTIC DIP/SOIC

20
19
18
17
16
15
14
13
12
11

VDD
St/GT
ESt
D3
D2
D1
D0
IRQ
DS/RD
RS0

/CP

R/W

IN+

IN-

GS

VRef

VSS
OSC1
OSC2

NC
NC

TONE

/WR

CS

1
2

3
4

5
6

7
8

9
10
11
12

24 PIN SSOP

24
23
22
21
20
19
18
17
16
15
14
13

VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC

/CP

IRQ
DS/RD
RS0

Figure 2 - Pin Connections

Pin Description

Pin #

20 24

11 IN+Non-inverting op-am p input.
22 IN- In vertin g op-am p input.
33 GSGain Select. Gives access to output of front end differential amplifier for co nnecti on of

44 V
55 V
66OSC1Oscillator input. This pin can also be driven directl y by an external clock.

Name Description

feedback resistor.
Reference Vo ltage output (VDD/2).

Ref

Ground (0V).

SS

77OSC2Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes

the internal oscillator circuit. Leave open circuit when OS C1 is driven externally.
8 10 TONE Output from internal DTMF transmitter.
911 R/W

)

(WR

10 12 CS

Chip Select input. This signal must be quali fie d externally by either address strobe (AS),

or (Intel) Write microprocessor input. TTL compatible.

(Motorola) Read/Write

valid memory address (VMA) or address latch enable (ALE) signal, see Figure 12.

11 13 RS0 Register Selec t input. Refer to Table 3 for bit interpretation. TTL compatible.
12 14 DS (RD

) (Motorola) Data Strobe or (Intel) Read microprocessor input. Act ivity on this input is only

required when the device is being accessed. TTL compatible.

13 15 IRQ

/CP Interrupt Request/Call Progress (ope n drain) outpu t. In interrupt mode, this output goes

low when a valid DTMF tone burst has been transmitted or received. In call progress mode,

this pin will output a rectangular signal representative of the input signal applied at the input

op-amp. The input signal must be within the bandwidth lim it s of the call progress filte r, see

Figure 8.

14-1718-21D0-D3 Microprocessor data bus. High impedance when CS

= 1 or DS =0 (Motorola) or RD = 1

(Intel). TTL compatible.

18 22 ESt Early Steering output. Present s a logic high once the digital algo rithm has detected a valid

tone pair (signal condition). Any moment ary loss of signal con dition will cause ESt to return

to a logic low.

19 23 St/GT Steering Input/Guard Time output (bidirect ional ). A voltage great er than V

detected at

TSt

St causes the device to register the detected tone pair and updat e the output latch. A

voltage less than V

frees the device to accept a new tone pair. The GT output acts to

TSt

reset the external steering time-const ant; its stat e is a function of ESt and the volt age on St.

20 24 V

8,9
16,

17

4-108

Positive power supply (5V typ.).

DD

NC No Connection.

Functional Description

MT8889C/MT8889C-1

The MT8889C/MT8889C-1 Integrated DTMF
Transceiver consists of a high performance DTMF
receiver with an internal gain setting amplifier and a
DTMF generator, which employs a burst counter to
synthesize precise tone bursts and pauses. A call
progress mode can be selected so that frequencies
within the specified passband can be detected. The
adaptive micro interface allows microcontrollers,
such as the 68HC11, 80C51 and TMS370C50, to
access the MT8889C/MT8889C-1 internal registers.

Input Configuration

The input arrangement of the MT8889C/MT8889C-1
provides a differential-input operational amplifier as
well as a bias source (V
inputs at V

/2. Provision is made for connection of

DD

a feedback resistor to the op-amp output (GS) for
gain adjustment. In a single-ended configuration, the
input pins are connected as shown in Figure 3.

Figure 4 shows the necessary connections for a
differential input configuration.

), which is used to bias the

Ref

C1

C2

DIFFERENTIAL INPUT AMPLIFIER

C1 = C2 = 10 nF
R1 = R4 = R5 = 100 kΩ
R2 = 60kΩ, R3 = 37.5 kΩ
R3 = (R2R5)/(R2 + R5)

VOLTAGE GAIN

diff) - R5/R1

(A

V

INPUT IMPEDANCE

(Z

diff) = 2 R12 + (1/ωC)

IN

R1

R4

R3

R5

R2

2

IN+

IN-

GS

V

Ref

MT8889C/
MT8889C-1

Receiver Se ction

Separation of the low and high group tones is
achieved by applying the DTMF signal to the inputs
of two sixth-order switched capacitor bandpass
filters, the bandwidths of which correspond to the low
and high group frequencies (see Table 1). The filters
also incorporate notches at 350 Hz and 440 Hz for
exceptional dial tone rejection. Each filter output is
followed by a single order switched capacitor filter
section, which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators
which are provided with hysteresis to prevent
detection of unwanted low-level signals. The outputs
of the comparators provide full rail logic swings at
the frequencies of the incoming DTMF signals.

IN+

C

VOLTAGE GAIN

(A

) = RF / R

V

R

IN

R

F

IN

Figure 3 - Single-Ended Input Configuration

IN-

GS

V

Ref

MT8889C/
MT8889C-1

Figure 4 - Differential Input Configuration

F

LOW

F

HIGH

DIGIT D

D

3

D

2

1

697 1209 1 0 0 0 1
697 1336 2 0 0 1 0
697 1477 3 0 0 1 1
770 1209 4 0 1 0 0
770 1336 5 0 1 0 1
770 1477 6 0 1 1 0
852 1209 7 0 1 1 1
852 1336 8 1 0 0 0
852 1477 9 1 0 0 1
941 1336 0 1 0 1 0
941 1209 * 1 0 1 1
941 1477 # 1 1 0 0
697 1633 A 1 1 0 1
770 1633 B 1 1 1 0
852 1633 C 1 1 1 1
941 1633 D 0 0 0 0

0= LOGIC LOW, 1= LOGIC HIGH

Table 1. Functional Encode/Decode Table

D

0

4-109

MT8889C/MT8889C-1

Following the filter section is a decoder employing
digital counting techniques to determine the
frequencies of the incoming tones and to verify that
they correspond to standard DTMF frequencies. A
complex averaging algorithm protects against tone
simulation by extraneous signals such as voice while
providing tolerance to small frequency deviations
and variations. This averaging algorithm has been
developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of
interfering frequencies (third tones) and noise. When
the detector recognizes the presence of two valid
tones (this is referred to as the “signal condition” in
some industry specifications) the “Early Steering”
(ESt) output will go to an active state. Any
subsequent loss of signal condition will cause ESt to
assume an inactive state.

V

DD

MT8889C/
MT8889C-1

V

DD

St/GT

ESt

R1

t

= (R1C1) In (VDD / V

GTA

t

= (R1C1) In [VDD / (VDD-V

GTP

Figure 5 - Basic Steering Circuit

Guard Time Adjustment

Vc

C1

TSt

)

)]

TSt

Steering Circuit

Before registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred
to as character recognition condition). This check is
performed by an external RC time constant driven by
ESt. A logic high on ESt causes v
rise as the capacitor discharges. Provided that the
signal condition is maintained (ESt remains high) for
the validation period (t
(V

) of the steering logic to register the tone pair,

TSt

), vc reaches the threshold

GTP

latching its corresponding 4-bit code (see Table 1)
into the Receive D ata Regist er. At thi s point the GT
output is activated and drives v
continues to drive high as long as ESt remains high.
Finally, after a short de lay to a ll ow th e o ut put latch to
settle, the delayed steering output flag goes high,
signalling that a received tone pair has been
registered. The status of the delayed steering flag
can be monitored by checking the appropriate bit in
the status register. If Interrupt mode has been
selected, the IRQ

/CP pin will pull low when the

delayed steering f l ag is activ e.

The contents of the output latch are updated on an
active delayed steering transition. This data is
presented to the four bit bidirectional data bus when
the Receive Data Register is read. The steering
circuit works in reverse to validate the interdigit
pause between signals. Thus, as well as rejecting
signals too short to be considered valid, the receiver
will tolerate signal interruptions (drop out) too short
to be considered a valid pause. This facility, together
with the capability of selecting the steering time
constants externally, allows the designer to tailor
performance to meet a wide variety of system
requirements.

(see Figure 5) to

c

to VDD. GT

c

The simple steering circuit shown in Figure 5 is
adequate for most applications. Component values
are chosen according to the following inequalities
(see Figure 7):

≥ t

t

REC

t

≤ t

REC

tID ≥ t

tDO ≤ t

DAmax

DPmax

DPmin

DAmin

+ t
+ t
+ t
+ t

GTPmax

GTPmin

GTAmax

GTAmin

- t

- t

- t

- t

DAmin

DAmax

DPmin

DPmax

The value of tDP is a device parameter (see AC
Electrical Characteristics) and t

is the minimum

REC

signal duration to be recognized by the receiver. A
value for C1 of 0.1 µF is recommended for most

V

DD

St/GT

ESt

V

DD

St/GT

ESt

R1

R1

= (RPC1) In [VDD / (VDD-V

t

GTP

= (R1C1) In (VDD/V

t

GTA

= (R1R2) / (R1 + R2)

R

P

C1

R2

a) d ecrea sing tGTP; (tGTP < tGTA)

t

= (R1C1) In [VDD / (VDD-V

GTP

t

= (RpC1) In (VDD/V

GTA

R

= (R1R2) / (R1 + R2)

P

C1

R2

b) decreasing tGTA; (tGTP > tGTA)

TSt

TSt

TSt

TSt

)]

)

)]

)

Figure 6 - Guard Time Adjustment

4-110

MT8889C/MT8889C-1

AAAA

AAAA

A

A

A

AAAA

AAAA

A

A

AA

applications, leaving R1 to be selected by the
designer. Different steering arrangements may be
used to select independent tone present (t
tone absent (t

) guard times. This may be

GTA

GTP

) and

necessary to meet system specifications which place
both accept and reject limits on tone duration and
interdigital pause. Guard time adjustment also allows
the designer to tailor system parameters such as talk
off and noise immunity.

Increasing t

improves talk-off performance since

REC

it reduces the probability that tones simulated by
speech will maintain a valid signal condition long
enough to be registered. Alternatively, a relatively
short t

with a long tDO would be appropriate for

REC

extremely noisy environments where fast acquisition
time and immunity to tone drop-outs are required.
Design information for guard time adjustment is
shown in Figure 6. The receiver timing is shown in
Figure 7 with a description of the events in Figure 9.

Call Progress Filter

A call progress mode, using the MT8889C/
MT8889C-1, can be selected allowing the detection
of various tones, which identify the progress of a
telephone call on the network. The call progress
tone input and DTMF input are common, however,
call progress tones can only be detected when CP

mode has been selected. DTMF signals cannot be
detected if CP mode has been selected (see Table

7). Figure 8 indicates the useful detect bandwidth of
the call progress filter. Frequencies presented to the
input, which are within the ‘accept’ bandwidth limits
of the filter, are hard-limited by a high gain
comparator with the IRQ

/CP pin serving as the
output. The squarewave output obtained from the
schmitt trigger can be analyzed by a microprocessor
or counter arrangement to determine the nature of
the call progress tone being detected. Frequencies
which are in the ‘reject’ area will not be detected and
consequently the IRQ

LEVEL

(dBm)

-25

0 250 500 750

= Reject
= May Accept

AAA

AAAA

A

AAAA

AAAA

= Accept

A

A

AAA

AAA

/CP pin will remain low.

AAAA

AAAA

AAAA

AAAA

AAAA

AAA

AAA

AAA

AAA

AAAA

AAAA

AAAA

FREQUENCY (Hz)

Figure 8 - Call Progress Response

EVENTS

V

in

ESt

St/GT

RX

-RX

0

b3

b2

Read
Status
Register

/CP

IRQ

ABCDEF

t

t

REC

REC

TONE #n

t

DP

t

GTP

3

DECODED TONE # (n-1)

t

PStRX

t

PStb3

t

ID

# n

t

DO

TONE
#n + 1

t

DA

t

GTA

TONE
#n + 1

V

TSt

# (n + 1)

Figure 7 - R ece iver Tim ing Diag ram

4-111

MT8889C/MT8889C-1

EXPLANATION OF EVENTS

A) TONE BURSTS DETECTED, TONE DURATION INVALID, RX DATA REGISTER NOT UPDATED.
B) TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.
C) END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER

D) TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.
E) ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, DATA REMAINS UNCHANGED.
F) END OF TONE #n+1 DE TECTED, TONE A BSENT DURATION VALID, INFORMATION IN RX DATA REGISTER

EXPLANATION OF SYMBOLS

V

in

ESt EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES.
St/GT STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT.
RX

0

b3 DEL AYED STEERING. INDICATES THAT VALID FREQUENCIES H AVE BEEN PRESENT/ABSENT FOR THE

b2 INDICATES THAT VALID DATA IS IN THE RECEIVE DATA RE GISTER. THE BIT IS CLEARED A FTER THE STATUS

IRQ

t

REC

t

REC

t

ID

t

DO

t

DP

t

DA

t

GTP

t

GTA

RETAINED UNTIL NEXT VALID TONE PAIR.

RETAINED UNTIL NEXT VALID TONE PAIR.

DTMF COMPOSITE INPUT SIG NAL.

-RX34-BIT DECODED DATA IN RE CEIVE DATA REGISTER

REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. ACTIVE LOW FOR THE DURATION OF A
VALID DTMF SIGNAL.

REGISTER IS READ.

/CP INTERRUPT IS ACTIVE INDICATING THAT NEW DATA IS IN THE RX DATA REGISTER. THE INTERRUPT IS

CLEARED AFTER THE STATUS REGISTER IS R EAD.

MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID.
MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION.
MINIMUM TIME BET WEEN VALID SEQUENTI AL D TMF SIG NAL S.
MAXIMUM ALLOWABLE DROPOUT DURING VALID DTMF SIGNAL.
TIME TO DETECT VALID FREQUENCIES PRESENT.
TIME TO DETECT VALID FREQUENCIES ABSENT.
GUARD TIME, TO NE PR ESEN T.
GUARD TIME, TO NE ABSEN T.

Figur e 9 - De scri pt ion of Tim in g Ev en ts

DTMF Generator

The DTMF transmitter employed in the MT8889C/
MT8889C-1 is capable of generating all sixteen
standard DTMF tone pairs with low distortion and
high accuracy. All frequencies are derived from an
external 3.579545 MHz crystal. The sinusoidal
waveforms for the individual tones are digitally
synthesized using row and column programmable
dividers and switched capacitor D/A converters. The
row and column tones are mixed and filtered
providing a DTMF signal with low total harmonic
distortion and high accuracy. To specify a DTMF
signal, data conforming to the encoding format
shown in Table 1 must be written to the transmit Data
Register. Note that this is the same as the receiver
output code. The individual tones which are
generated (f
Group and High Group tones. As seen from the
table, the low group frequencies are 697, 770, 852
and 941 Hz. The high group frequencies are 1209,
1336, 1477 and 1633 Hz. Typically, the high group to
low group amplitude ratio (twist) is 2 dB to com­pensate for high group attenuation on long loops.

The period of each tone consists of 32 equal time
segments. The period of a tone is controlled by
varying the length of these time segments. During

LOW

and f

) are referred to as Low

HIGH

write operations to the Transmit Data Register the 4
bit data on the bus is latched and converted to 2 of 8
coding for use by the programmable divider circuitry.
This code is used to specify a time segment length,
which will ultimately determine the frequency of the
tone. When the divider reaches the appropriate
count, as determined by the input code, a reset pulse
is issued and the counter starts again. The number
of time segments is fixed at 32, however, by varying
the segment length as described above the
frequency can also be varied. The divider output
clocks another counter, which addresses the
sinewave lookup ROM.

The lookup table contains codes which are used by
the switched capacitor D/A converter to obtain
discrete and highly accurate DC voltage levels. Two
identical circuits are employed to produce row and
column tones, which are then mixed using a low
noise summing amplifier. The oscillator described
needs no “start-up” time as in other DTMF
generators since the crystal oscillator is running
continuously thus providing a high degree of tone
burst accuracy. A bandwidth limiting filter is
incorporated and serves to attenuate distortion
products above 8 kHz. It can be seen from Figure 6
that the distortion products are very low in amplitude.

4-112

Scaling Information

10 dB/Div
Start Frequency = 0 Hz
Stop Frequency = 3400 Hz
Marker Frequency = 697 Hz and
1209 Hz

Figure 10 - Spectrum Plot

MT8889C/MT8889C-1

Burst Mode

In certain telephony applications it is required that
DTMF signals being generated are of a specific
duration determined either by the particular
application or by any one of the exchange transmitter
specifications currently existing. Standard DTMF
signal timing can be accomplished by making use of
the Burst M o de. T h e tr an s m itte r is capable o f i ssui n g
symmetric bursts/pauses of predetermined duration.
This bu rst/pau se durat ion is 51 ms±1 m s which i s a
standard interval for autodialer and central office
applications. After the burst/pause has been issued,
the appropriate bit is set in the Status Register
indicating that the transmitter is ready for more data.
The timing described above is available when DTMF
mode has been selected. However, when CP mode
(Call Progress mode) is selected, the burst/pause
duration i s do ub le d to 1 0 2 ms ± 2 ms . No te th a t wh e n
CP mode and Burst mode have been selected,
DTMF tones may be transmitted only and

not

received. In applications where a non-standard
burst/pause time is desirable, a software timing loop
or external timer can be used to provide the timing
pulses when the burst mode is disabled by enabling
and disabling the transmitter.

Single Tone Generation

ACTIVE

INPUT

L1
L2
L3

L4
H1
H2
H3
H4

OUTPUT FREQUENCY (Hz)

SPECIFIED ACTUAL

697 699.1 +0.30
770 766.2 -0.49
852 847.4 -0.54

941 948.0 +0.74
1209 1215.9 +0.57
1336 1331.7 -0.32
1477 1471.9 -0.35
1633 1645.0 +0.73

%ERROR

Table 2. Actual Frequencies Versus Standard

Requirements

Distortion Calculations

The MT8889C/MT8889C-1 is capable of producing
precise tone bursts with minimal error in frequency
(see Table 2). The internal summing amplifier is
followed by a first-order lowpass switched capacitor
filter to minimize harmonic components and
intermodulation products. The total harmonic
distortion for a
Equation 1, which is the ratio of the total power of all
the extraneous frequencies to the power of the
fundamental frequency expressed as a percentage.

single tone

can be calculated using

A single tone mode is available whereby individual
tones from the low group or high group can be
generated. This mode can be used for DTMF test
equipment applications, acknowledgment tone
generation and distortion measurements. Refer to
Control Register B description for details.

2

2

+ V

3f

V

fundamental

2

THD (%) = 100

V

+ V

2f

Equation 1. THD (%) For a Single Tone

+ .... V

4f

2

nf

4-113

MT8889C/MT8889C-1

The Fourier components of the tone output
correspond to V
waveform. The total harmonic distortion for a

tone

can be calculated using Equation 2. V
correspond to the low group amplitude and high
group amplitude, respectively and V

.... Vnf as measured on the output

2f

and V

L

2

is the sum

IMD

dual

of all the intermodulation components. The internal
switched-capacitor filter following the D/A converter
keeps distortion products down to a very low level as
shown in Figure 10.

2

THD (%) = 100

2L

+ V

V

2

3H

2

3L

+ .. V

V

V

+ .... V

2

2

+ V

L

nH

2

2

+ V

H

2

+ V

nL

+

2H

2

IMD

Equation 2. THD (% ) For a Dual Tone

DTMF Clo ck Ci rcuit

The internal clock circuit is completed with the
addition of a standard television colour burst
crystal. The crystal specification is as follows:

Frequency: 3.579545 MHz
Frequency Tolerance:
Resonance Mode: Parallel
Load Capacitance: 18pF
Maximum Series Resistance:150 ohms
Maximum Drive Level: 2mW

e.g. CTS Knig hts MP0 36 S

Toyocom TQC-203-A-9S

A number of MT8889C/MT8889C-1 devices can be
connected as shown in Figure 11 such that only one
crystal is required. Alternatively, the OSC1 inputs on
all devices can be driven from a TTL buffer with the
OSC2 outputs left unconnected.

MT8889C/

MT88 89C-1 MT88 89C-1 M T888 9C-1

OSC1 OSC2

3.579 545 MH z

OSC1 OSC2

Figure 11 - Common Crystal Connection

±0.1%

MT8889C/

MT8889C/

OSC1 OSC2

various kinds of microprocessors. Key functions of
this interface include the following:

H

• Continuous activity on DS/RD

is not necessary

to update the internal status registers.

• sens es w he th er in put ti mi ng is t ha t of an I nte l o r
Motorola controller by monitoring the DS (RD

(WR) and CS inputs.

R/W

• generate s equ ivale nt CS

signal for internal

operatio n for all proc ess ors.

• differentia tes be twee n mul tiplex ed a nd non­multiplexed microprocessor buse s. Address
and data ar e lat ched in accord ingly.

• compatible with Motorola and Intel processors.

Figure 17 shows the timing diagram for Motorola
microprocessors with separate address and data
buses. Members of this microprocessor family
include 2 MHz versions of the MC6800, MC6802 and
MC6809. For the MC6809, the chip select (CS
signal is formed by NANDing the (E+Q) clocks and
address decode output. For the MC6800 and
MC6802, CS

is formed by NANDing VMA and
address decode output. On the falling edge of CS
the internal logic senses the state of data strobe
(DS). When DS is low, Motorola proc essor o peration
is selected.

Figure 18 shows the timing diagram for the Motorola
MC68HC11 (1 MHz) microcontroller. The chip select

) input is formed by NANDing address strobe

(CS
(AS

) and address decode output. Again, the
MT8889C/MT8889C-1 examines the state of DS on
the falling edge of CS

to determine if th e mi c ro h a s a
Motorola bus (when DS is low). Additionally, the
Texas Instruments TMS370CX5X is qualified to have
a Motorola interface. Figure 12(a) summarizes
connection of these Motorola processors to the
MT8889C/MT8889C-1 DTMF transceiver.

Figures 19 and 20 are the timing diagrams for the
Intel 8031/8051 (12 MHz) and 8085 (5 MHz) micro­controllers with multiplexed address and data buses.
The MT8889C/MT8889C-1 latches in the state of RD
on the falling edge of CS. When RD is high, Intel
processor operation is selected. By NANDing the
address latch enable (ALE) output with the high-byte
address (P2) decode output, CS

can be generated.
Figure 12(b) summarizes the connection of these
Intel processors to the MT8889C/MT8889C-1
transceiver.

),

) inpu t

,

Microprocessor Int er face

The MT8889C/MT8889C-1 design incorporates an
adaptive interface, which allows it to be connected to

4-114

NOTE: The adaptive micro interface relies on high­to-low transition on CS
microcontroller interface and this pin must not

to recognize the

be tied

permanently low.

The adaptive mic ro interface prov ides access to five
internal registers. The read-only Receive Data
Register contains the decoded output of the last
valid DTMF digit received. Data entered into the
write-only Transmit Data Register will determine
which tone pair is to be generated (see Table 1 for
coding details). Transceiver control is accomplished
with two control registers (see Tables 6 and 7), CRA
and CRB, which have the same address. A write
operation to CRB is executed by first setting the
most significant bit (b3) in CRA. The following write
operation to the same address will then be directed
to CRB, and subsequent write cycles will be directed
back to CRA. The read-only status register indicates
the curre n t t ra n sce iver state (see Table 8).

MT8889C/MT8889C-1

Motorola Intel

RS0 R/W

0001

0110

1001
1110

Table 3. Inte rnal Re gis ter Fu nctio ns

WR RD FUNCTION

Write to Transmit
Data Register

Read from Receive
Data Register

Write to Control Register

Read from Status Register

A software reset must be included at the beginning
of all programs to initialize the control registers upon
power-up or power reset (see Figure 15). Refer to
Tables 4-7 for bit descriptions of the two control
registers.

The multiplexed IRQ

/CP pin can be programmed to
generate an interrupt upon validation of DTMF
signals or when the transmitter is ready for more
data (burst mode only). Alternatively, this pin can be
configured to provide a square-wave output of the
call progress signal. The IRQ

/CP pin is an open drain
output and requires an external pull-up resistor (see
Figure 13).

MC6800/6802

A0-A15

VMA

D0-D3

RW

Φ2

(a)

MT8889/MT8889C-1 MT8889C/MT8889C-1

CS
RS0

D0-D3
R/W

/WR

DS/RD

b3 b2 b1 b0

RSEL IRQ CP/DTMF

Table 4. CRA Bit Position s

b3 b2 b1 b0

C/R

S/D TEST BURST

Table 5. CRB Bit Position s

MC68HC11

A8-A15

AS

AD0-AD3

DS

RW

CS

D0-D3
RS0

DS/RD
R/W

/WR

TOUT

ENABLE

MC6809

A0-A15

D0-D3

R/W

MT8889/MT8889C-1

CS

Q

E

RS0

D0-D3
R/W/WR

DS/RD

8031/8051
8080/8085

A8-A15

ALE

RD

WR

P0

MT8889C/MT8889C-1

CS

D0-D3
RS0

DS/RD
R/W/WR

(b)

Figure 12 a) & b) - MT8889 Interface Connections for Various Intel and Motorola Micros

4-115

MT8889C/MT8889C-1

BIT NAME DESCRIPTION

b0 TOUT Tone Output Control. A logic high enables the tone output; a logic low turns the tone output

off. This bit controls all transmit tone functions.

b1 CP/DTMF

b2 IRQ Int errupt Enable. A logic high enables the interrupt function; a logic low de-activate s the

b3 RSEL Register Select. A logic high selects control register B for the next write cycle to the

BIT NAME DESCRIP TI ON

b0 BURST

Call Progress or DTMF Mode Select. A logic high enables the receive call progress mode;

a logic low enables DTMF mode. In DTMF mode the device is capable of receiving and
transmitting DTMF signals. In CP m ode a re tang ular wave representatio n of the re ceived
tone signal will be present on the IRQ
register A, b2=1). In order to be detected, CP signals must be within the bandwidth
specified in the AC Electrical Characteristi cs for Call Progress.
Note: DTMF signals cannot be detected when CP mode is selected .

interrupt function. When IRQ is en abled and DTM F mode is selected (cont rol registe r A,
b1=0), the IRQ
received for a valid guard time duration, or 2) the transm itter is ready for more data (burst
mode only).

control register address. Afte r writing to control regist er B, the following cont rol register
write cycle will be directed to control register A.

Burst Mode Sel ect. A logic hig h de-act ivat es burst mod e; a logi c low e nables b ur st mode.
When activated, t he digital code representing a DTMF sig nal (see Table 1) can be written
to the transmit register, which will result in a transmit DTMF tone burst and pause of equal
durations (typically 51 msec). Following the pause, the status register will be updated (b1 ­Transmit Data Register Empty), and an inte rrupt will occur if the interrupt mode has been
enabled.

/CP output pin will go low when either 1) a va lid DTMF signal has been

Table 6. Control Register A Description

/CP output pin if IRQ has been enabled (control

When CP mode (control register A, b1) is enabled the normal tone burst and pause
durations are extended from a typical duratio n of 51 msec to 102 msec.

When BURST is high (de-activated) the transmit tone burst duration is determined by the
TOUT bit (control register A, b0).

b1 TEST Test Mode Control. A logic high enables the test mode; a logic low de-activates the test

mode. When TEST is ena bled and DT M F mode is selected (con trol regist er A, b1=0), th e

b2 S/D

b3 C/R

signal present on the IRQ
STEERING bit of the status register (see Figure 7, signal b3).

Single or Dual Tone Generation. A logic high selects the single tone output; a logic low
selects the dual tone (DTM F) outpu t. The single tone generat ion function requ ires furthe r
selection of either t he row or colum n tones (l ow or hi gh group ) throu gh the C /R
register B, b3).

Column or Row Tone Select. A logic high selects a column tone output; a logic low selects
a row tone outp ut. Th is f unction is used in conjunctio n wi th th e S/ D
b2).

Ta ble 7

/CP pin will be analogous to the state of the DELAYED

bit (control

bit (control regi ster B,

. Control Register B Description

4-116

MT8889C/MT8889C-1

BIT NAME STATUS FL AG S E T STATUS FLAG CLEARE D

b0 IRQ Interrupt has occurred. Bit one

(b1) or bit two (b2) is set.

b1 TRANSM I T DATA

REGISTER EMPTY
(BURST MODE ONLY)

b2 RECEIVE DATA REGISTER

FULL

b3 DELAYED

STEERING Set upon the valid detect ion of

Pause duration has terminat ed
and transmitter is ready for new
data.

Valid data is in the Receive Data
Register.

the absence of a DTMF signal.

Table 8. Status Register Description

MT8889C/ MT8 889C-1

VDD

St/GT

ESt

IRQ

/CP

DS/RD

RS0

D3
D2
D1
D0

DTMF/CP
INPUT

DTMF
OUTPUT

C1

R1

R2

X-tal

R

IN+
IN­GS
VRef
VSS
OSC1
OSC2
TONE
R/W

L

/WR

CS

Interrupt is inactive. Cleared after
Status Register is read.

Cleared after Status Register is
read or when in non-burst mode.

Cleared after Status Register is
read.

Cleared upon the detection of a
valid DTMF signal.

V

DD

C3

C2

R4

R3

To µP
or µC

Notes:
R1, R2 = 100 kΩ 1%
R3 = 374 Ω 1%
R4 = 3.3 kΩ 10%
RL = 10 k Ω (min.)
C1 = 100 nF 5%
C2 = 100 nF 5%
C3 = 100 nF 10%*
X-tal = 3.579545 MHz

* Micro pro ces sor based syste ms can inject undesi rable noise into the supply rails.
The performance of the MT8889C/MT8889C-1 can be optimized by keeping
noise on the supply rails to a minimum. The decoupling capacitor (C3) should be
connected close to the device and ground loops should be avoided.

Figure 13 - Application Circuit (Single-Ended Input)

4-117

MT8889C/MT8889C-1

TEST POINT

130 pF

MMD6150 (or
equivalent)

24 kΩ

5.0 VDC

2.4 kΩ

MMD7000 (or
equivalent)

TEST POINT

Test load for IRQ

/CP pinTest load for D0-D3 pins

5.0 VDC

3 kΩ

100 pF

Figure 14 - Test Circuits

INITIALIZATION PROCEDURE

A software reset must be included at the beginning of all programs to initialize the control registers after
power up. The initialization procedure should be implemented 100ms after power up.

Description: Motorola

RS0 R/W

Intel Data

WR RD b3 b2 b1 b0

1) Read Status Register 1 1 1 0 X X X X

2) Write to Control Register 1 0 0 1 0 0 0 0

3) Write to Control Register 1 0 0 1 0 0 0 0

4) Write to Control Register 1 0 0 1 1 0 0 0

5) Write to Control Register 1 0 0 1 0 0 0 0

6) Read Status Register 1 1 1 0 X X X X

TYPICAL CONTROL SE QUE NCE FOR BURST MODE APPLIC ATIONS

Transmit DTMF tones of 50 ms burst/50 ms pause and Receive DTMF Tones.

Sequence:

RS0 R/W

WR RD b3 b2 b1 b0

1) Write to Control Register A 1 0 0 1 1 1 0 1
(tone out, DTMF, IRQ

, Select C ontrol Register B)

2) Write to Control Register B 1 0 0 1 0 0 0 0
(burst mode)

3) Write to Transmit Data Register 0 0 0 1 0 1 1 1
(send a digit 7)

4) Wait for an Interrupt or Poll Status Register

5) Read the Status Register 1 1 1 0 X X X X

-if bit 1 is set, the Tx is ready for the next tone, in which case ...
Write to Transmit Register 0 0 0 1 0 1 0 1
(send a digit 5)

-if bit 2 i s se t, a D T MF tone ha s be e n r ec e iv e d, in which case ....

Read the Receive Data Register 0 1 1 0 X X X X

-if both bits are set ...
Read the Receive Data Register 0 1 1 0 X X X X
Write to Transmit D a ta R e gister 0 0 0 1 0 1 0 1

NOTE: IN THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SET UNTIL 100 ms ( ±2 ms) AFTER THE DATA IS
WRITTEN TO THE TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO 200 ms (± 4 ms)

Figure 15 - Application Notes

4-118

Absolute Maximum Ratings*

Parameter Symbol Min Max Units

MT8889C/MT8889C-1

1 Power supply voltage V

DD-VSS

2 Voltage on any pin V
3 Current at any pin (Except V

DD and VSS

)10mA
4 Storage temperature T
5 Package power dissipation P

* Excee di ng these values ma y cause perm anen t damage . Function al ope rati on under the se conditi ons is not impl ied.

Recommended Operating Conditions - Voltages are with respect to ground (V

Parameter Sym Min Typ

1 Positive power supply V
2 Operating temperature T
3 Crystal clock frequency f

‡ Typical figures are at 25 °C and for design aid only: not guarante ed and not subject to prod ucti on testin g.

DC Electrical Characteristics

DD

O

CLK

†

- VSS=0 V.

4.75 5.00 5.25 V

-40 +85 °C

3.575965 3.579545 3.583124 MHz

V

DD

I

ST

D

‡

Max Units Test Conditions

VSS-0.3 VDD+0.3 V

-65 +150 °C

) unless otherwise stated.

SS

Characteristics Sym Min Typ‡Max Units Test Conditions

1
2 Operating supply current I
3 Power consumption P
4

5 Low level input voltage

6 Steering threshold voltage V
7

8 High level out put voltage

9 Output leaka ge current

10 V
11 V
12
13 High level inpu t volta ge V
14 Input leakage current I

15
16 Sink current I
17
18 Sink current I

19

† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25 °C, V
* Se e “Not es” following AC Electrical Chara cteri st ics Tables.

Operating supply volta ge V

S
U
P

High level input voltage

I

(OSC1)

N
P
U

(OSC1)

T
S

Low level output volt age
(OSC2) V

O
U
T

(OSC2) V

P
U

(IRQ) I

T
S

D

i

g

i
t

a

l

Data

Bus
ESt

and

St/GT

IRQ/

CP

output voltage V

Ref

output resistan ce R

Ref

Low level input voltage V

Source current I

Source current I

Sink current I

=5V and for design aid only: not guarantee d and not subje ct to produ ctio n testi ng.

DD

V

V

OLO

OHO

DD

DD

C

IHO

ILO

TSt

OZ

Ref
OR

IL
IH

IZ

OH
OL
OH
OL

OL

4.75 5.0 5.25 V

7.0 11 mA

57.8 mW

3.5 V Note 9*

1.5 V Note 9*

2.2 2.3 2.5 V VDD=5V
No load

0.1 V

Note 9*
No load

4.9 V

Note 9*

110µAVOH=2.4 V

2.4 2.5 2.6 V No load, VDD=5V

1.3 kΩ

0.8 V

2.0 V

10 µAVIN=VSS to V

-1.4 -6.6 mA VOH=2.4V

2.0 4.0 mA VOL=0.4V

-0.5 -3.0 mA VOH=4.6V
24 mAV

OL

=0.4V

416 mAVOL=0.4V

6V

1000 mW

DD

4-119

MT8889C/MT8889C-1

Electrical Characteristics
Gain Setting Amplifier - Voltages are with respect to ground (V

Characteristics Sym Min Typ

) unless otherwise stated, VSS= 0V, VDD=5V, TO=25°C.

SS

‡

Max Units Test Conditions

1 Input leakage current I
2 Input resistance R
3 Input offset voltage V

IN

IN

OS

±100 nA VSS ≤ VIN ≤ V

10 M Ω

25 mV
4 Power supply reject ion PSRR 60 dB 1 kHz
5 Comm on mo de rejecti on CMRR 60 dB 0. 75 ≤ V
6 DC open loop voltage gain A

VOL

65 dB
7 Unity gain band widt h BW 1.5 MHz
8 O utput volt age swing V
9 All owable capacit ive load (GS) C

10 Allowable resistive load (GS) R

11 Common mode ran ge V

‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing.

O

L
L

CM

MT8889C-1 AC Electrical Characte rist ics† - Voltages are with respect to ground (V

4.5 V

100 pF

50 k Ω

3.0 V

pp

pp

RL ≥ 100 kΩ to V

No Load

) unless otherwise stated.

SS

Characteristics Sym Min Typ Max Units Notes*

1

2 Input Signal Level Reject -37 dBm 1,2,3,5,6

Valid input signal levels
(each tone of composite
signal)

R
X

-31 +1 dBm 1,2,3,5,6

21.8 8 69 mV

RMS

1,2,3,5 ,6

≤ 4.25V

IN

DD

SS

1,2,3,5,6

) unless otherwise stated.

† Characteristics are over recommended temperature and at V

MT8889C AC Electrical Characteristics

10.9 mV

=5V, using the test circuit shown in Figure 13.

DD

†

- Voltages are with respect to groun d (V

RMS

SS

Characteristics Sym Min Typ‡Max Units Notes*

Valid input signal levels

R

1

† Characteristics are over recommended operating conditions (unless otherwise stated)

(each tone of composite

X

signal)

AC Electrical Characteristics† - Voltages are with respect to ground (V

-29 +1 dBm 1,2,3,5,6

27.5 869 mV

using the test circuit shown in Figure 13.

) unless otherwise stated. fC=3. 5795 45 MHz

SS

RMS

1,2,3,5,6

Characteristics Sym Min Typ‡Max Units Notes*

1

Positive twist accept 8 dB 2 ,3,6,9
2 Negative twist accept 8 dB 2,3,6,9
3 Freq. deviation accept ±1.5%± 2Hz 2,3,5

R

4 Freq. deviation reject ±3.5% 2,3,5

X

5 Third tone tolerance -16 dB 2,3,4,5,9, 10
6 Noise tolerance -12 dB 2,3,4,5,7,9,10
7 Dial ton e tole ra n ce 22 dB 2,3,4, 5,8, 9

† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD = 5V, and for design aid only: not guaranteed and not subject to production testing.
* *Se e “Not es” foll owi ng AC Electrical Characterist ic s Tables.

4-120

MT8889C/MT8889C-1

AC Electrical Characteristics†- Call Progress - Voltages are with respect to ground (V

), unless otherwise stated .

SS

Characteristi cs Sym Min Typ‡Max Units Conditi on s

1 Accept Bandwidth f

A

310 500 Hz @ -25 dBm,

Note 9
2 Lower freq. (REJECT) f
3 Upper freq. (REJECT) f
4 Call progress tone detect level (total

LR
HR

-30 dBm

290 Hz @ -25 dBm
540 Hz @ -25 dBm

power)

† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, V

=5V, and for design aid only: not guaranteed and not subject to production testing

DD

AC Electrical Characteristics†- DTMF Reception - Typical DTMF tone accept and reject requi reme nts. Actual

values are user selectable as per Figures 5, 6 and 7.

Characteristics Sym Min Typ

1 Minimum ton e accept duration t
2 Maximum tone reject duration t
3 Minimum int erdigit pause durat ion t
4 Maximum tone drop-out duration t

† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, V

=5V, and for design aid only: not guaranteed and not subject to production testing

DD

REC
REC

ID

OD

‡

Max Units Conditions

40 ms
20 ms
40 ms
20 ms

AC Electrical Characteristics† - Voltages are with respect to ground (V

Characteristics Sym Min Typ

T

1
2 Tone absent detect time t
3 Delay St to b3 t
4 Delay St to RX

5
6 Tone pause duration t
7 Tone burst duration (extended) t
8 Tone pause duration (extended) t
9 High group output level V

10 Low group output level V

11 Pre-emphasis dB
12 Output distortion (Single Tone) THD -35 dB 25 kHz Bandwidth
13 R
14 Frequency deviation f
15 Output load resistan ce R
16
17 Clock input rise and fall time t
18 Clock input duty cycle DC
19 Capacitive load (OSC2) C

† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and for desig n aid only: not guarantee d and not subje ct to productio n testi ng .

Tone present detect time t

O

N
E

I

N

-RX

0

3

Tone burst duration t

T

O

N
E

O

U
T

Crystal/clock frequency f

X
T
A

L

DP
DA

PStb3

t

PStRX

BST

PS

BSTE

PSE

HOUT

LOUT

D

LT

C

CLRF

LO

P

CL

3 11 14 ms Note 11

0.5 4 8. 5 ms Note 11

50 52 ms DTMF mode

50 52 ms DTMF mode
100 104 m s Call Progress mode
100 104 m s Call Progress mode

-6.1 -2.1 dBm RL=10kΩ

-8.1 -4. 1 dBm RL=10kΩ

023dBR

10 50 kΩ

3.5759 3.5795 3 .583 1 MHz

110 ns Ext. clock

40 50 60 % Ext. clo ck

), unless otherwise stated.

SS

‡

Max Units Conditions

13 µs See Figure 7

8 µs See Figure 7

=10kΩ

L

=10kΩ

L

±0.7 ±1.5 % fC=3.579545 MHz

30 pF

4-121

MT8889C/MT8889C-1

AC Electrical Characteristics†- MPU Interface - Voltages are with respect to ground (V

Characteristics Sym Min Typ

1DS/RD
2DS/RD
3DS/RD
4DS/RD
5DS/RD
6R/W
7R/W
8 Address setup time (RS0) t

9 Address hold time (RS0) t
10 Data hold time (read) t
11 DS/RD
12 Data setup time (write) t
13 Data hold time (write) t
14 Chip select setup time t
15 Chip select hold time t
16 Input Capacitance (data bus) C
17 Output Capacitance (IRQ

† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, V

/WR clock frequency f
/WR cycle period t
/WR low pulse width
/WR high pulse width t

/WR rise and fall time tR,t
setup time t
hold time t

to valid data delay (read) t

/CP) C

=5V, and for design aid only: not guaranteed and not subject to production testing

DD

CYC
CYC

tCL

CH

RWS
RWH

AS

AH
DHR
DDR
DSW
DHW

CSS
CSH

IN

OUT

150 ns Figure 16

F

23 ns Figures 17 & 18
20 ns Figures 17 & 18

0 ns Figures 17 - 20
40 20 ns Figures 17 - 20
22 ns Figures 17 - 20

45 ns Figures 17 - 20
10 ns Figures 17 - 20
45 35 ns Figures 17 - 20
40 ns Figures 17 - 20

‡

Max Units Conditions

4.0 MHz Figure 16

250 ns Figure 16

100 ns Figure 16

20 ns Figure 16

100 ns Figures 17 - 20

5pF
5pF

), unless otherwise stated.

SS

NOTES: 1) dBm=decibels above or below a reference power of 1 mW into a 600 ohm load.

2) Digit seq uence co ns is ts o f all 16 D TM F tones.

3) Tone duration=40 ms. Tone pause=40 ms.

4) Nominal DTMF frequencies are used.

5) Both tones in the composite signal have an equal amplitude.

6) The tone pa ir is devi ated by ± 1 .5 %±2 Hz.

7) Bandwid th limited (3 k H z) Gauss i an no is e.

8) The precise dial tone frequencies are 350 and 440 Hz (±2 %).

9) Guarante ed b y de si gn an d ch a r ac te riz at ion . N ot s ub jec t to produ ction testi ng .

10) Referenced to the low es t a mp li tu de to ne in the DTMF si gn al .
11 ) For guard t im e c a lc ulation purpos es.

t

CYC

DS/RD/WR

t

R

t

CH

t

F

t

CL

4-122

Figure 16 - D S /RD/WR Clock Pulse

MT8889C/MT8889C-1

DS

Q clk*

A0-A15
(RS0)

R/W(read)

Read Data
(D3-D0)

(write)

R/W

Write data
(D3-D0)

CS

= (E + Q).Addr [MC6809]

= VMA.Addr [MC6800, MC6802]

CS

*microprocessor pin

t

RWS

t

RWH

16 bytes of Addr

t

DDR

➀

t

DSW

t

CSS

t

AH

t

AS

t

AS

t

CSS

➀

t

CSH

t

AH

➀

t

CSH

t

DHR

t

DHW

➀ t

is from d ata to D S fal li ng e dg e; t

DSW

DS

R/W

Read
AD3-AD0
(RS0, D0-D3)

Write
AD3-AD0
(RS0-D0-D3)

Addr *
non-mux

AS *

Figure 17 - MC6800/MC6802/MC6809 Timing Diagram

is from DS rising edge to CS rising edge

CSH

t

RWS

t

t

AS

Addr

Addr

t

AH

High Byte of Addr

DDR

t

CSH

t

DSW

t

DHR

Data

Data

t

DHW

t

RWH

CS = AS.Addr

* microprocessor pins

Figure 18 - M C68H C11 Bus Timing (w ith multip lexed addr ess an d data bus es)

t

CSS

4-123

MT8889C/MT8889C-1

ALE*

RD

t

t

AS

P0*
(RS0,
D0-D3)

A0-A7

AH

t

CSS

t

DDR

Data

t

DHR

P2 *
(Addr)

= ALE.Addr

CS

* microprocessor pins

ALE*

WR

P0*
(RS0,
D0-D3)

P2 *
(Addr)

A8-A15 Address

t

CSH

Figure 19 - 8 031 /8051/ 8085 Rea d Timing Dia gram

t

CSS

t

t

AS

A0-A7

t

AH

A8-A15 Address

DSW

Data

t

DHW

= ALE.Addr

CS

* microprocessor pins

4-124

t

CSH

Figure 20 - 80 31/8 051 /8085 Wri te Timin g D iagra m