Datasheet MT8889CS, MT8889CE Datasheet (MITEL)

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Features

• Central office quality DTMF transmitter/ receiver

• Low power c onsu mpt ion

• High speed ada ptiv e micr o interf ace

• Adjustable guard time

• Automat ic tone bu rst mo de

• Call prog ress ton e det ection t o -30dBm

Applications

• Credit card systems

• Paging systems

• Repeater systems/mobile radio

• Interconn ect di alers

• Persona l comp uters

Description

The MT8889C is a monolithic DTMF transceiver with call progress filter. It is fabricated in CMOS technology offering low power consumption and high reliability.

The receiver section is based upon the industry standard MT8870 DTMF receiver while the transmitter utilizes a switched capacitor D/A converter for low distortion, high accuracy DTMF signalling. Internal counters provide a burst mode such that tone bursts can be transmitted with precise timing. A call progress filter can be selected allowing a microprocessor to analyze call progress tones.

The MT8889C utilizes an adaptive micro interface, which allows the device to be connected to a number of popular microcontrollers with minimal external logic. The MT8889C-1 is functionally identical to the MT8889C except the receiver is enhanced to accept lower level signals, and also has a specified low signal rejection level.

Ordering Information

MT8889CE/CE- 1 20 Pin Plast ic D IP MT8889CC/CC-1 20 Pin Ceramic DIP MT8889CS/CS- 1 20 Pin SOI C MT8889CN/C N-1 24 Pin SSOP

-40°C to +85°C

Figure 1 - Functional Block Diagram

TONE

IN+

INGS

OSC1 OSC2

DDVRefVSS

ESt St/GT

D0 D1 D2 D3

IRQ

/CP

DS/RD CS R/W/WR RS0

∑

D/A

Converters

Row and

Column

Counters

Transmit Data

Data

Bus

Buffer

Tone Burst Gating Cct.

Oscillator

Circuit

Bias

Circuit

Control

Logic

Digital

Algorithm and Code Converter

Control

Logic

Steerin g

Logic

Status

Control

Receive Data

Interrupt

Logic

I/O

Control

Low Group

Filter

High Group

Filter

Dial Tone Filter

ISSUE 2 May 1995

MT8889C/MT8889C-1

Integrated DTMFTransceiver

with Adaptive Micro Interface

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Figure 2 - Pin Connections

Pin Description

Pin #

Name Description

20 24

11 IN+Non-inverting op-am p input. 22 IN- Inverting op-amp input . 33 GSGain Select. Gives access to output of front end differential amplif ier for connecti on of

feedback resistor.

44 V

Ref

Reference Voltage output (VDD/2).

55 V

Ground (0V). 66OSC1Oscillator input. This pin can also be driven directl y by an external clock. 77OSC2Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes

the internal oscillator circuit. Leave open circuit when OSC1 is driven externally. 8 10 TONE Output from internal DTMF transmitter. 911 R/W

(WR

)

(Motorola) Read/Write

or (Intel) Write microprocessor input. TTL compatible.

10 12 CS

Chip Select input. This signal must be quali fie d externally by either address strobe (AS),

valid memory address (VMA) or address latch enable (ALE) signal, see Figure 12.

11 13 RS0 Register Select input. Refer to Table 3 for bit interpretation. TTL compatible. 12 14 DS (RD

) (Motorola) Data Strobe or (Inte l) Read microprocessor input. Act ivity on this input is only

required when the device is being accessed. TTL compatible.

13 15 IRQ

/CP Interrupt Request/Call Progress (ope n drain) outpu t. In interrupt mode, this output goes

low when a valid DTMF tone burst has been transmitted or received. In call progress mode,

this pin will output a rectangular signal representative of the input signal applied at the input

op-amp. The input signal must be within the bandwidth lim it s of the call progress filte r, see

Figure 8.

14-1718-21D0-D3 Microprocessor data bus. High impedance when CS

= 1 or DS =0 (Motorola) or RD = 1

(Intel). TTL compatible.

18 22 ESt Early Steering output. Present s a logic high once the digital algo rithm has detect ed a valid

tone pair (signal condition). Any moment ary loss of signal con dition will cause ESt to return

to a logic low.

19 23 St/GT Steering Input/Guard Time output (bidirect ional ). A voltage great er than V

TSt

detected at St causes the device to register the detected tone pair and updat e the output latch. A voltage less than V

TSt

frees the device to accept a new tone pair. The GT output acts to

reset the external steering time-const ant; its stat e is a function of ESt and the volt age on St.

20 24 V

Positive power supply (5V typ.).

8,9 16,

NC No Connection.

1 2

3 4

5 6

7 8 9

20 19 18 17 16 15 14 13

IN+

IN-

VRef

VSS OSC1 OSC2

TONE

R/W

/WR

VDD St/GT ESt D3 D2 D1 D0 IRQ

/CP

DS/RD RS0

1 2

3 4

5 6

7 8

9 10 11 12

24 23 22 21 20 19 18 17

IN+

IN-

VRef

VSS OSC1 OSC2

TONE

R/W

/WR

VDD St/GT ESt D3 D2 D1 D0 NC NC IRQ

/CP DS/RD RS0

24 PIN SSOP

20 PIN CERDIP/PLASTIC DIP/SOIC

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Functional Description

The MT8889C/MT8889C-1 Integrated DTMF Transceiver consists of a high performance DTMF receiver with an internal gain setting amplifier and a DTMF generator, which employs a burst counter to synthesize precise tone bursts and pauses. A call progress mode can be selected so that frequencies within the specified passband can be detected. The adaptive micro interface allows microcontrollers, such as the 68HC11, 80C51 and TMS370C50, to access the MT8889C/MT8889C-1 internal registers.

Input Configuration

The input arrangement of the MT8889C/MT8889C-1 provides a differential-input operational amplifier as well as a bias source (V

Ref

), which is used to bias the

inputs at V

/2. Provision is made for connection of a feedback resistor to the op-amp output (GS) for gain adjustment. In a single-ended configuration, the input pins are connected as shown in Figure 3.

Figure 4 shows the necessary connections for a differential input configuration.

Receiver Se ction

Separation of the low and high group tones is achieved by applying the DTMF signal to the inputs of two sixth-order switched capacitor bandpass filters, the bandwidths of which correspond to the low and high group frequencies (see Table 1). The filters also incorporate notches at 350 Hz and 440 Hz for exceptional dial tone rejection. Each filter output is followed by a single order switched capacitor filter section, which smooths the signals prior to limiting. Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the incoming DTMF signals.

Figure 3 - Single-Ended Input Configuration

IN+

IN-

Ref

VOLTAGE GAIN

) = RF / R

MT8889C/ MT8889C-1

Figure 4 - Differential Input Configuration

0= LOGIC LOW, 1= LOGIC HIGH

Table 1. Functional Encode/Decode Table

LOW

HIGH

DIGIT D

697 1209 1 0 0 0 1 697 1336 2 0 0 1 0 697 1477 3 0 0 1 1 770 1209 4 0 1 0 0 770 1336 5 0 1 0 1 770 1477 6 0 1 1 0 852 1209 7 0 1 1 1 852 1336 8 1 0 0 0 852 1477 9 1 0 0 1 941 1336 0 1 0 1 0 941 1209 * 1 0 1 1 941 1477 # 1 1 0 0 697 1633 A 1 1 0 1 770 1633 B 1 1 1 0 852 1633 C 1 1 1 1 941 1633 D 0 0 0 0

IN+

IN-

Ref

MT8889C/

DIFFERENTIAL INPUT AMPLIFIER

C1 = C2 = 10 nF R1 = R4 = R5 = 100 kΩ R2 = 60kΩ, R3 = 37.5 kΩ R3 = (R2R5)/(R2 + R5)

VOLTAGE GAIN

diff) - R5/R1

INPUT IMPEDANCE

diff) = 2 R12 + (1/ωC)

MT8889C-1

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Following the filter section is a decoder employing digital counting techniques to determine the frequencies of the incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm protects against tone simulation by extraneous signals such as voice while providing tolerance to small frequency deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the detector recognizes the presence of two valid tones (this is referred to as the “signal condition” in some industry specifications) the “Early Steering” (ESt) output will go to an active state. Any subsequent loss of signal condition will cause ESt to assume an inactive state.

Steering Circuit

Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt causes v

(see Figure 5) to rise as the capacitor discharges. Provided that the signal condition is maintained (ESt remains high) for the validation period (t

GTP

), vc reaches the threshold

TSt

) of the steering logic to register the tone pair, latching its corresponding 4-bit code (see Table 1) into the Receive D ata Regist er. At th is point t he GT output is activated and drives v

to VDD. GT continues to drive high as long as ESt remains high. Finally, after a short de lay to a ll ow th e o ut put latch to settle, the delayed steering output flag goes high, signalling that a received tone pair has been registered. The status of the delayed steering flag can be monitored by checking the appropriate bit in the status register. If Interrupt mode has been selected, the IRQ

/CP pin will pull low when the

delayed s t e er ing flag is a cti ve.

The contents of the output latch are updated on an active delayed steering transition. This data is presented to the four bit bidirectional data bus when the Receive Data Register is read. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (drop out) too short to be considered a valid pause. This facility, together with the capability of selecting the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements.

Figure 5 - Basic Steering Circuit

Guard Time Adjustment

The simple steering circuit shown in Figure 5 is adequate for most applications. Component values are chosen according to the following inequalities (see Figure 7):

REC

≥ t

DPmax

+ t

GTPmax

- t

DAmin

REC

≤ t

DPmin

+ t

GTPmin

- t

DAmax

tID ≥ t

DAmax

+ t

GTAmax

- t

DPmin

tDO ≤ t

DAmin

+ t

GTAmin

- t

DPmax

The value of tDP is a device parameter (see AC Electrical Characteristics) and t

REC

is the minimum signal duration to be recognized by the receiver. A value for C1 of 0.1 µF is recommended for most

Figure 6 - Guard Time Adjustment

St/GT

ESt

MT8889C/

GTA

= (R1C1) In (VDD / V

TSt

)

GTP

= (R1C1) In [VDD / (VDD-V

TSt

)]

MT8889C-1

St/GT

ESt

St/GT

ESt

GTA

= (R1C1) In (VDD/V

TSt

)

GTP

= (RPC1) In [VDD / (VDD-V

TSt

)]

= (R1R2) / (R1 + R2)

GTA

= (RpC1) In (VDD/V

TSt

)

GTP

= (R1C1) In [VDD / (VDD-V

TSt

)]

= (R1R2) / (R1 + R2)

a) decreasing tGTP; (tGTP < tGTA)

b) decreasing tGTA; (tGTP > tGTA)

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applications, leaving R1 to be selected by the designer. Different steering arrangements may be used to select independent tone present (t

GTP

) and

tone absent (t

GTA

) guard times. This may be necessary to meet system specifications which place both accept and reject limits on tone duration and interdigital pause. Guard t ime adjustment also allows the designer to tailor system parameters such as talk off and noise immunity.

Increasing t

REC

improves talk-off performance since it reduces the probability that tones simulated by speech will maintain a valid signal condition long enough to be registered. Alternatively, a relatively short t

REC

with a long tDO would be appropriate for extremely noisy environments where fast acquisition time and immunity to tone drop-outs are required. Design information for guard time adjustment is shown in Figure 6. The receiver timing is shown in Figure 7 with a description of the events in Figure 9.

Call Progress Filter

A call progress mode, using the MT8889C/ MT8889C-1, can be selected allowing the detection of various tones, which identify the progress of a telephone call on the network. The call progress tone input and DTMF input are common, however, call progress tones can only be detected when CP

mode has been selected. DTMF signals cannot be detected if CP mode has been selected (see Table

7). Figure 8 indicates the useful detect bandwidth of the call progress filter. Frequencies presented to the input, which are within the ‘accept’ bandwidth limits of the filter, are hard-limited by a high gain comparator with the IRQ

/CP pin serving as the output. The squarewave output obtained from the schmitt trigger can be analyzed by a microprocessor or counter arrangement to determine the nature of the call progress tone being detected. Frequencies which are in the ‘reject’ area will not be detected and consequently the IRQ

/CP pin will remain low.

Figure 8 - Call Progress Response

AAAA

AAA

AAAA

AAA

AAAA

LEVEL

(dBm)

FREQUENCY (Hz)

-25

0 250 500 750

= Reject = May Accept = Accept

Figure 7 - R ece iver Tim ing Diag ram

ESt

St/GT

-RX

Read Status Register

IRQ

/CP

EVENTS

ABCDEF

REC

TONE #n

TONE #n + 1

GTP

GTA

PStRX

PStb3

DECODED TONE # (n-1)

# n

# (n + 1)

TSt

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Figur e 9 - D e scri pt ion of Tim in g Ev en ts

EXPLANATION OF EVENTS

A) TONE BURSTS DETECTED, TONE DURATION INVALID, RX DATA REGISTER NOT UPDATED. B) TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER. C) END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER

RETAINED UNTIL NEXT VALID TONE PAIR. D) TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER. E) ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, DATA R EMAINS UNCHANGED. F) END OF TONE #n+1 DE TECTED, TONE A BSENT DURATION VALID, INFORMATION IN RX DATA REGISTER

RETAINED UNTIL NEXT VALID TONE PAIR.

EXPLANATION OF SYMBOLS

DTMF COMPOSITE INPUT SIG NA L. ESt EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES. St/GT STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT. RX

-RX34-BIT DECODED DATA IN RECEIVE DATA REGISTER

b3 DEL AYED STEERING. INDICATES THAT VALID FREQUEN CIES HAVE BEEN PRESENT/ABSENT FOR THE

REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. ACTIVE LOW FOR THE DURATION OF A VALID DTMF SIGNAL .

b2 INDICATES THAT VALID DATA IS IN THE RECEIVE DATA REGISTER. THE BIT IS CLEARED AFTER THE STATUS

IRQ

/CP INTERRUPT IS ACTIVE INDICATING THAT NEW DATA IS IN THE RX DATA REGISTER. THE INTERRUPT IS

CLEARED AFTER THE STATUS REGISTER IS READ.

REC

MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID. t

REC

MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION. t

MINIMUM TIME BET WEEN VALID SEQUENTIAL D TMF SIG NAL S. t

MAXIMUM ALLOWABLE DROPOUT DURING VALID DTMF SIGNAL. t

TIME TO DETECT VALID FREQUENCIES PRESENT. t

TIME TO DETECT VALID FREQUENCIES ABSENT. t

GTP

GUARD TIME, TO NE PR ESEN T. t

GTA

GUARD TIME, TO NE ABSEN T.

DTMF Generator

The DTMF transmitter employed in the MT8889C/ MT8889C-1 is capable of generating all sixteen standard DTMF tone pairs with low distortion and high accuracy. All frequencies are derived from an external 3.579545 MHz crystal. The sinusoidal waveforms for the individual tones are digitally synthesized using row and column programmable dividers and switched capacitor D/A converters. The row and column tones are mixed and filtered providing a DTMF signal with low total harmonic distortion and high accuracy. To specify a DTMF signal, data conforming to the encoding format shown in Table 1 must be written to the transmit Data Register. Note that this is the same as the receiver output code. The individual tones which are generated (f

LOW

and f

HIGH

) are referred to as Low Group and High Group tones. As seen from the table, the low group frequencies are 697, 770, 852 and 941 Hz. The high group frequencies are 1209, 1336, 1477 and 1633 Hz. Typically, the high group to low group amplitude ratio (twist) is 2 dB to compensate for high group attenuation on long loops.

The period of each tone consists of 32 equal time segments. The period of a tone is controlled by varying the length of these time segments. During

write operations to the Transmit Data Register the 4 bit data on the bus is latched and converted to 2 of 8 coding for use by the programmable divider circuitry. This code is used to specify a time segment length, which will ultimately determine the frequency of the tone. When the divider reaches the appropriate count, as determined by the input code, a reset pulse is issued and the counter starts again. The number of time segments is fixed at 32, however, by varying the segment length as described above the frequency can also be varied. The divider output clocks another counter, which addresses the sinewave lookup ROM.

The lookup table contains codes which are used by the switched capacitor D/A converter to obtain discrete and highly accurate DC voltage levels. Two identical circuits are employed to produce row and column tones, which are then mixed using a low noise summing amplifier. The oscillator described needs no “start-up” time as in other DTMF generators since the crystal oscillator is running continuously thus providing a high degree of tone burst accuracy. A bandwidth limiting filter is incorporated and serves to attenuate distortion products above 8 kHz. It can be seen from Figure 6 that the distortion products are very low in amplitude.

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Figure 10 - Spectrum Plot

Scaling Information

10 dB/Div Start Frequency = 0 Hz Stop Frequency = 3400 Hz Marker Frequency = 697 Hz and 1209 Hz

Burst Mode

In certain telephony applications it is required that DTMF signals being generated are of a specific duration determined either by the particular application or by any one of the exchange transmitter specifications currently existing. Standard DTMF signal timing can be accomplished by making use of the Burst M o de. T h e tr an s m itte r is capable o f i ssui n g symmetric bursts/pauses of predetermined duration. This bu rst/paus e durat ion is 51 ms±1 m s which i s a standard interval for autodialer and central office applications. After the burst/pause has been issued, the appropriate bit is set in the Status Register indicating that the transmitter is ready for more data. The timing described above is available when DTMF mode has been selected. However, when CP mode (Call Progress mode) is selected, the burst/pause duration i s do ub le d to 1 0 2 ms ± 2 ms . No te th a t wh e n CP mode and Burst mode have been selected, DTMF tones may be transmitted only and

not

received. In applications where a non-standard burst/pause time is desirable, a software timing loop or external timer can be used to provide the timing pulses when the burst mode is disabled by enabling and disabling the transmitter.

Single Tone Generation

A single tone mode is available whereby individual tones from the low group or high group can be generated. This mode can be used for DTMF test equipment applications, acknowledgment tone generation and distortion measurements. Refer to Control Register B description for details.

Table 2. Actual Frequencies Versus Standard

Requirements

Distortion Calculations

The MT8889C/MT8889C-1 is capable of producing precise tone bursts with minimal error in frequency (see Table 2). The internal summing amplifier is followed by a first-order lowpass switched capacitor filter to minimize harmonic components and intermodulation products. The total harmonic distortion for a

single tone

can be calculated using Equation 1, which is the ratio of the total power of all the extraneous frequencies to the power of the fundamental frequency expressed as a percentage.

Equation 1. THD (%) For a Single Tone

ACTIVE

INPUT

OUTPUT FREQUENCY (Hz)

%ERROR

SPECIFIED ACTUAL

697 699.1 +0.30

770 766.2 -0.49

852 847.4 -0.54

941 948.0 +0.74

1209 1215.9 +0.57

1336 1331.7 -0.32

1477 1471.9 -0.35

1633 1645.0 +0.73

THD (%) = 100

fundamental

+ V

+ .... V

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The Fourier components of the tone output correspond to V

.... Vnf as measured on the output

waveform. The total harmonic distortion for a

dual

tone

can be calculated using Equation 2. V

and V

correspond to the low group amplitude and high group amplitude, respectively and V

IMD

is the sum of all the intermodulation components. The internal switched-capacitor filter following the D/A converter keeps distortion products down to a very low level as shown in Figure 10.

Equation 2. THD (% ) For a Dual Tone

DTMF Clo ck Ci rcuit

The internal clock circuit is completed with the addition of a standard television colour burst crystal. The crystal specification is as follows:

Frequency: 3.579545 MHz Frequency Tolerance:

±0.1%

Resonance Mode: Parallel Load Capacitance: 18pF Maximum Series Resistance:150 ohms Maximum Drive Level: 2mW

e.g. CTS Kn ights MP0 36 S

To yoco m T QC-203-A-9S

A number of MT8889C/MT8889C-1 devices can be connected as shown in Figure 11 such that only one crystal is required. Alternatively, the OSC1 inputs on all devices can be driven from a TTL buffer with the OSC2 outputs left unconnected.

Figure 11 - Common Crystal Connection

Microprocessor Int erf ace

The MT8889C/MT8889C-1 design incorporates an adaptive interface, which allows it to be connected to

+ V

+ .... V

+ V

+ .. V

+ V

IMD

THD (%) = 100

MT8889C/

OSC1 OSC2

MT8889C/

OSC1 OSC2

MT8889C/

OSC1 OSC2

3.579 545 MH z

MT88 89C-1 MT88 89C-1 M T888 9C-1

various kinds of microprocessors. Key functions of this interface include the following:

• Continuous activity on DS/RD

is not necessary

to update the internal status registers.

• sens es w he th er i n put tim i ng is t ha t of an I nte l o r Motorola controller by monitoring the DS (RD

R/W

(WR) and CS inputs.

• generate s equ ivale nt CS

signal for internal

operation f or all proc essors .

• differentia tes be twee n mul tiplex ed a nd nonmultiplexed microprocessor buse s. Address and data ar e latc hed in accord ingly.

• compatible with Motorola and Intel processors.

Figure 17 shows the timing diagram for Motorola microprocessors with separate address and data buses. Members of this microprocessor family include 2 MHz versions of the MC6800, MC6802 and MC6809. For the MC6809, the chip select (CS

) inpu t signal is formed by NANDing the (E+Q) clocks and address decode output. For the MC6800 and MC6802, CS

is formed by NANDing VMA and

address decode output. On the falling edge of CS

, the internal logic senses the state of data strobe (DS). When DS is low, Motorola proces sor oper ation is selected.

Figure 18 shows the timing diagram for the Motorola MC68HC11 (1 MHz) microcontroller. The chip select (CS

) input is formed by NANDing address strobe

(AS

) and address decode output. Again, the MT8889C/MT8889C-1 examines the state of DS on the falling edge of CS

to deter m in e if th e m icro has a Motorola bus (when DS is low). Additionally, the Texas Instruments TMS370CX5X is qualified to have a Motorola interface. Figure 12(a) summarizes connection of these Motorola processors to the MT8889C/MT8889C-1 DTMF transceiver.

Figures 19 and 20 are the timing diagrams for the Intel 8031/8051 (12 MHz) and 8085 (5 MHz) microcontrollers with multiplexed address and data buses. The MT8889C/MT8889C-1 latches in the state of RD on the falling edge of CS. When RD is high, Intel processor operation is selected. By NANDing the address latch enable (ALE) output with the high-byte address (P2) decode output, CS

can be generated. Figure 12(b) summarizes the connection of these Intel processors to the MT8889C/MT8889C-1 transceiver.

NOTE: The adaptive micro interface relies on highto-low transition on CS

to recognize the

microcontroller interface and this pin must not

be tied

permanently low.

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The adaptive mic ro interface prov ides access to five internal registers. The read-only Receive Data Register contains the decoded output of the last valid DTMF digit received. Data entered into the write-only Transmit Data Register will determine which tone pair is to be generated (see Table 1 for coding details). Transceiver control is accomplished with two control registers (see Tables 6 and 7), CRA and CRB, which have the same address. A write operation to CRB is executed by first setting the most significant bit (b3) in CRA. The following write operation to the same address will then be directed to CRB, and subsequent write cycles will be directed back to CRA. The read-only status register indicates the curre n t t ra n sce iver state ( s ee Table 8).

A software reset must be included at the beginning of all programs to initialize the control registers upon power-up or power reset (see Figure 15). Refer to Tables 4-7 for bit descriptions of the two control registers.

The multiplexed IRQ

/CP pin can be programmed to generate an interrupt upon validation of DTMF signals or when the transmitter is ready for more data (burst mode only). Alternatively, this pin can be configured to provide a square-wave output of the call progress signal. The IRQ

/CP pin is an open drain output and requires an external pull-up resistor (see Figure 13).

Table 3. I nternal Regis ter Functi ons

Table 4. CRA Bit Positio ns

Table 5. CRB Bit Positio ns

Motorola Intel

RS0 R /W

WR RD FUNCTION

0001

Write to Transmit Data Register

0110

Read from Receive Data Register

1001

Write to Control Register

1110

Read from Status Register

b3 b2 b1 b0

RSEL IRQ CP/DTMF

TOUT

b3 b2 b1 b0

C/R

S/D TEST BURST

ENABLE

Figure 12 a) & b) - MT8889 Interface Connections for Various Intel and Motorola Micros

MC6800/6802

MT8889/MT8889C-1 MT8889C/MT8889C-1

A0-A15

VMA

D0-D3

MC68HC11

MC6809

MT8889/MT8889C-1

MT8889C/MT8889C-1

8031/8051 8080/8085

Φ2

CS RS0

D0-D3 R/W

/WR

DS/RD

A8-A15

AD0-AD3

RS0

D0-D3

R/W

/WR

DS/RD

A0-A15

D0-D3

R/W

CS RS0

D0-D3 R/W/WR

DS/RD

A8-A15

ALE

D0-D3 RS0

DS/RD R/W/WR

(a)

(b)

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Table 6. Control Register A Description

Ta ble 7

. C ontrol Re gister B Des cription

BIT NAME DESCRIPTION

b0 TOUT Tone Output Control. A logic high enables the tone output; a logic low turns the tone output

off. This bit controls all transmit tone functions.

b1 CP/DTMF

Call Progress or DTMF Mode Select. A logic high enables the receive call progress mode;

a logic low enables DTMF mode. In DTMF mode the device is capable of receiving and transmitting DTMF signals. In CP m ode a retangular wave rep r esentation of the re ce ived tone signal will be present on the IRQ

/CP output pin if IRQ has been enabled (control register A, b2=1). In order to be detected, CP signals must be within the bandwidth specified in the AC Electrical Characteristi cs for Call Progress. Note: DTMF signals cannot be detected when CP mode is selected .

b2 IRQ Interrupt Enable. A logic high enables the interrupt function; a logic low de-activate s the

interrupt function. When IRQ is en abled and DTM F mode is selected (cont rol registe r A, b1=0), the IRQ

/CP output pin wil l go low when either 1) a valid DTMF signal has been received for a valid guard time duration, or 2) the transm itter is ready for more data (burst mode only).

b3 RSEL Register Select. A logic high selects control register B for the next write cycle to the

control register address. Afte r writing to control register B, the following control register write cycle will be directed to control register A.

BIT NAME DESCRIP TI ON

b0 BURST

Burst Mode Sel ect. A logic hig h de-act ivate s burst mod e; a logi c low e nables b ur st mode. When activated, the d igital code representing a DTMF sig nal (see Table 1) can be writte n to the transmit register, which will result in a transmit DTMF tone burst and pause of equal durations (typically 51 msec). Following the pause, the status register will be updated (b1 Transmit Data Register Empty), and an inte rrupt will occur if the interrupt mode has been enabled.

When CP mode (control register A, b1) is enabled the normal tone burst and pause durations are extended from a typical duratio n of 51 msec to 102 msec.

When BURST is high (de-activated) the transmit tone burst duration is determined by the TOUT bit (control register A, b0).

b1 TEST Test Mode Control. A logic high enables th e test mode; a logic low de-activates the test

mode. When TEST is ena bled and DT MF m ode is selected (con trol regist er A, b1=0), th e signal present on the IRQ

/CP pin will be analogous to the state of the DELAYED

STEERING bit of the status register (see Figure 7, signal b3).

b2 S/D

Single or Dual Tone Ge neration. A logic high selects the single tone output; a logic low selects the dual tone (DTM F) output. The single tone generat ion function requ ires furthe r selection of either the r ow or colum n tones (l ow or hi gh group ) throu gh the C/ R

bit (control

b3 C/R

Column or Row Tone Select. A logic high selects a column tone output; a logic low selects a row tone outp ut. Th is f unction is used in conjunctio n wi th th e S/D

bit (control regi ster B,

b2).

Page 11

MT8889C/MT8889C-1

4-117

Table 8. Status Register Description

Figure 13 - Application Circuit (Single-Ended Input)

BIT NAME STATUS FL AG SE T STATUS FLAG CLEARED

b0 IRQ Interrupt has occurred. Bit one

(b1) or bit two (b2) is set.

Interrupt is inactive. Cleared after Status Register is read.

b1 TRANSM I T DATA

Pause duration has terminat ed and transmitter is ready for new data.

Cleared after Status Register is read or when in non-burst mode.

b2 RECEIVE DATA REGISTER

FULL

Valid data is in the Receive Data Register.

Cleared after Status Register is read.

b3 DELAYED

STEERING Set upon the valid detection of

the absence of a DTMF signal.

Cleared upon the detection of a valid DTMF signal.

IN+ INGS VRef VSS OSC1 OSC2 TONE R/W

/WR

VDD

St/GT

ESt

D3 D2 D1 D0

IRQ

/CP

DS/RD

RS0

DTMF/CP INPUT

DTMF OUTPUT

X-tal

To µP or µC

Notes: R1, R2 = 100 kΩ 1% R3 = 374 Ω 1% R4 = 3.3 kΩ 10% RL = 10 k Ω (min.) C1 = 100 nF 5% C2 = 100 nF 5% C3 = 100 nF 10%* X-tal = 3.579545 MHz

* Microprocessor based systems can inject undesirab le noise into the supply rails. The performance of the MT8889C/ MT 8889 C-1 can be optimized by keeping noise on the supply rails to a minimum. The decoupling capacitor (C3) should be connected close to the device and ground loops should be avoided.

MT8889C/MT8889C-1

Page 12

MT8889C/MT8889C-1

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Figure 14 - Test Circuits

Figure 15 - Application Notes

TEST POINT

MMD6150 (or equivalent)

5.0 VDC

2.4 kΩ

24 kΩ

130 pF

MMD7000 (or equivalent)

TEST POINT

5.0 VDC

3 kΩ

100 pF

Test load for IRQ

/CP pinTest load for D0-D3 pins

INITIALIZATION PROCEDURE

A software reset must be included at the beginning of all programs to initialize the control registers after power up. The initialization procedure should be implemented 100ms after power up.

Description: Motorola

Intel Data

RS0 R/W

WR RD b3 b2 b1 b0

1) Read Status Register 1 1 1 0 X X X X

2) Write to Control Register 1 0 0 1 0 0 0 0

3) Write to Control Register 1 0 0 1 0 0 0 0

4) Write to Control Register 1 0 0 1 1 0 0 0

5) Write to Control Register 1 0 0 1 0 0 0 0

6) Read Status Register 1 1 1 0 X X X X

TYPICAL CONTROL SE QUE NCE FOR BURST MODE APPLIC ATIONS

Transmit DTMF tones of 50 ms burst/50 ms pause and Receive DTMF Tones.

Sequence:

RS0 R/W

WR RD b3 b2 b1 b0

1) Write to Control Register A 1 0 0 1 1 1 0 1 (tone out, DTMF, IRQ

, Select C ontr o l Reg i st er B)

2) Write to Control Register B 1 0 0 1 0 0 0 0 (burst mode)

3) Write to Tr ansmit Data Register 0 0 0 1 0 1 1 1 (send a digit 7)

4) Wait for an Interrupt or Poll Status Register

5) Read the Status Register 1 1 1 0 X X X X

-if bit 1 is set, the Tx is ready for the next tone, in which case ... Write to Tr ansmit Register 0 0 0 1 0 1 0 1 (send a digit 5)

-if bit 2 i s se t, a D T MF tone ha s be e n r ec e iv e d, in which case .. ..

Read the Receive Data Register 0 1 1 0 X X X X

-if both bits are set ... Read the Receive Data Register 0 1 1 0 X X X X Write to Transmit D a ta R e gis te r 0 0 0 1 0 1 0 1

NOTE: IN THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SET UNTIL 100 ms ( ±2 ms) AFT ER THE DATA IS WRITTEN TO THE TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO 200 ms (± 4 ms)

Page 13

MT8889C/MT8889C-1

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* Excee di ng these values may cause pe rm anen t damage . Function al ope rati on under the se conditi ons is not implie d.

‡ Typical figures are at 25 °C and for design aid only: not guaranteed and not subject to producti on testin g.

† Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25 °C, V

=5V and for design aid only: not guaranteed an d not subje ct to production testing.

* Se e “Not es” followi ng AC Electrical Chara cteri st ics Tables.

Absolute Maximum Ratings*

Parameter Symbol Min Max Units

1 Power supply voltage V

DD-VSS

2 Voltage on any pin V

VSS-0.3 VDD+0.3 V

3 Current at any pin (Except V

DD and VSS

)10mA

4 Storage temperature T

-65 +150 °C

5 Package power dissipation P

1000 mW

Recommended Operating Conditions - Voltages are with respect to ground (V

) unless otherwise stated.

Parameter Sym Min Typ

‡

Max Units Test Conditions

1 Positive power supply V

4.75 5.00 5.25 V

2 Operating temperature T

-40 +85 °C

3 Crystal clock frequency f

CLK

3.575965 3.579545 3.583124 MHz

DC Electrical Characteristics

†

- VSS=0 V.

Characteristics Sym Min Typ‡Max Units Test Conditions

S U P

Operating supply volta ge V

4.75 5.0 5.25 V

2 Operating supply current I

7.0 11 mA

3 Power consumption P

57.8 mW

I N P U T S

High level input voltage (OSC1)

IHO

3.5 V Note 9*

5 Low level input voltage

(OSC1)

ILO

1.5 V Note 9*

6 Steering threshold voltage V

TSt

2.2 2.3 2.5 V VDD=5V

O U T P U T S

Low level output volt age (OSC2) V

OLO

0.1 V

No load Note 9*

8 High level out put voltage

(OSC2) V

OHO

4.9 V

No load Note 9*

9 Output leaka ge current

(IRQ) I

110µAVOH=2.4 V

10 V

Ref

output voltage V

Ref

2.4 2.5 2.6 V No load, VDD=5V

11 V

Ref

output resistan ce R

1.3 kΩ

i g

t a

Low level input voltage V

0.8 V

13 High level inpu t voltage V

2.0 V

14 Input leakage current I

10 µAVIN=VSS to V

Data

Bus

Source current I

-1.4 -6.6 mA VOH=2.4V

16 Sink current I

2.0 4.0 mA VOL=0.4V

ESt and

St/GT

Source current I

-0.5 -3.0 mA VOH=4.6V

18 Sink current I

24 mAVOL=0.4V

IRQ/

Sink current I

416 mAVOL=0.4V

Page 14

MT8889C/MT8889C-1

4-120

‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing.

† Characteristics are over recommended temperature and at V

=5V, using the test circuit shown in Figure 13.

† Characteristics are over recommended operating conditions (unless otherwise stated)

using the test circuit shown in Figure 13.

† Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C, VDD = 5V, and for design aid only: not guaranteed and not subject to production testing. * *Se e “Not es” foll owi ng AC Electrical Characterist ic s Tables.

Electrical Characteristics Gain Setting Amplifier - Voltages are with respect to ground (V

) unless otherwise stated, VSS= 0V, VDD=5V, TO=25°C.

Characteristics Sym Min Typ

‡

Max Units Test Conditions

1 Input leakage current I

±100 nA VSS ≤ VIN ≤ V

2 Input resistance R

10 MΩ

3 Input offset voltage V

25 mV 4 Power supply reject ion PSRR 60 dB 1 kHz 5 Comm on mo de rejecti on CMRR 60 dB 0. 75 ≤ V

≤ 4.25V

6 DC open loop voltage gain A

VOL

65 dB 7 Unity gain band widt h BW 1.5 M Hz 8 O utput volt age swing V

4.5 V

RL ≥ 100 kΩ to V

9 All owable capacit ive load (GS) C

100 pF

10 Allowable resistive load (GS) R

50 k Ω

11 Common mode range V

3.0 V

No Load

MT8889C-1 AC Electrical Characte rist ics† - Voltages are with respect to ground (V

) unless otherwise stated.

Characteristics Sym Min Typ Max Units Notes*

R X

Valid input signal levels (each tone of composite signal)

-31 +1 dBm 1,2,3,5,6

21.8 869 mV

RMS

1,2,3,5 ,6

2 Input Signal Level Reject -37 dBm 1,2,3,5,6

10.9 mV

RMS

1,2,3,5,6

MT8889C AC Electrical Characteristics

†

- Voltages are with respect to gro und (V

) unless otherwise stated.

Characteristics Sym Min Typ‡Max Units Notes*

R X

Valid input signal levels (each tone of composite signal)

-29 +1 dBm 1,2,3,5,6

27.5 869 mV

RMS

1,2,3,5,6

AC Electrical Characteristics† - Voltages are with respect to ground (V

) unless otherwise stated. fC=3. 579545 MHz

Characteristics Sym Min Typ‡Max Units Notes*

R X

Positive twist accept 8 dB 2,3,6,9 2 Negative twist accept 8 dB 2,3,6,9 3 Freq. deviation accept ±1.5%± 2Hz 2,3,5 4 Freq. deviation reject ±3.5% 2,3,5 5 Third tone tolerance -16 dB 2,3,4,5,9, 10 6 Noise tolerance -12 dB 2,3,4,5,7,9,10 7 Dial ton e tole ra n ce 22 dB 2 ,3,4,5,8, 9

Page 15

MT8889C/MT8889C-1

4-121

† Characteristics are over recommended operating conditions unless otherwise stated ‡ Typical figures are at 25°C, V

=5V, and for design aid only: not guaranteed and not subject to production testin g

† Characteristics are over recommended operating conditions unless otherwise stated ‡ Typical figures are at 25°C, V

=5V, and for design aid only: not guaranteed and not subject to production testin g

† Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and for design aid only: not guaranteed an d not subject to productio n testi ng.

AC Electrical Characteristics†- Call Progress - Voltages are with respect to ground (V

), unless otherwise stated .

Characteristi cs Sym Min Typ‡Max Units Conditi on s

1 Accept Bandwidth f

310 500 Hz @ -25 dBm,

Note 9

2 Lower freq. (REJECT) f

290 Hz @ -25 dBm

3 Upper freq. (REJECT) f

540 Hz @ -25 dBm

4 Call progress tone detect level (total

power)

-30 dBm

AC Electrical Characteristics†- DTMF Reception - Typical DTMF tone accept and reject requirements. Actual

values are user selectable as per Figures 5, 6 and 7.

Characteristics Sym Min Typ

‡

Max Units Conditions

1 Minimum ton e accept durati on t

REC

40 ms

2 Maximum tone reject duration t

REC

20 ms

3 Minimum int erdigit pause durat ion t

40 ms

4 Maximum tone drop-out duration t

20 ms

AC Electrical Characteristics† - Voltages are with respect to ground (V

), unless otherwise stated.

Characteristics Sym Min Typ

‡

Max Units Conditions

N E

Tone present dete ct time t

3 11 14 ms Note 11

2 Tone absent detect time t

0.5 4 8. 5 ms Note 11

3 Delay St to b3 t

PStb3

13 µs See Figure 7

4 Delay St to RX

-RX

PStRX

8 µs See Figure 7

N E

U T

Tone burst duration t

BST

50 52 ms DTMF mode

6 Tone pause duration t

50 52 ms DTMF mode

7 Tone burst duratio n (extended) t

BSTE

100 104 ms Call Progress mode

8 Tone pause duration (extended) t

PSE

100 104 ms Call Progress mode

9 High group output leve l V

HOUT

-6.1 -2.1 dBm RL=10kΩ

10 Low group output level V

LOUT

-8.1 -4.1 dBm RL=10kΩ

11 Pre-emphasis dB

023dBR

=10kΩ 12 Output distortion (Single Tone) THD -35 dB 25 kHz Bandwidth 13 R

=10kΩ 14 Frequency deviation f

±0.7 ±1.5 % fC=3.579545 MHz

15 Output load resistan ce R

10 50 kΩ

X T A

Crystal/clock frequency f

3.5759 3.5795 3 .583 1 MHz

17 Clock input rise and fall time t

CLRF

110 ns Ext. clock

18 Clock input duty cycle DC

40 50 60 % Ext. clo ck

19 Capacitive load (OSC2) C

30 pF

Page 16

MT8889C/MT8889C-1

4-122

† Characteristics are over recommended operating conditions unless otherwise stated ‡ Typical figures are at 25°C, V

=5V, and for design aid only: not guaranteed and not subject to production testin g

NOTES: 1) dBm=decibels above or below a reference power of 1 mW into a 600 ohm load.

2) Digit seq uence co ns is ts o f a ll 16 DTM F tones.

3) Tone duration=40 ms. Tone pause=40 ms.

4) Nominal DTMF frequencies are used.

5) Both tones in the composite signal have an equal amplitude.

6) The tone pa ir is devi at ed by ± 1 .5 %±2 Hz.

7) Bandwid th limited (3 k H z) G au s si an noise.

8) The precise dial tone frequencies are 350 and 440 Hz (±2 %).

9) Guarante ed b y de si gn an d ch a r acterizat ion . Not subjec t to pr o du c tio n tes ti ng .

10) Referenced to the low es t a mp li tu de to ne in the D TM F si gn al. 11 ) For guard t im e c a lc ul ation pur p os es .

Figure 16 - D S/RD/WR Clock Pulse

AC Electrical Characteristics†- MPU Interface - Voltages are with respect to ground (V

), unless otherwise stated.

Characteristics Sym Min Typ

‡

Max Units Conditions

1DS/RD

/WR clock frequency f

CYC

4.0 M Hz Figure 16

2DS/RD

/WR cycle period t

CYC

250 ns Figure 16

3DS/RD

/WR low pulse width

tCL

150 ns Figure 16

4DS/RD

/WR high pulse width t

100 ns Figure 16

5DS/RD

/WR rise and fall time tR,t

20 ns Figure 16

6R/W

setup time t

RWS

23 ns Figures 17 & 18

7R/W

hold time t

RWH

20 ns Figures 17 & 18

8 Address setup time (RS0) t

0 ns Figures 17 - 20

9 Address hold time (RS0) t

40 20 ns Figures 17 - 20

10 Data hold time (read) t

DHR

22 ns Figures 17 - 20

11 DS/RD

to valid data delay (read) t

DDR

100 ns Figures 17 - 20

12 Data setup time (write) t

DSW

45 ns Figures 17 - 20

13 Data hold time (write) t

DHW

10 ns Figures 17 - 20

14 Chip select setup time t

CSS

45 35 ns Figures 17 - 20

15 Chip select hold time t

CSH

40 ns Figures 17 - 20

16 Input Capacitance (data bus) C

5pF

17 Output Capacitance (IRQ

/CP) C

OUT

5pF

CYC

DS/RD/WR

Page 17

MT8889C/MT8889C-1

4-123

Figure 17 - MC6800/MC6802/MC6809 Timing Diagram

➀ t

DSW

is from d ata to D S fal li ng e dg e; t

CSH

is from DS rising edge to CS rising edge

Figure 18 - M C68H C11 Bus Timing (w ith m ultip lexed addr ess an d data buses)

Q clk*

A0-A15 (RS0)

R/W(read)

Read Data (D3-D0)

R/W

(write)

Write data (D3-D0)

= (E + Q).Addr [MC6809]

= VMA.Addr [MC6800, MC6802]

*microprocessor pin

RWS

RWH

16 bytes of Addr

DDR

DSW

➀

DHW

CSH

➀

CSS

CSH

➀

DHR

R/W

Read AD3-AD0 (RS0, D0-D3)

Write AD3-AD0 (RS0-D0-D3)

Addr * non-mux

AS *

CS = AS.Addr

* microprocessor pins

RWS

RWH

DDR

DHR

Data

DSW

DHW

CSH

CSS

High Byte of Ad dr

Addr

Page 18

MT8889C/MT8889C-1

4-124

Figure 19 - 8 031/ 8051/ 8085 Read Tim ing Dia gram

Figure 20 - 80 31/8 051 /8085 Wri te Timin g D iagra m

ALE*

P0* (RS0, D0-D3)

P2 * (Addr)

= ALE.Addr

* microprocessor pins

CSS

DDR

DHR

Data

A8-A15 Address

CSH

A0-A7

ALE*

P0* (RS0, D0-D3)

P2 * (Addr)

= ALE.Addr

* microprocessor pins

CSS

DSW

DHW

Data

A8-A15 Address

CSH

A0-A7