Datasheet MSP 3400 C Datasheet

PRELIMINARY DATA SHEET

MICRONAS
INTERMETALL

MSP 3400 C
Multistandard
Sound Processor

Edition Dec. 8, 1997
6251-377-3PD

MICRONAS

MSP 3400C

Contents
Page Section Title
5 1. Introduction
6 2. Features of the MSP 3400C

6 2.1. Features of the Demodulator and Decoder Sections
6 2.2. Features of the DSP-Section
6 2.3. Features of the Analog Section

7 3. Application Fields of the MSP 3400C

7 3.1. German 2-Carrier System (DUAL FM System)

9 4. Architecture of the MSP 3400C

9 4.1. Demodulator Block
9 4.1.1. Analog Sound IF – Input Section
9 4.1.2. Quadrature Mixers
10 4.1.3. Lowpass Filtering Block for Mixed Sound IF Signals
10 4.1.4. Phase and AM Discrimination
10 4.1.5. Differentiators
10 4.1.6. Lowpass Filter Block for Demodulated Signals
10 4.1.7. High Deviation FM Mode
10 4.1.8. MSPC-Mute Function in the Dual Carrier FM Mode
1 1 4.2. Analog Section and SCART Switching Facilities
1 1 4.3. MSP 3400C Audio Baseband Processing
11 4.3.1. Dual Carrier FM Stereo/Bilingual Detection
13 4.4. Audio PLL and Crystal Specifications
13 4.5. ADR Bus
14 4.6. S-Bus Interface
15 4.7. I

2

S Bus Interface

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16 5. I

17 5.1. Protocol Description
18 5.2. Proposal for MSP 3400C I2C Telegrams
18 5.2.1. Symbols
18 5.2.2. Write Telegrams
18 5.2.3. Read Telegrams
18 5.2.4. Examples
19 5.3. Start Up Sequence

20 6. Programming the Demodulator Part

20 6.1. Registers: Table and Addresses
21 6.2. Registers: Functions and Values
21 6.2.1. Setting of Parameter AD_CV
23 6.2.2. Control Register ‘MODE_REG’
24 6.2.3. FIR-Filter Switches
24 6.2.4. FIR-Parameter
26 6.2.5. DCO-Increments

2

C Bus Interface: Device and Subaddresses

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Contents, continued
Page Section Title

27 6.3. Sequences to Transmit Parameters and to Start Processing
27 6.4. Software Proposals for Multistandard TV-Sets
27 6.4.1. Multistandard System B/G German DUAL FM
28 6.4.2. Satellite Mode
28 6.4.3. Automatic Search Function for FM-Carrier Detection
28 6.4.4. Automatic Standard Detection

29 7. Programming the Audio Processing Part

29 7.1. Summary of the DSP Control Registers
31 7.1.1. Volume Loudspeaker Channel and Headphone Channel
32 7.1.2. Balance Loudspeaker and Headphone Channel
33 7.1.3. Bass Loudspeaker and Headphone Channel
33 7.1.4. Treble Loudspeaker and Headphone Channel
34 7.1.5. Loudness Loudspeaker and Headphone Channel
34 7.1.6. Spatial Effects Loudspeaker Channel
35 7.1.7. Volume SCAR T
35 7.1.8. Channel Source Modes
36 7.1.9. Channel Matrix Modes
36 7.1.10. SCART Prescale
36 7.1.11. FM Prescale
37 7.1.12. FM Matrix Modes
37 7.1.13. FM Fixed Deemphasis
37 7.1.14. FM Adaptive Deemphasis
37 7.1.15. I
37 7.1.16. ACB Register, Definition of the SCART-Switches and DIG_CTR_OUT Pins
38 7.1.17. Beeper
38 7.1.18. Identification Mode
38 7.1.19. FM DC Notch
38 7.1.20. Mode Tone Control
39 7.1.21. Equalizer Loudspeaker Channel
39 7.1.22. Automatic Volume Correction (AVC)
40 7.1.23. Subwoofer on Headphone Output
40 7.2. Exclusions
41 7.3. Summary of Readable Registers
41 7.3.1. Stereo Detection Register
41 7.3.2. Quasi Peak Detector
42 7.3.3. DC Level Register
42 7.3.4. MSP Hardware Version Code
42 7.3.5. MSP Major Revision Code
42 7.3.6. MSP Product Code
42 7.3.7. MSP ROM Version Code

2

S1 and I2S2 Prescale

MSP 3400C

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MSP 3400C

Contents, continued
Page Section Title
43 8. Specifications

43 8.1. Outline Dimensions
44 8.2. Pin Connections and Descriptions
48 8.3. Pin Configuration
51 8.4. Pin Circuits
53 8.5. Electrical Characteristics
53 8.5.1. Absolute Maximum Ratings
54 8.5.2. Recommended Operating Conditions
58 8.5.3. Characteristics

64 9. Application of the MSP 3400C
65 10. DMA Application
67 11. MSP Application with External Clock

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67 12. ADR Application
68 13. I
69 14. APPENDIX A: T echnical Code History
69 15. APPENDIX B: Documentation History

2

S Bus in Master/Slave Configuration with Standby Mode

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MSP 3400C

Multistandard Sound Processor

sound IF signal-in, down to processed analog AF-out, is
performed in a single chip. The IC is produced in 0.8 µm

Release Notes: The hardware description in this
document is valid for the MSP 3400C – C8 and newer

CMOS technology, combined with high performance
digital signal processing.

codes. Revision bars indicate significant changes
to the previous version.

The MSP 3400C 0.8 µ CMOS version is fully pin and
software compatible to the 1.0 µ MSP 3400 and MSP

1. Introduction

The MSP 3400C is designed as single-chip Multistan-

3410. The main difference between the MSP 3400C and
the MSP 3410, consists of the MSP 3410 being able to
decode NICAM signals.

dard Sound Processor for applications in analog and
digital TV sets, satellite receivers and video recorders.

The MSP-family , which is based on the MSP 2400, dem-

The MSP 3400C is available in PLCC68, PSDIP64,
PSDIP52, and PQFP80 package.

onstrates the progressive development towards highly
integrated multi-functional ICs.

Note: T o achieve compatibility with the functions of MSP

3400 and MSP 3410 (except NICAM), the load se­The MSP 3400C, again, improves function integration:
The full TV sound processing, starting with analog

quences must be programmed as described in the data

sheet of MSP 3410.

MSP 3400C Integrated Functions:

– FM-demodulation of all terrestrial standards (incl. identification decoding)
– FM-demodulation of all satellite standards
– various deemphasis types (incl. Panda1)
– volume, balance, bass, treble, loudness for loudspeaker and headphone output
– automatic volume correction (A.V.C.)
– 5 band graphic equalizer
– subwoofer output alternatively with headphone output
– spatial effect (pseudostereo/basewidth enlargement)
– ADR together with DRP 3510 A
– Dolby ProLogic together with DPL 3418/19/20 A
– 3 pairs of D/A converters
– 1 pair of A/D converters
– SCART switches

I2SI2C

25

MSP 3400C

2

2

2
2

LOUDSPEAKER OUT

HEADPHONE OUT

SCART1 OUT
SCART2 OUT

Sound IF 1
Sound IF 2

MONO IN
SCART1 IN
SCART2 IN
SCART3 IN

ADR/SBus

3

2
2
2

Fig. 1–1: Main I/O Signals MSP 3400C

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MSP 3400C

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2. Features of the MSP 3400C

2.1. Features of the Demodulator and Decoder
Sections

The MSP 3400C is designed to perform demodulation
of FM-mono TV sound and two carrier FM systems ac­cording to the German or Korean terrestrial specs. With
certain constraints, it is also possible to do AM-demodu­lation according to the SECAM system. Alternatively , the
satellite specs can be processed with the MSP 3400C.

For FM carrier detection in satellite operation, the AM­demodulation offers a powerful feature to calculate the
carrier field strength, which can be used for automatic
search algorithms. So, the IC facilitates a first step to­wards multistandard capability with its very flexible
application and may be used in TV -sets, satellite tuners,
and video recorders.

The MSP 3400C facilitates profitable multistandard ca­pability, offering the following advantages:

– two selectable analog inputs (TV and SA T-IF sources)
– Automatic Gain Control (AGC) for analog input: input

range: 0.14 – 3 Vpp

– integrated A/D converter for sound-IF inputs

2.2. Features of the DSP-Section

– flexible selection of audio sources to be processed
– digital input and output interfaces via I

nal DSP-processors, surround sound, ADR etc.

– digital interface to process ADR (Astra Digital Radio)

together with DRP 3510 A

– performance of all deemphasis systems including

adaptive Wegener Panda 1 without external compo­nents or controlling

– digitally performed FM-identification decoding and de-

matrixing

– digital baseband processing: volume, bass, treble,

5-band equalizer, loudness, pseudostereo, and base­width enlargement

– simple controlling of volume, bass, treble, equalizer

etc.

– increased audio bandwidth for FM-Audio-signals

(20 Hz – 15 kHz, 1 dB)

2.3. Features of the Analog Section

– three selectable analog pairs of audio baseband in-

puts (= three SCART inputs)
input level: ≤2 V RMS,
input impedance: ≥25 kΩ

2

S-Bus for exter-

– all demodulation and filtering is performed on chip and

is individually programmable
– no external filter hardware is required
– only one crystal clock (18.432 MHz) is necessary
– FM carrier level calculation for automatic search algo-

rithms and carrier mute function
– high deviation FM-mono mode (max. deviation:

approx. 360 kHz)

– one selectable analog mono input (i.e. AM sound),

input level: ≤2 V RMS,

input impedance: ≥10 kΩ
– two high quality A/D converters, S/N-Ratio: ≥85 dB
– 20 Hz to 20 kHz Bandwidth for SCART-to-SCART-

Copy facilities
– MAIN (loudspeaker) and AUX (headphones): two

pairs of 4-fold oversampled D/A-converters

output level per channel: max. 1.4 V RMS

output resistance: max. 5 kΩ

S/N-Ratio: ≥85 dB at maximum volume

max. noise voltage in mute mode: ≤10 µV (BW: 20 Hz

...16 kHz)
– one pair of four-fold oversampled D/A-converters sup-

plying two selectable pairs of SCART -Outputs. Output

level per channel: max. 2 V RMS, output resistance:

max. 0.5 kΩ, S/N-Ratio: ≥85 dB

(20 Hz...16 kHz)

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MSP 3400C

3. Application Fields of the MSP 3400C

The MSP 3400C processes TV sound according to the
German and Korean two carrier system and the com­monly used satellite systems. In the following sections,
a brief overview on the German FM-Stereo system
shows what is required of a multistandard audio IC.

3.1. German 2-Carrier System (DUAL FM System)

Since September 1981, stereo and dual sound pro­grams have been transmitted in Germany using the
2-carrier system. Sound transmission consists of the al­ready existing first sound carrier and a second sound
carrier additionally containing an identification signal.
More details of this standard are given in Table 3–1.

Table 3–1: European TV standards

TV-System Position of Sound

Carrier /MHz

Sound
Modulation

Color System Country

B/G 5.5/5.7421875 FM-Stereo PAL Germany
B/G 5.5/5.85 FM-Mono/NICAM PAL Scandinavia,Spain
L 6.5/5.85 AM-Mono/NICAM SECAM-L France
I 6.0/6.552 FM-Mono/NICAM PAL UK
D/K 6.5 /6.2578125 D/K1

FM-Stereo

SECAM-East USSR

6.5/6.7421875 D/K2

6.5/5.85 D/K-NICAM

FM-Mono/NICAM

Hungary

M
M-Korea

Satellite
Satellite

Tuner

4.5

4.5/4.724212

6.5

7.02/7.2

33 34 39 MHz 5 9 MHz

SAW Filter Sound IF Filter

Sound
IF
Mixer

Vision
Demo­dulator

Composite
Video

SCART
Inputs

FM-Mono
FM-Stereo

FM-Mono
FM-Stereo

AM Sound

SCART1

SCART2

SCART3

NTSC USA

Korea

PAL
PAL

MSP 3400C

2

2

2

2

2

SCART1

SCART2

Europe (ASTRA)
Europe (ASTRA)

Loudspeaker

Headphone

SCART
Outputs

According to the mixing characteristics of

I2S SBUS / ADR

I2S

the Sound-IF-mixer, the Sound-IF filter
may be omitted.

optional
Feature
Processor

AMU and DMA
or DRP

Fig. 3–1: Typical MSP 3400C application

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MSP 3400C

Table 3–2: Key parameters for B/G, D/K, and M 2-carrier sound system

Sound Carriers Carrier FM1 Carrier FM2

B/G D/K M B/G D/K M
Vision/sound power difference 13 dB 20 dB
Sound bandwidth 40 Hz to 15 kHz
Pre-emphasis 50 µs 75 µs 50 µs 75 µs
Frequency deviation ±50 kHz ±25 kHz ±50 kHz ±25 kHz

Sound Signal Components

Mono transmission mono mono
Stereo transmission (L+R)/2 (L+R)/2 R (L–R)/2
Dual sound transmission language A language B

PRELIMINARY DAT A SHEET

Identification of Transmission Mode on Carrier FM2

Pilot carrier frequency in kHz 54.6875 55.0699
Type of modulation AM
Modulation depth 50%
Modulation frequency mono: unmodulated

stereo: 117.5 Hz
dual: 274.1 Hz

Note: NICAM decoding can be achieved by using the
MSP 3410 instead of the MSP 3400C. Since the
MSP 3400C and the MSP 3410 are fully pin and soft­ware downwards compatible (concerning all features of
MSP 3410), it is possible to decide in the assembly line,
whether the application should be able to decode
NICAM or not.

149.9 Hz

276.0 Hz

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MSP 3400C

4. Architecture of the MSP 3400C

Fig. 4–1 shows a simplified block diagram of the IC. Its
architecture is split into three functional blocks:

1. demodulator section

2. digital signal processing (DSP) section performing
audio baseband processing

3. analog section containing two A/D-converters,
6 D/A-converters, and SCART switching facilities

4.1. Demodulator Block

4.1.1. Analog Sound IF – Input Section

The input pins ANA_IN1+, ANA_IN2+, and ANA_IN–
offer the possibility to connect two different sound IF
sources to the MSP 3400C. By means of bit [8] of
AD_CV (see Table 6–3), either terrestrial or satellite
sound IF signals can be selected. The analog-to-digital
conversion of the preselected sound IF signal is done by
a flash-converter, whose output can be used to control
an automatic gain circuit (AGC), providing optimum level
for a wide range of input levels. It is possible to switch
between automatic gain control and a fixed (setable) in­put gain. In the optimum case, the input range of the A/D
converter is completely covered by the sound IF source.

Some combinations of SAW filters and sound IF mixer
ICs, however, show large picture components on their
outputs. In this case, filtering is recommended. It was
found that the high pass filters formed by the coupling
capacitors at pins ANA_IN1+ and ANA_IN2+ as shown
in the application diagram are sufficient in most cases.

4.1.2. Quadrature Mixers

The digital input coming from the integrated A/D conver­ter may contain audio information at a frequency range
of theoretically 0 to 9 MHz corresponding to the selected
standards. By means of two programmable quadrature
mixers two different audio sources, for example FM1
and FM2, may be shifted into baseband position. In the
following, the two main channels are provided to pro­cess either:

– FM mono (channel 2) or
– FM2 (channel 1) and FM1 (channel 2).

Two independent digital oscillators are provided to gen­erate two pairs of sin/cos-functions. T wo programmable
increments, to be divided up into Low- and High Part, de­termine frequency of the oscillator, which corresponds
to the frequency of the desired audio carrier. In section

6.1., format and values of the increments are listed.

Sound IF

ANA_IN1+
ANA_IN2+

Mono

MONO_IN

SC1_IN_L

SCART1

SC1_IN_R

SC2_IN_L

SCART2

SC2_IN_R

SC3_IN_L

SCART3

SC3_IN_R

S_DA_IN / ADR_DA

S_CL / ADR_CL

SBUS/ADR Interface

Demodulator

S_ID / ADR_WS

A/D

A/D

SCART Switching Facilities

I2S_DA_OUT

S1..4

FM1 / AM
FM2

IDENT

SCART_L

SCART_R

I2S_DA_IN_1/2

I2S Interface

I2S1/2L/R

LOUD­SPEAKER L

LOUD­SPEAKER R

DFP

HEADPHONE L

HEADPHONE R

SCART_L

SCART_R

I2SL/R

I2S_CL

I2S_WS

D/A
D/A

D/A
D/A

D/A

D/A

AUD_CL_OUT

XTAL_IN

Audio PLL

XTAL_OUT

DACM_L

Loudspeaker

DACM_R

DACA_L

Headphone

DACA_R

SC1_OUT_L

SCART 1

SC1_OUT_R

SC2_OUT_L

SCART 2

SC2_OUT_R

Fig. 4–1: Architecture of the MSP 3400C

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MSP 3400C

PRELIMINARY DAT A SHEET

DCO1

VREFTOP

AD_CV[7:1]

ANA_IN1+

ANA_IN2+

AD_CV[8]

ANA_IN–

FRAME

FM2

DCO2

AGC AD

Pins

Internal signal lines

Control registers

Fig. 4–2: Demodulator architecture

Oscillator

FIR_REG_1

Mixer Lowpass

MSPC sound IF channel 1
(MSP-CH1: FM2)

MSPC sound IF channel 2
(MSP-CH2: FM1, AM)

Mixer Lowpass

FIR_REG_2

Oscillator

DCO2

Phase and
AM Dis­crimination

Amplitude

Amplitude

Phase and
AM Dis­crimination

Phase

Phase

Differen­tiator

Carrier
Detect

AD_CV[9,10,11]

Carrier
Detect

Differen­tiator

MODE_REG[8]

MODE_REG[8]

LowpassMute

Mixer IDENT

LowpassMute

FM1/AM

ADR_DA

FM2

4.1.3. Lowpass Filtering Block for Mixed Sound IF
Signals

FM bandwidth limitation is performed by a linear phase
Finite Impulse Response (FIR-filter). Just like the oscil­lators’ increments, the filter coefficients are program­mable and are written into the IC by the CCU via the con­trol bus. Two not necessarily dif ferent sets of coefficients
are required, one for channel 1 (FM2) and one for chan­nel 2 (FM1=FM-mono). In section 6.2.4., several coeffi­cient sets are proposed.

4.1.4. Phase and AM Discrimination

The filtered sound IF signals are demodulated by means
of the phase and amplitude discriminator block. On the
output, the phase and amplitude is available for further
processing. AM signals are derived from the amplitude
information, whereas the phase information serves for
FM demodulation.

4.1.5. Differentiators

FM demodulation is completed by differentiating the
phase information output.

4.1.6. Lowpass Filter Block for Demodulated
Signals

The demodulated FM and AM signals are further low­pass filtered and decimated to a final sampling frequen-

cy of 32 kHz. The usable bandwidth of the final base­band signals is about 15 kHz.

4.1.7. High Deviation FM Mode

By means of MODE_REG [9], the maximum FM-devi­ation can be extended to approximately 360 kHz.
Since this mode can be applied only for the MSPC sound
IF channel 2, the corresponding matrices in the base­band processing must be set to sound A. Apart from this,
the coefficient sets 380 kHz FIR_REG2 or 500 kHz
FIR_REG2 must be chosen for the FIR_REG_2. For a
given deviation, in relation to the normal FM-mode, the
audio level of the high-deviation mode is reduced by
6 dB.

4.1.8. MSPC-Mute Function in the Dual Carrier FM
Mode

T o prevent noise effects or FM identification problems in
the absence of one of the two FM carriers, the
MSP 3400 C offers a carrier detection feature, which
must be activated by means of AD_CV[9]. The mute lev­el may be programmed by means of AD_CV[10,11].
(see section 6.2.1.) If no FM carrier is available at the
MSPC channel 1, the corresponding channel FM2 is
muted. If no FM carrier is available at the MSPC channel
2, the corresponding channel FM1 is muted. In case of
the absence of both FM carriers, pure noise will be am­plified by the input AGC. Therefore, a proper mute func­tion depends on the noise quality of the TV set’s IF part
and cannot be guaranteed. The mute function is not rec­ommended for the satellite mode.

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MSP 3400C

4.2. Analog Section and SCART Switching Facilities

The analog input and output sections offer a wide range
of switching facilities, which are shown in Fig. 4–3. To
design a TV-set with 3 pairs of SCART-inputs and two
pairs of SCART -outputs, no external switching hardware
is required.

The switches are controlled by the ACB bits defined in
the audio processing interface (see section 7. Program­ming the Audio Processing Part).

If the MSP 3400C is switched off by first pulling ST AND­BYQ low, and then disconnecting the 5 V, but keeping
the 8 V power supply (‘Standby’-mode), the switches
S1, S2, and S3 maintain their position and function. This
facilitates the copying from selected SCART-inputs to
SCART-outputs in the TV-sets standby mode.

SCART_IN

SC1_IN_L/R

MONO

SC2_IN_L/R

SC3_IN_L/R

from Audio Baseband
Processing (DFP)

SCARTL/R

2

2

2

2

D

A

2

ACB[1:0]

00

01

10

11

S1

ACB[3:2]

2

00

2

01

2

10

2

11

S2

ACB[5:4]

00

2

2

01

S3

10

2

to Audio Baseband
Processing (DFP)

A

2

D

SCART_OUT

2

SC1_OUT_L/R

2

SC2_OUT_L/R

SCARTL/R

4.3. MSP 3400C Audio Baseband Processing

By means of the DFP processor, all audio baseband
functions are performed by digital signal processing
(DSP). The DSP functions are grouped into three pro­cessing parts: input preprocessing, channel selection,
and channel postprocessing.

The input preprocessing is intended to prepare the vari­ous signals of all input sources in order to form a stan­dardized signal at the input to the channel selector. The
signals can be adjusted in volume, are processed with
the appropriate deemphasis, and are dematrixed if nec­essary .

Having prepared the signals that way , the channel selec­tor makes it possible to distribute all possible source sig­nals to the desired output channels.

The ability to route in an external coprocessor for special
effects like surround and sound field processing is of
special importance. Routing can be done with each input
source and output channel via the I

2

S inputs and out-

puts.
All input and output signals can be processed simulta-

neously. Note that the NICAM input signals are only
available in the MSP 3410 version. While processing the
adaptive deemphasis, no dual carrier stereo (German or
Korean) is possible. Identification values are not valid ei­ther.

4.3.1. Dual Carrier FM Stereo/Bilingual Detection

In the German and Korean TV standard, audio informa­tion can be transmitted in three modes: mono, stereo, or
bilingual. To obtain information about the current audio
operation mode, the MSP 3400C detects the so-called
identification signal. Information is supplied via the Ste­reo Detection Register to an external CCU.

Fig. 4–3: SCART-Switching Facilities
Bold lines determine the default configuration

In case of power-on start or starting from standby , the IC
switches automatically to the default configuration,
shown in Fig. 4–3. This takes place after the first I2C

IDENT

AM

Demodu-

lation

Stereo

Detection

Filter

Bilingual
Detection

Filter

Level

Detect

Level

Detect

Stereo

–

Detection

Register

transmission into the DFP part. By transmitting the ACB
register first, the default setting mode can be changed.

Fig. 4–4: Stereo/bilingual detection

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MSP 3400C

r

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Analog
Inputs

Demodulated
IF
Inputs

SBUS
Inputs

2

I

S Bus

Inputs

SCARTL

SCARTR

FM1

FM2

SBUS1

SBUS2

SBUS3

SBUS4

2

S1L

I

I2S1R

2

I

S2L

2

S2R

I

Adaptive
Deemphasis

DC level readout FM1

Deemphasis

50/75 µs

J17

DC level readout FM2

SCART

Prescale

FM

Prescale

I2S1

Prescale

I2S2

Prescale

FM-Matrix

Loudspeaker

Headphone

Channel Select

Quasi-Peak-

Channel

Matrix

Channel

Matrix

SCART

Channel

Matrix

I2S

Channel

Matrix

Channel

Matrix

AVC

Quasi-Peak

Detector

Bass/

Treble

or

Equalizer

Bass/

Treble

Quasi peak readout L

Quasi peak readout R

∑

Beeper

∑

Loudness

Loudness

Comple-

mentary

Highpass

Lowpass

Spatial
Effects

Balance

Balance

Level

Adjust

Volume

Volume

Volume

Loudspeaker L

Loudspeaker R

Subwoofer

Headphone L

Headphone R

SCART_L

SCART_R

2

I

SL

I2SR

Loudspeake
Outputs

Headphone
Outputs

SCART
Outputs

2

I

S

Outputs

PRELIMINARY DAT A SHEET

Fig. 4–5: Audio baseband processing (DSP-Firmware)

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MSP 3400C

Table 4–1: Several examples for recommended channel assignments for demodulator and audio processing part

Mode MSPC Sound IF-

Channel 1 / FM2

B/G-Stereo FM2 (5.74 MHz): R FM1 (5.5 MHz): (L+R)/2 B/G Stereo Speakers: FM Stereo
B/G-Bilingual FM2 (5.74 MHz): Sound B FM1 (5.5 MHz): Sound A No Matrix Speakers: FM

Sat-Mono not used FM (6.5 MHz): mono No Matrix Speakers: FM Sound A
Sat-Stereo 7.20 MHz: R 7.02 MHz: L No Matrix Speakers: FM Stereo
Sat-Bilingual 7.38 MHz: Sound C 7.02 MHz: Sound A No Matrix Speakers: FM

Sat High Dev.
Mode (e.g.
EutelSat)

don’t care 6.552 MHz No Matrix Speakers: FM

4.4. Audio PLL and Crystal Specifications

MSPC Sound IF­Channel 2 / FM1

FM­Matrix

Channel
Select

H.Phone : FM

H.Phone : FM

H.Phone : FM

nominal free running frequency should match the center

of the tolerance range between 18.433 and 18.431 MHz
The MSP 3400C runs at 18.432 MHz. A detailed specifi­cation of the required crystal for different packages and
master/slave applications can be found in Table 8.5.2.

as closely as possible. Due to different layouts of cus-

tomer PCBs, the matching capacitor size should be de-

fined in the application (see also Table 8.5.2.).
The clock supply of the entire system depends on the
MSP 3400C operation mode:

1. FM-Stereo/I

2

S Master operation:

The system clock runs free on the crystal’s 18.432 MHz.

2. I2S Slave operation:
In this case, the system clock is synchronizing on the
I2S_WS signal, which is fed into the MSP 3400C
(Mode_Reg[3] = 1).

4.5. ADR Bus

T o be able to process ADR, the MSPC has a special de-

signed interface to work together with DRP 3510A. T o be

prepared for an upgrade to ADR with an additional DRP

board, the following lines of MSP 3400C should be pro-

vided on a feature connector:

Channel
Matrix

Speakers: Sound A
H.Phone : Sound B

Speakers: Sound A
H.Phone :Sound B=C

Speakers: Sound A
H.Phone : Sound A

3. D2-MAC operation:
In this case, the system clock is locked to a synchroniz­ing signal (DMA_SYNC) supplied by the D2-MAC chip
(Mode_Reg[0] = 1). The DMA and the AMU chips can be
driven by the MSP 3400C audio clock (AUD_CL_OUT).

Remark on using the crystal:

External capacitors at each crystal pin to ground are re­quired. They are necessary for tuning the open-loop fre­quency of the internal PLL and for stabilizing the fre­quency in closed-loop operation. The higher the
capacitors, the lower the clock frequency results. The

– AUD_CL_OUT

2

–I

S_DA_IN1 or I2S_DA_IN2
–I2S_DA_OUT
–I2S_WS
–I2S_CLK
– S_CL = ADR_CL
– S_ID = ADR_WS
– S_DA_IN = ADR_DA

MICRONAS INTERMETALL 13

MSP 3400C

4.6. S-Bus Interface

Digital audio information provided by the DMA 2381 via
the AMU is serially transmitted to the MSP 3400C via the
S-Bus. The MSP 3400C is always in S-Bus master
mode.

The S-Bus interface consists of three pins:

1. S_DA_IN:
Four channels (4*16 bits) per sampling cycle (32 kHz)
are transmitted.

2. S_CL:
Gives the timing for the transmission of S-DATA
(4.608 MHz).

3. S_ID:
After 64 S-CLOCK cycles, the S_ID determines the end
of one sampling period.

A detailed timing diagram is shown in Fig. 4–6.

PRELIMINARY DAT A SHEET

(Data: MSB first)

S-Ident

S-Clock

S-Data

H

L
H

L
H

L

Section A

S-Ident

S-Clock

4.608 MHz

H

L

H

L

64 Clock Cycles

16 Bit Sound 1

A

16 Bit Sound 2 16 Bit Sound 3 16 Bit Sound 4

B

Section B

t

S6

S-Ident

t

S1

t

S4

t

S2

S-Clock

4.608 MHz

t

S5

H

L

t

S3

H

L

S-Data

H

L

LSB of Sound 1

Fig. 4–6: S-Bus timing diagram

S-Data

H

MSB of Sound 4

L

MICRONAS INTERMETALL14

PRELIMINARY DAT A SHEET

4.7. I2S Bus Interface

By means of this standardized interface, additional fea­ture processors can be connected to the MSP 3400C.
Two possible formats are supported: The standard
mode (MODE_REG[4]=0) selects the SONY format,
where the I2S_WS signal changes at the word bound­aries. The so-called PHILIPS format, which is character­ized by a change of the I2S_WS signal, one I2S_CL peri­od before the word boundaries, is selected by setting
MODE_REG[4]=1.

MSP 3400C

2

The I

S bus interface consists of five pins:

1. I2S_DA_IN1:
For input, two channels (2*16 bits) per sampling cycle
(32 kHz) are transmitted.

2. I2S_DA_IN2:
For input, two channels (2*16 bits) per sampling cycle
(32 kHz) are transmitted.

3. I2S_DA_OUT:
For output, two channels (2*16 bits) per sampling cycle
(32 kHz) are transmitted.

The MSP 3400C normally serves as the master on the

2

I

S interface. Here, the clock and word strobe lines are
driven by the MSP 3400C. By setting MODE_REG[3]=1,
the MSP 3400C is switched to a slave mode. Now, these
lines are input to the MSP 3400 C, and the master clock
is synchronized to 576 times the I2S_WS rate (32 kHz).
No D2MAC operation is possible in this mode.

Data: MSB first)

2

I

S_WS

SONY Mode SONY Mode

2

S_CL

I

I2S_DAIN

PHILIPS Mode

R LSB L MSB

PHILIPS/SONY Mode programmable by MODE_REG[4]

Detail A

16 bit left channel

4. I2S_CL:
Gives the timing for the transmission of I

2

(1.024 MHz).

5. I2S_WS:
The I2S_WS word strobe line defines the left and right
sample.

A detailed timing diagram is shown in Fig. 4–7.

F

I2SWS

PHILIPS Mode

Detail C

L LSB R MSB

16 bit right channel

S serial data

R LSB L LSB

2

S_DAOUT

I

R LSB L MSB

Detail C Detail A,B

2

I

S_CL

2

I

S_WS as INPUT

I2S_WS as OUTPUT

Detail B

16 bit left channel 16 bit right channel

F

I2SCL

T

I2SWS1

T

I2S5

T

I2SWS2

T

I2S6

L LSB R MSB

I2S_CL

2

I

S_DA_IN

I2S_DA_OUT

T

I2S1

T

I2S3

T

I2S2

T

I2S4

R LSB L LSB

Fig. 4–7: I2S Bus timing diagram

MICRONAS INTERMETALL 15

MSP 3400C

PRELIMINARY DAT A SHEET

5. I2C Bus Interface: Device and Subaddresses

As a slave receiver, the MSP 3400C can be controlled

2

via I

C bus. Access to internal memory locations is
achieved by subaddressing. The demodulator part and
the audio processor part (DFP) have two separate sub­addressing register banks.

In order to allow for more MSP 3400C ICs to be con­nected to the control bus, an ADR_SEL pin has been im­plemented. With ADR_SEL pulled to high, the MSP
3400C responds to changed device addresses, thus two
identical devices can be selected. Other devices of the
same family will have different subaddresses (e.g. 34x0)

By means of the RESET bit in the CONTROL register,
all devices with the same device address are reset.

The IC is selected by asserting a special device address
in the address part of an I

2

C transmission. A device ad­dress pair is defined as a write address (80 hex or 84
hex) and a read address (81 hex or 85 hex). Writing is
done by sending the device write address first, followed
by the subaddress byte, two address bytes, and two
data bytes. For reading, the read address has to be
transmitted first by sending the device write address (80
hex or 84 hex), followed by the subaddress byte, and two
address bytes. Without sending a stop condition, read­ing of the addressed data is done by sending the device
read address (81 hex or 85 hex) and reading two bytes

of data. Refer to Fig. 5–1 I

2

C Bus Protocol and section

5.2. Proposal for MSP 3400C I2C Telegrams.
Due to the internal architecture of the MSP 3400C, the

IC cannot react immediately to an I2C request. The typi­cal response time is about 0.3 ms. If the addressed pro­cessor is not ready for further transmissions on the I

2

bus, the clock line I2C_CL is pulled low. This puts the
current transmission into a wait state. After a certain pe­riod of time, the MSP 3400C releases the clock, and the
interrupted transmission is carried on.

2

The I

C Bus lines can be set tristate by switching the IC

into “Standby”-mode.
I2C-Bus error conditions:

In case of any internal error, the MSP’ s wait-period is ex­tended to 1.77 ms. Afterwards, the MSP does not ac­knowledge (NAK) the device address. The data line will
be left HIGH by the MSP, and the clock line will be re­leased. The master can then generate a STOP condition
to abort the transfer.

By means of NAK, the master is able to recognize the er­ror state and to reset the IC via I

2

C-Bus. While transmit­ting the reset protocol (section. 5.2.4.) to ‘CONTROL’,
the master must ignore the not acknowledge bits (NAK)
of the MSP.

A detailed timing diagram is shown in Fig. 5–1 and
Fig. 5–2.

C

Table 5–1: I

2

C Bus Device Addresses

ADR_SEL Low High Left Open
Mode Write Read Write Read Write Read

MSP device address 80 hex 81 hex 84 hex 85 hex 88 hex 89 hex

Table 5–2: I2C Bus Device and Subaddresses

Name Binary Value Hex Value Function

CONTROL 0000 0000 00 software reset
TEST1 0000 0001 01 only for internal use
TEST2 0000 0010 02 only for internal use
WR_DEM 0001 0000 10 write address demodulator
RD_DEM 0001 0001 11 read address demodulator
WR_DFP 0001 0010 12 write address DFP
RD_DFP 0001 0011 13 read address DFP
AGC 0001 1110 1E read AGC RMS
PLL_CAP 0001 1111 1F read / write PLL_Cap

MICRONAS INTERMETALL16

PRELIMINARY DAT A SHEET

Ç

Table 5–3: Control Register

Name 15 14..0

CONTROL RESET 0

5.1. Protocol Description

Write to DFP or Demodulator Part (long protocol)

MSP 3400C

S daw Wait ACK sub-addr ACK addr-byte

high

ACK addr-byte low ACK data-byte high ACK data-byte low ACK P

Read from DFP Part (long protocol)

S daw Wait ACK sub-addr ACK addr-byte

high

ACK addr-byte

low

ACK S dar Wait ACK data-byte

high

ACK data-byte

Ç

low

NAK P

Write to Control / Test / AGC / PLL_Cap Registers (short protocol)

S daw Wait ACK sub-addr ACK data-byte high ACK data-byte low ACK P

Read from Control / Test / AGC / PLL_Cap Registers (short protocol)

S daw Wait ACK sub-addr ACK S dar Wait ACK data-byte high

ACK data-byte low

NAK P

Note: S = I2C-Bus Start Condition from master

P = I2C-Bus Stop Condition from master
daw = Device Address Write
dar = Device Address Read
ACK = Acknowledge-Bit: LOW on I2C_DA from slave (= MSPC, grey)

or master (= CCU, hatched)

NAK = Not Acknowledge-Bit: HIGH on I2C_DA from master (= CCU, hatched) to indicate

‘End of Read’ or from MSPC indicating internal error state (not illustrated)

Wait = I

2

C-Clock line held low by the slave (= MSPC) while interrupt is serviced (<1.77 ms)

I2C_DA

1

0

SP

I2C_CL

Fig. 5–1: I2C bus protocol

(MSB first; data must be stable while clock is high)

MICRONAS INTERMETALL 17

MSP 3400C

PRELIMINARY DAT A SHEET

(Data: LSB first)

I2C_CL

T

I2C1

I2C_DA as input

2

C_DA as output

I

Fig. 5–2: I2C bus timing diagram

T

I2C5

T

IMOL2

T

I2C4

F

IM

T

I2C3

T

I2C6

T

IMOL1

T

I2C2

5.2. Proposal for MSP 3400C I2C Telegrams

5.2.1. Symbols

daw device address write
dar device address read
< Start Condition
> Stop Condition
aa Address Byte
dd Data Byte

5.2.2.

Write Telegrams

<daw 00 dd dd> software RESET
<daw 10 aa aa dd dd> write data into demodulator register
<daw 12 aa aa dd dd> write data into DFP register

5.2.3. Read Telegrams

<daw 11 aa aa <dar dd dd> read data from demodulator
<daw 13 aa aa <dar dd dd> read data from DSP

5.2.4. Examples

<daw 00 80 00> RESET MSPC statically
<daw 00 00 00> clear RESET
<daw 12 00 08 00 20> set loudspeaker channel source

to FM and Matrix to STEREO

MICRONAS INTERMETALL18

PRELIMINARY DAT A SHEET

5.3. Start Up Sequence

After power on or RESET, the IC is in an inactive state.
The CCU has to transmit the required coefficient set for
a given operation via the I
with the demodulator part. If required for any reason, the
audio processing part can be loaded before the demo­dulator part.

The reset pin should not be >0.45 DVSUP (see recom­mended operation conditions) before the 5 Volt digital
power supply (DVSUP) and the analog power supply
(AVSUP) are >4.75 Volt and the MSP-Clock is running
(Delay: 2 ms max, 0.5 ms typ.).

This means, if the reset low-high edge starts with a delay
of 2 ms after DVSUP>4.75 Volt and AVSUP>4.75 V olt,
even under worst case conditions, the reset is ok.

2

C bus. Initialization must start

MSP 3400C

DVSUP/V
AVSUP/V

4.75

Oscillator

RESETQ

0.45 * DVSUP

Fig. 5–3: Power-up sequence

max. 2

min. 2

time / ms

time / ms

time / ms

Note: The reset should
not reach high level be­fore the oscillator has
started. This requires a
reset delay of >2 ms

MICRONAS INTERMETALL 19

MSP 3400C

6. Programming the Demodulator Part

6.1. Registers: Table and Addresses

In Table 6–1, all Write Registers are listed.
All transmissions on the control bus are 16 bits wide.

Data for the demodulator part has 8 or 12 significant bits.
These data have to be inserted LSB bound and filled
with zero bits into the 16 bit transmission word. If chan­nel 1 or channel 2 is selected in the channel matrix while
any of the parameters are changed, the corresponding
output must be muted. Click and crack noise may occur
during coefficient changes. Table 4–1 explains how to
assign FM carriers to the MSPC-Sound IF channels and
the corresponding matrix modes in the audio processing
part.

PRELIMINARY DAT A SHEET

Table 6–1: MSP 3400C demodulator write registers

Register Protocol Write

Address
(hex)

AD_CV long 00BB input selection, configuration of AGC and Mute Function,

MODE_REG long 0083 mode register
FIR_REG_1

FIR_REG_2
DCO1_LO

DCO1_HI
DCO2_LO
DCO2_HI

PLL_CAP

Table 6–2: MSP 3400C demodulator read registers

1)

long
long

long
long
long
long

short 1F switchable PLL capacities

0001
0005

0093
009B
00A3
00AB

Function

and selection of A/D-converter

serial shift register for 6 ⋅ 8 bit, filter coefficient channel 1 (48 bit)
serial shift register for 6 ⋅ 8 bit, + 2 ⋅ 12 bit off set (total 72 bit)

increment channel 1 Low Part
increment channel 1 High Part
increment channel 2 Low Part
increment channel 2 High Part

Register Protocol Read

Address
(hex)

PLL_CAP
AGC_RMS
C_AD_BITS long 0023 A read from this address always responds with 0. This ensures

1)

The registers PLL_CAP and AGC_RMS are only available in MSP 3400C. In MSP 3410 and MSP 34x0D, this register

cannot be accessed.

1)

1)

short 1F switchable PLL capacities
short 1E RMS value, comparable with reference value

Function

software compatibility with the MSP 3410 readout. Reading 0 from
this register signals “No NICAM”.

MICRONAS INTERMETALL20

PRELIMINARY DAT A SHEET

6.2. Registers: Functions and Values

In the following, the functions of several registers are ex­plained and their (default) values are defined.

6.2.1. Setting of Parameter AD_CV

Table 6–3: AD_CV Register

AD_CV Bit Range Meaning Settings

AD_CV [0] not used must be set to 0

MSP 3400C

AD_CV [6:1] Reference level in case of Automatic Gain

see Table 6–5
Control = on.
Constant gain factor when Automatic Gain

see Table 6–6
Control = off .

AD_CV [7] Determination of Automatic Gain or Constant

Gain

0 = constant gain

1 = automatic gain

AD_CV [8] Selection of analog input 0 = ANALOG IN1

1 = ANALOG IN2

AD_CV [9] MSPC-Carrier-Mute Function 0 = off: no mute

1 = on: mute (see section 4.1.8.)

AD_CV [1 1–10] Programmable Carrier-Mute Level see Table 6–4
AD_CV [15–12] not used must be set to 0

Table 6–4: Carrier Mute Level

Step AD_CV [11:10]

binary

0
1
2
3

00
01
10
11

AD_CV [11:10]
decimal

0
1
2
3

Internal reference level for mute active
(dBr: relative to MSP 3410 )

0 dBr
–3 dBr
–6 dBr

–12 dBr

Table 6–5: Reference values AD_CV [6:1] for active AGC (AD_CV[7] = 1)

Application Input Signal Contains Ref. Value

binary

Ref. Value
decimal

Range of Input Signal
at pin ANA_IN_1+ and
ANA_IN_2+

Terrestrial TV 2 FM Carriers 101000 40 0.14 – 3 V
SAT 1 or more FM Carriers 100011 35 0.14 – 3 V
ADR 1 or more FM Carriers and

010100 20 0.14 – 3 V

pp

pp

pp

1)

1)

1)

1 or more ADR Carriers

1)

For signals above 1.4 Vpp, the minimum gain of 3 dB is switched and overflow of the AD converter may result. Due
to the robustness of the internal processing in FM mode, the IC works properly up to and even more than 3 Vpp. In AM
mode, of course, no AD converter overflow is allowed. As a consequence, in the AM-mode, the maximum input at pins
41 or 43 must not exceed 1.4 Vpp.

MICRONAS INTERMETALL 21

MSP 3400C

Table 6–6: AD_CV parameters for constant input gain (AD_CV[7]=0)

PRELIMINARY DAT A SHEET

Step AD_CV [6:1]

Gain Input Level at pin ANA_IN1+ and ANA_IN2+

Constant Gain

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

1)

For signals above 1.4 Vpp, the minimum gain of 3 dB is switched and overflow of the AD converter may result. Due

000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100

3.00 dB

3.85 dB

4.70 dB

5.55 dB

6.40 dB

7.25 dB

8.10 dB

8.95 dB

9.80 dB

10.65 dB

11.50 dB

12.35 dB

13.20 dB

14.05 dB

14.90 dB

15.75 dB

16.60 dB

17.45 dB

18.30 dB

19.15 dB

20.00 dB

maximum input level1): 3 Vpp (FM) or 1.4 V

maximum input level: 0.14 V

pp

1)

pp

(AM)

to the robustness of the internal processing in FM mode, the IC works properly up to and even more than 3 Vpp. In AM
mode, of course, no AD converter overflow is allowed. As a consequence, in the AM-mode, the maximum input at pins
41 or 43 must not exceed 1.4 Vpp.

MICRONAS INTERMETALL22

PRELIMINARY DAT A SHEET

MSP 3400C

6.2.2. Control Register ‘MODE_REG’

The register ‘MODE_REG’ contains the control bits de­termining the operation mode of the MSP 3400C; Table
6–7 explains all bit positions.

Table 6–7: Control word ‘MODE_REG’: All bits are “0” after power-on-reset

Bit Function Comment Definition Recom-

mendation

[0] DMA_SYNC

1)

Synchronization to DMA 0 : off

X

1 : on

[1] DCTR_TRI Digital control out 0/1 tristate 0 : active

0

1 : tristate

[2] I2S_TRI I2S outputs tristate (I2S_CL,

I2S_WS, I2S_DA_OUT)

[3] I2S Mode

1)

Master/Slave mode of the

2

I

S bus

[4] I2S_WS Mode WS due to the Sony or

Philips-Format

[5] Audio_CL_OUT switch Audio_Clock_Output

to tristate

0 : active
1 : tristate

0 : Master
1 : Slave

0 : Sony
1 : Philips

0 : on
1 : tristate

0

X

X

X

[6] not used must be 0 0
[7] FM1 FM2 MSPC-channel 1 mode s.Table 6–8
[8] AM MSPC-channel 1/2 mode 0 : FM

s.Table 6–8

1 : AM

[9] HDEV High Deviation Mode

(channel matrix must be

0 : normal mode
1 : high deviation mode

s.Table 6–8

sound A )
[10] not used must be 1 1
[11] S-Bus Mode

2)

mode of Pins S_CL and S_ID 0 : Tristate

0

1 : Active

[12] FM2 FIR Filter Gain

(FM2 = Ch1)

[13] FM2 FIR Filter Coeff. Set

(FM2 = Ch1)

[14] ADR Mode of ADR Interface 0 : normal mode

see table 6–10 0 : Gain = 6 dB

1 : Gain = 0 dB

see table 6–10 0 : use FIR_REG_1

1 : use FIR_REG_2

0

0

X

1 : ADR mode

[15] AM-Gain additional gain in AM-mode 0 : 0 dB

0

1 : +12 dB

1)

In case of synchronization to DMA, no I2S-slave mode possible.
In case of I2S-slave mode, no synchronization to DMA allowed. I2S-Slave mode dominates.

2)

The normal operation mode is ‘Tristate’; SBUS is only used in conjunction with DMA.

X:Depend­ing on mode

MICRONAS INTERMETALL 23

MSP 3400C

Table 6–8: Channel modes ‘MODE_REG [7–9]‘

PRELIMINARY DAT A SHEET

FM1 FM2
bit[7]

AM
bit[8]

HDEV
bit[9]

channel 1 channel 2

0 0 0 mute FM-Mono (FM1)
1 0 0 FM2 FM1
X 1 0 AM AM
X X 1 FM-Mono (high deviation) FM-Mono (high deviation)

6.2.3. FIR-Filter Switches

To simplify programming of the MSP 3400C, two addi­tional switches have been implemented.

Table 6–9: Loading sequence for FIR-coefficients

WRITE_ADR = FIR_REG_1(Channel 1: FM2)
No. Symbol Name Bits Value

The FIR filter for channel1/FM2 can use either
FIR_REG_1 coefficients or FIR_REG_2 coefficients by
means of MODE_REG[13]. Herewith, it is no longer nec­essary to transmit both coefficient sets in FM-terrestrial
mode. The loading sequence for FIR_REG_2 is suffi-

1 FM2_Coeff. (5) 8 see Table 6–10.
2 FM2_Coeff. (4) 8

3 FM2_Coeff. (3) 8

cient.

4 FM2_Coeff. (2) 8

The additional gain of +6 dB in channel1/FM2 can be
switched to 0 dB by means of MODE_REG[12]. T ogeth­er with MODE_REG[13] set to 1, in satellite mode, it is
no longer necessary to transmit both FIR filter coefficient

5 FM2_Coeff. (1) 8
6 FM2_Coeff. (0) 8

sets. The loading sequence for FIR_REG_2 is sufficient.

WRITE_ADR = FIR_REG_2 (Channel 2: FM1/FM

6.2.4. FIR-Parameter

mono)
No. Symbol Name Bits Value

The following data values (see Table 6–9) are to be
transferred 8 bits at a time embedded LSB-bound in
a 16 bit word. These sequences must be obeyed. To
change a coefficient set, the complete block
FIR_REG_1 or FIR_REG_2 must be transmitted. The
new coefficient set will be active without a load_reg rou-

1 * IMREG1 (8 LSBS) 8 04 HEX
2 * IMREG1 / IMREG2

(4 MSBs / 4 LSBs)

3 * IMREG2 (8 MSBs) 8 00 HEX

8 40 HEX

tine.

4 FM_Coef (5) 8 see Table 6–10.
5 FM_Coef (4) 8

6 FM_Coef (3) 8
7 FM_Coef (2) 8
8 FM_Coef (1) 8
9 FM_Coef (0) 8
* IMREG_1/2: Two 12-bit off-set constants

MICRONAS INTERMETALL24

PRELIMINARY DAT A SHEET

MSP 3400C

Table 6–10: 8-bit FIR-coefficients (decimal integer) for MSP 3410D; reset status: all coefficients are “0”

Coefficients for FIR1 0001

Terrestrial TV-Standards FM - Satellite

B/G-,D/K-,M-Dual FM 130 kHz 180 kHz 200 kHz 280 kHz 380 kHz 500 kHz Autosearch

Coef(i) FIR2 FIR2 FIR2 FIR2 FIR2 FIR2 FIR2 FIR2
0 3 73 9 3 –8 –1 –1 75
1 18 53 18 18 –8 –9 –1 19
2 27 64 28 27 4 –16

3 48 119 47 48 6 5 2 35
4 66 101 55 66 78 65 59 39
5 72 127 64 72 107 123 126 40
MODE-REG[12] 0 1 1 1 1 1 1 0
MODE-REG[13] 1 1 1 1 1 1 1 0

MODE_REG[12] should be set to 0 (= 6 dB gain) if the level of the FM2-carrier processed in MSP-Ch1 is appr. 7 dB below the FM1-carrier of
MSP-Ch2. If both carriers have the same level, MODE_REG[12] must be set to 1 (=0 dB gain).

and FIR2 0005

hex

hex

FIR filter corresponds to a
bandpass with a band­width of B = 130 to 500 kHz

B

frequencyf

c

–8

36

MODE_REG[13]: If in MSP-Channel 1 and 2 the same bandwidth is required, it is sufficient to transmit FIR_REG2 only and to set
MODE_REG[13] to 1.

For compatibility (besides the above programming), the FIR-filter programming as used for the MSP 3410B is also possible.
ADR coefficients are listed in the DRP-data sheet.
The 130 kHz coefficients are based on subcarriers, which are 7 dB below an existent main carrier.

MICRONAS INTERMETALL 25

MSP 3400C

6.2.5. DCO-Increments

For a chosen TV standard, a corresponding set of 24-bit
increments determining the mixing frequencies of the
quadrature mixers, has to be written into the IC. In T able
6–11, several examples of DCO increments are listed.
It is necessary to divide them into low part and high part.
The formula for the calculation of the increments for any
chosen IF-Frequency is as follows:

PRELIMINARY DAT A SHEET

INCR
with: int = integer function

Conversion of INCR into hex-format and separation of
the 12-bit low and high parts lead to the required incre­ments. (DCO1_HI or _LO for channel 1, DCO2_HI or LO
for channel 2).

Table 6–11: DCO increments for the MSP 3400C; frequency in MHz, increments in Hex

= int(f/fs ⋅ 224)

dez

f = IF-frequency in MHz
fS= sampling frequency (18.432 MHz)

Frq. MHz DCO_HI DCO_LO Frq. MHz DCO_HI DCO_LO

4.5 03E8 0000

5.04

5.5

5.58

5.7421875

6.0

6.2

6.5

6.552

0460
04C6
04D8
04FC

0535
0561
05A4
05B0

0000
038E
0000
00AA

0555
0C71
071C
0000

5.76

5.85

5.94

6.6

6.65

6.8

0500
0514
0528

05BA
05C5
05E7

0000
0000
0000

0AAA
0C71
01C7

7.02 0618 0000 7.2 0640 0000

7.38 0668 0000 7.56 0690 0000

MICRONAS INTERMETALL26

PRELIMINARY DAT A SHEET

MSP 3400C

6.3. Sequences to Transmit Parameters and to Start
Processing

After having been switched on, the MSPC must be ini­tialized by transmitting the parameters according to the
LOAD_SEQ_1/2 of T able 6–12. In the MSPC, the initial­ization sequence must no longer be terminated by trans­mitting LOAD_REG_1/2. The transmitted data are ac­tive as soon as the corresponding I
finished. Therefore, while changing parameters of the
demodulator section, a mute is recommended for the af­fected channel (LOAD_SEQ_1/2: mute all FM,
LOAD_SEQ_1: switch audio processing to chan­nel2/FM1 or mute channel1/FM2). Otherwise, distorted
sound may occur while switching.

For FM-stereo operation, the evaluation of the identifica­tion signal must be performed. For positive identification
check, the MSP 3400C sound channels have to be
switched corresponding to the detected operation
mode.

2

C telegram has

6.4. Software Proposals for Multistandard TV-Sets

To familiarize the reader with the programming scheme
of the MSP 3400C, two examples in the shape of flow
diagrams are shown in the following sections.

6.4.1. Multistandard System B/G German DUAL FM

Fig. 6–1 shows a flow diagram for the CCU software,
applied for the MSP 3400C in a TV set, which facilitates
all standards according to System B/G. For the instruc­tions used in the diagram, please refer to Table 6–12.

After having switched on the TV-set and having initial­ized the MSP 3400C (LOAD_SEQ_1/2), FM-mono
sound is available.

Fig. 6–1 shows how to check for any stereo or bilingual
audio information in channel 1. If successful, the
MSP 3400C must be switched to the desired audio
mode.

Table 6–12: Sequences to initialize and start the MSP 3400C

LOAD_SEQ_1/2: General Initialization

1. AD_CV

2. FIR_REG_1

3. FIR_REG_2

4. MODE_REG

5. DCO1_LO

6. DCO1_HI

7. DCO2_LO

8. DCO2_HI

FM_IDENT_CHECK: Decoding of the identification signal

1. Evaluation of the stereo detection register (DFP register 0018

2. If necessary, switch the corresponding sound channels within the audio processing part

LOAD_SEQ_1: Reinitialization of Channel 1 without affecting Channel 2

1. FIR_REG_1

2. MODE_REG

3. DCO1_LO

4. DCO1_HI

(6 ⋅ 8 bit)
(12 bit)
(12 bit)

, high part)

hex

MICRONAS INTERMETALL 27

MSP 3400C

PRELIMINARY DAT A SHEET

Pause

START

LOAD_SEQ_1/2

Channel 1:

FM2 Parameter

Channel 2:

FM1 Parameter

Audio Processing Init

Bilingual

Set FM Matrix:

To NO_MATRIX

Set Channel Matrix:

To SOUND A or B

Mono

Set FM Matrix:

To NO_MATRIX

Set Channel Matrix:

To SOUNDA

Stereo

Set FM Matrix:

To G/KMATRIX

Set Channel Matrix:

To STEREO

< –t

IDENT_CHECK

0x0018

> –t & < t

> t

FM_

6.4.3. Automatic Search Function for FM-Carrier De­tection

The AM demodulation ability of the MSP 3400C offers
the possibility to calculate the “field strength” of the mo­mentarily selected FM carrier, which can be read out by
the CCU. In SAT receivers, this feature can be used to
make automatic FM carrier search possible.

Therefore, the MSPC has to be switched to AM-mode
(MODE_REG[8]), FM-Prescale must be set to
7F

=+127

hex

off. The sound-IF frequency range must now be
“scanned” in the MSPC-channel 2 by means of the pro­grammable quadrature mixer with an appropriate incre­mental frequency (i.e. 10 kHz).

After each incrementation, a field strength value is avail­able at the quasi-peak detector output (quasi-peak de­tector source must be set to FM), which must be ex­amined for relative maxima by the CCU. This results in
either continuing search or switching the MSP 3400C
back to FM demodulation mode.

During the search process, the FIR_REG_2 must be
loaded with the coefficient set “AUTOSEARCH”, which
enables small bandwidth, resulting in appropriate field
strength characteristics. The absolute field strength val­ue (can be read out of “quasi peak detector output FM1”)
also gives information on whether a main FM carrier or
a subcarrier was detected, and as a practical conse­quence, the FM bandwidth (FIR_REG_1/2) and the
deemphasis (50 µs or adaptive) can be switched auto­matically.

, and the FM DC Notch must be switched

dez

Fig. 6–1: CCU software flow diagram: Standard B/G,
t = threshold value for stereo/bilingual detection

START

LOAD_SEQ_1/2
MSP-Channel 1:

FM2-Parameter

MSP-Channel 2:

FM1-Parameter

Audio Processing Init

STOP

Fig. 6–2: CCU software flow diagram: SAT-mode

6.4.2. Satellite Mode

Fig. 6–2 shows the simple flow diagram to be used for
the MSP 3400C in a satellite receiver. For FM-mono
operation, the corresponding FM carrier should prefer­ably be processed at the MSPC-channel 2 or at the
MSPC-channel 1 with FIR gain = 0 dB.

Due to the fact that a constant demodulation frequency
offset of a few kHz, leads to a DC-level in the demodu­lated signal, a further fine tuning of the found carrier can
be achieved by evaluating the “DC Level Readout FM1”.
Therefore, the FM DC Notch must be switched on, and
the demodulator part must be switched back to FM-de­modulation mode.

For a detailed description of the automatic search func­tion, please refer to the corresponding MSP 3400C Win­dows software.

Note: The automatic search is still possible by evaluat­ing only the DC Level Readout FM1 (DC Notch On) as
it is described with the MSP 3410, but the above men­tioned method is faster.

6.4.4. Automatic Standard Detection

The AM demodulation ability of the MSP 3400 C en­ables a simple method of deciding between standard
B/G (FM-carrier at 5.5 MHz) and standard I (FM-carrier
at 6.0 MHz). It is achieved by tuning the MSP 3400C in
the AM-mode to the two discrete frequencies and eva­luating the field strength via the DC level register or the
quasi-peak detector output (Mode_Reg, DC Notch, FM
Prescale as described in section 6.4.3.).

MICRONAS INTERMETALL28

PRELIMINARY DAT A SHEET

7. Programming the Audio Processing Part

7.1. Summary of the DSP Control Registers

Control registers are 16 bit wide. Transmissions via I

2

bus have to take place in 16 bit words. Single data en­tries are 8 bit. Some of the defined 16 bit words are di­vided into low and high byte, thus holding two different
control entities. All control registers are readable.
Note: Unused parts of the 16 bit registers must be zero.

Table 7–1: DSP Control Registers

MSP 3400C

C

Name I2C Bus

Address

Volume loudspeaker channel 0000
Volume / Mode loudspeaker channel L 1/8 dB Steps, Reduce Volume / Tone Control 00
Balance loudspeaker channel [L/R] 0001

High/

Adjustable Range, Operational Modes Reset Mode

Low

H [+12 dB ... –114 dB, MUTE] MUTE

hex

H [0..100 / 100 % and vv][–127..0 / 0 dB and vv]

hex

hex

100%/100%

Balance Mode loudspeaker L [Linear mode / logarithmic mode] linear mode
Bass loudspeaker channel 0002
Treble loudspeaker channel 0003
Loudness loudspeaker channel 0004
Loudness Filter Characteristic
Spatial effect strength loudspeaker ch. 0005

H [+20 dB ... –12 dB] 0 dB

hex

H [+15 dB ... –12 dB] 0 dB

hex

H [0 dB ... +17 dB] 0 dB

hex

L [NORMAL, SUPER_BASS] NORMAL
H [–100%...OFF...+100%] OFF

hex

Spatial effect mode/customize L [SBE, SBE+PSE] SBE+PSE
Volume headphone channel 0006
Volume / Mode headphone channel L 1/8 dB Steps, Reduce Volume / Tone Control 00
Volume SCAR T channel 0007

H [+12 dB ... –114 dB, MUTE] MUTE

hex

hex

H [00

hex

... 7F

],[+12 dB ... –1 14 dB, MUTE] 00

hex

hex

hex

Volume / Mode SCAR T channel L [Linear mode / logarithmic mode] linear mode
Loudspeaker channel source 0008

H [FM, NICAM, SCART, I2S1, I2S2] FM

hex

Loudspeaker channel matrix L [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA
Headphone channel source 0009

H [FM, NICAM, SCART, I2S1, I2S2] FM

hex

Headphone channel matrix L [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA
SCART1 channel source 000a

H [FM, NICAM, SCART, I2S1, I2S2] FM

hex

SCART1 channel matrix L [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA
I2S channel source 000b

H [FM, NICAM, SCART, I2S1, I2S2] FM

hex

I2S channel matrix L [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA
Quasi-peak detector source

000c

hex

H

[FM, NICAM, SCART, I2S1, I2S2]

FM
Quasi-peak detector matrix L [SOUNDA, SOUNDB, STEREO, MONO...] SOUNDA
Prescale SCART 000d
Prescale FM 000e

hex

hex

H [00
H [00

hex

hex

... 7F
... 7F

] 00

hex

] 00

hex

hex

hex

FM matrix L [NO_MAT, GSTEREO, KSTEREO] NO_MAT

MICRONAS INTERMETALL 29

MSP 3400C

PRELIMINARY DAT A SHEET

Name

I2C Bus
Address

Deemphasis FM 000f

hex

Low

H [OFF , 50 µs, 75 µs, J17] 50 µs

Reset ModeAdjustable Range, Operational ModesHigh/

Adaptive Deemphasis FM L [OFF, WP1] OFF
Prescale I2S2 0012
ACB Register (SCART Switches and

0013

H [00

hex

H/L Bits [15..0] 00

hex

hex

... 7F

] 10

hex

DIG_OUT Pins)
Beeper 0014
Identification Mode 0015
Prescale I2S1 0016
FM DC Notch 0017
Mode Tone Control 0020
Equalizer loudspeaker ch. band 1 0021
Equalizer loudspeaker ch. band 2 0022
Equalizer loudspeaker ch. band 3 0023
Equalizer loudspeaker ch. band 4 0024
Equalizer loudspeaker ch. band 5 0025

H/L [00

hex

L [B/G, M] B/G

hex

H [00

hex

L [ON, OFF] ON

hex

H [BASS/TREBLE, EQUALIZER] BASS/TREB

hex

H [+12 dB ... –12 dB] 0 dB

hex

H [+12 dB ... –12 dB] 0 dB

hex

H [+12 dB ... –12 dB] 0 dB

hex

H [+12 dB ... –12 dB] 0 dB

hex

H [+12 dB ... –12 dB] 0 dB

hex

hex

hex

... 7F

... 7F

]/[00

hex

hex

... 7F

hex

] 10

] 0/0

hex

hex

hex

hex

Automatic Volume Correction 0029

H [off, on, decay time] off

hex

Volume Subwoofer channel 002Chex H [0dB ... –30 dB, mute] 0 dB
Subwoofer Channel Corner Frequency 002Dhex H [50 Hz ... 400 Hz]
Subwoofer: Complementary Highpass L [off, on] off
Balance headphone channel [L/R] 0030

H [0...100 / 100% and vv][–127...0 / 0 dB and vv]

hex

100%/100%

Balance Mode headphone L [Linear mode / logarithmic mode] linear mode
Bass headphone channel 0031
Treble headphone channel 0032
Loudness headphone channel 0033

H [+20 dB ... –12 dB] 0 dB

hex

H [+15 dB ... –12 dB] 0 dB

hex

H [0 dB ... +17 dB] 0 dB

hex

Loudness filter characteristic L [NORMAL, SUPER_BASS] NORMAL
Note: For compatibility to new technical codes of the MSP 3400C, please consider the following compatibility restrictions:

If adaptive deemphasis is switched on, 75 µs deemphasis must be activated.

MICRONAS INTERMETALL30

PRELIMINARY DAT A SHEET

MSP 3400C

7.1.1. Volume Loudspeaker Channel and Head­phone Channel

Volume

0000

hex

11 MSBs

loudspeaker
Volume

0006

hex

11 MSBs

headphone

+12 dB 0111 1111 000x 7F0
+11.875 dB 0111 1110 111x 7EE

+0.125 dB 0111 0011 001x 732
0 dB 0111 0011 000x 730
–0.125 dB 0111 0010 1 11x 72E

–113.875dB 0000 0001 001x 012
–114 dB 0000 0001 000x 010
Mute 0000 0000 xxxx 00x

hex

hex

hex

hex

hex

hex

hex

hex

RESET

Fast Mute 1111 1111 111x FFE

hex

Clipping Mode

0000

hex

3 LSBs

loudspeaker
Clipping Mode

0006

hex

3 LSBs

headphone

Reduce Volume x000 0

hex

RESET
Reduce Tone Control x001 1
Compromise Mode x010 2

hex

hex

If the clipping mode is set to “Reduce Volume”, the fol­lowing clipping procedure is used: To prevent severe
clipping effects with bass, treble, or equalizer boosts, the
internal volume is automatically limited to a level where,
in combination with either bass, treble, or equalizer set­ting, the amplification does not exceed 12 dB.

If the clipping mode is “Reduce Tone Control”, the bass
or treble value is reduced if amplification exceeds 12 dB.
If the equalizer is switched on, the gain of those bands
is reduced, where amplification together with volume ex­ceeds 12 dB.

The highest given positive 1 1-bit number (7F0

hex

) yields
in a maximum possible gain of 12 dB. Decreasing the
volume register by 1 LSB decreases the volume by

0.125 dB. Volume settings lower than the given mini­mum mute the output. With large scale input signals,
positive volume settings may lead to signal clipping.

With Fast Mute, volume is reduced to mute position by
digital volume only . Analog volume is not changed. This
reduces any audible DC plops. Going back from Fast
Mute should be done to the volume step before Fast
Mute was activated.

If the clipping mode is “Compromise Mode”, the bass or
treble value and volume are reduced half and half if am­plification exceeds 12 dB (see example below). If the
equalizer is switched on, the gain of those bands is re­duced half and half, where amplification together with
volume exceeds 12 dB.

Example: Vol.:

+6 dB

Bass:
+9 dB

Treble:
+5 dB

Red. Volume 3 9 5
Red. Tone Con. 6 6 5
Compromise 4.5 7.5 5

MICRONAS INTERMETALL 31

MSP 3400C

PRELIMINARY DAT A SHEET

7.1.2. Balance Loudspeaker and Headphone
Channel

Positive balance settings reduce the left channel without
affecting the right channel; negative settings reduce the
right channel leaving the left channel unaffected. In lin­ear mode, a step by 1 LSB decreases or increases the
balance by about 0.8% (exact figure: 100/127). In loga­rithmic mode, a step by 1 LSB decreases or increases
the balance by 1 dB.

Balance Mode

0001

hex

LSB

loudspeaker
Balance Mode

0030

hex

LSB

headphone

linear xxx0 0

hex

RESET

logarithmic xxx1 1

hex

Linear Mode

Logarithmic Mode

Balance loudspeaker

0001

hex

H

channel [L/R]
Balance headphone

0030

hex

H

channel [L/R]

Left –127 dB, Right 0 dB 0111 1111 7F
Left –126 dB, Right 0 dB 0111 1110 7E

Left –1 dB, Right 0 dB 0000 0001 01
Left 0 dB, Right 0 dB 0000 0000 00

RESET

Left 0 dB, Right –1 dB 1111 1111 FF
Left 0 dB, Right –127 dB 1000 0001 81

Left 0 dB, Right –128 dB 1000 0000 80

hex

hex

hex

hex

hex

hex

hex

Balance loudspeaker

0001

hex

H

channel [L/R]
Balance headphone

0030

hex

H

channel [L/R]

Left muted, Right 100% 0111 1111 7F
Left 0.8%, Right 100% 0111 1110 7E

Left 99.2%, Right 100% 0000 0001 01
Left 100%, Right 100% 0000 0000 00

RESET

Left 100%, Right 99.2% 1111 1111 FF
Left 100%, Right 0.8% 1000 0010 82

Left 100%, Right muted 1000 0001 81

hex

hex

hex

hex

hex

hex

hex

MICRONAS INTERMETALL32

PRELIMINARY DAT A SHEET

MSP 3400C

7.1.3. Bass Loudspeaker and Headphone Channel

Bass loudspeaker 0002
Bass headphone 0031

hex

hex

+20 dB 0111 1111 7F
+18 dB 0111 1000 78
+16 dB 0111 0000 70
+14 dB 0110 1000 68
+12 dB 0110 0000 60
+11 dB 0101 1000 58

+1 dB 0000 1000 08
+1/8 dB 0000 0001 01

0 dB 0000 0000 00

H
H

hex

hex

hex

hex

hex

hex

hex

hex

hex

RESET

–1/8 dB 1111 1111 FF

hex

7.1.4. Tr e bl e Loudspeaker and Headphone Channel

Treble loudspeaker 0003
Treble headphone 0032

hex

hex

+15 dB 0111 1000 78
+14 dB 0111 0000 70

+1 dB 0000 1000 08
+1/8 dB 0000 0001 01

0 dB 0000 0000 00

H
H

hex

hex

hex

hex

hex

RESET

–1/8 dB 1111 1111 FF
–1 dB 1111 1000 F8
–11 dB 1010 1000 A8

–12 dB 1010 0000 A0

hex

hex

hex

hex

–1 dB 1111 1000 F8
–11 dB 1010 1000 A8

–12 dB 1010 0000 A0

hex

hex

hex

With positive bass settings, internal overflow may occur
even with overall volume less than 0 dB. This will lead to
a clipped output signal. Therefore, it is not recom­mended to set bass to a value that, in conjunction with
volume, would result in an overall positive gain.

Loudspeaker channel: Bass and Equalizer cannot work
simultaneously (see Table: Mode Tone Control). If
Equalizer is used, Bass and Treble coef ficients must be
set to zero and vice versa.

With positive treble settings, internal overflow may occur
even with overall volume less than 0 dB. This will lead to
a clipped output signal. Therefore, it is not recom­mended to set treble to a value that, in conjunction with
volume, would result in an overall positive gain.

Loudspeaker channel: Treble and Equalizer cannot
work simultaneously (see Table: Mode T one Control). If
Equalizer is used, Bass and Treble coef ficients must be
set to zero and vice versa.

MICRONAS INTERMETALL 33

MSP 3400C

PRELIMINARY DAT A SHEET

7.1.5. Loudness Loudspeaker and Headphone
Channel

Loudness

0004

hex

H

loudspeaker
Loudness

0033

hex

H

headphone

+17 dB 0100 0100 44
+16 dB 0100 0000 40

+1 dB 0000 0100 04
0 dB 0000 0000 00

hex

hex

hex

hex

RESET

Mode Loudness

0004

hex

L

loudspeaker
Mode Loudness

0033

hex

L

headphone

Normal (constant
volume at 1 kHz)

Super Bass (constant

0000 0000 00
RESET

0000 0100 04

hex

hex

volume at 2 kHz)

7.1.6. Spatial Effects Loudspeaker Channel

Spatial effect strength

0005

hex

loudspeaker channel

Enlargement 100% 0111 1111 7F
Enlargement 50% 0011 1111 3F

Enlargement 1.5% 0000 0001 01
Effect off 0000 0000 00

RESET

Reduction 1.5% 1111 1111 FF
Reduction 50% 1100 0000 C0
Reduction 100% 1000 0000 80

Spatial Effect Mode 0005

Stereo Basewidth En­largement (SBE) and
Pseudo Stereo Effect

hex

0000 0
RESET
0000 0

(PSE). (Mode A)
Stereo Basewidth En-

0010 2
largement (SBE) only.
(Mode B)

Spatial Effect Cus-

0005

hex

tomize Coefficient

H

hex

hex

hex

hex

hex

hex

hex

[7:4]

hex

hex

hex

[3:0]

Loudness increases the volume of low and high frequen­cy signals, while keeping the amplitude of the 1 kHz ref­erence frequency constant. The intended loudness has
to be set according to the actual volume setting. Be­cause loudness introduces gain, it is not recommended
to set loudness to a value that ,in conjunction with vol­ume, would result in an overall positive gain.

By means of ‘Mode Loudness’, the corner frequency for
bass amplification can be set to two different values. In
Super Bass mode, the corner frequency is shifted up.
The point of constant volume is shifted from 1 kHz to
2 kHz.

max high pass gain 0000 0

hex

RESET
2/3 high pass gain 0010 2
1/3 high pass gain 0100 4
min high pass gain 0110 6
automatic 1000 8

hex

hex

hex

hex

There are several spatial effect modes available:
Mode A (low byte = 00

) is compatible to the formerly

hex

used spatial effect. Here, the kind of spatial effect de­pends on the source mode. If the incoming signal is in
mono mode, Pseudo Stereo Effect is active; for stereo
signals, Pseudo Stereo Effect and Stereo Basewidth
Enlargement is effective. The strength of the effect is
controllable by the upper byte. A negative value reduces
the stereo image. A rather strong spatial effect is recom­mended for small TV sets where loudspeaker spacing is
rather close. For large screen TV sets, a more moderate
spatial effect is recommended. In mode A, even in case
of stereo input signals, Pseudo Stereo Effect is active,
which reduces the center image.

In Mode B, only Stereo Basewidth Enlargement is effec­tive. For mono input signals, the Pseudo Stereo Effect
has to be switched on.

MICRONAS INTERMETALL34

PRELIMINARY DAT A SHEET

MSP 3400C

It is worth mentioning, that all spatial effects affect ampli­tude and phase response. With the lower 4 bits, the fre­quency response can be customized. A value of 0000

bin

yields a flat response for center signals (L = R) but a high
pass function of L or R only signals. A value of 0110

bin

has a flat response for L or R only signals but a lowpass
function for center signals. By using 1000

, the fre-

bin

quency response is automatically adapted to the sound
material by choosing an optimal high pass gain.

7.1.7. Volume SCART

Volume Mode SCART 0007

hex

linear xxx0 0

LSB

hex

RESET

logarithmic xxx1 1

hex

Linear Mode
V olume SCART 0007

hex

H

7.1.8. Channel Source Modes

Loudspeaker channel

0008

hex

source
Headphone channel

0009

hex

source
SCART channel

000a

hex

source
I2S channel source 000b
Quasi-peak detector

000c

hex

hex

source

FM 0000 0000 00

RESET

NONE

(MSP3410: NICAM)

0000 0001 01
SCART 0000 0010 02
SBUS12 0000 0011 03
SBUS34 0000 0100 04

H

H

H

H
H

hex

hex

hex

hex

hex

OFF 0000 0000 00

RESET

0 dB gain

0100 0000 40
(digital full scale (FS)
to 2 V

+6 dB gain (–6 dBFS
to 2 V

RMS

RMS

output)

0111 1111 7F

output)

Logarithmic Mode
V olume SCART 0007

hex

11 MSBs

+12 dB 0111 1111 000x 7F0
+11.875 dB 0111 1110 111x 7EE

+0.125 dB 0111 0011 001x 732
0 dB 0111 0011 000x 730
–0.125 dB 0111 0010 111x 72E

–113.875 dB 0000 0001 001x 012

hex

hex

hex

hex

hex

hex

hex

hex

hex

I2S1 0000 0101 05
I2S2 0000 0110 06

hex

hex

Note: For Headphone output it is also possible to select
a subwoofer signal derived from the Loudspeaker chan­nel. For more details see section 7.1.23.

–114 dB 0000 0001 000x 010
Mute 0000 0000 0000 000

hex

hex

RESET

MICRONAS INTERMETALL 35

MSP 3400C

PRELIMINARY DAT A SHEET

7.1.9. Channel Matrix Modes (see also Table 4–1)

Loudspeaker channel

0008

hex

L

matrix
Headphone channel

0009

hex

L

matrix
SCART channel

000a

hex

L

matrix
I2S channel matrix 000b
Quasi-peak detector-

000c

hex

hex

L
L

matrix

SOUNDA / LEFT /
MSP-IF-CHANNEL2

SOUNDB / RIGHT /

0000 0000 00
RESET

0001 0000 10

hex

hex

MSP-IF-CHANNEL1
STEREO 0010 0000 20
MONO 001 1 0000 30
SUM/DIFF 0100 0000 40
AB_XCHANGE 0101 0000 50
INVERT_B 0110 0000 60

hex

hex

hex

hex

hex

The sum/difference mode can be used together with the
quasi-peak detector to determine the sound material
mode. If the difference signal on channel B (right) is near
to zero, and the sum signal on channel A (left) is high,
the incoming audio signal is mono. If there is a significant
level on the difference signal, the incoming audio is ste­reo.

7.1.10. SCART Prescale

7.1.11. FM Prescale

Volume Prescale FM

000e

hex

(normal FM mode)

OFF 0000 0000 00

RESET

Maximum Volume
(28 kHz deviation

1)

0111 1111 7F

recommended FIR­bandwidth: 130 kHz)

Deviation 50 kHz

1)

0100 1000 48
recommended FIR­bandwidth: 200 kHz

Deviation 75 kHz

1)

0011 0000 30
recommended FIR­bandwidth: 200 or
280 kHz

Deviation 150 kHz

1)

0001 1000 18
recommended FIR­bandwidth: 380 kHz

Maximum deviation

0001 0011 13
192 kHz1)
recommended FIR­bandwidth: 380 kHz

Prescale for adaptive

0001 0000 10
deemphasis WP1
recommended FIR­bandwidth: 130 kHz

Volume Prescale FM

000e

hex

(High Deviation
Mode)

Deviation 150 kHz

1)

0011 0000 30
recommended FIR­bandwidth: 380 kHz

H

hex

hex

hex

hex

hex

hex

hex

H

hex

V olume Prescale

000d

hex

H

SCART

OFF 0000 0000 00

RESET

0 dB gain (2 V

RMS

in-

0001 1001 19

put to digital full scale)
+14 dB gain

(400 mV

RMS

input to

0111 1111 7F

digital full scale)

hex

hex

hex

Maximum deviation

0001 0011 13

hex

384 kHz1)
recommended FIR­bandwidth: 500 kHz

For the High Deviation Mode, the FM prescaling values
can be used in the range between 13

hex

to 30

. Please

hex

consider the internal reduction of 6 dB for this mode. The
FIR-bandwidth should be selected to 500 kHz.

1)

Given deviations will result in internal digital full scale
signals. Appropriate clipping headroom has to be set by
the customer. This can be done by decreasing the listed
values by a specific factor.

MICRONAS INTERMETALL36

PRELIMINARY DAT A SHEET

MSP 3400C

7.1.12. FM Matrix Modes (see also Table 4–1)

FM matrix 000e

hex

NO MATRIX 0000 0000 00

L

hex

RESET
GSTEREO 0000 0001 01
KSTEREO 0000 0010 02

hex

hex

NO_MA TRIX is used for terrestrial mono or satellite ste­reo sound. GSTEREO dematrixes (L+R, 2R) to (2L, 2R)
and is used for German dual carrier stereo system
(Standard B/G). KSTEREO dematrixes (L+R, L–R) to
(2L, 2R) and is used for the Korean dual carrier stereo
system (Standard M).

7.1.13. FM Fixed Deemphasis

Deemphasis FM 000f

hex

50 µs 0000 0000 00

H

hex

RESET
75 µs 0000 0001 01
J17 0000 0100 04
OFF 0011 1111 3F

hex

hex

hex

7.1.15. I

2

S1 and I2S2 Prescale

Prescale I2S1 0016
Prescale I2S2 0012

OFF 00
0 dB gain 10

hex

hex

hex

hex

H
H

RESET

+18 dB gain 7F

hex

7.1.16. ACB Register, Definition of the SCART­Switches and DIG_CTR_OUT Pins

ACB Register 0013

hex

H

DSP In

Selection of Source:

SC_1_IN
MONO_IN
SC_2_IN
SC_3_IN

xxxx xx00 RESET
xxxx xx01
xxxx xx10
xxxx xx11

SC_1_OUT_L/R
Selection of Source:

SC_3_IN
SC_2_IN
MONO_IN
DA_SCART

xxxx 00xx RESET
xxxx 01xx
xxxx 10xx
xxxx 11xx

7.1.14. FM Adaptive Deemphasis

FM Adaptive

000f

hex

L

Deemphasis WP1

OFF 0000 0000 00

hex

RESET
WP1 0011 1111 3F

hex

Must be set to ‘OFF’ in case of dual carrier stereo (Ger­man or Korean). If ‘ON’, FM fixed deemphasis must be
set to 75 µs.

SC_2_OUT_L/R
Selection of Source:

DA_SCART
SC_1_IN
MONO_IN

xx00 xxxx RESET
xx01 xxxx
xx10 xxxx

DIG_CTR_OUT1

low
high

x0xx xxxx RESET
x1xx xxxx

DIG_CTR_OUT2

low
high

0xxx xxxx RESET
1xxx xxxx

RESET: The RESET state is taken at the time of
the first write transmission on the control bus to
the audio processing part (DSP). By writing to the
ACB register first, the RESET state can be rede­fined.

MICRONAS INTERMETALL 37

MSP 3400C

PRELIMINARY DAT A SHEET

7.1.17. Beeper

Beeper V olume 0014

hex

OFF 0000 0000 00

H

hex

RESET

Maximum Volume (full

0111 1111 7F

hex

digital scale FDS)

Beeper Frequency 0014

hex

16 Hz (lowest) 0000 0001 01
1 kHz 0100 0000 40
4 kHz (highest) 1111 1111 FF

L

hex

hex

hex

A squarewave beeper can be added to the loudspeaker
channel and the headphone channel. The addition point
is just before loudness and volume adjustment.

7.1.18. Identification Mode

Identification Mode 0015

Standard B/G (German
Stereo)

0000 0000 00
RESET

hex

L

hex

7.1.19. FM DC Notch

FM DC Notch 0017

hex

ON 0000 0000 00

L

hex

Reset

OFF 0011 1111 3F

hex

The DC compensation filter (FM DC Notch) for FM input
can be switched off. This is used to speed up the auto­matic search function (see sector 6.4.3.). In normal FM­mode, the FM DC Notch should be switched on.

7.1.20. Mode Tone Control

Mode Tone Control 00020

hex

Bass and Treble 0000 0000 00

H

hex

RESET

Equalizer 1111 1111 FF

hex

By means of ‘Mode T one Control’, Bass/Treble or Equal­izer may be activated.

Standard M (Korean

0000 0001 01

hex

Stereo)
Reset of Ident-Filter 0011 1111 3F

hex

To shorten the response time of the identification algo­rithm after a program change between two FM-stereo
capable programs, the reset of ident-filter can be ap­plied.

Sequence:

1. Program change

2. Reset ident-filter

3. Wait at least 1 msec.

4. Set identification mode back to standard B/G or M

5. Wait approx. 1 sec.

6. Read stereo detection register

MICRONAS INTERMETALL38

PRELIMINARY DAT A SHEET

MSP 3400C

7.1.21. Equalizer Loudspeaker Channel

Band 1 (below 120 Hz) 0021
Band 2 (Center: 500 Hz) 0022
Band 3 (Center: 1.5 kHz) 0023
Band 4 (Center: 5 kHz) 0024
Band 5 (above 10kHz) 0025

hex

hex

hex

hex

hex

+12 dB 0110 0000 60
+11 dB 0101 1000 58

+1 dB 0000 1000 08
+1/8 dB 0000 0001 01

0 dB 0000 0000 00

RESET

–1/8 dB 1111 1111 FF
–1 dB 1111 1000 F8

Different sound sources (e.g. Terrestrial channels, SA T
channels or SCART) fairly often don’t have the same

H
H

volume level. Advertisement during movies as well has
mostly a different (higher) volume level, than the movie
itself. The Automatic Volume Correction (AVC) solves
this problem and equalizes the volume levels.

H
H
H

hex

hex

hex

The absolute value of the incoming signal is fed into a
filter with 16ms attack time and selectable decay time.
The decay time must be adjusted as shown in the table
above. This attack/decay filter block works similar to a
peak hold function. The volume correction value with it’s
quasi continuous step width is calculated using the at­tack/decay filter output.

The Automatic Volume Correction works with an internal
reference level of –18 dBFS. This means, input signals

hex

with a volume level of –18 dBFS will not be affected by
the A VC. If the input signals vary in a range of –24 dB to

hex

hex

0 dB the AVC compensates this.

Example: A static input signal of 1 kHz on Scart has an
output level as shown in the table below.

hex

–11dB 1010 1000 A8
–12 dB 1010 0000 A0

hex

hex

With positive equalizer settings, internal overflow may
occur even with overall volume less than 0 dB. This will
lead to a clipped output signal. Therefore, it is not recom­mended to set equalizer bands to a value that, in con­junction with volume, would result in an overall positive
gain.

Equalizer must not be used simultaneously with Bass
and Treble (Mode Tone Control must be set to FF to use
the Equalizer).

7.1.22. Automatic Volume Correction (AVC)

AVC on/off 0029hex [15:12]

AVC off and Reset

of int. variables

0000 0hex

RESET
AVC on 1000 8hex

AVC Decay Time 0029hex [1 1:8]

8 sec (long)
4 sec (middle)
2 sec (short)
20 ms (very short)

1000 8hex

0100 4hex

0010 2hex

0001 1hex

Scart Input
0dbr = 2 Vrms

Volume
Correc-

Main Output
0dBr = 1.4 Vrms

tion

0 dBr –18 dB –18 dBr
–6 dBr –12 dB –18 dBr
–12 dBr –6 dB –18 dBr
–18 dBr –0 dB –18 dBr
–24 dBr + 6 dB –18 dBr
–30 dBr + 6 dB –24 dBr
Loudspeaker Volume = 73h = 0 dBFS

Scart Prescale = 20h i.e. 2.0 Vrms = 0dBFS

To reset the internal variables, the AVC should be
switched off and on during any channel or source
change. For standard applications, the recommended
decay time is 4sec.

Note: AVC should not be used in any Dolby Prologic
modes, except PANORAMA, where no other than the
loudspeaker output is active.

MICRONAS INTERMETALL 39

MSP 3400C

PRELIMINARY DAT A SHEET

7.1.23. Subwoofer on Headphone Output

The subwoofer channel is created by combining the left
and right loudspeaker channels ( (L+R)/2 ) directly be­hind the tone control filter block. A third order lowpass fil­ter with programmable corner frequency and volume ad­justment respectively to the loudspeaker channel output
is performed to the bass-signal. Additionally , at the loud­speaker channels, a complementary high pass filter can
be switched on. The subwoofer channel output can be
switched to the headphone D/A converter alternatively
with the headphone output.

Subwoofer Channel
Volume Adjust

0 dB 0000 0000 00hex

–1 dB 1111 1111 FFhex
–29 dB 1110 001 1 E3hex

–30 dB 1110 0010 E2hex

002Chex H

RESET

7.2. Exclusions

In general, all functions can be switched independently
of the others. One exception exists:

1. If the adaptive deemphasis is activated (Reg. 000f
L), the FM fixed deemphasis (Reg. 000f
set to 75 µs.

H) must be

hex

hex

Mute 1000 0000 80hex

Subwoofer Channel
Corner Frequency

50 Hz .... 400 Hz

e.g. 50 Hz = 5 int

400 Hz = 40int

Headphone Output 002Dhex [7:4]

Headphone 0000 0hex
Subwoofer 1000 8hex

Subwoofer: Comple­mentary Highpass

HP off 0000 0hex
HP on 0001 1hex

Note: If subwoofer is chosen for headphone output, the
corner frequency must be set to the desired value, be­fore the loudspeaker volume is set. This is to avoid plop
noise.

002Dhex H

0000 0101 05hex
0010 1000 28hex

002Dhex [3:0]

MICRONAS INTERMETALL40

PRELIMINARY DAT A SHEET

7.3. Summary of Readable Registers

All readable registers are 16 bit wide. Transmissions via
I2C bus have to take place in 16 bit words. Single data
entries are 8 bit. Some of the defined 16 bit words are
divided into low and high byte, thus holding two different
control entities.

These registers are not writeable.

Name Address High/Low Output Range

MSP 3400C

Stereo detection register 0018
Quasi peak readout left 0019
Quasi peak readout right 001a
DC level readout FM1/Ch2–L 001b
DC level readout FM2/Ch1–R 001c
MSP hardware version code 001e
MSP major revision code
MSP product code 001f

hex

hex

hex

hex

hex

hex

hex

H [80
H&L [00
H&L [00
H&L [00
H&L [00
H [00
L [00
H [00

MSP ROM version code L [00

7.3.1. Stereo Detection Register

Stereo Detection

0018

hex

H

7.3.2. Quasi Peak Detector

Register

Stereo Mode Reading

(two’s complement)

... 7F

hex

... 7FFF

hex

... 7FFF

hex

... 7FFF

hex

... 7FFF

hex

... FF

hex

... FF

hex

... 0A

hex

... FF

hex

] 8 bit two’s complement

hex

hex

hex

hex

hex

]

hex

]

hex

]

hex

]

hex

Quasi peak readout
left

Quasi peak readout
right

] 16 bit binary
] 16 bit binary
] 16 bit binary
] 16 bit binary

0019

hex

001a

hex

H+L

H+L

MONO near zero

Quasi peak readout [0

... 7FFF

hex

hex

]

values are 16 bit binary

STEREO positive value (ideal

reception: 7F
BILINGUAL negative value (ideal

reception: 80

hex

hex)

)

The quasi peak readout register can be used to read out
the quasi peak level of any input source, in order to ad­just all inputs to the same normalized listening level. The
refresh rate is 32 kHz. The feature is based on a filter
time constant:

attack-time: 1.3 ms
decay-time: 37 ms

MICRONAS INTERMETALL 41

MSP 3400C

PRELIMINARY DAT A SHEET

7.3.3. DC Level Register

DC level readout FM1 001b
DC level readout FM2 001c

DC Level [0

hex

hex

hex

... 7FFF

hex

H+L
H+L

]

values are 16 bit binary

The DC level register measures the DC component of
the incoming FM signals (FM1 and FM2). This can be
used for seek functions in satellite receivers and for IF
FM frequencies fine tuning. For further processing, the
DC content of the demodulated FM signals is sup­pressed. The time constant τ, defining the transition time
of the DC Level Register, is approximately 28 ms.

7.3.4. MSP Hardware Version Code

Hardware Version 001e

Hardware Version [00
MSP 3400C – C8 03

hex

hex

hex

... FF

hex

H

]

7.3.6. MSP Product Code

Product 001f

hex

MSP 3400C 0000 0000 00
MSP 3400 0000 1010 0A
MSP 3410 0000 1010 0A

1)

Note: The MSP 3400 hardware is identical to the

H

hex

1)

hex

hex

MSP 3410. Therefore, the family code readout will show
‘MSP 3410’ instead of its label ‘MSP 3400’.

7.3.7. MSP ROM Version Code

ROM Version 001f

Major software revision [00

hex

hex

... FF
MSP 3400C – B5 0000 0101 05
MSP 3400C – C6 0000 0110 06
MSP 3400C – C8 0000 1000 08

hex

L

]

hex

hex

hex

A change in the hardware version code defines hard­ware optimizations that may have influence on the chip’s
behavior. The readout of this register is identical to the
hardware version code in the chip’s imprint.

7.3.5. MSP Major Revision Code

Major Revision 001e

MSP 3400C 03

hex

hex

L

The MSP 3400C is the third generation of ICs in the MSP
family .

A change in the ROM version code defines internal soft­ware optimizations, that may have influence on the
chip’s behavior, e.g. new features may have been in­cluded. While a software change is intended to create no
compatibility problems, customers that want to use the
new functions can identify new MSP 3400C versions ac­cording to this number. The readout of this register is
identical to the ROM version code in the chip’s imprint.

MICRONAS INTERMETALL42

PRELIMINARY DAT A SHEET

8. Specifications

8.1. Outline Dimensions

MSP 3400C

619

60

44

4327

+0.25

25

1

10

2

9

9

26

+0.25

25

Fig. 8–1:

68-Pin Plastic Leaded Chip Carrier Package

(PLCC68)

Weight approximately 4.8 g
Dimensions in mm

+0.2

x 45 °

1

1.9 1.5

4.05

±0.15

4.75

0.4570.2

0.711

0.9

23.4

0.1

2.4

1.27

2

0.1±

24.2

0.1± 0.1±

16 x 1.27 = 20.32

0.1±

15

0.1±

24.2

1.2 x 45°

2.4

0.1±

1.27

0.1± 0.1±

16 x 1.27 = 20.32

SPGS7004-3/4E

3364

1.9

3

±0.1

0.3

3.8

±0.4

4.8

0.3

2.5

132

±0.1

57.7

(1)

±0.4

1.29

3.2

1.778
31 x 1.778 = 55.118

±0.05

±0.1

1

0.457

±0.1

Fig. 8–2:

64-Pin Plastic Shrink Dual Inline Package

(PSDIP64)

Weight approximately 9.0 g
Dimensions in mm

0.27

19.3
18

±0.06

20.1

SPGS0016-4/2E

±0.1

±0.1

±0.6

2752

126

±0.1

47

±0.1

1

±0.05

1.778
25 x 1.778 = 44.47

0.457

±0.1

±0.2

0.4

±0.1

4

0.3

0.27

0.24

±0.2

3.2

Fig. 8–3:

52-Pin Plastic Shrink Dual In Line Package

(PSDIP52)

Weight approximately 5.5 g
Dimensions in mm

SPGS0015-1/2E

±0.1

15.6

±0.1

14

±0.06

0°...15°

MICRONAS INTERMETALL 43

MSP 3400C

PRELIMINARY DAT A SHEET

23 x 0.8 = 18.4

±0.03

4164

0.17

0.8

40

25

241

1.28

17.2

65

1.8

10.3

9.8

80

16

8

23.2

Fig. 8–4:

80-Pin Plastic Quad Flat Pack Package

(PQFP80)

Weight approximately 1.61 g
Dimensions in mm

8.2. Pin Connections and Short Descriptions

NC = not connected; leave vacant
LV = if not used, leave vacant
X = obligatory; connect as described

in circuit diagram

3

2.70

±0.2

1.8

14

0.1

8

5

20

AHVSS = connect to AHVSS
DVSS = if not used, connect to DVSS
– = pin does not exist in this package

0.8

15 x 0.8 = 12.0

SPGS0025-1/1E

Pin No. Pin Name Type Connection Short Description

PLCC
68-pin

1 16 14 9 S_ID

PSDIP
64-pin

PSDIP
52-pin

PQFP
80-pin

3410D in ( ) (if not used)

OUT LV SBUS Ident or ADR

(ADR_WS)

wordstrobe

1)

2 – – – NC LV Not connected
3 15 13 8 S_DA_IN

(ADR_DA)

OUT LV SBUS Data input or ADR

data output

1)

4 14 12 7 I2S_DA_IN1 IN LV I2S1 data input
5 13 11 6 I2S_DA_OUT OUT LV I2S data output
6 12 10 5 I2S_WS IN/OUT LV I2S wordstrobe
7 11 9 4 I2S_CL IN/OUT LV I2S clock
8 10 8 3 I2C_DA IN/OUT X I2C data
9 9 7 2 I2C_CL IN/OUT X I2C clock
10 8 – 1 NC LV Not connected
11 7 6 80 STANDBYQ IN X Standby (low-active)
12 6 5 79 ADR_SEL IN X I2C Bus address select

1)

Depending on MODE_REG[14], the SBUS Interface can be switched into ADR_MODE with S_CL
becoming ADR_CL, S_ID becoming ADR_WS and S_DA_IN becoming ADR_DA (see also section 4.5.).

2)

Due to compatibility with MSP 3410, it is possible to connect with DVSS as well.

MICRONAS INTERMETALL44

PRELIMINARY DAT A SHEET

MSP 3400C

Short DescriptionConnectionTypePin NamePin No.

PLCC
68-pin

PSDIP
64-pin

PSDIP
52-pin

80-pin

(if not used)3410D in ( )PQFP

13 5 4 78 D_CTR_OUT0 OUT LV Digital control output 0
14 4 3 77 D_CTR_OUT1 OUT LV Digital control output 1
15 3 – 76 NC LV Not connected
16 2 – – NC LV Not connected
17 – – 75 NC LV Not connected
18 1 2 74 AUD_CL_OUT OUT LV Audio clock output
19 64 1 73 DMA_SYNC IN LV DMA-Sync. Input
20 63 52 72 XT AL_OUT OUT X Crystal oscillator
21 62 51 71 XTAL_IN IN X Crystal oscillator
22 61 50 70 TESTEN IN X Test pin
23 60 49 69 ANA_IN2+ IN LV IF input 2 (if ANA_IN1+ is

used only, connect to
AVSS with 50 pF capaci-

tor)
24 59 48 68 ANA_IN– IN LV IF common
25 58 47 67 ANA_IN1+ IN LV IF input 1
26 57 46 66 AVSUP X Analog power supply +5 V
– – – 65 AVSUP X Analog power supply +5 V
– – – 64 NC LV Not connected
– – – 63 NC LV Not connected
27 56 45 62 AVSS X Analog ground
– – – 61 AVSS X Analog ground
28 55 44 60 MONO_IN IN LV Mono input
– – – 59 NC LV Not connected
29 54 43 58 VREFTOP X Reference voltage IF A/D

converter
30 53 42 57 SC1_IN_R IN LV Scart input 1 in, right
31 52 41 56 SC1_IN_L IN LV Scart input 1 in, left
32 51 – 55 ASG1 AHVSS Analog Shield Ground 1
33 50 40 54 SC2_IN_R IN LV Scart input 2 in, right
34 49 39 53 SC2_IN_L IN LV Scart input 2 in, left

1)

Depending on MODE_REG[14], the SBUS Interface can be switched into ADR_MODE with S_CL
becoming ADR_CL, S_ID becoming ADR_WS and S_DA_IN becoming ADR_DA (see also section 4.5.).

2)

Due to compatibility with MSP 3410, it is possible to connect with DVSS as well.

MICRONAS INTERMETALL 45

MSP 3400C

PRELIMINARY DAT A SHEET

Short DescriptionConnectionTypePin NamePin No.

PLCC
68-pin

PSDIP
64-pin

PSDIP
52-pin

80-pin

(if not used)3410D in ( )PQFP

35 48 – 52 ASG2 AHVSS Analog Shield Ground 2
36 47 38 51 SC3_IN_R IN LV Scart input 3 in, right
37 46 37 50 SC3_IN_L IN LV Scart input 3 in, left
38 45 – 49 NC (ASG4) LV Not connected
39 44 – 48 NC

LV Not connected

(SC4_IN_R)

40 43 – 47 NC

LV Not connected

(SC4_IN_L)

41 – – 46 NC LV or

Not connected

AHVSS

42 42 36 45 AGNDC X Analog reference voltage

high voltage part
43 41 35 44 AHVSS X Analog ground
– – – 43 AHVSS X Analog ground
– – – 42 NC LV Not connected
– – – 41 NC LV Not connected
44 40 34 40 CAPL_M X Volume capacitor MAIN
45 39 33 39 AHVSUP X Analog power supply

8.0 V
46 38 32 38 CAPL_A X Volume capacitor AUX
47 37 31 37 SC1_OUT_L OUT LV Scart output 1, left
48 36 30 36 SC1_OUT_R OUT LV Scart output 1, right
49 35 29 35 VREF1 X Reference ground 1 high

voltage part
50 34 28 34 SC2_OUT_L OUT LV Scart output 2, left
51 33 27 33 SC2_OUT_R OUT LV Scart output 2, right
52 – – 32 ASG3 AHVSS

2)

Analog Shield Ground 3
53 32 – 31 NC LV Not connected
54 31 26 30 NC

LV Not connected

(DACM_SUB)
55 30 – 29 NC LV Not connected
56 29 25 28 DACM_L OUT LV Analog output MAIN, left

1)

Depending on MODE_REG[14], the SBUS Interface can be switched into ADR_MODE with S_CL
becoming ADR_CL, S_ID becoming ADR_WS and S_DA_IN becoming ADR_DA (see also section 4.5.).

2)

Due to compatibility with MSP 3410, it is possible to connect with DVSS as well.

MICRONAS INTERMETALL46

PRELIMINARY DAT A SHEET

MSP 3400C

Short DescriptionConnectionTypePin NamePin No.

PLCC
68-pin

PSDIP
64-pin

PSDIP
52-pin

80-pin

(if not used)3410D in ( )PQFP

57 28 24 27 DACM_R OUT LV Analog output MAIN,

right

58 27 23 26 VREF2 X Reference ground 2 high

voltage part
59 26 22 25 DACA_L OUT LV Analog output AUX, left
60 25 21 24 DACA_R OUT LV Analog output AUX, right
– – – 23 NC LV Not connected
– – – 22 NC LV Not connected
61 24 20 21 RESETQ IN X Power-on-reset
62 23 – 20 NC LV Not connected
63 22 – 19 NC LV Not connected
64 21 19 18 NC LV Not connected
65 20 18 17 I2S_DA_IN2 IN LV I2S2-data input
66 19 17 16 DVSS X Digital ground
– – – 15 DVSS X Digital ground
– – – 14 DVSS X Digital ground
67 18 16 13 DVSUP X Digital power supply +5 V
– – – 12 DVSUP X Digital power supply +5 V
– – – 11 DVSUP X Digital power supply +5 V
68 17 15 10 S_CL

(ADR_CL)

1)

Depending on MODE_REG[14], the SBUS Interface can be switched into ADR_MODE with S_CL

OUT LV SBUS clock or ADR

clock

1)

becoming ADR_CL, S_ID becoming ADR_WS and S_DA_IN becoming ADR_DA (see also section 4.5.).

2)

Due to compatibility with MSP 3410, it is possible to connect with DVSS as well.

MICRONAS INTERMETALL 47

MSP 3400C

8.3. Pin Configurations

PRELIMINARY DAT A SHEET

S_ID

I2C_CL

NC

STANDBYQ

ADR_SEL
D_CTR_OUT0
D_CTR_OUT1

NC
NC
NC

AUD_CL_OUT

DMA_SYNC

XTAL_OUT

XTAL_IN
TESTEN

ANA_IN2+

ANA_IN–

ANA_IN1+

AVSUP

I2S_CL

I2C_DA

10
11
12
13
14
15
16
17
18
19

20
21
22
23
24
25
26

NC

S_DA_IN

I2S_DA_IN1

I2S_DA_OUT

I2S_WS

654321

789

MSP 3400C

27 28

29 30 31 32 33 34 35 36 37 38 39

S_CL

DVSUP

DVSS

I2S_DA_IN2

NC

NC

68 67 66 65 64 63 62 61

43424140

NC

RESETQ

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

DACA_R
DACA_L
VREF2
DACM_R
DACM_L
NC
NC
NC
ASG3

SC2_OUT_R
SC2_OUT_L
VREF1
SC1_OUT_R
SC1_OUT_L

CAPL_A
AHVSUP
CAPL_M

AVSS

MONO_IN

VREFTOP

SC1_IN_R

SC1_IN_L

ASG1

SC2_IN_R

SC2_IN_L

Fig. 8–5: 68-pin PLCC package

AHVSS

AGNDC

NC

NC

NC

NC

SC3_IN_L

SC3_IN_R

ASG2

MICRONAS INTERMETALL48

PRELIMINARY DAT A SHEET

MSP 3400C

NC
NC

NC

S_ID

S_CL

DVSS

NC
NC

NC

ASG3

NC
NC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

AUD_CL_OUT

D_CTR_OUT1
D_CTR_OUT0

ADR_SEL

STANDBYQ

I2C_CL

I2C_DA

I2S_CL

I2S_WS

I2S_DA_OUT

I2S_DA_IN1

S_DA_IN

DVSUP

I2S_DA_IN2 NC

RESETQ
DACA_R

DACA_L

VREF2

DACM_R

DACM_L

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49

48
47
46

MSP 3400C

45
44

43
42
41
40
39
38
37
36
35
34
33

DMA_SYNC
XTAL_OUT
XTAL_IN
TESTEN
ANA_IN2+
ANA_IN–
ANA_IN1+
AVSUP
AVSS
MONO_IN
VREFTOP
SC1_IN_R
SC1_IN_L
ASG1
SC2_IN_R
SC2_IN_L
ASG2
SC3_IN_R
SC3_IN_L

NC
NC
AGNDC
AHVSS
CAPL_M
AHVSUP
CAPL_A
SC1_OUT_L
SC1_OUT_R
VREF1
SC2_OUT_L
SC2_OUT_R

NC

AUD_CL_OUT

D_CTR_OUT1
D_CTR_OUT0

ADR_SEL

STANDBYQ

I2C_CL

I2C_DA

I2S_CL

I2S_WS

I2S_DA_OUT

I2S_DA_IN1

S_DA_IN

S_ID

S_CL

DVSUP

DVSS

I2S_DA_IN2

NC
RESETQ
DACA_R

DACA_L

VREF2
DACM_R
DACM_L

NC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

MSP 3400C

52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37

36
35
34
33
32
31
30
29
28
27

XTAL_OUT
XTAL_IN
TESTEN
ANA_IN2+
ANA_IN–
ANA_IN1+
AVSUP
AVSS
MONO_IN
VREFTOP
SC1_IN_R
SC1_IN_L
SC2_IN_R
SC2_IN_L
SC3_IN_R
SC3_IN_L
AGNDC
AHVSS
CAPL_M
AHVSUP
CAPL_A
SC1_OUT_L
SC1_OUT_R
VREF1
SC2_OUT_L
SC2_OUT_R

Fig. 8–6: 64-pin shrink PSDIP package

Fig. 8–7: 52-pin shrink PSDIP package

MICRONAS INTERMETALL 49

MSP 3400C

PRELIMINARY DAT A SHEET

AVSUP
AVSUP

ANA_IN1+

ANA_IN–

ANA_IN2+

TESTEN
XTAL_IN

XTAL_OUT

DMA_SYNC

AUD_CL_OUT

D_CTR_OUT1
D_CTR_OUT0

ADR_SEL

STANDBY_Q

NC
NC

NC

65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

SC2_IN_R

ASG1

SC1_IN_L

SC1_IN_R

VREFTOP

NC

MONO_IN

AVSS

AVSS

NC

626364

61 60 59 58 57 56

345678910111213

12

SC2_IN_L

55 54 53 52 51 50 49 48

ASG2

MSP 3400C

SC3_IN_R

SC3_IN_L

NC

NC

47 46 45 44 43 42 41

18 19 20 21 22 23 24

17161514

NC

NC

AGNDC

AHVSS

AHVSS

NC

NC

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

CAPL_M
AHVSUP
CAPL_A
SC1_OUT_L
SC1_OUT_R
VREF1
SC2_OUT_L
SC2_OUT_R
ASG3

NC
NC
NC
DACM_L
DACM_R

VREF2
DACA_L

NC
I2C_CL

I2C_DA

I2S_CL

I2S_WS

I2S_DA_OUT

I2S_DA_IN1

S_DA_IN I2S_DA_IN2

S_ID

Fig. 8–8: 80-pin PQFP package

S_CL

DVSUP

DVSUP

DACA_R

NC

NC

RESETQ

NC

NC

NC

DVSS

DVSS

DVSS

DVSUP

MICRONAS INTERMETALL50

PRELIMINARY DAT A SHEET

8.4. Pin Circuits

DV

SUP

P

MSP 3400C

N

GND

Fig. 8–9: Output Pins 1, 5, 13, 14, and 68
(S_ID, I

2

S_DA_OUT, D_CTR_OUT0/1, S_CL)

DV

SUP

P

N

GND

Fig. 8–10: Input Pins 4 and 65

2

(I

S_DA_IN1/2)

2.5 V

Fig. 8–14: Input Pin 19 (DMA_SYNC)

DV

SUP

P

N

GND

Fig. 8–15: Input Pin 3
(S_DA_IN)

P

N

GND

Fig. 8–11: Input/Output Pins 8 and 9
(I2C_DA, I2C_CL)

Fig. 8–12: Input Pins 11, 12, 61, and 62
(ST ANDBYQ, ADR_SEL, RESETQ, TESTEN)

DV

SUP

P

N

3–30 pF

3–30 pF

500 k

N

2.5 V

Fig. 8–16: Output/Input Pins 18, 20, and 21
(AUD_CL_OUT, XTALIN/OUT)

ANAIN1+
ANAIN2+

ANAIN–
VREFTOP

A

D

GND

Fig. 8–13: Input/Output Pins 6 and 7

2

(I

S_WS, I2S_CL)

Fig. 8–17: Input Pins 23–25 and 29
(ANA_IN2+, ANA_IN–, ANA_IN1+, VREFTOP)

MICRONAS INTERMETALL 51

MSP 3400C

16 K

≈ 3.75 V

AHV

SUP

0...1.2 mA

PRELIMINARY DAT A SHEET

Fig. 8–18: Input Pin 28 (MONO_IN)

0...2 V

Fig. 8–19: Capacitor Pins 44 and 46
(CAPL_M, CAPL_A)

40 K

≈ 3.75 V

3.3 K

Fig. 8–21: Output Pins 56, 57, 59, and 60
(DACA_L/R, DACM_L/R)

125 K

≈ 3.75 V

Fig. 8–22: Pin 42 (AGNDC)

40 pF

80 K

300

≈ 3.75 V

Fig. 8–20: Input Pins 30, 31, 33, 34, 36, and 37
(SC1–3_IN_L/R)

Fig. 8–23: Output Pins 47, 48, 50 and 51
(SC_1/2_OUT_L/R)

MICRONAS INTERMETALL52

PRELIMINARY DAT A SHEET

MSP 3400C

8.5. Electrical Characteristics

8.5.1. Absolute Maximum Ratings

Symbol Parameter Pin Name Min. Max. Unit

T

A

T

S

V

SUP1

V

SUP2

V

SUP3

dV

P

TOT

V

Idig

I

Idig

V

Iana

I

Iana

I

Oana

I

Oana

SUP23

Ambient Operating Temperature – 0 70 °C
Storage Temperature – –40 125 °C
First Supply Voltage AHVSUP –0.3 9.0 V
Second Supply Voltage DVSUP –0.3 6.0 V
Third Supply Voltage AVSUP –0.3 6.0 V
Voltage between AVSUP

and DVSUP
Chip Power Dissipation

PLCC68 without Heat Spreader
Input Voltage, all Digital Inputs –0.3 V

A VSUP,

–0.5 0.5 V

DVSUP
AHVSUP,

DVSUP, AVSUP 1100 mW

+0.3 V

SUP2

Input Current, all Digital Pins – –20 +20 mA
Input Voltage, all Analog Inputs SCn_IN_s,

2)

–0.3 V

SUP1

+0.3 V

MONO_IN

Input Current, all Analog Inputs SCn_IN_s,

2)

–5 +5 mA

MONO_IN
Output Current, all SCART Outputs SCn_OUT_s
Output Current, all Analog Outputs

DACp_s

2) 3), 4) 3), 4)

2) 3) 3)

except SCART Outputs

1)

1)

I

Cana

1)

positive value means current flowing into the circuit

2)

“n” means “1”, “2” or “3”, “s” means “L” or “R”, “p” means “M” or “A”

3)

The Analog Outputs are short circuit proof with respect to First Supply Voltage and Ground.

4)

Total chip power dissipation must not exceed absolute maximum rating.

Output Current, other pins
connected to capacitors

CAPL_p,

AGNDC

2)

3) 3)

Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only . Functional operation of the device at these or any other conditions beyond those indicated in the
“Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute maxi­mum ratings conditions for extended periods may affect device reliability.

MICRONAS INTERMETALL 53

MSP 3400C

ADR_SEL

I2C_DA

I2C_DA

8.5.2. Recommended Operating Conditions

(at TA = 0 to 70 °C)

PRELIMINARY DAT A SHEET

Symbol Parameter

V
V
V

V
V
t

REIL

SUP1

SUP2

SUP3

REIL

REIH

First Supply Voltage AHVSUP 7.6 8.0 8.4 V
Second Supply Voltage DVSUP 4.75 5.0 5.25 V
Third Supply Voltage AVSUP 4.75 5.0 5.25 V

RESET Input Low Voltage RESETQ 0.45 V
RESET Input High Voltage 0.8 V
RESET Low Time after DVSUP

Stable and Oscillator Startup

V

DMAIL

V

DMAIH

t

DMA

R

DMA

V

DIGIL

V

DIGIH

Sync Input Low Voltage DMA_SYNC 0.44 V
Sync Input High Voltage 0.56 V
Sync Input Frequency 18.0 kHz
Sync Input Clock High-Level Time 500 ns

Digital Input Low Voltage STANDBYQ,
Digital Input High Voltage

Pin Name

TESTEN

Min. Typ. Max. Unit

SUP2

SUP2

5 µs

SUP1

SUP1

0.25 V

SUP2

,

0.75 V

SUP2

t

STBYQ1

STANDBYQ Setup Time before
Turn-off of Second Supply Voltage

I2C-Bus Recommendations
V
V
f

IM

t

I2C1

t

I2C2

t

I2C3

t

I2C4

t

I2C5

IMIL

IMIH

I2C-BUS Input Low Voltage I2C_CL,
I2C-BUS Input High Voltage
I2C-BUS Frequency I2C_CL 1.0 MHz
I2C START Condition Setup Time I2C_CL,
I2C STOP Condition Setup Time
I2C-Clock Low Pulse Time I2C_CL 500 ns
I2C-Clock High Pulse Time 500 ns
I2C-Data Setup Time Before

Rising Edge of Clock

t

I2C6

I2C-Data Hold Time after Falling

Edge of Clock
V
V

I2SIL

I2SIH

I2S-Data Input Low Voltage I2S_DA_IN1/2 0.25 V

I2S-Data Input High Voltage 0.75 V

ST ANDBYQ,
DVSUP

I2C_CL,

2

I

C_DA

1 µs

0.3 V

0.6 V

120 ns
120 ns

55 ns

55 ns

SUP2

SUP2

SUP2

SUP2

MICRONAS INTERMETALL54

PRELIMINARY DAT A SHEET

MSP 3400C

t

I2S1

t

I2S2

V

I2SIDL

V

I2SIDH

f

I2SCL

R

I2SCL

f

I2SWS

t

I2SWS1

ParameterSymbol

I2S-Data Input Setup Time
before Rising Edge of Clock

I2S-Data Input Hold Time
after Falling Edge of Clock

I2S-Input Low Voltage when
MSP 3400C in I2S-Slave-Mode

I2S-Input High Voltage when
MSP 3400C in I2S-Slave-Mode

I2S-Clock Input Frequency when
MSP 3400C in I2S-Slave-Mode

I2S-Clock Input Ratio when
MSP 3400C in I2S-Slave-Mode

I2S-Wordstrobe Input Frequency
when MSP 3400C in I2S-Slave­Mode

I2S-Wordstrobe Input Setup Time
before Rising Edge of Clock when
MSP 3400C in I2S-Slave-Mode

Pin Name

I2S_DA_IN1/2,

20 ns

UnitMax.T yp.Min.

I2S_CL

0 ns

I2S_CL,

0.25 V

SUP2

I2S_WS

0.75 V

SUP2

I2S_CL 1.024 MHz

0.9 1.1

I2S_WS 32.0 kHz

I2S_WS,

60 ns

I2S_CL

t

I2SWS2

I2S-Wordstrobe Input Hold Time
after Falling Edge of Clock when
MSP 3400C in I2S-Slave-Mode

V

SBUSIL

I

SBUSIL

V

SBUSTRIG

t

SBUS1

SBUS-Data Input Low Voltage S_DA_IN 0.6 V
SBUS-Data Input Low Current 0.9 1.7 3.2 mA
SBUS-Data Input Trigger Voltage 0.8 1.2 V
SBUS-Data Input Setup Time

before Rising Edge of Clock

t

SBUS2

SBUS-Data Input Hold Time
after Falling Edge of Clock

Crystal Recommendations for Master-Slave Application
f

P

Parallel Resonance Frequency at
12 pF Load Capacitance

f

TOL

D

TEM

Accuracy of Adjustment –20 +20 ppm
Frequency Variation versus

Temperature

R

R

Series Resistance 8 25 Ω

S_DA_IN,
S_CL

0 ns

10 ns

0 ns

18.432 MHz

–20 +20 ppm

C

0

C

1

Shunt (Parallel) Capacitance 6.2 7.0 pF
Motional (Dynamic) Capacitance 19 24 fF

MICRONAS INTERMETALL 55

MSP 3400C

1)

1)

PRELIMINARY DAT A SHEET

ParameterSymbol

Pin Name

Load Capacitance Recommendations for Master-Slave Applications
C

L

f

CL

External Load Capacitance

Required Open Loop Clock

Frequency (T

amb

= 25°C)

2)

XTAL_IN,
XTAL_OUT

PSDIP 1.5
PLCC 3.3

18.431 18.433 MHz

Crystal Recommendations for FM Application (No Master-Slave Mode possible)
f

P

Parallel Resonance Frequency at

18.432 MHz

12 pF Load Capacitance
f

TOL

D

TEM

Accuracy of Adjustment –100 +100 ppm

Frequency Variation versus

–50 +50 ppm

Temperature
R

R

C

0

Series Resistance 8 25 Ω

Shunt (Parallel) Capacitance 6.2 7.0 pF
Load Capacitance Recommendations for FM Application (No Master-Slave Mode possible)

C

L

External Load Capacitance

2)

XTAL_IN,
XTAL_OUT

PSDIP 1.5
PLCC 3.3

UnitMax.Typ.Min.

pF
pF

pF
pF

Amplitude Recommendation for Operation with External Clock Input (C
V

XCA

External Clock Amplitude XTAL_IN 0.7 V

after reset = 22 pF)

load

Analog Input and Output Recommendations
C

AGNDC

AGNDC-Filter-Capacitor AGNDC –20% 3.3 µF

Ceramic Capacitor in Parallel –20% 100 nF
C

inSC

DC-Decoupling Capacitor in front

SCn_IN_s

–20% 330 +20% nF

of SCART Inputs
V

inSC

V

inMONO

R

LSC

C

LSC

C

VMA

SCART Input Level 2.0 V

Input Level, Mono Input MONO_IN 2.0 V

SCART Load Resistance SCn_OUT_s

10 kΩ
SCART Load Capacitance 6.0 nF
Main/AUX Volume Capacitor CAPL_M,

10 µF

CAPL_A

C

FMA

1)

“n” means “1”, “2” or “3”, “s” means “L” or “R”, “p” means “M” or “A”

2)

External capacitors at each crystal pin to ground are required. They are necessary to tune the open-loop fre-

Main/AUX Filter Capacitor DACM_s,

DACA_s

1)

–10% 1 +10% nF

quency of the internal PLL and to stabilize the frequency in closed-loop operation. The higher the capacitors,
the lower the clock frequency results. The nominal free running frequency should match 18.432 MHz as closely
as possible. Due to different layouts of customer PCBs, the matching capacitor size should be defined in the
application. The suggested values (1.5 pF/3.3 pF) are figures based on experience with various PCB layouts.

pp

RMS

RMS

MICRONAS INTERMETALL56

PRELIMINARY DAT A SHEET

ANA_IN

MSP 3400C

ParameterSymbol

Recommendations for Analog Sound IF Input Signal
C

VREFTOP

VREFTOP-Filter-Capacitor VREFTOP –20% 10 µF
Ceramic Capacitor in Parallel –20% 100 nF

V

IF

Analog Input Range
(Complete Sound IF, 0 – 9 MHz)

R

FM

Ratio: FM-Main/FM-Sub
Satellite

R

FM1/FM2

Ratio: FM1/FM2
German FM-System

R

FC

Ratio: Main FM Carrier/Color
Carrier

R

FV

Ratio: Main FM Carrier/Luma

Components
PR
SUP

IF

HF

Passband Ripple – – ±2 dB dB

Suppression of Spectrum

Above 9.0 MHz

Pin Name

ANA_IN1+,
ANA_IN2+,

–

UnitMax.T yp.Min.

0.14 0.8 3 Vpp

7 dB

7 dB

15 – – dB

15 – – dB

15 – dB

FM

MAX

Maximum FM-Deviation (apprx.)

normal mode

high deviation mode

±192
±360

kHz

MICRONAS INTERMETALL 57

MSP 3400C

D_CTR_OUT1

PRELIMINARY DAT A SHEET

8.5.3. Characteristics at TA = 0 to 70 °C, f

= 18.432 MHz

CLOCK

(Typical values are measured at TA = 25 °C, AHVSUP = 8 V, DVSUP = 5 V, AVSUP = 5 V.)

Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions

DCO
f

CLOCK

D

CLOCK

t

JITTER

V

xtalDC

t

Startup

Power Supply
I

SUP1A

I

SUP2A

Clock Input Frequency XTAL_IN 18.432 MHz
Clock High to Low Ratio 45 55 %
Clock Jitter (verification not

50 ps

provided in production test)
DC-Voltage Oscillator 2.5 V
Oscillator Startup Time at

VDD Slew-rate of 1 V / 1 µs

First Supply Current (active)

Analog Volume for Main and Aux at 0dB
Analog Volume for Main and Aux at –30dB

at Tj = 27 °C

XTAL_IN,
XTAL_OUT

AHVSUP

8.2

5.6

0.4 2.0 ms

14.8

10.0

22.0

15.0mAmA

f = 18.432 MHz
AHVSUP = 8 V
DVSUP = 5 V
AVSUP = 5 V

Second Supply Current (active) DVSUP 60 65 70 mA f = 18.432 MHz

DVSUP = 5 V

I

SUP3A

I

SUP1S

Third Supply Current (active) AVSUP 25 mA f = 18.432 MHz

First Supply Current
(standby mode) at T

Audio Clock Output
V

APUAC

V

APUDC

Audio Clock Output AC Voltage AUD_CL_OUT 1.2 V
Audio Clock Output DC Voltage 0.4 0.6 V

Digital Output
V

DCTROL

V

DCTROH

Digital Output Low Voltage D_CTR_OUT0
Digital Output High Voltage

I2C Bus
V

IMOL

I

IMOH

t

IMOL1

t

IMOL2

I2C-Data Output Low Voltage I2C_DA 0.4 V I
I2C-Data Output High Current 1 µA V
I2C-Data Output Hold Time after

Falling Edge of Clock
I2C-Data Output Setup Time

before Rising Edge of Clock

= 27 °C

j

AVSUP = 5 V

AHVSUP 2.8 5.0 7.2 mA ST ANDBYQ = low

VSUP = 8 V

40 pF load

= 1 mA

DDCTR

= –1 mA

DDCTR

= 3 mA

iMOL

= 5 V

IMOH

I2C_DA,

2

I

C_CL

pp

SUP1

0.4 V I

4.0 V I

15 ns

100 ns fIM = 1 MHz

DVSUP = 5 V

SBus
f

SB

t

S1/S2

t

S3

f

SIO

t

S6

SBUS-Clock Frequency S_CL 4608 kHz DVSUP = 5 V
SBUS-Clock High/Low-Ratio 0.9 1.0 1.1 ns
SBUS Setup Time before

Ident End Pulse

S_CL,
S_ID

210 ns DVSUP = 5.25 V

SBUS Ident frequency S_ID 32 kHz
SBUS-Ident End Pulse Time 210 ns DVSUP = 5.25 V

MICRONAS INTERMETALL58

PRELIMINARY DAT A SHEET

I2S_CL

1)

1)

→

I2S Bus

MSP 3400C

Test ConditionsUnitMax.Typ.Min.Pin NameParameterSymbol

V

I2SOL

V

I2SOH

f

I2SCL

f

I2SWS

t

I2S1/I2S2

t

I2S3

t

I2S4

t

I2S5

t

I2S6

Analog Ground
V

AGNDC0

R

outAGN

I2S Output Low Voltage I2S_WS,
I2S Output High Voltage

I2S_DA_OUT

,

4.0 V I

0.4 V I

I2SOL

I2SOH

= 1 mA

= –1 mA
I2S-Clock Output Frequency I2S_CL 1204 kHz DVSUP = 5 V
I2S-Wordstrobe Output Frequency I2S_WS 32.0 kHz DVSUP = 5 V
I2S-Clock High/Low-Ratio I2S_CL 0.9 1.0 1.1
I2S-Data Setup Time

before Rising Edge of Clock
I2S-Data Hold Time after Falling

I2S_CL,
I2S_DA_OUT

200 ns DVSUP = 4.75 V

12 ns DVSUP = 5.25 V

Edge of Clock
I2S-Wordstrobe Setup Time

before Rising Edge of Clock
I2S-Wordstrobe Hold Time after

I2S_CL,
I2S_WS

100 ns DVSUP = 4.75 V

50 ns DVSUP = 5.25 V

Falling Edge of Clock

AGNDC Open Circuit Voltage AGNDC 3.64 3.73 3.84 V R
AGNDC Output Resistance

at Tj = 27 °C
from T

= 0 to 70 °C

A

70
70

125 180

180

kΩ
kΩ

load

3 V ≤ V

≥ 10 MΩ

AGNDC

≤ 4 V

Analog Input Resistance
R

inSC

R

inMONO

SCART Input Resistance
at Tj = 27 °C
from T

= 0 to 70 °C

A

MONO Input Resistance
at T

= 27 °C

j

from T

= 0 to 70 °C

A

Audio Analog-to-Digital-Converter
V

AICL

Analog Input Clipping Level for
Analog-to-Digital-Conversion

SCART Outputs
R

outSC

dV

OUTSC

A

SCtoSC

f

rSCtoSC

SCART Output Resistance
at T

= 27 °C

j

from T

= 0 to 70 °C

A

Deviation of DC-Level at SCART
Output from AGNDC Voltage

Gain from Analog Input to SCART
Output

Frequency Response from Analog
Input to SCART Output
bandwidth: 0 to 20000 Hz

SCn_IN_s

1)

MONO_IN

SCn_IN_s,
MONO_IN

SCn_OUT_s

SCn_IN_s
MONO_IN

SCn_OUT_s

f

= 1 kHz,

signal

25
25

10
10

1)

2.02 2.12 2.22 V

0.20

0.20

40 58

58

16 23

23

0.33 0.46

0.5

kΩ
kΩ

kΩ
kΩ

RMS

kΩ
kΩ

I ≤ 0.05 mA

f

= 1 kHz,

signal

I ≤ 0.1 mA

f

= 1 kHz

signal

f

= 1 kHz, I = 0.1 mA

signal

–70 +70 mV

f

= 1kHz

–1.0 0 +0.5 dB

1)

signal

with respect to 1 kHz

–0.5 0 +0.5 dB

V

outSC

Signal Level at SCART-Output
during full-scale digital input signal

SCn_OUT_s

1)

1.8 1.9 2.0 V

RMS

f

signal

= 1 kHz

from DSP

1)

“n” means “1”, “2” or “3”, “s” means “L” or “R”, “p” means “M” or “A”

MICRONAS INTERMETALL 59

MSP 3400C

1)

Main and AUX Outputs

PRELIMINARY DAT A SHEET

Test ConditionsUnitMax.Typ.Min.Pin NameParameterSymbol

R

outMA

V

outDCMA

Main/AUX Output Resistance
at T

= 27 °C

j

from T

= 0 to 70 °C

A

DC-Level at Main/AUX-Output
for Analog Volume at 0 dB
for Analog Volume at –30 dB

V

outMA

Signal Level at Main/AUX-Output
during full-scale digital input signal
from DSP for Analog Volume at
0 dB

Analog Performance
SNR Signal-to-Noise Ratio

from Analog Input to DSP MONO_IN,

from Analog Input to
SCART Output

from DSP to SCART Output SCn_OUT_s

from DSP to Main/AUX-Output
for Analog Volume at 0 dB
for Analog Volume at –30 dB

DACp_s

SCn_IN_s

MONO_IN,
SCn_IN_s

1)

1)

→
SCn_OUT_s

DACp_s

1)

f

= 1 kHz, I = 0.1 mA

2.1

2.1

3.3 4.6

5.0

kΩ
kΩ

signal

1.74–1.94612.14–V
mV

1.23 1.37 1.51 V

RMS

f

signal

= 1 kHz

85 88 dB Input Level = –20 dB with

resp. to V
kHz, equally weighted
20 Hz...16 kHz

93 96 dB Input Level = –20 dB,

f

= 1 kHz,

sig

1)

1)

85 88 dB Input Level = –20 dB,

equally weighted
20 Hz...20 kHz

f

= 1 kHz,

sig

equally weighted
20 Hz...15 kHz

Input Level = –20 dB,
f

= 1 kHz,

sig

85
78

88
83

dB
dB

equally weighted
20 Hz...15 kHz

AICL

, f

= 1

sig

2)

3)

3)

THD Total Harmonic Distortion

from Analog Input to DSP MONO_IN,

SCn_IN_s

from Analog Input to
SCART Output

MONO_IN,
SCn_IN_s

1)

→
SCn_OUT_s

from DSP to SCART Output SCn_OUT_s

from DSP to Main or AUX Output DACA_s,

DACM_s

1)

“n” means “1”, “2” or “3”, “s” means “L” or “R”, “p” means “M” or “A”

2)

DSP measured at I2S-Output

3)

DSP Input at I2S-Input

1)

0.05 % Input Level = –3 dBr with
resp. to V
equally weighted
20 Hz...16 kHz,

= 30 kΩ

R

Load

AICL

, f

=1kHz,

sig

2)

0.01 0.03 % Input Level = –3 dBr,
f

= 1 kHz, equally

sig

1)

1)

0.01 0.03 % Input Level = –3 dBr,

weighted 20 Hz...20 kHz,

= 30 kΩ

R

Load

f

= 1 kHz, equally

sig

weighted 20 Hz...16 kHz,
R

Load

= 30 kΩ

3)

0.01 0.03 % Input Level = –3 dBr,
f

= 1 kHz, equally

sig

weighted 20 Hz...16 kHz,
R

Load

= 30 kΩ

3)

MICRONAS INTERMETALL60

PRELIMINARY DAT A SHEET

20 Hz

kHz)

channel, effect on each

g

MSP 3400C

Test ConditionsUnitMax.Typ.Min.Pin NameParameterSymbol

XTALK Crosstalk attenuation

– PLCC68
– PSDIP64

between left and right channel within SCART Input/Out­put pair (L→R, R→L)

SCn_IN → SCn_OUT

SCn_IN → DSP

DSP → SCn_OUT

1)

1)

between left and right channel within Main or AUX
Output pair

DSP → DACp

1)

between SCART Input/Output pairs
D = disturbing program

O = observed program
D: MONO/SCn_IN → SCn_OUT PLCC68

O: MONO/SCn_IN → SCn_OUT

Input Level = –3 dB,

= 1 kHz, unused ana-

f

sig

log inputs connected to
ground by Z<1 kΩ

equally weighted
20 Hz...20 kHz

1)

PLCC68

PSDIP648080

PLCC68

PSDIP648080

PLCC68

PSDIP648080

dB
dB

dB
dB

dB
dB

2)

3)

equally weighted
20 Hz...16 kHz

3)

(equally weighted

1)

PLCC68

PSDIP648075

dB
dB

...20
same signal source on
left and right disturbing

1)

PSDIP64

100
100

dB
dB

observed output channel

D: MONO/SCn_IN → SCn_OUT PLCC68
O: or unsel. MONO/SCn_IN → DSP

D: MONO/SCn_IN → SC1_OUT PLCC68
O: DSP → SCn_OUT

D: MONO/SCn_IN → unselected PLCC68
O: DSP → SC1_OUT

Crosstalk between Main and AUX Output pairs
DSP → DACp

1)

1)

1)

1)

PSDIP64

PSDIP64

PSDIP64

PLCC68

PSDIP649590

Crosstalk from Main or AUX Output to SCART Output
and vice versa

D = disturbing program
O = observed program

D: MONO/SCn_IN/DSP → SCn_OUT PLCC68
O: DSP → DACp

D: MONO/SCn_IN/DSP → SCn_OUT PLCC68
O: DSP → DACp

D: DSP → DACp PLCC68
O: MONO/SCn_IN → SCn_OUT

1)

1)

1)

PSDIP64

PSDIP64

PSDIP64

95
95

100
100

100
100

90
85

95
85

100
95

dB
dB

dB
dB

dB
dB

dB
dB

dB
dB

dB
dB

dB
dB

2)

3)

3)

(equally weighted
20 Hz...16 kHz)

3)

same signal source on
left and right disturbing
channel, effect on each
observed output channel

(equally weighted
20 Hz...20 kHz)
same signal source on
left and right disturbing
channel, effect on each
observed output channel

SCART output load resis­tance 10 kΩ

SCART output load resis­tance 30 kΩ

3)

1)

“n” means “1”, “2” or “3”, “s” means “L” or “R”, “p” means “M” or “A”

2)

DSP measured at I2S-Output

3)

DSP Input at I2S-Input

MICRONAS INTERMETALL 61

D: DSP → DACp PLCC68
O: DSP → SCn_OUT

1)

PSDIP64

100
95

dB
dB

MSP 3400C

PSRR: rejection of noise on AHVSUP at 1 kHz
PSRR AGNDC AGNDC 80 dB

PRELIMINARY DAT A SHEET

Test ConditionsUnitMax.Typ.Min.Pin NameParameterSymbol

From analog Input to DSP MONO_IN

SCn_IN_s

From analog Input to
SCART Output

MONO_IN
SCn_IN_s,

1)

SCn_OUT_s

From DSP to SCART Output SCn_OUT_s
From DSP to MAIN/AUX Output DACp_s

1)

1)

1)

1)

69 dB

74 dB

70 dB

80 dB
Sound IF Input Section
DC

VREFTOP

R

IFIN

DC voltage at VREFTOP VREFTOP 2.4 2.6 2.7 V V

Input Impedance ANA_IN1+,

ANA_IN2+,

1.5

10.5214.1

2.5

17.6

kOhm AGC = +20 dB

ANA_IN–

DC

ANA_IN

XTALK

BW

IF

IF

DC voltage on IF inputs 1.3 1.5 1.7 V AVSUP = 5 V

Crosstalk attenuation 40 t.b.d. – dB f

3 dB Bandwidth 10 – – MHz Input Level = –2 dBr

AGC AGC step width t.b.d. 0.85 t.b.d. dB f

SUPANALOG

R

Load

= 5 V

≥10 MΩ

AGC = +3 dB

≥10 MΩ

R

Load

R

≥10 MΩ

Load

= 1 MHz,

sig

Input Level = –2 dBr

= 1 MHz,

sig

Input Level = –2 dBr

1)

“n” means “1”, “2” or “3”, “s” means “L” or “R”, “p” means “M” or “A”

MICRONAS INTERMETALL62

PRELIMINARY DAT A SHEET

Overall Performance

MSP 3400C

Test ConditionsUnitMax.Typ.Min.Pin NameParameterSymbol

S/N

FM

S/N

D2MAC

THD

FM

THD

D2MAC

dV

FMOUT

dV-

D2MACOUT

fR

FM

fR

D2MAC

FM input to Main/AUX/SCART
Output

Signal to Noise ratio of D2MAC
baseband signal on Main/AUX/
SCART outputs

Total Harmonic Distortion + Noise
of FM demodulated signal on
Main/AUX/SCART output

Total Harmonic Distortion + Noise
of D2MAC baseband signal for
Main/AUX/SCART output

Tolerance of output voltage of FM
demodulated signal

Tolerance of output voltage of
D2MAC baseband signal

FM frequency response on Main/
AUX/SCART outputs, bandwidth
20 to 15000 Hz

D2MAC frequency response on
Main/AUX/SCART outputs, band­width 20 to 15000 Hz

DACp_s,
SCn_OUT_s

70 – dB 1 FM-carrier 5.5 MHz,

1)

50 µs, 1 kHz, 40 kHz de­viation; RMS, unweighted
0 to 15 kHz; full input
range

TBD – dB

– 0.3 % 1 FM-carrier 5.5 MHz,

1kHz, 50 µs; 40 kHz devi­ation; full input range

– 0.01 0.1 % 2.12 kHz, Modulator input

level = 0 dBref

–1.5 +1.5 dB 1 FM-carrier, 50 µs,

1 kHz
40 kHz deviation; RMS

–1.5 +1.5 dB 2.12 kHz, Modulator input

level = 0 dBref

–1.0 +1.0 dB 1 FM-carrier 5.5 MHz,

50 µs, Modulator input
level = –14.6 dBref; RMS

–1.0 +1.0 dB Modulator input level =

–12 dB dBref; RMS

SEP

FM

SEP

D2MAC

XTALK

FM

XTALK-

D2MAC

1)

“n” means “1”, “2” or “3”, “s” means “L” or “R”, “p” means “M” or “A”

FM channel separation (Stereo) 50 dB 2 FM-carriers 5.5/5.74

D2MAC channel separation
(Stereo)

FM crosstalk attenuation (Dual) 80 dB 2 FM-carriers 5.5/5.74

D2MAC crosstalk attenuation
(Dual)

MHz, 50 µs, 1 kHz, 40
kHz deviation; RMS

80 dB

MHz, 50 µs, 1 kHz, 40
kHz deviation; RMS

80 dB

MICRONAS INTERMETALL 63

MSP 3400C

9. Application of the MSP 3400C

PRELIMINARY DAT A SHEET

5V

DVSS

AHVSS

AHVSS

AHVSS

5V

DVSS

Tuner 2

Tuner 1

330 nF

330 nF
330 nF

330 nF
330 nF

330 nF
330 nF

IF 2 IN

Signal GND

IF 1 IN

50pF 50pF

50pF

Ana_IN1+ (58) 25

28 (55) MONO_IN
52 (30) ASG3
30 (53) SC1_IN_R
31 (52) SC1_IN_L
32 (51) ASG1

33 (50) SC2_IN_R
34 (49) SC2_IN_L

35 (48) ASG2
36 (47) SC3_IN_R
37 (46) SC3_IN_L

11 (7) STANDBY Q

12 (6) ADR_SEL

2

9 (9) I

C-CL

8 (10) I2C-DA
1 (16) S_ID

68 (17) S_CL
3 (15) S_DA_IN

6 (12) I2S_WS
7 (11) I2S_CL
4 (14) I2S_DA_IN1
65 (20) I2S_DA_IN2
5 (13) I2S_DA_OUT

10

100

µF

nF

-

+

3.3
µF

+

Ana_IN– (59) 24

Ana_IN2+ (60) 23

VREFTOP (54) 29

MSP 3400C

18.432

100

MHz

nF

AGNDC (42) 42

XTAL_IN (62) 21

0.1 pF

+8.0 V

++

10 µF

10 µF

CAPL_A (46) 38

CAPL_M (40) 44

XTAL_OUT (63) 20

DACM_L (29) 56

DACM_R (28) 57

DACA_L (26) 59

DACA_R (25) 60

SC1_OUT_L (37) 47

SC1_OUT_R (36) 48

SC2_OUT_L (34) 50

SC2_OUT_R (33) 51

D_CTR_OUT0 (5) 13
D_CTR_OUT1 (4) 14

AUD_CL_OUT (1) 18

DMA_SYNC (64) 19

TESTEN (61) 22

1 nF

1 nF

1 nF

1 nF

100Ω
100Ω

100Ω
100Ω

1µF

1µF

1µF

1µF

+

+

+

+

22 µF
22 µF

22 µF
22 µF

DVSS

MAIN

HEAD­PHONE

45 (39) AHVSUP

100
nF

43 (41) AHVSS

49 (35) VREF1

58 (27) VREF2

67 (18) DVSUP

61 (24) RESETQ

100
nF

+

10 µF

26 (57) AVSUP

66 (19) DVSS

100
nF

27 (56) AVSSAVSS

5V 5V 8.0 V

Note: Pin numbers refer to PLCC packages, pin numbers for PSDIP packages in brackets.
not connected pins are 2,10,15,16,17,38,39,40,41,53,54,55,62,63,64 (2,3,8,21,22,23,31,32,43,44,45)

MICRONAS INTERMETALL64

PRELIMINARY DAT A SHEET

MSP 3400C

10. DMA Application

Fig. 10–1 shows an example for the D2MAC application
with the MSP 3400 or MSP 3400C. T o obtain the optimal
amplitude and phase conditions for the clock input of

+ 5 Volt

S_DATA 66

S_IDENT 64

S_CLOCK 67

open

DMA 2381

Software:

SBS = 1
ACS = 1
ACF = 0
DCOF= 1
(addr. 204, 214)

ACLK

65 17 16

AMU, DMA 2386, and DMA 2381, it is recommended to
use a clock inverter circuit, as shown below right, a mini­mum gain of 1.0 at 18.432 MHz and an output phase as
specified in Fig. 10–2.

5 K

9 S_DATA_IN

15 S_IDENT

8 S_CLOCK

AMU 2481

S_Bus
Slave_mode

S_DATA_OUT 6

13 AUDIO_CLOCK

18.432 MHz

1 nF

4.7 nF

65 66 64

ACLK S_DATA S_IDENT

DMA 2386

Clock
Inverter

(see below)

+2...3 V

DMA 2381/86

and AMU 2481

68 S_CL

1 S_ID

MSP 3400C C6...
MSP 3410/00
TC15/F7

MODE_REG[0] = 1

18 AUD_CL_OUT

19 DMA_SYNC

To

3

S_DA_IN

Clock Inverter

+5 V

100 nF

120 6k8

10 nF

BC 848C

3k882

Fig. 10–1: DMA application with MSP 3410 TC15 or F7
Note: Pin numbers refer to PLCC packages for DMA 2381 and MSP 3400C and to PSDIP package for AMU 2481

MICRONAS INTERMETALL 65

MSP 3400C

MSP Clock Output

PRELIMINARY DAT A SHEET

Clock Inverter Output

Timing window

typ. 20 ns

at inverter output

>10 ns

for the low to high edge at
pin 17 of DMA 2381 (XTAL2)

<42 ns

Fig. 10–2: Timing requirements for the clock signal at the DMA 2381 clock input

In the following table, the input/output clock-specification of the D2MAC circuit is shown.

Table 10–1: Clock input and output specification for MSPs

XTAL_IN min

MSP 3400C >C6

new Version
>0.7 Vpp

MSP 3410/00 TC27

new Version
>0.7 Vpp

(minimum amplitude)
C input

22 pF

22 pF

(after Reset)

MSP 3410/00 TC15

actual Version
>0.7 Vpp

31 pF

AUD_CL_OUT min
with C load

Rout (HF) typ.

>1.2 Vpp
40 pF

150 Ω

>1.2 Vpp
40 pF

120 Ω

Table 10–2: Clock input and output specification for ICs connected to MSP

DMA 2381 DMA 2386 AMU2481

XTAL_IN min

>0.7 Vpp

>0.7 Vpp
Clock-in min
(minimal amplitude)

C input

24 pF

7pF

10 pF with: Adr.
204,14=1

For the DMA_SYNC input specification of the MSP, please refer to page 54 “V

DMAIL

, V

>1.0 Vpp
43 pF

120 Ω

>0.7 Vpp

7pF

DMAIH

.”

MICRONAS INTERMETALL66

PRELIMINARY DAT A SHEET

11. MSP Application with External Clock

If for some reason, e.g. to spare the cost of an additional
crystal, the MSP receives the 18.432 MHz clock from an
external source, for example from an other MSP , the fol­lowing circuit can be used. For input/output specification
see also Table 10–1.

18.432 MHz

6362

MSP 3400C

MSP 3400C or
MSP 3410B

AUD_CL_OUT 18

Fig. 11–1: MSP 3400C with external clock

12. ADR Application

18.432 MHz

Tuner
(Sat)

MSP 3400C

(in I2S Slave Mode)

I2S_DA_OUT

S_CL

S_ID

S_DA_IN

2

I

S_CL

2

S_WS

I

I2S_DA_IN

10 nF

LV

ADR-Interface

2

S-Interface

I

62 XTAL_IN

63 XTAL_OUT

18.432 MHz

SI1C
SI1I
SI1D

PI16
PI15
SO1C
SO1I
SO1D
PI14

MSP 3400C

DRP 3510A

MICRONAS INTERMETALL 67

MSP 3400C

13. I2S Bus in Master/Slave Configuration with
Standby Mode

In a master/slave application, both MSP, after power up
and reset, will start as master by default. This means that
before the slave MSP is set to slave-mode, relatively
large current-pulses (~20 mA) in the I2S_CL and
I2S_WS lines can cause some crackling noise during
startup time, if the the MSP is demuted before the slave
MSP is set to slave mode.

These high current pulses are also possible, if the active
I2S_CL and I2S_WS outputs of the master MSP are
clipped by the correspondent inputs of the slave MSP,
which is switched to standby mode.

To avoid this, it is recommended, that the I2S-bus lines
I2S_CL and I2S_WS are current-limited to about 5 mA
with series resistors of about 390 Ω (330...470 Ω).

Fig. 13–1 depicts the recommended application circuit
for two MSP 3410/00 or MSP 3400C, which are con­nected via I2S Bus in a master/slave configuration, and
where the slave MSP can be switched in standby mode
(+5 Volt power is switched off).

PRELIMINARY DAT A SHEET

18.432 MHz

6362

MSP 3410/00
MSP 3400C

(master)

+5 V

I2S_DA_OUT 13

I2S_DA_IN 14

I2S_WS 12

I2S_CL 11

R

C

minimal corner frequency = 4 MHz
with R = 390 Ω (330–470 Ω)

Standby control

DVSUP STANDBYQ

13 I2S_DA_OUT
14 I2S_DA_IN
12 I2S_WS

11 I2S_CL

718

MSP 3410/00
MSP 3400C

(slave)

18.432 MHz

6362

Fig. 13–1: I2S master/slave application

MICRONAS INTERMETALL68

PRELIMINARY DAT A SHEET

MSP 3400C

14. APPENDIX A: Technical Code History

TC01
First Release, compatible with MSP3410 and

MSP 3400. Date: June 1994.
TC04

Emulator version for software development.
Version B5

New Features:

1. Equalizer

2. Improved identification

3. Improved adaptive deemphasis
Version C6

New Features:

1. Adjustable Stereo Basewidth Enlargement (SBE) and
switchable Pseudo Stereo Effect (SBE)

2. New Channel Matrix Modes (Mono, Sum/Dif, etc)

3. New Audio Clock Output Driver

4. Fast mute (Volume)

5. Clipping mode (Volume)

6. Sub dB steps for Volume, Bass, Treble, Equalizer

15. APPENDIX B: Documentation History

1. Advance Information: “MSP 3400C Multistandard
Sound Processor”, Apr. 14, 1994, 6251-377-1AI.
First release of the advance information.

2. MSP 3400C Data Sheet: “MSP 3400C Multistandard
Sound Processor”, Dec. 14, 1994, 6251-377-1PD.
First release of the preliminary data sheet.

3. MSP 3400C Data Sheet: “MSP 3400C Multistandard
Sound Processor”, Oct. 6, 1996, 6251-377-2PD.
Second release of the preliminary data sheet.
Major changes: see Appendix A: Version C6

4. MSP 3400C Data Sheet: “MSP 3400C Multistandard
Sound Processor”, Dec. 8, 1997, 6251-377-3PD.
Third release of the preliminary data sheet.
Major changes: see Appendix A: Version C7 and C8

– new PQFP80 package

Version C7
New Features:

1. Balance, Bass, Treble and Loudness for Headphone
output

2. Prescale for I2S1 and I2S2 inputs

3. Balance in dB units and linear mode

4. SCART volume in dB units and linear mode

5. Increased range for Bass/Treble
Version C8

New Features:

1. Automatic Volume Control A.V.C.

2. Subwoofer Output alternatively with Headphone Out­put.

MICRONAS INTERMETALL 69

MSP 3400C

PRELIMINARY DAT A SHEET

MICRONAS INTERMETALL70

PRELIMINARY DAT A SHEET

MSP 3400C

MICRONAS INTERMETALL 71

MSP 3400C

PRELIMINARY DAT A SHEET

MICRONAS INTERMETALL GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. [phone]
Fax [phone]
E-mail: [e-mail]
Internet: http://www.intermetall.de

Printed in Germany
Order No. 6251-377-3PD

All information and data contained in this data sheet are with­out any commitment, are not to be considered as an offer for
conclusion of a contract nor shall they be construed as to
create any liability . Any new issue of this data sheet invalidates
previous issues. Product availability and delivery dates are ex­clusively subject to our respective order confirmation form; the
same applies to orders based on development samples deliv­ered. By this publication, MICRONAS INTERMET ALL GmbH
does not assume responsibility for patent infringements or
other rights of third parties which may result from its use.
Reprinting is generally permitted, indicating the source. How­ever, our prior consent must be obtained in all cases.

MICRONAS INTERMETALL72

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