Datasheet MSM9810GS-BK Datasheet (OKI)

E2D0020-39-93

¡ Semiconductor MSM9810

¡ Semiconductor

This version: Sep. 1999

Previous version: May 1997

MSM9810

8-channel Mixing OKI ADPCM Type Voice Synthesis LSI

GENERAL DESCRIPTION

The MSM9810 is an 8-channel mixing voice synthesis IC, to which up to 128 Mbits of ROM and/
or EPROM storing voice data can directly be connected externally.
The device is straight 8-bit PCM playback, non-linear 8-bit PCM playback, 4-bit ADPCM
playback, and 4-bit ADPCM2 playback selectable and provides 2-channel stereo output and
volume control. The MSM9810 contains a 14-bit D/A converter and LPF.
The MSM9810 can easily configure a system by connecting voice data storage memory, power
amplifier, and CPU externally.

FEATURES

• Non-linear 8-bit PCM / straight 8-bit PCM / 4-bit ADPCM / 4-bit ADPCM2

• Serial input or parallel input selectable

• Phrase Control Table function

• 8-channel mixing function

• Master clock frequency : 4.096 MHz

• Sampling frequency : 4.0 kHz, 5.3 kHz, 6.4 kHz, 8.0 kHz, 10.6 kHz,

12.8 kHz, 16.0 kHz, 21.2 kHz, 25.6kHz, 32.0kHz

• Maximum number of phrases : 256

• Output channel : L/R 2 channels

• Built-in volume control function (for each output channel)

• Built-in 14-bit D/A converter

• Built–in low–pass filter : Digital filter

• Package :
64-pin plastic QFP(QFP64-P-1414-0.80-BK)(Product name : MSM9810GS-BK)

New

1/31

RA23 RA0

ROE

RD7

RD0

BLOCK DIAGRAM

¡ Semiconductor MSM9810

D7/SD

D6/SI
D5/SO
D4/UD

D3/SR3
D2/SR2
D1/SR1
D0/SR0

RCS

CS

WR

RD

CMD

SERIAL

NCR/BUSY

TEST1
TEST2
TEST3
TEST4

XT

XT

CPU
interface

OSC

8-Bit LATCH

8

23-Bit Multiplexer

8

ADPCM

DATA

Synthesizer

Controller

23-Bit Address

Counter

PCM

Synthesizer

16

8

PAN

Register

16*9 MPY

Timing Controller

14-Bit

DAC

14-Bit

DAC

2/31

RESET

DD

DGNDDV

LDAO

DD

AGNDAV

RDAO

¡ Semiconductor MSM9810

PIN CONFIGURATION (TOP VIEW)

RA23

RA22

RA21

RA20

RA0

RA17

RA16

RA15

RA14

RA13

RA12

DGND

AGND

TEST4

LDAO

RDAO

AV

DD

DV

DD

RCS

TEST1

TEST2

XT

6463626160595857565554

1

2

3

4

5

6

7

8

9

10

11
12XT

13TEST3

14SERIAL
15CMD
16RD

53 RA11

52 RA10

51 RA9

50 RA19

49 RA18

48

DV

RA8

47

RA7

46

RA6

45

RA5

44

RA4

43

RA3

42

RA2

41

RA1

40

ROE

39

RD0

38

37 RD1

36 RD2

35 RD3

34 RD4

33 RD5

DD

1718192021222324252627

WR

NCR/BUSY

CS

D0/SR0

D1/SR1

D2/SR2

D3/SR3

D5/SO

D4/UD

D6/SI

NC

NC: No connection

64-pin Plastic QFP

28D7/SD

29RESET

30RD7

31RD6

32DGND

3/31

¡ Semiconductor MSM9810

PIN DESCRIPTIONS

Pin

40-47, 49-64

30, 31, 33-38

39

8

15

16

18

20

14

28

27

26

Symbol Type

RA23-RA0 O

RD7-RD0 I

ROE O Output enable pin for external memory.

RCS I

CMD I

RD I

WR I

CS I

SERIAL I

D7/SD I/O

D6/SI I/O

D5/SO I/O

Address pins for external memory. These pins become high impedance
when RCS pin is "H".

Data pin for external memory. Pull-down resistors are internally

connected to these pins. These pull-down resistors become valid when
the RCS pin is "H", and become invalid when the RCS pin is "L".

When this pin is "L", RA23 to RA0 and ROE pins output address data and

output enable signal.
When this pin is "H", RA23 to RA0 and ROE pins become high impedance.

Select pin for Command data or Subcommand data.

When this pin is "H", subcommand input is selected. When this pin is "L",

command input is selected.

A pull-up resistor is internally connected to this pin.

Read pin for CPU interface.

A pull-up resistor is internally connected to this pin.

Write pin for CPU interface.

A pull-up resistor is internally connected to this pin.
Chip select pin for CPU interface. When CS is "H", WR signal is not

entered in this IC. A pull-up resistor is internally connected to this pin.

CPU interface select pin. When SERIAL is "H", serial input interface is

selected.

When it is "L", parallel input interface is selected.

Data bus pin for CPU interface when parallel input interface is selected.
When WR is "L", this pin serves as data input pin.
When RD is "L", this pin serves as channel status data output pin.

When serial input interface is selected, this pin serves as serial data

input pin.

Data bus pin for CPU interface when parallel input interface is selected.
When WR is "L", this pin serves as data input pin.
When RD is "L", this pin serves as channel status output pin.

When serial input interface is selected, this pin serves as serial clock

input pin.

Data bus pin for CPU interface when parallel input interface is selected.
When WR is "L", this pin serves as data input pin.
When RD is "L", this pin serves as channel status output pin.

When serial input interface is selected, this pin serves as channel status

output pin.

Description

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¡ Semiconductor MSM9810

Symbol Type DescriptionPin

Data bus pin for CPU interface when parallel input interface is selected.
When WR is "L", this pin serves as data input pin.
When RD is "L", this pin serves as channel status output pin.

25

24

23

22

21

4

5

11

12

29

19

9

10

13

3

7, 48

6

1, 32

2

D4/UD I/O

D3/SR3

D2/SR2

D1/SR1

D0/SR0

LDA0 O LEFT side D/A output pin.

RDA0 O RIGHT side D/A output pin.

XT I

XT O

RESET I

NCR/BUSY I

TEST1

TEST2

TEST3

TEST4

DV

DD

AV

DD

DGND

AGND

When serial input interface is selected, this pin serves as channel status

selecter pin.

When UD is "H", channels 8 thru 5 are output to SR3 thru SR0, respectively.

When UD is "L", channels 4 thru 1 are output to SR3 thru SR0, respectively.

Data bus pin for CPU interface when parallel input interface is selected.
When WR is "L", this pin serves as data input pin.
When RD is "L", this pin serves as channel status output pin.

When serial input interface is selected, this pin serves as channel status

I/O

output pin.

When UD is "H", channels 8 thru 5 are output to SR3 thru SR0, respectively.

When UD is "L", channels 4 thru 1 are output to SR3 thru SR0, respectively.

Crystal or ceramic oscillator connection pin.
A feedback resistor of about 1MW is connected between XT and XT.

If necessary, enter external clocks into this pin.

Crystal or ceramic oscillator connection pin.

When external clocks are used, leave this pin open.

When this pin is "L" level, the LSI is initialized. At that time, oscillation

stopsand D/A outputs go to GND level.

Channel status select pin.
When this pin is "H", NCR signal is output. When it is "L", BUSY signal is

output.

Pins for IC testing. Apply "L" level to these pins.

Pull-down resistors are internally connected to these pins.

I

I Pins for IC testing. Apply "L" level to these pins.

Power supply pin.

—

GND pin.

—

5/31

¡ Semiconductor MSM9810

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Condition Rating Unit

Power Supply Voltage

Input Voltage

Storage Temperature

V

DD

V

IN

T

STG

Ta=25°C

—

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Condition Range Unit

Power Supply Voltage

Operating Temperature

Master Clock Frequency

V

T

f

OSC

DD

op

— 3.5 to 5.5 V

— –40 to +85 °C

—

ELECTRICAL CHARACTERISTICS

DC Characteristics

(DVDD=AVDD=4.5 to 5.5 V, DGND=AGND=0 V, Ta=–40 to +85°C)

Parameter Symbol Condition Min. Unit

High-level Input Voltage V

Low-level Input Voltage V

High-level Output Voltage V

Low-level Output Voltage V

High-level Input Current 1 I

High-level Input Current 2 I

Low-level Input Current 1 I

Low-level Input Current 2 I

Output Leakage Current I

Operating Current I

Standby Current I

IH1

IH2

IL1

IL2

LO

DD

DS

IH

IL

OH

OL

Applied to pins with internal

Applied to pins with internal

Ta = –40°C to +70°C — mA—15

Ta

— 0.84¥V

—— V— 0.16¥V

I

= –1mA VDD–0.4 V——

OH

I

= 2mA — V— 0.4

OL

V

= V

IH

DD

pull-down resistor

V

= GND –10 mA——

IL

pull-up resistor

0 £ V

OUT

£ V

—— mA615

= –40°C to +85°C — mA—50

DD

(GND=0 V)

–0.3 to +7.0

–0.3 to V

DD

+0.3

–55 to +150

(GND=0 V)

Min. Max.

3.5 4.5

Typ.

4.096

Typ. Max.

DD

DD

— mA—10

30 mA— 300

–300 mA— –30

–10 mA— +10

V

V

°C

MHz

V——

6/31

¡ Semiconductor MSM9810

AC Characteristics

(VDD=3.5 to 5.5V, GND=0 V, Ta=–40 to +85°C)

Parameter Symbol Min. Unit

Master Clock Duty Cycle

RESET Input Pulse Width
RESET Delay Time From Raising of Power Supply
Set up and Hold Time of CS for RD, at serial input I/F
RD Pulse Width

Output Data Valid Time after Fall of RD
Data Float Time after Rise of RD
Setup and Hold Time of CMD for WR
Setup and Hold Time of CS for WR
WR Pulse Width
Data Setup Time before Rise of WR
Data Hold Time after Rise of WR

WR-WR Pulse Interval
CS-CS Pulse Interval

Serial Data Setup Time

Serial Data Hold Time

Serial Clock Pulse Width

fduty

tw(RST)
tD(RST)

tCR

tRR

tDRE

tDRF

tDW

tCW

tWW

tDWS

tDWH

tWWS

tCC

tSDS

tSSD

tW(SCK)

40

1

0

30

200

—

—

50

30

200

100

30

160

100

30

30

200

Typ. Max.

50

—

—

—

—

—

10

—

—

—

—

—

—

—

—

—

—

60

—

—

—

—

100

50

—

—

—

—

—

—

—

—

—

—

%

ms

ms

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

7/31

¡ Semiconductor MSM9810

TIMING DIAGRAMS

Power-On Timing

V

DD

RESET (I)

Data Read Timing, Parallel Input

RD(I)

t

D(RST)

t

W(RST)

t

RR

D7 - D0(I/O)

Data Write Timing, Parallel Input

CMD(I)

CS(I)

WR(I)

D7 - D0(I)

Data Stable

t

DRE

t

WSS

Data out Valid

t

DW

t

CW

t

WW

t

DRF

Data Stable

t

DWS

t

DW

t

CW

t

DWH

8/31

¡ Semiconductor MSM9810

Data Write Timing, Serial Input

CMD(I)

CS(I)

WR(I)

SD(I)

SI(I)

t

DW

t

CC

t

CW

t

SDS

t

SSD

t

CW

t

W(SCK)

t

DW

Data Read Timing, Serial Input

CS(I)

RD(I)

SO(I)

SI(I)

t

CR

t

CR

9/31

¡ Semiconductor MSM9810

Command input timing in parallel input interface

• The phrase address "25H" data is played back via channel 1

• The command options selected are 1/2 V

(P-P) sound volume for all channels, use of an

DD

internal low pass filter, secondary digital filter processing, and voltage follower output.

CMD

CS

WR

D7-D0

09H 18H 25H 28H 01H 00H

Set option data

Subcommand

(OPT)

Transfer option

data Command

(OPT)

Set address

data Subcommand

(FADR)

Transfer address

data to channel 1

Command

(FADR)

Set Start flag

to channel 1

Subcommand

(START)

Start flag execution

(Channel 1)

Command

(START)

Channel 1 voice

systhesis starts

See 9. "Command Data and Subcommand Data" for further information on commands and subcommands.

Command input timing in serial input interface

• Phrase address "08H" to channel 1 data and Phrase address "02H" to channel 2 data are played
back simultaneously.

• The command option is default setting.

CMD

CS

WR

SD

SI

(08H)

Set address "01H" data

Subcommand

(FADR)

See 3-1 "Channel Synthesis" for further information on channel synthesis.

(28H)

Transfer address

data to channel 1

Command

(FADR)

(02H)

Set address "02H" data

Subcommand

(FADR)

(29H)

Transfer address data

to channel 2

(FADR)

(03H)

Set start flag to channel 1

and channel 2
Subcommand

(START)

(00H)

Start flag execution

(channel 1 and channel 2)

Command (START)

Channel 1 and channel 2

voice synthesis starts

10/31

¡ Semiconductor MSM9810

FUNCTIONAL DESCRIPTION

1. User Specification Phrase

A maximum of 256 phrases can be selected with user specification phrases. User specification
phrases are stored in the voice management area of external ROM. Merely by selecting a phrase,
sampling frequency and the start and stop address of voice are controlled.
The MSM9810 can directly specify a start address or stop address externally without using user
specification phrases. Only channels 1 to 4 can be used for directly specifying a start address or
stop address externally.

2. Playback Time and Memory Capacity

Table 2.1 shows the configuration of external ROM. The capacity of an actual voice data ROM is
different from the indicated ROM capacity.

Table 2.1 ROM Configuration

Address management area (16Kbits)

Voice data area or

Phrase Controll Table area

Playback time depends on external memory capacity, sampling frequency, and the playback
system. The relationship is shown below.

Playback time =

1.024 ¥ (memory capacity –16) (Kbits)

Sampling frequency (kHz) ¥ bit length

(Bit length is ADPCM, ADPCM2...4bits, PCM...8bits)

(Seconds)

For example, when one 8 Mbits ROM is used with a 16 kHz sampling frequency in a 4-bit ADPCM
type, the playback time becomes as follows.

Playback time=

1.024 ¥ (8192–16) Kbits

16 (kHz) ¥ 4 (bit)

.

=131 seconds

.

In the above equation, the playback time when the Phrase Controll Table function is not used is
shown.

11/31

¡ Semiconductor MSM9810

3. Sampling Frequency

Sampling frequency can be specified for each phrase in the address management area of external
ROM. For the sampling frequency, the following ten types can be selected when voice data is
created.

4.0 kHz, 8.0 kHz, 16.0 kHz, 32.0 kHz (Group 1)

5.3 kHz, 10.6 kHz, 21.3 kHz (Group 2)

6.4 kHz, 12.8 kHz, 25.6 kHz (Group 3)

3-1 Channel Synthesis

When the internal LPFs are used, use of a different sampling frequency than the selected
sampling frequency GroupX is not permitted for channel synthesis.
The internal LPF can be used by selecting "use of internal LPF" with the OPT command (see 9­4 "OPT Command").
When the internal LPFs are not used, channel synthesis can be made using a different sampling
frequency as shown below.

When channels are synthesized, the sampling frequency Group of the first vocalizing channel
(one of the above Group 1 to 3) is selected. If the sampling frequency Group other than the
selected Group is used for channel synthesis, playback becomes fast or slow. Figure 3.1 and
Figure 3.2 show examples.

S

=16.0kHz

Channel 1

Channel 2

Channel 3

f

S

=32.0kHz (Valid)

f

f

S

=25.6 kHz (Invalid, playback with fS=32.0 kHz)

Figure 3.1 When channel 3 is played back using a different sampling frequency

while channel 1 and 2 are being played back.

f

S

Channel 1

Channel 2

=16.0kHz

S

=25.6kHz (Valid)

f

Channel 1 ends

Figure 3.2 Channel 2 is played back using different sampling frequency

after channel 1 was played back

12/31

¡ Semiconductor MSM9810

When multiple channels are played back simultaneously, the sampling frequency Group of the
smallest channel has priority.

S

=8.0 kHz (Sampling frequency group of channel 3 is selected.)

Channel 3

Channel 4

Channel 8

f

S

=25.6 kHz (Invalid, playback with fs=32.0 kHz)

f

f

S

=32.0 kHz (Valid)

Figure 3.3 When channel 3, 4 and 8 are played back simultaneously.

13/31

¡ Semiconductor MSM9810

4. Reset Function

When “L” level is input to the RESET pin, LSI enters power down state, stopping oscillation and
minimizing current consumption. At the same time, the control circuit is reset and initialized.
Power down status is as follows.

(1) Oscillation stops and all internal circuits stop operation.
(2) Current consumption is minimized. When an external clock is in use, input “L” level

to the XT pin in power down status, so that current does not flow into the oscillation
circuit.

(3) When a crystal oscillator is in use, “L” level is output to the XT pin.
(4) GND level is output to the D/A output pin (LDAO, RDAO).

Be certain to input “L” level to the RESET pin when power is turned on.
␣

5. Playback System

This LSI has four types of playback systems to support various voices: 4-bit ADPCM, 4-bit
ADPCM2, 8-bit straight PCM, and 8-bit non-linear PCM.

5-1 4-bit ADPCM

ADPCM (Adaptive Differential Pulse Code Modulation) system adaptively changes the
quantization width and encodes 4-bit data for each sampling, so that the follow up to a voice
waveform improves.
ADPCM data is converted by using an analysis tool.
For a human voice, animal voice and natural sounds, it is better to use the ADPCM system
because the voice data capacity decreases.

5-2 4-bit ADPCM2

In 4-bit ADPCM 2, the follow-up characteristics to a voice waveform is even better than the 4-bit
ADPCM. This system is compatible only with MSM9841/MSM9842.
ADPCM2 data is converted by using an analysis tool.

5-3 8-bit Straight PCM

The follow-up characteristics to a voice waveform to all voice areas is the best of all four types.
This system is suitable for sound effects, where waveforms change rapidly, and for pulse shape
waveforms.

5-4 8-bit Non-linear PCM

This system plays back the center of a waveform to be a voice quality equivalent to 10 bits. This
system is to improve the voice quality of low volume sounds.
8-bit non-linear PCM data is converted by using an analysis tool.

14/31

¡ Semiconductor MSM9810

6. Voice Output

The voice is output as 14-bit D/A converter output in stereo (LDAO, RDAO), with L/R in phase.
The output amplitude from the D/A converter has a maximum (16383/16384) ¥ VDD, and the
output waveform has a step waveform synchronized with sampling frequency.
The command option has been set for voice output. D/A converter output and voltage follower
output can be selected by option.

7. Microcomputer Interface

There are two types of interface with microcomputer; one is parallel input interface and the other
is serial input interface. Either of the two interfaces can be selected with the SERIAL pin. The
parallel input interface is selected when SERIAL is at a "L" level.
The serial input interface is selected when SERIAL is at "H" level.
When the parallel input interface is selected, the MSM9810 is controlled by nine different
commands using D7 to D0 (data buses) and control pins CMD, CS, WR, and RD. The internal
status register is used to check the status of the LSI.
When the serial input interface is selected, the MSM9810 is controlled by nine different
commands using serial data input pin SD and serial clock input pin SI, and control pins CMD,
CS, WR, and RD.
The SO, SR3, SR2, SR1 and SR0 pins are used to check the status of the LSI.
The pins 21 to 28 function differently according to whether the parallel input interface is selected
or the serial input interface is selected.
The table 7-1 shows the pin names. See "PIN DESCRIPTIONS" for their functions.

Table 7-1 Difference between parallel input and serial input pins

28

27

26

25

24

23

22

Pin number

Parallel input

Serial input

21

D7

SD

D6

SI

D5

SO

D4

UD

D3

SR3

D2

SR2

D1

SR1

D0

SR0

15/31

¡ Semiconductor MSM9810

7-1 Parallel Input Interface

In the parallel input interface, the microcomputer controls the LSI via 13 pins of RESET, CMD,
CS, WR, RD and D7-D0.
Command and subcommand data are input from D7-D0 by control of CMD, CS and WR, as
shown in Figure 7-1, and the status is output from D7-D0 by control of RD, as shown in Figure
7-2.

CMD(I)

CS(I)

WR(I)

t

DW

t

CW

t

DW

t

CW

D7 - D0(I)

RD(I)

D7 - D0(I/O)

t

WSS

t

WW

Data Stable

Figure 7-1 Parallel input write cycle timing

t

RR

Data out Valid

t

DRE

Figure 7-2 Parallel input read cycle timing

t

DRF

Data Stable

t

DWS

t

DWH

16/31

¡ Semiconductor MSM9810

7-2 Serial Input Interface

In the serial input interface, the microcomputer controls the LSI via 8 pins of RESET, CMD, CS,
WR, RD, SD, SI and SO. In parallel input, data is output from D7-D0, but in serial input, data for
D7-D0 is input in serial from MSB using SD and SI.

Figure 7-3 shows the command and subcommand input timing, and Figure 7-4 shows read
timing.

CMD(I)

CS(I)

WR(I)

SD(I)

SI(I)

t

DW

t

CC

t

CW

t

SDS

t

SSD

t

CW

t

W(SCK)

t

DW

CS(I)

RD(I)

SO(I)

SI(I)

Figure 7-3 Serial input write cycle timing

t

CR

Figure 7-4 Serial input read cycle timing

t

CR

17/31

¡ Semiconductor MSM9810

8. Channel Status

The channel status is output from D7-D0.
There are two types of signals to be output as channel status: BUSYn (n = 1-8) signals and NCRn
signals. These two types are selected by the NCR/BUSY pin. When the NCR/BUSY pin is at “H”
level, NCR is output, and when at “L” level, BUSY is output.
The NCR signal is the command and subcommand input status signal (Next Command Request)
of each channel, and the WR signal input is enabled at “H” level.
The BUSY signal outputs “L” level while each channel is executing voice synthesis.
Each channel status signal is output from D7-D0 pins in parallel input interface, and from D5/
S0 pins and D3/SR3-D0/SR0 pins in serial input interface by control of RD. Table 8-1 shows the
relationship between D7-D0 and channels, and Figure 8-1 shows read timing in the parallel input
interface.

Table 8-1 Correspondence between D7-D0 and channels

RD(I)

D7 - D0(I/O)

Data bus

Corresponding channel

t

DRE

D7 D6 D5 D4 D3 D2 D1 D0

CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1

t

RR

Data out Valid

t

DRF

Figure 8-1 Read timing in parallel input interface

In serial input interface, serial output from D5/SO pins by control of CS and RD, and D3/SR3­D0/SR0 parallel output (constantly output) can be selected.

For serial output from D5/SO pin, D7-D0, shown in Table 8-1, are output from MSB in serial at
the rise of the SI pin when the RD pin is at “L” level.
Figure 8-2 shows this timing.

18/31

¡ Semiconductor MSM9810

CS

RD(I)

SI(I)

SO(O)

UD

SR3

SR2

SR1

SR0

CH8-5 CH4-1

CH8 CH4

CH7 CH3

CH6 CH2

CH5 CH1

D7

D6 D5 D4 D3 D2 D1 D0

Figure 8-2 Read timing in serial input interface

In serial input interface, status signals are constantly output from D3/SR3 to D0/SR0 pins.
Selection of NCR and BUSY is controlled by the NCR/BUSY pin. Since there are only four D3/
SR3 to D0/SR0 pins, 8 channels of status signals are selected by control of the D4/UD pin. Table
8-2 shows the relationship between D4/UD pin and D3/SR3 to D0/SR0 pins.

Table 8-2 Correspondence between D4/UD and D3/SR3 to D0/SR0

D3/SR3

D2/SR2

D1/SR1

D0/SR0

D4/UD="L"

Channel 4

Channel 3

Channel 2

Channel 1

D4/UD="H"

Channel 8

Channel 7

Channel 6

Channel 5

19/31

¡ Semiconductor MSM9810

9. Command Data and Subcommand Data

In parallel input, command data and subcommand data are controlled by the data bus of D7-D0
pins and by CMD, CS and WR control pins. In serial input, command data and subcommand data
are controlled by data input/output of SD, SI and SO pins and by CMD, CS and WR control pins.

This LSI reads data to the internal register (TMP register) by executing the subcommand, and
transfers data of the TMP register to the register of each command function and executes data by
executing the command.

A subcommand and command are distinguished by the level of the CMD pin. “H” level indicates
a subcommand, and “L” level indicates a command.

Table 9-1 shows the command data list, Table 9-2 shows details of C2-C0 of Table 9-1 (channel
specification), and Table 9-3 shows subcommand data list corresponding to command data.

Table 9-1 Command Data List

D7 D6 D5 D4 D3 D2 D1 D0

1

2

3

4

5

6

7

8

9

START

STOP

LOOP

OPT

MUON

FADR

DADR

CVOL

PAN

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

1

0

0

1

0

0

1

0

0

0

0

1

X

0

0

X

0

1

X

1

0

X

1

1

C2

0

0

C2

0

1

C2

1

0

C2

1

1

C2

0

0

Starts playback of the channel for which data stored in the register is "H".

X

X

Stops playback of channel for which data stored in the register is "H".

X

X

Repeats playback of channel for which data stored in the regiter is "H".

X

X

Changes option by command.

X

X

Inserts silence corresponding to the length of data stored in the register.

C1

C0

Transfers phrase address stored in the register to the phrase register

C1

C0

of the specified channel.

This command internally transfers the 7-byte start and stop address,

C1

C0

the value of sampling frequency and playback algorithm which are

stored in the TMP register.

Changes volume of the specified channel to the volume of data stored

C1

C0

in the register.

Changes volume of the right and left D/A converter to volume of data

C1

C0

stored in the register.

(X - - - don’t care. For C1, C2 and C0, see Table 9-2.)

Function

20/31

¡ Semiconductor MSM9810

Table 9-2 Channel Specification List

C2 Channel control

C1 C0

0

0

0

0

1

0

1

0

0

1

1

0

0

0

1

0

1

1

1

0

1

1

1

1

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

Channel 8

Table 9-3 Subcommand Data List

Command

START

STOP

LOOP

OPT

MUON

FADR

DADR

CVOL

PAN

SA23

SA15

(X - - - don’t care.)

D7

CH8

CH8

CH8

0

M7

FA7

SA7

ST23

ST15

ST7

S3

X

L3

D6

CH7

CH7

CH7

0

M6

FA6

SA22

SA14

SA6

ST22

ST14

ST6

S2

X

L2

D5

CH6

CH6

CH6

0

M5

FA5

SA21

SA13

SA5

ST21

ST13

ST5

S1

X

L1

D4 D3

CH5

CH5

CH5

O4

M4

FA4

SA20

SA19

SA12

SA11

SA4

ST20

ST19

ST12

ST11

ST4

S0

X

L0

CH4

CH4

CH4

O3

M3

FA3

SA3

ST3

P1

V3

R3

D2 D1

CH3

CH3

CH3

O2

M2

FA2

SA18

SA17

SA10

SA2

ST18

ST17

ST10

ST2

P0

V2

R2

CH2

CH2

CH2

O1

M1

FA1

SA9

SA1

ST9

ST1

X

V1

R1

D0

CH1

CH1

CH1

O0

M0

FA0

SA16

SA8

SA0

ST16

ST8

ST0

X

V0

R0

Subcommand funciton

Channel setting

Channel setting

Channel setting
Option setting

Silence time setting

Phrase address setting

(1st byte) address setting

(2nd byte)

(3nd byte)

(4nd byte)

(5nd byte)

(6nd byte)

(7nd byte)

Volume setting

Volume setting

21/31

¡ Semiconductor MSM9810

9-1 START Command

The START command starts voice synthesis of the channel corresponding to the data stored in
the TMP register. Table 9-4 shows the correspondence between data input (D7-D0) and channels.
For serial input, the sequence of D7-D0 and serial input data is shown in Figure 8-2.

Table 9-4 Correspondence between D7-D0 and Channels

Data bus

Corresponding channel

D7 D6 D5 D4 D3 D2 D1 D0

CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1

When the START command is input, data stored in the TMP register is set at the start register,
and voice synthesis processing starts. For example, when all “ 1” is written from the data bus to
the TMP register and the START command is input, all channels start voice synthesis
simultaneously.
Input the START command when the status signal (NCR or BUSY) of the channel to be started
is at “H”. When NCR is “L”, input is disabled.
Figure 9-1 shows the flowchart when the START command is input.

RD pulse input

NCRn="H"

YES

Subcommand input

START command input

NO

NCRn corresponding to each channel is output
to D7-D0

Check that D7-D0 corresponding to the channel
to start voice synthesis is "H".

After setting "H" to D7-D0 corresponding to the
channel to start voice synthesis from the data
bus, input the WR pulse. (Set CMD to "H".)

Figure 9-1 START Command Input Flow

9-2 STOP Command

The STOP command stops voice synthesis processing of the channel corresponding to data
stored in the TMP register. Table 9-5 shows the correspondence between data input (D7-D0) and
channels.

Table 9-5 Correspondence between D7-D0 and channels

Data bus

Corresponding channel

D7 D6 D5 D4 D3 D2 D1 D0

CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1

22/31

¡ Semiconductor MSM9810

When the STOP command is input, the LSI stops processing of voice synthesis of the corresponding
channel at the rise of the WR pulse. When voice synthesis stops, the PCM value of that channel
is cleared to 1/2 VDD, and the NCR and BUSY channel status signals become “H”.

When “H” has been set at the START register, the START register is cleared to “L”.

9-3 LOOP Command

The LOOP command repeats a playback of voice synthesis of the channel corresponding to data
stored in the TMP registers. Table 9-6 shows the correspondence between data input (D7-D0) and
channels.

Table 9-6 Correspondence between D7-D0 and channels

Data bus

Corresponding channel

D7 D6 D5 D4 D3 D2 D1 D0

CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1

When the LOOP command is input, the LSI writes data of the TMP register to the LOOP register
at rise of WR pulse, and repeats a playback of the channel where “H” is set. Once “H” is set at
the LOOP register, playback continues until “L” is set from the outside. If the phrase controll table
function has been used for a phrase address, the edited voice is repeatedly played back.
To end a repeating playback, set the register of the channel to end the repeat to “L” using the
LOOP command again. When the register is set to “L”, repeating ends with the current playback
phrase. If the START register has been set to continue the playback of another phrase, another
phrase is played back continuously after repeating ends.
Figure 9-2 shows an example.

Channel 1

1 phrase

LOOP start

1 phrase 1 phrase

LOOP end

2 phrase

Figure 9-2 LOOP Command Execution Example

23/31

¡ Semiconductor MSM9810

9-4 OPT Command

The OPT command changes the setting inside the LSI according to data stored in the TMP
register. Table 9-7 shows the correspondence between data input (D7 to D0) and options.

Table 9-7 Correspondence between D7-D0 and options

D4

D3

0

0

1

1

Sets volume of all channels to V

0

Sets volume of all channels to 1/2V

1

Sets volume of all channels to 1/4V

0

Sets volume of all channels to 1/8V

1

Option

DD(P-P).

DD(P-P).

DD(P-P).

DD(P-P).

D2

0

Uses internal LPF.

1

Does not use internal LPF.

D1

0

Executes 2nd digital filter processing.

1

Executes 1st digital filter processing.

D0

0

Outputs directly from the D/A converter.

1

Outputs via a voltage follower.

Option

Option

Option

(Input “L” to D7-D5.)

When the OPT command is input, the LSI changes the option at the rising edge of the WR pulse.
When power is turned on, or when the RESET pulse is input, the registers corresponding to D3­D0 have been set to “L”.
If the option is changed when voice synthesis is in execution, voice quality may change. Oki
recommends to set the option after power is turned on or after RESET is input.

1) Volume Option

Volume can be set by the CVOL command and PAN command, but a waveform may be clamped
when channel synthesis is executed.
If the CVOL command and PAN command are used to prevent a waveform from being clamped,
the number of steps used for actual volume decreases, and effective voice synthesis may not be
performed.
If it is known that a waveform will be clamped, this option can set the volume of all channels to
low, so that the number of steps of the volume can be utilized to the maximum level.

2) Digital Filter Processing

This LSI has a built-in oversampling circuit for digital filter processing. This oversampling
system evenly generates four times more points of sampling frequencies.
When power is turned on or if the RESET pulse is input, those pulses have been set to pass
through the oversampling circuit. If digital filter processing is unnecessary, change this setting
by the OPT command.

24/31

¡ Semiconductor MSM9810

3) Analog Output

When power is turned on, it has been set that the output of the D/A converter is output via the
voltage follower. To change this setting, use the OPT command.
The output impedance of analog signals being output via the voltage follower is about 500W.
The output impedance of analog signals directly output from the D/A converter is about 30kW.

9-5 MUON Command

The MUON command inserts silence into the specified channel at the rise of the WR pulse. The
length of silence is according to the size of data stored in the TMP register.
The length of silence data is input in advance, before executing the MUON command. Silence
length can be set for 255 steps, 4 ms to 1020 ms, in 4 ms intervals. Silence time can be set as follows.

tmu = (27 ¥ (D7) + 26 ¥ (D6) + 25 ¥ (D5) + 24 ¥ (D4) + 23 ¥ (D3) + 22 ¥ (D2) + 21 ¥ (D1) + 20 ¥ (D0)
¥ 4.096 ms

The operation of the MUON command is similar to the START command to start voice synthesis.
When the MUON command is input, “H” is set to the START register, and NCR and BUSY signals
becomes “L”.
If the MUON command is input when voice synthesis is in execution, silence time is inserted after
voice synthesis ends.
Input the MUON command when the status signal (NCR or BUSY) of the channel to start voice
synthesis is at “H”. When NCR is “L”, input is disabled.

Figure 9-3 shows a flow chart example when the MUON command is input.

RD pulse input

NCRn="H"

YES

Subcommand input

MUON command input

NO

NCRn corresponding to each channel
is output to D7-D0.

Check that D7-D0 corresponding to the
channel to insert silence is "H".

After setting time of inserting silence from
the data bus, input WR pulse (set CMD to "H").

Specify channel by silence command.

Figure 9-3 MUON Command Input Flow

25/31

¡ Semiconductor MSM9810

9-6 FADR Command

The FADR command transfers data stored in the TMP register to the phrase address register of
the corresponding channel at the rise of the WR pulse.

For the phrase address, the user specification phrases have been set by an analysis tool, and the
playback system, sampling frequency and start and stop address of voice data have been
registered to the address management area.
When the phrase address is set and the START command is input, the LSI reads data of the
address management area, and starts voice synthesis.
Since the phrase address is set by D7-D0, a maximum of 256 phrases can be set. The edit function
can be used for phrase addresses, so not only one phrase but combinations with other phrases
are possible.

9-7 DADR Command

The DADR command transfers data stored in the TMP (1-7) register to the start and stop address
register of the corresponding channel at the rise of the WR pulse.
For the direct address, the playback system, sampling frequency, and start and stop address of
voice data is directly input from the microcomputer without using the address management
area.
Direct address playback system is available with channel 1 to 4, and not available with channel
5 to 8.
Since the phrases that can be set at a phrase address is a maximum of 256, if voice data exceeds
256 phrases, use this command. Data on the playback system, sampling frequency, and start and
stop address of voice data is displayed when an analysis tool is used.
Data on the playback system, sampling frequency, and start and stop address of voice data is
input to the TMP1 to TMP7 registers divided in 7 steps, unlike the data input of other commands.
Figure 9-4 shows the input method.

CMD(I)

CS(I)

WR(I)

D7 - D0(I)

Stores TMP1

register data

Stores TMP2

register data

Figure 9-4 DADR Input Timing

Stores TMP3

register data

Stores TMP4

register data

Stores TMP5

register data

Stores TMP6

register data

Stores TMP7

register data

Executes command

26/31

¡ Semiconductor MSM9810

As Figure 9-4 shows, CS and WR pulses are input 7 times when CMD is in “H” status, to input
data to the TMP1 to TMP7 registers. The LSI increments the registers at the rise of the WR pulse
when CMD is “H”. CMD must not be “L” while inputting data. When CMD becomes “L” while
inputting data, the increment of registers is cleared.

Table 9-8 shows the configuration of data to be input to TMP1 to TMP7 registers.

Table 9-8 TMP Register Data Configuration

D7 D6 D5 D4 D3 D2 D1 D0

TMP1 register

TMP2 register

TMP3 register

TMP4 register

TMP5 register

TMP6 register

TMP7 register

A23 A22 A21 A20 A19 A18 A17 A16

A15 A14 A13 A12 A11 A10 A9 A8

A7 A6 A5 A4 A3 A2 A1 A0

T23 T22 T21 T20 T19 T18 T17 T16

T15 T14 T13 T12 T11 T10 T9 T8

T7 T6 T5 T4 T3 T2 T1 T0

S3 S2 S1 S0 P1 P0 0 0

Input the start address of voice data to TMP1 to TMP3 registers. Input the stop address of voice
data to TMP4 to TMP6 registers.

Input the playback system and sampling frequency to the TMP7 register. Table 9-9 shows the
input data configuration of the playback system and sampling frequency.

Table 9-9 Data Configuration of Playback System and Sampling Frequency

S3

S2

0

0

0

0

0

0

0

0

1

0

1

0

1

0

0

1

0

1

0

1

S1

P1

S0

Sampling frequency 4.0kHz

0

0

Sampling frequency 8.0kHz

1

0

Sampling frequency 16.0kHz

0

1

Sampling frequency 32.0kHz

1

1

Sampling frequency 6.4kHz

1

0

Sampling frequency 12.8kHz

0

1

Sampling frequency 25.6kHz

1

1

Sampling frequency 5.3kHz

1

0

Sampling frequency 10.6kHz

0

1

Sampling frequency 21.3kHz

1

1

P0

Playback system: 4-bit ADPCM

0

0

Playback system: 4-bit ADPCM2

1

0

Playback system: 8-bit non-linearPCM

0

1

Playback system: 8-bit straight PCM

1

1

27/31

¡ Semiconductor MSM9810

9-8 CVOL Command

The CVOL command adjusts the volume of the specified channel to the volume which corresponds
to the size of data stored in the TMP register at the rise of the WR pulse.

Volume can be set in 16 steps up to -30 dB in -2dB step units. Set data as shown in Table 9-10.

Table 9-10 Volume Setting Data Configuration

D2

D1

D3

0

0

0

0

0

0

0

0

1

0

1

0

1

0

1

0

0

1

0

1

0

1

0

1

1

1

1

1

1

1

1

1

D0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

Volume (dB)

0

0dB

1

–2dB

0

–4dB

1

–6dB

–8dB

0

–10dB

1

–12dB

0

–14dB

1

–16dB

0

–18dB

1

–20dB

0

–22dB

1

–24dB

0

–26dB

1

–28dB

0

–30dB

1

(D7-D4 : Don't care)

When power is turned on and the RESET pulse is input, all channels are set to 0dB.

28/31

¡ Semiconductor MSM9810

9-9 PAN Command

The PAN command adjusts the volume of the specified channel for the left and right respectively,
to the volume which corresponds to the size of data stored in the TMP register at the rise of the
WR pulse.
This command enables stereo output.
When volume is controlled by the OPT command and CVOL command, volume to be output is
the volume stored in ROM multiplied by volume set by the OPT command, CVOL command,
and PAN command respectively. This volume is output from LDAO and RDAO.
Volume can be set in 16 steps up to –30 dB in –2 dB step units. Set data as shown in Table 9-11.

Table 9-11 PAN Data Configuration

D7

D3

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

D6

D2

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

D5

D1

Volume at left side

D4

Volume at right side

D0

0

0

0

1

1

0

1

1

0

0

0

1

1

0

1

1

0

0

0

1

1

0

1

1

0

0

0

1

1

0

1

1

0dB

–2dB

–4dB

–6dB

–8dB

–10dB

–12dB

–14dB

–16dB

–18dB

–20dB

–22dB

–24dB

–26dB

–28dB

–30dB

29/31

MCU M9810

74HC139

Y3

2B

Y2

2AY1Y0

2G1G

M274000 M274000 M274000 M274000

APPLICATION CIRCUITS

¡ Semiconductor MSM9810

30/31

SI
SO

CMD
CS
WR
RD
RESET

SERIAL
NCR/BUSY

RCS

TEST1
TEST2
TEST3

RA20
RA19SD

RA18-0

RD7-0

ROE

LDAO

RDAO

XTXT

AMP

AMP

19

CE

A18-0

8

D7-0

OE OE OE OE

CE

A18-0

D7-0

CE

A18-0

D7-0

CE

A18-0

D7-0

Application circuit example when four 4Mbit EPROMs are connected (serial interface)

¡ Semiconductor MSM9810

PACKAGE DIMENSIONS

(Unit : mm)

QFP64-P-1414-0.80-BK

Mirror finish

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more

0.87 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

31/31

E2Y0002-29-62

NOTICE

1. The information contained herein can change without notice owing to product and/or

technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.

2. The outline of action and examples for application circuits described herein have been

chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.

3. When designing your product, please use our product below the specified maximum

ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.

4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or

unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.

5. Neither indemnity against nor license of a third party’s industrial and intellectual property

right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.

6. The products listed in this document are intended for use in general electronics equipment

for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.

7. Certain products in this document may need government approval before they can be

exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.

8. No part of the contents contained herein may be reprinted or reproduced without our prior

permission.

9. MS-DOS is a registered trademark of Microsoft Corporation.

Copyright 1999 Oki Electric Industry Co., Ltd.

Printed in Japan