The MSM9000B-xx is a dot-matrix LCD control driver which has functions of displaying 12 (5
x 7 dots) characters (2 lines) and 120-dot arbitrators.
The MSM9000B-xx is provided with a 16-dot common driver, 60-dot segment driver, Display
Data RAM (DDRAM), and Character Generator ROM (CGROM).
This device can be controlled with commands entered through the serial interface or parallel
interface.
The font data in the CGROM can be changed by mask option.
Since the MSM9000B-xx has an LCD driving bias generator circuit, LCD bias voltages can be
obtained by merely providing a required capacitance externally.
The MSM9000B-xx is applicable to a variety of LCD panels by controlling the contrast.
FEATURES
• Logic voltage(VDD): 2.5 to 3.3 V
• LCD driving voltage(VBI) : 3.0 to 5.5 V
• Low current consumption: 35 mA max.(operating)
• Switchable between 8-bit serial interface and 8-bit parallel interface
• Contains a 16-dot common driver and a 60-dot segment driver
• Contains CGROM with character fonts of (5 x 7 dots) x 256
Power supply voltageV
Bias voltageV
Input voltageV
DD
Ta=25°C, V
BI
I
Ta=25°C, VDD–V
DD–VSS
SS5
Ta=25°CV
–0.3 to +4.6
–0.3 to +7V
–0.3 to VDD + 0.3
Applicable pin
V
V
, V
DD
SS
, V
V
DD
SS5
All input pins
Chip–55 to +150
Storage temperature
T
STG
TCP–30 to +85
°C
—
Ta: Ambient temperature
RECOMMENDED OPERATING CONDITIONS
ParameterSymbolConditionRangeUnit
Power supply voltageV
Bias voltageV
IC source oscillationf
Operating temperature—–30 to +85T
DD
BI
int
op
*1 VDD is the highest pin and V
V
DD–VSS
*1, VDD–V
SS5
*2kHz
the lowest for the bias voltage.
SS5
2.5 to 3.3
3 to 5.5V
26 to 47
°C
*2 Connect the specified capacitors to the voltage doubler and LCD bias generator.
*3 Make sure that the crystal oscillation frequency or the divided clock frequency falls within
this range.
Applicable pin
V
, V
V
DD
V
DD, VSS5
*3
—
SS
Note 1: Ensure the chip is not exposed to any light.
Note 2: The bias voltage may exceed 5.5 V at some contrast stages. Adjust the stage with
software so that the bias voltage does not exceed 5.5 V.
5/38
Page 6
¡ Semiconductor
MSM9000B-xx
ELECTRICAL CHARACTERISTICS
DC Characteristics (1)
(V
= 2.5 to 3.3 V, VBI = 3 to 5.5 V, Ta = –30 to +85°C)
DD
ParameterSymbolConditionMin.Typ.Max.Unit
Input high voltage 1V
Input high voltage 2V
Input low voltage 1V
Input low voltage 2V
Input high current 1
Input high current 2
Input low current 1
Off leakage current
Output high voltage 1
Output low voltage 1VSO and DB0 to
COM output resistance
I
I
I
V
IH1
IH2
IL1
IL2
IH1
IH2
IL1
off
OH
OL1
C
S
—V
—0.8V
–0.25—V
DD
DD
—VDDVOther inputs
DD
—0—0.55V
—0—0.2V
VI=V
VI=V
DD
DD
—— 1
10—60
VI=0 V–1——
/0 V–1—1
V
I=VDD
I
=–500 mA
O
IO=500 mAV
=±50 mAR
I
O
I
=±20 mAR
O
0.9V
DD
——
——0.1V
——10
——30SEG output resistancekWSEG1 to SEG60
DD
DD
During operation *1
Drain current 1
DD1
Crystal oscillation
—1535
f = 32.768 kHz
During operation *1
Drain current 2
I
DD2
External clock
—1535mA
f = 32 kHz
Applicable pin
XT
V
XT
VOther input pins
Input pins other
mA
than XT and TEST
TEST (pull-down
mA
resistor)
mA
Input pins other
than XT and TEST
SO and DB0 to
mAI
DB7
V
SO and DB0 to
DB7
DB7
kWCOM1 to COM16
mAI
V
DD
V
DD
I
DD3
During standby
—— 7Drain current 3mAV
*1 No output load
Note : The values in this table are assured when the chip is not exposed to light.
DD
6/38
Page 7
¡ Semiconductor
MSM9000B-xx
DC Characteristics (2)
=0 V, VSS=–3 V, Ta=–30 to +85°C)
(V
DD
ParameterSymbolConditionMin.Typ.Max.Unit
Bias voltage 1–V
SS1
–V
= "A"V1/2A–0.11/2A1/2A+0.1V
SS2, 3
Applicable pin
V
N1 = "L", N2 = "L"
Bias voltages 2 and 3–V
Bias voltage 4–V
Bias voltage 5
Contrast pitch
–V
–V
SS2, 3
SS4
SS5
con
Contrast = "5"
–V
–V
= "A"V3/2A–0.13/2A3/2A+0.1VV
SS2, 3
= "A"V2A–0.22A2A+0.2
SS2, 3
VBI for each stage0.180.210.26
1.92.22.5VV
V
V
V
Note 1: Connect a 0.1 µF capacitor to the LCD bias generator.
Note 2: The values in this table are assured when the chip is not exposed to light.
AC Characteristics
Parallel interface
(VDD=2.5 to 3.3 V, VBI=3 to 5.5 V, Ta=–30 to +85°C)
ParameterSymbolConditionMin.
RD high-level widtht
WR high-level widtht
WR low-level width—t
WR-RD high-level width—t
CS or C/D setup time—t
CS or C/D hold time—t
Write data setup time—t
Write data hold time—t
Read data output delay timeCL=50 pFt
Read data hold time—t
External clock high-level width—t
External clock low-level width—t
RESET pulse width—t
Rise and fall time of external
clock
WRH
WRL
WWH
WWL
WWRH
AS
AH
DSW
DHW
DDR
DHR
WCH
WCL
WRE
, t
r
—200
—RD low-level widtht
200
—200
200
200—ns
50—ns
0—ns
50—ns
50—ns
—200ns
20—ns
1—ms
1—ms
2.0—ms
f
—t
—100ns
Max.
—
—
—
—
SS1
SS2, 3
SS4
SS5
—
Unit
ns
ns
ns
ns
Note:The values in this table are assured when the chip is not exposed to light.
(VDD = 2.5 to 3.3 V, VBI = 3 to 5.5 V, Ta = –30 to +85°C)
Max.
—100
—CS or C/D hold timet
20
—100
20
—
—
—
—
100—ns
100—ns
400—ns
—200ns
0200ns
—100ns
—200ns
200—ns
120—ns
2.0—ms
f
—t
—100ns
Unit
ns
ns
ns
ns
Note:The values in this table are assured when the chip is not exposed to light.
8/38
Page 9
¡ Semiconductor
Timing Diagram for the Parallel Interface
—
V
CS
C/D
WR
IH
—
V
IL
—
V
IH
—
V
IL
t
AS
—
V
IH
—
V
IL
t
WRH
t
WWL
MSM9000B-xx
t
AH
t
WWH
t
WWRH
t
AS
t
WRL
t
AH
RD
DB0-7
RESET
XT
—
V
IH
—
V
IL
t
DSW
V
IH
V
IL
t
WRE
—
V
IL
t
r
—
V
IH
—
V
IL
t
DHW
t
f
t
WCL
t
DDR
V
OH
V
OL
t
WCH
t
DHR
V
IH
V
OH
= 0.8VDD,
= 0.9VDD,
V
V
= 0.2V
IL
OL
= 0.1V
DD
DD
9/38
Page 10
¡ Semiconductor
Timing Diagram for the Serial Interface
—
V
CS
C/D
SI
SHT
IH
—
V
IL
—
V
IH
—
V
IL
—
V
IH
—
V
IL
t
SAS
—
V
IH
t
t
IS
IH
50%
—
V
IL
t
WSHL
t
WSHH
t
SHS
MSM9000B-xx
t
SAH
WR
SO
RESET
XT
—
V
IH
—
V
IL
t
ON
—
V
OH
V
OL
V
IL
"Z"
—
—
t
—
V
IH
—
V
IL
t
SYS
t
DS
t
WWLtBUSY
t
OFF
"Z"
t
WRE
t
r
f
V
= 0.8 VDD,
IH
V
= 0.2 V
IL
DD
V
OH
= 0.9 VDD,
V
OL
= 0.1 V
DD
10/38
Page 11
¡ Semiconductor
MSM9000B-xx
FUNCTIONAL DESCRIPTION
Pin Functional Description
• CS (Chip Select)
Chip select input pin. A logic low on the CS input selects the chip and a logic high on the CS
input does not select the chip. Command and display data inputs can be enabled only when
the chip is selected.
When the input is high, the SO pin and DB0 to DB7 pins are in the high impedance state,
causing SHT, WR and RD pins high level internally.
• WR (Write Enable)
When the parallel interface is used, this pin is the write signal input. Data is written into the
register at the rising edge of WR pulse. When the serial interface is used, this pin is the latch
signal input. This pin is normally high.
• RD (Read Enable)
When the parallel interface is used, this pin is the read signal input. While the pulse is low,
data can be read. The pin is normally high. When this pin is made low with C/D set low, the
display data pointed to by the address pointer is output from DB0 to DB7. When the pin is
made low with C/D set high, busy data is output from DB0 and low signals are output from
DB1 to DB7. After the rising edge of WR, busy data (H) is output. The data automatically
changes to non-busy (L) after the specified time elapses.
When the serial interface is used, fix this pin to "H" or "L".
•C/D (Command/Data Select)
This input pin selects whether the data to be input to the SI pin and the DB7 to DB0 pins is
handled as a command or display data, depending on the state of the pin at the rising edge
of WR. When the pin is H, the input data is handled as a command. When the pin is L, display
data is input.
• DB0 to DB7 (Data Buses 0 to 7)
Data input and output pins for the parallel interface. Normally data buses 0 to 7 are in high
impedance, when RD is driven low, display data and the busy signal are output.
When the serial interface is used, leave this pin open.
• SI (Serial Data Input)
Data input pin for the serial interface. Commands and display data are read at the rising edge
of SHT and written to registers at the rising edge of WR. The eight-bit data immediately before
the rising edge of WR is valid.
When the parallel interface is used, fix this pin to "H" or "L".
• SO (Serial Data Output)
Data output pin for the serial interface. The display data pointed to by the address pointer is
output at the rising edge of SHT. After the rising edge of WR, busy data (H) is output.
The data automatically changes to non-busy (L) after the specified time elapses.
When the parallel interface is used, this pin remains in the high impedance state.
• SHT (Shift Clock)
Clock input pin to input and output serial interface data. Data input is synchronous with the
rising edge of the clock, and the data output is synchronous with the falling edge of the clock.
This pin is normally high.
When the parallel interface is used, fix this pin to "H" or "L".
11/38
Page 12
¡ Semiconductor
MSM9000B-xx
• XT (Crystal)
Input pin for crystal oscillation. By connecting a 32.768-kHz crystal and capacitors to this pin
and the XT pin, a crystal oscillation circuit is formed. When an external clock is used, input
the clock to the XT pin.
• XT (Crystal)
Output pin for crystal oscillation. By connecting a 32.768-kHz crystal and capacitors to this
pin and the XT pin, a crystal oscillation circuit is formed. When the external clock is used,
leave this pin open.
XT
18 pF
XT
18 pF
32.768 kHz
When forming a crystal oscillation circuitWhen inputting an external clock
XT
XT
External
clocks
OPEN
Oscillation circuit diagram
• P/S (Parallel/Serial Select)
Input pin to choose between the parallel interface and serial interface. To select the parallel
interface, make this pin low. To select the serial interface, make this pin high. After power
is turned on, do not change the setting of this pin.
• 9D/16D (Duty Select)
Input pin to set a duty cycle. When this pin is set to "H", a duty cycle of 1/9 is selected.
When the pin is set to "L", a duty cycle of 1/16 is selected. Choose either according to the panel
to be used. When a duty cycle of 1/9 is chosen, leave common output pins COM10 to COM16
open.
• 32K/EXT (Clock Select)
Input pin to choose crystal oscillation mode or external clock input mode. Leave this pin at
a "L" level.
• RESET (Reset)
Reset signal input pin. Setting this pin to L results in the initial state. For modes and the
display after a reset input, see "Mode Settings after a Reset Input".
• N1, N2 (Contrast Change)
Input pins that determine the voltages of V
SS2
and V
together with contrast adjustment by
SS3
a command. The table below shows the relationships between pin states and contrast
adjustment ranges.
12/38
Page 13
¡ Semiconductor
MSM9000B-xx
N1N2
LL
LH
HL
HH
Contrast adjustment range by command
0 to 7
1 to 8
2 to 9
3 to A
• TEST (Test Signal)
Test signal input pin provided for test by the manufacturer. Fix this pin to L or leave it open.
• SEG1 to SEG60 (Segment 1 to Segment 60)
Segment signal output pins to drive the LCD. Leave the unused pins open.
• COM1 to COM16 (Common 1 to Common 16)
Common signal output pins to drive the LCD. When the duty cycle is 1/9, use COM1 to COM9
and leave COM10 to COM16 open.
•V
DD
Power supply pin to the logic section. Connect this pin to the positive terminal on the power
supply.
•V
SS
Pin to be connected to the GND power supply.
•V
SS1
, V
SS4
, V
SS5
Pins for voltage multiplier outputs and LCD power supply. Connect capacitors of 0.1 µF
between these pins and VDD for the charge distribution with V
capacitor and for voltage
SS2, 3
stabilization during generation of LCD bias voltages. The logical values of the LCD bias
voltage are as follows:
Highest voltage: V
Lowest voltage: V
DD
V
SS1=VSS2, 3
V
SS2, 3
V
SS4=VSS2, 3+VSS2, 3
SS5=VSS2, 3+VSS2, 3
/2
/2
/2+V
SS2, 3
/2
For both the 1/9 and 1/16 duty, 1/4 bias is used.
•V
SS2, 3
Voltage regulator output pin & LCD bias generator input used as a reference voltage for the
LCD bias generator.
Connect a capacitor of 0.1 µF between this pin and V
for charge distribution among
DD
capacitors and voltage stabilization during generation of various LCD bias voltages.
•V
SS6
Pin to connect the capacitor to store the 3-/2-fold voltage. Connect a capacitor of 0.1µF or more
between this pin and VDD.
•V
SH
Halves output pin for the voltage multiplier(3-/2-fold). Connect a 0.1 µF capacitor between
this pin and VDD.
13/38
Page 14
¡ Semiconductor
MSM9000B-xx
•VC1, V
CC1
Pins to connect the charge distribution capacitor used for the voltage malitiplier (3-/2-fold).
Connect a 0.1 µF capacitor between V
•VC2, V
CC2
and V
C1
CC1
.
Pins to connect the capacitor for charge distribution to generate LCD bias voltages on the basis
of V
. Connect a 0.1 µF capacitor between V
SS2, 3
and V
C2
CC2
.
14/38
Page 15
¡ Semiconductor
Parallel Interface Input-Output Timing
Input timing diagram
CS
C/D
MSM9000B-xx
DB7-0
WR
Output timing diagram
CS
C/D
RD
DATA
"H""L"
DB7-1
DB0
DATA"L"
DATA
When C/D="L", RAM display data is output on DB7-0 pins.
When C/D="H" and DB7-1="L", busy data is output on DB0 pin.
BUSY
15/38
Page 16
¡ Semiconductor
I/O Timings on the Serial Interface
Input timing diagram
CS
C/D
SHT
MSM9000B-xx
SI
WR
D7D6D5D4
Output timing diagram
CS
C/D
SHT
D3
D2D1D0
SO
WR
BUSYBUSY
D7D6D5D4
D3
D2D1D0
In SO output, the eight bits after the WR pulse is input are valid.
16/38
Page 17
¡ Semiconductor
MSM9000B-xx
LIST OF COMMANDS
*: Don't Care
No
Mnemonics
1LPALoad Pointer
2 LOTLoad Option 1011**I1I0Sets additional functions during execution of AINC.
3SFSet Frequency1010**F1F0Sets conditions on master frequency.
4BKCG 1/0Bank Change 1/0 100*0001/0Valid only in 1/9 duty.
5CONT U/DContrast
Operation
76543210
11A5 A4 A3A2 A1A0 Addresses 0-11, 16-27 for characters and
Address
100*0011/0Adjusts VLCD to 8 stages.
Up/Down
D
Comments
addresses 32-43, 48-59 for arbitrators
Changes display addresses 0-11, 16-27.
Adjustment range is changed by setting N1 and
N2 pins.
Contrast level is up if D0="1".
Contrast level is down if D0="0".
6STOPSet
Stop Mode
7SOE/DSerial Out
Enable/Disable
8DISPDisplay On/Off1001/01001/0 Display is ON if D0="1". Display is OFF if D0=0.
9AINCAddress
Increment
10ABBArbitrator Blink100*1101/0Data that is input after setting D0="1", is set as data
11CHBCharacter Blink000*001/0*Controls blinking of character.
12BPCBlink Pattern
Control
13ABLCArbitrator Line
Change
100*0100This mode is cancelled if D0="1" irrespective of
either "H" or "L" on C/D.
Stops oscillation and performs operation
equivalent to that of the DISP OFF command.
100*0111/0Switches between output and high impedance
of SO.
All commons and segments are at V
display is OFF.
Arbitrators alone are displayed if D4="1".
100*101*Pointer address is incremented by 1.
But, this command is invalid to operations that
are added by setting (I1, I0).
for arbitrator blink (1-dot unit).
This is cancelled by D0="0".
100*1111/0Sets blink patterns of characters.
( : chara) if D0="1", ( : chara) if D0="0".
011***L1L0Sets arbitrator display lines.
level if
DD
Notes :1 Pointer address is not changed even if commands numbers 1 to 8, 10, 12, 13 are enterd.
:2 Pointer address is automatically incremented by 1 when commands numbers 9, 11,
display code data, and arbitrator data are enterd.
17/38
Page 18
¡ Semiconductor
•LOT
I1I0RemarksAdditional function
00
01
10
11
No additional function
A blank code is written for each subsequent AINC.
Blinking is canceled for each subsequent AINC.
The above two functions are ORed.
•SF
F1F0RemarksFrequency of source oscillation in the IC
00
01
10
11
XT
XT ∏ 2
XT ∏ 4
XT ∏ 8
MSM9000B-xx
Used to automatically clear RAM at power-on.
Used to generate the optimum frequency when external
clocks are input.
•DISP
D4D0CharacterArbitratorRemarks
*0
01
11
OFFOFF
ONON
OFFON
Used to turn on and off the display.
* : Don't care
•ABLC (when the duty is 1/16)
L1L0Arbitrator 1Arbitrator 2Remarks
00
01
1*
COM1COM2
COM15COM16
COM16COM1
Arbitrator 1 indicates display data at addresses
32 to 43, while arbitrator 2 indicates display data
at addresses 48 to 59.
* : Don't care
•ABLC (when the duty is 1/9)
L1L0Arbitrator 1Arbitrator 2Remarks
00
01
1*
COM1COM2
COM8COM9
COM9COM1
Arbitrator 1 indicates display data at addresses
32 to 43, while arbitrator 2 indicates display data
at addresses 48 to 59.
* : Don't care
18/38
Page 19
¡ Semiconductor
MSM9000B-xx
Explanation of Commands
[D7, D6, D5, D4, D3, D2, D1, D0], X = Don't care
• LPA (Load Pointer Address)
[1, 1, A5, A4, A3, A2, A1, A0]
This command sets in the address pointer the address of the command to be executed or the
address of the display data to be input. The settable addresses are inconsecutive addresses
00H to 0BH, 10H to 1BH, 20H to 2BH, 30H to 3BH represented by A5 to A0. When addresses
0CH to 0FH, 1CH to 1FH, 2CH to 2FH, or 3CH to 3FH are set, 00H is assumed.
After RESET = "L", the address is set to 00H.
• LOT (Load Option)
[1, 0, 1, 1, X, X, I1, I0]
This command executes the additional function specified by I1 and I0 to the display of the
current address when the AINC command is executed. Additional functions are shown
below.
After RESET = "L",, both I1 and I0 are set to "0".
I1I0Additional function
00
01
10
11
None
After this command is executed, the blank code is writtern each time AINC is executed.
After this command is executed, blinking is canceled each time AINC is executed.
The above two additional functions are ORed.
• SF (Set Frequency)
[1, 0, 1, 0, X, X, F1, F0]
This command sets the number by which the external clock input from the XT pin is divided
in order to get the source frequency inside the IC. This command is valid when 32K/EXT pin
is "L". The dividing ratio is specified by F1 and F0 in the command. The table below lists the
source oscillation frequencies in the IC.
After RESET = "L", both F1 and F0 are set to "0".
F1F0Frequency of source oscillation in the IC
00
01
10
11
XT
XT ∏ 2
XT ∏ 4
XT ∏ 8
• BKCG1/0 (Bank Change 1/0)
[1, 0, 0, X, 0, 0, 0, 1/0]
This command changes addresses (banks) to be displayed. The command is valid only when
the duty is 1/9. When D0 is 0, addresses 0 to 11 (character 1), 32 to 43, and 48 to 59 (arbitrators
1 and 2) are displayed. When D0 is "1", addresses 16 to 27 (character 2), 32 to 43, and 48 to 59
(arbitrators 1 and 2) are displayed. The command and display data can be set regardless of
the bank setting.
After RESET = "L", D1 is set to "0".
19/38
Page 20
¡ Semiconductor
MSM9000B-xx
• CONT U/D (Contrast Up Down)
[1, 0, 0, X, 0, 0, 1, 1/0]
This command selects the voltage of V
bias. When the value of V
is changed, the contrast is changed accordingly.
SS2, 3
that is used as the reference voltage for the LCD
SS2, 3
The contrast is controlled by the value of the 3-bit up/down counter so that eight stages are
supported. The value of the up/down counter is incremented when "1" is entered by this
command and decremented when "0" is entered. The counter changes within the range of 0
to 7.
When the counter reaches 7, it goes back to "0".
According to the settings of N1 and N2, the contrast stages can be changed to 1 to 8, 2 to 9, or
3 to A.
At stage 0, the bias voltage is minimized. The larger the contrast stage, the higher the bias
voltage. At stage A, the bias voltage is maximized.
After a low RESET is input, the counter is set to the minimum value specified by N1 and N2.
Example: · · · 6´7´0´1´2´3´4´5´6´7´0 · · ·
Note: At some contrast stages, the bias voltage may be increased to 5.5 V or higher. Adjust
the stage so that the bias voltage does not exceed 5.5 V.
• STOP (Set Stop Mode)
[1, 0, 0, X, 0, 0, 1, 0]
This command sets standby mode. Specifically, the command stops the oscillation block to
prevent current form flowing through the oscillation block and outputs the VDD level to all
LCD output pins. Standby mode is canceled when D0 is set to "1" regardless of the setting of
the C/D pin. When a command or data with D0 set to "1" is entered, the command is executed
or the data is input. At the same time, standby mode is canceled.
After RESET = "L", standby mode is disabled.
• SOE/D (Serial Out Enable/Disable)
[1, 0, 0, X, 0, 1, 1, 1/0]
This command controls the impedance of the SO output pin. The command is valid only when
the serial interface is used. When D0 is set to "0", the SO pin is set in the high impedance state.
After RESET = "L", D0 is set to "0".
• DISP (Display On/Off)
[1, 0, 0, 1/0, 1, 0, 0, 1/0]
This command sets LCD display mode. When D0 is set to "1", the LCD is turned on. When
D0 is set to "0", the LCD is turned off, in which case, the VDD level is output to all segment and
common pins. When the LCD is turned ON (D0="1"), and D4 is set to "1", only arbitrators are
displayed and when D4 is set to "0", both characters and arbitrators are displayed. The table
below lists display modes.
After RESET = "L", both D4 and D0 are set to "0".
D4D0CharactersArbitrators
X0
01
11
OFFOFF
ONON
OFFON
20/38
Page 21
¡ Semiconductor
[
][
]
MSM9000B-xx
• AINC (Address Increment)
[1, 0, 0, X, 1, 0, 1, X]
This command increments the value of the address pointer by one. Each time this command
is input, the value is incremented by one. Addresses are increased as follows: 00 to 11 Æ 16
to 27 Æ 32 to 43 Æ 48 to 59 Æ 00 ···. This cycle is repeated. The function specified by the LOT
command is performed for the previous address before the address incremented by one every
time this command is input.
• ABB (Arbitrator Blink)
[1, 0, 0, X, 1, 1, 0, 1/0]
This command turns arbitrator blinking on or off. Display data input after D0 is set to "1" is
handled as arbitrator blink data. Input blink data corresponds to dots of the arbitrator at the
same address on a one-to-one basis. When the dot is "1", blinking is enabled. When the dot
is "0", blinking is disabled. While the dot is blinking, it is turned on and off repeatedly.
Blinking can be specified for a dot for which enabling the arbitrator is not specified, but the
dot does not blink.
Dummy data must be set for arbitrator data D5 to D7. Data cannot be written to addresses 00
to 31 and 44 to 47.
After RESET = "L", D0 is set to "0".
• CHB (Character Blink)
[0, 0, 0, X, 0, 1, 1/0, X]
This command enables or disables character blinking. The command is executed for the
address pointed to by the address pointer. When D1 is set to "1", blinking is enabled. When
D1 is set to "0", blinking is disabled. During blinking, the turning on of all dots (5 ¥ 7 dots) and
character display are repeated. In another blinking pattern, the turning off of all dots and
character display are repeated. Either pattern is selected by the BPC command.
After RESET = "L", the value of the address pointer is automatically incremented by one.
• BPC (Blink Pattern Control)
[1, 0, 0, X, 1, 1, 1, 1/0]
This command selects a character blinking pattern. When D0 is set to "1", the turning on of
all dots (5 ¥ 7 dots) and character display are repeated. When D0 is set to "0", the turning off
of all dots and character display are repeated.
When D0 is "1" but the character is a blank, the character does not blink visibly. When D0 is
"0", the character does not blink visibly while all its dots are turned on.
After RESET = "L", D0 is set to "0".
D0 = "1"
D0 = "0"
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MSM9000B-xx
• ABLC (Arbitrator Line Change)
[0, 1, 1, X, X, X, L1, L0]
This command selects a common line for arbitrator display, according to the settings of L1 and
L0. The table below shows the relationships between L1 and L0 and displayed common lines,
assuming that the display data at addresses 00 to 11 is character 1, the display data at
addresses 16 to 27 is character 2, the display data at addresses 32 to 43 is arbitrator 1, and the
display data at addresses 48 to 59 is arbitrator 2. Different common lines are displayed for 1/
16 duty and 1/9 duty.
After a low RESET is input, both L1 and L0 are set to "0".
Common lines displayed by the ABLC command are as follows:
When 1/16 duty is chosen
L1L0Character 1Character 2Arbitrator 1
00
01
1X
COM3 to 9COM10 to 16
COM1 to 7COM8 to 14
COM2 to 8COM9 to 15
COM1
COM15
COM16
Arbitrator 2
COM2
COM16
COM1
When 1/9 duty is chosen
L1L0Character 1Character 2Arbitrator 1
00
01
1X
COM3 to 9
COM1 to 7
COM2 to 8
COM1
COM8
COM9
Arbitrator 2
COM2
COM9
COM1
Note: When 1/9 duty is chosen, characters 1 and 2 can be switched by changing the bank.
• Increment of the address pointer by one
When display data or arbitrator blink data is input or the AINC or CHB command is executed,
the address pointer is incremented by one.
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MSM9000B-xx
Mode Setting after a Reset Input
The table below lists the settings of individual modes during a RESET =L input.
CommandMode settingRemarks
LPA
LOT
SF
BKCG 1/0Display addresses 00 to 11 are set.D0 = "0"
CONT U/D—The control counter is set to 0 (Stage 0).
STOP—Standby mode is disabled.
SOE/DThe SO pin is set to the high impedance state.D0 = "0"
DISPBoth characters and arbitrators display mode is set, but the dispaly is
ABBDisplay data input mode is enabled.D0 = "0"
BPCBlink mode is such that the turning on of all dots and character display
ABLCArbitrator 1 corresponds to COM1, and arbitrator 2 corresponds to
The address pointer is set to "00".
Load Option command with no additional function.
The dividing ratio is set to 1.
turned off.
are repeated.
COM2.
• Even when a reset is input, display RAM is not initialized. To clear the display data, a blank
code must be written. (This can be done with an additional function of the AINC command.)
Mode Settings during Standby
The table below lists the settings of individual modes during standby.
CommandMode settingRemarks
LPA
LOT
SF
BKCG 1/0
CONT U/D—The count before standby mode is retained.
STOP—Standby state 10. No change.
SOE/DThe setting before standby mode is retained.D0 = "0"
DISPBoth character and arbitrator display mode is set, but the display is
ABB
BPCThe setting before standby mode is retained.No change
ABLC
A5 to A0 = "0"
No change
D4 = "0", D0 = "0"
The address pointer is set to "00".
The setting before standby mode is retained.
turned off.
• Data before standby mode is retained in display RAM.
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Display Screen and Memory Addresses
Screen
MSM9000B-xx
Arbitrator 1
Arbitrator 2
Character 1
Character 2
Arbitrator 1
Arbitrator 2
Character 1
Character 2
RAM map
32334243
48495859
011011
16172627
Note:Characters are input as codes. Arbitrators are displayed directly without intervening
CG ROM. Input data is displayed as shown below.
D4
S5n+5S5n+1
D0
S: Segment
n: 0 to 11
Dummy data must be set for input data D7 to D5. Either "1" or "0" can be input as input data
of D7 to D5.
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MSM9000B-xx
Calculation Method of Various Kinds of Frequencies
Example
Source oscillation frequency = 32.768 kHz
Dividing ratio = 1/1
Clock cycle T
= 30.5 µs
S
Under these conditions, the blinking frequency can be calculated from expression (3) as
follows:
Blinking cycle Tf = 30.5 ¥ 10–6 ¥ 1 ¥ 215 = 1 s
Therefore
Blinking frequency = 1 Hz
• Source oscillation frequency and busy time
When data is written to or read from RAM or a command is input, data processing time (busy
time) is taken. The maximum busy time is the source clock cycle multiplied by 10. The busy
signal (not-busy = "L", busy = "H" ) is detected at the SO pin when the serial interface is used
or at the DB0 pin when the parallel interface is used. When display data or commands are
input consecutively, a wait must be inserted for the source clock cycle multiplied by 10.
Another way is to detect busy signals and input data or commands during not-busy time only.
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Flowchart at Power-on (parallel interface)
MSM9000B-xx
Turn on the power
Input a reset
="L"
CS
Set modes for SF, BKCG1/0,
BPC, and ABLC
LOT, I1="1", I0="1"
¥
AINC
LOT, I1="0", I0="0"
Input data to be displayed
on the initial screen
48 times
Input a reset after the V
5ms, external, or power-on reset
Chip enable.
Set a mode by the reset input according to specifications.
Set the load option. The blank code is written and
blinking is released each time AINC is executed.
RAM data is cleared.
The load option is cleared.
DD–VSS
level exceeds 2.5V.
NO
Has data to be displayed
on the initial screen been
input?
YES
DISP, D4="X", D0="1"
Perform ordinary operation
The display is turned on. The initial screen is displayed.
Set D4 according to the display.
• When the stage to be selected is already determined, contrast can be adjusted before the
display is turned on (for example, at the same time as when mode is set).
• After a command or display data is input, check for busy data. Make sure that the busy data
("H") has changed to not-busy data ("L") before making the next input.
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Flowchart at Power-on (serial interface)
MSM9000B-xx
Turn on the power
Input a reset
CS="L"
SOE/D, D0="1"
Wait for 10 clocks
Set modes for SF, BKCG1/0,
BPC, and ABLC
LOT, I1="1", I0="1"
AINC ¥ 48 times
LOT, I1="0", I0="0"
Input a reset after the VDD–VSS level exceeds 2.5V.
5ms, external, or power-on reset
Chip enable.
SO output is enabled to detect busy signal.
Insert a wait only in processing the SOE/D command.
(By busy signal detection for subsequent inputs).
Change the settings after a reset, if necessary.
Set the load option. The blank code is written and
blinking is disabled each time AINC is executed.
RAM data is cleared.
The load option is cleared.
Input data to be displayed
on the initial screen
NO
Has data to be displayed
on the initial screen been
input?
YES
DISP, D4="X", D0="1"
Perform ordinary operation
The display is turned on. The initial screen is displayed.
Set D4 according to the display.
• When the stage to be selected is already determined, contrast can be adjusted before the
display is turned on (for example, at the same time as when mode is set).
• After a command or display data is input, check for busy data. Make sure that the busy data
("H") has changed to not-busy data ("L") before making the next input.
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Flowcharts to Set and Cancel Standby Mode
Ordinary operation
MSM9000B-xx
NO
Busy signal detection
Not-busy?
YES
STOP
Standby mode
Standby mode
Set D0 to 1.
Confirm not-busy signal.
Set standby mode.
When the code in which D0 is set to 1 is input,
standby mode is canceled regardless of C/D input.
Wait until oscillation is stabilized.
Wait until voltage multiplier is stabilized.
Ordinary operation
The length of the wait depends on
the configuration of the oscillation circuit.