E2O0012-27-X2
¡ Semiconductor MSM82C84A-2RS/GS/JS
¡ Semiconductor
This version: Jan. 1998
Previous version: Aug. 1996
MSM82C84A-2RS/GS/JS
CLOCK GENERATOR AND DRIVER
GENERAL DESCRIPTION
The MSM82C84A-2RS/GS is a clock generator designed to generate MSM80C86A-10 and
MSM80C88A-10 system clocks of 8MHz.
Due to the use of silicon gate CMOS technology, standby current is only 40 mA (MAX.), and the
power consumption is very low with 16 mA (MAX.) when a 8 MHz clock is generated.
FEATURES
• Operating frequency of 6 to 24 MHz (CLK output 2 to 8 MHz)
•3 m silicon gate CMOS technology for low power consumption
• Built-in crystal oscillator circuit
• 3 V to 6 V single power supply
• Built-in synchronized circuit for MSM80C86A-10 and MSM80C88A-10 READY and RESET
• TTL compatible
• Built-in Schmitt trigger circuit (RES input)
• 18-pin Plastic DIP (DIP18-P-300-2.54): (Product name: MSM82C84A-2RS)
• 20-pin Plastic QFJ (QFJ20-P-S350-1.27): (Product name: MSM82C84A-2JS)
• 24-pin Plastic SOP (SOP24-P-430-1.27-K): (Product name: MSM82C84A-2GS-K)
FUNCTIONAL BLOCK DIAGRAM
RES
x
x
F/C
EFI
CSYNC
RDY
AEN
AEN
RDY
ASYNC
1
2
1
1
2
2
Crystal
Oscillator
D
Q
C
RESET
OSC
1
3
S
Y
N
C
1
2
S
Y
N
C
PCLK
CLK
C≠
D
Q
(F1)
CØ
D
(F2)
READY
Q
1/18
¡ Semiconductor MSM82C84A-2RS/GS/JS
PIN CONFIGURATION (TOP VIEW)
18 pin Plastic DIP
24 pin Plastic SOP
CSYNC
PCLK
AEN
RDY
READY
RDY
AEN
CLK
GND
CSYNC
READY
1
1
2
2
PCLK
NC
AEN
RDY
NC
RDY2
AEN
NC
CLK
GND
1
2
3
4
5
6
7
8
9
1
2
3
4
1
5
1
6
7
8
9
2
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
18
17
16
15
14
13
12
11
10
V
cc
X
1
X
2
NC
ASYNC
EFI
NC
F/C
OSC
NC
RES
RESET
V
CC
X
1
X
2
ASYNC
EFI
F/C
OSC
RES
RESET
20 pin Plastic QFJ
RDY
READY
RDY
AEN
NC
1
CC
AEN
PCLK
CSYNC
3
2
1
4
1
5
6
2
7
2
8
9
10
11
CLK
GND
RESET
V
20
12
RES
1
X
19
13
OSC
X
18
2
ASYNC
17
EFI
16
F/C
15
NC
14
(NC not connected)
2/18
¡ Semiconductor MSM82C84A-2RS/GS/JS
ABSOLUTE MAXIMUM RATINGS
Parameter Unit
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature
Power Dissipation
Symbol
V
CC
V
IN
V
OUT
T
STG
P
D
Condition
Respect
to GND
—
Ta = 25°C
MSM82C84A-2RS/JS
–0.5 to +7
–0.5 to V
–0.5 to V
–55 to +150
MSM82C84A-2GS
+0.5
CC
+0.5
CC
0.70.8
OPERATING RANGES
Rating
Parameter UnitSymbol
Supply Voltage
Operating Temperature
V
CC
T
op
Range
3 to 6
–40 to +85
RECOMMENDED OPERATING CONDITIONS
Parameter UnitSymbol
Supply Voltage
Operating Temperature
"L" Level Input Voltage V
"H" Level Input Voltage (except RES)
"H" Level Input Voltage (RES)
Min.
V
CC
T
op
IL
V
IH
4.5
–40
–0.5
2.2
0.6*V
CC
Typ.
5V
+25
—
—
Max.
+85
+0.8
V
CC
5.5
+0.5
V
V
V
°C
W
V
°C
°C
V
V
DC CHARACTERISTICS
Parameter
"L" Level Output Voltage (CLK) V
"L" Level Output Voltage (Others)
"H" Output Voltage (CLK)
"H" Output Voltage (Others) V
RES Input Hysteresis
Input Leak Current
(Except ASYNC)
Input Current (ASYNC)
Standby Supply Current
Operating Supply Current
Input Capacitance C
Note: 1. X1 ≥ V
F/C ≥ V
VIH ≥ V
– 0.2 V, X2 £ 0.2 V
CC
– 0.2 V, ASYNC = VCC or open
CC
– 0.2 V, VIL £ 0.2 V
CC
(V
= 5 V ± 10%, Ta = –40 to 85°C)
CC
Symbol Min.
OL
V
OL
V
OH
OH
V
IHR
-V
ILR
I
LI
I
LIA
I
CCS
I
CC
IN
I
= 4 mA
OL
= 2.5 mA
I
OL
I
= –4 mA
OH
I
= –1 mA
OH
0 £ V
0 £ V
Note 1
Condition
£ V
IN
CC
£ V
IN
CC
—
—
V
CC
CC
0.2*V
–1
—
–0.4
–0.4
CC
Max.
0.4
0.4
Unit
V
V
—V
—
—
+1
+10
40
VV
V
mA
mA–100
mA—
16 mAf = 24 MHz, CL= O PF
7
pFf =1 MHz —
3/18
¡ Semiconductor MSM82C84A-2RS/GS/JS
AC CHARACTERISTICS
(1)
= 5 V ± 10%, Ta = –40 to 85°C)
(V
CC
Parameter
EFI "H" Pulse Width
EFI "L" Pulse Width
EFI Cycle Time
Crystal Oscillator Frequency
Symbol
t
EHEL
t
ELEH
t
ELEL
—
Min. Max. Unit
13
17
36
—
—
—
6
24
ns
ns
ns
MHz
90% to 90%
10% to 10%
Conditions
—
—
Set up Time of RDY
or RDY 2 to
1
CLK Falling Edge (Active)
Set up Time of RDY
or RDY 2 to
1
CLK Rising Edge (Active)
Set up Time of RDY
or RDY 2 to
1
CLK Falling Edge (Inactive)
Hold Time of RDY
or RDY 2 to
1
CLK Falling Edge
Set up Time of ASYNC to CLK
Falling Edge
Hold Time of ASYNC to
CLK Falling Edge
Set up Time of AEN
RDY
(RDY 2) Rising Edge
1
Hold Time of AEN
(AEN2) to
1
(AEN2) to
1
CLK Falling Edge
Set up Time of CSYNC to EFI
Rising Edge
t
R1VCL
t
R1VCH
t
R1VCL
t
CLR1X
t
AYVCL
t
CLAYX
t
A1R1V
t
CLA1X
t
YHEH
35
35
35
50
15
20
—
ns
ASYNC
= High
—
ns
ASYNC
= Low
—
0
—
ns
ns
—
—
Output Load
Capacitance
—
0
—
—
0
—
—
ns
ns
ns
ns
ns
—
—
—
—
—
CLK output
= 100 pF
C
L
Others 30 pF
Hold Time of CSYNC to EFI
Rising Edge
CSYNC Pulse Width
Set up Time of RES to CLK Falling
Edge
Hold Time of RES to CLK Falling
Edge
Input Rising Edge Time
Input Falling Edge Time
t
EHYL
t
YHYL
t
I1HCL
t
CLI1H
t
ILIH
t
IHIL
2 ¥
10
65
20
—
—
t
ELEL
—
—
—
—
15
ns
ns
ns
ns
ns
15 ns
—
—
—
—
—
—
Note: Parameters where timing has not been indicated in the above table are measured at
VL = 1.5 V and VH = 1.5 V for both inputs and outputs.
4/18
¡ Semiconductor MSM82C84A-2RS/GS/JS
AC CHARACTERISTICS
(2)
(V
= 5 V ± 10%, Ta = -40 to 85°C)
CC
Parameter
CLK Cycle Time
CLK "H" Pulse Width
Symbol
t
CLCL
t
CHCL
Conditions
—
—
Min. Max. Unit
125
1
T
+ 2
CLCL
3
—
—
ns
ns
CLK "L" Pulse Width
CLK Rising and Falling Edge
Times
PCLK "H" Pulse Width
PCLK "L" Pulse Width
Time from READY Falling Edge
to CLK Falling Edge
Time from READY Rising Edge
to CLK Rising Edge
Delay from CLK Falling Edge
to RESET Falling Edge
Delay from CLK Falling Edge
to PCLK Rising Edge
Delay from CLK Falling Edge
to PCLK Falling Edge
Delay from OSC Falling Edge
to CLK Rising Edge
t
CLCH
t
CH1CH2
t
CL2CL1
t
PHPL
t
PLPH
t
RYLCL
t
RYHCH
t
CLIL
t
CLPH
t
CLPL
t
OLCH
—
1.0 V to 3.5 V
—
—
—
—
—
—
—
—
Output Load
Capacitance
CLK Output
= 100 pF
C
L
Others 30 pF
2
2
3
3
T
T
T
CLCL
CLCL
T
CLCL
CLCL
—
-8
—
—
—
–5
–20
–20
–15
–15
—
10
—
—
—
—
40
22
22
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
Delay from OSC Falling Edge
to CLK Falling Edge
Output Rising Edge Time
(Except CLK)
Output Falling Edge Time
(Except CLK)
t
OLCL
t
OLOH
t
OHOL
—
0.8 V to 2.2 V
2.2 V to 0.8 V
—
—
2
35
15
15
ns
ns
ns
Note: Parameters where timing has not been indicated in the above table are measured at
VL = 1.5 V and VH = 1.5 V for both inputs and outputs.
5/18
¡ Semiconductor MSM82C84A-2RS/GS/JS
PIN DESCRIPTION
Pin Symbol
Name
Input/Output
Clock
CSYNC
Synchronization
Single
PCLK
AEN
AEN
RDY
RDY
READY
CLK
RES
Peripheral Clock
1
Address Enable
2
1
2
Bus Ready
Ready Output Output
Clock Output
Output
Signals
Signals
Reset in Input
RESET Reset Output Output
Input
Output
Input
Input
Output
Function
Synchronizing signal for output of in-phase CLK signals when more
than one MSM82C84A-2 is used.
The internal counter is reset when this signal is at high level, and a
high level CLK output is generated. The internal counter is
subsequently activated and a 33% duty CLK output is generated when
this signal is switched to low level.
When this signal is used, external synchronization of EFI is necessary.
When the internal oscillator is used, it is necessary for this pin to be
kept to be low level.
This peripheral circuit clock signal is output in a 50% duty cycle at
a frequency half that of the clock signal.
The AEN
signal enables RDY1, and the AEN2 signal RDY2.
1
The respective RDY inputs are activated when the level applied to
these pins is low.
Although two separate inputs are used in multi-master systems, only
the AEN which enables the RDY input to be used is to be switched to
low level in the case of not using multi-master systems.
Completion of data bus reading and writing by the device connected
to the system data bus is indicated when one of these signals is
switched to high level.
The relevant RDY input is enables only when the corresponding AEN
is at low level.
This signal is obtained by synchronizing the bus ready signal with
CLK.
This signal is output after guaranteeing the hold time for the
CPU in phase with the RDY input.
This signal is the clock used by the CPU and peripheral devices
connected to the CPU system data bus. The output waveform is
generated in a 33% duty cycle at a frequency 1/3 the oscillating
frequency of the crystal oscillator connected to the X
and X2 pins,
1
or at a frequency 1/3 the EFI input frequency.
This low-level active input is used to generate a CPU reset signal.
Since a Schmitt trigger is included in the input circuit for this signal,
"power on resetting" can be achieved by connection of a simple RC
circuit.
This signal is obtained by CLK synchronization of the input signal
applied to RES and is output in opposite phase to the RES input.
This signal is applied to the CPU as the system reset signal.
F/C
EFI
X1, X
OSC
Clock Select
External Clock
Crystal Oscillator
2
Connecting Pins
Resonator
Signal
Signal
Crystal
Output
Input
Input
Input
Output
This signal selects the fundamental signal for generation of the CLK
signal. The CLK is generated from the crystal oscillator output when
this signal is at low level, and from the EFI input signal when at high
level.
The signal applied to this input pin generaters the CLK signal when
F/C is at high level. The frequency of the input signal needs to be
three times greater than the desired CLK frequency.
Crystal oscillator connections.
The crystal oscillator frequency needs to be three times greater than
the desired CLK frequency.
Crystal oscillator output. This output frequency is the same as the
oscillating frequency of the oscillator connected to the X
pins. As long as a Xtal oscillator is connected to the X
and X2
1
and X2 pins,
1
this output signal can be obtained independently even if F/C is set to
high level to enable the EFI input to be used CLK generation purpose.
6/18
¡ Semiconductor MSM82C84A-2RS/GS/JS
Pin Symbol
Name
Input/Output
Ready
ASYNC
synchronization
Input
select signal
V
CC
GND
—
—
—
—
TIMING DIAGRAM
CLK • PCLK • OSC Waveforms
t
ELEL
EFI
OSC
t
EHYL
CSYNC
t
YHYL
Function
Signal for selection of the synchronization mode of the READY signal
generator circuit. When this signal is at low level, the READY signal is
generated by double synchronization. And when at high level, the
READY signal is generated by single synchronization.
This pin is equipped with internal pull-up resistor.
+5 V power supply
GND
t
EHEL
t
ELEH
t
OLCH
t
YHEH
t
t
OLCL
CLCL
t
CHCL
t
CH1CH2
CLK
PCLK
RESET Waveform
CLK
RES
t
CLCH
t
CLPH
t
PHPL
t
CLI1H
t
CLPL
t
PLPH
t
I1HCL
t
CL2CL1
RESET
t
CLIL
7/18
¡ Semiconductor MSM82C84A-2RS/GS/JS
READY Waveform (ASYNC = L)
t
R1VCH
CLK
t
t
CLR1X
R1VCL
RDY1 -
AEN1 -
2
2
ASYNC
READY
READY Waveform (ASYNC = H)
t
A1R1V
t
AYVCL
t
RYHCH
t
CLR1X
t
RYLCL
t
CLA1X
t
CLAYX
CLK
RDY
1
AEN1 -
ASYNC
READY
-
t
t
R1VCL
t
CLR1X
2
t
A1R1V
2
t
AYVCL
t
RYHCH
t
CLR1X
R1VCL
t
RYLCL
t
CLA1X
t
CLAYX
8/18
¡ Semiconductor MSM82C84A-2RS/GS/JS
pp
OPERATIONAL DESCRIPTION
(1) Oscillator Circuit
The MSM82C84A-2 internal oscillator circuit can be driven by connecting a crystal oscillator to
the X1 and X2 pins.
The frequency of the crystal oscillator in this case needs to be three times greater than the desired
CLK frequency.
Since the oscillator circuit output (the same output as for the crystal resonator frequency)
appears at the OSC pin, independent use of this output is also possible.
Oscillator Circuit Example
Crystal Oscillator
Note: Because Oscillator circuit and values depend on crystal oscillator characteristics,
OKI recommends to make contact with crystal oscillator vendor to determine
the best circuit and values for customers' a
(2) Clock Generator Circuit
X
1
C
1
MSM
C
2
When input frequency is 6 to 15 MHz
= C2 = 33 pF
C
1
When input frequency is 15 to 24 MHz
C
= C2 = 10 pF
1
82C84A-2
X
2
OSC
lication.
This circuit generates two clock outputs-CLK obtained by dividing the input external clock or
crystal oscillator circuit output by three, and PCLK obtained by halving CLK. CLK and PCLK
are generated from the external clock applied to the EFI pin when F/C is at high level, and are
generated from the crystal oscillator circuit when at low level.
(3) Reset Circuit
Since a Schmitt trigger circuit is used in the RES input, the MSM82C84A-2 can be reset by “power
on” by connection to a simple RC circuit. If the MSM80C86A-10 or MSM80C88A-10 is used as
the CPU in this case, it is necessary to keep the RES input at low level for at least 50 ms after Vcc
reaches the 4.5V level.
9/18
¡ Semiconductor MSM82C84A-2RS/GS/JS
(4) Ready Circuit
The READY signal generator circuit can be set to synchronization mode by ASYNC.
(i) When ASYNC is at low level
The RDY input is output as the READY signal by double synchronization.
The high-level RDY input is synchronized once by the rising edge of the CLK of the first
stage flip-flop (F1 in the circuit diagram), and then synchronized again by the falling
edge of the CLK of the next stage flip-flop (F2 in the circuit diagram), resulting in output
of a high-level READY output signal (see diagram below).
The low-level RDY input is synchronized directly by the falling-edge of the CLK of the
next stage flip-flop, resulting in output of a low-level READY output signal (see
diagram below).
CLK
RDY
READY
(ii) When ASYNC is at high level
The RDY input is output as the READY signal by single synchronization.
Both low-level and high-level RDY inputs are synchronized by the falling edge of the
CLK of the next stage flip-flop, resulting output of respective low-level and high-level
READY output signals (see diagram below).
CLK
RDY
READY
10/18
¡ Semiconductor MSM82C84A-2RS/GS/JS
EXAMPLE OF USE (CSYNC)
The MSM82C84A-2 1/3 frequency divider counter is unsettled when the power is switched
on. Therefore, the CSYNC pin has been included to synchronize CLK with another signal.
When CSYNC is at high level, both CLK and PCLK are high-level outputs. If CSYNC is then
switched to low level, CLK is output from the next input clock rising edge, and is divided
by 3.
If CSYNC has not been synchronized with the input clock, use the following circuit to
achieve the required synchronization
External Sychronizing
Signal
External Clock
Signal (EFI)
When an external clock EFI is used as the clock source
External Sychronizing
Signal
When the crystal oscillator is used as the clock source
D
CK≠
D
CK≠
Q
Q D
D
CKØ
CKØ
Q
Q
CSYNC
MSM
82C84A-2
EFI CLK
CSYNC
MSM
82C84A-2
OSC
F/C
CLK
CLK
X
1
X
2
CLK
NOTES ON USE
The MSM82C84A-2 cannot be used if the MSM80C86A-10 or MSM80C88A-10 is used within the
range of 8 MHz < operating frequency £ 10 MHz.
11/18
¡ Semiconductor MSM82C84A-2RS/GS/JS
NOTICE ON REPLACING LOW-SPEED DEVICES WITH HIGH-SPEED DEVICES
The conventional low speed devices are replaced by high-speed devices as shown below.
When you want to replace your low speed devices with high-speed devices, read the replacement
notice given on the next pages.
High-speed device (New)
M80C85AH
M80C86A-10
M80C88A-10
M82C84A-2
M81C55-5
M82C37B-5
M82C51A-2
M82C53-2
M82C55A-2
Low-speed device (Old)
M80C85A/M80C85A-2
M80C86A/M80C86A-2
M80C88A/M80C88A-2
M82C84A/M82C84A-5
M81C55
M82C37A/M82C37A-5
M82C51A
M82C53-5
M82C55A-5
Remarks
8bit MPU
16bit MPU
8bit MPU
Clock generator
RAM.I/O, timer
DMA controller
USART
Timer
PPI
12/18
¡ Semiconductor MSM82C84A-2RS/GS/JS
Differences between MSM82C84A and MSM82C84A-5/MSM82C84A-2
1) Manufacturing Process
All these devices use a 3 m Si-Gate CMOS process technology.
The chip size of these devices is same.
The chip of the MSM82C84A-5 is entirely identical to that of the MSM82C84A-2.
2) Functions
Item
Internal processing of ASYNC pin
Notes on use
Normal CMOS input pin
The pin should have a pullup or
pulldown resistor if it is unused.
MSM82C84A
MSM82C84A-5/-2
Input pin with built-in pull up resistor
The value of pulldown resistor
(when used) is limited. (See page 3.)
3) Electrical Characteristics
3-1) DC Characteristics
Parameter
''L''Level Output Voltage (CLK) 0.45 V maximum (+5 mA) 0.40 V maximum (+4 mA)
''L''Level Output Voltage
(Other than CLK)
''H''Level Output Voltage (CLK)
''H''Level Output Voltage
(Other than CLK)
Symbol
V
OL
V
OL
V
OH
V
OH
MSM82C84A MSM82C84A-5/-2
0.45 V maximum (+5 mA) 0.40 V maximum (+2.5 mA)
3.7 V minimum (-1 mA) V
3.7 V minimum (-1 mA) V
-0.1 V minimum (-4 mA)
CC
0.1 V minimum (-1 mA)
CC-
RES Input Hysteresis Width
Input Current (ASYNC)
Input Leak Current
Supply Current (Standby)
IHR-
V
I
I
I
CCS
ILR
LIA
LI
0.25 V minimum 0.2 ¥ V
CC
-10 mA to +10 mA -100 mA~+10 mA
-10 mA to +10 mA -1 mA~+1 mA
100 mA maximum 40 mA maximum
V
As shown above, the MSM82C84A-5/MSM82C84A-2 satisfies the characteristics (except for V
and input current (ASYNC) of the MSM82C84A.
min
OL
13/18
¡ Semiconductor MSM82C84A-2RS/GS/JS
3-2) AC Charasteristics
1) MSM82C84A and MSM82C84A-2
Parameter
Input Rise Time
Input Fall Time
CLK High Time
CLK Low Time
Symbol
t
ILIH
t
ILIH
t
CHCL
t
CLCH
t
CH1CH2
MSM82C84A MSM82C84A-2
20 ns maximum 15 ns maximum
20 ns maximum 15 ns maximum
65 ns minimum 1/3 t
119 ns minimum 2/3 t
+2 ns minimum
CLCL
-15 ns minimum
CLCL
CLK Rise/Fall Time 15 ns maximum 10 ns maximum
t
CL1CL2
t
PCLK High Time
PCLK Low Time
READY Falling to CLK Rising 114 ns minimum 2/3 t
PHPL
t
PLPH
t
RYHCH
180 ns minimum t
180 ns minimum t
-20 ns minimum
CLCL
-20 ns minimum
CLCL
-15 ns minimum
CLCL
As shown above, the MSM82C84A-2 satisfies the characteristics (except for Input Rise/Fall Time)
of the MSM82C84A.
1) MSM82C84A-5 and MSM82C84A-2
Parameter
EFI High Time
EFI Low Time
EFI Period
Crystal Frequency
CLK Period
Symbol
t
EHEL
t
ELEH
t
ELEL
—
t
CHCL
MSM82C84A-5 MSM82C84A-2
20 ns minimum 13 ns minimum
20 ns minimum 17 ns minimum
66 ns minimum 36 ns minimum
15 MHz maximum 24 MHz maximum
200 ns minimum 125 ns minimum
As shown above, the MSM82C84A-2 satisfies the characteristics of the MSM82C84A-5.
14/18
¡ Semiconductor MSM82C84A-2RS/GS/JS
4) Notices on use
Note the following when replacing devices as the ASYNC pin is differently treated between the
MSM82C84A and the MSM82C84A-5/MSM82C84A-2:
Case 1: When only a pullup resistor is externally connected to.
The MSM82C84A can be replaced by the MSM82C84A-2.
Case 2: When only pulldown resistor is externally connected to.
When the pulldown resistor is 8 kiloohms or less, the MSM82C84A can be replaced by the
MSM82C84A-2.
When the pulldown resistor is greater than 8 kiloohms, use a pulldown resistor of 8 kiloohms or less.
Case 3: When an output of the other IC device is connected to the device.
The MSM82C84A can be replaced by the MSM82C84A-2 when the I
ASYNC pin of the MSM82C84A-2 has an allowance of 100 mA or more.
pin of the device to drive the
OL
15/18
¡ Semiconductor MSM82C84A-2RS/GS/JS
PACKAGE DIMENSIONS
(Unit : mm)
DIP18-P-300-2.54
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.30 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
16/18
¡ Semiconductor MSM82C84A-2RS/GS/JS
(Unit : mm)
QFJ20-P-S350-1.27
Spherical surface
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
Cu alloy
Solder plating
5 mm or more
0.59 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
17/18
¡ Semiconductor MSM82C84A-2RS/GS/JS
(Unit : mm)
SOP24-P-430-1.27-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.58 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
18/18
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