Page 1
FEDL1200V-03
FEDL1200V-03
¡ Semiconductor MSC1200-01/1200V-01
¡ Semiconductor
This version: Sep. 2000
Previous version: Nov. 1997
MSC1200-01/1200V-01
30-Bit Duplex Controller/Driver with Digital/Analog Dimming and Keyscan Functions
GENERAL DESCRIPTION
The MSC1200-01/1200V-01 is a Bi-CMOS display driver for 1/2-duty vacuum fluorescent
display tube. This device consists of a 64-bit shift register, latches, an analog dimming circuit,
a digital dimming circuit, a keyscan circuit, and drivers.
The interface with a microcomputer can be done only with four signal lines (CS, DATA I/O,
CLOCK, and INT). Also, the DATA I/O and CLOCK signal lines can be shared with other
peripherals by using the chip select function.
FEATURES
• Power supply voltage : 8V to 18V (built-in 5V regulator for logic)
• Operating temperature range : –40°C to +85°C
• 30-segment driver outputs (IOH = –6mA at VOH = V
• Built-in analog dimming circuit (PWM: 12.5% Max at 6-bit resolution)
• Built-in digital dimming circuit (11-bit resolution)
• Built-in 5 x 6 keyscan circuit
• Built-in RC oscillation circuit (external R and C)
• Built-in power-on-reset circuit.
• The product name differs depending on the bonding option pin selected:
PWM OUT/BLANK IN : MSC1200-01
DATA OUT : MSC1200V-01
• Package :
56-pin plastic QFP (QFP56–P–910-0.65–2K) (Product name: MSC1200-01GS-2K/MSC1200V-01GS-2K)
DD
– 0.8V)
1/26
Page 2
FEDL1200V-03
¡ Semiconductor MSC1200-01/1200V-01
BLOCK DIAGRAM
V
DD
GND
TEST1
OSC0
OSC1
V
PARK
V
DIM
5V
5V
Regulator
&POR
POR
S1, S6, S7, S8
SEG1
R/C
OSC
D
CK
SEG30 GRID1 GRID2
30 Segment Drivers Grid Driver
PLA (32 ¥ 32 Matrix)
Multiplexer
Bit Latch Mode Selector
64-Bit Shift Register
M3 M2 M1 M0
R
Timing Generator
R
Analog Dimming
R
Selector
Digital Dimming
R
S2, S7, S3, S8
SAS9S8S7S6S5S4S3S2S1
DATA OUT
(Optional)
PWM OUT/
BLANK IN
(Optional)
CS
DATAI/O
CLOCK
Control
Circuit
S5, S6, S9
SAS9S4
5 ¥ 6 Keyscan Circuit
10325410324
ROWCOLUMN
INT
R
2/26
Page 3
FEDL1200V-03
¡ Semiconductor MSC1200-01/1200V-01
INPUT AND OUTPUT CONFIGURATION
• Schematic Diagrams of Logic Portion Input Circuit
INPUT
V
DD
GND
(5V Reg.)
GND
• Schematic Diagrams of Logic Portion Input
Circuit 2
TEST1
COLn
V
DD
(5V Reg.)
• Schematic Diagrams of Logic Portion Input/
Output Circuit
(5V Reg.)
DATAI/O
V
DD
(5V Reg.)
GND
GND
• Schematic Diagrams of Logic Portion Output
Circuit
(5V Reg.)
GND
(5V Reg.)
OUTPUT
GND
GND
GND
GND
GND
• Schematic Diagrams of Driver Output Circuit
V
GND
DD
V
GND
DD
OUTPUT
3/26
Page 4
FEDL1200V-03
¡ Semiconductor MSC1200-01/1200V-01
PIN CONFIGURATION (TOP VIEW)
GRID2
GRID1
SEG30
SEG29
SEG28
SEG27
SEG26
GND
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
56
55
54
53
52
51
50
49
48
47
46
45
44
43
V
DD
V
PARK
V
DIM
CS
CLOCK
DATA I/O
INT
TEST1
*1
COLUMN0
COLUMN1
COLUMN2
COLUMN3
COLUMN4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
42
41
40
39
38
37
36
35
34
33
32
31
30
29
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
15
16
17
18
19
20
21
22
23
24
25
ROW0
COLUMN5
ROW1
ROW2
ROW3
ROW4
GND
OSC0
OSC1
SEG1
SEG2
56-Pin Plastic QFP
*1 Bonding option pin (DATA OUT or PWM OUT/BLANK IN)
26
SEG3
27
SEG4
28
SEG5
4/26
Page 5
FEDL1200V-03
¡ Semiconductor MSC1200-01/1200V-01
PIN DESCRIPTIONS
Pin Symbol Description
1V
DD
Type
—
Power Supply
Day/night switching pin. When the high level is input, the IC enters the night
mode and the value determined by the analog or digital dimming circuit is
2V
PARK
I
used as the output duty. When the low level is input, the IC enters the day
mode and the output duty is about 100%.
Analog voltage input for determining the analog dimming value.
When the analog dimming circuit is used, the output duty is determined by
3V
DIM
I
the analog voltage to be input to this pin.
When only the digital dimming circuit is used, pull down this pin to GND.
Chip select input. Only when the high level is input to this pin, interfacing
with a microcomputer is available through "CLOCK" and "DATA I/O" pins.
4CS
I
Therefore, 2 signal lines of "CLOCK" and "DATA I/O" can be shared with other
peripherals.
Serial clock input. Data is input-output through "DATA I/O" pin at the rising
5
CLOCK
6 DATA I/O
I
edge of the serial clock.
Serial data input-output. This pin enters output mode only when the keyscan
I/O
mode is selected. It enters input mode when other mode is selected.
Interrupt signal output to microcomputer. When any key is pressed or
7 INT
released, key scanning is started. After the completion of the one cycle, this
O
pin goes to the high level and keeps the high level until keyscan stop mode is
selected.
Test signal input. As this pin has a built-in pull-up resistor, it must be left
open or pulled up in the normal operation mode. When the low level is input
8 TEST1
I
to this pin, SEG1-30 go to the high level, and GRID1 and GRID2 go to the
low level. (All segments go on.)
Serial data output. Selecting this pin specifies the MSC1200V-01. The data
9
DATA OUT
(Option)
from DATA I/O is shifted out on the rising edge of the shift clock with a delay
O
of 64 bits in the shift register. This pin can be used for connecting the IC with
a LED driver in series.
When the V
pin is at the high level, the pulse with the duty ratio determin-
PARK
ed by the analog or digital dimming circuit is output through this pin. When
PWM OUT/
9
BLANK IN
(Option)
this pin is at the low level, the pulse with the duty ratio determined by external
circuit is input to this pin. This pin has an internal active pull-up resistor,
I/O
which becomes active only when the V
V
pin is at the low level, this pin receives blanking signal from external
PARK
pin is at the low level. When the
PARK
circuits, so that output duty cycle can be controlled. Selecting this pin specifies the MSC1200-01.
5/26
Page 6
FEDL1200V-03
¡ Semiconductor MSC1200-01/1200V-01
Pin Symbol Description
10-15
16-20
21, 49 GND Ground
22, 23
24-48,
50-54
55, 56 GRID1,2
COLUMN
0-5
ROW0-4
OSC0
OSC1
SEG1-30
Type
Return inputs from key matrix switch. A pull-up resistor is internally
connected to each of these pins so that they are at the high level except when
I
the low level is input by depression of a key. These pins are "L" active.
Key switch scanning outputs. Normally the low level is output through these
pins. When any key is depressed or released, keyscanning is started and is
continued until keyscan stop mode is selected. When the keyscan stop mode
O
is selected and then keyscanning is stopped, all outputs of ROW0-4 go back
to the low level.
—
Connecting pins for RC oscillation circuit. Connect a resistor between OSC1
I/O
and OSC0, and a capacitor between OSC0 and ground.
Segment signal output. Signals for driving VF display tube are output
O
through these pins.
Grid signal output. Signals for driving VF display tube are output through
these pins. Signals inverted with respect to grid signals are output.
O
Normally, these pins are connected to the external grid driver (PNP transistor
etc.) inputs.
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Page 7
FEDL1200V-03
¡ Semiconductor MSC1200-01/1200V-01
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Condition Rating Unit
Supply Voltage V
Input Voltage (1) V
Input Voltage (2) V
Power Dissipation P
DD
IN1
IN2
STG
—
All inputs except V
V
PARK
PARK
—Storage Temperature T
D
Ta = 85°C
–0.3 to +20 V
–0.3 to +6 V
–0.3 to VDD +0.3 V
–65 to +150 °C
400 mW
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Condition Max. Unit
Supply Voltage V
High Level Input Voltage (2) V
High Level Input Voltage (3) V
Low Level Input Voltage (1) V
Low Level Input Voltage (2) V
Clock Frequency f
DD
IH1
IH2
IH3
IL1
IL2
C
OSC
FR
op
—
All inputs except V
V
PARK
OSC0
All inputs except OSC0
OSC0
—
R = 4.7kW, C=10pFOSC Frequency f
f
=3MHzFrame Frequency f
OSC
—Operating Temperature T
PARK
Min.
& OSC0High Level Input Voltage (1) V
3.8
Typ.
8
—
18 V
5.5 V—
V
DD
V—3.8
5.5 V—4.5
0.8 V—0
0.5 V—0
250 kHz——
— MHz3.3—
—Hz201—
+85 °C—–40
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Page 8
FEDL1200V-03
¡ Semiconductor MSC1200-01/1200V-01
ELECTRICAL CHARACTERISTICS
DC Characteristics
= 8 to 18V)
DD
5.5 V
V
DD
5.5 V4.5
0.8 V0
0.5 V0
5 mA–5
30 mA–30
80 mA–80
–5 mA–5
–15 mA–160
0.1 mA–0.6
10 mA–10
—
6V4
6V4.5
2V—
1V—
0.3 V—
0.8 V—
20 mA—
V3.8
V
Parameter Symbol Condition Max. Unit
High Level Input Voltage (1) V
High Level Input Voltage (2)
High Level Input Voltage (3)
Low Level Input Voltage (1)
Low Level Input Voltage (2)
High Level Input Current (1)
*1
*9
*2
*10
*2
*3
*4
*5
*3
*4
*5
*6
*7
High Level Output Voltage (2)
Low Level Output Voltage (1)
Low Level Output Voltage (2)
*8
*7
*8
Power Supply Current
IH1
V
IH2
V
IH3
V
IL1
V
IL2
I
IH1
IH2
IH3
IL1
IL2
IL3
IL
OH1
OH2-1
OH2-2
OL1-1
OL1-2
OL1-3
OL2
DD
V
IH1
V
IH2
V
IH3
V
IL1
V
IL2
V
IL3
= 0 to 5.5VInput Leakage Current I
V
I
V
= 9.5V, I
DD
VDD = 9.5V, I
VDD = 9.5V, Output OpenV
VDD = 9.5V, I
VDD = 9.5V, I
VDD = 9.5V, I
VDD = 9.5V, I
= 3.3MHz, No loadI
f
OSC
—
—
—
—
—
= 5.0V
= 5.0VHigh Level Input Current (2) I
= 5.0VHigh Level Input Current (3) I
= 0VLow Level Input Current (1) I
= 0VLow Level Input Current (2) I
= 0VLow Level Input Current (3) I
OH1
= –200mAV
OH2
OL1-1
OL1-2
OL1-3
OL2
(Ta = –40 to +85°C, V
Min.
3.8
V
= –6mAHigh Level Output Voltage (1) V
DD
–0.8
= 500mAV
= 200mAV
= 2mAV
= 200mAV
*1 Applicable to all input pins (except V
and OSC0 pins)
PARK
*2 Applicable to OSC0 pin
*3 Applicable to CLOCK, DATA I/O, CS, and V
PARK
pins
*4 Applicable to COLUMN0 to COLUMN5 and PWM OUT/BLANK IN pins
*5 Applicable to TEST1 pin
*6 Applicable to V
DIM
pin
*7 Applicable to SEG1 to SEG30, GRID1, and GRID2 pins
*8 Applicable to ROW0 to ROW4, DATA I/O, PWMOUT/BLANK IN, DATAOUT, and INT
pins.
*9 Applicable to V
PARK
pin
*10 Applicable to all input pins (except OSC0)
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Page 9
FEDL1200V-03
¡ Semiconductor MSC1200-01/1200V-01
AC Characteristics
= 8 to 18V)
DD
4.66 MHz
3.7 MHz2.4
284 Hz122
568 Hz244
250 kHz—
— ms1.3
— ms1
—ns200
— ms68
— ms30
— ms2
— ms2
1 ms—
8 ms—
5 ms—
— ms300
—ms5
100 ms—
Parameter Symbol Condition Max. Unit
Oscillation Frequency f
Input Frequency to OSC0 from
Outside
Frame Frequency f
PWM OUT Frequency f
Clock Frequency f
Clock Pulse Width t
Data Setup Time t
Data Hold Time t
CS Pulse Width t
CS Off Time t
CS Setup Time
CS – Clock Time
CS Hold Time
Clock – CS Time
Data Output Delay
Clock – Data output Time
SEG & GRID Output Delay
from CS
Slew Rate (All Drivers)
CS Time at Power-on t
Hold Time at Power-off t
Rise Time at Power-on t
OSC
OSCI
FR
PWM
CW
DS
DH
CSW
CSL
t
CSH
t
CSH
t
PD
t
ODS
t
PCS
POF
PRZ
(Ta = –40 to +85°C, V
Min.
R = 4.7kW±1%, C = 10pF±5%
2
External input onlyf
—
—
C
—
—
—
—
—
—
—
—
—
CI = 100pF
R
CI = 100pF, t = 20% to 80% or
80% to 20% of V
DD
—
When mounted on the unit
=0.0V
V
DD
When mounted on the unit
9/26
Page 10
FEDL1200V-03
¡ Semiconductor MSC1200-01/1200V-01
Dimming Characteristics
• DC characteristics
(Ta = –40 to +85°C, V
Parameter Condition Max. Unit
D/A Output Voltage Error ±3%
Reference Voltage Accuracy ±6%—
—
Note 1
Min.
—
—
Typ.
—
= 8 to 18V)
DD
Note: 1. Reference voltage is 6.6V typical.
Keyscan Characteristics
(Ta = –40 to +85°C, V
Parameter Condition Max. Unit
=3.3 MHzKeyscan Cycle Time 640 ms
f
OSC
f
=3.3 MHzKeyscan Pulse Width 128 ms78
OSC
Min.
275
Typ.
390
55
= 8 to 18V)
DD
10/26
Page 11
FEDL1200V-03
¡ Semiconductor MSC1200-01/1200V-01
TIMING DIAGRAM
t
CSW
t
CSL
t
CSH
CS
3.8V
0.8V
t
CSS
f
C
t
CW
t
CW
CLOCK
DATA I/O
(INPUT)
CS
CLOCK
3.8V
0.8V
3.8V
0.8V
3.8V
0.8V
3.8V
0.8V
t
CSS
t
DS
t
DH
Figure 1 Data Input Timing
t
PD
t
DS
t
DH
VALIDVALID
t
CSH
t
PD
DATA I/O
(OUTPUT)
DATA OUT
3.8V
0.8V
Figure 2 Data Output Timing
11/26
Page 12
FEDL1200V-03
G
¡ Semiconductor MSC1200-01/1200V-01
TIMING DIAGRAM (Continued)
CS
V
CS
DD
8V
0V
3.8V
3.8V
t
PCS
t
POF
Figure 3 Power-On Timing
t
CSW
t
ODS
t
R
t
t
ODS
PRZ
t
R
SEG1-30
RID1, 2
80%
20%
Figure 4 SEG & GRID Output Timing
12/26
Page 13
FEDL1200V-03
¡ Semiconductor MSC1200-01/1200V-01
FUNCTIONAL DESCRIPTION
Power-on Reset
The IC is initialized by the built-in power-on reset circuit at power-on. The status of the internal
circuit after initialization is as follows;
1) Shift registers and latches are reset.
2) Analog dimming is selected.
3) Digital dimming data register is reset.
4) Display data input mode is selected.
Data Input
Data input is valid only when the high level is applied to the "CS" pin. Input data is input into
the shift register through "DATA I/O" pin at the rising edge of CLOCK. The data is automatically
loaded to latches at the falling edge of "CS" signal.
[Data Format]
1) Display Data Input Mode
Input data : 64 bits
VF display data : 60 bits
Mode select data : 4 bits
First In
Bit
64
D5963D5862D57
53
... ...
D4852M351M250M149M048D47
3D22D11
D0
Display
Data
(12 bits)
Mode
Data
(4 bits)
2) Correspondence between segment outputs and shift register bits
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SEGn
302928272625242322212019181716151413121110987654321GRID1
Bit
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 GRID2
Display
Data
(48 bits)
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Page 14
FEDL1200V-03
¡ Semiconductor MSC1200-01/1200V-01
3) Digital Dimming Data Input Mode
Input data : 16 bits
Digital dimming data : 11 bits
Mode select data : 4 bits
Bit
64
6311621061960859758657556455354253152
xx
MSB LSB
Dimming Data Mode Data
INPUT DATA (LSB)(MSB)
X00000000000
X00000000001 1/2048
X11111110000 2032/2048
X11111111111 2032/2048
M
3
DUTY CYCLE
0/2048
51
49
First In
M
0
50
M
M
2
1
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Page 15
FEDL1200V-03
¡ Semiconductor MSC1200-01/1200V-01
4) Function Mode
Mode
S1
S2 0 Analog Dimming Select011
S3 0 Digital Dimming Select101
S4 0 Digital Dimming Data Input & Digital Dimming Select001
S5 0 Keyscan Data Output111
S6 0 Display Data Input & Keyscan Data Output110
S7 0 Display Data Input & Analog Dimming Select010
S8 0 Display Data Input & Digital Dimming Select100
S9 1 Keyscan Data Output & Keyscan Stop000
SA 1 Keyscan S
M3 Function
M2 M1 M0
0 Display Data Input000
001
TOP
Note: Other combinations are used for test modes.
5) Analog Dimming Mode
Analog dimming is automatically selected when the V
pin is set to the high level after
PARK
power-on. Therefore, when digital dimming is used, mode setting is required before the
V
pin is set to the high level.
PARK
The output duty ratio for analog dimming is 12.5% maximum. The correspondence between
threshold voltage and output duty ratio is shown in V
Threshold Dimming Voltage VS.
DIN
PWM Duty Cycle.
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Page 16
FEDL1200V-03
¡ Semiconductor MSC1200-01/1200V-01
Keyscan
Keyscanning is started only when depression or release of any key is detected in order to
minimize noise caused by scanning signal. Then, keyscanning is continued until the keyscan
stop mode signal is sent from a microcomputer. The INT pin goes to the high level at the
completion of 1-cycle scanning after the keyscan start, so the (high level) signal sent from the INT
pin can be used as an interrupt signal.
[Keyscan Timing]
ROW 0
ROW 1
ROW 2
ROW 3
ROW 4
1 Cycle
INT
Depress/Release
Keyscan stop mode
is selected.
Note: Keyscanning cannot be stopped by selecting the keyscan stop mode only once if:
- keyscanning is started after depression or release of any key is detected, and then
- a key is depressed or released again before the keyscan stop mode is selected.
To stop keyscanning, it is required to select the keyscan stop mode once again.
16/26
Page 17
FEDL1200V-03
¡ Semiconductor MSC1200-01/1200V-01
[Example]
A) When Key Input Status is Changed
Depress Release
INT
CS
Keyscan Keyscan
SA S5 S5SA
Keyscan
stop
Keyscan stop Keyscan stop
Keyscan data
output
Keyscan
stop
B) When Key Input Status is Changed before Keyscan Stop Mode Select
Depress
INT
Release
* 1
Keyscan Keyscan
Keyscan data
output
Keyscan Stop
CS
Keyscan
stop
SA S5 SA S5
Keyscan data
output
*1: Keyscanning resumes after short period of keyscan stop.
Keyscan
stop
Keyscan data
output
17/26
Page 18
FEDL1200V-03
0
1
2
3
4
5
¡ Semiconductor MSC1200-01/1200V-01
Keyscan Data Output
When keyscan data output mode is selected, "DATA I/O" pin is changed to an output mode.
Then, 30 bits of keyscan data come out from "DATA I/O" pin synchronizing with the rising edge
of the clock. After the completion of 30 bits data output, the IC returns to the display data input
mode synchronizing with the falling edge of CS.
[Data Format]
1) Keyscan Data Stop Mode
Since the DATA I/O pin goes to the output mode after the keyscan stop mode signal is
received, be sure to output the keyscan data.
Input data : 16 bits
Mode select data : 4 bits
Bit
64
63xx62xx61xx60xx59xx58xx57xx56xx55xx54xx53xx52
xx
2) Keyscan Data Output Mode
Input data : 30 bits
Output data : 30 bits
CLOCK
30
45
29
S
S
44
28
43
.....
9
8
7
6
5
04
4
S
S
03
.....
S
12
S
S
S
S
11
10
05
Sxx
↑↑
ROW COLUMN
3) Key switch matrix for COLUMN input and ROW output
ROW0 ROW1 ROW2 ROW3 ROW4
S
00
S
01
S
02
S
03
S
04
S
05
S
10
S
11
S
12
S
13
S
14
S
15
S
20
S
21
S
22
S
23
S
24
S
25
S
30
S
31
S
32
S
33
S
34
S
35
S
S
S
S
S
S
=
51
50
M
M
M
3
2
1
49
M
First In
0
Mode Data
3
2
S
S
02
01
COLUMN
40
COLUMN
41
COLUMN
42
COLUMN
43
COLUMN
44
COLUMN
45
First Out
1
S
Keyscan Data
00
18/26
Page 19
FEDL1200V-03
¡ Semiconductor MSC1200-01/1200V-01
GRID/SEG Driver Operation and Digital/Analog Dimming Operation
Figure 5 shows the output timing of the GRID and SEG driver when the V
is the "H" level.
PARK
Figure 6 shows the output timing of the GRID and SEG drivers for the digital diming mode
operation.
Figure 7 shows the output timing of the GRID and SEG drivers for the analog dimming mode
operation.
1 Frame
4096 bit times
GRID1
16 bit times
GRID2
SEG1-30
Figure 5 GRID and SEG Output Timing (V
2032 bit times
6 bit times
2038 bit times 10 bit times
PARK
="H")
Note: 1 bit time = T
GRID1
GRID2
SEG1-30
OSC
(4/f
) = 1.2ms (typ.)
OSC
1 Frame
4096 bit times
2032 bit times
6 bit times
2038 bit times 10 bit times
16 bit times
Figure 6 GRID and SEG Output Timing (Digital Dimming Mode)
Notes: 1. Shown above is the timing in the digital dimming mode with the duty cycle of 2032/
2048 at V
PARK
= "L".
2. The length of time that the grids and the segments are turned on is specified with
respect to 11 bits of the ditigal dimming data.
3. 1 bit time = T
OSC
(4/f
) = 1.2ms (typ.)
OSC
19/26
Page 20
FEDL1200V-03
¡ Semiconductor MSC1200-01/1200V-01
1 Frame
4096 bit times
GRID1
2048 bit times
GRID2
Max. 256 bit times
SEG1-30
Figure 7 GRID and SEG Output Timing (Analog Dimming Mode)
Notes: 1. Shown above is the timing for the GRID and SEG Drivers in the analog dimming
mode at V
2. 1 bit time = T
PARK
OSC
= "L".
(4/f
) = 1.2ms (typ.)
OSC
20/26
Page 21
FEDL1200V-03
¡ Semiconductor MSC1200-01/1200V-01
PLA Code Table
SEG 1
SEG 2
SEG 3
SEG 4
SEG 5
SEG 6
SEG 7
SEG 8
SEG 9
SEG 10
SEG 11
SEG 12
SEG 13
SEG 14
SEG 15
SEG 16
SEG 17
SEG 18
SEG 19
SEG 20
SEG 21
SEG 22
SEG 23
SEG 24
SEG 25
SEG 26
SEG 27
SEG 28
SEG 29
SEG 30
PIN 24
PIN 25
PIN 26
PIN 27
PIN 28
PIN 29
PIN 30
PIN 31
PIN 32
PIN 33
PIN 34
PIN 35
PIN 36
PIN 37
PIN 38
PIN 39
PIN 40
PIN 41
PIN 42
PIN 43
PIN 44
PIN 45
PIN 46
PIN 47
PIN 48
PIN 49
PIN 50
PIN 51
PIN 52
PIN 53
PIN NAME
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
BIT 1, 31
BIT 2, 32
BIT 3, 33
BIT 4, 34
OUTPUT
BIT 1, 31
BIT 2, 32
BIT 3, 33
BIT 4, 34
BIT 5, 35
BIT 6, 36
BIT 7, 37
BIT 8, 38
BIT 9, 39
BIT 10, 40
BIT 5, 35
BIT 6, 36
BIT 7, 37
BIT 8, 38
BIT 9, 39
BIT10, 40
BIT11, 41
BIT12, 42
PIN NAME
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
BIT13, 43
BIT14, 44
BIT15, 45
BIT16, 46
BIT17, 47
BIT18, 48
BIT19, 49
OUTPUT
BIT 11, 41
BIT 12, 42
BIT 13, 43
BIT 14, 44
BIT 15, 45
BIT 16, 46
BIT 17, 47
BIT 18, 48
BIT 19, 49
BIT 20, 50
BIT20, 50
BIT21, 51
BIT22, 52
BIT23, 53
BIT24, 54
BIT25, 55
BIT26, 56
BIT27, 57
PIN NAME OUTPUT
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
BIT28, 58
BIT29, 59
BIT30, 60
BIT 21, 51
BIT 22, 52
BIT 23, 53
BIT 24, 54
BIT 25, 55
BIT 26, 56
BIT 27, 57
BIT 28, 58
BIT 29, 59
BIT 30, 60
21/26
Page 22
FEDL1200V-03
¡ Semiconductor MSC1200-01/1200V-01
V
Threshold Dimming Voltage VS. PWM Duty Cycle
DIM
=12.8V
V
DD
Pulse Step
Number
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
PWM Duty Cycle
Pulse Count % %Pulse Count
256/2048
240/2048
224/2048
208/2048
192/2048
184/2048
176/2048
168/2048
160/2048
152/2048
144/2048
136/2048
128/2048
120/2048
112/2048
104/2048
96/2048
92/2048
88/2048
84/2048
80/2048
76/2048
72/2048
68/2048
64/2048
60/2048
12.5
11.7
10.9
10.2
9.38
8.98
8.59
8.20
7.81
7.42
7.03
6.64
6.25
5.86
5.47
5.08
4.69
4.49
4.30
4.10
3.91
3.71
3.52
3.32
3.13
2.93
Threshold
Voltage
Vref
4.200
4.130
4.070
4.000
3.930
3.890
3.850
3.810
3.770
3.725
3.680
3.625
3.580
3.525
3.460
3.400
3.340
3.305
3.270
3.240
3.200
3.160
3.120
3.080
3.040
2.93
Pulse Step
Number
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PWM Duty Cycle
56/2048
52/2048
48/2048
46/2048
44/2048
42/2048
40/2048
38/2048
36/2048
34/2048
32/2048
30/2048
28/2048
26/2048
24/2048
23/2048
22/2048
21/2048
20/2048
19/2048
18/2048
17/2048
16/2048
15/2048
14/2048
13/2048
2.73
2.54
2.34
2.25
2.15
2.05
1.95
1.86
1.76
1.66
1.56
1.46
1.37
1.27
1.17
1.12
1.07
1.03
0.98
0.93
0.88
0.83
0.78
0.73
0.68
0.63
Threshold
Voltage
3.000
2.950
2.900
2.850
2.820
2.800
2.770
2.740
2.710
2.680
2.650
2.615
2.580
2.540
2.500
2.470
2.450
2.430
2.410
2.390
2.370
2.340
2.320
2.295
2.270
2.245
0.000
Note: A threshold voltage more than 5V cannot be set.
22/26
Page 23
FEDL1200V-03
¡ Semiconductor MSC1200-01/1200V-01
APPLICATION CIRCUITS
(A) Digital Dimming
1/2-Duty VF Display Tube
Driver
SEG1 SEG30 G1 G2
COLUMN5
COLUMN4
COLUMN3
COLUMN2
COLUMN1
COLUMN0
ROW0
ROW1
ROW2
ROW3
ROW4
Keyboard
Microcomputer
Lamp SW
Small Parking
2R
V
DD
GND
INT
CS
DATAI/O
CLOCK
OSC1
OSC0
V
PARK
V
R
DIM
MSC1200-01
Resistor
Luminance Control
23/26
Page 24
FEDL1200V-03
¡ Semiconductor MSC1200-01/1200V-01
(B) Analog Dimming
1/2-Duty VF Display Tube
Driver
SEG1 SEG30 G1 G2
Microcomputer
Lamp SW
Small Parking
2R
R
2R
Resistor
Luminance Control
Dashboard
Lamp
V
DD
GND
INT
CS
DATAI/O
CLOCK
OSC1
OSC0
V
PARK
V
DIM
R
COLUMN5
COLUMN4
COLUMN3
COLUMN2
COLUMN1
COLUMN0
MSC1200-01
ROW0
ROW1
ROW2
ROW3
ROW4
Keyboard
The setting voltage must not exceed 5V.
24/26
Page 25
FEDL1200V-03
¡ Semiconductor MSC1200-01/1200V-01
PACKAGE DIMENSIONS
(Unit : mm)
QFP56-P-910-0.65-2K
Mirror finish
Package material
Lead frame material
Pin treatment
Package weight (g)Oki Electric Industry Co., Ltd.
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5 mm)
0.43 TYP.
4/Vov. 28, 1996
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
25/26
Page 26
FEDL1200V-03
¡ Semiconductor MSC1200-01/1200V-01
NOTICE
1. The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6. The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7. Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
9. MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 2000 Oki Electric Industry Co., Ltd.
Printed in Japan
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