Datasheet MSC1163GS-BK Datasheet (OKI)

E2C0010-27-Y4

¡ Semiconductor MSC1163

¡ Semiconductor

This version: Nov. 1997

Previous version: Jul. 1996

MSC1163

40-Bit Anode Driver

GENERAL DESCRIPTION

The MSC1163 is a monolithic IC using the Bi-CMOS process for hybridizing CMOS and bipolar
transistors on the same chip. The logic portion such as the input stage, shift register and latch is
fabricated by CMOS and the output driver requiring a high withstand voltage is fabricated by
bipolar transistors.

Since the 60-pin plastic SSOP package is adopted and the pin configuration allows the circuit
wiring to be formed on the single side PCB, the display unit size can be reduced.
The shift register has a bidirectional configuration; therefore, it is easy to design the circuit wiring
in which devices are arranged so that they are symmetric with respect to the display.

FEATURES

The MSC1163 is designed as a VFD anode driver with emitter-follower output providing 40-bit
active pull-down and built-in 40-bit bidirectional shift register and latch.

• Logic Supply Voltage (VCC): 5V

• Driver Supply Voltage (VHV) : 65V

• Driver Output Current
I

OHVH

I

OHVL

• Built-in 40-bit output with latch

• Built-in 40-bit bidirectional shift register

• Clock frequency: 4MHz

• Package:

60-pin plastic SSOP (SSOP60-P-700-0.65-BK) (Product name: MSC1163GS-BK)

: –2mA
: 2mA

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¡ Semiconductor MSC1163

BLOCK DIAGRAM

V

V

V

CLK DIN R/L LS

D

R-1

R-2

11

22

CHG CL

CC

(1 to 20)

CC

(21 to 40)

(1 to 20)

HV

V

HV

(21 to 40)

HVO1

HVO2

40-Bit Latch

40-Bit Bi-directional Shift Register

40 40R-40

Q

DOUT

GND2

(1 to 20)

GND2

(21

to

40)

GND1

(1

to

20)

GND1

(21

to

HVO40

40)

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¡ Semiconductor MSC1163

INPUT AND OUTPUT CONFIGURATION

Schematic Diagrams of Logic Portion Input and Output Circuits

Input pin

Output pin

INPUT

V

CC

V

CC

GND1 GND2

V

CC

V

CC

DOUT

GND2 GND1

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¡ Semiconductor MSC1163

Schematic Diagram of Driver Output Circuit

V

GND 1

HV

V

HV

HVO

GND 1

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¡ Semiconductor MSC1163

PIN CONFIGURATION (TOP VIEW)

HVO 1
HVO 2
HVO 3
HVO 4
HVO 5
HVO 6
HVO 7
HVO 8

HVO 9
HVO 10
HVO 11
HVO 12
HVO 13
HVO 14

HVO 15
HVO 16
HVO 17
HVO 18
HVO 19
HVO 20

V

HV

GND 1
GND 2

CL

NC

LS

NC

R/L

DIN
V

CC

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

1
2
3
4
5
6
7
8
9

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

HVO 40
HVO 39
HVO 38
HVO 37
HVO 36
HVO 35
HVO 34
HVO 33

HVO 32
HVO 31
HVO 30
HVO 29
HVO 28
HVO 27

HVO 26
HVO 25
HVO 24
HVO 23
HVO 22
HVO 21
V

HV

GND 1
GND 2
NC
CHG
NC
CLK
NC
DOUT
V

CC

NC : No-connection pin

60-Pin Plastic SSOP

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¡ Semiconductor MSC1163

PIN DESCRIPTION

Function

Driver Output

Driver Power Supply

Driver GND

Logic GND

Clear Input

Latch Strobe Input

Shift Direction Control

Pin Symbol Description

1 - 20

41 - 60

21

HVO1 -

HVO40

V

HV

Type

O

—

Driver output pin, applicable to each bit of shift register

Power supply pin for driver circuit

40

22
39

GND 1

—

GND pin for driver circuit. Connect this pin to GND2 near
the mounted IC so that GND1 and GND2 will be at
common level.

23
38

GND 2

CL24

—

GND pin for the logic circuit (excluding driver circuit)
GND1 and GND2 are not connected inside of the IC.

I

Clear input pin with pull-up resistor. Normally "H" level.
In this condition, the driver outputs "H" or "L" according to
the corresponding latch output level. Setting to "L"
enables the driver output to be fixed at "L" without respect
to latch output.

26

LS

I

Latch strobe input pin with neither pull-up nor pull-down
resistor. When LS is "H", the output of the shift register
becomes that of the latch circuit. When LS is "L", the latch
circuit holds the contents of the shift register before LS
goes "L".

28

R/L

I

Shift direction control pin with a pull-up resistor.
Normally "H", and in this condition, data of bidirectional
shift register is shifted to the direction of R-40 from R-1.
When this pin is "L", bidirectional shift register shifts data
to the direction of R-1 from R-40.

Data Input

Logic Power Supply

29 DIN Shift register input pin with neither pull-up nor pull-down

30

V

CC

31

Data Output

Clock Input

Test Input I

32 DOUT

34 CLK

36 CHG

—

O

I

resistor. Display data is input in synchronization with
clock. (Positive logic)

Power supply pin for logic (except driver)
V

should be 4.5V to 5.5V.

CC

Serial output of bidirectional pin shift register. When R/L
is "H", DOUT outputs R-40's output. When R/L is "L",
DOUT outputs R-1's output.

I

Clock input pin with neither pull-up nor pull-down resistor.
Data of shift register is shifted from one stage to the next
at the rising edge of clock.

Test input pin with a pull-down resistor. Normally "L".
If CL = "H" in this condition, the driver outputs "H" or "L"
according to the corresponding latch output.
If CL = "H", setting CHG to "H" enables the driver output to
be fixed at "H" without respect to latch output.

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¡ Semiconductor MSC1163

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Condition Rating Unit Note

Logic Supply Voltage V

Driver Supply Voltage V

Input Voltage V

Data Output Voltage V

Driver Driving Frequency f
Power Dissipation P

Package Thermal Resistance

Storage Temperature T

DRV

R

STG

CC

HV

IN

OD

D

j-a

Applicable to logic supply

voltage pin

Applicable to driver supply

voltage pin

Applicable to all input

pins

Applicable to data output

pin

Notes: 1) Maximum Supply Voltage with respect to GND

2) Permanent damage may be caused if the voltage is supplied over the rating.

3) Package Thermal Resistance (between junction and atmosphere)
The junction temperature (Tj) given by the equation indicated below should not

exceed 150°C.

Tj=P ¥ R

+Ta (P: Maximum power consumption)

j–a

–0.3 to +6.5 V 1

VCC to 70 V 1, 2

–0.3 to VCC +0.3 V 1

–0.3 to VCC +0.3 V 1

0 to 15 kHz —Duty cycle 50% max

860

mW —Ta £ 25°C

145 °C/W 3—

–55 to +150 °C ——

7/13

¡ Semiconductor MSC1163

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Condition Max. Unit

Logic Supply Voltage V

High Level Input Voltage V

Low Level Input Voltage V

High Level Driver Output
Current

Low Level Driver Output
Current

CLK Frequency f

CLK Pulse Width t

Data in Setup Time t

Data in Hold Time t

LS Pulse Width t

CLK-LS Delay Time t

LS-CLK Delay Time t

LS-CHG Delay Time t
LS-CL Delay Time t

CHG Pulse Width t

WCHG

CL Pulse Width t

Operating Temperature T

CC

HV

IH

IL

OHVH

OHVL

f

WCLK

DS

DH

WLS

DCL

DLC

DLCG

DLCL

WCL

op

Applicable to logic supply voltage pin

Applicable to driver supply voltage pinDriver Supply Voltage V

Applicable to all input

pins

Applicable to all input

pins

Applicable to all driver output pinsI

Applicable to all driver output pinsI

See timing diagram

See timing diagram

See timing diagram

See timing diagram

See timing diagram

See timing diagram

See timing diagram

See timing diagram

See timing diagram

See timing diagram

See timing diagram

—

Min.

4.5

VCC=4.5V —V3.6

=5.5V —V4.4

V

CC

=4.5V 0.9 V—

V

CC

=5.5V 1.1 V—

V

CC

5.5 V

65 V10

–2 mA—

2mA—

4 MHz—

—ns75

—ns50

—ns50

—ns80

—ns50

—ns0

— ms0

— ms0

— ms2

— ms2

85 °C–40

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¡ Semiconductor MSC1163

ELECTRICAL CHARACTERISTICS

DC Characteristics

=5V±10%, VHV=10V to 65V, Ta=–40°C to +85°C)

(V

CC

Parameter Symbol Condition Max. Unit

Min.

Typ.

Logic Supply Current

I

Driver Supply Current

I

High Level Input Voltage

Low Level Input Voltage

Input Capacitance C

High Level Data Output
Voltage

Low Level Data Output
Voltage

High Level Data Output
Voltage

Low Level Data Output
Voltage

V

V

V

V

I

CC1

I

CC2

HV1

HV2

V

IH

V

IL

IN

IN

ODH1

ODL1

ODH2

ODL2

No load

V

=5.5V

CC

No load

V

=5.5V

CC

—

—

IO=–20mA

I

=20mA

O

IO=–0.1mA

I

=0.1mA

O

All input: Low

All input: High, All

driver output: High, Ta=25°C

All driver output: Low

All driver output:

High, Ta=25°C

V

=4.5V ——3.15

CC

V

=5.5V ——3.85

CC

VCC=4.5V 1.35——

V

=5.5V 1.65——

CC

Ta=25°CInput Leakage Current I

Ta=25°C

=4.5V ——4.2

V

CC

V

=5.5V ——5.2

CC

VCC=4.5V 0.2——

V

=5.5V 0.2——

CC

V

=4.5V ——3.5

CC

V

=5.5V ——4.5

CC

VCC=4.5V 1.1——

V

=5.5V 1.1——

CC

—

—

4.3

—

6.65

1.00.5—

1

3.82.45—

±1 mA——

—pF15—

mA

mA

mA

V

V

V

V

V

V

V

V

V

V

V

V

High Level Driver Output
Voltage

Low Level Driver Output
Voltage

AC Characteristics

Parameter Symbol Condition Max. UnitTyp.Min.

CLK-DOUT Delay Time t

Delay Time Low to High t

Transit Time Low to High t

Delay Time High to Low t

Transit Time High to Low t

OHVH

OHVL

PD

DLH

TLH

DHL

THL

I

=–2mAV

OHV

I

=2mAV

OHV

See timing diagram and test circuit

See timing diagram and test circuit

See timing diagram and test circuit

See timing diagram and test circuit

See timing diagram and test circuit

—V—VHV–3

3.0 V——

(V

=5V, VHV=65V, Ta=25°C)

CC

150 ns100—

1 ms0.3—

5 ms3—

1 ms0.3—

5 ms2—

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¡ Semiconductor MSC1163

10/13

TIMING DIAGRAM

1/f f

CLOCK

DIN

LS

HVO (OTHERS)

CL

HVO (1, 2, 39, 40)

CHG

DOUT

T1/2 T3/4

T39/40 T1/2 T3/4

t

WCLKtWCLK

tDHt

DS

tDHt

DS

t

WD

t

PD

t

PD

t

DCLtWLStDLC

t

DLCG

t

WCHG

t

WCHG

t

DLCL

t

WCL

t

WCL

t

DLH

t

DLH

t

DHL

t

DHL

t

DLH

90%

10%

10%

t

TLH

t

TLH

t

THL

t

THL

t

TLH

90%

¡ Semiconductor MSC1163

Test circuit

20pF

65V 5.0V

DIN

CLK

V

CC

V

HV

HVO1

30kW

HVO2

HVO40

DOUT

LS

R/L

CHG

CL

GND1, 2

30pF

11/13

¡ Semiconductor MSC1163

FUNCTIONAL DESCRIPTION

Notes on Use

1. The MSC1163GS is designed as an anode driver of VFD.
The data applied to the data input pin is read into the shift register at the rising edge
of the clock and shifted sequencially to the shift register synchronizing with the
clock.
The shift register output drives the output driver, passing through the latch and the
NOR circuit.
Setting the CL pin to "L" makes all driver outputs go into "L". This function can be
used for setting display blanking.

2. The contents of the shift register are undefined after power is turned on.
Therefore, two or more driver outputs may go into "H" at the same time after power­on.
To avoid this, take the following procedure:

1) Turn on the power of the logic portion while holding the CL pin to "L".

2) Turn on the power of the driver portion.

3) Apply a "L" level signal to the DIN pin and send clock pulses by the specified

number of grids to reset ("L") the entire contents of the shift register.

Function Table

LS

X
X

H

H

R-1R/L

H
L

R2n
R2n

R.X HVO.X

X
X

H

L

R1n
R1n

R3n
R3n

R2n
R2n

R4n
R4n

L

H

H

L

R3n
R3n

R5n
R5n

CLK

H
H

L
L

CL CHG

L
H

H

H

DIN

H

L

H

L

X

H

L

L

LL NCXH

L : Low Level, H: High Level, X: Don't Care, NC: No Change

R39n
R39n

H
L

DOUTR-40• • • • • • • •R-4R-3R-2

R39n
R39n

R2n
R2n

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¡ Semiconductor MSC1163

PACKAGE DIMENSIONS

(Unit : mm)

SSOP60-P-700-0.65-BK

Mirror finish

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more

1.21 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

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