Datasheet MC 33172 DG Datasheet

Page 1

MC33171, MC33172, MC33174, NCV33172

Single Supply 3.0 V to 44 V, Low Power Operational Amplifiers

Quality bipolar fabrication with innovative design concepts are

employed for the MC33171/72/74 series of monolithic operational amplifiers. These devices operate at 180 mA per amplifier and offer 1.8 MHz of gain bandwidth product and 2.1 V/ms slew rate without the use of JFET device technology. Although this series can be operated from split supplies, it is particularly suited for single supply operation, since the common mode input voltage includes ground potential (VEE). With a Darlington input stage, these devices exhibit high input resistance, low input offset voltage and high gain. The all NPN output stage, characterized by no deadband crossover distortion and large output voltage swing, provides high capacitance drive capability, excellent phase and gain margins, low open loop high frequency output impedance and symmetrical source/sink AC frequency response.

The MC33171/72/74 are specified over the industrial/automotive temperature ranges. The complete series of single, dual and quad operational amplifiers are available in plastic as well as the surface mount packages.

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PDIP−8

P SUFFIX

CASE 626

SO−8

D, VD SUFFIX

CASE 751

PDIP−14

P, VP SUFFIX

CASE 646

Features

• Low Supply Current: 180 mA (Per Amplifier)

• Wide Supply Operating Range: 3.0 V to 44 V or ±1.5 V to ±22 V

• Wide Input Common Mode Range, Including Ground (V

)

• Wide Bandwidth: 1.8 MHz

• High Slew Rate: 2.1 V/ms

• Low Input Offset Voltage: 2.0 mV

• Large Output Voltage Swing: −14.2 V to +14.2 V

(with ±15 V Supplies)

• Large Capacitance Drive Capability: 0 pF to 500 pF

• Low Total Harmonic Distortion: 0.03%

• Excellent Phase Margin: 60°

• Excellent Gain Margin: 15 dB

• Output Short Circuit Protection

• ESD Diodes Provide Input Protection for Dual and Quad

• Pb−Free Packages are Available

• NCV Prefix for Automotive and Other Applications Requiring Site

and Control Changes

SO−14

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet.

DEVICE MARKING INFORMATION

See general marking information in the device marking section on page 10 of this data sheet.

D, VD SUFFIX

CASE 751A

TSSOP−14

DTB SUFFIX

CASE 948G

October, 2006 − Rev. 9

1 Publication Order Number:

MC33171/D

Page 2

MC33171, MC33172, MC33174, NCV33172

PIN CONNECTIONS

Inputs

−

Offset Null

Inv. Input

Noninv. Input

Output 1

Inputs 1

Bias

SINGLE

− +

Output

Offset Null

(Single, Top View)

DUAL

− +

Output 2

− Inputs 2

(Top View)

Q3 Q4 Q5 Q6 Q7

Q9 Q10

Q11

Q13

Output 1

Inputs 1

Inputs 2

Output 2

Q14

QUAD

−

Output 4

−

Inputs 4

Inputs 3

Output 3

(Top View)

Q17

Q18

R6 R7

C2 D3

Q19

Q16Q15

Output

Q12

R3 R4

Offset Null

(MC33171)

Figure 1. Representative Schematic Diagram

(Each Amplifier)

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Current

Limit

VEE/GND

Page 3

MC33171, MC33172, MC33174, NCV33172

MAXIMUM RATINGS

Rating Symbol Value Unit

Supply Voltage VCC/V

Input Differential Voltage Range V

Input Voltage Range V

Output Short Circuit Duration (Note 2) t

Operating Ambient Temperature Range T

Operating Junction Temperature T

Storage Temperature Range T

IDR

stg

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

±22 V

(Note 1) V

Indefinite sec

(Note 3) °C

+150 °C

−65 to +150 °C

DC ELECTRICAL CHARACTERISTICS (V

= +15 V, VEE = −15 V, RL connected to ground, TA = +25°C, unless otherwise noted.)

Characteristics Symbol Min Typ Max Unit

Input Offset Voltage (VCM = 0 V)

VCC = +15 V, VEE = −15 V, TA = +25°C VCC = +5.0 V, VEE = 0 V, TA = +25°C VCC = +15 V, VEE = −15 V, TA = T

low

to T

high

(Note 3)

Average Temperature Coefficient of Offset Voltage

Input Bias Current (VCM = 0 V)

TA = +25°C TA = T

low

to T

high

(Note 3)

Input Offset Current (VCM = 0 V)

TA = +25°C TA = T

low

to T

high

(Note 3)

Large Signal Voltage Gain (VO = ±10 V, RL = 10 k)

TA = +25°C TA = T

low

to T

high

(Note 3)

Output Voltage Swing

VCC = +5.0 V, VEE = 0 V, RL = 10 k, TA = +25°C VCC = +15 V, VEE = −15 V, RL = 10 k, TA = +25°C VCC = +15 V, VEE = −15 V, RL = 10 k, TA = T

low

VCC = +5.0 V, VEE = 0 V, RL = 10 k, TA = +25°C VCC = +15 V, VEE = −15 V, RL = 10 k, TA = +25°C VCC = +15 V, VEE = −15 V, RL = 10 k, TA = T

low

Output Short Circuit (TA = +25°C)

to T

high

(Note 3)

DVIO/DT

VOL

−

2.0

2.5

−

− 10 −

−

50 25

3.5

13.6

13.3

−

5.0

−

500

−

4.3

14.2

−

0.05

−14.2

−

4.5

5.0

6.5

100 200

20 40

−

0.15

−13.6

−13.3

Input Overdrive = 1.0 V, Output to Ground

Source Sink

Input Common Mode Voltage Range

TA = +25°C TA = T

low

to T

high

(Note 3)

ICR

3.0 15

5.0 27

VEE to (VCC −1.8) VEE to (VCC −2.2)

−

Common Mode Rejection Ratio (RS ≤ 10 k), TA = +25°C CMRR 80 90 − dB

Power Supply Rejection Ratio (RS = 100 W), TA = +25°C

Power Supply Current (Per Amplifier)

VCC = +5.0 V, VEE = 0 V, TA = +25°C VCC = +15 V, VEE = −15 V, TA = +25°C VCC = +15 V, VEE = −15 V, TA = T

low

1. Either or both input voltages must not exceed the magnitude of VCC or V

2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded.

3. MC3317x T MC3317xV, NCV33172 T

to T

(Note 3)

high

EE.

= −40°CT

low

= −40°CT

low

= +85°C

high

= +125°C

high

PSRR 80 100 − dB

−

180 220

−

250 250 300

mV/°C

V/mV

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Page 4

MC33171, MC33172, MC33174, NCV33172

√

AC ELECTRICAL CHARACTERISTICS (V

Characteristics

Slew Rate (Vin = −10 V to +10 V, RL = 10 k, CL = 100 pF)

AV +1 AV −1

= +15 V, VEE = −15 V, RL connected to ground, TA = +25°C, unless otherwise noted.)

Symbol Min Typ Max Unit

1.6

−

2.1

−

V/ms

Gain Bandwidth Product (f = 100 kHz) GBW 1.4 1.8 − MHz

Power Bandwidth

= +1.0 RL = 10 k, VO = 20 Vpp, THD = 5%

Phase Margin

RL = 10 k RL = 10 k, CL = 100 pF

Gain Margin

RL = 10 k RL = 10 k, CL = 100 pF

Equivalent Input Noise Voltage

BWp

− 35 −

−

60 45

5.0

− 32 −

−

nV/Hz

RS = 100 W, f = 1.0 kHz

Equivalent Input Noise Current (f = 1.0 kHz) I

Differential Input Resistance

Vcm = 0 V

Input Capacitance C

Total Harmonic Distortion

THD

AV = +10, RL = 10 k, 2.0 Vpp ≤ VO ≤ 20 Vpp, f = 10 kHz

− 0.2 −

pA/ Hz√

− 300 −

− 0.8 − pF

− 0.03 −

Channel Separation (f = 10 kHz) CS − 120 − dB

Open Loop Output Impedance (f = 1.0 MHz) z

− 100 −

kHz

Deg

E (V)

−0.8

E RAN

LTA

−1.6

VCC/V

DVIO = 5.0 mV

= ±1.5 V to ± 22 V

−1.0

VCC/VEE = ±5.0 V to ± 22 V

TA = 25°C

Source

DE V

−2.4

N M

0.1 V

−55 −25 0 25 50 75 100

V , INPUT

ICR

TA, AMBIENT TEMPERATURE (°C)

Figure 2. Input Common Mode Voltage Range

versus Temperature

125 0 1.0 2.0 3.0 4.0

V, OUTPUT SATURATION VOLTAGE (V)

sat

1.0

Sink

IL, LOAD CURRENT (±mA)

Figure 3. Split Supply Output Saturation

versus Load Current

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Page 5

MC33171, MC33172, MC33174, NCV33172

3 0

VCC/VEE = ±15 V

RL = 10 k V

= 0 V

out

−10

TA = 25°C 1 − Phase

, OPEN LOOP VOLTAGE GAIN (dB)

2 − Phase, CL = 100 pF

−20 3 − Gain

VOL

4 − Gain, CL = 100 pF

−30

100 k 1.0 M 10 M

f, FREQUENCY (Hz)

Phase

Margin

= 58°

= 15 dB

Figure 4. Open Loop Voltage Gain and

Phase versus Frequency

1.3

VCC/V

= ±15 V

1.2

GBW

1.1

1.0

0.9

RL = 10 k

Gain

Margin

120

140

160

180

200

220

m, PHASE MARGIN (DEGREES)

, EXCESS PAHSE (DEGREES)

10 20 50 100 200 500 1.0 k

50 mV/DIV10 V/DIV

VCC/V

= ±15 V

CL, LOAD CAPACITANCE (pF)

= +1.0

VOL

RL = 10 k DVO = 20 mV TA = 25°C

Figure 5. Phase Margin and Percent

Overshoot versus Load Capacitance

5.0 ms/DIV

VCC/VEE = ±15 V VCM = 0 V VO = 0 V DIO = ±0.5 mA TA = 25°C

%, PERCENT OVERSHOOT

GBW AND SR (NORMALIZED)

0.8

0.7

−55 −25 0 25 50 75 100 125

TA, AMBIENT TEMPERATURE (°C)

Figure 6. Normalized Gain Bandwidth Product

and Slew Rate versus Temperature

140

VCC/VEE = ±15 V AV = +1.0

120

RL = 10 k CL = 100 pF

100

TA = 25°C

z , OUTPUT IMPEDANCE ()Ω

200 2.0 k 20 k 200 k 2.0 M 0 5.0 10 15 20 25

AV = 1000

AV = 100

AV = 10 AV = 1.0

f, FREQUENCY (Hz)

I, I, POWER SUPPLY CURRENT (mA)

1.1

1. TA = −55°C

2. TA = 25°C

3. TA = 125°C

0.9

0.7

0.5

0.3

0.1

5.0 ms/DIV

Figure 7. Small and Large Signal

Transient Response

Quad

Dual

Single

VCC/VEE, SUPPLY VOLTAGE (±V)

1 2 3

1 2

Figure 8. Output Impedance and Frequency Figure 9. Supply Current versus Supply Voltage

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Page 6

MC33171, MC33172, MC33174, NCV33172

APPLICATIONS INFORMATION − CIRCUIT DESCRIPTION/PERFORMANCE FEATURES

Although the bandwidth, slew rate, and settling time of the MC33171/72/74 amplifier family is similar to low power op amp products utilizing JFET input devices, these amplifiers offer additional advantages as a result of the PNP transistor differential inputs and an all NPN transistor output stage.

Because the input common mode voltage range of this input stage includes the VEE potential, single supply operation is feasible to as low as 3.0 V with the common mode input voltage at ground potential.

The input stage also allows differential input voltages up to ±44 V, provided the maximum input voltage range is not exceeded. Specifically, the input voltages must range between VCC and VEE supply voltages as shown by the maximum rating table. In practice, although not recommended, the input voltages can exceed the V voltage by approximately 3.0 V and decrease below the V

voltage by 0.3 V without causing product damage, although output phase reversal may occur. It is also possible to source up to 5.0 mA of current from VEE through either inputs’ clamping diode without damage or latching, but phase reversal may again occur. If at least one input is within the common mode input voltage range and the other input is within the maximum input voltage range, no phase reversal will occur. If both inputs exceed the upper common mode input voltage limit, the output will be forced to its lowest voltage state.

Since the input capacitance associated with the small geometry input device is substantially lower (0.8 pF) than that of a typical JFET (3.0 pF), the frequency response for a given input source resistance is greatly enhanced. This becomes evident in D−to−A current to voltage conversion applications where the feedback resistance can form a pole with the input capacitance of the op amp. This input pole creates a 2nd Order system with the single pole op amp and is therefore detrimental to its settling time. In this context, lower input capacitance is desirable especially for higher values of feedback resistances (lower current DACs). This input pole can be compensated for by creating a feedback zero with a capacitance across the feedback resistance, if necessary, to reduce overshoot. For 10 kW of feedback resistance, the MC33171/72/74 family can typically settle to within 1/2 LSB of 8 bits in 4.2 ms, and within 1/2 LSB of 12 bits in 4.8 ms for a 10 V step. In a standard inverting unity gain fast settling configuration, the symmetrical slew rate is typically ±2.1 V/ms. In the classic noninverting unity gain configuration the typical output positive slew rate is also

2.1 V/ms, and the corresponding negative slew rate will usually exceed the positive slew rate as a function of the fall time of the input waveform.

The all NPN output stage, shown in its basic form on the equivalent circuit schematic, offers unique advantages over the more conventional NPN/PNP transistor Class AB output stage. A 10 kW load resistance can typically swing within

0.8 V of the positive rail (V

) and negative rail (VEE),

providing a 28.4 Vpp swing from ±15 V supplies. This large output swing becomes most noticeable at lower supply voltages.

The positive swing is limited by the saturation voltage of

the current source transistor Q7, the V

of the NPN pull−up

transistor Q17, and the voltage drop associated with the short circuit resistance, R5. For sink currents less than

0.4 mA, the negative swing is limited by the saturation voltage of the pull−down transistor Q15, and the voltage drop across R4 and R5. For small valued sink currents, the above voltage drops are negligible, allowing the negative swing voltage to approach within millivolts of VEE. For sink currents (> 0.4 mA), diode D3 clamps the voltage across R4. Thus the negative swing is limited by the saturation voltage of Q15, plus the forward diode drop of D3 (≈VEE +1.0 V). Therefore an unprecedented peak−to−peak output voltage swing is possible for a given supply voltage as indicated by the output swing specifications.

If the load resistance is referenced to VCC instead of ground for single supply applications, the maximum possible output swing can be achieved for a given supply voltage. For light load currents, the load resistance will pull the output to VCC during the positive swing and the output will pull the load resistance near ground during the negative swing. The load resistance value should be much less than that of the feedback resistance to maximize pull−up capability.

Because the PNP output emitter−follower transistor has been eliminated, the MC33171/72/74 family offers a 15 mA minimum current sink capability, typically to an output voltage of (VEE +1.8 V). In single supply applications the output can directly source or sink base current from a common emitter NPN transistor for current switching applications.

In addition, the all NPN transistor output stage is inherently faster than PNP types, contributing to the bipolar amplifier’s improved gain bandwidth product. The associated high frequency low output impedance (200 W typ @ 1.0 MHz) allows capacitive drive capability from 0 pF to 400 pF without oscillation in the noninverting unity gain configuration. The 60° phase margin and 15 dB gain margin, as well as the general gain and phase characteristics, are virtually independent of the source/sink output swing conditions. This allows easier system phase compensation, since output swing will not be a phase consideration. The AC characteristics of the MC33171/72/74 family also allow excellent active filter capability, especially for low voltage single supply applications.

Although the single supply specification is defined at

5.0 V, these amplifiers are functional to at least 3.0 V @ 25°C. However slight changes in parametrics such as bandwidth, slew rate, and DC gain may occur.

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Page 7

MC33171, MC33172, MC33174, NCV33172

If power to this integrated circuit is applied in reverse polarity, or if the IC is installed backwards in a socket, large unlimited current surges will occur through the device that may result in device destruction.

As usual with most high frequency amplifiers, proper lead dress, component placement and PC board layout should be exercised for optimum frequency performance. For example, long unshielded input or output leads may result in unwanted input/output coupling. In order to preserve the relatively low input capacitance associated with these amplifiers, resistors connected to the inputs should be immediately adjacent to the input pin to minimize additional stray input capacitance. This not only minimizes the input

pole for optimum frequency response, but also minimizes extraneous “pick up” at this node. Supply decoupling with adequate capacitance immediately adjacent to the supply pin is also important, particularly over temperature, since many types of decoupling capacitors exhibit great impedance changes over temperature.

The output of any one amplifier is current limited and thus protected from a direct short to ground. However, under such conditions, it is important not to allow the device to exceed the maximum junction temperature rating. Typically for ±15 V supplies, any one output can be shorted continuously to ground without exceeding the maximum temperature rating.

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Page 8

2.2 k 510 k

1.0 k

100 k

−

100 k

= 101

BW ( −3.0 dB) = 20 kHz

MC33171, MC33172, MC33174, NCV33172

VO 0

100 k

3.6 Vpp

100 k

10 k

AV = 10

BW ( −3.0 dB) = 200 kHz

3.8 Vpp

−

10 k

100 kRL

Figure 10. AC Coupled Noninverting Amplifier

with Single +5.0 V Supply

4.7 k

100 k

VO 2.5 V

= 10

BW ( −3.0 dB) = 200 kHz

100 k

−

1.0 M

50 k R

4.2 Vpp

Figure 12. DC Coupled Inverting Amplifier

Maximum Output Swing with Single

+5.0 V Supply

Vin ≥ 0.2 Vdc

−

fo = 1.0 kHz

fo =

4 p RC

0.02

0.01

2R 32 k

16 k16 k

0.02

Figure 11. AC Coupled Inverting Amplifier

with Single +5.0 V Supply

6 5

− 1

10 k

Offset Nulling range is approximately ±80 mV with a 10 k potentiometer, MC33171 only.

Figure 13. Offset Nulling Circuit

2 H

p foC

fo = 30 kHz Q = 10 HO = 1.0

R2 =

4Q2R1 −R3

GBW

R1 R3

< 0.1

0.047

2.2 k

−

1.1 k

0.047

5.6 k

0.4

Then:

R1 =

Given fo = center frequency Ao = Gain at center frequency

R3 =

Choose Value fo, Q, Ao, C For less than 10% error for operational amplifier, where fo and GBW are expressed in Hz.

Figure 14. Active High−Q Notch Filter Figure 15. Active Bandpass Filter

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Page 9

MC33171, MC33172, MC33174, NCV33172

ORDERING INFORMATION

Op Amp

Function

Single

Dual

Quad

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. **NCV prefix for automotive and other applications requiring site and control changes.

Device

MC33171D

MC33171DG SO−8

MC33171DR2 SO−8

MC33171DR2G SO−8

MC33171P Plastic DIP

MC33171PG Plastic DIP

MC33172D

MC33172DG SO−8

MC33172DR2 SO−8

MC33172DR2G SO−8

MC33172P Plastic DIP

MC33172PG Plastic DIP

MC33172VD

MC33172VDG SO−8

MC33172VDR2 SO−8

MC33172VDR2G SO−8

NCV33172DR2** SO−8 2500 / Tape & Reel

MC33174D

MC33174DG SO−14

MC33174DR2 SO−14

MC33174DR2G SO−14

MC33174DTB TSSOP−14*

MC33174DTBG TSSOP−14*

MC33174DTBR2 TSSOP−14*

MC33174DTBR2G TSSOP−14*

MC33174P Plastic DIP

MC33174PG Plastic DIP

MC33174VDR2

MC33174VDR2G SO−14

MC33174VP Plastic DIP

MC33174VPG Plastic DIP

Operating

Temperature Range Package Shipping

SO−8

98 Units/Rail

(Pb−Free)

TA = −40° to +85°C

(Pb−Free)

SO−8

(Pb−Free)

TA = −40° to +85°C

(Pb−Free)

SO−8

(Pb−Free)

TA = −40° to +125°C

(Pb−Free)

SO−14

(Pb−Free)

TA = −40° to +85°C

(Pb−Free)

SO−14

(Pb−Free)

TA = −40° to +125°C

(Pb−Free)

2500 / Tape & Reel

50 Units/Rail

98 Units/Rail

2500 / Tape & Reel

50 Units/Rail

98 Units/Rail

2500 / Tape & Reel

55 Units/Rail

2500 / Tape & Reel

96 Units/Rail

2500 / Tape & Reel

25 Units/Rail

2500 / Tape & Reel

25 Units/Rail

†

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Page 10

MC33171, MC33172, MC33174, NCV33172

MARKING DIAGRAMS

PDIP−14

P SUFFIX

CASE 646

MC33174P

AWLYYWWG

PDIP−8

P SUFFIX

CASE 626

MC3317xP

YYWWG

AWL

PDIP−14

VP SUFFIX

CASE 646

MC33174VP

AWLYYWWG

SO−8 D SUFFIX CASE 751

3317x ALYW

TSSOP−14

DTB SUFFIX

CASE 948G



SO−8 MC33172VD NCV33172D

CASE 751

SO−14

D SUFFIX

CASE 751A

MC33174DG

AWLYWW

3317V ALYW



SO−14 VD SUFFIX CASE 751A

MC33174VDG

AWLYWW

MC33

174

ALYW



x = 1 or 2 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or  = Pb−Free Package

(Note: Microdot may be in either location)

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Page 11

NOTE 2

−T−

SEATING PLANE

MC33171, MC33172, MC33174, NCV33172

−B−

−A−

0.13 (0.005) B

PACKAGE DIMENSIONS

PDIP−8

P SUFFIX

CASE 626−05

ISSUE L

NOTES:

1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.

2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS).

3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

DIM MIN MAX MIN MAX

A 9.40 10.16 0.370 0.400 B 6.10 6.60 0.240 0.260 C 3.94 4.45 0.155 0.175

D 0.38 0.51 0.015 0.020 F 1.02 1.78 0.040 0.070 G 2.54 BSC 0.100 BSC H 0.76 1.27 0.030 0.050 J 0.20 0.30 0.008 0.012 K 2.92 3.43 0.115 0.135 L 7.62 BSC 0.300 BSC

M −−− 10 −−− 10

N 0.76 1.01 0.030 0.040

INCHESMILLIMETERS



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Page 12

−Y−

−Z−

MC33171, MC33172, MC33174, NCV33172

PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AH

NOTES:

−X− A

0.25 (0.010)

SEATING PLANE

0.10 (0.004)

0.25 (0.010) Z

SXS

X 45



1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 8 0 8



N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244

INCHES

SOLDERING FOOTPRINT*

1.52

0.060

7.0

0.275

0.6

0.024

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

4.0

0.155

1.270

0.050

SCALE 6:1

inches

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Page 13

−T−

SEATING PLANE

14 8

MC33171, MC33172, MC33174, NCV33172

PACKAGE DIMENSIONS

PDIP−14

CASE 646−06

ISSUE P

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

14 PL

0.13 (0.005)

3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

DIM MIN MAX MIN MAX

A 0.715 0.770 18.16 19.56 B 0.240 0.260 6.10 6.60 C 0.145 0.185 3.69 4.69 D 0.015 0.021 0.38 0.53 F 0.040 0.070 1.02 1.78 G 0.100 BSC 2.54 BSC H 0.052 0.095 1.32 2.41 J 0.008 0.015 0.20 0.38 K 0.115 0.135 2.92 3.43 L

0.290 0.310 7.37 7.87

M −−− 10 −−− 10

N 0.015 0.039 0.38 1.01

MILLIMETERSINCHES



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Page 14

−T−

SEATING PLANE

MC33171, MC33172, MC33174, NCV33172

PACKAGE DIMENSIONS

SOIC−14

CASE 751A−03

ISSUE H

NOTES:

1. DIMENSIONING AND TOLERANCING PER

−A−

−B−

P 7 PL

0.25 (0.010) B

D 14 PL

0.25 (0.010) A

R X 45



SOLDERING FOOTPRINT*

7.04

14X

0.58

14X

1.52

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 8.55 8.75 0.337 0.344 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009

M 0 7 0 7

 

P 5.80 6.20 0.228 0.244 R 0.25 0.50 0.010 0.019

INCHESMILLIMETERS

1.27 PITCH

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

http://onsemi.com

Page 15

0.10 (0.004)

−T−

SEATING PLANE

MC33171, MC33172, MC33174, NCV33172

PACKAGE DIMENSIONS

TSSOP−14

CASE 948G−01

ISSUE B

NOTES:

1. DIMENSIONING AND TOLERANCING PER

14X REFK

0.25 (0.010)

U0.15 (0.006) T

2X L/2

0.10 (0.004) V

PIN 1 IDENT.

U0.15 (0.006) T

−V−

−U− F

DETAIL E

SECTION N−N

DETAIL E

−W−

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−.

DIM MIN MAX MIN MAX

A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C −−− 1.20 −−− 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC

M 0 8 0 8



INCHESMILLIMETERS

SOLDERING FOOTPRINT*

7.06

14X

0.36

14X

1.26

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

http://onsemi.com

0.65

PITCH

Page 16

MC33171, MC33172, MC33174, NCV33172

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MC33171/D

Datasheet MC 33172 DG Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual