Datasheet M41T00 Datasheet (SGS Thomson Microelectronics)

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M41T00

■ 2.0V to 5.5V SUPPLY VOLTAGE

■ COUNTERS for SECONDS, MINUTES,

HOURS, DAY, DATE , MONTH, YEARS and CENTURY

■ YEAR 2000 COMPLIANT

■ SOFTWARE CLOCK CALIBRATION

■ AUTOMATIC SWITCH-OVER and DESELECT

CIRCUITRY

■ I

C BUS C O MPATI BLE

■ ULTRA-LOW BATTERY SUPPLY CURRENT

of 1µA

■ LOW OPERATING CURRENT of 300µA

■ OPERATING TEMP ERATURE of –40 to 85°C

■ AUTOMATIC LEAP YEAR COMPENSATION

■ SPECIAL SOFTWARE PROGRAMMABLE

OUTPUT

DESCRIPTION

The M41 T0 0 TIMEKEEPER

RAM is a low power Serial TIMEKEEPER with a built-in 32.768kHz os cillator (external crystal controlled). Eight bytes of the RAM are u sed for the clock/calenda r function and are configured in binary coded decimal (BCD) format. Addresses and data are transferred serially via a two-line bi-directional bus. The bu ilt-in address register is incremented automatically after each write or read data byte.

Table 1. Signal Names

OSCI Oscillator Input OCSO Oscillator Output

Serial Access TIMEKEEPER

SO8 (M)

150mil Width

Figure 1. Logic Diagram

OSCI

SCL

M41T00

BAT

OSCO

SDA

FT/OUT

SDA Serial Data Address Input / Output SCL Serial Clock V

BA T

Frequency Test / Output Driver (Open Drain)

Battery Supp ly Voltage Supply Voltage Ground

AI00530

1/15May 2000

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M41T00

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

STG

Note: Stress es greater than thos e listed under "A bsolute Maximum Rati ngs" may cause permanent damage to the device. This i s a stre ss

rating onl y and funct i onal operat i on of the dev i ce at these or any other conditio ns above those indicated in the op erational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability.

CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in th e B attery Ba ck- up m ode.

Ambient Operating Temperature –40 to 85 °C Storage Temperature (VCC Off, Oscillator Off) Input or Output Voltages –0.3 to 7 V Supply Voltage –0.3 to 7 V Output Current 20 mA Power Dissipation 0.25 W

–55 to 125 °C

Figure 2. SOIC Connections

M41T00

OSCI V

BAT

1 2 3 4

8 7 6 5

AI00531

FT/OUTOSCO SCL SDAV

The M41T00 clock has a built-in power sense circuit which detects power failures and automatically switches to the battery supply during power failures. The energy needed to sustain the RAM and clock operations can be supplied from a small lithium co in cell.

Typical data retention time is in excess of 5years with a 50mA/h 3V lithium cell. The M41T00 is supplied in 8 lead Plastic Small Outline package.

OPERATION

The M41T00 clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 8 bytes contained in the device can then be accessed sequentially in the following order:

1. Seconds Regis ter

2. Minutes Register

3. Century/Hours Register

4. Day Register

5. Date Register

6. Month Register

7. Years Register

8. Control Register The M41T00 clock continually monitors V

out of tolerance condition. Shoul d V V

, the device terminates an ac ces s in progress

for an

fall belo w

and resets the device ad dress counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from an out of tolerance system. When V

falls below VSO, the device automatically switches over to the battery and powers down into an ult ra low current mode of operation to conserve battery life. Upon power-up, the device switches from battery to V

at VSO and recognizes inputs.

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Figure 3. Block Diagram

M41T00

OSCI

OSCO

FT/OUT

BAT

SCL

SDA

OSCILLATOR

32.768 kHz

VOLTAGE

SENSE and

SWITCH

CIRCUITRY

SERIAL

BUS

INTERFACE

DIVIDER

CONTROL

LOGIC

ADDRESS

1 Hz

SECONDS

MINUTES

CENTURY/HOURS

DAY

DATE

MONTH

YEAR

CONTROL

AI00603

Table 3. Register Map

Address

Data

D7 D6 D5 D4 D3 D2 D1 D0

0 ST 10 Seconds Seconds Seconds 00-59 1 X 10 Minutes Minutes Minutes 00-59

(1)

CEB

CB 10 Hours Hours Century/Hour 0-1/00-23 3 XXXXX Day Day 01-07 4 X X 10 Date Date Date 01-31

5 X X X 10 M. Month Month 01-12 6 10 Years Years Year 00-99 7 OUT FT S Calibration Control

Note: 1. When CEB is set to ’1’, CB will toggle from ’0’ to ’1’ or from ’1’ to ’ 0’ a t the turn of the century (dependent upon the initial value set).

Keys: S = SIGN Bit

When CEB is set to ’0’, CB will not toggle.

FT = FREQUENCY TEST Bit ST = STOP Bit OUT = Output level

X = Don’t care CEB = Cent ury Enable Bit CB = Century Bit

Function/Rang e

BCD Format

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M41T00

Table 4. AC Measurement Conditions

Input Rise and Fall Times ≤ 5ns

0.2V

0.3V

to 0.8V

to 0.7V

Input Pulse Voltages Input and Output Timing Ref.

Voltages

Note that Output Hi-Z is defined as the point where data is no longer driven.

2-WIRE BUS CHARACTERISTICS

This bus is intended for communication between different ICs. It consists of two lines: one bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the SCL lines must be connected to a positive supply voltage via a pull-up resistor.

The following protocol has been defined: – Data transfer may be initiated only when the bus

is not busy.

– During data trans fer, the dat a line mus t remain

stable whenever the clock line is High. Changes in the data line while the clock line is High will be interpreted as control signals.

Accordingly, the following bus conditions have been defined:

Bus not busy. Both data and clock lines remain High.

Start data transfer. A change in the state of t he data line, from High to Low, while the clock is High, defines the START condition.

Stop data transfer. A change in the state of the data line, from Low to High, while the clock is High, defines the STOP condition.

Figure 4. AC Testing Load Circuit

0.8V

0.2V

0.7V

0.3V

AI02568

Data valid. The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the High period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.

By definition, a device that gives out a message is called "transmitter", the receiving de vice t hat g ets the message is called "rece iver". The device that controls the message is called "master". The devices that are controlled by the master are cal led "sla ve s".

Table 5. Capacitance

= 25 °C, f = 1 MHz)

Symbol Parameter Min Max Unit

(3)

OUT

Note: 1. Effective capacitance measure d wi th power su pply at 5V.

2. Sampled only, not 100% tested.

3. Outputs deselected.

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(1, 2)

Input Capacitance (SCL) 7 pF Output Capacitance (SDA, FT/OUT) 10 pF Low-pass filter input time constant (SDA and SCL) 250 1000 ns

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M41T00

Table 6. DC Characteristics

= –40 to 85°C; VCC = 2.0V to 5.5V)

Symbol Parameter Test Condition Min Typ Max Unit

Input Leakage Current

CC1

CC2

V V

BAT

Note: 1. STMicroelectroni cs recommends the RAYOVA C BR1225 or BR 1632 (or equivalent) as the battery sup pl y.

Output Leakage Current

Supply Current Switch Frequency = 100kHz 300 µA Supply Current (Standby) Input Low Voltage –0.3

Input High Voltage

Output Low Voltage

(1)

Battery Supply Voltage 2 3 3.5 V

Battery Supply Current

Table 7. Power Down/Up Trip Points DC Characteristics

0V ≤ V

OUT

≤ V

SCL, SDA = V

= 3mA

= 25°C, VCC = 0V,

Oscillator ON, V

≤ V

BAT

– 0.3V

= 3V

(1)

0.7 V

±1 µA ±1 µA

70 µA

0.3 V

VCC + 0.8

0.4 V

0.8 1 µA

(TA = –40 to 85°C)

Symbol Parameter Min Typ Max Unit

(2)

Note: 1. All voltages referenced to VSS.

2. Switch-over and deselect poi nt.

Battery Back-up Switchover Voltage

BA T

– 0.70 V

– 0.50 V

BAT

BA T

– 0.30

V V

Table 8. Crystal Electrical Characteristics

(Externally Supplied)

Symbol Parameter Min Typ Max Unit

Note: Load c apacitor s are i ntegra ted within the M41T 00. C ircuit board layout consi deratio ns fo r the 32.768k Hz cry stal of mini mum tr ace

lengths and isolation from RF generating signals should be taken into account . STMicroelectron i cs recommends the KDS DT-38 Tuning Fork Type quartz cry st al for industri al temperatur e operations .

KDS can b e contacted at 913-491-6825 or http://w ww.kdsj.co .j p for further in formation on t hi s crystal type.

Resonant Frequency 32.768 kHz Series Resistance 35 kΩ Load Capacitance 12.5 pF

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M41T00

Table 9. Power Down/Up AC Characteristics

(1)

(TA = –40 to 85°C)

Symbol Parameter Min Max Unit

REC

Note: 1. VCC fall time should not exceed 5mV/µs.

SCL and SDA at VIH before Power Down SCL and SDA at VIH after Power Up

0ns

10 µs

Figure 5. Power Down/Up Mode AC Waveforms

VSO

SDA SCL

tPD

DON'T CARE

tREC

AI00596

Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level put on the bus b y the receiver, whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte. Also, a master receiver must generate an acknowledge a fter the reception of e ach byte that has been clocked out of the slave transmitter.

The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable Low during the High period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end-of-data to the slave transm itter by not generating an acknowledge on t he last byte that has been clocked out of the slave. In this case, the transmitter must leave the data line High to enable the master to generate the STOP condition.

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M41T00

Table 10. AC Characteristics

= –40 to 85°C; VCC = 2.0V to 5.5V)

Symbol Parameter Min Max Unit

SCL

LOW

HIGH

HD:STA

SU:STA

SU:DAT

HD:DAT

SU:STO

BUF

Note: 1. Transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of SCL.

WRITE MODE

In this mode the master transmitter transmits to the M41T00 slave receiver. Bus protocol is shown in Figure 10. Following the START condition and slave address, a logic ’0’ (R/W bus and indicates to the addressed device that word address An will follow and is to be written to the on-chip address p ointer. Th e data wo rd to be written to the memory is strobed in next and the internal address pointer is incremented to the next memory location within the RAM on the reception of an acknowledge clock. The M 41T00 slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address and again after it has received the word address and each data byte (see Figure 9).

READ MODE

In this mode, the master reads the M41T00 s lave after setting the slave address (see Figure 11). Following the write mode control bit (R/W

SCL Clock Frequency 0 100 kHz Clock Low Period 4.7 µs

Clock High Period 4 µs SDA and SCL Rise Time 1 µs SDA and SCL Fall Time 300 ns START Condition Hold Time

(after this period the first clock pulse is generated) START Condition Setup Time

(only relevant for a repeated start condition) Data Setup Time 250 ns

(1)

Data Hold Time 0 µs STOP Condition Setup Time 4.7 µs Time the bus must be free before a new transmission can start 4.7 µs

4µs

4.7 µs

ten to the on-chip address pointer. Next the START condition and slave address are repeated, followed by the READ mode control bit (R/W At this point, the master transmitter becomes the

= 0) is placed on the

master receiver. The data byte which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter. The address pointer is only incremented on reception of an acknowledge bit. The M41T00 s lave tr ansmitt er will now place the data byte at address A

on the bus. The ma ster re-

n+1

ceiver reads and acknowledges the n ew byte and the address pointer is incremented to A

This cycle of reading con secutive addresses will continue until the mast er receiver sends a STOP condition to the slave transmitter.

An alternate READ mode may also be implemented, whereby the master reads the M41T00 slave without first writing to the (volatile) a ddress pointer. The first address that is read is the last one

= 0) and

stored in the pointer, see Figure12.

the acknowledge bit, the word address An is writ-

n+2

=1).

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M41T00

Figure 6. Serial Bus Data Transfer Sequence

DATA LINE

STABLE

DATA VALID

CLOCK

DATA

START

CONDITION

Figure 7. Acknowledgment Sequen ce

START

SCLK FROM MASTER

DATA OUTPUT BY TRANSMITTER

DATA OUTPUT BY RECEIVER

12 89

MSB LSB

CLOCK OPERATION

The eight byte clock register (see Table 3) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal form at. Seconds, Minutes, and Hours are contained within the first three registers. Bits D6 and D7 of clock register 2 (Hours Register) contain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a ’1’ will cause CB to toggle, either from ’0’ to ’1’ or from ’1’ to ’0’ at the turn of the century (depending upon its initial state). If CEB is set to a ’0’, CB will not toggle. Bits D0 through D2 of register 3 contain the Day (day of week). Registers 4, 5 and 6 contain the Date (day of month), Month and Years. The final register is the Control Register (this is described in the Clock Calibration section). Bit D7 of register 0 contains the STOP Bit (ST). Setting this bit to a ’1’ will cause the oscillator

CHANGE OF

DATA ALLOWED

STOP

CONDITION

AI00587

CLOCK PULSE FOR

ACKNOWLEDGEMENT

AI00601

to stop. If the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a ’0’ the oscillator restarts within one second.

The seven Clock Registers may be read one byte at a time, or in a sequential block. The Control Register (Address location 7) may be accessed independently. Provision has been made to assure that a clock update does not occur while any of the seven clock addresses are being read. If a clock address is being read, an update of the clock registers will be delayed by 250ms to allow the read to be completed before the update occurs. This will prevent a tran s it ion of dat a d ur ing t he re ad .

Note: This 250ms delay affects only the clock register update and does not alter the actual clock time.

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Figure 8. Bus Timing Requirements Sequence

SDA

M41T00

tHD:STAtBUF

SCL

Note: P = STOP and S = START

tHIGH

tLOW

Figure 9. Slave Address Location

R/W

START A

SLAVE ADDRESS

MSB

0100011

LSB

AI00602

CLOCK CALIBRATION

The M41T00 is driven by a quartz controlled oscillator with a nominal frequency of 32,768Hz. The devices are tested not to exceed 35ppm (parts per

million) oscillator frequency error at 25°C , which equates to about ±1.53 m inutes per month. With the calibration bits properly set, the accuracy of each M41T00 im proves to better than +2/–1 ppm at 25°C.

The oscillation rate of any crystal changes with temperature (see Figure 14). Most clock chips

tHD:STA

tSU:DAT

tHD:DAT

tSU:STOtSU:STA

AI00589

compensate for crystal frequency and temperature shift error with cumbersome trim capacitors. The M41T00 design, however, employs periodic counter correction. The calibration c ircuit adds or subtracts counts from the o scillator divider circuit at the divide by 256 stage, as shown in Figure 13. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five bit Calibration byte found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down.

The Calibration byte occupies the five lower order bits (D4-D0) in the Control register (Addr 7). This byte can be set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64minute cycle. The first 62 m inutes i n t he c ycle m ay , onc e per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, t he first 12 will be affected, and so on.

Therefore, each cal ibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of adjustment per calibration step in the cal ibration registe r. Ass um ing that the oscillator is in fact running at exactly 32,768Hz, each of the 31 in crements in the Calibration b yte would represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –2.75 minutes per month.

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M41T00

Figure 10. Wri t e Mode Sequence

BUS ACTIVITY: MASTER

BUS ACTIVITY:

START

SLAVE

ADDRESS

Figure 11. Read Mode Sequence

BUS ACTIVITY: MASTER

SDA LINE

BUS ACTIVITY:

START

SLAVE

ADDRESS

R/W

WORD

ADDRESS (n)

ACK

R/W

WORD

ADDRESS (n)

ACK

DATA n DATA n+1 DATA n+X

ACK

START

ACK

SLAVE

ADDRESS

ACK

R/W

DATA n DATA n+1

ACK

STOP

PSDA LINE

ACK

AI00591

ACK

DATA n+X

Figure 12. Alternate Read Mode Sequence

BUS ACTIVITY: MASTER

BUS ACTIVITY:

START

SLAVE

ADDRESS

R/W

DATA n DATA n+1 DATA n+X

ACK

STOP

NO ACK

ACK

AI00899

STOP

PSDA LINE

ACK

NO ACK

AI00895

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Figure 13. Cloc k C al ib rat i on

NORMAL

POSITIVE CALIBRATION

NEGATIVE CALIBRATION

M41T00

AI00594B

Two methods are available for ascertaining how much calibration a given M41T00 may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. All the designer has to do is provide a simple utility that accessed the Calibration byte.

The second approach is better suit ed to a manufacturing environment, and involves the use of some test equipment. When the F requency Test (FT) bit, the seventh-most significant bit in the Control Register, is set to a '1', and the oscillator is running at 32,768Hz, the FT/OUT pin of the device will toggle at 512Hz. Any deviation from 512Hz indicates t he degre e and direc tion of o scillator frequency shift at the test temperature.

For example, a reading of 512.01024Hz woul d indicate a +20ppm oscillator frequency error, requir-

ing a –10(XX001010) to be loaded into the Calibration Byte for correction. Note that setting or changing the Calibration Byte does n ot affect the Frequency test output frequency.

OUTPUT DRIVER PIN

When the FT bit is not set, the FT/OUT pin becomes an output driver that reflects the contents of D7 of the control register. In other words, when D6 of location 7 is a zero and D7 of location 7 i s a zero and then the FT/OUT pin will be driven low.

Note: The FT/OUT pin is open drain which requires an external pull-up resistor.

POWER-ON DEFAULTS

Upon initial application of power to the device, the FT bit will be set to a '0' and the OUT bit will be set to a '1'. All other Register bits will initially power-on in a random state.

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M41T00

Figure 14. Crystal Accuracy Across Temp eratur e

Frequency (ppm)

–20

–40

–60

–80

∆F

–100

–120

–140

–160

0 10203040506070

Temperature °C

= -0.038 (T - T

ppm

T0 = 25 °C

)2 ± 10%

80–10–20–30–40

AI00999

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M41T00

Table 11. Ordering Information Scheme

Example: M41T00 M 6 TR

Device Type

M41T

Package

M = SO8 150mil Width

Temperature Range

6 = –40 to 85°C

Shipping Method for SOIC

blank = Tubes TR = Tape & Reel

For a list of available options (Speed, Pac kage, etc...) or for furthe r information on any aspect of this device, please contact the ST Sales Office nearest to you.

Table 12. Revision History

Date Revision Details

March 1999 First Issue 05/15/00 AC Characteristic conditions changed (Table 10)

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M41T00

Table 13. SO8 - 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data

Symb

Typ Min Max Typ Min Max

A 1.35 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.010

B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 3.80 4.00 0.150 0.157 e 1.27 – – 0.050 – –

H 5.80 6.20 0.228 0.244 h 0.25 0.5 0 0.010 0.020 L 0.40 0.9 0 0.016 0.035 α 0° 8° 0° 8° N8 8

CP 0.10 0.004

mm in ches

Figure 15. SO8 - 8 le ad Plastic S mall Outline, 1 50 mils body width, Package Outline

h x 45˚

LA1 α

SO-a

Drawing is not to scale.

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M41T00

Information furnishe d is bel i eved to be accurate and reliable. However, STMicroelectroni cs assumes no responsibility for t he consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implic ation or oth erwise unde r any patent or patent rights of STMi croelectronics. Speci fications me ntioned in th i s publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as crit i cal component s i n l i f e support devices or systems wi thout expre ss written appr oval of STMicroelectronics.

The ST log o i s registered trademark of STM i croelectronics

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