Datasheet IXDN409SI, IXDN409CI, IXDD409YI, IXDD409PI, IXDD409CI Datasheet (IXYS)

Features

• Built using the advantages and compatibility
of CMOS and IXYS HDMOSTM processes.

• Latch Up Protected

• High Peak Output Current: 9A Peak

• Operates from 4.5V to 25V

• Ability to Disable Output under Faults

• High Capacitive Load
Drive Capability: 2500pF in <15ns

• Matched Rise And Fall Times

• Low Propagation Delay Time

• Low Output Impedance

• Low Supply Current

Applications

• Driving MOSFETs and IGBTs

• Motor Controls

• Line Drivers

• Pulse Generators

• Local Power ON/OFF Switch

• Switch Mode Power Supplies (SMPS)

• DC to DC Converters

• Pulse Transformer Driver

• Limiting di/dt under Short Circuit

• Class D Switching Amplifiers

First Release

Copyright © IXYS CORPORATION 2002 Patent Pending

General Description

The IXDD409/IXDI409/IXDN409 are high speed high current
gate drivers specifically designed to drive the largest
MOSFETs and IGBTs to their minimum switching time and
maximum practical frequency limits. The IXDD409/IXDI409/
IXDN409 can source and sink 9A of peak current while
producing voltage rise and fall times of less than 30ns. The
input of the drivers are compatible with TTL or CMOS and are
fully immune to latch up over the entire operating range.
Designed with small internal delays, cross conduction/
current shoot-through is virtually eliminated in the IXDD409/
IXDI409/IXDN409. Their features and wide safety margin in
operating voltage and power make the drivers unmatched in
performance and value.

The IXDD409 incorporates a unique ability to disable the
output under fault conditions. When a logical low is forced
into the Enable input, both final output stage MOSFETs
(NMOS and PMOS) are turned off. As a result, the output of
the IXDD409 enters a tristate mode and achieves a Soft Turn­Off of the MOSFET/IGBT when a short circuit is detected.
This helps prevent damage that could occur to the MOSFET/
IGBT if it were to be switched off abruptly due to a dv/dt over­voltage transient.

The IXDN409 is configured as a non-inverting gate driver, and
the IXDI409 is an inverting gate driver.

The IXDD409/IXDI409/IXDN409 are available in the standard 8­pin P-DIP (PI), SOP-8 (SI), 5-pin TO-220 (CI) and in the TO-263
(YI) surface-mount packages.

Figure 1A - IXDD409 Functional Diagram

IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI
IXDN409PI / 409SI / 409YI / 409CI
9 Amp Low-Side Ultrafast MOSFET Driver

Figure 1B - IXDN409 Functional Diagram

Figure 1C - IXDI409 Functional Diagram

Part Number Package Type Temp. Range Configuration

IXDD409PI 8-Pin PDIP
IXDD409SI 8-Pin SOIC
IXDD409YI 5-Pin TO-263
IXDD409CI 5-Pin TO-220

-40°C to +85°C

Non Inverting
With Enable Line

IXDI409PI 8-Pin PDIP
IXDI409SI 8-Pin SOIC
IXDI409YI 5-Pin TO-263
IXDI409CI 5-Pin TO-220

-40°C to +85°C

Inverting

IXDN409PI 8-Pin PDIP
IXDN409SI 8-Pin SOIC
IXDN409YI 5-Pin TO-263
IXDN409CI 5-Pin TO-220

-40°C to +85°C

Non Inverting

Ordering Information

2

IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI
IXDN409PI / 409SI / 409YI / 409CI

Unless otherwise noted, TA = 25 oC, 4.5V ≤ V

CC

≤ 25V .

All voltage measurements with respect to GND. IXDD409 configured as described in Test Conditions.

Electrical Characteristics

Symbol Parameter Test Conditions Min Typ Max Units

V

IH

High input voltage 3.5 V
VIL Low input voltage 0.8 V
VIN Input voltage range -5 V

CC

+ 0.3 V

IIN Input current

0V ≤ V

IN

≤ V

CC

-10 10

µA

VOH High output voltage V

CC

- 0.025 V
VOL Low output voltage 0.025 V
ROH Output resistance

@ Output high

I

OUT

= 10mA, V

CC

= 18V

0.8 1.5

Ω

ROL Output resistance

@ Output Low

I

OUT

= 10mA, V

CC

= 18V 0.8 1.5

Ω

I

PEAK

Peak output current VCC is 18V

9 A

I

DC

Continuous output

current

Limited by package power
dissipation

2 A

V

EN

Enable voltage range IXDD409 Only - .3 Vcc + 0.3 V

V

ENH

High En Input Voltage IXDD409 Only 2/3 Vcc V

V

ENL

Low En Input Voltage IXDD409 Only 1/3 Vcc V
tR Rise time CL=2500pF Vcc=18V 8 10 15 ns
tF Fall time CL=2500pF Vcc=18V 8 10 15 ns
t

ONDLY

On-time propagation

delay

CL=2500pF Vcc=18V 33 36 40 ns

t

OFFDLY

Off-time propagation

delay

CL=2500pF Vcc=18V 31 33 36 ns

t

ENOH

Enable to output high

delay time

IXDD409 Only, Vcc=18V 52 ns

t

DOLD

Disable to output low

Disable delay time

IXDD409 Only, Vcc=18V 30 ns

VCC Power supply voltage 4.5 18 25 V
ICC Power supply current V

IN

= 3.5V

V

IN

= 0V

V

IN

= + VCC

1 0 3

10
10

mA

µA
µA

Absolute Maximum Ratings (Note 1)

Parameter Value

Supply Voltage 25 V
All Other Pins -0.3 V to VCC + 0.3 V

Power Dissipation, T

AMBIENT

≤25 oC
8 Pin PDIP (PI) 975mW
8 Pin SOIC (SI) 1055mW
TO220 (CI), TO263 (YI) 17W

Derating Factors (to Ambient)

8 Pin PDIP (PI)

7.6mW/oC

8 Pin SOIC (SI)

8.2mW/oC

TO220 (CI), TO263 (YI)

0.14W/oC

Storage Temperature

-65 oC to 150 oC

Lead Temperature (10 sec)

300 oC

Operating Ratings

Parameter Value

Maximum Junction Temperature

150 oC

Operating Temperature Range

-40 oC to 85 oC
Thermal Impedance (Junction To Case)
TO220 (CI), TO263 (YI) (θJC)

0.95 oC/W

Specifications Subject To Change Without Notice

3

IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI
IXDN409PI / 409SI / 409YI / 409CI

Pin Description

SYMBOL FUNCTION DESCRIPTION

VCC Supply Voltage

Positive power-s upply voltage inp ut. This pin provides power to the
entire chip. The range for this voltage is from 4.5V to 25V.

IN Input Input signal-TTL or CMOS compatible.

EN * Enable

The system ena ble pin. T his pin, when dri ven lo w, disabl es the c hip,
forcing high impedance state to the output (IXDD409 Only).

OUT Output

Driver Output. For application purposes, this pin is connected,
through a resistor, to Gate of a MOSFET/IGBT.

GND Ground

The system ground pin. Internally connec ted to all circuitry, this pin
provides ground reference for the entire chip. This pin should be
connected to a low noise analog ground plane for optimum
performance.

Figure 2 - Characteristics Test Diagram

* This pin is used only on the IXDD409, and is N/C on the IXDI409 and IXDN409.
Note 1: Operating the device beyond parameters with listed “absolute maximum ratings” may cause permanent

damage to the device. Typical values indicate conditions for which the device is intended to be functional, but do not
guarantee specific performance limits. The guaranteed specifications apply only for the test conditions listed.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD procedures
when handling and assembling this component.

V

IN

8 PIN DIP (PI)

SO8 (SI)

TO220 (CI)
TO263 (YI)

Vcc
OUT
GND
IN
EN *

1
2
3
4
5

Pin Configurations

VCC

IN

EN *

GND

VCC

OUT

GND

OUT

1

2

3

4

8

7

6

5

4

IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI
IXDN409PI / 409SI / 409YI / 409CI

Typical Performance Characteristics

Fig. 3

Fig. 4

Fig. 5

Fig. 6

Fig. 7

Fig. 8

Rise Times vs . Supply Voltage

0

5

10

15

20

25

30

35

40

8 9 10 11 12 13 14 15 16 17 18

Supply Voltage (V)

Rise Time (ns)

2950 pF

5860 pF

8900 pF

11900 pF

1500 pF

Rise Time v s. Load Capacitance

5

10

15

20

25

30

35

1.35 2.7 5.4 8.1 10.8
Load Capacitance

Rise time (ns)

8V

10V
12V

14V
16V
18V

Fa ll Tim e s v s. S u pp ly Vo ltag e

0

5

10

15

20

25

30

8 9 10 11 12 13 14 15 16 17 18

Supply Voltage (V)

Fall Times (ns)

5860 pF

2950 pF

8900 pF

11900 pF

1500 pF

Fall Time vs. Load Cap acitance

5

7

9

11

13

15

17

19

21

23

25

1.35 2.7 5.4 8.1 10.8
Load Capacitance (nF)

Fall Time (ns)

14V
16V

18V

Rise And Fall Times vs. Temperature

CL =2500pF, Vcc=18V

0

2

4

6

8

10

12

-40-200 2540 6085

Tem peratur e

Rise time

Fal l tim e

M ax / M in In p u t v s. T e m pe ratu re

0

0.5

1

1.5

2

2.5

3

3.5

-40-200 25406085
Tem perature

Max / Min Input (V)

Minimum Input Low

Maximum Input High

5

IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI
IXDN409PI / 409SI / 409YI / 409CI

Fig. 9 Fig. 10

Fig. 11

Fig. 12

Fig. 13

Fig. 14

Supply Current vs. Load Capacitance

Vcc = 18V

0.1

1

10

100

1000

1000 10000

Load Capacitance (pF)

Supply Current (mA)

Supply Cu rrent vs. Load Capacitance

Vcc = 12 V

0.1

1

10

100

1000

1000 10000

Load Capacitance (pF)

Supply Current (mA)

10kHz

50kHz

100kHz

1M Hz

2M Hz

500kHz

Supply C urrent vs. Load Capacitance

Vcc = 8V

0.1

1

10

100

1000

1000 10000

Load Capacitance (pF)

Supply Current (mA)

10kHz

50kHz

100kH z

500kH z

1M Hz

2M Hz

Supply Current vs. Frequency

Vcc = 18V

0.1

1

10

100

1000

1101001000

Frequency (kHz)

Supply Current (mA

)

1350 pF

2700 pF

5400 pF

8100 pF

10800 pF

Supp ly Cu rrent vs. Frequ en cy

Vcc = 12 V

0.01

0.1

1

10

100

1000

1 10 100 1000 10000

Frequency (kHz)

Supply Current (mA)

1350 pF

2700 pF

5400 pF

8100 pF

10800 pF

Supply Current vs. Frequency

Vcc = 8V

0.01

0.1

1

10

100

1000

1 10 100 1000 10000

Frequency (kHz)

Supply Current (mA)

1350 pF

2700

p

F

5400 pF

8100 pF

10800 pF

6

IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI
IXDN409PI / 409SI / 409YI / 409CI

Fig. 15

Fig. 16

Fig. 17

Fig. 18

Fig. 19

Fig. 20

Propagation Delay v s. Supply Voltage

30

32

34

36

38

40

42

44

46

48

50

8 9 10 11 12 13 14 15 16 17 18

Supply Voltage (V)

Propagation Delay (ns)

Tondly (DD 409, DN 409)
Toff dly (DI409)

Toff dly(DD409, D N 409)
Tondly (DI409)

Propagation Delay v s. Input Voltage

30

32

34

36

38

40

42

44

46

48

50

3456789101112

Input Voltage (V)

Propagation Delay (ns)

Tondly (DD409, DN409)
To ffd ly (D I4 0 9)

Toffdly (DD409, DN409)
Tondly (DI409)

Propagation Delay T imes v s. Jun ction T em perature

0

5

10

15

20

25

30

35

40

45

-40-200 25406085
Temp erature (C)

Time (ns)

Tondly (DD409, DN409)
To ff d ly (D I4 0 9)

Toffdly (DD4 09, DN4 09 )
Tondly (DI409)

Qu iescent Supply Cu rrent vs. Jun ction Tem perature

Vcc=18v Vin=5v@ 1kHz

0

0.1

0.2

0.3

0.4

0.5

0.6

-40-20 025406085
Temperature (C)

Quiescent Supply Current (mA)

Vcc vs. P Channel Peak Output Current

CL = 10 nF

-14

-12

-10

-8

-6

-4

-2

0

5 7.5 10 12.5 15 17.5 20 22.5 25

Vcc (V )

P Channel Peak Output Current (A)

Vcc vs. N Channel Peak Output Current

CL=10 nF

0

2

4

6

8

10

12

14

16

18

20

5 7.5 10 12.5 15 17.5 20 22.5 25

Vcc (V )

N Channel Peak Output Current (A)

7

IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI
IXDN409PI / 409SI / 409YI / 409CI

Figure 25 - Typical Application Short Circuit di/dt Limit

Fig. 21

Fig. 22

Fig. 23

High S tate O u tp u t R es istanc e v s. S u pply V oltag e

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

5 7.5 10 12.5 15 17.5 20 22.5 25

Supply Voltage (V)

High State Output Resistance (Ohms)

Low State O utput R esistance vs. Supply Voltage

0

0.2

0.4

0.6

0.8

1

1.2

5 7.5 10 12.5 15 17.5 20 22.5 25

Supply Voltage (V)

Low State Output Resistance (Ohms)

Fig. 24

P Ch ann el Output Cu rrent vs. Tem perature

Vcc = 18V CL = 10 n F

8

8.2

8.4

8.6

8.8

9

9.2

9.4

9.6

9.8

10

-60 -40 -20 0 20 40 60 80 100

Tem perature (C)

P Channel Out

p

ut Current

(

A

)

N C han nel Peak O upu t Current vs. Tem perature

Vcc = 18V CL = 10 nF

10

10.5

11

11.5

12

12.5

13

13.5

14

14.5

15

-60 -40 -20 0 20 40 60 80 100

Tem perature (C)

N

Ch

anne

l

O

u

tp

u

t

C

urren

t

(A)

8

IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI
IXDN409PI / 409SI / 409YI / 409CI

Short Circuit di/dt Limit

A short circuit in a high-power MOSFET module such as the
VM0580-02F, (580A, 200V), as shown in Figure 25, can cause
the current through the module to flow in excess of 1500A for
10µs or more prior to self-destruction due to thermal runaway.
For this reason, some protection circuitry is needed to turn off
the MOSFET module. However, if the module is switched off
too fast, there is a danger of voltage transients occuring on the
drain due to Ldi/dt, (where L represents total inductance in
series with drain). If these voltage transients exceed the
MOSFET's voltage rating, this can cause an avalanche break­down.

The IXDD409 has the unique capability to softly switch off the
high-power MOSFET module, significantly reducing these
Ldi/dt transients.

Thus, the IXDD409 helps to prevent device destruction from
both dangers; over-current, and avalanche breakdown due to
di/dt induced over-voltage transients.

The IXDD409 is designed to not only provide ±9A under normal
conditions, but also to allow it's output to go into a high
impedance state. This permits the IXDD409 output to control
a separate weak pull-down circuit during detected overcurrent
shutdown conditions to limit and separately control d

VGS

/dt gate

turnoff. This circuit is shown in Figure 26.
Referring to Figure 26, the protection circuitry should include

a comparator, whose positive input is connected to the source
of the VM0580-02. A low pass filter should be added to the input
of the comparator to eliminate any glitches in voltage caused
by the inductance of the wire connecting the source resistor to

ground. (Those glitches might cause false triggering of the
comparator).

The comparator's output should be connected to a SRFF(Set
Reset Flip Flop). The flip-flop controls both the Enable signal,
and the low power MOSFET gate. Please note that CMOS 4000­series devices operate with a V

CC

range from 3 to 15 VDC, (with

18 VDC being the maximum allowable limit).
A low power MOSFET, such as the 2N7000, in series with a

resistor, will enable the VMO580-02F gate voltage to drop
gradually. The resistor should be chosen so that the RC time
constant will be 100us, where "C" is the Miller capacitance of
the VMO580-02F.

For resuming normal operation, a Reset signal is needed at
the SRFF's input to enable the IXDD409 again. This Reset can
be generated by connecting a One Shot circuit between the
IXDD409 Input signal and the SRFF restart input. The One Shot
will create a pulse on the rise of the IXDD409 input, and this
pulse will reset the SRFF outputs to normal operation.

When a short circuit occurs, the voltage drop across the low­value, current-sensing resistor, (Rs=0.005 Ohm), connected
between the MOSFET Source and ground, increases. This
triggers the comparator at a preset level. The SRFF drives a low
input into the Enable pin disabling the IXDD409 output. The
SRFF also turns on the low power MOSFET, (2N7000).

In this way, the high-power MOSFET module is softly turned off
by the IXDD409, preventing its destruction.

APPLICATIONS INFORMATION

Figure 26 - Application Test Diagram

10uH

Ld

0.1ohm

Rd

Rs

20nH

Ls

1ohm

Rg

10kohm

R+

VMO58 0-02F

High_Power

5kohm

Rcomp

100pF

C+

+

-

V+
V-

Comp
LM339

1600ohm

Rsh

Ccomp

1pF

VCC
VCCA

IN
EN

GND
SUB

OUT

IXDD409

+

-

VIN

+

-

VCC

+

-

REF

+

-

VB

CD4001A

NOR2

1Mohm

Ros

NOT2

CD4049A

CD4011A

NAND

CD4049A

NOT1

CD4001A

NOR1

CD4049A

NOT3

Low_Power

2N7002/PLP

1pF

Cos

0

S

R

EN

Q

One Shot Circuit

SR Flip-Flop

9

IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI
IXDN409PI / 409SI / 409YI / 409CI

When designing a circuit to drive a high speed MOSFET
utilizing the IXDD409/IXDI409/IXDN409, it is very important to
keep certain design criteria in mind, in order to optimize
performance of the driver. Particular attention needs to be paid
to Supply Bypassing, Grounding, and minimizing the Output
Lead Inductance.

Say, for example, we are using the IXDD409 to charge a
5000pF capacitive load from 0 to 25 volts in 25ns…

Using the formula: I= ∆V C / ∆t, where ∆V=25V C=5000pF &
∆t=25ns we can determine that to charge 5000pF to 25 volts
in 25ns will take a constant current of 5A. (In reality, the charging
current won’t be constant, and will peak somewhere around
8A).

SUPPLY BYPASSING

In order for our design to turn the load on properly, the IXDD409
must be able to draw this 5A of current from the power supply
in the 25ns. This means that there must be very low impedance
between the driver and the power supply. The most common
method of achieving this low impedance is to bypass the
power supply at the driver with a capacitance value that is a
magnitude larger than the load capacitance. Usually, this
would be achieved by placing two different types of bypassing
capacitors, with complementary impedance curves, very close
to the driver itself. (These capacitors should be carefully
selected, low inductance, low resistance, high-pulse current­service capacitors). Lead lengths may radiate at high frequency
due to inductance, so care should be taken to keep the lengths
of the leads between these bypass capacitors and the IXDD409
to an absolute minimum.

GROUNDING

In order for the design to turn the load off properly, the IXDD409
must be able to drain this 5A of current into an adequate
grounding system. There are three paths for returning current
that need to be considered: Path #1 is between the IXDD409
and it’s load. Path #2 is between the IXDD409 and it’s power
supply. Path #3 is between the IXDD409 and whatever logic
is driving it. All three of these paths should be as low in
resistance and inductance as possible, and thus as short as
practical. In addition, every effort should be made to keep these
three ground paths distinctly separate. Otherwise, (for
instance), the returning ground current from the load may
develop a voltage that would have a detrimental effect on the
logic line driving the IXDD409.

OUTPUT LEAD INDUCTANCE

Of equal importance to Supply Bypassing and Grounding are
issues related to the Output Lead Inductance. Every effort
should be made to keep the leads between the driver and it’s
load as short and wide as possible. If the driver must be placed
farther than 2” from the load, then the output leads should be
treated as transmission lines. In this case, a twisted-pair
should be considered, and the return line of each twisted pair
should be placed as close as possible to the ground pin of the
driver, and connect directly to the ground terminal of the load.

Supply Bypassing and Grounding Practices,
Output Lead inductance

The enable (EN) input to the IXDD409 is a high voltage
CMOS logic level input where the EN input threshold is ½ V

CC

,
and may not be compatible with 5V CMOS or TTL input levels.
The IXDD409 EN input was intentionally designed for
enhanced noise immunity with the high voltage CMOS logic
levels. In a typical gate driver application, V

CC

=15V and the
EN input threshold at 7.5V, a 5V CMOS logical high input
applied to this typical IXDD409 application’s EN input will be
misinterpreted as a logical low, and may cause undesirable
or unexpected results. The note below is for optional
adaptation of TTL or 5V CMOS levels.

The circuit in Figure 27 alleviates this potential logic level
misinterpretation by translating a TTL or 5V CMOS logic input
to high voltage CMOS logic levels needed by the IXDD409 EN
input. From the figure, VCC is the gate driver power supply,
typically set between 8V to 20V, and VDD is the logic power
supply, typically between 3.3V to 5.5V. Resistors R1 and R2
form a voltage divider network so that the Q1 base is
positioned at the midpoint of the expected TTL logic transition
levels.

A TTL or 5V CMOS logic low, V

TTLLOW

=~<0.8V, input applied to
the Q1 emitter will drive it on. This causes the level translator
output, the Q1 collector output to settle to V

CESATQ1

+

V

TTLLOW

=<~2V, which is sufficiently low to be correctly
interpreted as a high voltage CMOS logic low (<1/3VCC=5V for
VCC =15V given in the IXDD409 data sheet.)

A TTL high, V

TTLHIGH

=>~2.4V, or a 5V CMOS high,

V

5VCMOSHIGH

=~>3.5V, applied to the EN input of the circuit in
Figure 27 will cause Q1 to be biased off. This results in Q1
collector being pulled up by R3 to VCC=15V, and provides a
high voltage CMOS logic high output. The high voltage CMOS
logical EN output applied to the IXDD409 EN input will enable
it, allowing the gate driver to fully function as an 8 Amp output
driver.

The total component cost of the circuit in Figure 27 is less
than $0.10 if purchased in quantities >1K pieces. It is
recommended that the physical placement of the level
translator circuit be placed close to the source of the TTL or
CMOS logic circuits to maximize noise rejection.

Figure 27 - TTL to High Voltage CMOS Level Translator

TTL to High Voltage CMOS Level Translation
(IXDD409 Only)

10K

R3

3.3K R2

Q1
2N3904

EN

Output

CC

(From G a te D river

Powe r Supply)

Inp ut)

TTL

CMOS

3.3K

R1

V

DD
(From Lo g ic
Powe r Supply)

or

High V olta

ge

(To IXDD409
EN Input)

10

IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI
IXDN409PI / 409SI / 409YI / 409CI

IXYS Semiconductor GmbH
Edisonstrasse15 ; D-68623; Lampertheim
Tel: [phone]; Fax: [phone]
e-mail: [e-mail]

IXYS Corporation
3540 Bassett St; Santa Clara, CA 95054
Tel: [phone]; Fax: [phone]
www.ixys.com
e-mail: [e-mail]

Directed Energy, Inc.
An IXYS Company
2401 Research Blvd. Ste. 108
Ft. Collins, CO 80526
Tel: [phone]; Fax: [phone]
www.directedenergy.com
e-mail: [e-mail]

Doc #9200-0252 R1

Package Information

NOTE: Mounting or solder tabs on all packages are connected to ground