Datasheet IXDD404PI Datasheet (IXYS)

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Page 1

IXDD404PI / 404SI / 404SI-16

4 Amp Dual Low-Side Ultrafast MOSFET Driver

Features

• Built using the advantages and compatibility of CMOS and IXYS HDMOSTM processes

• Latch-Up Protected

• High Peak Output Current: 4A Peak

• Wide Operating Range: 4.5V to 25V

• Ability to Disable Output under Faults

• High Capacitive Load Drive Capability: 1800pF in <15ns

• Matched Rise And Fall Times

• Low Propagation Delay Time

• Low Output Impedance

• Low Supply Current

• Two identical drivers in single chip

Applications

• Driving MOSFETs and IGBTs

• Limiting di/dt under Short Circuit

• Motor Controls

• Line Drivers

• Pulse Generators

• Local Power ON/OFF Switch

• Switch Mode Power Supplies (SMPS)

• DC to DC Converters

• Pulse Transformer Driver

• Class D Switching Amplifiers

General Description

The IXDD404 is comprised of two 4 Amp CMOS high speed MOSFET drivers. Each output can source and sink 4 A of peak current while producing voltage rise and fall times of less than 15ns to drive the latest IXYS MOSFETS & IGBT's. The input of the driver is compatible with TTL or CMOS and is fully immune to latch up over the entire operating range. Designed with small internal delays, cross conduction/current shootthrough is virtually eliminated in the IXDD404. Improved speed and drive capabilities are further enhanced by very low, matched rise and fall times.

Additionally, each driver in the IXDD404 incorporates a unique ability to disable the output under fault conditions. When a logical low is forced into the Enable input of a driver, both of it's final output stage MOSFETs (NMOS and PMOS) are turned off. As a result, the respective output of the IXDD404 enters a tristate mode and achieves a Soft Turn-Off of the MOSFET/ IGBT when a short circuit is detected. This helps prevent damage that could occur to the MOSFET/IGBT if it were to be switched off abruptly due to a dv/dt over-voltage transient.

The IXDD404 is available in the standard 8 pin P-DIP (PI), SOP-8 (SI) and SOP-16 (SI-16) packages.

Figure 1 - Functional Diagram

ENA

INB

ENB

GND

200k

Vcc

OUTA

OUTB

First Release

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IXDD404PI/404SI/404SI-16

Absolute Maximum Ratings (Note 1)

Parameter Value

Supply Voltage 25 V All Other Pins -0.3 V to VCC + 0.3 V

Junction Temperature Storage Temperature Lead Temperature (10 sec)

150 oC

-65 oC to 150 oC 300 oC

Operating Ratings

Parameter Value

Operating Temperature Range Thermal Impedance (To Ambient)

8 Pin PDIP (PI) ( 8 Pin SOIC (SI) ( 16 Pin SOIC (SI-16) (

)

-40 oC to 85 oC

120 oC/W 110 oC/W 110 oC/W

Electrical Characteristics

Unless otherwise noted, TA = 25 oC, 4.5V ≤ V All voltage measurements with respect to GND. IXDD404 configured as described in Test Conditions. All specifications are for one channel.

Symbol Parameter Test Conditions Min Typ Max Units

High input voltage 3.5 V VIL Low input voltage 0.8 V VIN Input voltage range -5 V IIN Input current

VOH High output voltage V VOL Low output voltage 0.025 V ROH Output resistance

@ Output high ROL Output resistance

@ Output Low I

Peak output current VCC is 18V

PEAK

Continuous output

current V

High En Input Voltage 2/3 Vcc V

ENH

Low En Input Voltage 1/3 Vcc V

ENL

Enable voltage range - 0.3 Vcc + 0.3 V

tR Rise time CL=1800pF Vcc=18V 11 12 15 ns tF Fall time CL=1800pF Vcc=18V 12 14 17 ns t

On-time propagation

ONDLY

delay t

Off-time propagation

OFFDLY

delay t

Enable to output high

ENOH

delay time t

Disable to output low

DOLD

Disable delay time VCC Power supply voltage 4.5 18 25 V

Power supply current V

REN Enable Pull-up Resistor 200

≤ 25V .

+ 0.3 V

0V ≤ V

≤

-10 10

- 0.025 V

= 10mA, V

OUT

= 18V

1.5 3

Ω

= 10mA, V

OUT

= 18V 1.5 3

Ω

4 A

1 A

CL=1800pF Vcc=18V 33 34 38 ns CL=1800pF Vcc=18V 28 30 35 ns 30 ns 30 ns

= 3.5V = 0V

= + VCC

1 0 3

10 10

kΩ

Page 3

Pin Configurations

IXDD404PI/404SI/404SI-16

SO8 (SI) 8 PIN DIP (PI)

IN A

GND

IN B

EN A

I X D

OUT A

4 0 4

EN B

VCC

OUT B

SO16 (SI-16)

Pin Description

SYMBOL FUNCTION DESCRIPTION

EN A A Channel Enable

IN A A Channel Input A Channel Input signal-TTL or CMOS compatible.

GND Ground

IN B B Channel Input B Channel Input signal-TTL or CMOS compatible.

OUT B B Channel Output

VCC Supply Voltage

OUT A A Channel Output

EN B B Channel Enable

Note 1: Operating the device beyond parameters with listed “absolute maximum ratings” may cause permanent damage to the device. Typical values indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. The guaranteed specifications apply only for the test conditions listed. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD procedures when handling and assembling this component.

The Channel A enable pin. This pin, when driven low, disables the A Channel, forcing a high impedance state to the A Channel Output.

The system ground pin. Internally connected to all circuitry, this pin provides ground reference for the entire chip. This pin should be connected to a low noise analog ground plane for optimum performance.

B Channel Driver output. For application purposes, this pin is connected, through a resistor, to Gate of a MOSFET/IGBT. Positive power-supply voltage input. This pin provides power to the entire chip. The range for this voltage is from 4.5V to 25V. A Channel Driver output. For application purposes, this pin is connected, through a resistor, to Gate of a MOSFET/IGBT. The Channel B enable pin. This pin, when driven low, disables the B Channel, forcing a high impedance state to the B Channel Output.

Figure 2 - Characteristics Test Diagram

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)

IXDD404PI/404SI/404SI-16

Typical Performance Characteristics

Fig. 3

Rise Time (ns)

81012141618

Rise Time vs. Supply Voltage

CL=4700 pF

1800 pF

200 pF

Supply Voltage (V)

Fig. 5

Rise And Fall Times vs. Temperature

=18V VCC=18V

Fig. 4

Fall Time (ns)

81012141618

Fall Time vs. Supply Voltage

CL=4700 pF

1800 pF

200 pF

Supply Voltage (V)

Fig. 6

Rise Time vs. Load Cap acitance

10V

Time (ns)

-40-200 20406080100120

Temperature (°C

Fig. 7

100

Fall Time (ns)

0k 2k 4k 6k 8k 10k

F a ll T ime v s . L o a d Cap acitan c e

14V

16V

Load Capacitance (pF)

10V

12V

18V

Rise Time (ns)

0k 2k 4k 6k 8k 10k

14V

Load Capa citance (pF)

Fig. 8

3.2

3.0

2.8

2.6

2.4

2.2

Max / Min Input (V)

2.0

1.8

1.6

-60 -40 -20 0 20 40 60 80 100

Max / Min Input vs. Temperature

=18V CL=1nF

Minimum Input High

Maximum Input Low

Temperature (oC)

12V

18V

16V

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IXDD404PI/404SI/404SI-16

(

Fig. 9

100

Supply Current vs. Load Capacitance

Vcc=18V

2 MHz

1 MHz

500 KHz

Supply Current (mA)

0.1k 1.0k 10.0k

Load Capa citance (pF)

Fig. 11

100

Supply Current vs. Load Capacitance

Vcc=12V

100 kHz

50 kHz 10 kHz

Fig. 10

100

Supply Current vs. Frequency

Vcc=18V

CL= 1800 pF

200 pF

urren y

upp

0.1

0.01 1 10 100 1000

Frequency (kHz)

Fig. 12

100

Supply Current vs. Frequency

Vcc=12V

CL= 1800 pF

1000 pF

1 MHz

2 MHz

500 KHz

Supply Current (mA)

0.1k 1.0k 10.0k

100 kHz

50 kHz

10 kHz

Load Capa citance (pF)

Fig. 13

100

Supply Current (mA)

0.1k 1.0k 10.0k

Supply Current vs. Load Capacitance

Vcc=8V

1 MHz

2 MHz

10 kHz

500 KHz

100 kHz

50 kHz

Load Capa citance (pF)

urren y

upp

0.1

0.01 1 10 100 1000

Frequency (kHz)

Fig. 14

100

Supply Current vs. Frequency

Vcc=8V

CL= 1800 pF

urren y

upp

0.1

0.01 1 10 100 1000

Frequency (kHz)

1000 pF

200 pF

1000 pF

200 pF

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(

)

IXDD404PI/404SI/404SI-16

Propagation Delay vs. Supply Voltage

=1800pF VIN=5V@1kHz

Propagation Delay (ns)

8 1012141618

Fig. 17

Time (ns)

-40-200 20406080100120

Supply Voltage (V)

Propagation Delay Times vs. Temperature

=1800pF VCC=18V

Temperature

ONDLY

OFFDLY

ONDLY

OFFDLY

Fig. 16Fig. 15

Propagation Delay vs. Input Voltage

=1800pF VCC=15V

ONDLY

OFFDLY

Propagation Delay (ns)

024681012

Input Voltage (V)

Fig. 18

0.26

0.24

0.22

0.20

0.18

0.16

Quiescent Supply Current vs. Temperature

=18V VIN=5V@1kHz CL=1000pF

Quiescent Vcc Input Current (mA)

0.14

-40-200 20406080

Temperature (oC)

Fig. 19

P Channel Output Current Vs. Temperature

=18V, CL=1000pF

P Channel Output Current (A)

-40-200 20406080100

Temperature (oC)

Fig. 20

N Channel Output Current Vs. Temperature

=18V, CL=1000pF

N Channel Output Current (A)

-40-200 20406080100

Temperature (oC)

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IXDD404PI/404SI/404SI-16

Fig. 21

Enable Threshold (V)

Enable Threshold vs. Supply Voltage

8 101214161820222426

Supply Voltage (V)

Fig. 23

Lo w-Sta te Output Re s istance

Vs. Supply Voltage

3.0

2.0

Fig. 22

High State Output Resistance

vs. Supply Voltage

High State Output Resistance (Ohm)

10 15 20 25

Supply Voltage (V)

Fig. 24

-2

Vcc vs. P Channel Output Current

Fig. 25

1.0

Low-State Output Resistance (Ohms)

0.0 8

10 15 20 25

Supply Voltage (V)

VCC vs. N Channel Output Current

N Channel Output Current (A)

-4

-6

P Channel Output Current (A)

-8 8

10 15 20 25 30

Vcc

Figure 26 - Typical Application Short Circuit di/dt Limit

10 15 20 25 30

Vcc

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APPLICATIONS INFORMATION

Short Circuit di/dt Limit

IXDD404PI/404SI/404SI-16

A short circuit in a high-power MOSFET such as the IXFN100N20, (20A, 1000V), as shown in Figure 26, can cause the current through the module to flow in excess of 60A for 10µs or more prior to self-destruction due to thermal runaway. For this reason, some protection circuitry is needed to turn off the MOSFET module. However, if the module is switched off too fast, there is a danger of voltage transients occuring on the drain due to Ldi/dt, (where L represents total inductance in series with drain). If these voltage transients exceed the MOSFET's voltage rating, this can cause an avalanche breakdown.

The IXDD404 has the unique capability to softly switch off the high-power MOSFET module, significantly reducing these Ldi/dt transients.

Thus, the IXDD404 helps to prevent device destruction from both dangers; over-current, and avalanche breakdown due to di/dt induced over-voltage transients.

The IXDD404 is designed to not only provide ±4A per output under normal conditions, but also to allow it's outputs to go into a high impedance state. This permits the IXDD404 output to control a separate weak pull-down circuit during detected overcurrent shutdown conditions to limit and separately control d

/dt gate turnoff. This circuit is shown in Figure 27.

VGS

Referring to Figure 27, the protection circuitry should include a comparator, whose positive input is connected to the source of the IXFD100N20. A low pass filter should be added to the input of the comparator to eliminate any glitches in voltage

Figure 27 - Application Test Diagram

VCC

VIN

NOT2

CD4049A

One Shot Circuit

NOT1

CD4049A

Ros

1Mohm

NAND

CD4011A

Cos 1pF

caused by the inductance of the wire connecting the source resistor to ground. (Those glitches might cause false triggering of the comparator).

The comparator's output should be connected to a SRFF( Reset Flip Flop). The flip-flop controls both the Enable signal, and the low power MOSFET gate. Please note that CMOS 4000series devices operate with a VCC range from 3 to 15 VDC, (with 18 VDC being the maximum allowable limit).

A low power MOSFET, such as the 2N7000, in series with a resistor, will enable the IXFN100N20 gate voltage to drop gradually. The resistor should be chosen so that the RC time constant will be 100us, where "C" is the Miller capacitance of the IXFN100N20.

For resuming normal operation, a Reset signal is needed at the SRFF's input to enable the IXDD404 again. This Reset can be generated by connecting a One Shot circuit between the IXDD408 Input signal and the SRFF restart input. The One Shot will create a pulse on the rise of the IXDD404 input, and this pulse will reset the SRFF outputs to normal operation.

When a short circuit occurs, the voltage drop across the lowvalue, current-sensing resistor, (Rs=0.005 Ohm), connected between the MOSFET Source and ground, increases. This triggers the comparator at a preset level. The SRFF drives a low input into the Enable pin disabling the IXDD404 output. The SRFF also turns on the low power MOSFET, (2N7000).

In this way, the high-power MOSFET module is softly turned off by the IXDD404, preventing its destruction.

0.1ohm

High_Power

IXFN100N20

Ls 20nH

10uH

IXDD404

VCC VCCA

IN EN

DGND SUB

OUT

Rcomp 5kohm

Ccomp

1pF

Rsh

1600ohm

Comp LM339

Low_Power 2N7002/PLP

1ohm

R+

10kohm

V+ V-

REF

C+

100pF

Set

NOT3

CD4049A

SR Flip-Flop

NOR1

CD4001A

NOR2

CD4001A

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IXDD404PI/404SI/404SI-16

Supply Bypassing and Grounding Practices, Output Lead inductance

When designing a circuit to drive a high speed MOSFET utilizing the IXDD404, it is very important to keep certain design criteria in mind, in order to optimize performance of the driver. Particular attention needs to be paid to Supply Bypassing, Grounding, and minimizing the Output Lead Inductance.

Say, for example, we are using the IXDD404 to charge a 2500pF capacitive load from 0 to 25 volts in 25ns.

Using the formula: I= ∆V C / ∆t, where ∆V=25V C=2500pF & ∆t=25ns we can determine that to charge 2500pF to 25 volts in 25ns will take a constant current of 2.5A. (In reality, the charging current won’t be constant, and will peak somewhere around 4A).

SUPPLY BYPASSING

In order for our design to turn the load on properly, the IXDD404 must be able to draw this 2.5A of current from the power supply in the 25ns. This means that there must be very low impedance between the driver and the power supply. The most common method of achieving this low impedance is to bypass the power supply at the driver with a capacitance value that is a magnitude larger than the load capacitance. Usually, this would be achieved by placing two different types of bypassing capacitors, with complementary impedance curves, very close to the driver itself. (These capacitors should be carefully selected, low inductance, low resistance, high-pulse current-service capacitors). Lead lengths may radiate at high frequency due to inductance, so care should be taken to keep the lengths of the leads between these bypass capacitors and the IXDD404 to an absolute minimum.

GROUNDING

In order for the design to turn the load off properly, the IXDD404 must be able to drain this 2.5A of current into an adequate grounding system. There are three paths for returning current that need to be considered: Path #1 is between the IXDD404 and it’s load. Path #2 is between the IXDD404 and it’s power supply. Path #3 is between the IXDD404 and whatever logic is driving it. All three of these paths should be as low in resistance and inductance as possible, and thus as short as practical. In addition, every effort should be made to keep these three ground paths distinctly separate. Otherwise, (for instance), the returning ground current from the load may develop a voltage that would have a detrimental effect on the logic line driving the IXDD404.

OUTPUT LEAD INDUCTANCE

Of equal importance to Supply Bypassing and Grounding are issues related to the Output Lead Inductance. Every effort should be made to keep the leads between the driver and it’s load as short and wide as possible. If the driver must be placed farther than 2” from the load, then the output leads should be treated as transmission lines. In this case, a twisted-pair should be considered, and the return line of each twisted pair should be placed as close as possible to

driver, and connect directly to the ground terminal of the load.

the ground pin of the

TTL to High Voltage CMOS Level Translation

The enable (EN) input to the IXDD404 is a high voltage CMOS logic level input where the EN input threshold is ½

, and may not be compatible with 5V CMOS or TTL input

levels. The IXDD404 EN input was intentionally designed for enhanced noise immunity with the high voltage CMOS logic levels. In a typical gate driver application, V and the EN input threshold at 7.5V, a 5V CMOS logical high input applied to this typical IXDD404 application’s EN input will be misinterpreted as a logical low, and may cause undesirable or unexpected results. The note below is for optional adaptation of TTL or 5V CMOS levels.

The circuit in Figure 28 alleviates this potential logic level misinterpretation by translating a TTL or 5V CMOS logic input to high voltage CMOS logic levels needed by the IXDD404 EN input. From the figure, VCC is the gate driver power supply, typically set between 8V to 20V, and VDD is the logic power supply, typically between 3.3V to 5.5V. Resistors R1 and R2 form a voltage divider network so that the Q1 base is positioned at the midpoint of the expected TTL logic transition levels.

A TTL or 5V CMOS logic low, V to the Q1 emitter will drive it on. This causes the level

=~<0.8V, input applied

TTLLOW

translator output, the Q1 collector output to settle to V + V interpreted as a high voltage CMOS logic low (<1/3VCC=5V

=<~2V, which is sufficiently low to be correctly

TTLLOW

for VCC =15V given in the IXDD404 data sheet.) A TTL high, V

5VCMOSHIGH

Figure 28 will cause Q1 to be biased off. This results in Q1

=~>3.5V, applied to the EN input of the circuit in

=>~2.4V, or a 5V CMOS high,

TTLHIGH

collector being pulled up by R3 to VCC=15V, and provides a high voltage CMOS logic high output. The high voltage CMOS logical EN output applied to the IXDD404 EN input will enable it, allowing the gate driver to fully function as a ±4 Amp output driver.

The total component cost of the circuit in Figure 28 is less than $0.10 if purchased in quantities >1K pieces. It is recommended that the physical placement of the level translator circuit be placed close to the source of the TTL or CMOS logic circuits to maximize noise rejection.

Figure 28 - TTL to High Voltage CMOS Level Translator

(From Gate Driver

Power Supply)

DD (From Logic Power Supply)

TTL

Input)

3.3K

3.3K R2

10K

Q1 2N3904

=15V

CESATQ1

High Voltage

CMOS

Output

(To IXDD404 EN Input)

Page 10

IXDD404PI/404SI/404SI-16

Ordering Information

Part Number Package Type Tem p. Range

IXDD404PI 8-Pin PDIP IXDD404SI 8-Pin SOIC IXDD404SI-16 16-Pin SOIC

-40°C to +85°C

NOTE: Mounting or solder tabs on all

packages are connected to ground

IXYS Corporation 3540 Bassett St; Santa Clara, CA 95054 Tel: 408-982-0700; Fax: 408-496-0670 e-mail: [email protected]

IXYS Semiconductor GmbH Edisonstrasse15 ; D-68623; Lampertheim Tel: +49-6206-503-0; Fax: +49-6206-503627 e-mail: [email protected]

Directed Energy, Inc. An IXYS Company 2401 Research Blvd. Ste. 108, Ft. Collins, CO 80526 Tel: 970-493-1901; Fax: 970-493-1903 e-mail: [email protected]

Doc #9200-0226 R4