Datasheet HSDL-7000 Datasheet (HP)

IR 3/16 Encode/Decode IC

Technical Data

H

HSDL-7000

Features

• Compliant with IrDA
Physical Layer Specs

• Interfaces with IrDA
Compliant HSDL-1000 IR
Transceiver

• 1 Micron CMOS Gate Array

• Used in Conjunction with
Standard 16550 UART

• Pin Compatible with
PLX-1000

Applications
Interfaces with

HSDL-1000 to perform:

• Serial Half-Duplex Data
Transfer Between:

Notebook Computers
Subnotebooks
Desktops PCs
PDAs
Printers
Other Peripheral Devices

• Telecom Applications in:

Modems
Fax Machines
Pagers
Phones

• Industrial Applications in:

Data Collection Devices

• Medical Applications in:

Patient and Pharmaceutical

Data Collection

Description

The HSDL-7000 performs the
modulation/demodulation
function used to both encode and
decode the electrical pulses from
the IR transceiver. These pulses
are then sent to a standard UART
which has a BAUDOUT signal
available externally. This signal is
16 times the selected baud rate.
In applications where the
16XCLK is not available, an
external means of generating the
16XCLK must be designed.

The HSDL-7000 is comprised of
two state machines – the serial IR
encode and the serial IR decode
blocks. Each of these blocks
derives their timing from the
16XCLK input signal from the
UART. The Encode block is
driven by the negative edge
triggered TXD signal from the
UART. This initiates the modula­tion state machine resulting in
the 3/16 modulated IR_TXD
signal which drives the IR trans­ceiver module, HSDL-1000. The
IR Decode block is driven by the
negative edge triggered IR_RCV
signal from the HSDL-1000. After
this signal is demodulated and
stretched, it drives the RCV signal
to the UART.

Schematic

HSDL-7000

TXD IR_TXD

RCV IR_RCV

NRST

IR ENCODE

IR DECODE

Pin Out

16XCLK

TXD

RCV

GND

1

2

HP 7000

YYWW

3

4

8

7

6

5

V

CC

IR_TXD

IR_RCV

NRST

5964-9278E

4-43

Pin Description

16XCLK - Positive edge

triggered input clock that is set to
16 times the data transmission
baud rate. The encode and
decode schemes require this
signal. The signal is usually tied
to a UART’s BAUDOUT signal.

TXD - Negative edge triggered
input signal; usually tied to a
UART’s SOUT signal (serial data
to be transmitted).

Package Dimensions

6.65 (0.26)
MAX.

8

RCV - Output signal which is
usually tied to a UART’s SIN
signal (received serial data).

GND - Chip ground.

NRST - Active low signal used to

reset the decode state machine.
This signal can be tied to POR
(Power on reset) or VCC. This
signal can also be used to disable
any data reception.

1.05

(0.041)

5

IR_RCV - A 3/16th pulse width
input signal from the HSDL-1000.
The signal is a demodulated
(pulse stretched) to generate the
RCV output signal.

IR_TXD - This signal is the
modulated 3/16ths TXD signal
which is input to the HSDL-1000.

VCC - Power.

0.10

(0.004)

SCALE 5

1

1.55

(0.06)

0.40 + 0.10/-0.00

(0.016 + 0.004/-0.000)

NOTE: DIMENSIONS IN MILLIMETERS (INCHES).

1.27

(0.05)

4

1.42

(0.056)

MAX.

0.15 + 0.10/-0.00

(0.006 + 0.004/-0.00)

SEE DETAIL A

0.6 ± 0.2

(0.024 ± 0.008)

DETAIL A, SCALE 20

5.60 (0.22)

7.7 ± 0.3

(0.30 ± 0.012)

4-44

Encoding Scheme

16 CLOCK CYCLES

16 X CLOCK

TXD

IRTXD

7 cs

3 cs

The encoder sends a pulse for
every space or “0” that is sent on
the TXD line. On a high to low
transition of the TXD line, the
generation of the pulse is delayed

Decoding Scheme

16 CLOCK CYCLES

16 X CLOCK

IR_RXD

3 cs

for 7 clock cycles of the 16XCLK
before the pulse is set high for 3
clock cycles (or 3/16th of a bit
time) and then subsequently
pulled low.

RXD

A high to low transition of the
IR_RXD line from the HSDL-1000
signifies a 3/16th pulse. This
pulse is stretched to accommo­date 1 bit time (16 clock cycles).
Every pulse that is received is

translated into a “0” or space on
the RXD line equal to 1 bit time.

Note: The stretched pulse must
be at least 3/4 of a bit time in
duration to be correctly
interpreted by a UART.

4-45

Absolute Maximum Ratings

Parameter Symbol Min. Max. Units Conditions

Storage Temperature T
Operating Temperature T
Output Current I
Power Dissipation P
Input/Output Voltage VI/V
Power Supply Voltage V

S

A

O

MAX

O

CC

Switching Specifications

(VCC = 5 Volts ± 10%, TA= -40 to +85°C)

Parameter Symbol Min. Typ. Max. Units Conditions

Toggle Frequency f
Propagation Delay Time t

Output Fall Time t
Output Rise Time t

Note: f

represents the maximum internal D-Type Flip Flop toggle rate

tog

tog

pd

f
r

-65 +150 °C

-40 +85 °C

10 mA

0.22 W

-0.5 VCC + 0.5 V

-0.5 +6.5 V

120 Mhz

0.5 ns Internal Gate

1.0 ns Input Buffer

2.0 ns Output Buffer

1.42 ns Output Buffer (CL = 15 pF)

1.54 ns Output Buffer (CL = 15 pF)

Capacitance

(VCC = 0 Volts, TA= -40 to +85°C)

Parameter Symbol Min. Typ. Max. Units Conditions

Input Capacitance C
Output Capacitance C

IN

OUT

Output Fall Time 10 20 pF

10 20 pF f = 1 MHz - Unmeasured Pins
10 20 pF

Returned to 0 Volts

4-46

Recommended Operating Conditions

(TA= -40 to +85°C)

Parameter Symbol Min. Typ. Max. Units Conditions

Supply Voltage V
Input Voltage V
Ambient Temperature T
High Level Input Voltage V
Low Level Input Voltage V
Positive Trigger Voltage V
Negative Trigger Voltage V
Hysteresis Voltage V
Power Dissipation P
Input Rise Time t
Input Fall Time t
Max Clk Frequency (16XCLK) f
Minimum Pulse Width (IR_TXD)* t

*IrDA Parameters. The Max Clk Frequency represents the maximum clock frequency to drive the HSDL-7000’s internal state machine.
Under normal circumstances, this clock input should not exceed 16 * 115.2 Kbp/s or 1.8432 MHz. This product can operate at higher
clock rates, but the above is the recommended rate.

The Minimum Pulse Width represents the minimum pulse width of the encoded IR_TXD pulse (and the IR_RCV pulse). As per the IrDA
specifications, the minimum pulse width of the IR_TXD and IR_RCV pulses should be 3 * (1/1.8432 MHz) or 1.63 µs. The minimum
pulse width specified for the HSDL-7000 is 250 ns, which is within IrDA specification. Under normal circumstances, the pulse width
should not be less than 1.63 µs.

CC

I

A

IH

IL
P
N
H

DISS

ri
fa

16XCLK

mpx

2.7 5.0 5.5 V CMOS level

0.0 V

CC

V CMOS level

-40 +85 °C CMOS level

0.7 V

CC

0.0 0.3 V

V

CC

CC

V CMOS level
V CMOS level

1.61 4.00 V CMOS level

0.55 3.10 V CMOS level

0.50 2.00 V CMOS level

4.9 220 mW f
200 ns f
200 ns f

16XCLK
16XCLK
16XCLK

2 MHz

250 ns f

16XCLK

= 2 MHz
= 2 MHz
= 2 MHz

= 2 MHz

Application Circuits

HSDL-7000 Connection to UART

HSDL-1000 HSDL-7000

TXD

RCV

Note: At the time of this publication, Light Emitting Diodes (LEDs) that are contained in this product are regulated for eye safety in
Europe by the Commission for European Electrotechnical Standardization (CENELEC) EN60825-1. Please refer to Application Briefs
I-008, I-009, I-015 for more information.

IR_TXD

IR_RCV

TXD

RCV

16XCLK

UART 16550

SOUT

SIN

BAUDOUT

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