Datasheet GL852G-HHGXX, GL852G-MNGXX, GL852G-OHGXX, GL852G-PMGXX Datasheet (Genesys)

035/4

Genesys Logic, Inc.

GL852G

USB 2.0 MTT Hub Controller

Datasheet

Revision 1.26 May 16, 2012

GL852G Datasheet

Copyright

Ownership and Title

Genesys Logic, Inc. owns and retains of its right, title and interest in and to all materials provided herein. Genesys Logic, Inc. reserves all rights, including, but not limited to, all patent rights, trademarks, copyrights and any other propriety rights. No license is granted hereunder.

Disclaimer

All Materials are provided “as is”. Genesys Logic, Inc. makes no warranties, express, implied or otherwise, regarding their accuracy, merchantability, fitness for any particular purpose, and non-infringement of intellectual property. In no event shall Genesys Logic, Inc. be liable for any damages, including, without limitation, any direct, indirect, consequential, or incidental damages. The materials may contain errors or omissions. Genesys Logic, Inc. may make changes to the materials or to the products described herein at anytime without notice.

Genesys Logic, Inc.

12F., No. 205, Sec. 3, Beixin Rd., Xindian Dist. 231,

New Taipei City, Taiwan

Tel :

(886-2) 8913-1888

Fax : (886-2) 6629-6168

http ://www.genesyslogic.com

GL852G Datasheet

Revision History

Revision Date Description

1.00 05/26/2009 First formal release

1.01 06/18/2009 Add On-chip power regulator spec, Ch6.6, p.28

Update 3.3 pin description,p.14

1.02 09/01/2009

1.03 10/23/2009 Modify table 5.3 – port number configuration, p.23

1.04 11/04/2009 Update Table 6.6 – DC Supply Current, p.26

1.05 05/17/2010 Update Table 6.6 – DC Supply Current for GL852G-1x version, p.26

1.06 06/04/2010

1.07 12/27/2010

1.08 03/22/2011

1.09 04/21/2011 Add LQFN 46 package information, p8, 9, 13, 15~17, 26, 27, 37, 38

1.10 05/11/2011 Modify SSOP28 package dimension information, p.36

1.20 07/15/2011 Update Table 3.3 pin description, RREF I/O type, p.16

1.21 07/15/2011 Update Table 3.1, 3.2, 3.3, 3.4, 3.5 RREF I/O type, p.14~16

1.22 08/26/2011 Update Table-6.3 DC characteristics except USB signals (R

1.23 11/21/2011 Update Table 3.5 Pin Description, p.17

1.24 12/22/2011 Updated Table 6.2 Operating Ranges, p.28

1.25 01/03/2012 Updated Table 3.5 Pin Descriptions, p.17

1.26 05/16/2012 Modified CH8 Ordering Information, p.38

Update table-6.2 operating ranges, p.24 Update table-6.3 power dissipation, p.25 Update Ch8 order information, p.32

Update Table 5.3 – port number configuration for GL852G-1x version, p.24

Add SSOP28 package information, p.8, 9, 12~15, 26 Modify Ch2 features, p.9 Modify 5.2.5 EEPROM Setting, p.24 Modify 6.6 On-Chip Power Regulator, p.31

Modify SSOP28 pinout, p.12~15 Update table-6.3 DC characteristics except USB signals, p.27

), p.29

DN, RUP

GL852G Datasheet

Table of Contents

CHAPTER 1 GENERAL DESCRIPTION ........................................................................ 8

CHAPTER 2 FEATURES.................................................................................................... 9

CHAPTER 3 PIN ASSIGNMENT .................................................................................... 10

3.1 Pinouts ......................................................................................................................... 10

3.2 Pin List......................................................................................................................... 14

3.3 Pin Descriptions.......................................................................................................... 16

CHAPTER 4 BLOCK DIAGRAM ................................................................................... 19

CHAPTER 5 FUNCTION DESCRIPTION..................................................................... 20

5.1 General Description.................................................................................................... 20

5.1.1 USPORT Transceiver......................................................................................... 20

5.1.2 PLL (Phase Lock Loop) .....................................................................................20

5.1.3 FRTIMER ........................................................................................................... 20

5.1.4 μC ......................................................................................................................... 20

5.1.5 UTMI (USB 2.0 Transceiver Microcell Interface)........................................... 20

5.1.6 USPORT Logic ................................................................................................... 20

5.1.7 SIE (Serial Interface Engine)............................................................................. 20

5.1.8 Control/Status Register...................................................................................... 20

5.1.9 REPEATER ........................................................................................................ 21

5.1.10 TT (Transaction Translator) ........................................................................... 21

5.1.11 REPEATER/TT Routing Logic....................................................................... 21

5.1.12 DSPORT Logic ................................................................................................. 22

5.1.13 DSPORT Transceiver....................................................................................... 22

5.2 Configuration and I/O Settings ................................................................................. 23

5.2.1 RESET Setting .................................................................................................... 23

5.2.2 PGANG Setting................................................................................................... 24

5.2.3 SELF/BUS Power Setting .................................................................................. 25

5.2.4 LED Connections................................................................................................ 25

5.2.5 EEPROM Setting................................................................................................ 26

5.2.6 Power Switch Enable Polarity (Only Available for LQFP48/LQFN46

Package)........................................................................................................................26

5.2.7 Port Number Configuration (Only Available for LQFP48/LQFN46 Package)

....................................................................................................................................... 26

GL852G Datasheet

5.2.8 Non-removable Port Configuration (Only Available for LQFP48/LQFN46

Package)......................................................................................................................... 27

5.2.9 Reference Clock Configuration (Only Available for LQFP48/LQFN46

Package)........................................................................................................................27

CHAPTER 6 ELECTRICAL CHARACTERISTICS..................................................... 28

6.1 Maximum Ratings ...................................................................................................... 28

6.2 Operating Ranges ....................................................................................................... 28

6.3 DC Characteristics .....................................................................................................28

6.4 Power Consumption ................................................................................................... 30

6.5 AC Characteristics .....................................................................................................30

6.5.1 93C46 EEPROM IF............................................................................................ 31

6.5.2 24C02 EEPROM Interface ................................................................................ 32

6.6 On-Chip Power Regulator......................................................................................... 33

CHAPTER 7 PACKAGE DIMENSION .......................................................................... 34

CHAPTER 8 ORDERING INFORMATION .................................................................. 38

GL852G Datasheet

List of Figures

Figure 3.1 - GL852G 48 Pin LQFP Pinout Diagram .......................................................... 10

Figure 3.2 - GL852G 28 Pin QFN Pinout Diagram............................................................. 11

Figure 3.3 - GL852G SSOP 28 Pin Pinout Diagram ........................................................... 12

Figure 3.4 - GL852G LQFN 46 Pin Pinout Diagram .......................................................... 13

Figure 4.1 - GL852G Block Diagram (Multiple TT)........................................................... 19

Figure 5.1 - Operating in USB 1.1 Schemes......................................................................... 21

Figure 5.2 - Operating in USB 2.0 Schemes......................................................................... 22

Figure 5.3 - Power on Reset Diagram................................................................................... 23

Figure 5.4 - Power on Sequence of GL852G........................................................................ 23

Figure 5.5 - Timing of PGANG Strapping........................................................................... 24

Figure 5.6 - GANG Mode Setting ......................................................................................... 24

Figure 5.7 - SELF/BUS Power Setting ................................................................................. 25

Figure 5.8 - LED Connection ................................................................................................ 25

Figure 5.9 - Schematics between GL852G and 93C46........................................................ 26

Figure 6.1 - Vin(V5) vs Vout(V33)*...................................................................................... 33

Figure 7.1 - GL852G 48 Pin LQFP Package........................................................................ 34

Figure 7.2 - GL852G 28 Pin QFN Package.......................................................................... 35

Figure 7.3 - GL852G 28 Pin SSOP Package ........................................................................36

Figure 7.4 - GL852G 46 Pin LQFN Package ....................................................................... 37

GL852G Datasheet

List of Tables

Table 3.1 - GL852G LQFP 48 Pin List................................................................................. 14

Table 3.2 - GL852G QFN 28 Pin List ................................................................................... 14

Table 3.3 - GL852G SSOP 28 Pin List ................................................................................. 14

Table 3.4 - GL852G LQFN 46 Pin List ................................................................................15

Table 3.5 - Pin Descriptions................................................................................................... 16

Table 5.1 - Configuration by Power Switch Type ............................................................... 26

Table 5.2 - Port Number Configuration............................................................................... 26

Table 5.3 - Ref. Clock Configuration.................................................................................... 27

Table 6.1 - Maximum Ratings............................................................................................... 28

Table 6.2 - Operating Ranges................................................................................................ 28

Table 6.3 - DC Characteristics except USB Signals ............................................................ 28

Table 6.4 - DC Characteristics of USB Signals under FS/LS Mode .................................. 29

Table 6.5 - DC Characteristics of USB Signals under HS Mode ....................................... 29

Table 6.6 - DC Supply Current ............................................................................................. 30

Table 6.7 - AC Characteristics of EEPROM Interface (93C46) ........................................ 31

Table 6.8 - AC Characteristics of EEPROM Interface (24C02) ........................................ 32

Table 8.1 - Ordering Information......................................................................................... 38

GL852G Datasheet

CHAPTER 1 GENERAL DESCRIPTION

GL852G is Genesys Logic’s premium 4-port hub solution which fully complies with Universal Serial Bus

Specification Revision 2.0. GL852G implements multiple TT* (Note1) architecture that provide dedicated

TT* to each downstream (DS) ports, which guarantee Full-Speed(FS) data passing bandwidth when multiple FS device perform heavy loading operations. The controller inherits Genesys Logic’s cutting edge technology on cost and power efficient serial interface design. GL852G has proven compatibility, lower power consumption figure and better cost structure above all USB2.0 hub solutions worldwide.

GL852G implements multiple hub configuration features onto internal mask ROM, which traditionally requires one external EEPROM. The microprocessor detects general purpose I/O (GPIO) status during the initial stage to configure hub settings such as (1) number of DSport, (2) declare of compound device (3) gang/individual mode selection…etc. External EEPROM can be removed if no vendor specified PID/VID or product string is required for the application.

GL852G supports three package types, summarized as below table. LQFP48/LQFN46 package provides full hub features such as (1) two-color (green/amber) status LEDs for each DS ports, (2) Individual/Gang mode power management scheme that indicates DS port over-current events. (3) Number of DS ports setting configured by GPIO setting (4) non-removable declaration configured by GPIO setting (5) Support both 93C46 and 24C02 EEPROM (6) power switch polarity selections…etc. QFN28/SSOP28 package support only partial hub features but provide smaller footprint that targets space limited PCB layout environments such as embedded system or UMPC/MID applications.

Package

Type

LQFP 48 4 GPIO

QFN 28 4 EEPROM EEPROM Individual/Gang N/A 24C02

SSOP 28 4 EEPROM EEPROM Gang N/A 24C02

LQFN46 4 GPIO

*Note 1: TT (transaction translator) is the main traffic control engine in an USB 2.0 hub to handle the unbalanced traffic speed between the upstream port and the downstream ports.

# of DS

Ports

Port #

Config.

Non-removable

Declaration

EEPROM/

GPIO

EEPROM/

GPIO

GL852G Package – Feature Summary

Power Mgmt. LED Support EEPROM

Individual/Gang Green/Amber 93C46/ 24C02

GL852G Datasheet

CHAPTER 2 FEATURES



Compliant to USB specification Revision 2.0

 4 downstream ports  Upstream port supports both high-speed (HS) and full-speed (FS) traffic  Downstream ports support HS, FS, and low-speed (LS) traffic

 1 control pipe (endpoint 0, 64-byte data payload) and 1 interrupt pipe (endpoint 1, 1-byte data payload)

 Backward compatible to USB specification Revision 1.1

 On-chip 8-bit micro-processor

 RISC-like architecture  USB optimized instruction set  Dual cycle instruction execution  Performance: 6 MIPS @ 12MHz  With 64-byte RAM and 2K internal ROM  Support customized PID, VID by reading external EEPROM  Support downstream port configuration by reading external EEPROM

 Multiple Transaction translator (MTT)

 MTT provides respective TT control logics for each downstream port.

 Each downstream port supports two-color status indicator, with automatic and manual modes compliant to

USB specification Revision 2.0

 Built-in upstream port 1.5KΩ pull-up and downstream port 15KΩ pull-down resistors  Support both individual and gang modes of power management and over-current detection for

downstream ports

 Conform to bus power requirements of USB 2.0 specification  Automatic switching between self-powered and bus-powered modes  Integrate USB 2.0 transceiver  Embedded PLL support external 12 MHz crystal / Oscillator clock input  Optional 27/48 MHz Oscillator clock input (Only available in LQFP48/ LQFN46 package)  Support compound-device (non-removable in downstream ports) by I/O pin configuration (Only available

in LQFP48/ LQFN46 package)

 Number of Downstream port can be configured by GPIO without external EEPROM (Only available in

LQFP48/ LQFN46 package)

 Built-in 5V to 3.3V regulator  Improve output drivers with slew-rate control for EMI reduction  Internal power-fail detection for ESD recovery  Available package types: 48 pin LQFP, 28 pin QFN, 28 pin SSOP and 46 pin LQFN  Applications:

 Stand-alone USB hub / USB docking  UMPC/MID, motherboard on-board applications  Consumer electronics built-in hub application  Monitor built-in hub  Embedded systems  Compound device to support USB hub function such as keyboard hub applications

GL852G Datasheet

CHAPTER 3 PIN ASSIGNMENT

3.1 Pinouts

PSELF 37

DVDD 38

PGANG 39

OVCUR2# 40

PWREN2#

OVCUR1# 42

PWREN1# / SDA 43

SEL27# 44

GREEN1/EE_SK 45

AMBER1/EE_CS 46

V5 47

V33 48

24

23

22

21

41

20

19

18

17

16

15

14

13

AMBER4

GREEN4

DP4

DM4

GND

AVDD

DP3

DM3

AVDD

X2

X1

GND

Figure 3.1 - GL852G 48 Pin LQFP Pinout Diagram

GL852G Datasheet

PSELF

PGANG

OVCUR2#

OVCUR1#

SDA

V5

V33

22

23

24

25

26

27

28

DVDD

21

1

OVCUR4#

OVCUR3#

20

19

QFN-28

2

3

18

RESET#

17

5

TEST/SCL

4

DP4

16

6

DM4

15

14

13

12

11

10

9

8

7

AVDD

DP3

DM3

X2

X1

AVDD

RREF

DM0

DP0

DM1

DP1

DM2

DP2

AVDD

Figure 3.2 - GL852G 28 Pin QFN Pinout Diagram

GL852G Datasheet

AVDD

DM2

DP2

RREF

AVDD

X1

X2

DM3

DP3

AVDD

DM4

DP4

RESET#

10

11

12

13

1

2

3

4

5

6

7

8

9

28

27

26

25

24

23

22

PWREN1#

21

OVCUR1#

20

PWREN2#

19

OVCUR2#

18

PGANG

17

PSELF

16

DVDD

DP1

DM1

DP0

DM0

V33

V5

TEST/SCL

14

15

GND

Figure 3.3 - GL852G SSOP 28 Pin Pinout Diagram

GL852G Datasheet

V33

V5

AMBER1

GREEN1

SEL27#

PWREN1#

OVCUR1#

PWREN2#

OVCUR2#

PGANG

PSELF

AMBER2

GREEN2

DVDD

46 45 44 43 42 41 40 39 38 37 36 35 34 33

AVDD

1

32

AMBER3

AVDD

DM0

DP0

DM1

DP1

DM2

DP2

RREF

2

3

4

5

6

7

8

9

10 11 12 13

X1

NC

AVDD

X2

LQFN - 46

14 15

AVDD

16 17 18 19 20 21 22 23

DM3

DP3

AVDD

DM4

DP4

GREEN4

AMBER4

NC

31

30

29

28

27

26

25

24

NC

GREEN3

PWREN3#

OVCUR3#

PWREN4#

OVCUR4#

TEST

RESET#

SEL48#

Figure 3.4 - GL852G LQFN 46 Pin Pinout Diagram

GL852G Datasheet

3.2 Pin List

Table 3.1 - GL852G LQFP 48 Pin List

Pin# Pin Name Type Pin# Pin Name Typ e Pin# Pin Name Type Pin# Pin Name Typ e

1 AVDD P 13 GND P 25 SEL48# I 37 PSELF I

2 GND P 14 X1 I 26 RESET# I 38 DVDD P

3 DM0 B 15 X2 O 27 TEST / SCL B 39 PGANG B

4 DP0 B 16 AVDD P 28 OVCUR4# I 40 OVCUR2# I

5 DM1 B 17 DM3 B 29 PWREN4# O 41 PWREN2# O

6 DP1 B 18 DP3 B 30 OVCUR3# I 42 OVCUR1# I

7 AVDD P 19 AVDD P 31 PWREN3# O 43 PWREN1#/ SDA B

8 GND P 20 GND P 32 GREEN3 O 44 SEL27# I

9 DM2 B 21 DM4 B 33 AMBER3 O 45 GREEN1/EE_SK O

10 DP2 B 22 DP4 B 34 DVDD P 46 AMBER1/EE_CS O

11 RREF A 23 GREEN4 O 35

12 AVDD P 24 AMBER4 O 36

GREEN2/

EE_DO

AMBER2/

EE_DI

O47 V5 I/P

O48 V33 O/P

Table 3.2 - GL852G QFN 28 Pin List

Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Ty pe

1 DM0 B 8 RREF A 15 DM4 B 22 PSELF I_5V

2 DP0 B 9 AVDD P 16 DP4 B 23 PGANG B

3 DM1 B 10 X1 I 17 RESET# I_5V 24 OVCUR2# I_5V

4 DP1 B 11 X2 I 18 TEST/SCL I/B 25 OVCUR1# I_5V

5 AVDD P 12 DM3 B 19 OVCUR4# I_5V 26 SDA O

6 DM2 B 13 DP3 B 20 OVCUR3# I_5V 27 V5 I/P

7 DP2 B 14 AVDD P 21 DVDD P 28 V33 O/P

Table 3.3 - GL852G SSOP 28 Pin List

Pin# Pin Name Ty pe Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Ty pe

1 AVDD P 8 DM3 B 15 GND P 22 PWREN1# O

2 DM2 B 9 DP3 B 16 DVDD P 23 V5 P

3 DP2 B 10 AVDD P 17 PSELF I_5V 24 V33 P

4 RREF A 11 DM4 B 18 PGANG B 25 DM0 B

5 AVDD P 12 DP4 B 19 OVCUR2# I_5V 26 DP0 B

6 X1 I 13 RESET# I 20 PWREN2#* O 27 DM1 B

7 X2 O 14 TEST/SCL I/B 21 OVCUR1#* I_5V 28 DP1 B

GL852G Datasheet

Table 3.4 - GL852G LQFN 46 Pin List

Pin# Pin Name Type Pin# Pin Name Ty pe Pin# Pin Name Ty pe Pin# Pin Name Type

1 AVDD P 13 X2 O 25 RESET# I 37 PGANG B

2 DM0 B 14 AVDD P 26 TEST I 38 OVCUR2# I

3 DP0 B 15 DM3 B 27 OVCUR4# I 39 PWREN2# O

4 DM1 B 16 DP3 B 28 PWREN4# O 40 OVCUR1# I

5 DP1 B 17 AVDD P 29 OVCUR3# I 41 PWREN1# O

6 AVDD P 18 DM4 B 30 PWREN3# O 42 SEL27# I

7 DM2 B 19 DP4 B 31 GREEN3 O 43 GREEN1 O

8 DP2 B 20 GREEN4 O 32 AMBER3 O 44 AMBER1 O

9 RREF A 21 AMBER4 O 33 DVDD P 45 V5 P

10 AVDD P 22 NC - 34 GREEN2 O 46 V33 P

11 NC - 23 NC - 35 AMBER2 O

12 X1 I 24 SEL48# I 36 PSELF I

GL852G Datasheet

3.3 Pin Descriptions

Table 3.5 - Pin Descriptions

USB Interface

Pin Name

LQFP 48 Pin

GL852G

QFN

28 Pin

SSOP

28 Pin

LQFN

46 Pin

I/O

Type

Description

DM0,DP0 3,4 1,2 25,26 2,3 B USB signals for USPORT

DM1,DP1 5,6 3,4 27,28 4,5 B USB signals for DSPORT1

DM2,DP2 9,10 6,7 2,3 7,8 B USB signals for DSPORT2

DM3,DP3 17,18 12,13 8,9 15,16 B USB signals for DSPORT3

DM4,DP4 21,22 15,16 11,12 18,19 B USB signals for DSPORT4

RREF 11 8 4 9 A

A 680Ω resister must be connected between RREF and analog ground (AGND).

Note: USB signals must be carefully handled in PCB routing. For detailed information, please refer to

GL85X Design Guide.

Hub Interface

GL852G

Pin Name

OVCUR1#~4

PWREN1#~4

GREEN1~4

AMBER1~4

LQFP 48 Pin

42,40,

30,28

43,41,

31,29

45,35,

32,23

46,36,

33,24

QFN

28 Pin

25,24,

20,19

SSOP

28 Pin

21,19

- 22,20

- -

LQFN 46 Pin

40,38,

29,27I (pu)

41,39,

30,28

43,34,

31,20

44,35,

32,21O (pd)

PSELF 37 22 17 36 I

I/O

Type

O

1,3,4: O

2: B (pd)

Description

Active low. Over current indicator for DSPORT1~4 OVCUR1# is the only over current flag for GANG

mode.

Active low. Power enable output for DSPORT1~4 PWREN1# is the only power-enable output for

GANG mode.

Green LED indicator for DSPORT1~4

*GREEN[1~2] are also used to access the external EEPROM

For detailed information, please refer to Chapter 5.

Amber LED indicator for DSPORT1~4

*Amber [1~2] are also used to access the external EEPROM

0: GL852G is bus-powered. 1: GL852G is self-powered.

This pin is default put in input mode after power-on reset. Individual/gang mode is strapped during this period. After the strapping period, this pin will be set to output mode, and then output high for normal mode.

PGANG 39 23 18 37 B

When GL852G is suspended, this pin will output low.

*For detailed explanation, please see Chapter 5 Gang input:1, output: 0@normal,

1@suspend Individual input:0, output: 1@normal,

0@suspend

GL852G Datasheet

Clock and Reset Interface

GL852G

Pin Name

X1 14 10 6 12 I Crystal / OSC clock input

X2 15 11 7 13 O Crystal clock output.

RESET# 26 17 13 25 I

SEL48#/

SEL27#

LQFP

48 Pin

25,44 -- -- 24,42 I

QFN

28 Pin

SSOP

28 Pin

LQFN 46 Pin

I/O

Type

Active low. External reset input, default pull high 10KΩ. When RESET# = low, whole chip is reset to the initial

state.

SEL48#/SEL27#: 0 1: 48MHz OSC-in 1 0: 27MHz OSC-in 1 1: 12MHz X’tal/OSC-in

System Interface

GL852G

Pin Name

TEST/SCL 27 18 14 26

SDA -- 26 -- - B I2C data pin

LQFP 48 Pin

QFN

28 Pin

SSOP

28 Pin

LQFN

46 Pin

I/O

Type

I

TEST: 0: Normal operation.

(pd)

1: Chip will be put in test mode.

B

I2C: clock output pin

Description

Power / Ground

GL852G

Pin Name

AV D D

DVDD 34,38 21 16 33 P 3.3V digital power input for digital circuits

GND

V5 47 27 23 45 P / I

V33 48 28 24 46 P / O

LQFP 48 Pin

1,7,12,

16,19

2,8,

13,20

Note: Analog circuits are quite sensitive to power and ground noise. PCB layout must take care the power

routing and the ground plane. For detailed information, please refer to GL85X Design Guide.

QFN

28 Pin

5,9,14 1,5,10

SSOP

28 Pin

- 15 - P

LQFN 46 Pin

1,6,10,

14,17

I/O

Type

P 3.3V analog power input for analog circuits.

Ground Exposed pad is connected to GND (QFN28/ LQFN46)

5V Power input. It need be NC if using external regulator

5V-to-3.3V regulator Vout (LQFP48/ LQFN46) 5V-to-3.3V regulator Vout & 3.3 input

(QFN28/SSOP28) It can be NC or connect to 3.3V power if using external

regulator (LQFP48/ LQFN46 only)

Description

GL852G Datasheet

Notation:

Type O Output

I Input

B Bi-directional

B/I Bi-directional, default input

B/O Bi-directional, default output

P Power / Ground

A Analog

SO Automatic output low when suspend

pu Internal pull up

pd Internal pull down

odpu Open drain with internal pull up

GL852G Datasheet

CHAPTER 4 BLOCK DIAGRAM

D+ D-

USPORT

Transceiver

UTMI

REPEATER

FRTIMER

USPORT

TT

(Transaction

Translator)

Logic

TT

(Transaction

Translator)

PLL

x40, x10

SIE

(Transaction

12/27/48

MHz

TT

Translator)

RA

ROM

M

CPU

Control/Status

Register

TT

(Transaction

Translator)

GPIO

REPEATER / TT Routing Logic

DSPORT1 Logic DSPORT2 Logic DSPORT3 Logic DSPORT4 Logic

DSPORT

Transceiver

D+ D-

LED/

OVCUR/

PWRENB

DSPORT DSPORT DSPORT

Transceiver Transceiver Transceiver

D+ D-

LED/

OVCUR/

PWRENB

D+ D-

LED/

OVCUR/

PWRENB

D+ D-

LED/

OVCUR/

PWRENB

Figure 4.1 - GL852G Block Diagram (Multiple TT)

GL852G Datasheet

CHAPTER 5 FUNCTION DESCRIPTION

5.1 General Description

5.1.1 USPORT Transceiver

USPORT (upstream port) transceiver is the analog circuit that supports both full-speed and high-speed electrical characteristics defined in chapter 7 of USB specification Revision 2.0. USPORT transceiver will operate in full-speed electrical signaling when GL852G is plugged into a 1.1 host/hub. USPORT transceiver will operate in high-speed electrical signaling when GL852G is plugged into a 2.0 host/hub.

5.1.2 PLL (Phase Lock Loop)

GL852G contains a 40x PLL. PLL generates the clock sources for the whole chip. The generated clocks are proven quite accurate that help in generating high speed signal without jitter.

5.1.3 FRTIMER

This module implements hub (micro)frame timer. The (micro)frame timer is derived from the hub’s local clock and is synchronized to the host (micro)frame period by the host generated Start of (micro)frame (SOF). FRTIMER keeps tracking the host’s SOF such that GL852G is always safely synchronized to the host. The functionality of FRTIMER is described in section 11.2 of USB Specification Revision 2.0.

5.1.4 μC

μC is the micro-processor unit of GL852G. It is an 8-bit RISC processor with 2K ROM and 64 bytes RAM. It operates at 6MIPS of 12 MHz clock to decode the USB command issued from host and then prepares the data to respond to the host. In addition, μC can handle GPIO (general purpose I/O) settings and reading content of EEPROM to support high flexibility for customers of different configurations of hub. These configurations include self/bus power mode setting, individual/gang mode setting, downstream port number setting, device removable/non-removable setting, and PID/VID setting.

5.1.5 UTMI (USB 2.0 Transceiver Microcell Interface)

UTMI handles the low level USB protocol and signaling. It’s designed based on the Intel’s UTMI specification 1.01. The major functions of UTMI logic are to handle the data and clock recovery, NRZI encoding/decoding, Bit stuffing /de-stuffing, supporting USB 2.0 test modes, and serial/parallel conversion.

5.1.6 USPORT Logic

USPORT implements the upstream port logic defined in section 11.6 of USB specification Revision 2.0. It mainly manipulates traffics in the upstream direction. The main functions include the state machines of Receiver and Transmitter, interfaces between UTMI and SIE, and traffic control to/from the REPEATER and TT.

5.1.7 SIE (Serial Interface Engine)

SIE handles the USB protocol defined in chapter 8 of USB specification Revision 2.0. It co-works with μC to play the role of the hub kernel. The main functions of SIE include the state machine of USB protocol flow,

CRC check, PID error check, and timeout check. Unlike USB 1.1, bit stuffing/de-stuffing is implemented in UTMI, not in SIE.

5.1.8 Control/Status Register

Control/Status register is the interface register between hardware and firmware. This register contains the information necessary to control endpoint0 and endpoint1 pipelines. Through the firmware based architecture, GL852G possesses higher flexibility to control the USB protocol easily and correctly.

GL852G Datasheet

5.1.9 REPEATER

Repeater logic implements the control logic defined in section 11.4 and section 11.7 of USB specification Revision 2.0. REPEATER controls the traffic flow when upstream port and downstream port are signaling in the same speed. In addition, REPEATER will generate internal resume signal whenever a wakeup event is issued under the situation that hub is globally suspended.

5.1.10 TT (Transaction Translator)

TT implements the control logic defined in section 11.14 ~ 11.22 of USB specification Revision 2.0. TT basically handles the unbalanced traffic speed between the USPORT (operating in HS) and DSPORTS (operating in FS/LS) of hub. GL852G adopts multiple TT architecture to provide the most performance effective solution. Multiple TT provides control logics for each downstream port respectively.

5.1.11 REPEATER/TT Routing Logic

REPEATER and TT are the major traffic control machines in the USB 2.0 hub. Under situation that USPORT and DSPORT are signaling in the same speed, REPEATER/TT routing logic switches the traffic channel to the REPEATER. Under situation that USPORT is in the high speed signaling and DSPORT is in the full/low speed signaling, REPEATER/TT routing logic switches the traffic channel to the TT.

5.1.11.1 Connected to 1.1 Host/Hub

If an USB 2.0 hub is connected to the downstream port of an USB 1.1 host/hub, it will operate in USB 1.1 mode. For an USB 1.1 hub, both upstream direction traffic and downstream direction traffic are passing through REPEATER. That is, the REPEATER/TT routing logic will route the traffic channel to the REPEATER.

Figure 5.1 - Operating in USB 1.1 Schemes

GL852G Datasheet

5.1.11.2 Connected to USB 2.0 Host/Hub

If an USB 2.0 hub is connected to an USB 2.0 host/hub, it will operate in USB 2.0 mode. The upstream port signaling is in high speed with bandwidth of 480 Mbps under this environment. The traffic channel will then be routed to the REPEATER when the device connected to the downstream port is signaling also in high speed. On the other hand, the traffic channel will then be routed to TT when the device connected to the downstream port is signaling in full/low speed.

USB 2.0 HOST/HUB

USPORToperating in HS signaling

HS vs. HS: Traffic channel is routed to REPEATER

REPEATER

TT

HS vs. FS/LS: Traffic channel is routed to TT

DSPORT operating in HS signaling

DSPORT operating in FS/LS signaling

Figure 5.2 - Operating in USB 2.0 Schemes

5.1.12 DSPORT Logic

DSPORT (downstream port) logic implements the control logic defined in section 11.5 of USB specification Revision 2.0. It mainly manipulates the state machine, the connection/disconnection detection, over current detection and power enable control, and the status LED control of the downstream port. Besides, it also output the control signals to the DSPORT transceiver.

5.1.13 DSPORT Transceiver

DSPORT transceiver is the analog circuit that supports high-speed, full-speed, and low-speed electrical characteristics defined in chapter 7 of USB specification Revision 2.0. In addition, each DSPORT transceiver accurately controls its own squelch level to detect the detachment and attachment of devices.

GL852G Datasheet

5.2 Configuration and I/O Settings

5.2.1 RESET Setting

GL852G’s power on reset can either be triggered by external reset or internal power good reset circuit. The external reset pin, RESETJ, is connected to upstream port Vbus (5V) to sense the USB plug / unplug or 5V voltage drop. The reset trigger voltage can be set by adjusting the value of resistor R1 and R2 (Suggested value refers to schematics) GL852G’s internal reset is designed to monitor silicon’s internal core power (3.3V) and initiate reset when unstable power event occurs. The power on sequence will start after the power good voltage has been met, and the reset will be released after approximately 2.7 μS after power good. GL852G’s reset circuit as depicted in the picture

Silicon

Ext. VBUS power-good

detection circuit input

(Pin"RESET#")

EXT

INT

Int. 3.3V power-good

detection circuit input

(USB PHY reset)

Global Reset#

V

BUS

(External 5V)

PCB

R1

R2

Figure 5.3 - Power on Reset Diagram

To fully control the reset process of GL852G, we suggest the reset time applied in the external reset circuit should longer than that of the internal reset circuit. Timing of POR is illustrated as below figure.

Figure 5.4 - Power on Sequence of GL852G

GL852G Datasheet

5.2.2 PGANG Setting

To save pin count, GL852G uses the same pin to decide individual/gang mode as well as to output the suspend flag. The individual/gang mode is decided within 20us after power on reset. Then, about 50ms later, this pin is changed to output mode. GL852G outputs the suspend flag once it is globally suspended. For individual mode, a pull low resister greater than 100KΩ should be placed. For gang mode, a pull high resister which greater than 100KΩ should be placed. In figure 5.6, we also depict the suspend LED indicator schematics. It should be noticed that the polarity of LED must be followed, otherwise the suspend current will be over spec limitation (2.5mA).

Figure 5.5 - Timing of PGANG Strapping

"0": Individual Mode "1": GANG Mode

SUSPNDO

GANG_CTL

Inside GL852G

On PCB

DVDD(3.3V)

100K ohm

GAND Mode

DVDD(3.3V)

Suspend LED Indicator

Individual

Mode

Figure 5.6 - GANG Mode Setting

GL852G Datasheet

5.2.3 SELF/BUS Power Setting

GL852G can operate under bus power and conform to the power consumption limitation completely (suspend current < 2.5 mA, normal operation current < 100 mA). By setting PSELF, GL852G can be configured as a bus-power or a self-power hub.

1: Power Self

0: Power Bus

Inside GL852G

PSELF

On PCB

Figure 5.7 - SELF/BUS Power Setting

5.2.4 LED Connections

GL852G controls the LED lighting according to the flow defined in section 11.5.3 of Universal Serial Bus Specification Revision2.0. Both manual mode and Automatic mode are supported in GL852G. When GL852G is globally suspended, GL852G will turn off the LED to save power.

Figure 5.8 - LED Connection

GL852G Datasheet

5.2.5 EEPROM Setting

GL852G replies to host commands by the default settings in the internal ROM. GL852G also offers the ability to reply to the host according to the settings in the external EEPROM (LQFP48/LQFN46 supports both 93C46 and 24C02; QFN28 only supports 24C02). And to prevent the content of EEPROM from being over-written, amber LED will be disabled when EEPROM exists. The detail setting information please refers to the GL852G AP Note_EEPROM Info document.

The schematics between GL852G and 93C46 are depicted in the following figures:

Figure 5.9 - Schematics between GL852G and 93C46

GL852G firstly verifies the check sum after power on reset. If the check sum is correct, GL852G will take the configuration of 93C46 as part of the descriptor contents. To prevent the content of 93C46 from being over-written, amber LED will be disabled when 93C46 exists.

5.2.6 Power Switch Enable Polarity (Only Available for LQFP48/LQFN46 Package)

Both low/high-enabled power switches are supported. It is determined by jumper setting, based on the state of pin AMBER2, as the following table:

Table 5.1 - Configuration by Power Switch Type

AMBER2 Power Switch Enable Polarity

0 Low-active

1 High-active

5.2.7 Port Number Configuration (Only Available for LQFP48/LQFN46 Package)

Number of downstream port can be configured as 2/3/4 ports by pin strapping in addition to EEPROM, based on the state of pin AMBER 3, AMBER 4, as the following table:

Table 5.2 - Port Number Configuration

AMBER 3 AMBER 4 # of DP Declaration

1 1 1 (Port1)

1 0 2 (Port1/2)

0 1 3 (Port1/2/3)

0 0 4 (Port1/2/3/4)

GL852G Datasheet

5.2.8 Non-removable Port Configuration (Only Available for LQFP48/LQFN46 Package)

For compound application or embedded system, downstream ports that always connected inside the system can be set as non-removable based on the state of corresponding status LED, pin GREEN 1~4. If the pin is pull high in the initial stage (POR reset), the corresponding port will be set as non-removable. (Feature Limitation: Green 1 & Green 2 pull-high concurrently will enable GL852G vendor proprietary function that may affect system compatibility. System integrator should evade configuring both port #1 and #2 as non-removable by this strapping feature)

5.2.9 Reference Clock Configuration (Only Available for LQFP48/LQFN46 Package)

GL852G can support optional 27/48MHz clock source, which is selectable through GPIO configurations. For some on-board design that 27/48MHz clock source is available, such as motherboard or Monitor built-in applications, system integrator can leverage this feature to further reduce BOM cost by removing external crystal.

Table 5.3 - Ref. Clock Configuration

SEL48 SEL27 Clock Source

0 1 48MHz OSC-in

1 0 27MHz OSC-in

1 1 12MHz X’tal/OSC-in

GL852G Datasheet

CHAPTER 6 ELECTRICAL CHARACTERISTICS

6.1 Maximum Ratings

Table 6.1 - Maximum Ratings

Symbol Parameter Min. Max. Unit

V5 5V Power Supply -0.5 +6.0 V

VDD 3.3V Power Supply -0.5 +3.6 V

VIN 3.3V Input Voltage for digital I/O(EE_DO) pins -0.5 +3.6 V

V

Open-Drain Input (Ovcur1-4,Pself,Reset) -0.5 +5.5 V

INOD

V

Input Voltage for USB signal (DP, DM) pins -0.5 +3.6 V

INUSB

TS Storage Temperature under bias -60 +100

F

Frequency

OSC

6.2 Operating Ranges

12 MHz  500ppm

o

C

Table 6.2 - Operating Ranges

Symbol Parameter Min. Ty p. Max. Unit

V5 5V Power Supply 4.5 5.0 5.5 V

VDD 3.3V Power Supply 3.0 3.3 3.6 V

V

Input Voltage for digital I/O pins -0.5 3.3 3.6 V

IND

V

Input Voltage for USB signal (DP, DM) pins 0.5 3.3 3.6 V

INUSB

TA Ambient Temperature 0 - 70

TJ Absolute maximum junction temperature 0 - 125

Thermal Characteristics LQFP 48 - 78.7 -

θJA

Thermal Characteristics QFN 28 - 33.3 -

Thermal Characteristics SSOP 28 - 61.6 -

6.3 DC Characteristics

Table 6.3 - DC Characteristics except USB Signals

Symbol Parameter Min. Ty p. Max. Unit

PD Power Dissipation - - 431.5 mW

VIL LOW level input voltage - - 0.8 V

VIH HIGH level input voltage 2.0 - - V

V

LOW to HIGH threshold voltage 1.4 1.5 1.6 V

TLH

V

HIGH to LOW threshold voltage 0.87 0.94 0.99 V

THL

VOL LOW level output voltage when IOL=8mA - - 0.4 V

VOH HIGH level output voltage when IOH=8mA 2.4 - - V

I

OLK

RDN Pad internal pull down resister 29K 59K 135K Ω

RUP Pad internal pull up resister 80K 108K 140K Ω

Leakage current for pads with internal pull up or pull

down resistor

- - 30

o

C/W

o

C/W

o

C/W

A

C

GL852G Datasheet

Table 6.4 - DC Characteristics of USB Signals under FS/LS Mode

Symbol Parameter Min. Ty p. Max. Unit

VOL DPF/DMF static output LOW(RL of 1.5K to 3.6V ) 0 - 0.3 V

VOH DPF/DMF static output HIGH (RL of 15K to GND ) 2.8 - 3.6 V

VDI Differential input sensitivity 0.2 - - V

VCM Differential common mode range 0.8 - 2.5 V

VSE Single-ended receiver threshold 0.2 - - V

CIN Transceiver capacitance - - 20 pF

ILO Hi-Z state data line leakage -10 - +10

Z

Driver output resistance 28 - 44 Ω

DRV

A

Table 6.5 - DC Characteristics of USB Signals under HS Mode

Symbol Parameter Min. Ty p. Max. Unit

VOL DPH/DMH static output LOW(RL of 1.5K to 3.6V ) - - 0.1 V

CIN Transceiver capacitance 4 4.5 5 pF

ILO Hi-Z state data line leakage -5 0 +5

Z

Driver output resistance for USB 2.0 HS 48 45 42 Ω

DRV

A

GL852G Datasheet

6.4 Power Consumption

Table 6.6 - DC Supply Current

Symbol

Active ports Host Device

I

Suspend 784 uA

SUSP

4

3

ICC

2

1

No Active

Condition

F*1 F 89.9

H*1 H 81.6

H F 87.6

F F 78.9

H H 72.6

H F 76.3

F F 67.7

H H 61.6

H F 65.3

F F 56.9

H H 52

H F 54.4

F N/A 42.5

H N/A 43.9

Internal

Regulator

Unit

mA

*: F: Full-Speed, H: High-Speed

Note:

Test result represents silicon level operating current, without considering additional power consumption contributed by external over-current protection circuit such as power switch or polyfuse.

6.5 AC Characteristics

GL852G LQFP 48/LQFN46 pin package can support both 93C46 & 24C02 type EEPROM for customized VID/PID. GL852G QFN28/SSOP28 pin package can only support 24C02 type EEPROM. AC characteristics of these two types of EEPROM summarized as below figures and tables.

GL852G Datasheet

6.5.1 93C46 EEPROM IF

Table 6.7 - AC Characteristics of EEPROM Interface (93C46)

Symbol Parameter Min. Typ. Max. Units

t

CS Setup Time 3.0

CSS

t

CS Hold Time 3.0

CSH

t

SK High Time 1.0

SKH

t

SK Low Time 2.2

SKL

t

DI Setup Time 1.8

DIS

t

DI Hold Time 2.4

DIH

t

Output Delay to “1” 1.8

PD1

t

Output Delay to “0” 1.8

PD0

us

GL852G Datasheet

6.5.2 24C02 EEPROM Interface

Table 6.8 - AC Characteristics of EEPROM Interface (24C02)

GL852G Datasheet

6.6 On-Chip Power Regulator

GL852G requires 3.3V source power for normal operation of internal core logic and USB physical layer (PHY). The integrated low-drop power regulator converts 5V power input from USB cable (Vbus) to 3.3V voltage for silicon power source. The 3.3V power output is guaranteed by an internal voltage reference circuit to prevent unstable 5V power compromise USB data integrity. The regulator’s maximum current loading is 200mA, which provides enough tolerance for normal GL852G operation (below 100mA).

On-chip Power Regulator Features:

 5V to 3.3V low-drop power regulator  200mA maximum output driving capability  Provide stable 3.3V output when Vin = 3.4V~5.5V  Max. suspend current:190uA; typical suspend current 164uA

Figure 6.1 - Vin(V5) vs Vout(V33)*

*Note: Measured environment: Ambient temperature = 25℃ / Current Loading = 200mA

GL852G Datasheet

CHAPTER 7 PACKAGE DIMENSION

Internal

No.

Date

Code

Lot Code

Versio n No.

Figure 7.1 - GL852G 48 Pin LQFP Package

GL852G Datasheet

Internal

No.

Date Code

Version

No.

Lot Code

Figure 7.2 - GL852G 28 Pin QFN Package

GL852G Datasheet

Internal No.

Date

Code

Lot Code

Version

No.

Figure 7.3 - GL852G 28 Pin SSOP Package

GL852G Datasheet

Internal

No.

Date

Code

Lot No.

Versio n No.

Figure 7.4 - GL852G 46 Pin LQFN Package

GL852G Datasheet

CHAPTER 8 ORDERING INFORMATION

Table 8.1 - Ordering Information

Part Number Package Green/Wire Material Version Status

GL852G-MNGXX LQFP 48 Green Package XX Available

GL852G-OHG*XX QFN 28 Green Package XX Available

GL852G-HHGXX SSOP 28 Green Package XX Available

GL852G-PMGXX LQFN 46 Green Package XX Available

*The marking of "OHG" will not be shown on the IC due to QFN28 package size limitation.