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Genesys Logic, Inc.
12F., No. 205, Sec. 3, Beixin Rd., Xindian Dist. 231,
GL852G is Genesys Logic’s premium 4-port hub solution which fully complies with Universal Serial Bus
Specification Revision 2.0. GL852G implements multiple TT* (Note1) architecture that provide dedicated
TT* to each downstream (DS) ports, which guarantee Full-Speed(FS) data passing bandwidth when multiple
FS device perform heavy loading operations. The controller inherits Genesys Logic’s cutting edge
technology on cost and power efficient serial interface design. GL852G has proven compatibility, lower power
consumption figure and better cost structure above all USB2.0 hub solutions worldwide.
GL852G implements multiple hub configuration features onto internal mask ROM, which traditionally
requires one external EEPROM. The microprocessor detects general purpose I/O (GPIO) status during the
initial stage to configure hub settings such as (1) number of DSport, (2) declare of compound device (3)
gang/individual mode selection…etc. External EEPROM can be removed if no vendor specified PID/VID or
product string is required for the application.
GL852G supports three package types, summarized as below table. LQFP48/LQFN46 package provides full
hub features such as (1) two-color (green/amber) status LEDs for each DS ports, (2) Individual/Gang mode
power management scheme that indicates DS port over-current events. (3) Number of DS ports setting
configured by GPIO setting (4) non-removable declaration configured by GPIO setting (5) Support both
93C46 and 24C02 EEPROM (6) power switch polarity selections…etc. QFN28/SSOP28 package support only
partial hub features but provide smaller footprint that targets space limited PCB layout environments such as
embedded system or UMPC/MID applications.
Package
Type
LQFP 48 4 GPIO
QFN 28 4 EEPROM EEPROM Individual/GangN/A 24C02
SSOP 28 4 EEPROM EEPROM Gang N/A 24C02
LQFN46 4 GPIO
*Note 1: TT (transaction translator) is the main traffic control engine in an USB 2.0 hub to handle the
unbalanced traffic speed between the upstream port and the downstream ports.
4 downstream ports
Upstream port supports both high-speed (HS) and full-speed (FS) traffic
Downstream ports support HS, FS, and low-speed (LS) traffic
1 control pipe (endpoint 0, 64-byte data payload) and 1 interrupt pipe (endpoint 1, 1-byte data payload)
Backward compatible to USB specification Revision 1.1
On-chip 8-bit micro-processor
RISC-like architecture
USB optimized instruction set
Dual cycle instruction execution
Performance: 6 MIPS @ 12MHz
With 64-byte RAM and 2K internal ROM
Support customized PID, VID by reading external EEPROM
Support downstream port configuration by reading external EEPROM
Multiple Transaction translator (MTT)
MTT provides respective TT control logics for each downstream port.
Each downstream port supports two-color status indicator, with automatic and manual modes compliant to
USB specification Revision 2.0
Built-in upstream port 1.5KΩ pull-up and downstream port 15KΩ pull-down resistors
Support both individual and gang modes of power management and over-current detection for
downstream ports
Conform to bus power requirements of USB 2.0 specification
Automatic switching between self-powered and bus-powered modes
Integrate USB 2.0 transceiver
Embedded PLL support external 12 MHz crystal / Oscillator clock input
Optional 27/48 MHz Oscillator clock input (Only available in LQFP48/ LQFN46 package)
Support compound-device (non-removable in downstream ports) by I/O pin configuration (Only available
in LQFP48/ LQFN46 package)
Number of Downstream port can be configured by GPIO without external EEPROM (Only available in
LQFP48/ LQFN46 package)
Built-in 5V to 3.3V regulator
Improve output drivers with slew-rate control for EMI reduction
Internal power-fail detection for ESD recovery
Available package types: 48 pin LQFP, 28 pin QFN, 28 pin SSOP and 46 pin LQFN
Applications:
Stand-alone USB hub / USB docking
UMPC/MID, motherboard on-board applications
Consumer electronics built-in hub application
Monitor built-in hub
Embedded systems
Compound device to support USB hub function such as keyboard hub applications
DM0,DP0 3,4 1,2 25,26 2,3 B USB signals for USPORT
DM1,DP1 5,6 3,4 27,28 4,5 B USB signals for DSPORT1
DM2,DP2 9,10 6,7 2,3 7,8 B USB signals for DSPORT2
DM3,DP3 17,18 12,13 8,9 15,16B USB signals for DSPORT3
DM4,DP4 21,22 15,16 11,12 18,19B USB signals for DSPORT4
RREF 11 8 4 9 A
A 680Ω resister must be connected between RREF
and analog ground (AGND).
Note: USB signals must be carefully handled in PCB routing. For detailed information, please refer to
GL85X Design Guide.
Hub Interface
GL852G
Pin Name
OVCUR1#~4
PWREN1#~4
GREEN1~4
AMBER1~4
LQFP
48 Pin
42,40,
30,28
43,41,
31,29
45,35,
32,23
46,36,
33,24
QFN
28 Pin
25,24,
20,19
SSOP
28 Pin
21,19
- 22,20
- -
- -
LQFN
46 Pin
40,38,
29,27I (pu)
41,39,
30,28
43,34,
31,20
44,35,
32,21O (pd)
PSELF 37 22 17 36 I
I/O
Type
O
1,3,4: O
2: B
(pd)
Description
Active low. Over current indicator for DSPORT1~4
OVCUR1# is the only over current flag for GANG
mode.
Active low. Power enable output for DSPORT1~4
PWREN1# is the only power-enable output for
GANG mode.
Green LED indicator for DSPORT1~4
*GREEN[1~2] are also used to access the external
EEPROM
For detailed information, please refer to Chapter 5.
Amber LED indicator for DSPORT1~4
*Amber [1~2] are also used to access the external
EEPROM
0: GL852G is bus-powered.
1: GL852G is self-powered.
This pin is default put in input mode after power-on
reset. Individual/gang mode is strapped during this
period. After the strapping period, this pin will be
set to output mode, and then output high for normal
mode.
PGANG 39 23 18 37 B
When GL852G is suspended, this pin will output low.
*For detailed explanation, please see Chapter 5
Gang input:1, output: 0@normal,
USPORT (upstream port) transceiver is the analog circuit that supports both full-speed and high-speed
electrical characteristics defined in chapter 7 of USB specification Revision 2.0. USPORT transceiver will
operate in full-speed electrical signaling when GL852G is plugged into a 1.1 host/hub. USPORT transceiver
will operate in high-speed electrical signaling when GL852G is plugged into a 2.0 host/hub.
5.1.2 PLL (Phase Lock Loop)
GL852G contains a 40x PLL. PLL generates the clock sources for the whole chip. The generated clocks are
proven quite accurate that help in generating high speed signal without jitter.
5.1.3 FRTIMER
This module implements hub (micro)frame timer. The (micro)frame timer is derived from the hub’s local
clock and is synchronized to the host (micro)frame period by the host generated Start of (micro)frame (SOF).
FRTIMER keeps tracking the host’s SOF such that GL852G is always safely synchronized to the host. The
functionality of FRTIMER is described in section 11.2 of USB Specification Revision 2.0.
5.1.4 μC
μC is the micro-processor unit of GL852G. It is an 8-bit RISC processor with 2K ROM and 64 bytes RAM. It
operates at 6MIPS of 12 MHz clock to decode the USB command issued from host and then prepares the
data to respond to the host. In addition, μC can handle GPIO (general purpose I/O) settings and reading
content of EEPROM to support high flexibility for customers of different configurations of hub. These
configurations include self/bus power mode setting, individual/gang mode setting, downstream port number
setting, device removable/non-removable setting, and PID/VID setting.
UTMI handles the low level USB protocol and signaling. It’s designed based on the Intel’s UTMI
specification 1.01. The major functions of UTMI logic are to handle the data and clock recovery, NRZI
encoding/decoding, Bit stuffing /de-stuffing, supporting USB 2.0 test modes, and serial/parallel conversion.
5.1.6 USPORT Logic
USPORT implements the upstream port logic defined in section 11.6 of USB specification Revision 2.0. It
mainly manipulates traffics in the upstream direction. The main functions include the state machines of
Receiver and Transmitter, interfaces between UTMI and SIE, and traffic control to/from the REPEATER and
TT.
5.1.7 SIE (Serial Interface Engine)
SIE handles the USB protocol defined in chapter 8 of USB specification Revision 2.0. It co-works with μC
to play the role of the hub kernel. The main functions of SIE include the state machine of USB protocol flow,
CRC check, PID error check, and timeout check. Unlike USB 1.1, bit stuffing/de-stuffing is implemented in
UTMI, not in SIE.
5.1.8 Control/Status Register
Control/Status register is the interface register between hardware and firmware. This register contains the
information necessary to control endpoint0 and endpoint1 pipelines. Through the firmware based
architecture, GL852G possesses higher flexibility to control the USB protocol easily and correctly.
Repeater logic implements the control logic defined in section 11.4 and section 11.7 of USB specification
Revision 2.0. REPEATER controls the traffic flow when upstream port and downstream port are signaling in
the same speed. In addition, REPEATER will generate internal resume signal whenever a wakeup event is
issued under the situation that hub is globally suspended.
5.1.10 TT (Transaction Translator)
TT implements the control logic defined in section 11.14 ~ 11.22 of USB specification Revision 2.0. TT
basically handles the unbalanced traffic speed between the USPORT (operating in HS) and DSPORTS
(operating in FS/LS) of hub. GL852G adopts multiple TT architecture to provide the most performance
effective solution. Multiple TT provides control logics for each downstream port respectively.
5.1.11 REPEATER/TT Routing Logic
REPEATER and TT are the major traffic control machines in the USB 2.0 hub. Under situation that USPORT
and DSPORT are signaling in the same speed, REPEATER/TT routing logic switches the traffic channel to
the REPEATER. Under situation that USPORT is in the high speed signaling and DSPORT is in the full/low
speed signaling, REPEATER/TT routing logic switches the traffic channel to the TT.
5.1.11.1 Connected to 1.1 Host/Hub
If an USB 2.0 hub is connected to the downstream port of an USB 1.1 host/hub, it will operate in USB 1.1
mode. For an USB 1.1 hub, both upstream direction traffic and downstream direction traffic are passing
through REPEATER. That is, the REPEATER/TT routing logic will route the traffic channel to the
REPEATER.
If an USB 2.0 hub is connected to an USB 2.0 host/hub, it will operate in USB 2.0 mode. The upstream port
signaling is in high speed with bandwidth of 480 Mbps under this environment. The traffic channel will
then be routed to the REPEATER when the device connected to the downstream port is signaling also in
high speed. On the other hand, the traffic channel will then be routed to TT when the device connected to
the downstream port is signaling in full/low speed.
USB 2.0 HOST/HUB
USPORToperating
in HS signaling
HS vs. HS:
Traffic channel is
routed to REPEATER
REPEATER
TT
TT
HS vs. FS/LS:
Traffic channel
is routed to TT
DSPORT operating
in HS signaling
DSPORT operating
in FS/LS signaling
Figure 5.2 - Operating in USB 2.0 Schemes
5.1.12 DSPORT Logic
DSPORT (downstream port) logic implements the control logic defined in section 11.5 of USB specification
Revision 2.0. It mainly manipulates the state machine, the connection/disconnection detection, over current
detection and power enable control, and the status LED control of the downstream port. Besides, it also
output the control signals to the DSPORT transceiver.
5.1.13 DSPORT Transceiver
DSPORT transceiver is the analog circuit that supports high-speed, full-speed, and low-speed electrical
characteristics defined in chapter 7 of USB specification Revision 2.0. In addition, each DSPORT transceiver
accurately controls its own squelch level to detect the detachment and attachment of devices.
GL852G’s power on reset can either be triggered by external reset or internal power good reset circuit. The
external reset pin, RESETJ, is connected to upstream port Vbus (5V) to sense the USB plug / unplug or 5V
voltage drop. The reset trigger voltage can be set by adjusting the value of resistor R1 and R2 (Suggested
value refers to schematics) GL852G’s internal reset is designed to monitor silicon’s internal core power
(3.3V) and initiate reset when unstable power event occurs. The power on sequence will start after the power
good voltage has been met, and the reset will be released after approximately 2.7 μS after power good.
GL852G’s reset circuit as depicted in the picture
Silicon
Ext. VBUS power-good
detection circuit input
(Pin"RESET#")
EXT
INT
Int. 3.3V power-good
detection circuit input
(USB PHY reset)
Global
Reset#
V
BUS
(External 5V)
PCB
R1
R2
Figure 5.3 - Power on Reset Diagram
To fully control the reset process of GL852G, we suggest the reset time applied in the external reset circuit
should longer than that of the internal reset circuit. Timing of POR is illustrated as below figure.
To save pin count, GL852G uses the same pin to decide individual/gang mode as well as to output the
suspend flag. The individual/gang mode is decided within 20us after power on reset. Then, about 50ms later,
this pin is changed to output mode. GL852G outputs the suspend flag once it is globally suspended. For
individual mode, a pull low resister greater than 100KΩ should be placed. For gang mode, a pull high
resister which greater than 100KΩ should be placed. In figure 5.6, we also depict the suspend LED indicator
schematics. It should be noticed that the polarity of LED must be followed, otherwise the suspend current
will be over spec limitation (2.5mA).
GL852G can operate under bus power and conform to the power consumption limitation completely
(suspend current < 2.5 mA, normal operation current < 100 mA). By setting PSELF, GL852G can be
configured as a bus-power or a self-power hub.
1: Power Self
0: Power Bus
Inside GL852G
PSELF
On PCB
Figure 5.7 - SELF/BUS Power Setting
5.2.4 LED Connections
GL852G controls the LED lighting according to the flow defined in section 11.5.3 of Universal Serial Bus
Specification Revision2.0. Both manual mode and Automatic mode are supported in GL852G. When
GL852G is globally suspended, GL852G will turn off the LED to save power.
GL852G replies to host commands by the default settings in the internal ROM. GL852G also offers the
ability to reply to the host according to the settings in the external EEPROM (LQFP48/LQFN46 supports
both 93C46 and 24C02; QFN28 only supports 24C02). And to prevent the content of EEPROM from being
over-written, amber LED will be disabled when EEPROM exists. The detail setting information please refers
to the GL852G AP Note_EEPROM Info document.
The schematics between GL852G and 93C46 are depicted in the following figures:
Figure 5.9 - Schematics between GL852G and 93C46
GL852G firstly verifies the check sum after power on reset. If the check sum is correct, GL852G will take
the configuration of 93C46 as part of the descriptor contents. To prevent the content of 93C46 from being
over-written, amber LED will be disabled when 93C46 exists.
5.2.6 Power Switch Enable Polarity (Only Available for LQFP48/LQFN46 Package)
Both low/high-enabled power switches are supported. It is determined by jumper setting, based on the state
of pin AMBER2, as the following table:
Table 5.1 - Configuration by Power Switch Type
AMBER2 Power Switch Enable Polarity
0 Low-active
1 High-active
5.2.7 Port Number Configuration (Only Available for LQFP48/LQFN46 Package)
Number of downstream port can be configured as 2/3/4 ports by pin strapping in addition to EEPROM,
based on the state of pin AMBER 3, AMBER 4, as the following table:
5.2.8 Non-removable Port Configuration (Only Available for LQFP48/LQFN46 Package)
For compound application or embedded system, downstream ports that always connected inside the system
can be set as non-removable based on the state of corresponding status LED, pin GREEN 1~4. If the pin is
pull high in the initial stage (POR reset), the corresponding port will be set as non-removable. (Feature
Limitation: Green 1 & Green 2 pull-high concurrently will enable GL852G vendor proprietary function that
may affect system compatibility. System integrator should evade configuring both port #1 and #2 as
non-removable by this strapping feature)
5.2.9 Reference Clock Configuration (Only Available for LQFP48/LQFN46 Package)
GL852G can support optional 27/48MHz clock source, which is selectable through GPIO configurations.
For some on-board design that 27/48MHz clock source is available, such as motherboard or Monitor built-in
applications, system integrator can leverage this feature to further reduce BOM cost by removing external
crystal.
Test result represents silicon level operating current, without considering additional power
consumption contributed by external over-current protection circuit such as power switch or
polyfuse.
6.5 AC Characteristics
GL852G LQFP 48/LQFN46 pin package can support both 93C46 & 24C02 type EEPROM for customized
VID/PID. GL852G QFN28/SSOP28 pin package can only support 24C02 type EEPROM. AC characteristics
of these two types of EEPROM summarized as below figures and tables.
GL852G requires 3.3V source power for normal operation of internal core logic and USB physical layer
(PHY). The integrated low-drop power regulator converts 5V power input from USB cable (Vbus) to 3.3V
voltage for silicon power source. The 3.3V power output is guaranteed by an internal voltage reference
circuit to prevent unstable 5V power compromise USB data integrity. The regulator’s maximum current
loading is 200mA, which provides enough tolerance for normal GL852G operation (below 100mA).
On-chip Power Regulator Features:
5V to 3.3V low-drop power regulator
200mA maximum output driving capability
Provide stable 3.3V output when Vin = 3.4V~5.5V
Max. suspend current:190uA; typical suspend current 164uA
Figure 6.1 - Vin(V5) vs Vout(V33)*
*Note: Measured environment: Ambient temperature = 25℃ / Current Loading = 200mA