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GL813 -
Genesys Logic, Inc.
USB 2.0 CompactFlash Card Reader
Controller
Specification 1.2
pril 12, 2002
Genesys Logic, Inc.
10F., No.11, Ln.155, Sec.3, Peishen Rd., Shenkeng, Taipei, Taiwan
Tel: 886-2-2664-6655 Fax: 886-2-2664-5757
http://www.genesyslogic.com
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GL813 - USB2.0 CompactFlash Card Reader Controller
Contents
1. General Description.........................................................................................3
2. Features............................................................................................................4
3. Function Block.................................................................................................5
3.1 Block Diagram..............................................................................................5
3.2 Functional Overview.....................................................................................6
4. Pinning Information.........................................................................................7
4.1 48-pin LQFP Package..................................................................................7
4.2 100-pin LQFP package.................................................................................9
5. Functional Description..................................................................................15
5.1 Transmit Operation .....................................................................................15
5.2 Receive Operation......................................................................................17
6. Electrical Characteristics..............................................................................19
6.1 Absolute Maximum Ratings........................................................................19
6.2 Recommended Operating Conditions.........................................................19
6.3 DC Characteristics (Digital Pins) ................................................................19
6.4 DC Characteristics (D+/D-).........................................................................20
6.5 Switching Characteristics ...........................................................................20
7. Package Dimension.......................................................................................22
7.1 48-pin LQFP Package................................................................................22
7.2 100-pin LQFP Package..............................................................................23
8. Revision History.............................................................................................24
©2001-2002 Genesys Logic Inc.—All rights reserved. Page 2 of 24
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GL813 - USB2.0 CompactFlash Card Reader Controller
1. General Description
The GL813 is a high performance, low cost USB2.0 CompactFlash-single card
reader controller. With the integration of GenesysLogic own design USB 2.0 high
speed UTMI transceiver, the GL813 has made a conspicuous improvement with
full speed USB 1.1 card readers on data transfer rate between PC host and flash
memory card.
There are totally 4 endpoints in GL813 controller, Control, Bulk In, Bulk Out, and
Interrupt. Complies with USB 480Mbps specification ver. 2.0 and USB Storage
Class specification ver. 1.0. (Bulk only protocol), the GL813 can support not only
plug and play but also Windows ME/ 2000/ XP default driver. For the EMI
consideration, the GL813 uses 12MHZ crystal and slew-rate controlled pads to
reduce the EMI issue.
The GL813 is 48-pin LQFP package (9mmX9mm) to make the best cost
competitive for the high speed single flash card reader design and applications.
Also we provide 100-pin LQFP package (14mmX14mm) with external ROM/ Flash
for design flexibility.
©2001-2002 Genesys Logic Inc.—All rights reserved. Page 3 of 24
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GL813 - USB2.0 CompactFlash Card Reader Controller
2. Features
Complies with Universal Serial Bus specification rev. 2.0.
Complies with Compact Flash specification rev. 1.4.
Complies with USB Storage Class specification ver.1.0. (Bulk only protocol)
Operating system supported: Win XP/ 2000/ ME/ 98/ 98SE; Mac OS 9.X/ X.
Supports 4 endpoints: Control/ Bulk Read/ Bulk Write/ Interrupt.
64/ 512 bytes Data Payload for full / high speed Bulk Endpoint.
Supports 8-bit / 16-bit Standard PIO mode interface.
Embedded USB 2.0 UTMI transceiver.
Embedded 7.5 MIPS RISC CPU.
Supports external ROM/ Flash modes for design flexibility. (100-pin LQFP)
Supports Power Down mode and USB suspend indicator.
Supports USB 2.0 TEST mode features.
12MHz external clock to provide better EMI3.3V power input.
5V tolerance pad for Compact Flash Card interface.
Supports EEPROM to customize USB VID / PID and String Descriptors.
Available in 48-pin (9mmX9mm) / 100-pin (14mmX14mm) LQFP package.
©2001-2002 Genesys Logic Inc.—All rights reserved. Page 4 of 24
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GL813 - USB2.0 CompactFlash Card Reader Controller
3. Function Block
3.1 Block Diagram
CPU Control Register
12MHz
X40
Compact
Flash
Controller
Engine
Clkgen
CONTROL FIFO
TXFIFO0
TXFIFO1
RXFIFO0
RXFIFO1
SIE
UTMI
LOGIC
USB2.0
TXCVR
©2001-2002 Genesys Logic Inc.—All rights reserved. Page 5 of 24
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GL813 - USB2.0 CompactFlash Card Reader Controller
3.2 Functional Overview
3.2.1 USB 2.0 TXCVR
The USB 2.0 Transceiver is the analog circuitry to handle the USB HS/FS
signaling.
3.2.2 UTMI Logic
The UTMI Logic is compliant to Intel’s UTMI specification 1.01. This block handles
the low level USB protocol and signaling. The major jobs of UTMI Logic is data and
clock recovery, NRZI encoding/decoding, Bit Stuffing/De-stuffing, USB2.0 test
modes supporting and serial / parallel conversion.
3.2.3 PLL
40XPLL block will provide 480MHz for USB HS data transmission.
3.2.4 CLKGEN
CLKGEN is the clock generator block for the logic blocks. It generates 15MHz
clock for micro controller, 12MHz for PIO mode, and 30MHz clock for UTMI, SIE,
and FIFO.
3.2.5 CPU
The CPU is the control center of GL813. It’s an 8-bit micro controller operating in
15MHz, 7.5 MIPS. After receiving a USB command, it decodes the host command,
then it re-assigns tasks to the CompactFlash controller engine, GPIO, FIFO, and
response proper data/ status to USB host.
3.2.6 CompactFlash Controller Engine
The CompactFlash controller engine is extended from standard ATA/ ATAPI
protocol. It supports PIO mode data transfers.
3.2.7 FIFOs
Control FIFO is used as Control Read / Write FIFO. TXFIFO0 / TXFIFO1 are two
sets of 512-byte ping-pong FIFO for Bulk Read endpoint. It buffers data from
CompactFlash controller engine, and re-direct to USB SIE logic. RXFIFO0 /
RXFIFO1 are two sets of 512-byte ping-pong FIFO for Bulk Write endpoint. It
buffers data from USB SIE logic, and re-direct to CompactFlash controller engine.
3.2.8 Control Registers
Control Register configures GL813 to proper operation. For example, CPU can set
register to generate wakeup event, enter suspend, transmits proper USB packet to
host.
©2001-2002 Genesys Logic Inc.—All rights reserved. Page 6 of 24
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GL813 - USB2.0 CompactFlash Card Reader Controller
4. Pinning Information
4.1 48-pin LQFP
CFRST
CS
IODD[7]
IODD[6]
IODD[5]
IODD[4]
DVCC2
DGND2
IODD[3]
IODD[2]
IODD[1]
38
23
IODD[0]
37
36
35
34
33
32
31
30
29
28
27
26
25
24
DIOW_
DIOR_
IORDY
INTRQ
DA1/ Dl
DA0
CS0_
TEST
CFDET
GND1
X1
X2
CFPWR
IODD[8]
IODD[9]
IODD[10]
IODD[11]
IODD[12]
IODD[13]
IODD[14]
!ODD[15]
DVCC1
DGND1
DO
1
2
3
4
5
6
7
8
9
10
11
12
48
47
46
45
44
43
42
41
40
39
GL813
48 LQFP
13
14
15
16
17
18
19
20
21
22
CS1
DA2/ S
RPU
RESET#
AVCC0
DPF
DPH
DMF
DMH
RREF
AGND0
AVCC1
Pin # Name I/O Pad Type Description
1
CFPWR
2~5
8~11
12
13
IODD [8:11]
6
DVCC1
7
DGND1
IODD [12:15]
DO
CS1_
©2001-2002 Genesys Logic Inc.—All rights reserved. Page 7 of 24
B Tri-state Compact flash card power control
I Tri-state IDE data bus 8~11
P Power Digital VCC
P Power Digital ground
B Tri-state IDE data bus 12~15
I Tri-state DO from EEPROM
O Tri-state IDE chip select 1
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GL813 - USB2.0 CompactFlash Card Reader Controller
Pin # Name I/O Pad Type Description
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37~40
41
42
3~46
47
DA2 / SK
RESET#
RPU
AVCC0
DPF
DPH
DMF
DMH
AGND0
RREF
AVCC1
X2
X1
AGND1
CFDET
TEST
CS0_
DA0
DA1 / DI
INTRQ
IORDY
DIOR_
DIOW_
IODD [0:3]
DGND2
DVCC2
IODD [4:7]
CS
O Tri-state IDE address 2 / SK to EEPROM
I Pull-high HW reset
A U20mia 3.3v output
P Power Analog VCC
B U20mia Full speed DP
B U20mia High speed DP
B U20mia Full speed DM
B U20mia High speed DM
P Power Analog ground
U20mia Reference resister connect (*)
P Power Analog VCC
B Clock Crystal output
I Clock Crystal input, 12Mhz
P Power Analog ground
I Tri-state Compact flash card detect
I Pull-low TEST mode input
O Tri-state IDE Chip select 0
O Tri-state IDE address 0
O Tri-state IDE address 1 / DI to EEPROM
I Tri-state IDE Interrupt request
I Tri-state IDE IO ready
O Tri-state IDE read signal
O Tri-state IDE write signal
B Tri-state IDE data bus 0~3
P Power Digital ground
P Power Digital VCC
B Tri-state IDE data bus 4~7
O Tri-state CS to EEPROM
48
CFRST
B Tri-state Compact Flash Card HW reset
(*) RREF must be connected with a 510 ohm resister to ground.
©2001-2002 Genesys Logic Inc.—All rights reserved. Page 8 of 24
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GL813 - USB2.0 CompactFlash Card Reader Controller
4.2 100-pin LQFP
GPIO7
GPIO4
GPIO3
GPIO2
GPIO1
IODD7
IODD6
IODD5
IODD4
DVCC2
DGND2
IODD3
IODD2
IODD1
IODD0
DMARQ
GPIO9
GPIO10
GPIO11
GPIO12
NC
NC
NC
NC
9998979695949392919089888786858483828180797877
100
1
NC
2
NC
3
NC
4
NC
5
GPIO8
6
GPIO5
7
GPIO6
8
IODD8
9
IODD9
DVCC1
NC
NC
DGND1
EXT0
EXT1
EXT2
EXT3
EXT4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26272829303132333435363738394041424344454647484950
GL813
100 LQFP
IODD10
IODD11
IODD12
IODD13
IODD14
IODD15
CBLID
DIOW_
76
NC
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DIOR_
IORDY
DMACK_
INTRQ
GPIO13
GPIO14
GPIO15
GPIO16
DA1
DA0
CS0_
GPIO17
GPIO18
GPIO19
EXT15
EXT14
NC
GND1
X1
X2
NC
NC
NC
NC
NCNCNC
EXT5
NC
EXT6
EXT7
EXT8
EXT9
EXT11
EXT10
EXT12
EXT13
DA2
CS1
RPU
RESET#
AVCC0
DPF
DPH
DMF
DMH
RREF
AVCC1
AGND0
©2001-2002 Genesys Logic Inc.—All rights reserved. Page 9 of 24
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GL813 - USB2.0 CompactFlash Card Reader Controller
Pin # Name I/O Pad Type Description
1
2
3
4
5
6
7
8~11
12
13
14
15
16~19
20
21
22
23
24
25
NC
NC
NC
NC
GPIO8
GPIO5
GPIO6
IODD [8:11]
DVCC1
NC
NC
DGND1
IODD [12:15]
CBLID_
NC/ECPURD/EROMD0
NC/ECPUWR/EROMD1
NC/ECPUA5/EROMD2
NC/ECPUA4/EROMD3
NC/ECPUA3/EROMD4
- - -
- - -
- - -
- - B Tri-state GPIO8 (*)
B Tri-state GPIO5
B Tri-state GPIO6
B Tri-state IDE data bus 8 ~ 11
P Power Digital VCC
- - -
- - P Power Digital ground
B Tri-state IDE data bus 12 ~ 15
I Tri-state Cable select input
NC: Embedded CPU mode
ECPURD: Read signal when
I Pull-low
external CPU mode
EROMD0: Data0 when external
ROM mode
NC: Embedded CPU mode
ECPUWR: Write signal when
I Pull-low
external CPU mode
EROMD1: Data1 when external
ROM mode
NC: Embedded CPU mode
ECPUA5: Address5 when external
I Pull-low
CPU mode
EROMD2: Data2 when external
ROM mode
NC: when embedded CPU mode
ECPUA4: Address4 when external
I Pull-low
CPU mode
EROMD3: Data3 when external
ROM mode
NC: Embedded CPU mode
ECPUA3: Address3 when external
I Pull-low
CPU mode
EROMD4: Data4 when external
ROM mode
©2001-2002 Genesys Logic Inc.—All rights reserved. Page 10 of 24
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GL813 - USB2.0 CompactFlash Card Reader Controller
Pin # Name I/O Pad Type Description
NC: Embedded CPU mode
ECPUA2: Address2 when external
26
27
28
29
30
31
32
33
34
35
36
37
NC/ECPUA2/EROMD5
NC
NC
NC
NC
NC/ECPUA1/EROMD6
NC/ECPUA0/EROMD7
NC/ECPUD7/EROMD8
NC/ECPUD6/EROMD9
NC/ECPUD5/EROMD10
NC/ECPUD4/EROMD11
NC/ECPUD3/EROMD12
I Pull-low
CPU mode
EROMD5: Data5 when external
ROM mode
- - -
- - -
- - -
- - -
NC: Embedded CPU mode
ECPUA1: Address1 when external
I Pull-low
CPU mode
EROMD6: Data6 when external
ROM mode
NC: Embedded CPU mode
ECPUA0: Address0 when external
I Pull-low
CPU mode
EROMD7: Data7 when external
ROM mode
NC: Embedded CPU mode
ECPUD7: Data7 when external
B Pull-low
CPU mode
EROMD8: Data8 when external
ROM mode
NC: Embedded CPU mode
ECPUD6: Data6 when external
B Pull-low
CPU mode
EROMD9: Data9 when external
ROM mode
NC: Embedded CPU mode
ECPUD5: Data5 when external
B Pull-low
CPU mode
EROMD10: Data10 when external
ROM mode
NC: Embedded CPU mode
ECPUD4: Data4 when external
B Pull-low
CPU mode
EROMD11: Data11 when external
ROM mode
NC: Embedded CPU mode
ECPUD3: Data3 when external
B Pull-low
CPU mode
EROMD12: Data12 when external
ROM mode
©2001-2002 Genesys Logic Inc.—All rights reserved. Page 11 of 24
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GL813 - USB2.0 CompactFlash Card Reader Controller
Pin # Name I/O Pad Type Description
NC: Embedded CPU mode
ECPUD2: Data2 when external
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
NC/ECPUD2/EROMD13
CS1_
DA2
RESET#
RPU
AVCC0
DPF
DPH
DMF
DMH
AGND0
RREF
AVCC1
NC
NC
NC
NC
X2
X1
AGND1
NC
NC/ECPUD1/EROMA0
NC/ECPUD0/EROMA1
GPIO19
GPIO18/GPIO18/EROM
A11
B Pull-low
CPU mode
EROMD13: Data13 when external
ROM mode
O Tri-state Chip select 1
O Tri-state IDE address 2
I Pull-high Reset pin
A U20mia 3.3v output
P Power Analog VCC
B U20mia Full speed DP
B U20mia High speed DP
B U20mia Full speed DM
B U20mia High speed DM
P Power Analog ground
U20mia Reference resister connect (*)
P Power Analog VCC
- - -
- - -
- - -
- - -
B Clock Crystal output
I Clock Crystal input, 12Mhz
P Power Analog ground
- - NC: Embedded CPU mode
ECPUD1: Data1 when external
B Pull-low
CPU mode
EROMA0: Address0 when external
ROM mode
NC: Embedded CPU mode
ECPUD0: Data0 when external
B Pull-low
CPU mode
EROMA1: Address1 when external
ROM mode
B Pull-low
GPIO19
GPIO18: for embedded or external
B Pull-low
CPU mode
EROMA11: Address11 when
external ROM mode
©2001-2002 Genesys Logic Inc.—All rights reserved. Page 12 of 24
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GL813 - USB2.0 CompactFlash Card Reader Controller
Pin # Name I/O Pad Type Description
GPIO17: For embedded or external
63
GPIO17/GPIO17/EROM
A10
B Pull-low
CPU mode
EROMA10: Address10 when
external ROM mode
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
CS0_
DA0
DA1
GPIO16/GPIO16/EROM
A9
GPIO15/GPIO15/EROM
A8
GPIO14/GPIO15/EROM
A7
GPIO13/GPIO14/EROM
A6
INTRQ
DMACK_
IORDY
DIOR_
NC
DIOW_
NC
NC
NC
NC
GPIO12/GPIO13/EROM
A5
GPIO11/GPIO12/EROM
A4
O Tri-state Chip select 0
O Tri-state IDE address 0
O Tri-state IDE address 1
GPIO16: For embedded or external
B Pull-low
CPU mode
EROMA9: Address9 when external
ROM mode
GPIO15: For embedded or external
B Pull-low
CPU mode
EROMA8: Address8 when external
ROM mode
GPIO14: For embedded or external
B Pull-low
CPU mode
EROMA7: Address7 when external
ROM mode
GPIO13: For embedded or external
B Pull-low
CPU mode
EROMA6: Address6 when external
ROM mode
I Tri-state IDE interrupt input
O Tri-state IDE acknowledge
I Pull-high IDE ready
O Tri-state IDE read signal
- - -
O Tri-state IDE write signal
- - -
- - -
- - -
- - GPIO12: For embedded or external
B Pull-low
CPU mode
EROMA5: Address5 when external
ROM mode
GPIO11: For embedded or external
B Pull-low
CPU mode
EROMA4: Address4 when external
ROM mode
©2001-2002 Genesys Logic Inc.—All rights reserved. Page 13 of 24
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GL813 - USB2.0 CompactFlash Card Reader Controller
Pin # Name I/O Pad Type Description
GPIO10: For embedded or external
83
84
85
6~89
90
91
92~95
96
97
98
99
100
GPIO10/GPIO10/EROM
A3
GPIO9/GPIO9/EROMA2
DMARQ
IDEDD [0:3]
DGND2
DVCC2
IDEDD [4:7]
GPIO1
GPIO2
GPIO3
GPIO4
GPIO7
B Pull-low
B Pull-low
I Pull-low
B Tri-state
P Power
P Power
B Tri-state
B Pull-high
B Pull-high
B Pull-high
B Pull-low
B Pull-low
CPU mode
EROMA3: Address3 when external
ROM mode
GPIO9: For embedded or external
CPU mode
EROMA2: Address2 when external
ROM mode
IDE request
IDE data bus 0~3
Digital ground
Digital VCC
IDE data bus 4~7
GPIO1
GPIO2
GPIO3
GPIO4
GPIO 7 (*)
(*) When operating in default mode: GPIO7 is the IDE reset input, GPIO8 is used to
control the power input of IDE device.
©2001-2002 Genesys Logic Inc.—All rights reserved. Page 14 of 24
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GL813 - USB2.0 CompactFlash Card Reader Controller
5. Functional Description
5.1 Transmit Operation
5.1.1 Transmit State Diagram
!TXVLD
HRST# !HRST#
Reset
TX Wait
!TXRDY
Send SYNC
TXVLD
TX Hold
Reg Empty
TX Hold
Reg Full
TX Data Wait
!TXRDY
TX Data Load
TXRDY
TX Hold
Reg Empty
TX Hold
Reg Full
!TXVLD
EOP not
done
Send EOP
!TXRDY
Transmit must be asserted to enable any transmissions.
The SIE asserts TXVLD to begin a transmission.
The SIE negates TXVLD to end a transmission.
After the SIE asserts TXVLD it can assume that the transmission has started when it
detects TXRDY asserted.
The SIE assumes that the UTM has consumed a data byte if TXRDY and TXVLD are
asserted.
The SIE must have valid packet information (PID) asserted on the Data bus
coincident with the assertion of TXVLD. Depending on the UTM implementation,
TXRDY may be asserted by the Transmit State Machine as soon as one CLK after
the assertion of TXVLD.
TXVLD and TXRDY are sampled on the rising edge of CLKOUT.
The Transmit State Machine does not automatically generate Packet ID’s (PIDs) or
©2001-2002 Genesys Logic Inc.—All rights reserved. Page 15 of 24
Page 16
a
SYNC
a
CRC
CRCEO
GL813 - USB2.0 CompactFlash Card Reader Controller
CRC. When transmitting, the SIE is always expected to present a PID as the first
byte of the data stream and if appropriate, CRC as the last bytes of the data stream.
The SIE must use LINEST0/1 to verify a Bus Idle condition before asserting TXVLD
in the TX Wait state.
5.1.2 Transmit Timing for Data Packet
CLKOUT
TXVLD
Data
TXRDY
PID
DataDataDataDat
CRCCRC
DP/DM
PID DataDataDataDat
P
The SIE negates TXVLD to complete a packet. Once negated, the Transmit State
Machine will never reassert TXRDY until after the EOP has been loaded into the Transmit
Shift Register. Note that the UTM Transmit State Machine can be ready to start another
package immediately, however the SIE must confirm to the minimum inter-packet delays
identified in the USB 2.0 Specification.
©2001-2002 Genesys Logic Inc.—All rights reserved. Page 16 of 24
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GL813 - USB2.0 CompactFlash Card Reader Controller
5.2 Receive Operation
5.2.1 Receive State Diagram
!SYNC
HRST#
Reset
!RXACTV
!RXVLD
SYNC Detected
Trip SYNC
RXACTV
SYNC
!HRST#
Data
!Data
RX Data Wait
Data
Rx Data
RXVLD
Data
!RXVLD
RX Wait
EOP
Detected
Receive
Error
!Data
Strip EOP
!RXACTV
!RXVLD
Abort 1
!RXACTV
!RXVLD
!RXERR
Error
RXERR
!Idle
state
RXACTV and RXVLD are sampled on the rising edge of CLKOUT.
Terminate
!RXACTV
Idle
state
Abort 2
!RXVLD
!RXERR
In the RX Wait state the receiver is always looking for SYNC.
The Macrocell asserts RXACTV when SYNC is detected (Strip SYNC state).
The Macrocell negates RXACTV when an EOP is detected (Strip EOP state).
When RXACTV is asserted, RXVLD will be asserted if the RX Holding Register is
full.
RXVLD will be negated if the RX Holding Register was not loaded during the
previous byte time. This will occur if 8 stuffed bits have been accumulated.
The SIE must be ready to consume a data byte if RXACTV and RXVLD are asserted
(RX Data state).
In FS mode, if a bit stuff error is detected then the Receive State Machine will negate
RXACTV and RXVLD, and return to the RXWait state.
©2001-2002 Genesys Logic Inc.—All rights reserved. Page 17 of 24
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GL813 - USB2.0 CompactFlash Card Reader Controller
5.2.2 Receive Timing for Data Packet (with CRC-16)
CLKOUT
RXACTV
Data
Data
Data Data Data CRC CRC PID
RXVLD
RXERR
DP/DM
SYNC PID Data Data Data
Data
CRC CRC EOP
Note that the USB 2.0 transceiver does not decode Packet ID’s (PIDs). They are passed
to the SIE for decoding.
This timing example is in HS mode. When a HS/FS UTM is in FS mode there are
approximately 40 clock cycles every byte time. The Receive State Machine assumes that
the SIE captures the data on the data bus if RXACTV and RXVLD are asserted. In FS
mode, RXVLD will only be asserted for one clock per byte time.
Note that the receive and transmit sections of the transceiver operate independently. The
receiver will receive any packets on the USB. The transceiver does not identify whether
the packet that it is receiving from the upstream or the downstream port. The SIE must
ignore receive data while it is transmitting.
©2001-2002 Genesys Logic Inc.—All rights reserved. Page 18 of 24
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GL813 - USB2.0 CompactFlash Card Reader Controller
6. Electrical Characteristics
6.1 Absolute Maximum Ratings
Symbol Description Min Max Unit
VCC DC supply voltage -0.3 +3.6 V
VI DC input voltage -0.3 V
V
DC input voltage range for I/O -0.3 V
I/O
V
DC input voltage for USB D+/D- pins -0.3 V
AI/O
V
DC voltage applied to outputs in High Z state -0.3 V
I/OZ
V
S tatic discharge voltage 4000 V
ESD
CC
CC
CC
CC
TA Ambient Temperature 0 100 oC
6.2 Recommended Operating Conditions
Item Value
Supply Volt age +3.3V to + 3.6V
Ground Voltage 0V
F
osc
12 MHz ± 100 ppm
Operating Temperature 0 oC ~ 70 oC
+ 0.3 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
6.3 DC Characteristics (Digital Pins)
Symbol Description Min Typ Max Unit
PD Power Dissipation mA
VDD Power Supply Voltage 3 3.3 3.6 V
IO
DC output sink current excluding D+/ D-/
VCC/ GND
8 mA
VIL LOW level input voltage 0.9 V
VIH HIGH level input voltage 2.0 V
V
LOW to HIGH threshold voltage 1.3 1.43 1.56 V
TLH
V
HIGH to LOW threshold voltage 1.3 1.43 1.56 V
THL
©2001-2002 Genesys Logic Inc.—All rights reserved. Page 19 of 24
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GL813 - USB2.0 CompactFlash Card Reader Controller
Symbol Description Min Typ Max Unit
V
Hysteresis voltage - 0 - V
HYS
VOL LOW level output voltage when IOL=8mA 0.4 V
VOH HIGH level output voltage when IOH=8mA 2.4 V
I
OLK
Leakage current for pads with internal pull
up or pull down resistor
46
µA
RDN Pad internal pull down resister 79K 105K 152K Ohms
RUP Pad internal pull up resister 78K 104K 146K Ohms
6.4 DC Characteristics (D+/D-)
Symbol Description Min Typ Max Unit
VOL D+/D- static output LOW (RL of 1.5K to 3.6V ) 0.3 V
VOH D+/D- static output HIGH (RL of 15K to GND ) 2.8 3.6 V
VDI Differential input sensitivity 0.2 V
VCM Differential common mode range 0.8 2.5 V
VSE Single-ended receiver threshold 0.2 V
CIN Transceiver capacitance 20 pF
ILO Hi-Z state data line leakage -10 +10
µA
Z
Driver output resistance 28 43 Ohms
DRV
6.5 Switching Characteristics
Symbol Description Min Typ Max Unit
FX1 X1 crystal frequency 11.97 12 12.03 MHz
T
X1 cycle time 83.3 ns
CYC
T
X1 clock LOW time 0.45T
X1L
T
X1 clock HIGH time 0.45T
X1H
T
r30pf
T
f30pf
Output pad rise time from 10% to 90%
swing with 30pF loading
Output pad fall time from 10% to 90% swing
with 30pF loading
cyc
cyc
ns
ns
ns
ns
©2001-2002 Genesys Logic Inc.—All rights reserved. Page 20 of 24
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GL813 - USB2.0 CompactFlash Card Reader Controller
Symbol Description Min Typ Max Unit
T
T
T
T
r50pf
f50pf
rUSB
fUSB
Output pad rise time from 10% to 90%
swing with 50pF loading
Output pad fall time from 10% to 90% swing
with 50pF loading
ns
ns
D+/D- rise time with 50pF loading 4 20 ns
D+/D- fall time with 50pF loading 4 20 ns
©2001-2002 Genesys Logic Inc.—All rights reserved. Page 21 of 24
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GL813 - USB2.0 CompactFlash Card Reader Controller
7. Package Dimension
7.1 48-pin LQFP
SYMBOL MIN MAX
A 1.6
A1 0.05 0.15
A2 1.35 1.45
C1 0.09 0.16
D 9.00BSC
D1 7.00BSC
E 9.00BSC
E1 7.00BSC
e 0.5BSC
b 0.17 0.27
L 0.45 0.75
L1 1 REF
©2001-2002 Genesys Logic Inc.—All rights reserved. Page 22 of 24
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GL813 - USB2.0 CompactFlash Card Reader Controller
7.2 100-pin LQFP
©2001-2002 Genesys Logic Inc.—All rights reserved. Page 23 of 24
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GL813 - USB2.0 CompactFlash Card Reader Controller
8. Revision History
Version Description Date
1.0 First draft 2002/03/20
1.1 Correction and supplement of Electrical Characteristics data 2002/04/03
1.2 Add 100-pin LQFP package related data 2002/04/12
©2001-2002 Genesys Logic Inc.—All rights reserved. Page 24 of 24
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