• High performance and low-cost solution for USB keyboard with hub solution
• USB Specification Compliance
− Conforms to USB specification Rev. 1.1
− Conforms to HID Class specification Rev. 1.0
− Supports 1 device address for hub, 1 device address for keyboard
− Supports 2 endpoints of hub, 3 endpoints for keyboard
• 8-bit micro-processor
− RISC-like architecture
− USB optimized instruction set
− Single cycle instruction execution
− Operation Speed: DC to 24 MHz clock input
− Performance: 12 MIPS @ 24MHz
• I/O ports
− Up to 20 output pins for key matrix drive pin
− Up to 8 input pins for key matrix sense pin
− Up to 5 I/O pins with LED drive capability : 3 for keyboard, 2 for hub
− Up to 8 general purpose I/O pins for customization
• Internal memory
− 80 bytes of RAM
− 3.25K × 14 of program ROM
− larger size of ROM makes it possible for customization
• On-chip 3.3v output
− No external regulator required
• Integrated USB transceiver
• 12 MHz external clock
• Improved output drivers with slew-rate control to reduce EMI
• Internal power-on reset(POR)
• Internal power-fail detector for ESD recovery
• Support suspend/normal mode power management
• Remote wakeup is supported for both keyboard and hub
• Support power management for downstream port devices
• Automatic switching between self/bus powered mode
• Smart LED traffic indicator
− The higher data traffic flows through the hub downstream port, the higher
frequency that port’s LED will blink.
• 100 pin LQFP package for demo, COB structure is supported
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2 FUNCTION OVERVIEW
The GL651USB is an USB keyboard hub with 1 upstream port and 2 downstream ports.
It integrates USB keyboard and hub in a single chip to add extra value to traditional
keyboard and lower its total cost. The GL651USB uses an 8-bit RISC-like uC to
encode/decode the host commands and to decode the keyboard matrix data. Its 8 generalpurpose I/O(GPIO) pins and the uC-based structure make the implementation of
customization very easy. The GL651USB supports 20 drive pins to meet the diversity of
keyboard matrix. Besides, 5 GPIO pins support the LED driving, 3 for keyboard and 2
for hub. Hence vendors can decide whether or not to enable the hub LED function easily.
For giving more design flexibility, the power supply of GL651USB can be switched
automatically: self-power or bus-power. In the same way, vendors can pullup/pulldown
the SELF pin to support only self/bus power if they have cost issue. The GL651USB can
be configured as ganged/individual mode for hub functions by strapping through
pullup/pulldown the SUSPND pin. To prevent from abnormal current consumption of
downstream port devices, the GL651USB supplies power enable flags by reading the
over-current flags. By hub LED, The GL651USB also supports smart traffic indication,
i.e., the higher data traffic flows through one port, the higher frequency of that port’s
LED blinks. In order to minimize the power consumption, the GL651USB will turn LED
off and stop the clock automatically when it is suspended.
The GL651USB is the most featured and flexible product for those venders who are
looking for “USB Keyboard with Hub” solution. Besides, vendors can easily modify their
board circuits to meet their own requirement if they have product differentiation or cost
issues. Further more, if vendor has the requirement of saving their package cost, COB
componen t also can be supplied by request.
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3 PIN DEFINITIONS AND DESCRIPTIONS
l GL651USB
Pin No. Name I/O Description
3 GND - Analog ground
5 DM2 I/O Downstream port 2 USB data7 DP2 I/O Downstream port 2 USB data+
9 DM0 I/O Upstream port USB data11 DP0 I/O Upstream port USB data+
13 VCP - 3.3V output
15 DM1 I/O Downstream port 1 USB data17 DP1 I/O Downstream port 1 USB data+
19 VDD - VCC(5V)
21 NUMLOCK I/O Keyboard Num LOCK LED
Also can be used as general purpose pin GPIO0
23 CAPSLOCK I/O Keyboard Caps Lock LED
Also can be used as general purpose pin GPIO1
25 SCLOCK I/O Keyboard Scroll Lock LED
Also can be used as general purpose pin GPIO2
27 TEST I Test mode input: (internal pull low)
For 48 Mhz oscillator clock input, pull high
For 12 Mhz crystal clock input, floating
29 DRV1 O Key matrix drive output 1
31 DRV2 O Key matrix drive output 2
32 DRV3 O Key matrix drive output 3
34 DRV4 O Key matrix drive output 4
35 DRV5 O Key matrix drive output 5
37 DRV6 O Key matrix drive output 6
38 DRV7 O Key matrix drive output 7
40 DRV8 O Key matrix drive output 8
41 DRV9 O Key matrix drive output 9
43 DRV10 O Key matrix drive output 10
44 DRV11 O Key matrix drive output 11
46 DRV12 O Key matrix drive output 12
47 DRV13 O Key matrix drive output 13
49 DRV14 O Key matrix drive output 14
50 DRV15 O Key matrix drive output 15
52 GND - GND
54 DRV16 O Key matrix drive output 16
56 DRV17 O Key matrix drive output 17
58 DRV18 O Key matrix drive output 18
60 DRV19 O Key matrix drive output 19
62 DRV20 O Key matrix drive output 20
64 SUSPND I/O Suspend indication output and individual setting input
Pull low: individual mode.
Pull high: ganged mode
66 GPIO7 I/O General purpose pin 7
68 GPIO6 I/O General purpose pin 6
70 VDD - VCC(5V)
72 GPIO5 I/O General purpose pin 5
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73 GPIO4 I/O General purpose pin 4
75 GPIO3 I/O General purpose pin 3
76 RESET I Reset input
78 SELF I 1: self-powered. 0: bus-powered
79 SENSE1 I Keyboard matrix sense input 1
81 SENSE2 I Keyboard matrix sense input 2
82 SENSE3 I Keyboard matrix sense input 3
84 SENSE4 I Keyboard matrix sense input 4
85 SENSE5 I Keyboard matrix sense input 5
87 SENSE6 I Keyboard matrix sense input 6
88 SENSE7 I Keyboard matrix sense input 7
90 SENSE8 I Keyboard matrix sense input 8
91 PWRENB1# O Power enable for downstream port 1
93 PWRENB2# O Power enable for downstream port 2
94 OVCUR1# I Over current flag for downstream port1
96 OVCUR2# I Over current flag for downstream port2
97 XTAL2 O Ceramic resonator or crystal out
99 XTAL1 I Ceramic resonator or crystal in
TRANSCIVER: TRANSCIVER is the analog circuits, which takes care of the electrical
characteristics of USB.
SIE: SIE is the serial interface engine. The main responsibility of SIE is to
code/decode USB protocol. SIE guarantee the GL651USB always
function in a correct state.
KMIF: KMIF is the interface of key matrix and GL651USB. KMIF drives the
key matrix and sense the input. The sensed data is then output to the
registers, which provide the uC to judge the pressed key.
REGISTERS: REGISTERS is the interface of hardware and software. The used
registers will be listed in the later section.
REPEATER: REPEATER is the kernel of hub. It repeats the data accurately from the
upstream port to the downstream port, and vice versa.
PORT CONTROLLER: Each downstream port of hub needs a PORT CONTROLLER
respectively. It monitors the state of the port.
PLL: PLL extracts 48 Mhz clock from input 12 Mhz clock. This 48 Mhz
clock is used to generate USB clock in the digital PLL circuit.
5 REGISTER SUMMARY
MNEMONIC OFFSET DESCRIPTION
DEVCTL 00h Device control register
EVTFLG_1 01h USB function interrupt flag
EVTFLG_2 02h USB function interrupt flag
RXCTL0_HB 03h Endpoint 0 RX control of hub
RXCTL0_KB 04h Endpoint 0 RX control of keyboard
TXCTL0_HB 05h Endpoint 0 TX control of hub
TXCTL0_KB 06h Endpoint 0 TX control of keyboard
TXCTL123 07h Endpoint 1,2, and 3 TX control
FFDAT0_HB 08h Data buffer (FIFO) for endpoint 0 of hub
FFDAT0_KB 09h Data buffer (FIFO) for endpoint 0 of keyboard
FFDAT123 0Ah Data buffer (FIFO) for endpoint 1, 2, and 3
BUFCTL 0Bh Data buffer control register
DRVSEL 0Ch DRV1 ~ DRV18 select
SENSE 0Dh SENSE1 ~ SENSE8 input
ENDP_PORT_SEL 0Eh Endpoint selected and hub port to be configured
HUB_STAT_CHG 0Fh Hub status and status change indicator
PORT_STATUS 10h Hub ports status indicator
BUS_PORT_DATA 11h Hub ports status change indicator
HOST_CMD 12h Host command to HUB
ENP2_IND 13h Hub interrupt indicator
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LEDCTL 14h LED control flag
KBSTUS 15h Keyboard address and configuration status
REV 16h Chip revision
HUBSTUS 17h USB hub address and configuration status
MODSEL 18h Strapping mode register
R/O: read only
R/W: read / write
R/W1C: read / write “1” to clear
W/O: write only
DEVCTL ( offset 00, default = 00h )
R/W R/O R/W R/W R/W R/O R/W
USBRDY --
USBRDY : 0 - USB interface is not ready. The device drives USB with SE0.
GANG : 0 – Individual mode. 1 – gang mode.
RW_KB : remote wakeup ability enable for keyboard.
RW_HUB : remote wakeup ability enable for hub.
SFRAME : short frame option for test purpose
SELF : 0 - HUB is bus powered.
1 - HUB is self-powered.
PWRDN : power down mode
GANG
1 - USB interface is ready. The device stops driving USB with SE0.
After power -on reset, USBRDY is cleared and the device looks like
disconnected. Set USBRDY to ‘1’ to enable USB interface.
Set SFRAME to ‘1’ will shorten frame length to 1/15 ms. It is to shorten the
time required for test.
RW_KB RW_HUB SFRAME SELF PWRDN
In suspend state, firmware can set PWRDN to put the controller into power
down mode. In this mode, the embedded micro-controller and most internal
activities are frozen.
EVTFLG _1 ( offset 01, default = 00h )
R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C
--
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EP3TX EP2TX EP1TX EP0TXKB EP0TXHB
Interrupt event flag –
EP0RXHB : a SETUP or OUT transaction to endpoint 0 of hub is accepted
EP0RXKB : a SETUP or OUT transaction to endpoint 0 of keyboard is accepted
EP0TXHB : USB host controller accepts hub data transmitted via endpoint 0.
EP0TXKB : USB host controller accepts keyboard data transmitted via endpoint 0.
EPnTX : USB host controller accepts data transmitted via endpoint n
EP0RXKB
EP0RXHB
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GL651USB USB KEYBOARD HUB CONTROLLER
EVTFLG _2 ( offset 02, default = 00h )
R/W1C R/W1C R/W1C R/W1C R/W1C
-Interrupt event flag –
SUSPD : the controller goes into suspend state
WAKEUP : remote wakeup is detected when global suspended
USBRST : End of USB reset
SOF : SOF detected or generated by HUB timer.
C_LCPWR : POWER source change.
RXCTL0 of hub.
Status of endpoint 0 receiving –
RXCNT3~0 : EP0 received data byte count.
RXSEQ : 1 - The received data PID is DATA1
RXOUT : 1 - The received token PID is OUT.
RXSETUP : 1 - The received token PID is SETUP.
RXDIS : 0 - Endpoint 0 FIFO is empty and ready for data-packet receiving.
If RXDIS = 1, the device will not accept an OUT transaction addressed to it, and will respond
with a NAK to an error -free transaction. Hardware will automatically set RXDIS after a
successful receiving. After processing, the micro-controller should clear RXDIS to enable next
data-packet receiving or free FF0 for filling of the data to transmit. Note that a SETUP
transaction addressed to the device is always accepted even though RXDIS = 1.
Endpoint 0 transmit setting –
EP0CNT3~0 : number of data bytes to transmit
EP0OE : enable data transmit
EP0SEQ : data packet type
EP0STL : set endpoint 0 stall
1 – EP0 will respond to USB host controller with STALL packet
EP0STL will be automatically cleared when a setup transaction is accepted.
After filling the data-to-transmit into FF0, the micro-controller should setup this register to
enable endpoint 0 data transmit. If EP0OE = 0, endpoint 0 will respond to a valid IN transaction
-- -- WAKEUP SUSPD USBRST SOF C_LCPWR
0 - The received data PID is DATA0
1 - Endpoint 0 FIFO is filled with data and will reject the new -coming data
packet.
1 – ready to transmit data packet
0 – not ready to transmit data packet (default)
0 –DATA0
1 –DATA1
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with a NAK. EP0OE will be automatically cleared after a successful transmission, or when
endpoint 0 has incidentally accepted another SETUP or OUT transaction.
TXCTL0_KB ( offset 06, default = 00h )
R/W R/W R/W R/W R/W R/W R/W
-- EP0STL EP0OE EP0SEQ EP0CNT3 EP0CNT2 EP0CNT1 EP0CNT0
TXCTL0 of hub. Definition of each bit is the same as TXCTL0_HB.
EPnCNT3~0 : number of data bytes to transmit.
EPnOE : enable data transmit
1 – ready to transmit data packet
0 – not ready to transmit data packet (default)
EPnSEQ : data packet type
0 –DATA0
1 –DATA1
EPnSTL : set endpoint n stall
1 – EPn will respond to USB host controller with STALL packet
0 – default
After preparing the data to transmit, the micro-controller should setup this register to enable
endpoint n data transmit. If EPnOE = 0, endpoint n will respond to a valid IN transaction with a
NAK. After a successful transmission, the device will automatically clear EPnOE. EPSEL1~3
must be set before settingTXCTL123.
FFDAT0_HB ( offset 08, default = 00h )
R/W R/W R/W R/W R/W R/W R/W R/W
FFD7 FFD6 FFD5 FFD4 FFD3 FFD2 FFD1 FFD0
FFDAT0 of hub.
Each FFDAT0 read/write will automatically increase the FIFO pointer, which is a 3-bit circular
counter, by 1. Writing FPRST0 with ‘1’ (in BUFCTL) will reset the pointer. Note that to fill
FFDAT0, RXDIS (in RXCTL0) must be first cleared.
FFDAT0_KB ( offset 09, default = 00h )
R/W R/W R/W R/W R/W R/W R/W R/W
FFD7 FFD6 FFD5 FFD4 FFD3 FFD2 FFD1 FFD0
FFDAT0 of hub. Definition of each bit is the same as FFDAT0_HB.
FFDAT123 ( offset 0A, default = 00h )
R/W R/W R/W R/W R/W R/W R/W R/W
FFD7 FFD6 FFD5 FFD4 FFD3 FFD2 FFD1 FFD0
Each FFDAT123 read/write will automatically increase the FIFO pointer, which is a 3-bit
circular counter, by 1. Writing FPRST1 with ‘1’ (in BUFCTL) will reset the pointer. E PSEL1~3
must be set before setting FFDAT123.
BUFCTL ( offset 0B)
R/W R/W
-- -- -- -- -- -- FPRST1 FPRST0
Data buffer control –
FPRST[1:0] : Reset FIFO pointer of FIFO 0~3.
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Before FFRST[1:0] is used, ENDP[1~3] must have been set.
DRVSEL ( offset 0C)
R/W R/W R/W R/W R/W R/W R/W
-- INVDRV DRVOE DRV4 DRV3 DRV2 DRV1 DRV0
DRV[4:0] : Select one of DRV1 to DRV20 port to drive if DRVOE is set.
5’h00 ~ 5’h11 stand for DRV1 to DRV20.
NOTE: 5’h14 ~5’h1f are invalid.
DROVE : DRV[4:0] output enable. ONLY when DRVOE is set can DRV[4:0] drive
out.
INVDRV : Set this bit to drive all DRV1-20 to low except the selected drive pin
Port under host command or Endpoint under host request
PORTSEL1 1’b1 – port 1 selected
PORTSEL2 1’b1 – port 2 selected
PORTSEL3 1’b1 – port 3 selected
EPSEL3 1’b1 – endpoint 3 is selected
EPSEL2 1’b1 – endpoint 2 is selected
EPSEL1 1’b1 – endpoint 1 is selected
Before FFDAT123 and TXCTL123 is used, EPSEL1~3 must have been set.
HUB_STAT_CHG ( offset 0F, default = 00h )
R/O R/O R/O R/O
LCPWR OVCUR -- -- -- -- C_LCPWR C_OVCUR
HUB status and status change
LCPWR : HUB local power status
1’b0 – local power good
1’b1 – local power lost
OVRCUR : HUB over current indicator
1’b0 – No over -current condition currently exists
1’b1 – A hub over -current condition exists
C_LCPWR : Local power status change
1’b0 – No change has occurred to local power status
1’b1 – local power status has changed
C_OVRCUR : HUB over current indicator change
1’b0 – No change has occurred to the over -current indicator
1’b1 – Hub over -current indicator has changed
PT_PWR 1’b0 – port is in power off state, 1’b1 – port is not in power
off state
PT_RST :1’b0 – Reset signaling not asserted, 1b’1 – Reset signal ing
asserted
PT_OVCUR : 1’b0 – No over -current condition occurred on this port
1’b1 – An over -current condition exists on this port
PT_SUS : 1’b0 – port not suspended, 1’b1 – port suspended or
resuming
PT_EN : 1’b0 – port is disabled, 1’b1 – port is enabled
PT_CON : 1’b0 – No device is present, 1’b1 – A device is present on
this port
BUS_PORT_DATA ( offset 11, default = 00h )
R/O R/O R/O R/O R/O R/O R/O
VP VM -- C_PT_RST C_PT_
OVCUR
Bus state and Port status change indicator:
VP : VP state on the downstream port
VM : VM state on the downstream port
C_PT_RST : 1’b0 – No change, 1’b1 – Reset complete
C_PT_OVCUR : 1’b0 – No change has occurred to over-current indicator
: 1’b1 – over -current indicator has changed
C_PT_SUS : 1’b0 – No change, 1’b1: – Resume complete
C_PT_EN : Set to one when a port is disabled because of a Port_error
condition
C_PT_CON : 1’b0 – No change has occurred to current connect status
: 1’b1 – Current connect status has changed
-- -- P2_ON P1_ON -- -- P2_TRX P1_TRX
Hub LED control flag:
P1_TRX : upstream traffic happens on downstream port 1
P2_TRX : upstream traffic happens on downstream port 2
P1_ON : if 1’b1, L ED is always on, otherwise, judge according to TRXFLAG
register.
P2_ON : if 1’b1, LED is always on, otherwise, judge according to TRXFLAG
USB hub status registers. Procedure to set the device address:
1. After USB reset, the device responds to default address 0, and hub configuration = 0.
2. USB host controller issues SET_ADDRESS request to the device. (INTRB asserted)
3. Micro-controller recognizes the request, then set DEVADR register with appropriate value.
4. Micro-controller prepares the status stage of SET_ADDRESS request by programming
TXCTL0 register.
5. When the hub configuration value is not equal zero, HCONFIG is set to one.
USB reset will clear this register.
MODSEL (offset 18, default = 07h)
R/O R/O R/O R/O R/O R/O R/O R/O
MOD7 MOD6 MOD5 MOD4 MOD3 MOD2 MOD1 MOD0
MOD[7:0] is strapping value at initial state from GPIO[7:0]. GPIO[2:0] is default pull high for
keyboard LED control. F/W can utilize these bits for customization.
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6 MAXIMUM RATINGS
Maximum ratings are the extreme limits to which the GL651USB can be exposed without permanently
damaging it. The GL651USB contains circuitry to protect the inputs against damage from high static
voltages; however, do not apply voltages higher than those shown in the tabl e. Keep VIN and V
the range GND ≤ (VIN or V
) ≤ VCC. Connect unused inputs to the appropriate voltage level, either GND
OUT
OUT
or VDD.
Symbol Characteristic Value Unit
T
Storage temperature -55 to +150
STG
TOP Operating temperature 0 to +70
°C
°C
VCC Supply voltage -0.5 to +7.0 V
VIN DC input voltage -0.5 to +V
+ 0.5 V
DD
I Maximum current per pin excluding VDD and VSS 25 mA
I
Maximum current out of GND 100 mA
MGND
I
Maximum current out of VCC 100 mA
MVCC
V
Static discharge voltage >4000 V
ESD
7 ELECTRICAL CHARACTERISTICS
Symbol Parameter Tese Conditions Min. Typ. Max. Unit
Supply
VDD Digital Power Supply 4.5 5.0 5.5 V
V
Analog Power Supply 4.5 5.0 5.5 V
DDA
IDD Digital Supply Current mA
I
Analog Supply Current mA
DDA
USB Bus: DP and DM
VCP Regulated Voltage Output 3.0 3.3 3.6 V
VDI Static Input Voltage 0 - VCP V
VDO Static Output Voltage 0 - VCP V
Digital I/O Pins
VIL Input Logic Low Voltage - - 0.8 V
VIH Input Logic High Voltage 2.0 - - V
VOL Output Logic Low V oltage IO=-4.0mA - - 0.1xVDD V
VOH Output Logic High Voltage IO=+4.0mA 0.9xVDD - - V