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FSTYC9055R

Datasheet FSTYC9055R, FSTYC9055D Datasheet (Intersil Corporation)

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Page 1
TM
FSTYC9055D, FSTYC9055R
Data Sheet June 2000
Radiation Hardened, SEGR Resistant P-Channel Power MOSFETs
The Intersil portfolio of SEGR resistant radiation hardened MOSFETs includes N-Channel and P-Channel devices in a variety of voltage, current and on-resistance ratings. Numerous packaging options are also available.
This MOSFET is an enhancement-mode silicon-gate power field-effect transistor of the vertical DMOS (VDMOS) structure. It is specially designed and processed to be radiation tolerant. The MOSFET is well suited for applications exposed to radiation environments such as switching regulation, switching converters, motor drives, relay drivers and drivers for high-power bipolar switching transistors requiring high speed and low gate drive power. This type can be operated directly from integrated circuits.
Reliability screening is available as either commercial, TXV equivalent of MIL-S-19500, or Space equivalent of MIL-S-19500. Contact Intersil for any desired deviations from the data sheet.
Formerly available as type TA17750T.
File Number 4755.1
Features
• 64A, -60V, r
• Total Dose
- Meets Pre-RAD Specifications to 100K RAD (Si)
• Typical SEE Immunity
- LET of 36MeV/mg/cm Breakdown and V
- LET of 26MeV/mg/cm Breakdown and V
• Dose Rate
- Typically Survives 3E9 RAD (Si)/s at 80% BV
- Typically Survives 2E12 if Current Limited to I
• Photo Current
- 6nA Per-RAD (Si)/s Typically
• Neutron
- Maintain Pre-RAD Specifications for 3E13 Neutrons/cm
- Usable to 3E14 Neutrons/cm
DS(ON)
= 0.023Ω
2
with VDS up to 80% of Rated
of 0V
GS
2
with VDS up to 100% of Rated
of 5V Off-Bias
GS
2
2
Symbol
D
G
S
DSS
DM
Ordering Information
RAD LEVEL SCREENING LEVEL PART NUMBER/BRAND
10K Commercial FSTYC9055D1 10K TXV FSTYC9055D3 100K Commercial FSTYC9055R1 100K TXV FSTYC9055R3 100K Space FSTYC9055R4
1
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
Packaging
SMD2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
Page 2
FSTYC9055D, FSTYC9055R
Absolute Maximum Ratings T
= 25oC, Unless Otherwise Specified
C
FSTYC9055D, FSTYC9055R UNITS
Drain to Source Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
Drain to Gate Voltage (RGS = 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DS
DGR
-60 V
-60 V
Continuous Drain Current
TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
D D
DM
GS
64 A
41 A 192 A ±20 V
Maximum Power Dissipation
TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
T T
162 W
65 W
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.30 W/oC
Single Pulsed Avalanche Current, L = 100µH, (See Test Figure) . . . . . . . . . . . . . . . . . . . . . . . . I
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Pulsed Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, T
STG
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
AS
S
SM
L
192 A
64 A
192 A
-55 to 150 300
o
C
o
C
(Distance >0.063in (1.6mm) from Case, 10s Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications T
= 25oC, Unless Otherwise Specified
C
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BV Gate Threshold Voltage V
DSSID
GS(TH)VGS
= 1mA, VGS = 0V -60 - - V
= VDS,
ID = 1mA
TC = -55oC - - -7.0 V TC = 25oC -2.0 - -6.0 V TC = 125oC -1.0 - - V
Zero Gate Voltage Drain Current I
Gate to Source Leakage Current I
DSS
GSS
VDS = -48V, VGS = 0V
TC = 25oC--25µA TC = 125oC - - 250 µA
VGS = ±20V TC = 25oC - - 100 nA
TC = 125oC - 200 nA Drain to Source On-State Voltage V Drain to Source On Resistance r
Turn-On Delay Time t
DS(ON)VGS
DS(ON)12ID
d(ON)
Rise Time t Turn-Off Delay Time t
d(OFF)
Fall Time t Total Gate Charge Q
g(TOT)VGS
Gate Charge at 12V Q Threshold Gate Charge Q Gate Charge Source Q Gate Charge Drain Q Plateau Voltage V
(PLATEAU)ID
Input Capacitance C Output Capacitance C Reverse Transfer Capacitance C Thermal Resistance Junction to Case R
r
f
g(12)
g(TH)
gs
gd
ISS OSS RSS
JC
θ
= -12V, ID = 64A - - -1.60 V
= 41A,
VGS = -12V VDD = -30V, ID = 64A,
RL = 0.47Ω, VGS = -12V, RGS = 2.35Ω
TC = 25oC - 0.016 0.023 Ω TC = 125oC - - 0.037 Ω
- - 60 ns
- - 45 ns
- - 90 ns
- - 35 ns
= 0V to -20V VDD = -30V,
VGS = 0V to -12V - 160 190 nC
ID = 64A
- - 330 nC
VGS = 0V to -2V - - 18 nC
-5171nC
-3146nC
= 64A, VDS = -15V - -7 - V
VDS = -25V, VGS = 0V, f = 1MHz
- 7100 - pF
- 2130 - pF
- 370 - pF
- - 0.77
o
C/W
2
Page 3
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Forward Voltage V Reverse Recovery Time t
SD
rr
FSTYC9055D, FSTYC9055R
ISD = 64A -0.6 - -1.8 V ISD = 64A, dISD/dt = 100A/µs - - 120 ns
Electrical Specifications up to 100K RAD T
= 25oC, Unless Otherwise Specified
C
PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS
Drain to Source Breakdown Volts (Note 3) BV Gate to Source Threshold Volts (Note 3) V Gate to Body Leakage (Notes 2, 3) I Zero Gate Leakage (Note 3) I Drain to Source On-State Volts (Notes 1, 3) V Drain to Source On Resistance (Notes 1, 3) r
DS(ON)12VGS
DSS
GS(TH)
GSS DSS
DS(ON)VGS
VGS = 0, ID = 1mA -60 - V VGS = VDS, ID = 1mA -2.0 -6.0 V VGS = ±20V, VDS = 0V - 100 nA VGS = 0, VDS = -48V - 25 µA
= -12V, ID = 64A - -1.60 V = -12V, ID = 41A - 0.023 Ω
NOTES:
1. Pulse test, 300µs Max.
2. Absolute value.
3. Insitu Gamma bias must be sampled for both VGS = -12V, VDS = 0V and VGS = 0V, VDS = 80% BV
DSS
.
Single Event Effects (SEB, SEGR) Note 4
ENVIRONMENT (NOTE 5)
TEST SYMBOL
ION
SPECIES
TYPICAL LET
(MeV/mg/cm)
TYPICAL
RANGE (µ)
Single Event Effects Safe Operating Area SEESOA Ni 26 43 20 -60
Br 37 36 10 -60 Br 37 36 15 -36 Br 37 36 20 -24
NOTES:
4. Testing conducted at Brookhaven National Labs; witnessed by Naval Surface Warfare Center (NSWC), Crane, IN.
5. Fluence = 1E5 ions/cm2 (typical), TC = 25oC.
6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR).
APPLIED
VGS BIAS
(V)
(NOTE 6)
MAXIMUM
VDSBIAS (V)
Performance Curves Unless Otherwise Specified
LET = 26MeV/mg/cm LET = 37MeV/mg/cm2, RANGE = 36µ
(V)
DS
V
-70
-60
-50
-40
-30
-20
-10
FLUENCE = 1E5 IONS/cm2 (TYPICAL)
TEMP = 25oC
0
0101520 25
5
FIGURE 1. SINGLEEVENT EFFECTS SAFE OPERATINGAREA FIGURE2. DRAININDUCTANCE REQUIRED TO LIMIT
3
2
, RANGE = 43µ
1E-3
1E-4
1E-5
1E-6
LIMITING INDUCTANCE (HENRY)
1E-7
(V)
V
GS
-30 DRAIN SUPPLY (V)
GAMMA DOT CURRENT TO I
ILM = 10A
30A
100A
300A
-300-100-10
AS
-1000
Page 4
FSTYC9055D, FSTYC9055R
Performance Curves Unless Otherwise Specified (Continued)
70
60
50
40
30
, DRAIN (A)
D
I
20
10
0
TC, CASE TEMPERATURE (oC)
FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE
-12V
Q
G
500
100
10
, DRAIN CURRENT (A)
D
I
150100500-50
OPERATION IN THIS AREA MAY BE LIMITED BY r
1
-1
DS(ON)
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
-10 -100
TC = 25oC
100µs
1ms
10ms
-200
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
2.5
2.0
DS(ON)
1.5
PULSE DURATION = 250ms, VGS = -12V, ID = 41A
Q
GS
V
G
Q
GD
CHARGE
1.0
NORMALIZED r
0.5
0.0
-80 -40 0 40 80 120 160 T
J
FIGURE 5. BASIC GATE CHARGE WAVEFORM FIGURE 6. NORMALIZEDr
10
)
1
JC
θ
NORMALIZED
THERMAL RESPONSE (Z
0.1
0.01
0.001
0.5
0.2
0.1
0.05
0.02
0.01 SINGLE PULSE
-5
10
-4
10
NOTES: DUTY FACTOR: D = t1/t
PEAK TJ = PDM x Z
-3
10
t, RECTANGULAR PULSE DURATION (s)
2
+ T
JC
C
θ
-2
10
P
DM
-1
10
, JUNCTION TEMPERATURE (oC)
vs JUNCTION TEMPERATURE
DS(ON)
t
1
t
2
0
10
1
10
FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
4
Page 5
FSTYC9055D, FSTYC9055R
Performance Curves Unless Otherwise Specified (Continued)
500
100
, AVALANCHE CURRENT (A)
AS
I
Test Circuits and Waveforms
ELECTRONIC SWITCH OPENS
WHEN IAS IS REACHED
V
DS
L
VARY t
TO OBTAIN
P
REQUIRED PEAK I
0V
t
P
VGS≤ 20V
CURRENT
TRANSFORMER
AS
50Ω
+
I
AS
-
DUT
50W
STARTING TJ = 25oC
STARTING TJ = 150oC
IF R = 0
= (L) (IAS) / (1.3 RATED BV
t
AV
IF R ≠ 0 tAV = (L/R) ln [(IAS*R) / (1.3 RATED BV
10
0.1 1 , TIME IN AVALANCHE (ms)
t
AV
DSS
- VDD)
DSS
- VDD) + 1]
FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING
+
V
DD
-
50V-150V
10
BV
DSS
t
P
I
AS
t
AV
V
DS
V
DD
FIGURE 9. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 10. UNCLAMPED ENERGY WAVEFORMS
0V
V
GS
= -12V
t
V
DD
R
L
V
DS
V
DS
t
d(ON)
90%
ON
t
r
10%
DUT
R
GS
V
GS
10%
PULSE WIDTH
t
d(OFF)
90%
t
OFF
t
10%
50%50%
FIGURE 11. RESISTIVE SWITCHING TEST CIRCUIT FIGURE 12. RESISTIVE SWITCHING WAVEFORMS
5
f
90%
Page 6
FSTYC9055D, FSTYC9055R
Screening Information
Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table).
Delta Tests and Limits (JANTXV Equivalent, JANS Equivalent) T
PARAMETER SYMBOL TEST CONDITIONS MAX UNITS
Gate to Source Leakage Current I Zero Gate Voltage Drain Current I Drain to Source On Resistance r Gate Threshold Voltage V
NOTES:
7. Or 100% of Initial Reading (whichever is greater).
8. Of Initial Reading.
DS(ON)
GS(TH)
GSS DSS
VGS = ±20V ±20 (Note 7) nA VDS = 80% Rated Value ±25 (Note 7) µA TC = 125oC at Rated I ID = 1.0mA ±20% (Note 8) V
Screening Information
TEST JANTXV EQUIVALENT JANS EQUIVALENT
Gate Stress VGS = -30V, t = 250µsV Pind Optional Required Pre Burn-In Tests (Note 9) MIL-S-19500 Group A,
Subgroup 2 (All Static Tests at 25oC)
Steady State Gate Bias (Gate Stress)
Interim Electrical Tests (Note 9) All Delta Parameters Listed in the Delta Tests
Steady State Reverse Bias (Drain Stress)
PDA 10% 5% Final Electrical Tests (Note 9) MIL-S-19500, Group A, Subgroup 2 MIL-S-19500, Group A,
NOTE:
9. Test limits are identical pre and post burn-in.
MIL-STD-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours
and Limits Table MIL-STD-750, Method 1042, Condition A
VDS = 80% of Rated Value, TA = 150oC, Time = 160 hours
= 25oC, Unless Otherwise Specified
C
D
MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25oC)
MIL-STD-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours
All Delta Parameters Listed in the Delta Tests and Limits Table
MIL-STD-750, Method 1042, Condition A VDS = 80% of Rated Value, TA = 150oC, Time = 240 hours
Subgroups 2 and 3
±20% (Note 8) Ω
= -30V, t = 250µs
GS
Additional Screening Tests
PARAMETER SYMBOL TEST CONDITIONS MAX UNITS
Safe Operating Area SOA VDS = -48V, t = 10ms 9.0 A Unclamped Inductive Switching I Thermal Response ∆V Thermal Impedance ∆V
6
AS
SD SD
V
GS(PEAK)
tH = 10ms; VH = -25V; IH = 4A 65 mV tH = 500ms; VH = -20V; IH = 4A 135 mV
= -15V, L = 0.1mH 192 A
Page 7
FSTYC9055D, FSTYC9055R
Rad Hard Data Packages - Intersil Power Transistors
TXV Equivalent
1. RAD HARD TXV EQUIVALENT - STANDARD DATA PACKAGE
A. Certificate of Compliance B. Assembly Flow Chart C. Preconditioning - Attributes Data Sheet D. Group A - Attributes Data Sheet E. Group B - Attributes Data Sheet
F. Group C - Attributes Data Sheet
G. Group D - Attributes Data Sheet
2. RAD HARD TXV EQUIVALENT - OPTIONAL DATA PACKAGE
A. Certificate of Compliance B. Assembly Flow Chart C. Preconditioning - Attributes Data Sheet
- Pre and Post Burn-In Read and Record Data
D. Group A - Attributes Data Sheet E. Group B - Attributes Data Sheet
- Pre and Post Read and Record Data for Intermittent Operating Life (Subgroup B3)
- Bond Strength Data (Subgroup B3)
- Pre and Post High TemperatureOperating Life Read and Record Data (Subgroup B6)
F. Group C - Attributes Data Sheet
- Pre and Post Read and Record Data for Intermittent Operating Life (Subgroup C6)
- Bond Strength Data (Subgroup C6)
G. Group D - Attributes Data Sheet
- Pre and Post RAD Read and Record Data
Class S - Equivalents
1. RAD HARD “S” EQUIVALENT - STANDARD DATA PACKAGE
A. Certificate of Compliance
B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report
E. Preconditioning - Attributes Data Sheet
- HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data
- HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data
F. Group A - Attributes Data Sheet
G. Group B - Attributes Data Sheet
H. Group C - Attributes Data Sheet
I. Group D - Attributes Data Sheet
2. RAD HARD MAX. “S” EQUIVALENT - OPTIONAL DATA PACKAGE
A. Certificate of Compliance
B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report
E. Preconditioning - Attributes Data Sheet
- HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data
- HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data
- X-Ray and X-Ray Report
F. Group A - Attributes Data Sheet
- Subgroups A2, A3, A4, A5 and A7 Data
G. Group B - Attributes Data Sheet
- Subgroups B1, B3, B4, B5 and B6 Data
H. Group C - Attributes Data Sheet
- Subgroups C1, C2, C3 and C6 Data
I. Group D - Attributes Data Sheet
- Pre and Post Radiation Data
7
Page 8
SMD2
3 PAD CERAMIC LEADLESS CHIP CARRIER
FSTYC9055D, FSTYC9055R
E
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.130 0.142 3.30 3.60 3 b 0.135 0.145 3.43 3.68 ­D 0.520 0.530 13.20 13.46 -
D
D D
0.435 0.445 11.05 11.30 -
1
0.115 0.125 2.92 3.17 -
2
E 0.685 0.695 17.40 17.65 -
E
1
E
2
0.470 0.480 11.94 12.19 -
0.152 0.162 3.86 4.11 -
NOTES:
A
1. No current JEDEC outline for this package.
2. Controlling dimension: INCH.
3. Measurement prior to pre-solder coating the mounting pads.
E
E
1
D
1
3
2
2
D
2
b
1
4. Revision 3 dated 5-00.
1 - GATE 2 - SOURCE 3 - DRAIN
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only.Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240
EUROPE
Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05
ASIA
Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369
8
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