Datasheet FSTU6800WMX, FSTU6800WM, FSTU6800QSCX, FSTU6800QSC, FSTU6800MTCX Datasheet (Fairchild Semiconductor)
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© 1999 Fairchild Semiconductor Corporation DS500194 www.fairchildsemi.com
December 1998
Revised December 1999
FSTU6800 10-Bit Bus Switch with Pre-Charged Outputs
FSTU6800
10-Bit Bus Switch with Pre-Charged Outputs
and −2V Undershoot Hardened Circuit (UHC) Protection
General Description
The Fairchild Sw itch FSTU6800 provides 10-bits of highspeed CMOS TTL-comp atible bus switching. The low on
resistance of the switch allows inp uts to be connected to
outputs without adding propagation delay or generating
additional ground bounce noise. Both the A Ports and the B
Ports are “undersh oot hardened ” with UHC pr otection to
support an extended input range to 2.0V belo w ground.
Fairchild’s integrated Undershoot Hardened Circuit, UHC
senses undershoot at the I/Os, and responds by preventing
voltage differentials from developing and turning on the
switch. The device als o prechar ges the B Port to a selectable bias voltage (BiasV) to minimize live insertion noise.
The device is organized as a 10-bit switch with a bus
enable (OE
) signal. When OE is LOW, the switch is ON
and Port A is connect ed to Po rt B. Whe n OE
is HIGH, the
switch is OPEN and the B Port is precharged to BiasV
through an equivalent 10-kΩ resistor.
Features
■ 4Ω switch connection between two ports.
■ Undershoot Hardened to -2.0V.
■ Soft enable turn-on to minimize bus-to-bus charge
sharing during enable.
■ Low l
CC
.
■ Zero bounce in flow-through mode.
■ Output precharge to minimize live insertion noise.
■ Control inputs compatible with TTL level.
■ See Applications Note AN-5008 for details.
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending the s uffix let te r “X” to the ordering code.
Logic Diagram
Pin Descriptions
Connection Diagram
Truth Table
UHC is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
FSTU6800WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MO-153 4.4mm Wide
FSTU6800QSC MQA24 24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide
FSTU6800MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Name Description
OE
Bus Switch Enable
ABus A
BBus B
BiasV Bus B Voltage Bias
OE
B0–B
9
Function
LA
0–A9
Connect
HBiasV Precharge
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FSTU6800
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
(Note 3)
Note 1: The Absolute Maximum Ratings are those values beyond which
the safety of the dev ice cannot be guaranteed. T he device sh ould not be
operated at these limit s. The parametric values defin ed in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The Recommende d Opera ting Condit ions table s will de fine the co nditions
for actual device operation.
Note 2: The input and output ne gative vo ltage ra tings may be excee ded if
the input and output diode current ratings are observed.
Note 3: Unused control inputs must be held HIGH or LOW. They may not
float.
DC Electrical Characteristics
Note 4: Measured by the volta ge drop between A and B pi ns at th e indicated current through the switch. On resistance is determined by the lower of the
voltages on the two (A or B) pins.
Note 5: Typi c al values are at V
CC
= 5.0V and TA= +25°C
Supply Voltage (VCC) −0.5V to +7.0V
DC Switch Voltage (V
S
) −2.0V to +7.0V
Bias V Voltage Range −0.5V to +7.0V
DC Input Voltage (V
IN
) (Note 2) −0.5V to +7.0V
DC Input Diode Current (l
IK
) VIN< 0V −50mA
DC Output (I
OUT
) Sink Current 128mA
DC V
CC
/GND Current (ICC/I
GND
) +/− 100mA
Storage Temperature Range (T
STG
) −65°C to +150 °C
Power Supply Operating (V
CC
) 4.0V to 5.5V
Precharge Supply (BiasV) 1.5V to V
CC
Input Voltage (VIN)0V to 5.5V
Output Voltage (V
OUT
)0V to 5.5V
Input Rise and Fall Time (t
r
, tf)
Switch Control Input 0 nS/V to 5 nS/V
Switch I/O 0nS/V to DC
Free Air Operating Temperature (T
A
) −40 °C to +85 °C
Symbol Parameter
V
CC
(V)
TA = −40 °C to +85 °C
Units Conditions
Min
Typ
(Note 5)
Max
V
IK
Clamp Diode Voltage 4.5 −1.2 V IIN = −18mA
V
IH
HIGH Level Input Voltage 4.0–5.5 2.0 V
V
IL
LOW Level Input Voltage 4.0–5.5 0.8 V
I
I
Input Leakage Current 5.5 ±1.0 µA0 ≤ VIN ≤ 5.5V
I
O
Output Current 4.5 0.25 mA BiasV = 2.4V, B = 0
I
OZ
OFF-STATE Leakage Current 5.5 ±1.0 µA0 ≤ A ≤ VCC, VIN = V
IH
R
ON
Switch On Resistance 4.5 4 7 Ω VS = 0V, IIN = 64 mA
(Note 4) 4.5 4 7 Ω V
S
= 0V, IIN = 30 mA
4.5 8 15 Ω V
S
= 2.4V, IIN = 15 mA
4.0 11 20 Ω VS = 2.4V, IIN = 15 mA
I
CC
Quiescent Supply Current 5.5 3 µAVS = VCC or GND, I
OUT
= 0
∆ I
CC
Increase in I
CC
per Input 5.5 2.5 mA OE input at 3.4V
Other inputs at VCC or GND
I
BIAS
Bias Pin Leakage Current 5.5 ±1.0 µAOE = 0V, B = 0V, BiasV = 5.5V
I
OZU
Switch Undershoot Current 5.5 100 µAIIN = −20 mA, OE = 5.5V, V
OUT
≥ V
IH
V
IKU
Voltage Undershoot 5.5 −2.0 V 0.0 mA ≥ IIN ≥ −50 mA, OE = 5.5V
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FSTU6800
AC Electrical Characteristics
Note 6: This par ameter is guaranteed by design but is not tes t ed. The bus swit c h c ontributes no propagation delay other t han the RC delay of the typical On
resistance of the switc h and the 50 pF load capac it anc e, when driven by an ide al v olt age the source (zero ou tp ut im pedance).
Capacitance (Note 7)
Note 7: TA = +25°C, f = 1 MHz, Ca pacitance is characteriz ed but not tested.
AC Loading and Waveforms
Note: Input driven by 50 Ω source terminated in 50 Ω, RU = RD = 500 Ω
Note: C
L
includes load and stray capacitance, CL= 50 pF
Note: Input PRR = 1.0 MHz, t
W
= 500 nS
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
Symbol Parameter
T
A
= −40 °C to +85 °C,
C
L
= 50 pF, RU = RD = 500Ω
Units Conditions Figure No.
V
CC
= 4.5 – 5.5V VCC = 4.0V
Min Max Min Max
t
PHL,tPLH
Prop Delay Bus to Bus (Note 6) 0.25 0.25 ns VI = OPEN Figure 1
Figure 2
t
PZH
Output Enable Time 7.0 30.0 35.0 ns VI = OPEN
BiasV = GND
Figure 1
Figure 2
t
PZL
7.0 30.0 35.0 ns VI = 7V
BiasV = 3V
t
PHZ
Output Disable Time 1.0 6.1 6.5 ns VI = OPEN
BiasV = GND
Figure 1
Figure 2
t
PLZ
1.0 7.3 6.8 ns VI = 7V
BiasV = 3V
Symbol Parameter Typ Max Units Conditions
C
IN
Control Pin Input Capacitance 3 pF VCC = 5.0V
C
I/O
Input/Output Capacitance 5 pF VCC, OE = 5.0V
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FSTU6800
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MO-153 4.4mm Wide
Package Number M24B
24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide
Package Number MQA24
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FSTU6800 10-Bit Bus Switch with Pre-Charged Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Thin Shrink Sm all Ou tline Pa ck age (TS SO P), JE DE C MO-153, 4.4mm Wide
Package Number MTC24
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven switch t echnology used for several years in it s
74LVX3L384 (FST3384) bus switch product.
Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are dev ices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provide d in the labe l ing, can be re asonably expected to result in a significant injury to the
user.
2. A critical component i n any compo nent o f a l ife supp ort
device or system whose failure to perform can be reasonably expected to cause the failure of the l ife support
device or system, or to affect its safety or effectiveness.
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