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FSTU16861
FSTU16861 20-Bit Bus Switch with
May 2001
Revised May 2001
20-Bit Bus Switch with
General Description
The Fairchild Switch FS TU16861 provide s 20-Bits of hi ghspeed CMOS TTL-compatible bus switching. The low On
Resistance of the switch allows inputs to be connected to
outputs without adding propagation delay or generating
additional ground bounce noise.
The device is organ ized as a 10-bit or 20-Bit bus switch.
When OE
nected to Port 1B. When OE
to Port 2B. When OE
exists between the A and B Ports . The A an d B Ports a re
protected against undershoot to support an extended
range to 2.0V below ground. Fairchild’s integrated Undershoot Hardened Circuit (UHC
I/O and responds by prevent ing voltage differentials from
developing and turnin g the switch on. When OE
the switch is OPEN and a high-impedance state exists
between the two ports.
is LOW, the switch is ON and Port 1A is con-
1
is LOW, Port 2A is connected
2
is HIGH, a high imped ance state
X
) senses undersh oot a t the
−2V Undershoot Protection
Features
■ Undershoot hardened to −2V (A and B Ports)
Ω switch connection between two ports
■ 4
■ Minimal propagation delay through the switch
■ Low l
CC
■ Zero bounce in flow-through mode
■ Control inputs compatible with TTL level
■ See Application Note AN-5008 for details
is HIGH,
Ordering Code:
Order Number Package Number Package Description
FSTU16861MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also availab l e in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
−
2V Undershoot Protection
UHC is a trademark of Fairchild Semiconductor Corporation.
© 2001 Fairchild Semiconductor Corporation DS500422 www.fairchildsemi.com
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Connection Diagram Logic Diagram
FSTU16861
Pin Descriptions Truth Table
Pin Name Description
OE
1A
1B
1
n
n
, OE
, 2A
, 2B
n
n
2
Bus Switch Enables
Bus A
Bus B
Inputs Inputs/Outputs
OE
1
LL1A
LH1A
HL Z 2A
HH Z Z
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
OE
2
1A, 1B 2A, 2B
= 1B 2A = 2B
= 1B Z
= 2B
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Absolute Maximum Ratings(Note 1) Recommended Operating
Supply Voltage (VCC) −0.5V to +7.0V
DC Switch Voltage (V
DC Input Voltage (V
DC Input Diode Current (l
DC Output Current (I
DC V
/GND Current (ICC/I
CC
Storage Temperature Range (T
) (Note 2) −2.0V to +7.0V
S
) (Note 3) −0.5V to +7.0V
IN
) V
< 0V −50 mA
IK
IN
)128 mA
OUT
) ±100 mA
GND
) −65°C to +150 °C
STG
Conditions
Power Supply Operating (V
Input Voltage (V
Output Voltage (V
Input Rise and Fall Time (t
Switch Control Input 0 ns/V to 5 ns/V
Switch I/O 0 ns/V to DC
Free Air Operating Temperature (T
Note 1: The “Absolute Maximum Ratings” are those value s beyond which
the safety of the d evice cannot b e guaranteed . The device sh ould not be
operated at these limit s. The parametric values defi ned in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recomm ended O peratin g Cond itions ” table will defin e the condition s
for actual device operation.
is the volt age observed / applied at either the A or B Ports across
Note 2: V
S
the switch.
Note 3: The input and output negative voltage ratings may be exceeded if
the input and ou t put diode curre nt ratings are observed.
Note 4: Unused control inputs must be held HIGH or LOW. They may not
float.
(Note 4)
CC)
) 0V to 5.5V
IN
) 0V to 5.5V
OUT
, tf)
r
)-40 °C to +85 °C
A
4.0V to 5.5V
DC Electrical Characteristics
V
Symbol Parameter
V
IK
V
IH
V
IL
I
I
I
OZ
R
ON
I
CC
∆ I
V
IKU
Note 5: Typical values are at VCC = 5.0V and TA = +25°C
Note 6: Measured by the voltage drop between A and B pins at the indicated c urrent through the switch. On Resistanc e is determined by the lower of the
voltages on the two (A or B) pins.
Clamp Diode Voltage 4.5 −1.2 V IIN = −18 mA
HIGH Level Input Voltage 4.0–5.5 2.0 V
LOW Level Input Voltage 4.0–5.5 0.8 V
Input Leakage Current 5.5 ±1.0 µA0 ≤ VIN ≤ 5.5V
OFF-STATE Leakage Current 5.5 ±1.0 µA0 ≤ A, B ≤ V
Switch On Resistance 4.5 4 7 Ω VIN = 0V, IIN = 64 mA
(Note 6) 4.5 4 7 Ω V
Quiescent Supply Current 5.5 3 µAVIN = VCC or GND, I
Increase in I
CC
Voltage Undershoot 5.5 −2.0 V 0.0 mA ≥ I
per Input 5.5 2.5 mA One Input at 3.4V
CC
CC
(V) Min Typ
010µAV
4.5 8 14 Ω V
4.0 11 20 Ω VIN = 2.4V, IIN = 15 mA
TA = −40 °C to +85 °C
(Note 5)
Max
Units Conditions
= 5.5V
IN
CC
= 0V, IIN = 30 mA
IN
= 2.4V, IIN = 15 mA
IN
Other Inputs at VCC or GND
OE
= 5.5V
≥ −50 mA
IN
OUT
FSTU16861
= 0
3 www.fairchildsemi.com
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AC Electrical Characteristics
= −40 °C to +85 °C,
T
A
C
= 50pF, RU = RD = 500Ω
Symbol Parameter
FSTU16861
t
, t
PHL
t
PZH
t
PHZ
Note 7: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
Resistance of the s witch and the 50pF load capacitance, wh en driven by an ideal volt age source (zero output impedance).
Propagation Delay Bus-to-Bus
PLH
(Note 7)
, t
Output Enable Time 1.0 5.9 6.4 ns VI = 7V for t
PZL
, t
Output Disable Time 1.0 6.9 7.4 ns VI = 7V for t
PLZ
L
= 4.5 – 5.5V VCC = 4.0V
V
CC
Min Max Min Max
0.25 0.25 ns VI = OPEN Figures
Units Conditions
VI = OPEN for t
VI = OPEN for t
PZL
PZH
PLZ
PHZ
Capacitance (Note 8)
Symbol Parameter Typ Max Units Conditions
C
IN
C
I/O
Note 8: TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested.
Control Pin Input Capacitance 3 pF VCC = 5.0V, VIN = 0V
Input/Output Capacitance “OFF State” 6pFV
, OE = 5.0V, VIN = 0V
CC
Undershoot Characteristic (Note 9)
Symbol Parameter Min Typ Max Units Conditions
V
OUTU
Note 9: This test is intended to characterize the device’s protective capabilities by ma intaining output signal integrity d uring an input tran sient voltage
undershoot event.
Output Voltage During Undershoot 2.5 VOH - 0.3 V Figure 1
Figure
Number
2, 3
Figures
2, 3
Figures
2, 3
FIGURE 1.
Device Test Conditions Transient
Parameter Value Units
V
IN
R1 = R
V
TRI
V
CC
see Waveform V
2
100K Ω
11.0 V
5.5 V
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Input Voltage (V
) Waveform
IN
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AC Loading and Waveforms
Note: Input driven by 50Ω source terminated in 50Ω
includes load and stray capacitance
Note: C
L
Note: Input PRR = 1.0 MHz, t
= 500 ns
W
FSTU16861
FIGURE 2. AC Test Circuit
FIGURE 3. AC Waveforms
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Physical Dimensions inches (millimeters) unless otherwise noted
2V Undershoot Protection
−
FSTU16861 20-Bit Bus Switch with
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven s witch technol ogy used for several years i n its
74LVX3L384(FST3384) bus switch product.
Fairchild does not assume any responsibility for use of any circuitr y described, no circuit patent licenses are implied a nd
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are device s or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
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2. A critical component in any compon ent of a l ife supp ort
device or system whose failu re to perform can be reasonably expected to cause the failure of the li fe su pp ort
device or system, or to affect its safety or effectiveness.
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