Datasheet FAN6300HMY, FAN6300AMY Specification

December 2009

FAN6300A / FAN6300H
Highly Integrated Quasi-Resonant Current Mode
PWM Controller

FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller

Features

High-Voltage Startup


 Quasi-Resonant Operation
 Cycle-by-Cycle Current Limiting
 Peak-Current-Mode Control
 Leading-Edge Blanking (LEB)
 Internal Minimum t

OFF

 Internal 5ms Soft-Start
 Over Power Compensation
 GATE Output Maximum Voltage
 Auto-Recovery Over-Current Protection(FB Pin)
 Auto-Recovery Open-Loop Protection(FB Pin)
 VDD Pin and Output Voltage (DET Pin)

OVP Latched

 Low Frequency Operation (below 100kHz) for

FAN6300A

 High Frequency Operation (up to 190kHz) for

FAN6300H

Applications

 AC/DC NB Adapters
 Open-Frame SMPS

Description

The highly integrated FAN6300A/H of PWM controller
provides several features to enhance the performance
of flyback converters. FAN6300A is applied on quasi­resonant flyback converters where maximum operating
frequency is below 100kHz. FAN6300H is suitable for
high-frequency operation (up to 190kHz). A built-in HV
startup circuit can provide more startup current to
reduce the startup time of the controller. Once the V
voltage exceeds the turn-on threshold voltage, the HV
startup function is disabled immediately to reduce
power consumption. An internal valley voltage detector
ensures power system operates at quasi-resonant
operation over a wide-range of line voltage and any
load conditions, as well as reducing switching loss to
minimize switching voltage on drain of power MOSFET.

To minimize standby power consumption and light-load
efficiency, a proprietary green-mode function provides
off-time modulation to decrease switching frequency
and perform extended valley voltage switching to keep
to a minimum switching voltage. The operating
frequency is limited by minimum t
to 8µs in FAN6300A and 13µs to 3µs in FAN6300H, so
FAN6300H can operate at higher switching frequency
than FAN6300A.

FAN6300A/H controller also provides many protection
functions. Pulse-by-pulse current limiting ensures the
fixed-peak current limit level, even when a short circuit
occurs. Once an open-circuit failure occurs in the
feedback loop, the internal protection circuit disables
PWM output immediately. As long as V
the turn-off threshold voltage, the controller also
disables PWM output. The gate output is clamped at
18V to protect the power MOS from high gate-source
voltage conditions. The minimum t
prevents the system frequency from being too high. If
the DET pin triggers OVP, internal OTP is triggered and
the power system enters latch-mode until AC power is
removed.

The FAN6300A/H controller is available in the 8-pin
Small Outline Package (SOP) and the Dual Inline
Package (DIP).

time, which is 38µs

off

drops below

DD

time limit

OFF

DD

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN6300A/H • Rev. 1.0.1

Ordering Information

FAN6300A/H — Highly-Integrated Quasi-Resonant Current Mode PWM Controller

Part Number

FAN6300AMY Green -40°C to +125°C 8-Lead, Small Outline Package (SOP) Tape & Reel

FAN6300HMY Green -40°C to +125°C 8-Lead, Small Outline Package (SOP) Tape & Reel

FAN6300ANY Green -40°C to +125°C 8-Lead, Dual In-line Package (DIP) Tube

FAN6300HNY Green -40°C to +125°C 8-Lead, Dual In-line Package (DIP) Tube

For Fairchild’s definition of Eco Status, please vis it: http://www.fairchildsemi.com/company/green/rohs_green.html

Eco Status

Operating

Temperature Range

Package

Packing

Method

Application Diagram

Figure 1. Typical Application

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN6300A(H) Rev. 1.0.1 2

Internal Block Diagram

FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller

FB

CS

DET

HV

8

27 V

FB OLP

t

TIME -OUT

Intern a l

OTP

OVP

I

2.1ms

30 µs

Valley

Detector

HV

Timer

52m s

Starter

4.2V

S/H

2R

I

DET

0.3V

V

DET

V

DET

2.5V

0.3V

R

PW M

Current Lim it

DET OVP

Latched

Soft -S tar t

2

3

1

t

OFF

Blanking

5ms

Blanking

Circuit

Over-Power

Com pensation

I

5V

t

OFF-MIN

DET

Latched

Latched

VDD

6

Two Steps

UVLO

16 V /10 V / 8V

Latched

Intern al

Bias

SET

S

R

CLR

DRV

Q

Q

18V

5

GATE

Marking Information

4 7

GND

Figure 2. Functional Block Diagram

NC

: Fairchild Logo

Z: Plant Code

X: Year Code

Y: Week Code

TT: Die Run Code

T: Package Type (N = DIP, M = SOP)

P: Y = Green Package

M: Manufacturing Flow Code

Figure 3. Marking Diagram

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN6300A / FAN6300H • Rev. 1.0.1 3

Pin Configuration

Figure 4. Pin Configuration

Pin Definitions

Pin # Name Description

This pin is connected to an auxiliary winding of the transformer via resistors of the divider for
the following purposes:

- Generates a ZCD signal once the secondary-side switching current falls to zero.

- Produces an offset voltage to compensate the threshold voltage of the peak current limit to

provide a constant power limit. The offset is generated in accordance with the input voltage

1 DET

2 FB

3 CS

4 GND

5 GATE

6 VDD

7 NC No connect

8 HV High-voltage startup.

when PWM signal is enabled.

- Detects the valley voltage of the switching waveform to achieve the valley voltage switching

and minimize the switching losses.

A voltage comparator and a 2.5V reference voltage develop a output OVP protection. The ratio
of the divider decides what output voltage to stop gate, as an optical coupler and secondary
shunt regulator are used.

The feedback pin should to be connected to the output of the error amplifier for achieving the
voltage control loop. The FB should be connected to the output of the optical coupler if the
error-amplifier is equipped at the secondary-side of the power converter.

For the primary-side control application, FB is applied to connect a RC network to the ground
for feedback-loop compensation.

The input impedance of this pin is a 5kΩ equivalent resistance. A 1/3 attenuator connected
between the FB and the PWM circuit is used for the loop-gain attenuation. FAN6300A/H
performs an open-loop protection once the FB voltage is higher than a threshold voltage
(around 4.2V) more than 55ms.

Input to the comparator of the over-current protection. A resistor senses the switching current
and the resulting voltage is applied to this pin for the cycle-by-cycle current limit.

The power ground and signal ground. A 0.1µF decoupling capacitor placed between VDD and
GND is recommended.

Totem-pole output generates the PWM signal to drive the external power MOSFET. The
clamped gate output voltage is 18V.

Power supply. The threshold voltages for startup and turn-off are 16V and 10V, respectively.
The startup current is less than 20µA and the operating current is lower than 4.5mA.

FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN6300A / FAN6300H • Rev. 1.0.1 4

FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VDD DC Supply Voltage 30 V

VHV HV 500 V

VH GATE -0.3 25.0 V

VL VFB, VCS, V

PD Power Dissipation

TJ Operating Junction Temperature +150 °C

T

Storage Temperature Range -55 +150 °C

STG

TL Lead Temperature (Soldering 10 Seconds) +270 °C

ESD

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

2. All voltage values, except differential voltages, are given with respect to GND pin.

Human Body Model, JEDEC:JESD22-A114 3.0

Charged Device Model, JEDEC:JESD22-C101

-0.3 7.0 V

DET

SOP-8 400

DIP-8 800

1.5

mW

KV

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Conditions Min. Typ. Max. Unit

TA Operating Ambient Temperature -40 +125 °C

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN6300A / FAN6300H • Rev. 1.0.1 5

FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller

Electrical Characteristics

Unless otherwise specified, VDD=10~25V, TA=-40°C~125°C (TA=TJ).

Symbol Parameter Conditions Min. Typ. Max. Unit

VDD Section

VOP Continuously Operating Voltage 25 V

V

Turn-On Threshold Voltage 15 16 17 V

DD-ON

V

DD-PWM-OFF

V

DD-OFF

I

DD-ST

I

DD-OP

I

DD-GREEN

I

DD-PWM-OFF

V

DD-OVP

t

VDD-OVP

I

DD-LATCH

HV Startup Current Source Section

V

HV-MIN

I

HV-LC

Feedback Input Section

V

FB-OLP

t

D-OLP

PWM Off Threshold Voltage 9 10 11 V

Turn-Off Threshold Voltage 7 8 9 V

Startup Current

Operating Current

Green-Mode Operating Supply Current
(Average)

Operating Current at PWM-Off Phase

VDD=V
GATE Open

VDD=15V, fS=60KHz,
C

=2nF

L

V

=15V, fS=2KHz,

DD

C

=2nF

L

VDD=V

0.5V

-0.16V

DD-ON

DD-PWM-OFF

10 20 µA

4.5 5.5 mA

3.5 mA

­70 80 90 µA

VDD Over-Voltage Protection (Latch-Off) 26 27 28 V

VDD OVP Debounce Time 100 150 200 µs

VDD OVP Latch-Up Holding Current VDD=5V 42 µA

Minimum Startup Voltage on Pin HV 50 V

I

HV

Supply Current Drawn from Pin HV

Leakage Current After Startup

AV Input-Voltage to Current Sense Attenuation

VAC=90V(VDC=120V)
V

=0V

DD

HV=500V,
V

DD=VDD-OFF

=ΔVCS/ΔV

A

V

0<VCS<0.9

+1V

FB

1.5 4.0 mA

1 20 µA

1/2.75 1/3.00 1/3.25 V/V

ZFB Input Impedance 3 5 7 KΩ

IOZ Bias Current FB=VOZ 1.2 2 mA

VOZ Zero Duty-Cycle Input Voltage 0.8 1.0 1.2 V

Open Loop Protection Threshold Voltage 3.9 4.2 4.5 V

Debounce Time for Open-Loop/Overload
Protection

46 52 62 ms

tSS Internal Soft-Start Time 5 ms

Continued on the following page...

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN6300A / FAN6300H • Rev. 1.0.1 6

FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller

Electrical Characteristics (Continued)

Unless otherwise specified, VDD=10~25V, TA=-40°C ~125°C (TA=TJ).

Symbol Parameter Conditions Min. Typ. Max. Unit

DET Pin OVP and Valley Detection Section

V

V

t

I

DET-SOURCE

V

V

t

VALLEY-DELAY

t

t

TIME-OUT

Comparator Reference Voltage 2.45 2.50 2.55 V

DET-OVP

Av Open-Loop Gain

Bw Gain Bandwidth

Output High Voltage 4.5 V

V-HIGH

V

Output Low Voltage 0.5 V

V-LOW

Output OVP (Latched) Debounce Time 100 150 200 µs

DET-OVP

Maximum Source Current V

Upper Clamp Voltage I

DET-HIGH

Lower Clamp Voltage I

DET-LOW

Delay Time from Valley-Signal Detected to
Output Turn-On

Leading-Edge-Blanking Time for DET when

OFF-BNK

PWM MOS Turns Off

Time-Out after t

(3)

60 dB

(3)

1 MHz

=0V 1 mA

DET

=-1mA 5 V

DET

=1mA 0.1 0.3 V

DET

(3)

OFF-MIN

(3)

200 ns

FAN6300A 4.0

FAN6300H 1.5

FAN6300A 9

FAN6300H 5

µs

µs

Oscillator Section

t

Maximum On-Time 38 45 54 µs

ON-MAX

V

t

Minimum Off-Time

OFF-MIN

VN

VG

ΔV

FBG

t

STARTER

Beginning of Green-On Mode at FB Voltage
Level

Beginning of Green-Off Mode at FB Voltage
Level

Green-Off Mode VFB Hysteresis Voltage 0.05 0.10 0.20 V

Start Timer (Time-Out Timer)

FB≧VN,

FAN6300A

VFB≧VN
FAN6300H

VFB=V

G

FAN6300A

VFB=VG
FAN6300H

1.95 2.10 2.25 V

1.0 1.2 1.4 V

V

FB<VG

VFB>V

25 30 45 µs

FB-OLP

8 µs

3 µs

38 µs

13 µs

1.8 2.1 2.4 ms

Output Section

VOL Output Voltage Low

VOH Output Voltage High

tR Rising Time 145 200 ns

tF Falling Time 55 120 ns

V

Gate Output Clamping Voltage 16.7 18.0 19.3 V

CLAMP

VDD=15V,
I

=150mA

O

=12V,

V

DD

I

=150mA

O

1.5 V

7.5 V

Continued on following page…

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN6300A / FAN6300H • Rev. 1.0.1 7

FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller

Electrical Characteristics(Continued)

Unless otherwise specified, VDD=10~25V, TA=-40°C ~125°C (TA=TJ).

Symbol Parameter Conditions Min. Typ. Max. Unit

Current Sense Section

tPD Delay to Output 20 150 200 ns

I

< 74.41µA 0.82 0.85 0.88 V

V

V

SLOPE

t

V

t

LIMIT

BNK

CS-H

CS-H

Limit Voltage on CS Pin for Over-Power
Compensation

Slope Compensation

Leading-Edge-Blanking Time
(MOS Turns ON)

V

Clamped High Voltage once CS Pin

CS

Floating

(3)

Delay Time once CS Pin Floating CS Pin Floating 150 µs

Internal Over-Temperature Protection Section

T

Internal Threshold Temperature for OTP

OTP

T

OTP-HYST

Note:

3. Guaranteed by design.

Hysteresis Temperature for Internal OTP

DET

I

=550µA 0.380 0.415 0.450 V

DET

=45µs 0.3 V

t

ON

tON=0µs 0.1 V

525 625 725 ns

CS Pin Floating 4.5 5.0 V

(3)

+140 °C

(3)

+15 °C

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN6300A / FAN6300H • Rev. 1.0.1 8

Typical Performance Characteristics

Graphs are normalized at TA=25°C.

FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller

17.0

16.5

(V)

16.0

DD-ON

V

15.5

15.0

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Temp eratu re(oC)

10.00

9.80

(V)

9.60

9.40

DD-P WM -O FF

V

9.20

9.00

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Temperatur e(°C)

Figure 5. Turn-On Threshold Voltage Figure 6. PWM-Off Threshold Voltage

8.1

8.0

7.9

(V)

7.8

DD-OFF

V

7.7

7.6

7.5

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80 ℃ 95℃ 110℃ 125℃

Temperature(oC)

18

16

14

(µA)

12

DD-ST

I

10

8

6

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Temperature(°C )

Figure 7. Turn-Off Threshold Voltage Figure 8. Startup Current

4.50

4.20

3.90

(mA )

DD-OP

I

3.60

3.30

3.00

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 1 10℃ 125℃

Temperat ure(°C)

4.0

3.5

3.0

2.5

(mA)

HV

I

2.0

1.5

1.0

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Temperature(°C)

Figure 9. Operating Current Figure 10. Supply Current Drawn From HV Pin

0.32

0.31

0.30

0.29

(µA)

0.28

HV-LC

I

0.27

0.26

0.25

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Temperature(°C)

0.40

0.35

0.30

(V)

0.25

DET-LOW

V

0.20

0.15

0.10

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Temperature(oC)

Figure 11. Leakage Current After Startup Figure 12. Lower Clamp Voltage

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN6300A / FAN6300H • Rev. 1.0.1 9

Typical Performance Characteristics (Continued)

These characteristic graphs are normalized at TA = 25°C.

2.52

FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller

8.70

2.51

(V)

2.50

DET-OVP

V

2.49

2.48

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Temperature(oC)

8.40

(µs)

8.10

off-min

t

7.80

7.50

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Temperature(°C)

Figure 13. Comparator Reference Voltage Figure 14. Minimum Off Time (VFB>VN)

42.0

40.0

38.0

(μs)

36.0

OFF-MIN

t

34.0

32.0

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Temperature(oC)

2.50

2.40

2.30

(ms)

2.20

STARTER

t

2.10

2.00

1.90

-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃

Temperatur e(°C)

Figure 15. Minimum Off Time (VFB=VG) Figure 16. Start Timer (VFB<VG)

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN6300A / FAN6300H • Rev. 1.0.1 10

Operation Description

The FAN6300A/H PWM controller integrates designs to
enhance the performance of flyback converters. An
internal valley voltage detector ensures power system
operates at Quasi-Resonant (QR) operation across a
wide range of line voltage. The following descriptions
highlight some of the features of the FAN6300A/H.

Startup Current

For startup, the HV pin is connected to the line input or
bulk capacitor through an external diode and resistor,
R

, which are recommended as 1N4007 and 100kΩ.

HV

Typical startup current drawn from the HV pin is 1.2mA
and it charges the hold-up capacitor through the diode
and resistor. When the V
the startup current switches off. At this moment, the V
capacitor only supplies the FAN6300A/H to maintain V
until the auxiliary winding of the main transformer
provides the operating current.

Valley Detection

The DET pin is connected to an auxiliary winding of the
transformer via resistors of the divider to generate a
valley signal once the secondary-side switching current
discharges to zero. It detects the valley voltage of the
switching waveform to achieve the valley voltage
switching. This ensures QR operation, minimizes
switching losses, and reduces EMI. Figure 17 shows
divider resistors R
150kΩ to 220kΩ to achieve valley voltage switching.
When V

AUX

voltage is clamped to 0.3V.

DET

(in Figure 17) is negative, the DET pin

voltage level reaches V

DD

and RA. R

is recommended as

DET

DD-ON

DD

DD

,

Green-Mode Operation

The proprietary green-mode function provides off-time
modulation to linearly decrease the switching frequency
under light-load conditions. V
the voltage feedback loop, is taken as the reference. In
Figure 19, once V
linearly with lower V

is lower than VN, t

FB

. The valley voltage detection

FB

signal does not start until t
valley detect circuit is activated until t
which decreases the switching frequency and provides
extended valley voltage switching. However, in very light
load condition, it might fail to detect the valley voltage
after the t
t

TIME-OUT

(with 5µs delay for H version). Figure 20 and

delay

expires. Under this condition, an internal

OFF-MIN

signal initiates a new cycle start after a 9μs

Figure 21 show the two different conditions.

t

OFF-MIN

2.1ms

38/13μ s

8/3μ s

1.2V 2.1V

Figure 19. VFB vs. t

, which is derived from

FB

OFF-MIN

finishes. Therefore, the

OFF-MIN

OFF-MIN

Curve

OFF-MIN

increases

finishes,

V

FB

FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller

Figure 17. Valley Detect Section

The internal timer (minimum t

time) prevents gate

OFF

retriggering within 8µs (3µs for H version) after the gate
signal going-low transition. The minimum t

OFF

limit

prevents system frequency being too high. Figure 18

Figure 20. QR Operation in Extended Valley Voltage

Detection Mode

shows a typical drain voltage waveform with first valley
switching.

Figure 21. Internal t

Figure 18. First Valley Switching

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN6300A / FAN6300H • Rev. 1.0.1 11

Failure to Detect Valley Voltage

(with 5µs Delay for FAN6300H version)

Initiates New Cycle After

TIME-OUT

FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller

Current Sensing and PWM Current Limiting

Peak-current-mode control is utilized to regulate output
voltage and provide pulse-by-pulse current limiting. The
switch current is detected by a sense resistor into the
CS pin. The PWM duty cycle is determined by this
current-sense signal and V
reaches around V

LIMIT

terminated immediately. V

. When the voltage on CS

FB

= (VFB-1.2)/3, the switch cycle is

is internally clamped to a

LIMIT

variable voltage around 0.85V for output power limit.

Leading-Edge Blanking (LEB)

Each time the power MOFFET switches on, a turn-on
spike occurs on the sense resistor. To avoid premature
termination of the switching pulse, lead-edge blanking
time is built in. During the blanking period, the current limit
comparator is disabled; it cannot switch off the gate driver.

Under-Voltage Lockout (UVLO)

The turn-on, PWM-off, and turn-off thresholds are fixed
internally at 16/10/8V. During startup, the startup
capacitor must be charged to 16V through the startup
resistor to enable the IC. The hold-up capacitor
continues to supply V
from the auxiliary winding of the main transformer. V
must not drop below 10V during this startup process.
This UVLO hysteresis window ensures that hold-up
capacitor is adequate to supply V

until energy can be delivered

DD

during startup.

DD

DD

VDD Over-Voltage Protection

VDD over-voltage protection prevents damage due to
abnormal conditions. Once the V
V

over-voltage protection voltage (V

DD

for t

, the PWM pulse is disabled until the VDD

VDDOVP

voltage is over the

DD

DD-OVP

) and lasts

voltage drops below the UVLO, then starts again.

Output Over-Voltage Protection

The output over-voltage protection works by the
sampling voltage, as shown in Figure 23, after switch-off
sequence. A 4μs (1.5μs for H version) blanking time
ignores the leakage inductance ringing. A voltage
comparator and a 2.5V reference voltage develop an
output OVP protection. The ratio of the divider
determines the sampling voltage of the stop gate, as an
optical coupler and secondary shunt regulator are used.
If the DET pin OVP is triggered, the power system enters
latch-mode until AC power is removed.

Gate Output

The BiCMOS output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
18V Zener diode to protect power MOSFET transistors
against undesired over-voltage gate signals.

Over-Power Compensation

To compensate this variation for wide AC input range,
the DET pin produces an offset voltage to compensate
the threshold voltage of the peak current limit to provide
a constant-power limit. The offset is generated in
accordance with the input voltage when PWM signal is
enabled. This results in a lower current limit at high-line
inputs than low-line inputs. At fixed-load condition, the
CS limit is higher when the value of R
also affects the H/L line constant power limit.

is higher. R

DET

DET

Figure 23. Voltage Sampled After 4μs

(1.5μs for FAN6300H version) Blanking Time

After Switch-Off Sequence

Short-Circuit and Open-Loop Protection

The FB voltage increases every time the output of the
power supply is shorted or overloaded. If the FB voltage
remains higher than a built-in threshold for longer than
t

, PWM output is turned off. As PWM output is

D-OLP

turned-off, the supply voltage V

When V
V

decreases to 8V, then the controller is totally shut

DD

down. V

goes below the PWM-off threshold of 10V,

DD

is charged up to the turn-on threshold voltage

DD

of 16V through the startup resistor until PWM output is
restarted. This protection feature continues as long as
the overloading condition persists. This prevents the
power supply from overheating due to overloading.

begins decreasing.

DD

Figure 22. H/L Line Constant Power Limit

Compensated by DET Pin

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN6300A / FAN6300H • Rev. 1.0.1 12

Physical Dimensions

5.00

4.80

3.81

8

A

0.65

5

B

6.20

5.80

PIN ONE

INDICATOR

(0.33)

1.75 MAX

R0.10

R0.10

8°
0°

0.90

0.406

1

0.25

0.10

DETAIL A

SCALE: 2:1

4

1.27

0.51

0.33

0.50

0.25

SEATING PLANE

(1.04)

4.00

3.80

CMBA0.25

C

0.10 C

x 45°

GAGE PLANE

0.36

1.75

5.60

1.27

LAND PATTERN RECOMMENDATION

SEE DETAIL A

0.25

0.19

OPTION A - BEVEL EDGE

OPTION B - NO BEVEL EDGE

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13

Figure 24. 8-Pin Small Outline Package (SOP)

Package drawings are provided as a service to cust omers considering Fairchild components. Drawings may change in any manner
without notice. Pl ease note the revision and/or date on t he drawing and contact a Fairchild Semiconductor representative t o verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsem i.com/p ackagi ng/

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN6300A / FAN6300H Rev. 1.0.1 13

.

Physical Dimensions (Continued)

9.83

9.00

FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller

6.67

6.096

8.255

7.61

5.08 MAX

0.33 MIN

(0.56)

2.54

7.62

0.56

0.355

3.60

3.00

1.65

1.27

3.683

3.20

0.356

0.20

7.62

9.957

7.87

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO

JEDEC MS-001 VARIATION BA

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS ARE EXCLUSIVE OF BURRS,

MOLD FLASH, AND TIE BAR EXTRUSIONS.

D) DIMENSIONS AND TOLERANC

ES PER

ASME Y14.5M-1994

E) DRAWING FILENAME AND REVSION: MKT-N08FREV2.

Figure 25. 8-Pin Dual Inline Package (DIP)

Package drawings are provided as a service to cust omers considering Fairchild components. Drawings may change in any manner
without notice. Pl ease note the revision and/or date on t he drawing and contact a Fairchild Semiconductor representative t o verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsem i.com/p ackagi ng/

.

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN6300A / FAN6300H • Rev. 1.0.1 14

FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller

© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN6300A / FAN6300H • Rev. 1.0.1 15