Datasheet EM73PA88ABQ, EM73PA88AAQ Datasheet (ELAN)

1

* This specification are subject to be changed without notice.

EM73PA88AEM73PA88A

EM73PA88A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

10.8.2001

PreliminaryPreliminary

Preliminary

GENERAL DESCRIPTIONGENERAL DESCRIPTION

GENERAL DESCRIPTION

EM73PA88A is an advanced single chip CMOS 4-bit one-time programming (OTP) micro-controller. It contains 16K-byte ROM, 500-nibble RAM, 4-bit ALU, 13-level subroutine nesting, 22-stage time base, two 12-bit timer/ counters for the kernel function. EM73PA88A also equipped with 6 interrupt sources, 3 I/O ports (including 1 input port and 2 bidirection ports), LCD display (64x16), built-in sound generator and speech synthesizer can direct drive speaker. It's low power consumption and high speed feature are further strengten with DUAL, SLOW, IDLE and STOP operation mode for optimized power saving.

FEATURESFEATURES

FEATURES

• Operation voltage : 2.2V to 4.8V.

• Clock source : Dual clock system. Low-frequency oscillator is 32 KHz Crystal or RC oscillator and high-frequency oscillator is a built-in internal oscillator (4.6 MHz).

• Instruction set : 107 powerful instructions.

• Instruction cycle time : 1.7µs for 4.6M Hz (high speed clock). 244µs for 32768 Hz (low speed clock).

• ROM capacity : 16K x 8 bits.

• RAM capacity : 500 x 4 bits.

• Input port : 1 port (P0.0-P0.3), IDLE/STOP releasing function is available by mask option. (each input pin has a pull-up and pull-down resistor available by mask option).

• Bidrection port : 2 ports (P4, P8). IDLE/STOP release function for P8(0..3) is available by mask option.

• Built-in watch-dog-timer counter : It is available by mask option.

• 12-bit timer/counter : Two 12-bit timer/counters are programmable for timer, event counter and pulse width measurement mode.

• Built-in time base counter : 22 stages.

• Subroutine nesting : Up to 13 levels.

• Interrupt : External interrupt . . . . . . 2 input interrupt sources.

Internal interrupt . . . . . . 2 timer overflow interrupts, 1 time base interrupt.

1 speech interrupt.

• LCD driver : 64x16 dots, 1/16 duty, 1/5 bias with voltage multiplier.

• Sound effect : Tone generator and random generator.

• Speech synthesizer : 448K speech data ROM (use as 448K nibbles data ROM).

• PWM or current D/A : Output selection by mask option.

• Power saving function : SLOW, IDLE, STOP operation modes.

• Package type : Chip form 109 pins. QFP form 160 pins (AQ). QFP form 128 pins (BQ).

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EM73PA88AEM73PA88A

EM73PA88A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

PreliminaryPreliminary

Preliminary

FUNCTION BLOCK DIAGRAMFUNCTION BLOCK DIAGRAM

FUNCTION BLOCK DIAGRAM

Interrupt

Control

Time Base

Timer/Counter

(TA,TB)

System Control

Instruction Decoder Instruction Register

ROM

PC

Data Bus

Reset

Control

Clock

Generator

Timing

Generator

Clock Mode

Control

Data pointer

ACC

ALU

Flag

ZCS

Stack pointer

Stack

RAM

HR

LR

I/O Control

P0.0/WAKEUP0 P0.1/WAKEUP1 P0.2/WAKEUP2 P0.3/WAKEUP3

P4.0

P4.1

P4.2

P4.3

P8.0(INT1)/WAKEUPA

P8.1(TRGB)/WAKEUPB

P8.2(INT0)/WAKEUPC

P8.3(TRGA)/WAKEUPD

RESET

CLK

LXOUT

Speech

synthesizer

LCD Driver

V1~V5

VA,VB

COM0~COM15

BZ1

BZ2

SEG0~SEG63

LXIN

Sound

Generator

3

* This specification are subject to be changed without notice.

EM73PA88AEM73PA88A

EM73PA88A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

10.8.2001

PreliminaryPreliminary

Preliminary

PIN ASSIGNMENTPIN ASSIGNMENT

PIN ASSIGNMENT

123456789

101112131415161718192021222324252627282930

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

110

109

108

107

106

105

104

103

102

101

100

99989796959493929190898887868584838281

141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160

SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34

NC NC NC NC NC NC NC NC NC

NGNGNG

SEG33

SEG32

P8.0/DIN

P8.1/DOUT

P8.2

P8.3

P4.0

P4.1

P4.2

P4.3

P0.0/ACLK

P0.1/PGM

P0.2/OE

P0.3/DCLK

VDD2

BZ1

BZ2

VSS

RESET

CLK

VPP

LXIN

LXOUT

VDD

V1V2V3

SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 NC NC NC NC NC NC NC NC NC

SEG62

SEG63

COM15

COM14

COM13

COM12

COM11

COM10

COM9

COM8

COM7

COM6

COM5

COM3

COM2

COM1

COM0

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8NCNC

NC

EM73PA88AAQ

QFP 160

313233343536373839

40

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

120

119

118

117

116

115

114

113

112

111

121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140

V4

V5

VA

VB

SEG31

SEG30

NC

SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18

NC NC NC NC NC NC NC NC NC NC

SEG56

SEG57

SEG58

SEG59

SEG60

SEG61

NCNCNC

SEG55

SEG48 SEG47 SEG46 SEG45

SEG52 SEG51 SEG50 SEG49

NC

NC SEG54 SEG53

NC

COM4

4

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EM73PA88A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

PreliminaryPreliminary

Preliminary

PIN ASSIGNMENTPIN ASSIGNMENT

PIN ASSIGNMENT

123456789

101112131415161718192021222324252627282930

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

102

101

100

99989796959493929190898887868584838281

109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128

NC NC

NCNCNC

EM73PA88ABQ

QFP 128

31323334353637

38

64 63 62 61

103 104 105 106 107 108

NCNCNC

NC NC NC

NC

40 39

NC NC

807978777675747372717069686766

65

NC

P8.0/DIN

P8.1/DOUT

P8.2

P8.3

P4.0

P4.1

P4.2

P4.3

P0.0/ACLK

P0.1/PGM

P0.2/OE

P0.3/DCLK

VDD2

BZ1

BZ2

VSS

RESET

CLK

VPP

LXIN

LXOUT

VDD

V1V2V3V4V5

VA

VB

SEG31

SEG32

SEG30

SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29

SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18

SEG62

SEG63

COM15

COM14

COM13

COM12

COM11

COM10

COM9

COM8

COM7

COM6

COM5

COM3

COM2

COM1

COM0

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG56

SEG57

SEG58

SEG59

SEG60

SEG61

COM4

SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34

SEG48 SEG47 SEG46 SEG45

SEG52 SEG51 SEG50 SEG49

SEG54 SEG53

SEG55

SEG33

5

* This specification are subject to be changed without notice.

EM73PA88AEM73PA88A

EM73PA88A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

10.8.2001

PreliminaryPreliminary

Preliminary

SymbolSymbol

Symbol

Pin-type Pin-type

Pin-type

FunctionFunction

Function

VDD Power supply (+).

Power supply (+) for programming OTP. VDD2 Power supply (+). VSS Power supply (-).

Power supply (-) for programming OTP. RESET RESET-A System reset input signal, low active.

Reset input signal for programming OTP.

Always internal pull-up. CLK OSC-G Capacitor connecting pin for internal high frequency oscillator. LXIN OSC-B/OSC-H Crystal or RC osc connecting pin for low speed clock source. LXOUT OSC-B Crystal osc connecting pin for low speed clock source. P0(0..3)/WAKEUP0..3 INPUT-B 4-bit input port with IDLE/STOP releasing function

P0.0/ACLK : address counter clock for programming OTP.

P0.1/PGMB : program data to OTP cells for programming OTP.

P0.2/OEB : data output enable for programming OTP.

P0.3/DCLK : data in/out clock signal for programming OTP.

mask option : wakeup enable, pull-up

wakeup enable, none wakeup disable, pull-up wakeup disable, pull-down wakeup disable, none

P4(0..3) I/O-O 4-bit bidirection I/O port with high current source.

mask option : open-drain

push-pull, high current PMOS

push-pull, low current PMOS P8.0(INT1)/WAKEUPA I/O-L 2-bit bidirection I/O port with external interrupt sources input and IDLE P8.2(INT0)/WAKEUPC /STOP releasing function.

P8.0/DIN : data input for programming OTP. mask option : wakeup enable, push-pull

wakeup disable, push-pull

wakeup disable, open-drain P8.1(TRGB)/WAKEUPB I/O-L 2-bit bidirection I/O port with time/counter A,B external input and IDLE P8.3(TRGA)/WAKEUPD /STOP releasing function.

P8.1/DOUT : data output for programming OTP. mask option : wakeup enable, push-pull

wakeup disable, push-pull

wakeup disable, open-drain BZ1 Tone / Speech PWM / D/A output pin. BZ2 Tone / Speech PWM output pin. V1, V2, V3, V4, V5, LCD bias pins. VA, VB COM0~COM15 LCD common output pins. SEG0~SEG63 LCD segment output pins. TEST/VPP Test pin must be floating.

VPP : high voltage (12V) power source for programming OTP.

PIN DESCRIPTIONSPIN DESCRIPTIONS

PIN DESCRIPTIONS

6

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EM73PA88A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

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PreliminaryPreliminary

Preliminary

.

SCALL, subroutine call entry address

Data table for [LDAX],[LDAXI] instruction

Subroutine call entry address designated by [LCALL a] instruction

Bank 1

Bank 2

Bank 3

Reset start address INT0 ; interrupt service routine entry address

TRGA TRGB TBI INT1

0000h 0002h 0004h 0006h 0008h 000Ah 000Ch 000Eh 0086h

07FFh 0800h

0FFFh 1000h

1FFFh

SPI

FUNCTION DESCRIPTIONSFUNCTION DESCRIPTIONS

FUNCTION DESCRIPTIONS

PROGRAM ROM ( 16K X 8 bits )PROGRAM ROM ( 16K X 8 bits )

PROGRAM ROM ( 16K X 8 bits )

16 K x 8 bits program ROM contains user's program and some fixed data. The basic structure of the program ROM may be categorized into 5 partitions.

1. Address 0000h: Reset start address.

2. Address 0002h - 000Ch : 6 kinds of interrupt service routine entry addresses.

3. Address 000Eh-0086h : SCALL subroutine entry address, only available at 000Eh, 0016h, 001Eh, 0026h, 002Eh, 0036h, 003Eh, 0046h, 004Eh, 0056h, 005Eh, 0066h, 006Eh, 0076h, 007Eh,0086h.

4. Address 0000h - 07FFh : LCALL subroutine entry address.

5. Address 0000h - 1FFFh : Except used as above function, the other region can be used as user's program and

data region.

address Bank 0 :

7

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EM73PA88A

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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

10.8.2001

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User's program and fixed data are stored in the program ROM. User's program is executed using the PC value to fetch an instruction code. The 16Kx8 bits program ROM can be divided into 4 banks. There are 4Kx8 bits per bank. The program ROM bank is selected by P3(1..0). The program counter is a 13-bit binary counter. The PC and P3 are initialized to "0" during reset. When P3(1..0)=00B, the bank0 and bank1 of program ROM will be selected. P3(1..0)=01B, the bank0 and bank2 will be selected.

Address P3=xx00B P3=xx01B P3=xx10B

0000h

: : Bank0 Bank0 Bank0

0FFFh

1000h

: : Bank1 Bank2 Bank3

1FFFh

PROGRAM EXAMPLE :

BANK 0

START: :

: : LDIA #00H ; set program ROM to bank1 OUTA P3 B XA1 :

XA : :

: LDIA #01H ; set program ROM to bank2 OUTA P3 B XB1 :

XB : :

: LDIA #02H ; set program ROM to bank3 OUTA P3 B XC1 :

XC : :

: BXD

XD : :

: :

; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

BANK 1

XA1 : :

: BXA :

XA2 : :

8

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B XA2 :

; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

BANK 2

XB1 : :

: BXB :

XB2 : :

B XB2 :

; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

BANK 3

XC1 : :

: BXC :

XC2 : :

B XC2

Fixed data can be read out by table-look-up instruction. Table-look-up instruction is requires the Data point (DP) to indicate the ROM address in obtaining the ROM code data (Except bank 0) :

LDAXLDAX

LDAX

Acc Acc

Acc

←←

←

ROM[DP] ROM[DP]

ROM[DP]

LL

L

LDAXILDAXI

LDAXI

Acc Acc

Acc

←←

←

ROM[DP] ROM[DP]

ROM[DP]

HH

H

,DP+1,DP+1

,DP+1

DP is a 12-bit data register that stores the program ROM address as pointer for the ROM code data. User has to initially load ROM address into DP with instructions "STADPL", and "STADPM, STADPH", then to obtain the lower nibble of ROM code data by instruction "LDAX" and higher nibble by instruction "LDAXI"

PROGRAM EXAMPLE: Read out the ROM code of address 1777h by table-look-up instruction.

LDIA #07h; STADPL ; [DP]L ← 07h STADPM ; [DP]M ← 07h STADPH ; [DP]H ← 07h, Load DP=777h : LDL #00h; LDH #03h; LDAX ; ACC ← 6h STAMI ; RAM[30] ← 6h LDAXI ; ACC ← 5h STAM ; RAM[31] ← 5h ; ORG 1777h DATA 56h;

DATA RAM ( 500-nibble ) DATA RAM ( 500-nibble )

DATA RAM ( 500-nibble )

A total 500 - nibble data RAM is available from address 000 to 1FFh Data RAM includes the zero page region, stacks and data areas.

9

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ZERO- PAGE:

From 000h to 00Fh is the zero-page location. It is used as the zero-page address mode pointer for the instruction of "STD #k,y; ADD #k,y; CLR y,b; CMP k,y".

PROGRAM EXAMPLE: To write immediate data "07h" to RAM [03] and to clear bit 2 of RAM [0Eh].

STD #07h, 03h ; RAM[03] ← 07h CLR 0Eh,2 ; RAM[0Eh]2 ← 0

STACK:

There are 13 - level (maximum) stack levels that user can use for subroutine (including interrupt and CALL). User can assign any level be the starting stack by providing the level number to stack pointer (SP). When an instruction (CALL or interrupt) is invoked, before enter the subroutine, the previous PC address is saved into the stack until returned from those subroutines, the PC value is restored by the data saved in stack.

DATA AREA:

Except the area used by user's application, the whole RAM can be used as data area for storing and loading general data.

ADDRESSING MODE

The 500 nibble data memory consists of two banks (bank 0 and bank 1). There are 244x4 bits (address 000h~0F3h) in bank 0 and 256x4 bits (address 100h~1FFh) in bank 1.

Increment

Address

020h - 02Fh

0C0h - 0CFh

0D0h - 0DFh

0E0h - 0EFh

Level 0 Level 4 Level 8

Level 12

Level 1 Level 5 Level 9

Level 2 Level 6

Level 10

Level 3 Level 7

Level 11

Increment

Zero-page

000h - 00Fh 010h - 01Fh

0F0h - 0F3h

: : :

110h - 11Fh

1E0h - 1EFh

1F0h - 1FFh

100h - 10Fh

: : :

Bank 0

Bank 1

10

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PreliminaryPreliminary

Preliminary

P9.3

instruction field

RAM address

xxxxxxxx

0

instruction field

RAM address

yyyy

0000

yyyy

PROGRAM EXAMPLE: Load the data of RAM address "143h" to RAM address "023h".

SEP P9,3 ; P9.3← 1 LDA 43h ; Acc← RAM[143h] CLP P9,3 ; P9.3← 0 STA 23h ; RAM[023h]← Acc

(3) Zero-page addressing mode:

The zero-page is in the bank 0 (address 000h~00Fh). The address is the lower 4 bits code of the second byte in the instruction field.

PROGRAM EXAMPLE: Write immediate "0Fh" to RAM address "005h".

STD #0Fh, 05h ; RAM[05h]← 0Fh

The bank is selected by P9.3. When P9.3 is cleared to "0", the bank 0 is selected. When P9.3 is set to "1", the bank 1 is selected. The Data Memory consists of three Address mode, namely -

(1) Indirect addressing mode:

The address in the bank is specified by the HL registers.

PROGRAM EXAMPLE: Load the data of RAM address "143h" to RAM address "032h".

SEP P9,3 ; P9.3← 1 LDL #3h ; LR← 3 LDH #4h ; HR← 4 LDAM ; Acc← RAM[134h] CLP P9,3 ; P9.3← 0 LDL #2h ; LR← 2 LDH #3h ; HR← 3 STAM ; RAM[023h]← Acc

(2) Direct addressing mode:

The address in the bank is directly specified by 8 bits code of the second byte in the instruction field.

P9.3 HR LR

R

AM address

11

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10.8.2001

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Preliminary

+2

PROGRAM COUNTER (16K ROM)PROGRAM COUNTER (16K ROM)

PROGRAM COUNTER (16K ROM)

Program counter ( PC ) is composed by a 13-bit counter, which indicates the next executed address for the instruction of program ROM instruction. For BRANCH and CALL instructions, PC is changed by instruction indicating. PC only can indicate the address from 0000h-1FFFh. The bank number is decided by P3.

(1) Branch instruction:(1) Branch instruction:

(1) Branch instruction:

SBR aSBR a

SBR a

Object code: 00aa aaaa Condition: SF=1; PC ← PC

12-6.a

( branch condition satisified )

PC Hold original PC value+1 aaaaaa

SF=0; PC← PC +1( branch condition not satisified)

PC Original PC value + 1

LBR aLBR a

LBR a

Object code: 1100 aaaa aaaa aaaa Condition: SF=1; PC ← PC

12.a

( branch condition satisified )

PC

Hold

a a a a a aaaaaaa

SF=0; PC← PC +2( branch condition not satisified)

PC Original PC value + 2

SLBR aSLBR a

SLBR a

Object code: 0101 0101 1100 aaaa aaaa aaaa (a:1000h~1FFFh)

0101 0111 1100 aaaa aaaa aaaa (a:0000h~0FFFh)

Condition: SF=1; PC ← a ( branch condition satisified)

PCaaaaaaaaaaaa a

SF=0 ; PC ← PC + 3 ( branch condition not satisified )

PC Original PC value + 3

(2) Subroutine instruction:(2) Subroutine instruction:

(2) Subroutine instruction:

SCALL aSCALL a

SCALL a

Object code: 1110 nnnn Condition : PC ← a ; a=8n+6 ; n=1..Fh ; a=86h, n=0

PC00000aaaaa aaa

LCALL aLCALL a

LCALL a

Object code: 0100 0aaa aaaa aaaa Condition: PC ← a

12

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PreliminaryPreliminary

Preliminary

(3) Interrupt acceptance operation:(3) Interrupt acceptance operation:

(3) Interrupt acceptance operation:

When an interrupt is accepted, the original PC is pushed into stack and interrupt vector will be loaded into PC. The interrupt vectors are as follows :

INT0INT0

INT0 (External interrupt from P8.2)

PC00000000000 1 0

SPISPI

SPI (speech end interrupt)

PC000000000010 0

TRGATRGA

TRGA (Timer A overflow interrupt)

PC0000000000 1 1 0

TRGBTRGB

TRGB (Time B overflow interrupt)

PC00000000 0 1 0 0 0

TBI TBI

TBI (Time base interrupt)

PC00000000 0 1 0 1 0

INT1INT1

INT1 (External interrupt from P8.0)

PC00000000 0 1 1 0 0

(4) Reset operation:(4) Reset operation:

(4) Reset operation:

PC00000000000 0 0

PC00aaaaaaaaaa a

RETRET

RET

Object code: 0100 1111 Condition: PC ← STACK[SP]; SP + 1

PC The return address stored in stack

RT IRT I

RT I

Object code: 0100 1101 Condition : FLAG. PC ← STACK[SP]; EI ← 1; SP + 1

PC The return address stored in stack

13

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Preliminary

(5) Other operations:(5) Other operations:

(5) Other operations:

For 1-byte instruction execution: PC + 1 For 2-byte instruction execution: PC + 2 For 3-byte instruction execution: PC + 3

ACCUMULATORACCUMULATOR

ACCUMULATOR

Accumulator(ACC) is a 4-bit data register for temporary data storage. For the arithematic, logic and comparative opertion.., ACC plays a role which holds the source data and result.

FLAGSFLAGS

FLAGS

There are three kinds of flag, CF (Carry flag), ZF (Zero flag) and SF (Status flag), these three 1-bit flags

are included by the arithematic, logic and comparative .... operation.

All flags will be put into stack when an interrupt subroutine is served, and the flags will be restored after RTI instruction is executed.

(1) Carry Flag ( CF )

The carry flag is affected by the following operations: a. Addition : CF as a carry out indicator, under addition operation, when a carry-out occures, the CF is "1",

likewise, if the operation has no carry-out, CF is "0".

b. Subtraction : CF as a borrow-in indicator, under subtraction operation, when a borrow occures, the CF

is "0", likewise, if there is no borrow-in, the CF is "1".

c. Comparision: CF as a borrow-in indicator for Comparision operation as in the subtraction operation.

d. Rotation: CF shifts into the empty bit of accumulator for the rotation and holds the shift out data after

rotation.

e. CF test instruction : Under TFCFC instruction, the CF content is sent into SF then clear itself as "0".

Under TTSFC instruction, the CF content is sent into SF then set itself as "1".

(2) Zero Flag ( ZF )

ZF is affected by the result of ALU, if the ALU operation generates a "0" result, the ZF is "1", likewise, the ZF is "0".

(3) Status Flag ( SF )

The SF is affected by instruction operation and system status.

a. SF is initiated to "1" for reset condition.

b. Branch instruction is decided by SF, when SF=1, branch condition is satisified, likewise, when SF = 0,

branch condition is unsatisified.

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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

PreliminaryPreliminary

Preliminary

PROGRAM EXAMPLE:

Check following arithematic operation for CF, ZF, SF

CF ZF SF

LDIA #00h; - 1 1 LDIA #03h; - 0 1 ADDA #05h; - 0 1 ADDA #0Dh; - 0 0 ADDA #0Eh; - 0 0

ALUALU

ALU

The arithematic operation of 4 - bit data is performed in ALU unit . There are 2 flags that can be affected by the result of ALU operation, ZF and SF. The operation of ALU is affected by CF only.

ALU STRUCTUREALU STRUCTURE

ALU STRUCTURE

ALU supported user arithematic operation functions, including Addition, Subtraction and Rotaion.

ALU FUNCTIONALU FUNCTION

ALU FUNCTION

(1) Addition:

ALU supports addition function with instructions ADDAM, ADCAM, ADDM #k, ADD #k,y .... .

The addition operation affects CF and ZF. Under addition operation, if the result is "0", ZF will be "1", otherwise, ZF will be "0", When the addition operation has a carry-out. CF will be "1", otherwise, CF will be "0".

EXAMPLE:

Operation Carry Zero 3+4=7 0 0 7+F=6 1 0 0+0=0 0 1 8+8=0 1 1

(2) Subtraction:

ALU supports subtraction function with instructions SUBM #k, SUBA #k, SBCAM, DECM... . The

subtraction operation affects CF and ZF. Under subtraction operation, if the result is negative, CF will be "0", and a borrow out, otherwise, if the result is positive, CF will be "1". For ZF, if the result of subtraction operation is "0", the ZF is "1", likewise, ZF is "1".

ZF CF SF

ALU

DATA BUS

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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

10.8.2001

PreliminaryPreliminary

Preliminary

ACC

CF

MSB LSB

3 2 1 0

H REGISTER

3 2 1 0

L REGISTER

ACC

CF

MSB LSB

EXAMPLE:

Operation Carry Zero 8-4=4 1 0 7-F= -8(1000) 0 0 9-9=0 1 1

(3) Rotation:

Two types of rotation operation are available, one is rotation left, the other is rotation right. RLCA instruction rotates Acc value counter-clockwise, shift the CF value into the LSB bit of Acc and hold the shift out data in CF.

RRCA instruction operation rotates Acc value clockwise, shift the CF value into the MSB bit of Acc and hold the shift out data in CF.

PROGRAM EXAMPLE: To rotate Acc clockwise (right) and shift a "1" into the MSB bit of Acc.

TTCFS; CF ← 1 RRCA; rotate Acc right and shift CF=1 into MSB.

HL REGISTERHL REGISTER

HL REGISTER

HL register are two 4-bit registers, they are used as a pair of pointer for the RAM memoryaddress. They are used as also 2 independent temporary 4-bit data registers. For certain instructions, L register can be a pointer to indicate the pin number ( Port4 only ).

HL REGISTER STRUCTUREHL REGISTER STRUCTURE

HL REGISTER STRUCTURE

HL REGISTER FUNCTIONHL REGISTER FUNCTION

HL REGISTER FUNCTION

(1)HL register is used as a temporary register for instructions : LDL #k, LDH #k, THA, THL, INCL, DECL,

EXAL, EXAH.

PROGRAM EXAMPLE:

Load immediate data "5h" into L register, "0Dh" into H register. LDL #05h; LDH #0Dh;

(2) HL register is used as a pointer for the address of RAM memory for instructions : LDAM, STAM, STAMI ..,

PROGRAM EXAMPLE: Store immediate data "#0Ah" into RAM of address 35h.

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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

PreliminaryPreliminary

Preliminary

CLOCK AND TIMING GENERATORCLOCK AND TIMING GENERATOR

CLOCK AND TIMING GENERATOR

The clock generator is supported by a dual clock system. The high-frequency oscillator is internal oscillator, the working frequency is 4.6 MHz. The low-frequency oscillator may be sourced from crystal or RC osc, the working frequency is 32 KHz.

CLOCK GENERATOR STRUCTURECLOCK GENERATOR STRUCTURE

CLOCK GENERATOR STRUCTURE

There are two clock generator for system clock control unit, P14 is the status register that hold the CPU status. P16, P19 and P22 are the command register for system clock mode control.

LDL #5h; LDH #3h; STDMI #0Ah; RAM[35] ← Ah

(3) L register is used as a pointer to indicate the bit of I/O port for instructions : SELP, CLPL, TFPL,

(When LR = 0 indicate P4.0)

PROGRAM EXAMPLE: To set bit 0 of Port4 to "1"

LDL #00h; SEPL ; P4.0 ← 1

STACK POINTER (SP)STACK POINTER (SP)

STACK POINTER (SP)

Stack pointer is a 4-bit register that stores the present stack level number. Before using stack, user must set the SP value first, CPU will not initiate the SP value after reset condition. When a new subroutine is received, the SP is decreased by one automatically, likewise, if returning from a subroutine, the SP is increased by one. The data transfer between ACC and SP is done with instructions "LDASP" and "STASP".

DATA POINTER (DP)DATA POINTER (DP)

DATA POINTER (DP)

Data pointer is a 12-bit register that stores the ROM address can indicating the ROM code data specified by user (refer to data ROM).

High-frequency

generator

System clock

mode control

fc

fs

System control

Crystal connection

LXIN

open

LXOUT

P14

P16

P22

P19

Low-frequency

generator

LXIN

CLK

LXOUT

LXIN

LXOUT

VDD

R

RC oscillator connection

R=1MΩ

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EM73PA88AEM73PA88A

EM73PA88A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

10.8.2001

PreliminaryPreliminary

Preliminary

SYSTEM CLOCK MODE CONTROLSYSTEM CLOCK MODE CONTROL

SYSTEM CLOCK MODE CONTROL

The system clock mode controller can start or stop the high-frequency and low-frequency clock oscillator and switch between the basic clocks. EM73PA88A has four operation modes (DUAL, SLOW, IDLE and

STOP operation modes).

Operation ModeOperation Mode

Operation Mode

OscillatorOscillator

Oscillator

System ClockSystem Clock

System Clock

Available functionAvailable function

Available function

One instruction cycleOne instruction cycle

One instruction cycle

NORMAL High, Low frequency High frequency clock LCD, speech, sound gen. 8 / fc

SLOW Low frequency Low frequency clock LCD 8 / fs

IDLE Low frequency CPU stops LCD -

STOP None CPU stops All disable -

DUAL OPERATION MODEDUAL OPERATION MODE

DUAL OPERATION MODE

The 4-bit µc is in the DUAL operation mode when the CPU is reseted. This mode is dual clock system (high-frequency and low-frequency clocks oscillating). It can be changed to SLOW or STOP operation mode with the command register (P22 or P16). LCD display, speech synthesizer and sound generator are available for the DUAL operation mode.

SLOW OPERATION MODESLOW OPERATION MODE

SLOW OPERATION MODE

The SLOW operation mode is single clock system (low-frequency clock oscillating). It can be changed to the DUAL operation mode with the command register (P22), STOP operation mode with P16 and IDEL operation mode with P19.

LCD display is available for the SLOW operation mode. Speech synthesizer and sound generator are disabled in this mode.

STOP

operation

mode

NORMAL

operation

mode

IDLE (CPU

stops)

SLOW

operation

mode

RESET

operation

High osc : stopped Low osc : stopped

High osc : stopped Low osc : oscillating

High osc : oscillating Low osc : oscillating

High osc : stopped Low osc : oscillating

Command

(P16)

Command

(P16)

Command

(P22)

Command

(P22)

Command

(P19)

Reset

Reset release

I/O wakeup

I/O or internal timer wakeup

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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

PreliminaryPreliminary

Preliminary

P22 32 1 0 Initial value : 0000

* SOM

SOM Select operation mode 0 0 0 DUAL operation mode 1 * * SLOW operation mode

P14 32 10 Initial value : *000

* WKS LFS CPUS

LFS Low-frequency status CPUS CPU status

0 LXIN source is not stable 0 DUAL operation mode 1 LXIN source is stable 1 SLOW operation mode

WKS Wakeup status

0 Wakeup not by internal timer 1 Wakeup by internal timer

Port14 is the status register for CPU. P14.0 (CPU status) and P14.1 (Low-frequency status) are read-only bits. P14.2 (wakeup status) will be set as "1" when CPU is waked by internal timer. P14.2 will be cleared as "0" when user out data to P14.

IDLE OPERATION MODEIDLE OPERATION MODE

IDLE OPERATION MODE

The IDLE operation mode suspends all CPU functions except the low-frequency clock oscillation and the LCD driver. It keeps the internal status with low power consumption without stopping the slow clock oscillator and LCD display.

LCD display is available for the IDLE operation mode. Sound generator is disabled in this mode. The IDLE operation mode will be wakeup and return to the SLOW operation mode by the internal timing generator or I/O pins (P0(0..3)/WAKEUP 0..3 and P8(0..3)/WAKEUPA..D).

P19 32 10 Initial value : 0000

* IDME SIDR

IDME Enable IDLE mode SIDR Select IDLE releasing condition

1 Enable IDLE mode 0 0 P0(0..3), P8(0..3) pin input 0 no function 0 1 P0(0..3), P8(0..3) pin input and 1 sec signal

1 0 P0(0..3), P8(0..3) pin input and 0.5 sec signal 1 1 P0(0..3), P8(0..3) pin input and 15.625 ms signal

STOP OPERATION MODESTOP OPERATION MODE

STOP OPERATION MODE

The STOP operation mode suspends system operation and holds the internal status immediately before the suspension with low power consumption. This mode will be released by reset or I/O pins (P0(0..3)/ WAKEUP 0..3 and P8(0..3)/WAKEUP A..D).

LCD display and sound generator are disabled in the STOP operation mode.

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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

10.8.2001

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Preliminary

P16 32 1 0 Initial value : 0000

* SPME SWWT

SPME Enable STOP mode SWWT Set wake-up warm-up time

1 Enable STOP mode 0 0 2

14

/LXIN

0 no function 0 1 210/LXIN

10 2

12

/LXIN

1 1 no function

TIME BASE INTERRUPT (TBI )TIME BASE INTERRUPT (TBI )

TIME BASE INTERRUPT (TBI )

The time base can be used to generate a single fixed frequency interrupt. Eight types of frequencies can be selected with the "P25" setting.

P25 3 2 1 0

initial value : 0000

P25 DUAL operation mode SLOW operation mode

0 0 x x Interrupt disable Interrupt disable 0 1 0 0 Interrupt frequency LXIN / 2

3

Hz Reserved 0 1 0 1 Interrupt frequency LXIN / 24 Hz Reserved 0 1 1 0 Interrupt frequency LXIN / 25 Hz Reserved 0 1 1 1 Interrupt frequency LXIN / 2

14

Hz Interrupt frequency LXIN / 2

14

Hz 1 1 0 0 Interrupt frequency LXIN / 21 Hz Reserved 1 1 0 1 Interrupt frequency LXIN / 26 Hz Interrupt frequency LXIN / 26 Hz 1 1 1 0 Interrupt frequency LXIN / 28 Hz Interrupt frequency LXIN / 28 Hz 1 1 1 1 Interrupt frequency LXIN / 2

10

Hz Interrupt frequency LXIN / 2

10

Hz 1 0 x x Reserved Reserved

TIMER / COUNTER ( TIMERA, TIMERB)TIMER / COUNTER ( TIMERA, TIMERB)

TIMER / COUNTER ( TIMERA, TIMERB)

Timer/counters support three special functions:

1. Even counter

2. Timer.

3. Pulse-width measurement.

These three functions can be executed by 2 timer/counter independently. With timerA, the counter data is saved in timer register TAH, TAM, TAL. User can set counter initial value and read the counter value by instruction "LDATAH(M,L)" and "STATAH(M,L)". With timer B register is TBH, TBM, TBL and the W/R instruction are "LDATBH (M,L)" and "STATBH (M,L)".

The basic structure of timer/counter is composed by two identical counter module, these two modules can be set initial timer or counter value to the timer registers, P28 and P29 are the command registers for timerA and timer B, user can choose different operation modes and internal clock rates by setting these two registers. When timer/counter overflows, it will generate a TRGA(B) interrupt request to interrupt control unit.

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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

PreliminaryPreliminary

Preliminary

Port 28

3 2 1 0

TMSA IPSA

Initial state: 0000

TIMER/COUNTER MODE SELECTION

TMSA (B) Function description

0 0 Stop 0 1 Event counter mode 1 0 Timer mode 1 1 Pulse width measurement mode

Port 29

3 2 1 0

TMSB IPSB

Initial state: 0000

INTERRUPT CONTROL

TRGA request

P8.3/ TRGA

EVENT COUNTER CONTROL

TIMER CONTROL

internal clock

P28

12 BIT COUNTER

TMSA IPSA

DATA BUS

P8.1/ TRGB

EVENT COUNTER CONTROL

TIMER CONTROL

internal clock

P29

12 BIT COUNTER

TMSB IPSB

TRGB request

PULSE-WIDTH MEASUREMENT

CONTROL

PULSE-WIDTH MEASUREMENT

CONTROL

TIMER/COUNTER CONTROLTIMER/COUNTER CONTROL

TIMER/COUNTER CONTROL

P8.1/TRGB, P8.3/TRGA are the external timer inputs for timerB and timerA, they are used in event counter and pulse-width measurement mode.

Timer/counter command port: P28 is the command port for timer/counterA and P29 is for the timer/ counterB.

IPSA(B) DUAL mode

0 0 LXIN/2 Hz

0 1 LXIN/2 Hz

1 0 LXIN/2 Hz

1 1 LXIN/2 Hz

INTERNAL PULSE-RATE SELECTION

3

7

11

15

7

11

15

SLOW mode

Reserved

LXIN/2 Hz

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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

10.8.2001

PreliminaryPreliminary

Preliminary

PROGRAM EXAMPLE: To generate TRGA interrupt request after 60 ms with system clock LXlN=32KHz

LDIA #0100B; EXAE; enable mask 2 EICIL 110111b; interrupt latch ←0, enable EI LDIA #0Ah; STATAL; LDIA #00h; STATAM; LDIA #0Fh; STATAH; LDIA #1000B; OUTA P28; enable timerA with internal pulse rate: LXIN/23 Hz

NOTE: The preset value of timer/counter register is calculated as following procedure.

Internal pulse rate: LXIN/2

3

; LXIN = 32KHz The time of timer counter count one = 23 /LXIN = 8/32768=0.244ms The number of internal pulse to get timer overflow = 60 ms/ 0.244ms = 245.901= 0F6h The preset value of timer/counter register = 1000h - 0F6h = F0Ah

PULSE WIDTH MEASUREMENT MODE

Internal pulse

TimerB (TimerA )value

n n+1 n+2 n+3 n+4 n+5 n+6

n+7

P8.1/TRGB (P8.3/TRGA)

TimerB (TimerA) value n n+1 n+2 n+3 n+4 n+5 n+6

TIMER/COUNTER FUNCTIONTIMER/COUNTER FUNCTION

TIMER/COUNTER FUNCTION

Timer/counterA,B are programmable for timer, event counter and pulse width measurement mode. Each timer/counter can execute any of these functions independently.

EVENT COUNTER MODE

under event counter mode, the timer/counter is increased by one at any rising edge of P8.1/TRGB for timerB (P8.3/TRGA for timer A). When timerB (timerA) counts overflow, it will provide an interrupt request TRGB (TRGA) to interrupt control unit.

PROGRAM EXAMPLE: Enable timerA with P28

LDIA #0100b; OUTA P28; Enable timerA with event counter mode

TIMER MODE

Under timer mode ,the timer/counter is increased by one at any rising edge of internal pulse. User can choose up to 4 types of internal pulse rate by setting IPSB for timerB (IPSA for timerA). When timer/counter counts overflow, an interrupt request will be sent to interrupt control unit.

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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

PreliminaryPreliminary

Preliminary

PROGRAM EXAMPLE: Enable timerA by pulse width measurement mode.

LDIA #1100b; OUTA P28; Enable timerA with pulse width measurement mode.

INTERRUPT FUNCTIONINTERRUPT FUNCTION

INTERRUPT FUNCTION

Six interrupt sources are available, 2 from external interrupt sources and 4 from internal interrupt sources. Multiple interrupts are admitted according to their priority.

TypeType

Type

Interrupt sourceInterrupt source

Interrupt source

PriorityPriority

Priority

InterruptInterrupt

Interrupt

InterruptInterrupt

Interrupt

Program ROMProgram ROM

Program ROM

LatchLatch

Latch

Enable conditionEnable condition

Enable condition

entry addressentry address

entry address

External External interrupt(INT0) 1 IL5 EI=1 002h Internal speech end interrupt (SPI) 2 IL4 EI=1, MASK3=1 004h Internal TimerA overflow interrupt (TRGA) 3 IL3 EI=1, MASK2=1 006h Internal TimerB overflow interrupt (TRGB) 4 IL2 EI=1, MASK1=1 008h Internal Time base interrupt(TBI) 5 IL1 00Ah External External interrupt(INT1) 6 IL0 EI=1,MASK0=1 00Ch

Internal pulse

TimerB(TimerA) value

n n+1 n+2 n+3 n+4 n+5

P8.1/TRGB(P8.3/TRGA)

Interrupt controller:

IL0-IL5 : Interrupt latch. Hold all interrupt requests from all interrupt sources. IL's can not

be set by program, but can be reset by program or system reset, so IL can only decide which interrupt source can be accepted.

MASK0-MASK3 : Except INT0, MASK register may permit or inhibit all interrupt sources.

INTERRUPT STRUCTUREINTERRUPT STRUCTURE

INTERRUPT STRUCTURE

Reset by system reset and program

instruction

MASK0 MASK1 MASK1 MASK2 MASK3

IL0

INT1

r0

IL1

TBI

r1

IL2r2IL3

TRGA r3

IL4

r4

IL5

INT0

r5

Priority checker

EI

Entry address generator

Interrupt request Interrupt entry address

Reset by system reset and program

instruction

Set by program instruction

TRGB

SPI

Under the pulse width measurement mode, the counter is incresed at the rising edge of internal pulse during external timer/counter input (P8.1/TRGB, P8.3/TRGA ) in high level, interrupt request is generated as soon as timer/counter count overflow.

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EM73PA88AEM73PA88A

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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

10.8.2001

PreliminaryPreliminary

Preliminary

LCD DRIVERLCD DRIVER

LCD DRIVER

It can directly drive the liquid crystal display ( LCD ) and has 64 segments, 16 commons output pins. There are total 64x16 dots can be display. The V1~V5 are the LCD bias voltage input pins.

(1) LCD driver control command register:(1) LCD driver control command register:

(1) LCD driver control command register:

Port27 3210 Initial value: 0000

LDC LDC

LDC

* *

*

**

*

LCD DISPLAY CONTROLLCD DISPLAY CONTROL

LCD DISPLAY CONTROL

LDC Function description 0 0 LCD display disable 0 1 Blanking 1 0 no function

1 1 LCD display enable

* : Don't care. P27 is the LDC driver control command register. The initial value is 0000.

When LDC ( bit2 and bit3 of P27 ) is set to "00", the LCD display is disabled. When LDC is set to "01", the LCD is blanking, the COM pins are inactive and the SEG pins output the display data continuously. When LDC is set to "11", the LCD display is enabled.

(2) LCD display data area:(2) LCD display data area:

(2) LCD display data area:

The LCD display data is stored in the display data area of the data memory (RAM). The LCD display data area is as illustrated below :

EI : Enable interrupt Flip-Flop may promit or inhibit all interrupt sources, when inter-

rupt occurs, EI is auto cleared to "0", after RTI instruction is executed, EI is auto set to "1" again.

Priority checker : Check interrupt priority when multiple interrupts occur.

INTERRUPT OPERATIONINTERRUPT OPERATION

INTERRUPT OPERATION

The procedure of interrupt operation :

1. Push PC and all flags to stack.

2. Set interrupt entry address into PC.

3. Set SF= 1.

4. Clear EI to inhibit other interrupts occur.

5. Clear the IL with which interrupt source has already been accepted.

6. Excute interrupt subroutine from the interrupt entry address.

7. CPU accept RTI, restore PC and flags from stack. Set EI to accept other interrupt requests.

PROGRAM EXAMPLE: To enable interrupt of "INT0, TRGA"

LDIA #0100B; EXAE; set mask register "1100b" EICIL 010111B ; enable interrupt F.F. and clear IL3 and IL5

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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

PreliminaryPreliminary

Preliminary

LCD display data area :LCD display data area :

LCD display data area :

Bank1Bank1

Bank1

P9.3=1

P26 is the start address register of LCD common pin. Port26 3210 Initial value: 0000

CSACSA

CSA

PROGRAM EXAMPLE:

LDIA #0000B OUTA P26 LDIA #1100B ; LCD display enable OUTA P27 LDIA #1010B ; store 1010B to RAM[101h] SEP P9,3 STA 01H

CSA

100109h

110119h

120129h

130139h

140149h

150159h

160169h

170179h

180189h

190199h

1A01A9h

1B01B9h

1C01C9h

1D01D9h

1E01EF9h

1F01F9h

Common start address register

RAM

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

COM0 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1

COM1 COM0 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2

COM2 COM1 COM0 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3

COM3 COM2 COM1 COM0 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4

COM4 COM3 COM2 COM1 COM0 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5

COM5 COM4 COM3 COM2 COM1 COM0 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6

COM6 COM5 COM4 COM3 COM2 COM1 COM0 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7

COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8

COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COM15 COM14 COM13 COM12 COM11 COM10 COM9

COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COM15 COM14 COM13 COM12 COM11 COM10

COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COM15 COM14 COM13 COM12 COM11

COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COM15 COM14 COM13 COM12

COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COM15 COM14 COM13

COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COM15 COM14

COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COM15

COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0

The display data from the display data area are automatically read out and send to the LCD driver directly by the hardware. Therefore, the display patterns can be changed only by overwritting the contents of the display data area through software.

The dispaly memory area that is not used to store the LCD display data could be used as the ordinary data memory.

100-10Fh 110-11Fh 120-12Fh 130-13Fh 140-14Fh 150-15Fh 160-16Fh 170-17Fh 180-18Fh 190-19Fh 1A0-1AFh 1B0-1BFh 1C0-1CFh 1D0-1DFh 1E0-1EFh 1F0-1FFh

COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15

012345 6789ABCDEF

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

SEG42

SEG43

SEG44

SEG45

SEG46

SEG47

SEG48

SEG49

SEG50

SEG51

SEG52

SEG53

SEG54

SEG55

SEG56

SEG57

SEG58

SEG59

SEG60

SEG61

SEG62

SEG63

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EM73PA88AEM73PA88A

EM73PA88A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

10.8.2001

PreliminaryPreliminary

Preliminary

(3) LCD waveform : (1/5 bias)(3) LCD waveform : (1/5 bias)

(3) LCD waveform : (1/5 bias)

(4) LCD drive voltage :(4) LCD drive voltage :

(4) LCD drive voltage :

• The LCD bias voltage is supplied by voltage multiplier. The application circuit is illustated as below :

V5 V4 V3 V2 V1

VA

VB

0.1µF

SPEECH SYNTHESIZERSPEECH SYNTHESIZER

SPEECH SYNTHESIZER

Block diagram of speech and sound effect

: ON

: OFF

COM0

COM1

COM15

SEG0

SEG0-COM0

V5

V4 V3 V2 V1

Vss

COM0

V5

V4 V3 V2 V1

Vss

COM1

SEG0

ON

SEG0-COM0

ON

SEG0-COM1

OFF

SEG0-COM1

OFF

Frame freq.=64Hz

* TYPE A :

* TYPE B :

S E G 0

P23,24 Write

P6 Write

P5 Write

P7 Read

Sound effect generator

Set sound freq.

P30 Write

Set sound mode

P17 Write

Set sound effect amplitude

PWM

speech decoder

speech ROM

BZ1

BZ2

Set speech address (write 4 times)

P7 Write

Set data address (write 5 times)

Read data

Set sample rate

P5.3 read

Speech active

SPI interrupt

D/A

26

* This specification are subject to be changed without notice.

10.8.2001

EM73PA88AEM73PA88A

EM73PA88A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

PreliminaryPreliminary

Preliminary

EM73PA88A speech synthesizer operates as following :

1. Send the speech start address to the address latch by writing P6 four times.

2. Choose the sampling rate, enable the speech synthesizer by writing P5.

3. The ROM address counters send the ROM address A6 .. A17 to the speech ROM.

4. ACT is the speech acknowledge signal. When the speech synthesizer has voice output. ACT is high . When ACT is changed from high to low, the speech synthesizer can generate the speech ending interrupt SPI. The ACT signal can be read from P5.3.

SPEECH SYNTHESIZER CONTROLSPEECH SYNTHESIZER CONTROL

SPEECH SYNTHESIZER CONTROL

Speech sample rate control register (P5 write) :

3210 Initial value : *111

SR

SRSR

SR

Sample rate selectionSample rate selection

Sample rate selection

Sample rateSample rate

Sample rate

000 PWM on CLK/64/1/3 24K port 5 -- initialization is "*111". 001 CLK/64/1/4 18K port 6 -- initialization is pointed to the low010 CLK/64/2/3 12K nibble of start address latch. 011 CLK/64/2/4 9K 100 CLK/64/3/3 8K CLK=4.6 MHz 101 CLK/64/3/4 6K 111 PWM off

Speech active flag (P5 read) :

3210 Initial value : 0***

ACT * * *

ACT is the speech acknowledge signal. When the speech synthesizer has voice output, ACT is high. When ACT is high → low, the speech synthesizer can generate the speech ending interrupt SPI.

Speech start address register (P6 write) :

3210 Initial value : 1111

Port 6

P6L1 P6L2 P6L3 P6L4

A9 A8 A7 A6 A13 A12 A11 A10 A17 A16 A15 A14 - - - A18

Send the speech start address to the speech synthesizer by writing P6 four times. There is a pointer counter to point the address latch (P6L1, P6L2, P6L3, P6L4). It will increase one when write P6. So, the first time writing P6 to P6L1, the second time is P6L2, the third time is P6L3, the fourth time is P6L4 and the fifth time is P6L1 latch again, ... etc. The pointer counter point to P6L1 when CPU is reset or P5 is writen. In the NORMAL operation mode, the speech synthesizer is available. In the other operation modes, it is disable.

27

* This specification are subject to be changed without notice.

EM73PA88AEM73PA88A

EM73PA88A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

10.8.2001

PreliminaryPreliminary

Preliminary

PROGRAM EXAMPLE:

SP_ADR1 EQU 1234H ; the start address of the speech section

: LDIA #SP_ADR1 OUTA P6 LDIA #SP_ADR1/10H OUTA P6 LDIA #SP_ADR1/100H OUTA P6 LDIA #SP_ADR1/1000H OUTA P6

; set sample rate & start speech

LDIA #0010B

OUTA P5 ; wait speech end WAIT TTP P5,3 ; get speech active flag

B WAIT

USING SPEECH ROM AS DATA ROMUSING SPEECH ROM AS DATA ROM

USING SPEECH ROM AS DATA ROM

The speech ROM can be used for speech synthesizer and for data ROM simutaneously. First, write initial address to P7 (five times), and after four cycles, you can read P7 to get data, and address counter increases one automatically.The following read operations must be at an internval of instruction cycles which are more than 3. The read operation should be all done before you leave normal mode and change to slow mode.

Get speech ROM data (P7 read) :

3210

Port 7

Set speech ROM address (P7 write) :

3210

Port 7

P7L1 P7L2 P7L3 P7L4 P7L5

A3 A2 A1 A0 A7 A6 A5 A4 A11 A10 A9 A8 A15 A14 A13 A12 - A18 A17 A16

PROGRAM EXAMPLE:

D_ADR1 EQU 12345H ; the start address of the speech ROM

:

LDIA #D_ADR1

OUTA P7

LDIA #D_ADR1/10H

OUTA P7

LDIA #D_ADR1/100H

OUTA P7

LDIA #D_ADR1/1000H

OUTA P7

LDIA #D_ADR1/10000H

OUTA P7

28

* This specification are subject to be changed without notice.

10.8.2001

EM73PA88AEM73PA88A

EM73PA88A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

PreliminaryPreliminary

Preliminary

MELODY (SOUND EFFECT) CONTROLMELODY (SOUND EFFECT) CONTROL

MELODY (SOUND EFFECT) CONTROL

One channel melody/sound effect output, controlled by port 23, 24, 17, and 30.

There is a built-in sound effect. It includes the tone generator and random generator. The tone generator is a binary down counter and the random generator is a 9-bit liner feedback shift register.

Sound effect command register (P30)

There are 4 kinds of basic frequency for sound generator which can be selected by P30. The output of sound effect is tone and random combination.

Port30

3 2 1 0

BFREQ SMODE Initial value : 0000

BFREQ Basic frequency (f1) select SMODE Sound generator mode

0 0 CLK/16 0 0 Disable 0 1 CLK/32 0 1 Tone output 1 0 CLK/64 1 0 Random output 1 1 Reserved 1 1 Tone+random output (CLK=4.6MKz)

STA TEMP NOP

INA P7 ; read D_ADR1+1

Tone frequency register (P23, P24)

The 8-bit tone frequency register is P24 and P23. The tone frequency will be changed when user output the different data to P23. Thus, the data must be output to P24 before P23 when users want to change the 8bit tone frequency (TF).

Port24 Port23

3 2 1 0 3 2 1 0 Initial value : 1111 1111 Higher nibble register Lower nibble register

** f1=CLK/2X, f2=f1/(TF+1)/2, TF=1~255, TF-0 ** Example : CLK=4.6 MHz, BFREQ=10, TF=00110001B.

⇒ f1=143.75K Hz, f2=143.75K Hz/50/2=1430 Hz

3 cycles

4 cycles

NOP NOP NOP NOP

; READ DATA

INA P7 ; read D_ADR1

2

CLK/8

f1

f2x2

P23,P24

PWM / D/A ckt.

P30

Output control

Tone

generator

Random

generator

4 kinds

of divider

f2

29

* This specification are subject to be changed without notice.

EM73PA88AEM73PA88A

EM73PA88A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

10.8.2001

PreliminaryPreliminary

Preliminary

The basic structure of Watch-Dog-Timer control is composed by a 4-stage binary counter and a control unit . The WDT counter counts for a certain time to check the CPU status, if there is no malfunction happened, the counter will be cleared and continue counting . Otherwise, if there is a malfunction happened, the WDT control will send a WDT signal ( low active ) to reset CPU. The WDT checking period is assign by P21 ( WDT command port ).

0

WDT control

WDT command port

12

3

counter clear request

RESET pin

LXIN/2

13

WDT counter

P21

mask option

tp

ts

tp=

CLK/64 (CLK=4.6MHz)

1

PROGRAM EXAMPLE:

LDIA #1001B ; basic frequency : CLK/32, tone output OUTA P30 LDIA #0111B ; volume control OUTA P17 LDIA #0011B ; 1430 Hz tone output OUTA P24 LDIA #0001B OUTA P23

WATCH-DOG-TIMER (WDT)WATCH-DOG-TIMER (WDT)

WATCH-DOG-TIMER (WDT)

Watch-dog-timer can help user to detect the malfunction (runaway) of CPU and give system a timeup signal every certain time . User can use the time up signal to give system a reset signal when system is fail. This function is available by mask option. If the mask option of WDT is enabled, it will stop counting when CPU is reseted or in the STOP operation mode.

123456789

+

Random generator

f(x)=x9+x4+1

Volume control register (P17) The are 16 levels of volume for sound generator. P17 is the volume control register.

Port17 Initial value : 1111 3 2 1 0

VCR

VCR ts/tp 1 1 1 1 15/16 1 1 1 0 14/16

:: 0 0 0 1 1/16 0 0 0 0 0/16

30

* This specification are subject to be changed without notice.

10.8.2001

EM73PA88AEM73PA88A

EM73PA88A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

PreliminaryPreliminary

Preliminary

P21 is the control port of watch-dog-timer, and the WDT time up signal is connected to RESET.

Port 21 3210Initial value :0000

CWC * * WDT

CWC Clear watchdog timer counter

0 Clear counter then return to 1 1 Nothing

WDT Set watch-dog-timer detect time

0 3 x 213/LXIN = 3 x 213/32K Hz = 0.75 sec 1 7 x 2

13

/LXIN = 7 x 213/32K Hz = 1.75 sec

PROGRAM EXAMPLE

To enable WDT with 7 x 213/LXIN detection time.

LDIA #0001B OUTA P21; set WDT detection time and clear WDT counter : :

RESETTING FUNCTIONRESETTING FUNCTION

RESETTING FUNCTION

When CPU in normal working condition and RESET pin is held in low level for three instruction cycles at least, then CPU begins to initialize the whole internal states, when RESET pin changes to high level, CPU begins to work in normal condition. The CPU internal state during reset condition is as following table :

Hardware condition in RESET state Initial value Program counter 0000h Status flag 01h Interrupt enable flip-flop ( EI ) 00h MASK0 ,1, 2, 3 00h Interrupt latch ( IL ) 00h P3, 9, 14, 16, 19, 21, 22, 25, 26, 27, 28, 29, 30 00h P5 07h P0, 4, 6, 7, 8, 17, 23, 24 0Fh CLK, LXIN Start oscillation

The RESET pin is a hysteresis input pin and it has a pull-up resistor available by mask option. The simplest RESET circuit is connect RESET pin with a capacitor to VSS and a diode to VDD.

RESET

31

* This specification are subject to be changed without notice.

EM73PA88AEM73PA88A

EM73PA88A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

10.8.2001

PreliminaryPreliminary

Preliminary

EM73PA88A I/O PORT DESCRIPTION :EM73PA88A I/O PORT DESCRIPTION :

EM73PA88A I/O PORT DESCRIPTION :

PortPort

Port

Input functionInput function

Input function

Output functionOutput function

Output function

NoteNote

Note

0 E Input port , wakeup function 1-- -2-- -3 -- I P3(1..0) : ROM bank selection 4 E Input port E Output port 5 I P5.3 : Speech active signal (ACT) I Speech sample rate register 6 -- I Speech start address register 7 I DATA ROM data I Data start address register 8 E Input port, wakeup function, E Output port

external interrupt input

9 -- I P9.3 : RAM bank selection 10 -- -11 -- -12 -- -13 -- -14 I CPU status register -15 -- -16 I STOP mode control register 17 I Sound effect volume control register 18 -19 I IDLE mode control register 20 -21 I WDT control register 22 I DUAL/SLOW mode control register 23 I Sound effect frequency register low nibble 24 I Sound effect frequency register high nibble 25 I Timebase control register 26 I LCD common start address register 27 I LCD control register 28 I Timer/counter A control register 29 I Timer/counter B control register 30 I Sound effect command register 31 --

32

* This specification are subject to be changed without notice.

10.8.2001

EM73PA88AEM73PA88A

EM73PA88A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

PreliminaryPreliminary

Preliminary

APPLICATION CIRCUITAPPLICATION CIRCUIT

APPLICATION CIRCUIT

P0.0

P0.1

P0.2

BZ1

BZ2

RESET

VSS

VA

VB

V5 V4 V3 V2 V1

LXOUT

LXIN

CLK

20P

0.022µF

32.768KHz

all 0.1µF

0.1µF

SEG0~ SEG63 COM0~ COM15

LCD PANNEL

V

BA T

V

BA T

V

DD2

V

DD

EM73PA88A

100Ω

RESET

3V

100

33

* This specification are subject to be changed without notice.

EM73PA88AEM73PA88A

EM73PA88A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

10.8.2001

PreliminaryPreliminary

Preliminary

Parameters Sym. Parameters Sym.

Parameters Sym.

Min.Min.

Min.

Typ.Typ.

Typ.

Max.Max.

Max.

UnitUnit

Unit

ConditionsConditions

Conditions

ABSOLUTE MAXIMUM RATINGSABSOLUTE MAXIMUM RATINGS

ABSOLUTE MAXIMUM RATINGS

ItemsItems

Items

Sym.Sym.

Sym.

RatingsRatings

Ratings

ConditionsConditions

Conditions

Supply Voltage V

DD

-0.5V to 6V

Input Voltage V

IN

-0.5V to VDD+0.5V

Output Voltage V

O

-0.5V to VDD+0.5V

Power Dissipation P

D

300mW T

OPR

=50oC

Operating Temperature T

OPR

0oC to 50oC

Storage Temperature T

STG

-55oC to 125oC

RECOMMANDED OPERATING CONDITIONSRECOMMANDED OPERATING CONDITIONS

RECOMMANDED OPERATING CONDITIONS

ItemsItems

Items

Sym.Sym.

Sym.

RatingsRatings

Ratings

ConditionCondition

Condition

Supply Voltage V

DD

2.2V to 4.8V

Input Voltage V

IH

0.90xVDD to V

DD

V

IL

0V to 0.10xV

DD

Operating Frequency F

C

4.6MHz CLK

Fs 32KHz LXIN,LXOUT

Supply current I

DD

- 0.5 1.2 mA VDD=3.3V,no load,DUAL mode,Fs=32KHz, Fc=4.6MHz

-2538µAV

DD

=3.3V,SLOW mode,LCD on

-2033µAV

DD

=3.3V,IDLE mode,LCD on

-712µAV

DD

=3.3V,IDLE mode,LCD off

- 0.1 1 µA V

DD

=3.3V, STOP mode

Hysteresis voltage V

HYS+

0.50V

DD

- 0.75V

DD

V RESET, P0, P8

V

HYS-

0.20V

DD

- 0.40V

DD

V

Input current I

IH

- - ±1 µA P0, RESET, VDD=3.3V,VIH=3.3/0V

- - ±1 µA Open-drain, V

DD

=3.3V,VIH=3.3/0V

I

IL

- -250 -500 µA Normal current push-pull,VDD=3.3V,P4(low), P8

Output voltage V

OH

2.4 - - V Push-pull, P4(high current PMOS), SOUND, V

DD

=2.7V, IOH=-0.9mA

2.0 2.4 - V Push-pull, P4(low current PMOS), P8, V

DD

=2.7V, IOH=-40µA

V

OL

- 0.15 0.3 V VDD=2.7V,IOL=0.9mA, P4, P8

Leakage current I

LO

- - 1 µA Open-drain, VDD=3.3V, VO=3.3V

Input resistor R

IN

100 200 300 KΩ P0 300 600 900 KΩ RESET

DC ELECTRICAL CHARACTERISTICSDC ELECTRICAL CHARACTERISTICS

DC ELECTRICAL CHARACTERISTICS (VDD=3±0.3V, VSS=0V, T

OPR

=25oC)

34

* This specification are subject to be changed without notice.

10.8.2001

EM73PA88AEM73PA88A

EM73PA88A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

PreliminaryPreliminary

Preliminary

Parameters Sym. Parameters Sym.

Parameters Sym.

Min.Min.

Min.

Typ.Typ.

Typ.

Max.Max.

Max.

UnitUnit

Unit

ConditionsConditions

Conditions

Output current I

OH

25 - 60 mA VDD=3V,VBZ=1.5V,

of BZ1, BZ2 I

OL

25 - 60 mA

Output current - 2 3 4 mA V

DD

=3V,VO=0.7V of VO LCD bias voltage V

1

- 0.9 - V VDD=3V, LCD on, no load

V

2

- 1.8 - V

V

3

- 2.7 - V

V

4

- 3.6 - V

V

5

- 4.5 - V

DC ELECTRICAL CHARACTERISTICSDC ELECTRICAL CHARACTERISTICS

DC ELECTRICAL CHARACTERISTICS (VDD=3±0.3V, VSS=0V, T

OPR

=25oC)

35

* This specification are subject to be changed without notice.

EM73PA88AEM73PA88A

EM73PA88A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

10.8.2001

PreliminaryPreliminary

Preliminary

RESET

LXIN

LXOUT

Crystal Osc.

P0/WAKEUP TYPE INPUT-A

CLK

WAKEUP function mask option

Internal

Osc.

: mask option

RC Osc.

LXIN

RESET PIN TYPERESET PIN TYPE

RESET PIN TYPE

TYPE RESET-A

OSCILLATION PIN TYPEOSCILLATION PIN TYPE

OSCILLATION PIN TYPE

TYPE OSC-B TYPE OSC-G

INPUT PIN TYPEINPUT PIN TYPE

INPUT PIN TYPE

TYPE INPUT-A TYPE INPUT-B

TYPE OSC-H

36

* This specification are subject to be changed without notice.

10.8.2001

EM73PA88AEM73PA88A

EM73PA88A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

PreliminaryPreliminary

Preliminary

I/O PIN TYPEI/O PIN TYPE

I/O PIN TYPE

TYPE I/OTYPE I/O

TYPE I/O

TYPE I/O-LTYPE I/O-L

TYPE I/O-L

Path A : For set and clear bit of port instructions, data goes through path A from output data latch to CPU. Path B : For input and test instructions, data from output pin go through path B to CPU and the output data latch

will be set to high.

Input data

Output data

path B

path A

TYPE I/O-N

Output data latch

Special function output

: mask option

mask option

TYPE I/O

Output data latch

Input data

Output data

path B

path A

SEL

Special function control input

WAKEUP function mask option

TYPE I/O-NTYPE I/O-N

TYPE I/O-N

TYPE I/O-OTYPE I/O-O

TYPE I/O-O

37

* This specification are subject to be changed without notice.

EM73PA88AEM73PA88A

EM73PA88A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

10.8.2001

PreliminaryPreliminary

Preliminary

PAD DIAGRAMPAD DIAGRAM

PAD DIAGRAM

108

1

2

3

4

5

6

7

8 9

10

11

12

13

14

15

16

17

18

19

20

21

22

23 24

25

SEG32

P8.0/DIN

P8.1/DOUT

P8.2

P8.3

P4.0

P4.1 P4.2

P4.3

P0.0/ACLK

P0.1/PGM

P0.2/OE

P0.3/DCLK

BZ1

BZ2

(0,0)

VSS

RESET

CLK

TEST/VPP

LXIN

LXOUT

VDD

V1

V2

53

52

51

50

48

47

46

34

35

36

37

38

39

40

41

42

43

89

9091

92

93

94

95

88

98

99

100

101

102104

105

106

107

VDD2

SEG56 SEG57

SEG58 SEG59

SEG60

SEG61 SEG62

SEG63

COM15

COM14

COM13

COM12

COM9

COM8 COM7

COM6

COM5

COM4

COM3

COM2

COM1

COM0

COM11

SEG29

SEG28

SEG27

SEG26

SEG25

SEG24

SEG21

SEG20

SEG19

SEG18

SEG17

SEG16

SEG15

SEG14

SEG12

SEG11

SEG10

SEG9

SEG13

SEG34

SEG35

SEG37

SEG38

SEG39

SEG41

SEG42

SEG43

SEG49

SEG50

SEG47

SEG48

SEG45

SEG44

SEG52

SEG53

SEG54

SEG51

EM73PA88A

28

29

30

26

27

49

87

86

71

70

69 68

67

66

65

64 63

62

73

59

58

57

56

55

61

60

103

96

109

V3

V4

V5

VA VB

SEG31 SEG30

SEG23

SEG22

SEG0

SEG1

SEG2

SEG3

SEG4 SEG5

SEG6

SEG7 SEG8

SEG40

SEG46

31

32

33

44

45 54

72

74

75

76

77

78

79

80

81

82

83

84

85

97

COM10

SEG36

SEG33

SEG55

ELAN

38

* This specification are subject to be changed without notice.

10.8.2001

EM73PA88AEM73PA88A

EM73PA88A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

PreliminaryPreliminary

Preliminary

Pad No.Pad No.

Pad No.

SymbolSymbol

Symbol

XX

X

YY

Y

1 SEG33 -1414.4 2805.6 2 SEG32 -1628.0 2655.6 3 P8.0/DIN -1628.0 2530.6 4 P8.1/DOUT -1628.0 2410.5 5 P8.2 -1628.0 2290.6 6 P8.3 -1628.0 2170.5 7 P4.0 -1633.0 2050.6 8 P4.1 -1633.0 1930.6

9 P4.2 -1633.0 1810.5 10 P4.3 -1633.0 1690.6 11 P0.0/ACLK -1633.0 1570.5 12 P0.1/PGM -1633.0 1450.6 13 P0.2/OE -1633.0 1330.6 14 P0.3/DCLK -1633.0 1210.5 15 VDD2 -1601.5 1008.2 16 BZ1 -1605.8 780.2 17 BZ2 -1605.8 377.3 18 VSS -1601.5 150.1 19 RESET -1613.0 -332.9 20 CLK -1613.0 -503.1 21 TEST/VPP -1613.0 -661.5 22 LXIN -1613.0 -843.1 23 LXOUT -1613.0 -1012.9 24 VDD -1613.0 -1193.0 25 V1 -1613.0 -1395.3 26 V2 -1613.0 -1565.5 27 V3 -1613.0 -1735.3 28 V4 -1613.0 -1905.5 29 V5 -1613.0 -2107.8 30 VA -1613.0 -2288.5 31 VB -1613.0 -2458.3 32 SEG31 -1613.0 -2629.1 33 SEG30 -1613.0 -2798.8 34 SEG29 -1319.6 -2816.0 35 SEG28 -1189.6 -2816.0 36 SEG27 -1059.6 -2816.0 37 SEG26 -929.6 -2816.0 38 SEG25 -799.6 -2816.0 39 SEG24 -669.6 -2816.0 40 SEG23 -539.6 -2816.0

39

* This specification are subject to be changed without notice.

EM73PA88AEM73PA88A

EM73PA88A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

10.8.2001

PreliminaryPreliminary

Preliminary

Pad No.Pad No.

Pad No.

SymbolSymbol

Symbol

XX

X

YY

Y

41 SEG22 -409.6 -2816.0 42 SEG21 -279.6 -2816.0 43 SEG20 -149.6 -2816.0 44 SEG19 -19.6 -2816.0 45 SEG18 110.4 -2816.0 46 SEG17 240.4 -2816.0 47 SEG16 370.0 -2816.0 48 SEG15 499.9 -2816.0 49 SEG14 629.9 -2816.0 50 SEG13 759.9 -2816.0 51 SEG12 889.9 -2816.0 52 SEG11 1020.0 -2816.0 53 SEG10 1149.9 -2816.0 54 SEG9 1279.9 -2816.0 55 SEG8 1618.5 -2609.9 56 SEG7 1618.5 -2479.8 57 SEG6 1618.5 -2349.9 58 SEG5 1618.5 -2219.8 59 SEG4 1618.5 -2089.8 60 SEG3 1618.5 -1959.9 61 SEG2 1618.5 -1829.9 62 SEG1 1618.5 -1699.8 63 SEG0 1618.5 -1569.9 64 COM0 1618.5 -1439.8 65 COM1 1618.5 -1309.9 66 COM2 1613.5 -1035.1 67 COM3 1613.5 -865.3 68 COM4 1613.5 -695.0 69 COM5 1613.5 -526.3 70 COM6 1613.5 -357.2 71 COM7 1613.5 -188.5 72 COM8 1613.5 -19.4 73 COM9 1613.5 149.2 74 COM10 1613.5 318.3 75 COM11 1613.5 487.1 76 COM12 1613.5 656.2 77 COM13 1613.5 824.9 78 COM14 1613.5 993.9 79 COM15 1613.5 1162.6 80 SEG63 1613.5 1331.8

40

* This specification are subject to be changed without notice.

10.8.2001

EM73PA88AEM73PA88A

EM73PA88A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

PreliminaryPreliminary

Preliminary

Pad No.Pad No.

Pad No.

SymbolSymbol

Symbol

XX

X

YY

Y

81 SEG62 1613.5 1500.4 82 SEG61 1613.5 1669.5 83 SEG60 1613.5 1838.2 84 SEG59 1613.5 2007.3 85 SEG58 1613.5 2176.0 86 SEG57 1613.5 2345.1 87 SEG56 1613.5 2513.9 88 SEG55 1442.2 2805.6 89 SEG54 1312.1 2805.6 90 SEG53 1182.1 2805.6 91 SEG52 1052.1 2805.6 92 SEG51 922.1 2805.6 93 SEG50 792.2 2805.6 94 SEG49 662.1 2805.6 95 SEG48 532.1 2805.6 96 SEG47 402.1 2805.6 97 SEG46 272.1 2805.6 98 SEG45 142.2 2805.6

99 SEG44 12.1 2805.6 100 SEG43 -117.9 2805.6 101 SEG42 -247.9 2805.6 102 SEG41 -377.9 2805.6 103 SEG40 -507.9 2805.6 104 SEG39 -637.9 2805.6 105 SEG38 -767.9 2805.6 106 SEG37 -897.9 2805.6 107 SEG36 -1027.9 2805.6 108 SEG35 -1157.9 2805.6 109 SEG34 -1287.9 2805.6

Unit : µm Chip Size : 3530 x 5910 µm Note : For PCB layout, IC substrate must be floated or connected to Vss.

41

* This specification are subject to be changed without notice.

EM73PA88AEM73PA88A

EM73PA88A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

10.8.2001

PreliminaryPreliminary

Preliminary

INSTRUCTION TABLEINSTRUCTION TABLE

INSTRUCTION TABLE

(1) Data Transfer(1) Data Transfer

(1) Data Transfer

Mnemonic Object code ( binary )Mnemonic Object code ( binary )

Mnemonic Object code ( binary )

Operation descriptionOperation description

Operation description

ByteByte

Byte

CycleCycle

Cycle

Flag Flag

Flag

CC

C

ZZ

Z

S S

S

LDA x 0110 1010 xxxx xxxx Acc←RAM[x] 2 2 - Z 1 LDAM 0101 1010 Acc ←RAM[HL] 1 1 - Z 1 LDAX 0110 0101 Acc←ROM[DP]

L

12-Z1

LDAXI 0110 0111 Acc←ROM[DP]H,DP+1 1 2 - Z 1 LDH #k 1001 kkkk HR←k11--1 LDHL x 0100 1110 xxxx xx00 LR←RAM[x],HR←RAM[x+1] 2 2 - - 1 LDIA #k 1101 kkkk Acc←k11-Z1 LDL #k 1000 kkkk LR←k11--1 STA x 0110 1001 xxxx xxxx RAM[x]←Acc 2 2 - - 1 STAM 0101 1001 RAM[HL]←Acc 1 1 - - 1 STAMD 0111 1101 RAM[HL]←Acc, LR-1 1 1 - Z C STAMI 0111 1111 RAM[HL]←Acc, LR+1 1 1 - Z C' STD #k,y 0100 1000 kkkk yyyy RAM[y]←k22--1 STDMI #k 1010 kkkk RAM[HL]←k, LR+1 1 1 - Z C' THA 0111 0110 Acc←HR 1 1 - Z 1 TLA 0111 0100 Acc←LR 1 1 - Z 1

(2) Rotate(2) Rotate

(2) Rotate

Mnemonic Object code ( binary )Mnemonic Object code ( binary )

Mnemonic Object code ( binary )

Operation descriptionOperation description

Operation description

ByteByte

Byte

CycleCycle

Cycle

Flag Flag

Flag

CC

C

ZZ

Z

SS

S

RLCA 0101 0000 ←CF←Acc← 11CZC' RRCA 0101 0001 →CF→Acc→ 11CZC'

(

3) Arithmetic operation3) Arithmetic operation

3) Arithmetic operation

Mnemonic Object code ( binary )Mnemonic Object code ( binary )

Mnemonic Object code ( binary )

Operation descriptionOperation description

Operation description

ByteByte

Byte

CycleCycle

Cycle

Flag Flag

Flag

CC

C

Z Z

Z

SS

S

ADCAM 0111 0000 Acc←Acc + RAM[HL] + CF 1 1 C Z C' ADD #k,y 0100 1001 kkkk yyyy RAM[y]←RAM[y] +k 2 2 - Z C' ADDA #k 0110 1110 0101 kkkk Acc←Acc+k 2 2 - Z C' ADDAM 0111 0001 Acc←Acc + RAM[HL] 1 1 - Z C' ADDH #k 0110 1110 1001 kkkk HR←HR+k 2 2 - Z C' ADDL #k 0110 1110 0001 kkkk LR←LR+k 2 2 - Z C' ADDM #k 0110 1110 1101 kkkk RAM[HL]←RAM[HL] +k 2 2 - Z C' DECA 0101 1100 Acc←Acc-1 1 1 - Z C DECL 0111 1100 LR←LR-1 1 1 - Z C DECM 0101 1101 RAM[HL]←RAM[HL] -1 1 1 - Z C INCA 0101 1110 Acc←Acc + 1 1 1 - Z C'

42

* This specification are subject to be changed without notice.

10.8.2001

EM73PA88AEM73PA88A

EM73PA88A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

PreliminaryPreliminary

Preliminary

INCL 0111 1110 LR←LR + 1 1 1 - Z C' INCM 0101 1111 RAM[HL]←RAM[HL]+1 1 1 - Z C' SUBA #k 0110 1110 0111 kkkk Acc←k-Acc 2 2 - Z C SBCAM 0111 0010 Acc←RAM[HLl - Acc - CF' 1 1 C Z C SUBM #k 0110 1110 1111 kkkk RAM[HL]←k - RAM[HL] 2 2 - Z C

((

(

4) Logical operation4) Logical operation

4) Logical operation

Mnemonic Object code ( binary )Mnemonic Object code ( binary )

Mnemonic Object code ( binary )

Operation descriptionOperation description

Operation description

ByteByte

Byte

CycleCycle

Cycle

Flag Flag

Flag CC

CC

C

ZZ

Z

SS

S

ANDA #k 0110 1110 0110 kkkk Acc←Acc&k 2 2 - Z Z' ANDAM 0111 1011 Acc←Acc & RAM[HL] 1 1 - Z Z' ANDM #k 0110 1110 1110 kkkk RAM[HL]←RAM[HL]&k 2 2 - Z Z' ORA #k 0110 1110 0100 kkkk Acc←Acc k 2 2 - Z Z' ORAM 0111 1000 Acc ←Acc RAM[HL] 1 1 - Z Z' ORM #k 0110 1110 1100 kkkk RAM[HL]←RAM[HL] k 2 2 - Z Z' XORAM 0111 1001 Acc←Acc^RAM[HL] 1 1 - Z Z'

(5) Exchange(5) Exchange

(5) Exchange

Mnemonic Object code ( binary )Mnemonic Object code ( binary )

Mnemonic Object code ( binary )

Operation descriptionOperation description

Operation description

ByteByte

Byte

CycleCycle

Cycle

Flag Flag

Flag

CC

C

ZZ

Z

SS

S

EXA x 0110 1000 xxxx xxxx Acc↔RAM[x] 2 2 - Z 1 EXAH 0110 0110 Acc↔HR 1 2 - Z 1 EXAL 0110 0100 Acc↔LR 1 2 - Z 1 EXAM 0101 1000 Acc↔RAM[HL] 1 1 - Z 1 EXHL x 0100 1100 xxxx xx00 LR↔RAM[x],

HR↔RAM[x+1] 2 2 - - 1

(6) Branch(6) Branch

(6) Branch

Mnemonic Object code ( binary )Mnemonic Object code ( binary )

Mnemonic Object code ( binary )

Operation descriptionOperation description

Operation description

ByteByte

Byte

CycleCycle

Cycle

Flag Flag

Flag

CC

C

ZZ

Z

SS

S

SBR a 00aa aaaa If SF=1 then PC←PC

12-6.a5-0

11--1

else null

LBR a 1100 aaaa aaaa aaaa If SF= 1 then PC←a else null 2 2 - - 1 SLBR a 0101 0101 1100 aaaa If SF=1 then PC←a else null 3 3 - - 1

aaaa aaaa (a:1000~1FFFh)

0101 0111 1100 aaaa

aaaa aaaa (a:0000~0FFFh)

(7) Compare(7) Compare

(7) Compare

Mnemonic Object code ( binary )Mnemonic Object code ( binary )

Mnemonic Object code ( binary )

Operation descriptionOperation description

Operation description

ByteByte

Byte

CycleCycle

Cycle

Flag Flag

Flag

CC

C

ZZ

Z

SS

S

CMP #k,y 0100 1011 kkkk yyyy k-RAM[y] 2 2 C Z Z' CMPA x 0110 1011 xxxx xxxx RAM[x]-Acc 2 2 C Z Z'

- -

43

* This specification are subject to be changed without notice.

EM73PA88AEM73PA88A

EM73PA88A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

10.8.2001

PreliminaryPreliminary

Preliminary

(8) Bit manipulation(8) Bit manipulation

(8) Bit manipulation

Mnemonic Object code ( binary )Mnemonic Object code ( binary )

Mnemonic Object code ( binary )

Operation descriptionOperation description

Operation description

ByteByte

Byte

CycleCycle

Cycle

Flag Flag

Flag

CC

C

ZZ

Z

SS

S

CLM b 1111 00bb RAM[HL]b←011--1 CLP p,b 0110 1101 11bb pppp PORT[p]

b

←022--1

CLPL 0110 0000 PORT[LR

3-2

+4]LR

1-0

←012--1

CLR y,b 0110 1100 11bb yyyy RAM[y]

b

←022--1

SEM b 1111 01bb RAM[HL]

b

←111--1

SEP p,b 0110 1101 01bb pppp PORT[p]

b

←122--1

SEPL 0110 0010 PORT[LR

3-2

+4]LR

l-0

←112 --1

SET y,b 0110 1100 01bb yyyy RAM[y]

b

←122--1

TF y,b 0110 1100 00bb yyyy SF←RAM[y]

b

'22--*

TFA b 1111 10bb SF←Acc

b

'11--*

TFM b 1111 11bb SF←RAM[HL]

b

'11--*

TFP p,b 0110 1101 00bb pppp SF←PORT[p]

b

'22--*

TFPL 0110 0001 SF←PORT[LR

3-2

+4]LR

1-0

'1 2--*

TT y,b 0110 1100 10bb yyyy SF←RAM[y]

b

22--*

TTP p,b 0110 1101 10bb pppp SF←PORT[p]

b

22--*

(9) Subroutine(9) Subroutine

(9) Subroutine

Mnemonic Object code ( binary )Mnemonic Object code ( binary )

Mnemonic Object code ( binary )

Operation descriptionOperation description

Operation description

ByteByte

Byte

CycleCycle

Cycle

Flag Flag

Flag

CC

C

ZZ

Z

SS

S

LCALL a 0100 0aaa aaaa aaaa STACK[SP]←PC, 2 2 - - -

SP←SP -1, PC←a

SCALL a 1110 nnnn STACK[SP]←PC, 1 2 - - -

SP←SP - 1, PC←a, a = 8n + 6 (n =1∼15),0086h (n = 0)

RET 0100 1111 SP←SP + 1, PC←STACK[SP] 1 2 - - -

(10) Input/output(10) Input/output

(10) Input/output

Mnemonic Object code ( binary )Mnemonic Object code ( binary )

Mnemonic Object code ( binary )

Operation descriptionOperation description

Operation description

ByteByte

Byte

CycleCycle

Cycle

Flag Flag

Flag

CC

C

ZZ

Z

SS

S

INA p 0110 1111 0100 pppp Acc←PORT[p] 2 2 - Z Z' INM p 0110 1111 1100 pppp RAM[HL]←PORT[p] 2 2 - - Z' OUT #k,p 0100 1010 kkkk pppp PORT[p]←k22--1 OUTA p 0110 1111 000p pppp PORT[p]←Acc 2 2 - - 1 OUTM p 0110 1111 100p pppp PORT[p]←RAM[HL] 2 2 - - 1

Mnemonic Object code ( binary )Mnemonic Object code ( binary )

Mnemonic Object code ( binary )

Operation descriptionOperation description

Operation description

ByteByte

Byte

CycleCycle

Cycle

Flag Flag

Flag

CC

C

ZZ

Z

SS

S

CMPAM 0111 0011 RAM[HL] - Acc 1 1 C Z Z' CMPH #k 0110 1110 1011 kkkk k - HR 2 2 - Z C CMPIA #k 1011 kkkk k - Acc 1 1 C Z Z' CMPL #k 0110 1110 0011 kkkk k-LR 2 2 - Z C

44

* This specification are subject to be changed without notice.

10.8.2001

EM73PA88AEM73PA88A

EM73PA88A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

PreliminaryPreliminary

Preliminary

Mnemonic Object code ( binary )Mnemonic Object code ( binary )

Mnemonic Object code ( binary )

Operation descriptionOperation description

Operation description

ByteByte

Byte

CycleCycle

Cycle

Flag Flag

Flag

CC

C

ZZ

Z

SS

S

TFCFC 0101 0011 SF←CF', CF←0110-* TTCFS 0101 0010 SF←CF, CF←1111-* TZS 0101 1011 SF←ZF 1 1 - - *

(12) Interrupt control(12) Interrupt control

(12) Interrupt control

Mnemonic Object code ( binary )Mnemonic Object code ( binary )

Mnemonic Object code ( binary )

Operation descriptionOperation description

Operation description

ByteByte

Byte

CycleCycle

Cycle

Flag Flag

Flag

CC

C

ZZ

Z

SS

S

CIL r 0110 0011 11rr rrrr IL←IL & r 2 2 - - 1 DICIL r 0110 0011 10rr rrrr EIF←0,IL←IL&r 2 2 - - 1 EICIL r 0110 0011 01rr rrrr EIF←1,IL←IL&r 2 2 - - 1 EXAE 0111 0101 MASK↔Acc 1 1 - - 1 RTI 0100 1101 SP←SP+1,FLAG.PC 1 2 * * *

←STACK[SP],EIF ←1

(13) CPU control(13) CPU control

(13) CPU control

Mnemonic Object code ( binary )Mnemonic Object code ( binary )

Mnemonic Object code ( binary )

Operation descriptionOperation description

Operation description

ByteByte

Byte

CycleCycle

Cycle

Flag Flag

Flag CC

CC

C

ZZ

Z

SS

S

NOP 0101 0110 no operation 1 1 - - -

(14) Timer/Counter & Data pointer & Stack pointer control(14) Timer/Counter & Data pointer & Stack pointer control

(14) Timer/Counter & Data pointer & Stack pointer control

Mnemonic Object code ( binary )Mnemonic Object code ( binary )

Mnemonic Object code ( binary )

Operation descriptionOperation description

Operation description

ByteByte

Byte

CycleCycle

Cycle

Flag Flag

Flag

CC

C

ZZ

Z

SS

S

LDADPL 0110 1010 1111 1100 Acc←[DP]

L

22-Z1

LDADPM 0110 1010 1111 1101 Acc←[DP]

M

22-Z1

LDADPH 0110 1010 1111 1110 Acc←[DP]

H

22-Z1

LDASP 0110 1010 1111 1111 Acc←SP 2 2 - Z 1 LDATAL 0110 1010 1111 0100 Acc←[TA]

L

22-Z1

LDATAM 0110 1010 1111 0101 Acc←[TA]

M

22-Z1

LDATAH 0110 1010 1111 0110 Acc←[TA]

H

22 -Z1

LDATBL 0110 1010 1111 1000 Acc←[TB]

L

22-Z1

LDATBM 0110 1010 1111 1001 Acc←[TB]

M

22-Z1

LDATBH 0110 1010 1111 1010 Acc←[TB]

H

22-Z1

STADPL 0110 1001 1111 1100 [DP]

L

←Acc 2 2 - - 1

STADPM 0110 1001 1111 1101 [DP]

M

←Acc 2 2 - - 1

STADPH 0110 1001 1111 1110 [DP]

H

←Acc 2 2 - - 1

STASP 0110 1001 1111 1111 SP←Acc 2 2 - - 1 STATAL 0110 1001 1111 0100 [TA]

L

←Acc 2 2 - - 1

STATAM 0110 1001 1111 0101 [TA]

M

←Acc 2 2 - - 1

STATAH 0110 1001 1111 0110 [TA]

H

←Acc 2 2 - - 1

STATBL 0110 1001 1111 1000 [ TB]

L

←Acc 2 2 - - 1

STATBM 0110 1001 1111 1001 [TB]

M

←Acc 2 2 - - 1

STATBH 0110 1001 1111 1010 [TB]

H

←Acc 2 2 - - 1

(11) Flag manipulation(11) Flag manipulation

(11) Flag manipulation

45

* This specification are subject to be changed without notice.

EM73PA88AEM73PA88A

EM73PA88A

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

10.8.2001

PreliminaryPreliminary

Preliminary

**** SYMBOL DESCRIPTION**** SYMBOL DESCRIPTION

**** SYMBOL DESCRIPTION

SymbolSymbol

Symbol

DescriptionDescription

Description

SymbolSymbol

Symbol

DescriptionDescription

Description

HR H register LR L register PC Program counter DP Data pointer SP Stack pointer STACK[SP] Stack specified by SP A

CC

Accumulator FLAG All flags CF Carry flag ZF Zero flag SF Status flag EI Enable interrupt register IL Interrupt latch MASK Interrupt mask PORT[p] Port ( address : p ) ΤΑ Timer/counter A ΤΒ Timer/counter B RAM[HL] Data memory (address : HL ) RAM[x] Data memory (address : x ) ROM[DP]

L

Low 4-bit of program memory

ROM[DP]

H

High 4-bit of program memory [DP]

L

Low 4-bit of data pointer register

[DP]

M

Middle 4-bit of data pointer register [DP]

H

High 4-bit of data pointer register

[TA]L([TB]L) Low 4-bit of timer/counter A [TA]M([TB]M) Middle 4-bit of timer/counter A

(timer/counter B) register (timer/counter B) register [TA]H([TB]H) High 4-bit of timer/counter A LR

1-0

Contents of bit assigned by bit

(timer/counter B) register 1 to 0 of LR LR

3-2

Bit 3 to 2 of LR a

5-0

Bit 5 to 0 of destination address for

branch instruction

PC

12-6

Bit 12 to 6 of program counter ← Transfer ↔ Exchange + Addition

- Substraction & Logic AND

Logic OR ^ Logic XOR

Inverse operation . Concatenation #k 4-bit immediate data x 8-bit RAM address y 4-bit zero-page address p 4-bit or 5-bit port address b Bit address r 6-bit interrupt latch

- -

Datasheet EM73PA88ABQ, EM73PA88AAQ Datasheet (ELAN)

Specifications and Main Features

Frequently Asked Questions

User Manual