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GENERAL DESCRIPTIONGENERAL DESCRIPTION
GENERAL DESCRIPTION
GENERAL DESCRIPTIONGENERAL DESCRIPTION
EM73362 is an advanced single chip CMOS 4-bit micro-controller. It contains 3K-byte ROM, 52-nibble RAM,
4-bit ALU, 13-level subroutine nesting, 22-stage time base, one 12-bit timer for the kernal function and one high
speed counter. EM73362 also contains 5 interrupt sources, 1 input port, 4 bidirection ports, built-in watchdog-timer and LCD driver (27x3 to 15x3).
Except low-power consumption and high speed, EM73362 has the STOP mode and IDLE mode operation for
power saving function.
FEATURESFEATURES
FEATURES
FEATURESFEATURES
• Operation voltage : 1.2V to 1.8V.(clock frequency : 32 K Hz)
• Clock source : Single clock system for crystal, connect a external resistor or external clock
• Instruction set : 109 powerful instructions.
• Instruction cycle time : Up to 122µs for 32 K Hz.
• ROM capacity : 3072 x 8 bits.
• RAM capacity : 52 x 4 bits.
• Input port : 1 port (4-bit).
• Bidirection port : 4 ports (P4, P6, P7, P8) are available by mask option. P4 is a high current port.
• 12-bit timer : One 12-bit timer is programmable for timer.
• High speed counter : The high speed counter includes one 8-bit high speed counter, one 12-bit general
• Built-in time base counter: 22 stages.
• Subrountine nesting : Up to 13 levels.
• Interrupt : External interrupt . . . . . .2 input interrupt sources.
• LCD driver : 27x3 to 15x3 dots available by mask option. 1/3, 1/2 and static three kinds of duty
• Built-in watch-dog-timer is available by mask option.
• Built-in low battery detector.
• Power saving function : STOP mode and IDLE mode.
• Package type : Chip form 49 pins.
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source, available by mask option.
(P4.0 and TONE available by mask option. P4.1~P4.3 are shared with the input/
output of RFO.) P6, P7 and P8 are shared with SEG15-SEG26.
counter and a resistor frequency oscillator. It has resistor to frequency oscillation
mode, melody mode and auto load timer mode.
Internal interrupt . . . . . . 2 timer overflow interrupts,
1 time base interrupt.
(1/2 bias) selectable. The programming method of LCD driver is RAM mapping.
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FUNCTION BLOCK DIAGRAMFUNCTION BLOCK DIAGRAM
FUNCTION BLOCK DIAGRAM
FUNCTION BLOCK DIAGRAMFUNCTION BLOCK DIAGRAM
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RESET
Reset
Control
Interrupt
Control
Time
Base
XOUT
XIN
WDT
Clock
Generator
Instruction Decoder
Instruction Register
12-bit
timer
(TA)
Frequency
doubler
System Control
ROM
PC
Data pointer
Data Bus
ZCS G
Timing
Generator
ACC
ALU
Flag
Sleep Mode
Control
Stack pointer
Stack
RAM
HR
LR
I/O Control
P0.0(INT1)/WAKEUP0
P0.1/WAKEUP1
P0.2(INT0)/WAKEUP2
P0.3/WAKEUP3
VA
VB
LCD
driver
Low battery detector
Tone generator
High speed counter
VEE
COM0~COM2
SEG0~SEG14
P6,P7,P8/SEG(26..15)
BAT
TONE
P4.0(RX)/TONE
P4.1(CS)
P4.2(RY)
P4.3(RZ)
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PIN DESCRIPTIONSPIN DESCRIPTIONS
PIN DESCRIPTIONS
PIN DESCRIPTIONSPIN DESCRIPTIONS
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Pin name Function P
VDD Power supply (+)
VSS Power supply (-)
RESET System reset input signal, low active RESET_A
mask option : none
pull-up
XIN Crystal / external resistor or external clock source OSC_A / OSC_F
connecting pin
XOUT Crystal / external resistor connecting pin OSC_A / OSC_F
P0.0(INT1)/WAKEUP0, 2-bit input pins with external interrupt sources input INPUT_J
P0.2(INT0)/WAKEUP2 and STOP/IDLE releasing function
mask option : wake-up enable, pull-up
wakeup enable, none
wakeup disable, pull-up
wakeup disable, pull-down
wakeup disable, none
P0(1,3)/WAKEUP1,3 2-bit input pins with STOP / IDLE releasing function INPUT_H
mask option : wakeup enable, pull-up
wakeup enable, none
wakeup disable, pull-up
wakeup disable, pull-down
wakeup disable, none
P4.0(RX)/TONE 1-bit bidirection I/O pin or inver se sound effect output or I/O_O
RF oscillation
mask option : TONE enable, push-pull, high current PMOS
TONE disable, open-drain(apply to RF oscillation)
TONE disable, push-pull, high current PMOS
TONE disable, push-pull, low current PMOS
P4.1(CS) 1-bit bidirection I/O pin or RF oscillation bias pin I/O_X
mask option : open-drain(apply to RF oscillation)
push-pull, high current PMOS
push-pull, low current PMOS
P4.2(RY), P4.3(RZ) 2-bit bidirection I/O pins or RF oscillation input pins I/O_Y
mask option : open-drain(apply to RF oscillation)
push-pull, high current PMOS
push-pull, low current PMOS
P6(0..3)/SEG(23..26), 12-bit bidirection I/O pins are shared with LCD segment pin I/O_O
P7(0..3)/SEG(19..22), mask option : segment enable, open-drain
P8(0..3)/SEG(15..18) segment disable, open-drain
segment disable, push-pull, high current PMOS
segment disable, push-pull, low current PMOS
BAT Connect the capacitor for built-in low battery detector
TONE Built-in tone generator output
VA, VB, VEE Connect the capacitors for LCD bias voltage
COM0 ~ COM2 LCD common output pins
SEG0 ~ SEG14 LCD segment output pins
TEST Tie Vss as package type, no connecting as COB type.
IN type
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FUNCTION DESCRIPTIONSFUNCTION DESCRIPTIONS
FUNCTION DESCRIPTIONS
FUNCTION DESCRIPTIONSFUNCTION DESCRIPTIONS
PROGRAM ROM ( 3K X 8 bits )PROGRAM ROM ( 3K X 8 bits )
PROGRAM ROM ( 3K X 8 bits )
PROGRAM ROM ( 3K X 8 bits )PROGRAM ROM ( 3K X 8 bits )
3 K x 8 bits program ROM contains user's program and some fixed data.
The basic structure of program ROM can be divided into 4 parts.
1. Address 000h: Reset start address.
2. Address 002h - 00Ch : 5 kinds of interrupt service routine entry addresses.
3. Address 00Eh-086h : SCALL subroutine entry address, only available at 00Eh,016h,01Eh,026h, 02Eh,
036h, 03Eh, 046h, 04Eh, 056h, 05Eh, 066h, 06Eh, 076h, 07Eh, 086h.
4. Address 000h - 7FFh : LCALL subroutine entry address.
5. Address 000h - BFFh : Except used as above function, the other region can be used as user's program region.
address 3072 x 8 bits
000h Reset start address
002h INT0; External interrupt service toutine entry address
004h
006h TRGA; Timer/counter A interrupt service routine entry address
008h TRGB; Timer/counter B interrupt service routine entry address
00Ah TBI; Time base interrupt service routine entry address
00Ch INT1; External interrupt service routine entry address
00Eh
086h
.
.
.
SCALL, subroutine call entry address
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BFFh
User's program and fixed data are stored in the program ROM. User's program is according the PC value
to send next executed instruction code. Fixed data can be read out by table-look-up instruction.
Table-look-up instruction is depended on the Data Pointer (DP) to indicate to ROM address, then to get the
ROM code data.
LDAXLDAX
LDAX
LDAXLDAX
LDAXILDAXI
LDAXI
LDAXILDAXI
Acc Acc
Acc
Acc Acc
Acc Acc
Acc
Acc Acc
←←
ROM[DP] ROM[DP]
←
ROM[DP]
←←
ROM[DP] ROM[DP]
←←
ROM[DP] ROM[DP]
←
ROM[DP]
←←
ROM[DP] ROM[DP]
LL
L
LL
,DP+1,DP+1
,DP+1
,DP+1,DP+1
HH
H
HH
DP is a 12-bit data register which can store the program ROM address to be the pointer for the ROM code data.
First, user load ROM address into DP by instruction "STADPL, STADPM, STADPH", then user can get the
lower nibble of ROM code data by instruction "LDAX" and higher nibble by instruction "LDAXI".
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PROGRAM EXAMPLE: Read out the ROM code of address 777h by table-look-up instruction.
LDIA #07h;
STADPL ; [DP]L ← 07h
STADPM ; [DP]M ← 07h
STADPH ; [DP]H ← 07h, Load DP=777h
:
LDL #00h;
LDH #03h;
LDAX ; ACC ← 6h
STAMI ; RAM[30] ← 6h
LDAXI ; ACC ← 5h
STAM ; RAM[31] ← 5h
;
ORG 777h
DATA 56h;
:
DATA RAM ( 52-nibble ) DATA RAM ( 52-nibble )
DATA RAM ( 52-nibble )
DATA RAM ( 52-nibble ) DATA RAM ( 52-nibble )
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There is total 52 - nibble data RAM from address 00 to 33h
Data RAM includes 3 parts: zero page region, stacks and data area.
Address
00h - 0Fh
10h - 1Fh
20h - 2Fh
30h - 33h
Increment
Level 0
Level 4
Level 8
Level 12
Level 1
Level 5
Level 9
Level 2
Level 6
Level 10
Stack Zero-page
Level 3
Level 7
Level 11
Increment
ZERO- PAGE:
From 00h to 0Fh is the location of zero-page. It is used as the pointer in zero-page addressing mode for the
instruction of "STD #k,y; ADD #k,y; CLR y,b; CMP k,y".
PROGRAM EXAMPLE: To wirte immediate data "07h" to address "03h" of RAM and to clear bit 2 of RAM.
STD #07h, 03h ; RAM[03] ← 07h
CLR 0Eh,2 ; RAM[0Eh]2 ← 0
STACK:
There are 13-level (maximum) stack for user using for subroutine (including interrupt and CALL). User can
assign any level be the starting stack by giving the level number to stack pointer (SP).
When user using any instruction of CALL or subroutine, before entry the subroutine, the previous PC address
will be saved into stack until return from those subroutines, the PC value will be restored by the data saved
in stack.
DATA AREA:
Except the special area used by user, the whole RAM can be used as data area for storing and loading general
data.
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ADDRESSING MODE
(1) Indirect addressing mode:
Indirect addressing mode indicates the RAM address by specified HL register.
For example:
LDAM ; Acc ← RAM[HL]
STAM ; RAM[HL] ← Acc
(2) Direct addressing mode:
Direct addressing mode indicates the RAM address by immediate data.
For example:
LDA x ; Acc← RAM[x]
STA x ; RAM[x] ← Acc
(3) Zero-page addressing mode
For zero-page region, user can using direct addressing to write or do any arithematic, comparsion or bit
manupulated operation directly.
For example: STD #k,y ; RAM[y] ← #k
ADD #k,y; RAM[y] ← RAM[y] + #k
LCD DISPLALCD DISPLA
LCD DISPLA
LCD DISPLALCD DISPLA
Y RAMY RAM
Y RAM
Y RAMY RAM
RAM address from 40h ~ 46h, 50h ~ 56h, 60h ~ 66h are LCD display RAM, the RAM data of this region can't
be operated by instruction “LDHL xx” and “EXHL”.
40h~46h (COM0)
50h~56h (COM1)
60h~66h (COM2)
PROGRAM COUNTER (3K ROM)PROGRAM COUNTER (3K ROM)
PROGRAM COUNTER (3K ROM)
PROGRAM COUNTER (3K ROM)PROGRAM COUNTER (3K ROM)
Address Increment bit 0 1 2 3 0 1 2
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
Increment
Program counter ( PC ) is composed by a 12-bit counter, which indicates the next executed address for the
instruction of program ROM.
For a 3K - byte size ROM, PC can indicate address form 000h - BFFh, for BRANCH and CALL instructions,
PC is changed by instruction indicating.
(1) Branch instruction:(1) Branch instruction:
(1) Branch instruction:
(1) Branch instruction:(1) Branch instruction:
SBR aSBR a
SBR a
SBR aSBR a
Object code: 00aa aaaa
Condition: SF=1; PC ← PC
( branch condition satisified )
11-6.a
PC Hold original PC value+1 aaaaaa
SF=0; PC← PC +1( branch condition not satisified)
PC Original PC value + 1
LBR aLBR a
LBR a
LBR aLBR a
Object code: 1100 aaaa aaaa aaaa
Condition: SF=1; PC ← a ( branch condition satisified)
PCaaaaaaaaaaaa
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SF=0 ; PC ← PC + 2 (branch condition not satisfied)
PC Original PC value + 2
(2) Subroutine instruction:(2) Subroutine instruction:
(2) Subroutine instruction:
(2) Subroutine instruction:(2) Subroutine instruction:
SCALL aSCALL a
SCALL a
SCALL aSCALL a
Object code: 1110 nnnn
Condition : PC ← a ; a=8n+6 ; n=1..15 ; a=86h, n=0
PC 0 0 0 0 a a a a a a a a
LCALL aLCALL a
LCALL a
LCALL aLCALL a
Object code: 0100 0aaa aaaa aaaa
Condition: PC ← a
PC0aaaaaaaaaaa
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RETRET
RET
RETRET
Object code: 0100 1111
Condition: PC ← STACK[SP]; SP + 1
PC The return address stored in stack
RT IRT I
RT I
RT IRT I
Object code: 0100 1101
Condition : FLAG. PC ← STACK[SP]; EI ← 1; SP + 1
PC The return address stored in stack
(3) Interrupt acceptance operation:(3) Interrupt acceptance operation:
(3) Interrupt acceptance operation:
(3) Interrupt acceptance operation:(3) Interrupt acceptance operation:
When an interrupt is accepted, the original PC is pushed into stack and interrupt vector will be loaded into
PC. The interrupt vectors are as following:
INT0 INT0
INT0 (External interrupt from P0.2)
INT0 INT0
PC000000000010
TRGATRGA
TRGA (Timer A overflow interrupt)
TRGATRGA
PC000000000110
TRGBTRGB
TRGB (Time B overflow interrupt)
TRGBTRGB
PC000000001000
TBITBI
TBI (Time base interrupt)
TBITBI
PC000000001010
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INT1 INT1
INT1 (External interrupt from P0.0)
INT1 INT1
PC000000001100
(4) Reset operation:(4) Reset operation:
(4) Reset operation:
(4) Reset operation:(4) Reset operation:
PC000000000000
(5) Other operations:(5) Other operations:
(5) Other operations:
(5) Other operations:(5) Other operations:
For 1-byte instruction execution: PC + 1
For 2-byte instruction execution: PC + 2
ACCUMULATORACCUMULATOR
ACCUMULATOR
ACCUMULATORACCUMULATOR
Accumulator is a 4-bit data register for temporary data. For the arithematic, logic and comparative opertion
.., ACC plays a role which holds the source data and result.
FLAGSFLAGS
FLAGS
FLAGSFLAGS
There are four kinds of flag, CF (Carry flag), ZF (Zero flag), SF (Status flag) and GF (General flag),
these 4 1-bit flags are affected by the arithematic, logic and comparative .... operation.
All flags will be put into stack when an interrupt subroutine is served, and the flags will be restored after
RTI instruction executed.
(1) Carry Flag ( CF )
The carry flag is affected by following operation :
a. Addition : CF as a carry out indicator, when the addition operation has a carry-out, CF will be "1",
in another word, if the operation has no carry-out, CF will be "0".
b. Subtraction : CF as a borrow-in indicator, when the subtraction operation must has a borrow, in the CF
will be "0", in another word, if no borrow-in, CF will be "1".
c. Comparision: CF is as a borrow-in indicator for Comparision operation as the same as subtraction
operation.
d. Rotation: CF shifts into the empty bit of accumulator for the rotation and holds the shift out data after
rotation.
e. CF test instruction : For TFCFC instruction, the content of CF sends into SF then clear itself "0".
For TTSFC instruction, the content of CF sends into SF then set itself "1".
(2) Zero Flag ( ZF )
ZF is affected by the result of ALU, if the ALU operation generate a "0" result, the ZF will be "1",
otherwise, the ZF will be "0".
(3) Status Flag ( SF )
The SF is affected by instruction operation and system status.
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a. SF is initiated to "1" for reset condition.
b. Branch instruction is decided by SF, when SF=1, branch condition will be satisified, otherwise,
branch condition will not be satisified by SF = 0.
(4) General Flag ( GF )
GF is a one bit general purpose register which can be set, clear, test by instruction SGF, CGF and TGS.
PROGRAM EXAMPLE :
Check following arithematic operation for CF, ZF, SF
CF ZF SF
LDIA #00h; - 1 1
LDIA #03h; - 0 1
ADDA #05h; - 0 1
ADDA #0Dh; - 0 0
ADDA #0Eh; - 0 0
ALUALU
ALU
ALUALU
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The arithematic operation of 4 - bit data is performed in ALU unit. There are 2 flags can be affected by
the result of ALU operation, ZF and SF. The operation of ALU can be affected by CF only.
ALU STRUCTUREALU STRUCTURE
ALU STRUCTURE
ALU STRUCTUREALU STRUCTURE
ALU supported user arithematic operation function, including : addition, subtraction and rotaion.
DATA BUS
ALU
ZF CF SF GF
ALU FUNCTIONALU FUNCTION
ALU FUNCTION
ALU FUNCTIONALU FUNCTION
(1) Addition:
For instruction ADDAM, ADCAM, ADDM #k, ADD #k,y .... ALU supports addition function.
The addition operation can affect CF and ZF. For addition operation, if the result is "0", ZF will be "1",
otherwise, not equal "0", ZF will be "0". When the addition operation has a carry-out, CF will be "1",
otherwise, CF will be "0".
EXAMPLE:
Operation Carry Zero
3+4=7 0 0
7+F=6 1 0
0+0=0 0 1
8+8=0 1 1
(2) Subtraction:
For instruction SUBM #k, SUBA #k, SBCAM, DECM... ALU supports user subtraction function. The
subtraction operation can affect CF and ZF, For subtraction operation, if the result is negative, CF will
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be "0", it means a borrow out, otherwise, if the result is positive, CF will be "1". For ZF, if the result
of subtraction operation is "0", the ZF will be "1", otherwise, ZF will be "1".
EXAMPLE:
Operation Carry Zero
8-4=4 1 0
7-F= -8(1000) 0 0
9-9=0 1 1
(3) Rotation:
There are two kinds of rotation operation, one is rotation left, the other is rotation right.
RLCA instruction rotates Acc value to left, shift the CF value into the LSB bit of Acc and the shift out data
will be hold in CF.
MSB LSB
ACC
CF
RRCA instruction operation rotates Acc value to right, shift the CF value into the MSB bit of Acc and
the shift out data will be hold in CF.
MSB LSB
ACC
CF
PROGRAM EXAMPLE: To rotate Acc right and shift a "1" into the MSB bit of Acc.
TTCFS; CF ← 1
RRCA; rotate Acc right and shift CF=1 into MSB.
HL REGISTERHL REGISTER
HL REGISTER
HL REGISTERHL REGISTER
HL register are two 4-bit registers, they are used as a pair of pointer for the address of RAM memory and also
2 independent temporary 4-bit data registers. For some instruction, L register can be a pointer to indicate the
pin number (Port4, Port6, Port7).
HL REGISTER STRUCTUREHL REGISTER STRUCTURE
HL REGISTER STRUCTURE
HL REGISTER STRUCTUREHL REGISTER STRUCTURE
HL REGISTER FUNCTIONHL REGISTER FUNCTION
HL REGISTER FUNCTION
HL REGISTER FUNCTIONHL REGISTER FUNCTION
3 2 1 0
H REGISTER
3 2 1 0
L REGISTER
(1)For instruction : LDL #k, LDH #k, THA, THL, INCL, DECL, EXAL, EXAH, HL register used as a
temporary register.
PROGRAM EXAMPLE: Load immediate data "5h" into L register, "Dh" into H register.
LDL #05h;
LDH #0Dh;
(2) For instruction LDAM, STAM, STAMI .., HL register used as a pointer for the address of RAM memory.
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PROGRAM EXAMPLE: Store immediate data #Ah into RAM of address 35h.
LDL #5h;
LDH #3h;
STDMI #0Ah; RAM[35] ← Ah
(3) For instruction : SELP, CLPL, TFPL, L register be a pointer to indicate the bit of I/O port.
When LR = 0 - 1, indicate P4.0 - P4.1.
PROGRAM EXAMPLE: To set bit 1 of Port 4 to "1"
LDL #01h;
SEPL ; P4.1 ← 1
STACK POINTER (SP)STACK POINTER (SP)
STACK POINTER (SP)
STACK POINTER (SP)STACK POINTER (SP)
Stack pointer is a 4-bit register which stores the present stack level number.
Before using stack, user must set the SP value first, CPU will not initiate the SP value after reset condition.
When a new subroutine is accepted, the SP will be decreased one automatically, in another word, if
returning from a subroutine, the SP will be increased one.
The data transfer between ACC and SP is by instruction of "LDASP" and "STASP".
DATA POINTER (DP)DATA POINTER (DP)
DATA POINTER (DP)
DATA POINTER (DP)DATA POINTER (DP)
Data pointer is a 12-bit register which stores the address of ROM can indicate the ROM code data
specified by user (refer to data ROM).
CLOCK AND TIMING GENERATORCLOCK AND TIMING GENERATOR
CLOCK AND TIMING GENERATOR
CLOCK AND TIMING GENERATORCLOCK AND TIMING GENERATOR
The clock generator is supported by a single clock system, the clock source comes from crystal (resonator)
or RC oscillation, the working frequency range is 32 KHz to 100 KHz depending on the working voltage.
CLOCK AND TIMING GENERATOR STRUCTURECLOCK AND TIMING GENERATOR STRUCTURE
CLOCK AND TIMING GENERATOR STRUCTURE
CLOCK AND TIMING GENERATOR STRUCTURECLOCK AND TIMING GENERATOR STRUCTURE
The clock generator connects outside compoments (crystal or resonator by XIN and XOUT pin for crystal
osc type, capacitor for RC osc type, these two type is decided by mask option) the clock generator
generates a basic system clock "fc".
When CPU sleeping, the clock generator will be stopped until the sleep condition released.
The system clock control generates 4 basic phase signals (S1, S2, S3, S4) and system clock.
Mask option
XIN
sleep
fc
Mask option for choose Crystal or RC oscillation
System clock
clock generator System clock control
XOUT
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S1 S2 S3 S4
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
XIN
XOUT
Crystal connection
CLOCK AND TIMING GENERATOR FUNCTIONCLOCK AND TIMING GENERATOR FUNCTION
CLOCK AND TIMING GENERATOR FUNCTION
CLOCK AND TIMING GENERATOR FUNCTIONCLOCK AND TIMING GENERATOR FUNCTION
Resistor connection
XIN
XOUT
The frequency of fc is the oscillation frequency for XIN, XOUT by crystal (resonator) or by RC osc.
When CPU sleeps, the XOUT pin will be in "high" state.
The instruction cycle equal 4 basic clock fc.
1 instructure cycle = 4 / fc
OPERATION MODE CONTROLOPERATION MODE CONTROL
OPERATION MODE CONTROL
OPERATION MODE CONTROLOPERATION MODE CONTROL
EM73362 has 3 operation modes. They are Normal, Idle, and Stop mode.
IDLE
mode
(P19)
Reset
Reset release
Reset
RESET
operation
Command
NORMAL
operating
mode
Reset
Input pin or
Internal timer wakeup
Input timer wakeup
Command
(P16)
STOP
mode
Operation Mode Oscillator CPU Available Function
Normal Oscillating Run LCD, RFC, Low battery detector
Idle Oscillating Run LCD
Stop Stop Stop All disable
*
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ST ST
ST
ST ST
STOP operation mode condition :
1. Osc stop and CPU internal status held.
2. Internal time base clear to "0".
3. CPU internal memory, flags, register, I/O held original states.
4. Program counter hold the executed address after STOP release.
Release condition :
1. Release STOP operation mode by the falling edge of any one of P0(0..3)/
2. Osc start to oscillating.
3. Warm-up time passing.
4. According PC to execute the following program.
OP OPERAOP OPERA
OP OPERA
OP OPERAOP OPERA
TION MODETION MODE
TION MODE
TION MODETION MODE
During STOP operation mode, CPU holds the system’s internal status with a low power consumption, for
the STOP mode, the system clock will be stopped in the STOP condition and system need a warm up time
for the stability of system clock running after wakeup.
The STOP operation mode is controlled by Port 16 and released by P0(0..3)/
WAKEUP 0 3..
.
P16 3 2 1 0 Initial value : 0000
SPME SWWT
SPME Enable STOP mode SWWT Set wake-up warm-up time
9
0 1 Enable STOP mode 0 0 2
* * Reserved 0 1 2
1 0 2
/ XIN
14
/ XIN
16
/ XIN
1 1 Reserved
WAKEUP 0 3..
.
Note : There are 4 independent mask options for wakeup function in EM73362. So, the wakeup function of
P0(0..3)/
IDLE OPERAIDLE OPERA
IDLE OPERA
IDLE OPERAIDLE OPERA
WAKEUP 0 3..
TION MODETION MODE
TION MODE
TION MODETION MODE
are enabled or disabled independently.
The IDLE operation mode retains the internal status with low power consumption without stopping the
system clock function and LCD display.
The IDLE operation mode is controlled by Port 19 and released by P0(0..3)/
WAKEUP 0..3
or the internal
timing generator.
P19 3 2 1 0 Initial value : 0000
IDME SIDR
IDME Enable IDLE mode SIDR Select IDLE releasing condition
0 1 Enable IDLE mode 0 0 P0(0..3) pin input
* * Reserved 0 1 P0(0..3) pin input and 1 sec signal
1 0 P0(0..3) pin input and 0.5 sec signal
1 1 P0(0..3) pin input and 15.625m sec signal
*
This specification are subject to be changed without notice.
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TIMING GENERATOR AND TIME BASETIMING GENERATOR AND TIME BASE
TIMING GENERATOR AND TIME BASE
TIMING GENERATOR AND TIME BASETIMING GENERATOR AND TIME BASE
The timing generator produces the system clock from basic clock pulse which can be normal mode or slow
mode clock.
1 instruction cycle = 4 basic clock pulses
There are 22 stages time base.
Binary counter
fc
Prescaler
123
0 5 6 7 8 9 10 11 12 134212019 181716 15 14
When working in the single clock mode, the timebase clock source is come from fc.
Time base provides basic frequency for following function:
1. TBI (time base interrupt).
2. Timer/counter, internal clock source.
3. Warm-up time for STOP - mode releasing.
TIME BASE INTERRUPT (TBI)TIME BASE INTERRUPT (TBI)
TIME BASE INTERRUPT (TBI)
TIME BASE INTERRUPT (TBI)TIME BASE INTERRUPT (TBI)
The time base can be used to generate a fixed frequency interrupt. There are 8 kinds of frequencies can be
selected by setting "P25"
Single clock mode
P25 3210( initial value 0000 )
0 0 x x: Interrupt disable
0 1 0 0: Interrupt frequency XIN / 29 Hz
0 1 0 1: Interrupt frequency XIN / 2
0 1 1 0: Interrupt frequency XIN / 2
0 1 1 1: Interrupt frequency XIN / 2
1 1 0 0: Interrupt frequency XIN / 2
1 1 0 1: Interrupt frequency XIN / 2
1 1 1 0: Interrupt frequency XIN / 2
1 1 1 1: Interrupt frequency XIN / 2
1 0 x x: Reserved
10
Hz
12
Hz
13
Hz
14
Hz
15
Hz
16
Hz
17
Hz
*
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TIMER ( TIMERA, TIMERB)TIMER ( TIMERA, TIMERB)
TIMER ( TIMERA, TIMERB)
TIMER ( TIMERA, TIMERB)TIMER ( TIMERA, TIMERB)
EM73362 only can support timer function for timerA.
For timerA, the timer data is saved in timer register TAH, TAM, TAL, which user can set timer initial
value and read the timer value by instruction "LDATAH(M,L), STATAH(M,L)".
This counter can be set initial value and send counter value to timer register, P28 is the command port for
timerA, user can choose different internal clock rate by setting this port. When timer overflows, it will
generate a TRGA interrupt request to interrupt control unit.
INTERRUPT CONTROL
DATA BUS
12 BIT COUNTER
internal clock
TIMER CONTROLTIMER CONTROL
TIMER CONTROL
TIMER CONTROLTIMER CONTROL
P28
TIMER CONTROL
TMSA IPSA
Timer command port: P28 is the command port for timerA.
Port 28
3 2 1 0
TMSA IPSA
Initial state: 0000
TMSA Mode Selection
0 0 Stop
0 1 Reserved
1 0 Timer mode
1 1 Reserved
IPSA Clock rate Selection
0 0 XIN/2 Hz
0 1 XIN/2 Hz
1 0 XIN/2 Hz
1 1 XIN/2 Hz
*
This specification are subject to be changed without notice.
5
7
11
15
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TIMER FUNCTIONTIMER FUNCTION
TIMER FUNCTION
TIMER FUNCTIONTIMER FUNCTION
For timer mode, timerA increase one at any rising edge of internal pulse. User can choose 4 kinds of internal
pulse rate by setting IPSA for timerA.
When timerA counts overflow, TRGA will be generated to interrupt control unit.
Internal pulse
TimerA value
n n+1 n+2 n+3 n+4 n+5 n+6 n+7
PROGRAM EXAMPLE: To generate TRGA interrupt request after 60 ms with system clock XlN=32K Hz
LDIA #0100B;
EXAE; enable mask 2
EICIL 110111B; interrupt latch ←0, enable EI
LDIA #04H;
STATAL;
LDIA #0CH;
STATAM;
LDIA #0FH;
STATAH;
LDIA #1000B;
OUTA P28; enable timerA with internal pulse rate: XIN/25 Hz
NOTE: The preset value of timer/counter register is calculated as following procedure.
Internal pulse rate: XIN/2
5
; XIN = 32KHz
The time of timer counter count one = 25 /XIN = 32/32K=1ms
The number of internal pulse to get timer overflow = 60 ms/ 1ms = 60 = 03CH
The preset value of timer/counter register = 1000H - 03CH = 0FC4H
INTERRUPT FUNCTIONINTERRUPT FUNCTION
INTERRUPT FUNCTION
INTERRUPT FUNCTIONINTERRUPT FUNCTION
There are 3 internal interrupt sources and 2 external interrupt sources. Multiple interrupts are admitted
according the priority.
TypeType
Type
TypeType
External External interrupt (INT0) 1 IL 5 EI=1 002H
Internal Reserved 2 IL4 EI=1, MASK3=1 004H
Internal TimerA overflow interrupt (TRGA) 3 IL3 EI=1, MASK2=1 006H
Internal TimerB overflow interrupt (TRGB) 4 IL 2 EI=1, MASK1=1 008H
Internal Time base interrupt(TBI) 5 IL 1 00AH
External External interrupt (INT1) 6 IL 0 EI=1,MASK0=1 00CH
*
This specification are subject to be changed without notice.
Interrupt sourceInterrupt source
Interrupt source
Interrupt sourceInterrupt source
PriorityPriority
Priority
PriorityPriority
InterruptInterrupt
Interrupt
InterruptInterrupt
LatchLatch
Latch
LatchLatch
InterruptInterrupt
Interrupt
InterruptInterrupt
Enable conditionEnable condition
Enable condition
Enable conditionEnable condition
Program ROMProgram ROM
Program ROM
Program ROMProgram ROM
entry addressentry address
entry address
entry addressentry address
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INTERRUPT STRUCTUREINTERRUPT STRUCTURE
INTERRUPT STRUCTURE
INTERRUPT STRUCTUREINTERRUPT STRUCTURE
Reset by system reset and program
instruction
Reset by system reset and program
instruction
Set by program instruction
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
MASK0 MASK1 MASK1 MASK2 MASK3
INT1
r0
IL0
TBI
r1
IL1
EI Entry address generator
TRGB
r2
IL2
TRGA
r3
Priority checker
IL3
Reserved
r4
IL4
INT0
r5
IL5
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Interrupt request Interrupt entry address
Interrupt controller:
IL0-IL5 : Interrupt latch. Hold all interrupt requests from all interrupt sources. ILr can not be
set by program, but can be reset by program or system reset, so IL only can decide
which interrupt source can be accepted.
MASK0-MASK3 : MASK register can promit or inhibit all interrupt sources.
EI : Enable interrupt Flip-Flop can promit or inhibit all interrupt sources, when inter-
rupt happened, EI is cleared to "0" automatically, after RTI instruction happened,
EI will be set to "1" again.
Priority checker: Check interrupt priority when multiple interrupts happened.
INTERRUPT FUNCTIONINTERRUPT FUNCTION
INTERRUPT FUNCTION
INTERRUPT FUNCTIONINTERRUPT FUNCTION
The procedure of interrupt operation:
1. Push PC and all flags to stack.
2. Set interrupt entry address into PC.
3. Set SF= 1.
4. Clear EI to inhibit other interrupts happened.
5. Clear the IL for which interrupt source has already be accepted.
6. To execute interrupt subroutine from the interrupt entry address.
7. CPU accept RTI, restore PC and flags from stack. Set EI to accept other interrupt requests.
PROGRAM EXAMPLE: To enable interrupt of "TRGA"
LDIA #1100B;
EXAE; set mask register "1100B"
EICIL 111111B ; enable interrupt F.F.
*
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LCD DRIVERLCD DRIVER
LCD DRIVER
LCD DRIVERLCD DRIVER
EM73362 can directly drive the liquid crystal display (LCD) and has 27 segment, 3 common output pins.
There are total 27 x 3 dots can be display. The VDD, VEE, VA, VB and VSS pins are the bias voltage
inputs of the LCD driver. The method of LCD programming is RAM mapping.
CONTRCONTR
CONTR
CONTRCONTR
OL OF LCD DRIVEROL OF LCD DRIVER
OL OF LCD DRIVER
OL OF LCD DRIVEROL OF LCD DRIVER
The LCD driver control command register is P27. When LDC is 00, the LCD is disabled and changes the
duty only. When LDC is 01, the LCD is blanking, the COM pins are inactive and the SEG pins continuously
output the display data. When LDC is 11, the LCD driver enables, the power switc h is turned on and it
cannot be turned off forever except the CPU is reseted or in the STOP operation mode. Users must enable
the LCD driver by self when the CPU is woke up.
P27 3 2 1 0 Initial value : 0000
LDC DUTY
LDC LCD display control DUTY Driving method select
0 0 LCD display disable 0 0 Reserved
0 1 Blanking 0 1 1/3 duty ( 1/2 bias )
1 0 Reserved 1 0 1/2 duty ( 1/2 bias )
1 1 LCD display enable 1 1 Static
LCD driving methods
There are four kinds of driving methods can be selected by DUTY ( P27.0 ~ P27.1 ). The driving wave
forms of LCD driver are as below :
1/3 duty (1/2 bias)
C
C1C
O2O
O
M
M
M
0
SEG0
SEG1
SEG2
:
*
This specification are subject to be changed without notice.
COM0
COM1
COM2
SEG0
SEG0 - COM0
ON
SEG0 - COM1
OFF
Frame
1/2 duty (1/2 bias)
Frame
Static
ON OFF
Frame
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LCD frame frequency : According to the drive method to set the frame frequency.
Driving method Frame frequency (Hz)
1/3 duty 86 x (3/3) = 86
1/2 duty 86 x (3/2) = 129
Static 86
LCD drive voltage
When the power supply is 1.5V, the VEE is connected a capacitor to VSS and the VA is connected a
capacitor to VB for the voltage doubler. The output of VEE is 2 x 1.5V for LCD bias voltage.
VA
VEE
0.1uF
VB
VDD
1.5V
VSS
0.1uF
PROGRAM EXAMPLE
LDIA #0001B ; set LCD mode 1/3 duty 1/2 bias
OUTA P27
LDIA #1100B
OUTA P27 ; enable LCD
:
:
*
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LCD DISPLALCD DISPLA
LCD DISPLA
LCD DISPLALCD DISPLA
Y DY D
Y D
Y DY D
AA
TT
A A
AREAAREA
A
T
A
AREA
AA
TT
A A
AREAAREA
The LCD display data is stored in RAM from address 40h ~ 46h, 50h ~ 56h and 60h ~ 66h. The relation of
data area and COM / SEG pin is as below :
Address Increment bit 0 1 2 3 0 1 2
40h~46h (COM0)
50h~56h (COM1)
60h~66h (COM2)
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
Increment
Read automatically by the display data from the display data area and send to the LCD driver by the
hardware. Therefore, the display patterns can be changed only by overwritting the contents of the display
data area with the software.
The relation between LCD display RAM and driving method
Driving method LCD display RAM address
40h ~ 46h 50h ~ 56h 50h ~ 66h
1/3 duty COM0 COM1 COM2
1/2 duty COM0 COM1 Static COM0 - -
HIGH SPEEDHIGH SPEED
HIGH SPEED
HIGH SPEEDHIGH SPEED
COUNTER COUNTER
COUNTER
COUNTER COUNTER
EM73362 has one high speed counter for resistor to frequency oscillation mode, melody mode and auto load
timer mode. The resistor to frequency oscillation (RFO) circuit as show below :
F
RF
P18(3..2)
Counter
P5
X
RF/2
F
8-bit Counter
P17(1..0) P17(3..2)
Rate
gating
clock
rate
rate
P3
TCB
TONE
Mode
P4.0(RX)
P4.2(RY)
P4.3(RZ)
P4.1(CS)
P18(1..0)
MUX
Resistor
to
frequency
oscillator
*
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
CONTRCONTR
CONTR
CONTRCONTR
OL OF HIGH SPEED COUNTEROL OF HIGH SPEED COUNTER
OL OF HIGH SPEED COUNTER
OL OF HIGH SPEED COUNTEROL OF HIGH SPEED COUNTER
The high speed counter is controlled by the command registers (P17, P18) :
P17 3 2 1 0 Initial value : 0000
MODE RATE
MODE Selection of HTC mode
0 0 Disable HTC
0 1 Melody mode
1 0 Auto load timer mode
1 1 Resistor to frequency oscillation mode
RATE Internal pulse rate / Counter start request frequency
( Hz ) Resistor to frequency Auto load timer mode / Melody
oscillation mode mode internal pulse rate
0 0 XIN / 2
0 1 XIN / 2
1 0 XIN / 2
1 1 XIN / 2
10
12
14
15
XIN / 2
XIN / 2
XIN / 2
XIN / 2
0
2
4
6
P18 3 2 1 0 Initial value : 0000
RFIP RFIN
RFIP Input frequency of RFO RFIN Selection of RFO Pin
0 0 F
0 1 F
1 0 F
1 1 F
RF / 2 0 0 Normal I/O
RF / 4 0 1 P4.0 (RX) for RFO
RF / 8 1 0 P4.2 (RY) for RFO
RF / 16 1 1 P4.3 (RZ) for RFO
P3 and P5 are the 8-bit binary counter registers of the HTC. P3 is lower nibble register and P5 is higher
nibble register.
P5 P3
3 2 1 0 3 2 1 0 Initial value : 0000 0000
Higher nibble register Lower nibble register
The HTC consist of one auto-reload and presetable 8-bit binary counter, 12-bit general counter and clock
source selectors. The command register can select the internal clock pulse for the melody, auto load counter
and resistor to frequency oscillation modes. The HTC increases one at the rising edge of the clock pulses.
When the first rising edge occurs by the HTC enabled, the HTC starts counting.
*
This specification are subject to be changed without notice.
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8-BIT BINARY COUNTER
Write the preset value to the registers
The value of 8-bit binary counter can be presetted by P3 and P5. The value of registers can be loaded into
the 8-bit binary counter when the counter starts counting or occurs overflow. If you write values to the
registers before the next overflow occurs, the preset value can be changed.
Read the count value from the registers
The count value of 8-bit binary counter can be read out from P3 and P5. The value is unstable when you
read out the value during counting. Thus, you must disable the counter before reading out the value.
12-BIT GENERAL COUNTER (TCB)
Write the initial value to the registers
The initial value can be written into the 12-bit counter registers by using STATBL, STATBM and STA TBH
instructions. The value of registers can be loaded into the 12-bit binary counter (TCB) and the TCB in
creases one when the 8-bit binary counter overflows.
Read the count value from the registers
The count value of 12-bit binary counter can be read out from the counter registers by using LDATBL,
LDATBM and LDATBH instructions.
20-BIT COUNTER FUNCTION
The 8-bit binary counter is connected to TCB which is one 12-bit general counter and becomes to the 20bit counter. The TCB increases one when the 8-bit binary counter overflows and generats an overflow
interrupt (TRGB) when the TCB overflows. In this case, the TCB cannot be used as a 12-bit counter
alone.
FUNCTION OF HIGH SPEED COUNTERFUNCTION OF HIGH SPEED COUNTER
FUNCTION OF HIGH SPEED COUNTER
FUNCTION OF HIGH SPEED COUNTERFUNCTION OF HIGH SPEED COUNTER
The HTC has three modes which are RFO mode, melody mode and auto load timer mode. In these
mode, the HTC loads the initial values from the counter registers (P3, P5) when it is enabled by P17 and
it also can be auto-reloaded the initial values when it overflows. The HTC is counted by the internal pulse
and the value of TCB increases one when 8-bit binary counter overflows. The TCB can generate an
overflow interrupt (TRGB) when it overflows. The TRGB cannot be generated when the HTC is in the
melody mode or disabled.
The HTC is disabled when the CPU is reseted or in the STOP/IDLE operation mode. Users must enable
it by self when the CPU is waked up.
*
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Resistor to frequency oscillation mode
In this case, the window gate width interval is from the time base output fall to rise and the value of window
gate width setting is the same as the time base interrupt frequency. The time base can be generated a fixed
frequency interrupt when the time base interrupt (TBI) is enabled. The content of the HTC can be read and
initialized by the TBI interrupt service routine.
HTC input pulse
Time base
8-bit binary counter
8-bit binary counter
overflow
TCB counter
Program
ex. TBI interrupt frequency is XIN/2
The window gate width of RFO is 2
PROGRAM EXAMPLE
DSEG
ORG 00H
RFCON: RES 1
:
CSEG
ORG 00H
LBR MAIN ;initial jump
ORG 0AH
LBR TBI ;timebase interrupt vector address
:
TBI: CMP #00H,RFCON
B TBI1
STD #01H,RFCON
LDIA #00H ;initial TCB & HTC register
OUTA P5
OUTA P3
STATBL
STATBM
STATBH
B TBIEND
n+1 00 01 00 01n FF
00 001
Disable
HTC and
read data.
TBI interrupt service routine
15
Hz (P25=1101B). The pulse rate of RFO is XIN/215 Hz (P17=1111B).
14
/XIN sec.
Enable HTC
and write data.
Window gate width
;timebase interrupt service routine
*
This specification are subject to be changed without notice.
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TBI1: LDIA #00H ;disable RFO before reading the counter value
OUTA P17
IN A P3 ;store the counter value to RAM[00] - RAM[04]
STA 00H
INA P5
STA 01H
LDATBL
STA 02H
LDATBM
STA 03H
LDATBH
STA 04H
TBIEND: RTI
;main program
MAIN: STD #00H,RFCON
LDIA #0001B ;P4.0 (RX) output
OUTA P18
LDIA #0010B ;enable timebase interrupt
EXAE
EICIL 0
LDIA #1111B ;enable RFO mode, the window gate width of RFO=2
OUTA P17
LDIA #1101B ;enable timebase, interrupt frequency : XIN / 2
OUTA P25
:
15
Hz
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14
/XIN sec.
Melody mode
TONE
The P4.0/
in the melody mode, the P4.0/
and TONE pins will output the square wave in the melody mode. When the CPU is not
TONE
is high and TONE is low.
The 8-bit tone frequency register is P5 and P3. The tone frequency will be changed when users output
the different data to P3. Thus, the data must be output to P5 before P3 when users want to change the
8-bit tone frequency (TF).
P5 P3
3 2 1 0 3 2 1 0 Initial value : 0000 0000 ( TF )
Higher nibble register Lower nibble register
** F
= [ (XIN / 2X) / (100H - TF) ] / 2, TF = 0 ~ 255
TONE
** Example : XIN = 32KHz, RATE = 01, TF = 11110000B = 0F0H.
F
*
This specification are subject to be changed without notice.
= [ (32K Hz / 22) / (100H - 0F0H) ] / 2 = 256 Hz.
TONE
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
PROGRAM EXAMPLE :
LDIA #0FH
OUTA P5
LDIA #00H
OUTA P3
OUTA P18
LDIA #0101B ;enable melody mode
OUTA P17
:
Auto load timer mode
In this mode, there are four different internal pulse rates can be selected by P17. The HTC loads the
initial values by the counter registers (P3, P5) and increases at the rising edges of internal pulse generated
by the time base. The value of TCB increases one when the high speed counter overflows and generates
an overflow interrupt (TRGB) when the TCB overflows.
PROGRAM EXAMPLE :
LDIA #00H ; initial TCB & HTC register
STATBL
STATBM
STATBH
OUTA P5
OUTA P3
OUTA P18
LDIA #1011B ; auto load timer mode, internal pulse rate : XIN/2
OUTA P17
:
LDIA #00H ; disable timer mode
OUTA P17
IN A P3 ; store the counter value to RAM[00] - RAM[04]
STA 00H
INA P5
STA 01H
LDATBL
STA 02H
LDATBM
STA 03H
LDATBH
STA 04H
6
*
This specification are subject to be changed without notice.
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
WW
AA
TCH-DOG-TIMER ( TCH-DOG-TIMER (
W
A
TCH-DOG-TIMER (
WW
AA
TCH-DOG-TIMER ( TCH-DOG-TIMER (
WDT )WDT )
WDT )
WDT )WDT )
Watch-dog-timer can help user to detect the malfunction (runaway) of CPU and give system a time up
signal every certain time. User can use the time up signal to give system a reset signal when system is fail.
This function is available by mask option. If the mask option of WDT is enabled, it will stop counting when
CPU is reseted or in the STOP operation mode.
The basic structure of watch-dog-timer control is composed by a 4-stage binary counter and a control unit.
The WDT counter counts for a certain time to check the CPU status, if there is no malfunction happened,
the counter will be cleared and counting. Otherwise, if there is a malfunction happened, the WDT control
will send a WDT signal (low active) to reset CPU. The WDT checking period is assign by P21 (WDT
command port).
13
WDT counter
XIN / 2
0 1 2 3
RESET pin
counter clear request
WDT control
P21
WDT
command port
P21 is the control port of watch-dog-timer, and the WDT time up signal is connected to
P21 3 2 1 0 Initial value : 0000
CWC * * WDT
CWC Clear watch-dog-timer counter
0 Clear counter then return to 1
1 Nothing
mask option
RESET
.
WDT Set watch-do g-timer detect time
0 3 x 2
1 7 x 2
13
/XIN = 3 x 213/32K Hz = 0.75 sec
13
/XIN = 7 x 213/32K Hz = 1.75 sec
PROGRAM EXAMPLE
13
To enable WDT with 7 x 2
/XIN detection time.
LDIA #0001B
OUTA P21 ;set WDT detection time and clear WDT counter
:
:
*
This specification are subject to be changed without notice.
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
LOLO
W BW B
AA
TTERTTER
LO
W B
LOLO
A
W BW B
AA
EM73362 has a built-in low battery detector. This function is disabled when CPU is reseted or in the STOP
/IDLE operation mode. User must enable the low battery detector by self when the CPU is waked up. If the
low battery detector is enabled, the operating current of whole chip will increase.
TTER
TTERTTER
Y DETECTY DETECT
Y DETECT
Y DETECTY DETECT
OR ( LBD )OR ( LBD )
OR ( LBD )
OR ( LBD )OR ( LBD )
P15.0
BAT
CONTRCONTR
CONTR
CONTRCONTR
3 2 1 0 3 2 1 0
OL OF LOOL OF LO
OL OF LO
OL OF LOOL OF LO
Port15 is the control register of low battery detector. P15.1 (Low battery detector status) is a read-only bit.
When LBE is 1, the low battery detector is enabled. When VDD<1.35 ± 0.05V, SLB is 1.
P15 ( write port ) P15 ( read port ) Initial value : **00
* * * LBE * * SLB *
LBE Low battery detector control SLB Status of low battery detector
0 Low battery detector disable 0 VDD
1 Low battery detector enable 1 VDD < 1.25 ± 0.05V ( Low battery )
W BW B
W B
W BW B
AA
TTERTTER
A
TTER
AA
TTERTTER
Y DETECTY DETECT
Y DETECT
Y DETECTY DETECT
+
_
reference voltage
OROR
OR
OROR
> 1.25 ± 0.05V
*
This specification are subject to be changed without notice.
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
RESETTING FUNCTIONRESETTING FUNCTION
RESETTING FUNCTION
RESETTING FUNCTIONRESETTING FUNCTION
When CPU in normal working condition and RESET pin holds in low level for three instruction cycles at least,
then CPU begins to initialize the whole internal states, and when RESET pin changes to high level, CPU begins
to work in normal condition.
The CPU internal state during reset condition is as following table :
Hardware condition in RESET state Initial value
Program counter 000h
Status flag 01h
Interrupt enable flip-flop ( EI ) 00h
MASK0 ,1, 2, 3 00h
Interrupt latch ( IL ) 00h
P3, 5, 15, 16, 17, 18, 19, 21, 25, 27 00h
P4, 6, 7, 8 0Fh
XIN Start oscillation
The RESET pin is a hysteresis input pin and it has a pull-up resistor available by mask option.
The simplest RESET circuit is connect RESET pin with a capacitor to VSS and a diode to VDD.
RESET
*
This specification are subject to be changed without notice.
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EM73362 PORT DESCRIPTION :EM73362 PORT DESCRIPTION :
EM73362 PORT DESCRIPTION :
EM73362 PORT DESCRIPTION :EM73362 PORT DESCRIPTION :
EM73362EM73362
EM73362
EM73362EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
PortPort
Port
PortPort
0 E Input port , wake-up function ,
1-- -2-- -3 - - I High speed counter register low nibble
4 E Input port , E Output port, P4.0/TONE
5 -- I High speed counter register high nibble
6 E Input port E Output port , LCD segment pin
7 E Input port E Output port , LCD segment pin
8 E Input port E Output port , LCD segment pin
9-- -10 -- -11 -- -12 -- -13 -- -14 -- -15 I P15.1 ( low battery detector status ) I P15.1 ( low battery detector control )
16 I Stop mode control register
17 I HTC control register
18 I HTC control register
19 I Idle mode control register
20 -21 I WDT control register
22 -23 -24 -25 I Timebase control register
26 -27 I LCD control register
28 I Timer A control register
29 -30 -31 --
Input functionInput function
Input function
Input functionInput function
external interrupt input
Resistor to frequency oscillation
Output functionOutput function
Output function
Output functionOutput function
NoteNote
Note
NoteNote
*
This specification are subject to be changed without notice.
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EM73362EM73362
EM73362
EM73362EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
ABSOLUTE MAXIMUM RAABSOLUTE MAXIMUM RA
ABSOLUTE MAXIMUM RA
ABSOLUTE MAXIMUM RAABSOLUTE MAXIMUM RA
TINGTING
TING
TINGTING
Items Sym. Ratings Conditions
Supply voltage V
Input voltage V
Output voltage V
Power dissipation P
Operating temperature T
Storage temperature T
RECOMMENDED OPERARECOMMENDED OPERA
RECOMMENDED OPERA
RECOMMENDED OPERARECOMMENDED OPERA
DD
IN
O
D
OPR
STG
TING CONDITIONSTING CONDITIONS
TING CONDITIONS
TING CONDITIONSTING CONDITIONS
-0.5V to 2V
-0.5V to VDD + 0.5V
-0.5V to VDD + 0.5V
100mW T
0 °C to 50 °C
-55 °C to 125 °C
= 50 °C
OPR
Items Sym. Ratings Conditions
Supply voltage V
Input voltage V
DC ELECTRICAL CHARADC ELECTRICAL CHARA
DC ELECTRICAL CHARA
DC ELECTRICAL CHARADC ELECTRICAL CHARA
DD
IH
V
IL
CTERISTICS ( CTERISTICS (
CTERISTICS (
CTERISTICS ( CTERISTICS (
1.2V to 1.8V Fc = 32KHz
0.90 x VDD to V
0V to 0.10 x V
VV
V
VV
DD
DD
= 1.5 ± 0.2V = 1.5 ± 0.2V
= 1.5 ± 0.2V
= 1.5 ± 0.2V = 1.5 ± 0.2V
DDDD
DD
DDDD
,,
VV
= 0V = 0V
,,
= 0V
= 0V = 0V
,
,,
,
V
,,
VV
SSSS
SS
SSSS
TT
T
TT
OPROPR
OPR
OPROPR
Parameters Sym. Min. Typ. Max. Unit Conditions
Supply current I
-610µA RC osc. VDD=1.7V, Fc=32KHz, no load,
DD
-58µAX’tal osc. RFO off, LBD off
-48µA RC osc. V
-36µAX’tal osc. mode, no load
- 0.1 1 µAVDD=1.7V, STOP mode
- 80 250 µAX’tal osc. V
-4060µAV
Low battery detector V
Frequency of RFO F
Frequency ratio of F
RFO F
Hysteresis voltage V
Input current I
1.20 1.25 1.30 V
LBD
95 120 140 KHz R = 10KΩ,VDD=1.5V
RF1
8.9 10.5 13 KHz R = 100KΩ,VDD=1.5V
F
RF2
F
780 980 1300 Hz R = 1MΩ,VDD=1.5V
RF3
10.1 10.6 11.1 VDD=1.5V, R1=10KΩ, R2=100KΩ,
RF1
RF2
F
10.1 10.6 11.1
RF2
F
RF3
0.50V
HYS+
V
0.20V
HYS-
-1015µA P0, Pull-down, VIH=V
IH
- 0.75V
DD
- 0.40V
DD
V RESET, P0
DD
V
DD
R3=1MΩ
-15 -10 - µA P0, Pull-up, VIH=V
--1µA P0, None
Output voltage V
1.1 - - V Push-pull : P4 high current PMOS, TONE
OH
=1.3V, IOH=-500µA
V
DD
1.1 - - V Push-pull : P4 low current PMOS, others,
V
=1.3V, IOH=-30µA
V
Leakage current I
Input resistor R
LCD bias voltage V
- - 0.2 V VDD=1.3V, IOL=500µA
OL
--1µA Open-drain, VDD=1.7V, VO=1.7V
LO
50 100 200 KΩ RESET
IN
2VDD-0.1 2V
EE
2VDD+0.1 V Voltage doubler
DD
DD
= 25°C ) = 25°C )
= 25°C )
= 25°C ) = 25°C )
=1.7V, Fc=32KHz, IDLE
DD
=1.5V, Fc=32KHz, RFO on
DD
=1.5V, Fc=32KHz, LBD on
DD
DD
SS
*
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Parameters Sym. Min. Typ. Max. Unit Conditions
COM, SEG pins Vo
output current Vo
Vo
VEE-0.1 V
1
VDD-0.1 V
2
-V
3
-VIo
EE
VDD+0.1 V Io2 = ±5µA
DD
VSS+0.1 V Io3 = 5µA
SS
= -5µA
1
Frequency stability - 20 - % Fc=32K Hz, RC osc, R=620KΩ,
[F(1.5V)-F(1.3V)]/F(1.5V)
Frequency variation - 20 - % Fc=32K Hz, V
=1.5V, RC osc,R=620KΩ,
DD
[F(typical)-F(worse case)]/F(typical)
EM73362EM73362
EM73362
EM73362EM73362
*
This specification are subject to be changed without notice.
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RESET PIN TYPE
TYPE RESET_A
EM73362EM73362
EM73362
EM73362EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
RESET
mask option
OSCILLATION PIN TYPE
TYPE OSC_A TYPE OSC_F
XIN
Crystal
Osc.
XOUT
XIN
XOUT
INPUT PIN TYPE
TYPE INPUT_H TYPE INPUT_J
WAKEUP function
mask option
RC Osc.
(inverter)
WAKEUP function
mask option
: mask option
I/O PIN TYPE
TYPE I/O_N TYPE I/O_O
: mask option
*
This specification are subject to be changed without notice.
TYPE I/O_N
: mask option
path B
path A
input data
special function
control input
: mask option
Output
data
latch
Special function output
Input
data
Output
data
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
TYPE I/O_X
TYPE I/O_N
path B
path A
SEL
Output
data
latch
Special function
control input
Input data
Output
data
TYPE I/O_Y
MUX
Special function control output
path B
path A
TYPE I/O_N
Output
data
latch
Input
data
Output
data
PATH A :For set and clear bit of port instructions, data goes through path A from output data latch to CPU.
PATH B :For input and test instructions, data from output pin go through path B to CPU and the output data
latch will be set to high.
*
This specification are subject to be changed without notice.
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PAD DIAGRAMPAD DIAGRAM
PAD DIAGRAM
PAD DIAGRAMPAD DIAGRAM
SEG2
SEG3
SEG4
SEG5
SEG6
EM73362EM73362
EM73362
EM73362EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG1
SEG0
COM1
COM0
VEE
VSS
XIN
XOUT
VDD
VB
VA
10
11
434446 45474849
1
2
3
4
5
6
7
8
9
Y
(0,0)
EM73362
12
13
14
15 16
17 18
40 38394142
X
19 20 21 22
37
23
36
35
34
33
32
31
30
29
28
27
26
25
24
P8.0/SEG15
P8.1/SEG16
P8.2/SEG17
P8.3/SEG18
P7.0/SEG19
P7.1/SEG20
P7.2/SEG21
P7.3/SEG22
P6.0/SEG23
P6.1/SEG24
P6.2/SEG25
P6.3/SEG26
COM2
BAT
RESET
P0.1/WAKEUP1
P0.0(INT1)/WAKEUP0
P0.2(INT0)/WAKEUP2
TONE
P0.3/WAKEUP3
Chip Size : 2140 x 2070 UM.
Pad No. Pad No.
Pad No.
Pad No. Pad No.
SymbolSymbol
Symbol
SymbolSymbol
1 SEG1 -911.4 752.3
2 SEG0 -911.4 632.4
3 COM1 -911.4 512.5
4 COM0 -911.4 392.0
5 VEE -910.5 270.5
6 VB -910.5 148.4
7 VA -910.5 27.4
*
This specification are subject to be changed without notice.
P4.1(CS)
P4.0(RX)/TONE
XX
X
XX
P4.2(RS)
P4.3(RZ)
TEST
YY
Y
YY
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EM73362EM73362
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Pad No.Pad No.
Pad No.
Pad No.Pad No.
SymbolSymbol
Symbol
SymbolSymbol
XX
X
XX
8 VSS -896.4 -132.1
9 XIN -911.4 -263.9
10 XOUT -911.4 -636.1
11 VDD -892.4 -857.5
12 BAT -705.0 -874.1
13 RESET -583.0 -874.1
14 P0.0(INT1)/WAKEUP0 -463.1 -874.1
15 P0.1/WAKEUP1 -338.5 -874.1
16 P0.2(INT0)/WAKEUP2 -213.8 -874.1
17 PO.3/WAKEUP3 -89.2 -874.1
18 TONE 47.3 -877.4
19 P4.0(RX)/TONE 168.8 -877.4
20 P4.1(CS) 290.4 -877.4
21 P4.2(RS) 411.9 -877.4
22 P4.3(RZ) 533.5 -877.4
23 TEST 655.6 -874.1
24 COM2 907.9 -772.2
25 P6.3/SEG26 907.1 -637.8
26 P6.2/SEG25 907.1 -516.2
27 P6.1/SEG24 907.1 -394.7
28 P6.0/SEG23 907.1 -273.1
29 P7.3/SEG22 907.1 -151.6
30 P7.2/SEG21 907.1 -30.0
31 P7.1/SEG20 907.1 91.5
32 P7.0/SEG19 907.1 213.1
33 P8.3/SEG18 907.1 334.6
34 P8.2/SEG17 907.1 456.2
35 P8.1/SEG16 907.1 577.7
36 P8.0/SEG15 907.1 699.3
37 SEG14 692.3 874.7
38 SEG13 572.4 874.7
39 SEG12 452.5 874.7
40 SEG11 332.6 874.7
41 SEG10 212.7 874.7
42 SEG9 92.8 874.7
43 SEG8 -27.1 874.7
44 SEG7 -147.0 874.7
45 SEG6 -266.9 874.7
46 SEG5 -386.8 874.7
47 SEG4 -506.7 874.7
48 SEG3 -626.6 874.7
49 SEG2 -746.5 874.7
Unit : µm
For PCB layout, IC substrate must be floated or connected to Vss.
*
This specification are subject to be changed without notice.
YY
Y
YY
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INSTRUCTION TABLEINSTRUCTION TABLE
INSTRUCTION TABLE
INSTRUCTION TABLEINSTRUCTION TABLE
(1) Data Transfer(1) Data Transfer
(1) Data Transfer
(1) Data Transfer(1) Data Transfer
EM73362EM73362
EM73362
EM73362EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Mnemonic Object code ( binary )Mnemonic Object code ( binary )
Mnemonic Object code ( binary )
Mnemonic Object code ( binary )Mnemonic Object code ( binary )
Operation descriptionOperation description
Operation description
Operation descriptionOperation description
ByteByte
Byte
ByteByte
CycleCycle
Cycle
CycleCycle
Flag Flag
Flag
Flag Flag
CC
C
CC
ZZ
S S
Z
S
ZZ
S S
LDA x 0110 1010 xxxx xxxx Acc←RAM[x] 2 2 - Z 1
LDAM 0101 1010 Acc ←RAM[HL] 1 1 - Z 1
LDAX 0110 0101 Acc←ROM[DP]
LDAXI 0110 0111 Acc←ROM[DP]
L
,DP+1 1 2 - Z 1
H
12-Z1
LDH #k 1001 kkkk HR←k11--1
LDHL x 0100 1110 xxxx xx00 LR←RAM[x],HR←RAM[x+1] 2 2 - - 1
LDIA #k 1101 kkkk Acc←k11-Z1
LDL #k 1000 kkkk LR←k11--1
STA x 0110 1001 xxxx xxxx RAM[x]←Acc 2 2 - - 1
STAM 0101 1001 RAM[HL]←Acc 1 1 - - 1
STAMD 0111 1101 RAM[HL]←Acc, LR-1 1 1 - Z C
STAMI 0111 1111 RAM[HL]←Acc, LR+1 1 1 - Z C'
STD #k,y 0100 1000 kkkk yyyy RAM[y]←k22--1
STDMI #k 1010 kkkk RAM[HL]←k, LR+1 1 1 - Z C'
THA 0111 0110 Acc←HR 1 1 - Z 1
TLA 0111 0100 Acc←LR 1 1 - Z 1
(2) Rotate(2) Rotate
(2) Rotate
(2) Rotate(2) Rotate
Mnemonic Object code ( binary )Mnemonic Object code ( binary )
Mnemonic Object code ( binary )
Mnemonic Object code ( binary )Mnemonic Object code ( binary )
Operation descriptionOperation description
Operation description
Operation descriptionOperation description
ByteByte
Byte
ByteByte
CycleCycle
Cycle
CycleCycle
Flag Flag
Flag
Flag Flag
CC
C
CC
ZZ
SS
Z
S
ZZ
SS
RLCA 0101 0000 ←CF←Acc← 11CZC'
RRCA 0101 0001 →CF→Acc→ 11CZC'
3) Arithmetic operation3) Arithmetic operation
(
3) Arithmetic operation
3) Arithmetic operation3) Arithmetic operation
Mnemonic Object code ( binary )Mnemonic Object code ( binary )
Mnemonic Object code ( binary )
Mnemonic Object code ( binary )Mnemonic Object code ( binary )
Operation descriptionOperation description
Operation description
Operation descriptionOperation description
ByteByte
Byte
ByteByte
CycleCycle
Cycle
CycleCycle
Flag Flag
Flag
Flag Flag
CC
C
CC
Z Z
Z
Z Z
SS
S
SS
ADCAM 0111 0000 Acc←Acc + RAM[HL] + CF 1 1 C Z C'
ADD #k,y 0100 1001 kkkk yyyy RAM[y]←RAM[y] +k 2 2 - Z C'
ADDA #k 0110 1110 0101 kkkk Acc←Acc+k 2 2 - Z C'
ADDAM 0111 0001 Acc←Acc + RAM[HL] 1 1 - Z C'
ADDH #k 0110 1110 1001 kkkk HR←HR+k 2 2 - Z C'
ADDL #k 0110 1110 0001 kkkk LR←LR+k 2 2 - Z C'
ADDM #k 0110 1110 1101 kkkk RAM[HL]←RAM[HL] +k 2 2 - Z C'
DECA 0101 1100 Acc←Acc-1 1 1 - Z C
DECL 0111 1100 LR←LR-1 1 1 - Z C
DECM 0101 1101 RAM[HL]←RAM[HL]-1 1 1 - Z C
INCA 0101 1110 Acc←Acc + 1 1 1 - Z C'
*
This specification are subject to be changed without notice.
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EM73362
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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
INCL 0111 1110 LR←LR + 1 1 1 - Z C'
INCM 0101 1111 RAM[HL]←RAM[HL]+1 1 1 - Z C'
SUBA #k 0110 1110 0111 kkkk Acc←k-Acc 2 2 - Z C
SBCAM 0111 0010 Acc←RAM[HLl - Acc - CF' 1 1 C Z C
SUBM #k 0110 1110 1111 kkkk RAM[HL]←k - RAM[HL] 2 2 - Z C
((
4) Logical operation4) Logical operation
(
4) Logical operation
4) Logical operation4) Logical operation
((
Mnemonic Object code ( binary )Mnemonic Object code ( binary )
Mnemonic Object code ( binary )
Mnemonic Object code ( binary )Mnemonic Object code ( binary )
ANDA #k 0110 1110 0110 kkkk Acc←Acc&k 2 2 - Z Z'
ANDAM 0111 1011 Acc←Acc & RAM[HL] 1 1 - Z Z'
ANDM #k 0110 1110 1110 kkkk RAM[HL]←RAM[HL]&k 2 2 - Z Z'
ORA #k 0110 1110 0100 kkkk Acc←Acc k 2 2 - Z Z'
ORAM 0111 1000 Acc ←Acc RAM[HL] 1 1 - Z Z'
ORM #k 0110 1110 1100 kkkk RAM[HL]←RAM[HL] k 2 2 - Z Z'
XORAM 0111 1001 Acc←Acc^RAM[HL] 1 1 - Z Z'
(5) Exchange(5) Exchange
(5) Exchange
(5) Exchange(5) Exchange
Mnemonic Object code ( binary )Mnemonic Object code ( binary )
Mnemonic Object code ( binary )
Mnemonic Object code ( binary )Mnemonic Object code ( binary )
Operation descriptionOperation description
Operation description
Operation descriptionOperation description
- -
- -
Operation descriptionOperation description
Operation description
Operation descriptionOperation description
- -
ByteByte
Byte
ByteByte
ByteByte
Byte
ByteByte
CycleCycle
Cycle
CycleCycle
CycleCycle
Cycle
CycleCycle
Flag Flag
Flag
Flag Flag
CC
C
CC
Flag Flag
Flag
Flag Flag
CC
C
CC
EXA x 0110 1000 xxxx xxxx Acc↔RAM[x] 2 2 - Z 1
EXAH 0110 0110 Acc↔HR 1 2 - Z 1
EXAL 0110 0100 Acc↔LR 1 2 - Z 1
EXAM 0101 1000 Acc↔RAM[HL] 1 1 - Z 1
EXHL x 0100 1100 xxxx xx00 LR↔RAM[x],
HR↔RAM[x+1] 2 2 - - 1
(6) Branch(6) Branch
(6) Branch
(6) Branch(6) Branch
ZZ
SS
Z
S
ZZ
SS
ZZ
SS
Z
S
ZZ
SS
Mnemonic Object code ( binary )Mnemonic Object code ( binary )
Mnemonic Object code ( binary )
Mnemonic Object code ( binary )Mnemonic Object code ( binary )
SBR a 00aa aaaa If SF=1 then PC←PC
Operation descriptionOperation description
Operation description
Operation descriptionOperation description
11-6.a5-0
ByteByte
Byte
ByteByte
CycleCycle
Cycle
CycleCycle
Flag Flag
Flag
Flag Flag
CC
C
CC
11--1
else null
LBR a 1100 aaaa aaaa aaaa If SF= 1 then PC←a else null 2 2 - - 1
(7) Compare(7) Compare
(7) Compare
(7) Compare(7) Compare
Mnemonic Object code ( binary )Mnemonic Object code ( binary )
Mnemonic Object code ( binary )
Mnemonic Object code ( binary )Mnemonic Object code ( binary )
Operation descriptionOperation description
Operation description
Operation descriptionOperation description
ByteByte
Byte
ByteByte
CycleCycle
Cycle
CycleCycle
Flag Flag
Flag
Flag Flag
CC
C
CC
CMP #k,y 0100 1011 kkkk yyyy k-RAM[y] 2 2 C Z Z'
CMPA x 0110 1011 xxxx xxxx RAM[x]-Acc 2 2 C Z Z'
CMPAM 0111 0011 RAM[HL] - Acc 1 1 C Z Z'
CMPH #k 0110 1110 1011 kkkk k - HR 2 2 - Z C
CMPIA #k 1011 kkkk k - Acc 1 1 C Z Z'
CMPL #k 0110 1110 0011 kkkk k-LR 2 2 - Z C
*
This specification are subject to be changed without notice.
10.8.2001
ZZ
SS
Z
S
ZZ
SS
ZZ
SS
Z
S
ZZ
SS
37
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(8) Bit manipulation(8) Bit manipulation
(8) Bit manipulation
(8) Bit manipulation(8) Bit manipulation
EM73362EM73362
EM73362
EM73362EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
Mnemonic Object code ( binary )Mnemonic Object code ( binary )
Mnemonic Object code ( binary )
Mnemonic Object code ( binary )Mnemonic Object code ( binary )
Operation descriptionOperation description
Operation description
Operation descriptionOperation description
ByteByte
Byte
ByteByte
CycleCycle
Cycle
CycleCycle
Flag Flag
Flag
Flag Flag
CC
C
CC
ZZ
SS
Z
S
ZZ
SS
CLM b 1111 00bb RAM[HL]b←011--1
CLP p,b 0110 1101 11bb pppp PORT[p]
CLPL 0110 0000 PORT[LR
CLR y,b 0110 1100 11bb yyyy RAM[y]
←022--1
b
+4]LR
3-2
←022--1
b
←012--1
1-0
SEM b 1111 01bb RAM[HL]b←111--1
SEP p,b 0110 1101 01bb pppp PORT[p]
SEPL 0110 0010 PORT[LR
SET y, b 0110 1100 01bb yyyy RAM[y]
TF y,b 0110 1100 00bb yyyy SF←RAM[y]
←122--1
b
+4]LR
3-2
←122--1
b
←112 --1
l-0
'22--*
b
TFA b 1111 10bb SF←Accb'11--*
TFM b 1111 11bb SF←RAM[HL]
TFP p,b 0110 1101 00bb pppp SF←PORT[p]
TFPL 0110 0001 SF←PORT[LR
TT y,b 0110 1100 10bb yyyy SF←RAM[y]
TTP p, b 0110 1101 10bb pppp SF←PORT[p]
(9) Subroutine(9) Subroutine
(9) Subroutine
(9) Subroutine(9) Subroutine
Mnemonic Object code ( binary )Mnemonic Object code ( binary )
Mnemonic Object code ( binary )
Mnemonic Object code ( binary )Mnemonic Object code ( binary )
Operation descriptionOperation description
Operation description
Operation descriptionOperation description
'11--*
b
'22--*
b
b
b
+4]LR
3-2
'12--*
1-0
22--*
22--*
ByteByte
Byte
ByteByte
CycleCycle
Cycle
CycleCycle
Flag Flag
Flag
Flag Flag
CC
C
CC
ZZ
SS
Z
S
ZZ
SS
LCALL a 0100 0aaa aaaa aaaa STACK[SP]←PC, 2 2 - - -
SP←SP -1, PC←a
SCALL a 1110 nnnn STACK[SP]←PC, 1 2 - - -
SP←SP - 1, PC←a,a = 8n + 6
(n =1∼15),0086h (n = 0)
RET 0100 1111 SP←SP + 1, PC←STACK[SP] 1 2 - - -
(10) Input/output(10) Input/output
(10) Input/output
(10) Input/output(10) Input/output
Mnemonic Object code ( binary )Mnemonic Object code ( binary )
Mnemonic Object code ( binary )
Mnemonic Object code ( binary )Mnemonic Object code ( binary )
Operation descriptionOperation description
Operation description
Operation descriptionOperation description
ByteByte
Byte
ByteByte
CycleCycle
Cycle
CycleCycle
Flag Flag
Flag
Flag Flag
CC
C
CC
ZZ
SS
Z
S
ZZ
SS
INA p 0110 1111 0100 pppp Acc←PORT[p] 2 2 - Z Z'
INM p 0110 1111 1100 pppp RAM[HL]←PORT[p] 2 2 - - Z'
OUT #k,p 0100 1010 kkkk pppp PORT[p]←k22--1
OUTA p 0110 1111 000p pppp PORT[p]←Acc 2 2 - - 1
OUTM p 0110 1111 100p pppp PORT[p]←RAM[HL] 2 2 - - 1
(11) Flag manipulation(11) Flag manipulation
(11) Flag manipulation
(11) Flag manipulation(11) Flag manipulation
Mnemonic Object code ( binary )Mnemonic Object code ( binary )
Mnemonic Object code ( binary )
Mnemonic Object code ( binary )Mnemonic Object code ( binary )
Operation descriptionOperation description
Operation description
Operation descriptionOperation description
ByteByte
Byte
ByteByte
CycleCycle
Cycle
CycleCycle
Flag Flag
Flag
Flag Flag
CC
C
CC
ZZ
SS
Z
S
ZZ
SS
CGF 0101 0111 GF←011--1
SGF 0101 0101 GF←111--1
*
This specification are subject to be changed without notice.
10.8.2001
38
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EM73362EM73362
EM73362
EM73362EM73362
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
TFCFC 0101 0011 SF←CF', CF←0110-*
TGS 0101 0100 SF←GF 1 1 - - *
TTCFS 0101 0010 SF←CF, CF←1111-*
TZS 0101 1011 SF←ZF 1 1 - - *
(12) Interrupt control(12) Interrupt control
(12) Interrupt control
(12) Interrupt control(12) Interrupt control
Mnemonic Object code ( binary )Mnemonic Object code ( binary )
Mnemonic Object code ( binary )
Mnemonic Object code ( binary )Mnemonic Object code ( binary )
Operation descriptionOperation description
Operation description
Operation descriptionOperation description
ByteByte
Byte
ByteByte
CycleCycle
Cycle
CycleCycle
Flag Flag
Flag
Flag Flag
CC
C
CC
CIL r 0110 0011 11rr rrrr IL←IL & r 2 2 - - 1
DICIL r 0110 0011 10rr rrrr EIF←0,IL←IL&r 2 2 - - 1
EICIL r 0110 0011 01rr rrrr EIF←1,IL←IL&r 2 2 - - 1
EXAE 0111 0101 MASK↔Acc 1 1 - - 1
RTI 0100 1101 SP←SP+1,FLAG.PC 1 2 * * *
←STACK[SP],EIF ←1
(13) CPU control(13) CPU control
(13) CPU control
(13) CPU control(13) CPU control
Mnemonic Object code ( binary )Mnemonic Object code ( binary )
Mnemonic Object code ( binary )
Mnemonic Object code ( binary )Mnemonic Object code ( binary )
Operation descriptionOperation description
Operation description
Operation descriptionOperation description
ByteByte
Byte
ByteByte
CycleCycle
Cycle
CycleCycle
Flag Flag
Flag
Flag Flag
CC
C
CC
NOP 0101 0110 no operation 1 1 - - -
(14) Timer/Counter & Data pointer & Stack pointer control(14) Timer/Counter & Data pointer & Stack pointer control
(14) Timer/Counter & Data pointer & Stack pointer control
(14) Timer/Counter & Data pointer & Stack pointer control(14) Timer/Counter & Data pointer & Stack pointer control
Mnemonic Object code ( binary )Mnemonic Object code ( binary )
Mnemonic Object code ( binary )
Mnemonic Object code ( binary )Mnemonic Object code ( binary )
LDADPL 0110 1010 1111 1100 Acc←[DP]
LDADPM 0110 1010 1111 1101 Acc←[DP]
LDADPH 0110 1010 1111 1110 Acc←[DP]
Operation descriptionOperation description
Operation description
Operation descriptionOperation description
L
M
H
ByteByte
Byte
ByteByte
CycleCycle
Cycle
CycleCycle
Flag Flag
Flag
Flag Flag
CC
C
CC
22-Z1
22-Z1
22-Z1
LDASP 0110 1010 1111 1111 Acc←SP 2 2 - Z 1
LDATAL 0110 1010 1111 0100 Acc←[TA]
LDATAM 0110 1010 1111 0101 Acc←[TA]
LDATAH 0110 1010 1111 0110 Acc←[TA]
LDATBL 0110 1010 1111 1000 Acc←[TB]
LDATBM 0110 1010 1111 1001 Acc←[TB]
LDATBH 0110 1010 1111 1010 Acc←[TB]
STADPL 0110 1001 1111 1100 [DP]
STADPM 0110 1001 1111 1101 [DP]
STADPH 0110 1001 1111 1110 [DP]
←Acc 2 2 - - 1
L
←Acc 2 2 - - 1
M
←Acc 2 2 - - 1
H
L
M
H
L
M
H
22-Z1
22-Z1
22 -Z1
22-Z1
22-Z1
22-Z1
STASP 0110 1001 1111 1111 SP←Acc 2 2 - - 1
STATAL 0110 1001 1111 0100 [TA]
STATAM 0110 1001 1111 0101 [TA]
STATAH 0110 1001 1111 0110 [TA]
STATBL 0110 1001 1111 1000 [ TB]
STATBM 0110 1001 1111 1001 [TB]
STATBH 0110 1001 1111 1010 [TB]
←Acc 2 2 - - 1
L
←Acc 2 2 - - 1
M
←Acc 2 2 - - 1
H
←Acc 2 2 - - 1
L
←Acc 2 2 - - 1
M
←Acc 2 2 - - 1
H
ZZ
SS
Z
S
ZZ
SS
ZZ
SS
Z
S
ZZ
SS
ZZ
SS
Z
S
ZZ
SS
*
This specification are subject to be changed without notice.
10.8.2001
39
Page 40
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
4-BIT MICRO-CONTROLLER FOR LCD PRODUCT4-BIT MICRO-CONTROLLER FOR LCD PRODUCT
**** SYMBOL DESCRIPTION**** SYMBOL DESCRIPTION
**** SYMBOL DESCRIPTION
**** SYMBOL DESCRIPTION**** SYMBOL DESCRIPTION
SymbolSymbol
Symbol
SymbolSymbol
DescriptionDescription
Description
DescriptionDescription
SymbolSymbol
Symbol
SymbolSymbol
DescriptionDescription
Description
DescriptionDescription
HR H register LR L register
PC Program counter DP Data pointer
SP Stack pointer STACK[SP] Stack specified by SP
A
CC
Accumulator FLAG All flags
CF Carry flag ZF Zero flag
SF Status flag GF General flag
EI Enable interrupt register IL Interrupt latch
MASK Interrupt mask PORT[p] Port ( address : p )
ΤΑ Timer/counter A ΤΒ Timer/counter B
RAM[HL] Data memory (address : HL ) RAM[x] Data memory (address : x )
ROM[DP]
[DP]
L
[DP]
H
L
Low 4-bit of program memory ROM[DP]
Low 4-bit of data pointer register [DP]
M
H
High 4-bit of program memory
Middle 4-bit of data pointer register
High 4-bit of data pointer register [TA]L([TB]L) Low 4-bit of timer/counter A
(timer/counter B) register
[TA]M([TB]M) Middle 4-bit of timer/counter A [TA]H([TB]H) High 4-bit of timer/counter A
(timer/counter B) register (timer/counter B) register
← Transfer ↔ Exchange
+ Addition - Substraction
- -
& Logic AND Logic OR
^ Logic XOR ' Inverse operation
. Concatenation #k 4-bit immediate data
x 8-bit RAM address y 4-bit zero-page address
p 4-bit or 5-bit port address b Bit address
r 6-bit interrupt latch PC
LR
1-0
Contents of bit assigned by bit a
5-0
11-6
Bit 11 to 6 of program counter
Bit 5 to 0 of destination address for
1 to 0 of LR branch instruction
LR
3-2
Bit 3 to 2 of LR
EM73362EM73362
EM73362
EM73362EM73362
*
This specification are subject to be changed without notice.
10.8.2001
40
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