Datasheet EM564161BC-85, EM564161BC-70, EM564161BA-85E, EM564161BA-85, EM564161BA-70E Datasheet (ETRON)

EtronTech

EM564161

256K x 16 Low Power SRAM

Preliminary, Rev 2.6 10/2000

Features

• Single power supply voltage of 2.3V to 3.6V

• Power down features using CE1# and CE2

• Low power dissipation

• Data retention supply voltage: 1.0V to 3.6V

• Direct TTL compatibility for all input and output

• Wide operating temperature range: -40°C to 85°C

• Standby current @ VDD = 3.6 V

I

DDS2

Typical Maximum
EM564161BA/BC-70/85
EM564161BA-70E/85E

1 µA 10 µA
5 µA 80 µA

Ordering Information

Part Number Speed I

EM564161BC-70 70 ns
EM564161BA-70 70 ns
EM564161BA-70E 70 ns
EM564161BC-85 85 ns
EM564161BA-85 85 ns
EM564161BA-85E 85 ns

DDS2

10 µA
10 µA
80 µA
10 µA
10 µA
80 µA

Package

6x8 BGA
8x10 BGA
8x10 BGA
6x8 BGA
8x10 BGA
8x10 BGA

Pin Configuration

48-Ball BGA (CSP), Top View

1 2 3 4 5 6

A

LB# OE# A0 A1 A 2 CE 2

B

DQ8 U B # A3 A4 CE 1 # DQ 0

C

DQ9 DQ10 A5 A6 DQ1 DQ2

D

GND D Q 1 1 A 17 A7 DQ 3 VDD

E

VDD DQ12 NC A1 6 DQ4 G ND

F

DQ1 4 DQ1 3 A14 A15 DQ5 DQ 6

G

DQ1 5 NC A12 A 13 W E# DQ7

H

NC A8 A9 A10 A11 NC

Pin Description

Symbol Function

A0 - A17 Address Inputs
DQ0 - DQ15 Data Inputs / Outputs
CE1#, CE2 Chip Enable Inputs
OE# Output Enable
WE# Read / Write Control Input
LB#, UB# Data Byte Control Inputs
GND Ground
V

DD

NC No Connection

Power Supply

Overview

The EM564161 is a 4,194,304-bit SRAM organized as 262,144 words by 16 bits. It is designed with advanced
CMOS technology. This Device operates from a single 2.3V to 3.6V power supply. Advanced circuit
technology provides both high speed and low power. It is automatically placed in low-power mode when chip
enable (CE1#) is asserted high or (CE2) is asserted low. There are three control inputs. CE1# and CE2 are
used to select the device and for data retention control, and output enable (OE#) provides fast memory access.
Data byte control pin (LB#,UB#) provides lower and upper byte access. This device is well suited to various
microprocessor system applications where high speed, low power and battery backup are required. And, with a
guaranteed operating range from -40°C to 85°C, the EM564161 can be used in environments exhibiting
extreme temperature conditions.

Etron Technology, Inc.

No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.
TEL: [phone] FAX: [phone]

Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.

EtronTech

Block Diagram

EM564161

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

A0

A17

MEMORY

CELL ARRAY

2,048X128X16

(4,194,304)

SENSE AMP

COLUMN ADDRESS
DECODE R

VDD

GND

WE#
UB#

LB#

OE#
CE1#
CE2

Preliminary

POWER DOWN
CIRCUIT

2 Rev 2.6

October 2000

EtronTech

Operating Mode

Mode CE1# CE2 OE# WE# LB# UB# DQ0~DQ7 DQ8~DQ15

EM564161

L L D

Read L H L H

Write L H X L

L H H H X X

Output Deselect

L H X X H H

H X X X X X

Standby

X L X X X X

H L High-Z D

L H D
L L D

H L High-Z D

L H D

Note: X = don't care. H=logic high. L=logic low.

Absolute Maximum Ratings

OUT

OUT

IN

IN

High-Z High-Z

High-Z High-Z

D

OUT
OUT

High-Z

D

IN
IN

High-Z

Supply voltage, V
Input voltages, V

Input and output voltages, V
Operating temperature, T

Storage temperature, T
Soldering Temperature (10s), T
Power dissipation, P

DD

IN

I/O

OPR

STRG

D

SOLDER

-0.3 to +4.6V

-0.3 to +4.6V

-0.5 to V

-40 to +85°C

-55 to +150°C

DD

+0.5V

260°C

0.6 W

DC Recommended Operating Conditions (Ta=-40°C to 85°C)

Symbol Parameter Min Typ Max Unit

V

DD

V

IH

V

IL

V

DR
Note:
(1) Overshoot : VDD +2.0V in case of pulse width ≤ 20ns
(2) Undershoot : -2.0V in case of pulse width ≤ 20ns

Power Supply Voltage 2.3

Input High Voltage 2.2

Input Low Voltage -0.3

Data Retention Supply Voltage 1.0

(2)

−

−

−

−

3.6 V

V

+ 0.3

DD

0.6 V

3.6 V

(1)

V

Preliminary

3 Rev 2.6

October 2000

EtronTech

EM564161

DC Characteristics (Ta = -40°C to 85°C, VDD = 2.3V to 3.6V)

Parameter Symbol Test Conditions Min Typ* Max Unit

Input low current I
Output low

voltage
Output high

voltage

Operating current

Standby current

Notes:

* Typical value are measured at Ta = 25°C.
** In standby mode with CE1# ≥ VDD - 0.2V, these limits are assured for the condition
CE2 ≥ V

- 0.2V or CE2 ≤ 0.2V.

DD

V

V

DD1

I

DD2

I

DDS1

I

DDS2

(Note)

IL

OL

OH

I

= 0V to V

IN

I

= 2.1 mA -

OL

I

= -1.0 mA

OH

CE1# = V
CE2 = V
I

OUT

Other Input = V

CE1# = V

CE1# = V

**

CE2 = 0.2V

IL

IH

= 0mA

IH

DD

DD

and

and

/ V

IH

or CE2 = V

– 0.2V or

Cycle time

IL

IL

-70/85

-70E/85E V

V

DD

V

V

V
V
V

DD

DD

DD
DD
DD
DD

= min

Cycle time = 1µs

= 3.6 V

= 2.7 V

= 2.3 V

= 3.6 V
= 2.7 V
= 2.3 V
= 3.6 V

- 1

VDD -

0.15

−

−

−

− −

− −

−

−

−

−

−

0.4 V

−

− −

15 25

10 15I

7 12

0.5 mA

1 10

0.8

0.5
5 80

1

µA

V

mA

5

5

µA

3

Capacitance (Ta = 25°C; f = 1 MHz)

Parameter Symbol Min Typ Max Unit Test Conditions

Input capacitance C
Output capacitance C

Notes:

This parameter is periodically sampled and is not 100% tested.

Preliminary

IN

OUT

− −

− −

10 pF VIN = GND
10 pF V

OUT

= GND

4 Rev 2.6

October 2000

EtronTech

EM564161

AC Characteristics and Operating Conditions (Ta = -40°C to 85°C, VDD = 2.3V to 3.6V)

Read Cycle

EM564161

Symbol Parameter

-85 -70

Min Max Min Max

Unit

t

RC

t

AA

t

CO1

t

CO2
t

OE

t

BA

t

LZ

t

OLZ

t

BLZ
t

HZ

t

OHZ

t

BHZ
t

OH

Write Cycle

Symbol Parameter

Read cycle time 85
Address access time
Chip Enable (CE1#) Access Time
Chip Enable (CE2) Access Time
Output enable access time
Data Byte Control Access Time
Chip Enable Low to Output in Low-Z 10
Output enable Low to Output in Low-Z 3
Data Byte Control Low to Output in Low-Z 5
Chip Enable High to Output in High-Z
Output Enable High to Output in High-Z
Data Byte Control High to Output in High-Z
Output Data Hold Time 10

70

−

85

−

85

−

85

−

45

−

45

−

−

−

−

35

−

35

−

35

−

−

EM564161

-85 -70

Min Max Min Max

−

−

−

−

−

10

3
5

−

−

−

10

−

70
70
70
35
35

−

−

−

25
25
25

−

ns

Unit

t

WC

t

WP

t

CW

t

BW

t

AS

t

WR

t

WHZ
t

OW

t

DS

t

DH

Write cycle time 85
Write pulse width 55
Chip Enable to end of write 70
Data Byte Control to end of Write 70
Address setup time 0
Write Recovery time 0
WE# Low to Output in High-Z
WE# High to Output in Low-Z 5
Data Setup Time 35
Data Hold Time 0

AC Test Condition

• Output load : 50pF + one TTL gate

• Input pulse level : 0.4V, 2.4V

• Timing measurements : 0.5 x V

• tR, tF : 5ns

DD

Preliminary

−

−

−

−

−

−

35

−

−

−

−

5 Rev 2.6

70

−

55

−

60

−

60

−

0

−

0

−

30

−

5

−

30

−

0

−

October 2000

ns

EtronTech

Read Cycle
(See Note 1)

Address

t

EM564161

RC

CE1#

CE2

OE#

t

HZ

t

OH

t

AA

t

CO1

t

CO2

t

OE

UB# LB#

,

D

OUT

Preliminary

t

OHZ

t

BA

t

BLZ

t

OLZ

t

LZ

VALID DATA OUT

6 Rev 2.6

t

BHZ

October 2000

EtronTech

Write Cycle1
(WE# Controlled)(See Note 4)

Address

t

EM564161

WC

WE#

CE1#

CE2

UB# LB#

,

t

AS

t

WHZ

t

CW

t

CW

t

BW

t

WP

t

W R

t

OW

D

OUT

D

IN

Preliminary

(See Note2) (See Note3)

(See Note 5)

t

DS

VALID DATA IN (See Note 5)

7 Rev 2.6

t

DH

October 2000

EtronTech

Write Cycle 2
(CE1# Controlled)(See Note 4)

Addres s

t

EM564161

WC

WE#

CE1#

CE2

UB# LB#

,

t

AS

BLZ

t

WHZ

t

t

CW

t

CW

t

BW

t

WP

t

WR

D

OUT

D

IN

Preliminary

t

LZ

t

DS

(See Note 5) VALID DATA IN

8 Rev 2.6

t

DH

October 2000

EtronTech

Write Cycle 3
(CE2 Controlled)(See Note 4)

Addres s

t

EM564161

WC

WE#

CE1#

CE2

D

OUT

t

AS

t

WHZ

t

LZ

t

CW

t

CW

t

WP

t

WR

t

DS

t

DH

D

IN

Preliminary

(See Note 5) VALID DATA IN

9 Rev 2.6

October 2000

EtronTech

Write Cycle4
(UB#, LB# Controlled)(See Note 4)

Addres s

t

EM564161

WC

WE#

CE1#

CE2

UB# LB#

,

t

AS

BLZ

t

WHZ

t

t

CW

t

CW

t

BW

t

WP

t

WR

D

OUT

t

LZ

t

DS

D

IN

(See Note 5) VALID DATA IN

t

DH

Note:

1. WE# remains HIGH for the read cycle.

2. If CE1# goes LOW (or CE2 goes HIGH) with or after WE# goes LOW, the outputs will remain at high
impedance.

3. If CE1# goes HIGH (or CE2 goes LOW) coincident with or before WE# goes HIGH, the outputs will remain
at high impedance.

4. If OE# is HIGH during the write cycle, the outputs will remain at high impedance.

5. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be
applied.

Preliminary

10 Rev 2.6

October 2000

EtronTech

EM564161

Data Retention Characteristics (Ta = -40°C to 85°C)

Symbol Parameter Min Typ Max Unit

V

Data Retention Supply

DR

Voltage

CE1# ≥ V
VIN ≥ V
VDD = 1.0V, CE1# ≥ V

I

Data Retention Current

DR

CE2 ≤ 0.2V, VIN ≥ V
VIN ≤ 0.2V

t

SDR

t

RDR

Chip Deselect to Data Retention Mode Time 0
Recovery Time t

CE1# Controlled Data Retention Mode

t

SDR

V

DD

2.7V

2.2V
V

DR

CE1#

- 0.2V, CE2 ≤ 0.2V,

DD

- 0.2V or VIN ≤ 0.2V

DD

DD

DD

Data Reten tion Mode

Note 1

- 0.2V,

- 0.2V or

1.0

t

RDR

−

RC

3.6 V

−

0.5 3.5

− −

− −

µA

ns
ns

GND

CE2 Controlled Data Retention Mode

V

D D

2.7 V

CE2

V

D R

0.4V

GND

t

S DR

Note:

1. CE1# ≥ VDD – 0.2V or UB# = LB# ≥ VDD – 0.2V

2. CE2 ≤ 0.2V

D ata R eten tion Mode

Note 2

t

RDR

Preliminary

11 Rev 2.6

October 2000

EtronTech

Package Diagrams
48-Ball (6mm x 8mm) BGA

Units in mm

EM564161

TOP VIEW

PIN 1 CORNER

1 2 3 4 5 6

BOTTOM VIEW

0.10SS C

0.25

0.30 0.05(48X)

6 5 4 3 2 1

PIN 1 CORNER

C A B

- C - SEATING PLANE

- B -

0.75

3.75

- A -

0.20(4X)

0.10

Preliminary

12 Rev 2.6

October 2000

EtronTech

Package Diagrams
48-Ball (8mm x 10mm) BGA

Units in mm

EM564161

PIN 1 CORNER

A

B

C
D

E

F

G

H

TOP VI EW

1 2 3 4 5 6

0.1
.0

10

BOTT OM VIEW

0.10SS C

0.25

0.30 0.0 5(48X)

6 5 4 3 2 1

5
2

5.

5
7

0.

PIN 1 CO RNER

C A B

A

B

C
D

E

F

G

H

02

0.
2

0.5

X
MA
20

1.

- C -

SEATING PL ANE

- B -

0.75

- A -

05

0.
5

0.2

5

2

0

0

0.

0.
6

3

0.

0.20(4X)

D

D

0.10

3.75

8.0 0.10

Preliminary

13 Rev 2.6

October 2000