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DM9102
10/100 Mbps Si ngle Chi p LAN Controller
Final 1
Version: DM9102-DS-F03
August 30,2000
T
General Description
The DAVICOM’s DM9102 is a hig hly integrated singlechip Fa s t Et he rn et co n tr ol ler . It f ully integrated 100BASETX/10Base-T Fast Ethernet MAC, PHY and PMD. It is
fully compliant with PCI Spec. 2.1 and IEEE802.3u.
The DM9102 provides a direct interface to the PCI local
bus and direct connection to the network wire. A s a
controller, it provides the bus master capability. The
DM9102 also supports auto-negotiation function that
enables it to detect speed and duplex automatically. Due
to the well-controlled rising/falling time, it requires no
external filter to transmit signal to the media.
T
Block Diagram
DMA
EEPROM
Interface
Boot ROM
Interface
PCI
Interface
TX+/-
RX+/-
MII Management Control
& MII Register
Autonegotiation
LED Driver
RX
MachineRXFIFO
TX
FIFO
TX
Machine
MAC
MII
NRZ to NRZINRZI to MLT3
Parallel to
Serial
Scrambler
4B/5B
Encoding
MLT3 to NRZI NRZI to NRZ
Parallel to
Serial
De-
Scrambler
4B/5B
Decoding
AEQ
PHYceiver
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DM9102
10/100Mbps S ingl e Chip L AN Controller
2 Final
Version: DM9102-DS-F03
August 30, 2000
Table of Contents
General Descri pti on................................................1
Block Diagram........................................................1
Features................................................................. 4
Pin Configuration: DM9102 QFP.............................5
Pin Description.......................................................6
- PCI Bus Interface................................................6
- Boot ROM and EEPROM Interface ......................7
Multiplex M ode ...................................................7
Direct M o d e.........................................................8
- LED Pins.............................................................9
- Network Interface..............................................10
- Clock Pins.........................................................10
- Miscellaneous Pins............................................10
- Power Pins........................................................11
Register Definition................................................12
✧ PCI Configuration Registers..............................12
Key to Default.......................................................13
Identifi c ation ID..................................................14
Command & Status............................................14
Command Register Definition ............................16
Revisio n ID........................................................17
Miscellaneous Function .....................................17
I/O Bas e Ad d r e ss...............................................18
Memory Mapped Base Address .........................18
Subsystem Identification....................................19
Expansion ROM Base Address..........................19
Capabilities Pointer............................................20
Interrupt & Latency Configuration.......................20
Device Speci fic Con figur ation R egis ter ..............20
✧ Control and Status Register (CR)......................22
Key to Default.......................................................22
1. System Control Register (CR0) .........................23
2. Transmit Descriptor Poll Demand (CR1)............24
3. Receive Descript or Poll Demand (CR2) ............24
4. Receive Descriptor Base Address (CR3)........... 24
5. Transmit Descriptor Base Address (CR4).......... 25
6. Network Status Report Register (CR5).............. 25
7. Network Operation Register (CR6)....................27
8. Interrupt Mask Register (CR7)...........................29
9. Statistical Counter Register (CR8).....................30
10. PROM & Management Access Register (CR9)31
11. Programming ROM Address Register (CR10) .32
12. General Purpose Timer Register (CR11).........32
13. PHY Status Register (CR12)...........................32
14. Frame Access Register...................................33
15. Frame Data Register (CR14)..........................33
16. Watching & Jabber Timer Register (CR15) .....33
✧ PHY Management Register Set........................34
Key To Default .....................................................34
Basic Mode Control Register (BMCR)
- Register 0 ..........................................................35
Basic Mode Status Register (BMSR)
- Register 1 ..........................................................36
PHY ID Identifier Register #1 (PHYIDR1)
- Register 2 ..........................................................37
PHY ID Identifier Register #2 (PHYIDR2)
- Register 3 ..........................................................37
Auto-negotiation Advertisement Register (ANAR)
- Register 4 ..........................................................37
Auto-negotiation Link Partner Ability Register
(ANLPAR) - Register 5.........................................38
Auto-negotiation Expansion Register (ANER)
- Register 6 ..........................................................39
DAVICOM Specified Configuration Register (DSCR)
- Register 16.........................................................39
DAVICOM Specified Configuration and Status
Register (DSCSR) - Register 17 ...........................40
10Base-T Configuration/Status (10BTSCRCSR)
- Register 18.........................................................41
Functional Descr i pti on..........................................42
✧ System Buffer Management..............................42
1. Overview..........................................................42
2. Data Structure and Descriptor List ....................42
3. Buffer Managemen t: Ring Stru cture Method .....42
4. Buffer Managemen t: Chain Structure Method ...43
5. Descriptor List: Buffer Descriptor Format..........43
(a). Receive Descriptor Format .............................43
(b). Transmit Descriptor Format ............................45
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DM9102
10/100 Mbps Si ngle Chi p LAN Controller
Final 3
Version: DM9102-DS-F03
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Initialization Procedure..........................................48
Data Buffer Proc ess in g Algor ithm..........................48
1. Receive Data Buffer Processing........................48
2. Transmit Data Buffer Processing.......................49
✧ Network Function ..............................................50
1. Overview...........................................................50
2. Receive Process and State Machine .................50
3. Transmit Pr oc ess and State Machine ................50
4. Physical Layer Overview ...................................50
✧ Serial Management Interface.............................51
Configu r ation R OM Overview................................52
1. Subsystem ID Block..........................................52
2. CROM Version..................................................53
3. Controller Count................................................53
4. Controller_X Information ...................................53
5. Controller Information Body Pointed By
Controll er_X Info Block Offset Item in Controller
Information Header ............................................53
Abso lu te Maximum Ratings...................................55
DC Electrical Characteristics.................................55
AC Electrical Char ac teristics & Timing Waveforms56
PCI Clock Spec. Timing.....................................56
Other PCI Signals Timing Diagram ....................56
Multiplex M ode Boot ROM Timing......................57
Direct Mode Boot ROM Timing ..........................57
EEPROM Timing...............................................58
PHYceiver.........................................................58
Auto-negotiation and Fast Link Pulse Timing
Diagram ............................................................59
Package Information.............................................60
Ordering Information.............................................61
Disclaimer ............................................................61
Company Overview ..............................................61
Products...............................................................61
Contact Windows..................................................61
Warning................................................................61
Appendix A...........................................................62
DM9102 SROM Format..................................... 62
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10/100Mbps S ingl e Chip L AN Controller
4 Final
Version: DM9102-DS-F03
August 30, 2000
T
Features
T
Single chip LAN controller integrated Fast Ethernet MAC,
PHY and transceiver
T
Compliant w ith IEEE 80 2.3u 100BASE-T X, IEEE 802.3
10BASE-T and ANSI X3T12 TP-PMD s tandard
T
Direct in te rface to th e PCI b us & fu ll y c om plia nt wit h PCI
specification 2.1
T
PCI bus master architecture
T
Support PCI bus burst mode data transfer with
programmable burst size
T
EEPROM 93C46 interface to s tore con figuration
information and user defined message
T
Support up to 256K bytes Boot ROM interface
T
Two large independent receive FIFO (4K) & transmit
FIFO (2K) with programmable FIFO threshold and full
packet burst processing
T
Support automatic packet deletion for runt packets and
packet re-transmission with no FIFO reload
T
Support Full/H alf Duplex operation
T
Physical, broadcast address recognition and 512-bit hash
table algorithm for multicast addres s filtering
T
Compliant with IEEE802.3u Auto-negotiation protocol for
automatic link type selection
T
High performance 100Mbps clock generator and data
recovery circuit
T
Dig ita l clo c k r ec o ver y c irc u it us in g adva nc e d digi t al
algorithm to reduce jitter
T
Adaptive equalization circuit and Baseline wandering
restoration circuit for 100Mbps receiver
T
Provides Loopback mode for easy system diagnostics
T
128 pin QFP with CMOS process
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DM9102
10/100 Mbps Si ngle Chi p LAN Controller
Final 5
Version: DM9102-DS-F3
August 30, 2000
T
Pin Configuration
11
DM9102
807978777675747372717069686766
65
64
63
62
60
59
58
57
56
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
90
91
92
93
94
95
96
97
98
99
100
123456789
10121314151617181920212223242526282930
55
54
53
52
51
61
81
82
83
84
85
86
87
88
89
INT#
RST#
DVDD
GNT#
REQ#
PCLK
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
CBE3#
DGND
NC
IDSEL
AD23
AD21
AD20
AD19
AD18
AD17
AD16
CBE2#
AD22
DVDD
DGND
FRAME#
STOP#
IRDY#
TRDY#
DEVSEL#
PERR#
SERR#
CBE0#
BGGND
BGRES
OSCVDD
X1/OSC
X2
OSCGND
LEDTRF
LEDFDX
LED100M
DGND
LED10M
BPA0
BPA1/TEST
EEDI
EEDO
EECK
EECS
SELROM
TEST0
TEST1
TEST2
BPAD4
BPAD5
BPAD6
BPAD7
BPCS#
BPAD0
BPAD1
BPAD2
BPAD3
AD0
AD1
AD2
AD6
AD7
DVDD
AD5
AD3
DGND
AD4
AD9
AD10
DGND
AD11
DVDD
AD13
AD14
AD15
AD12
AD8
CBE1#
PAR
(MA10/LEDTRF)
(MA11/LEDFDX)
(MA12/LED100M)
(MA13LED10M)
(MD0/EEDI)
(MD1)
(MD2)
(MD3)
(MD4)
(MD5)
(MD6)
(MD7)
(ROMCS)
(MA0)
(MA1)
(MA2)
(MA3/EEDO)
(MA4/EECK)
(MA5)
(MA6/SELROM)
(MA7)
(MA8)
(MA9)
DVDD
DGND
DGND
DVDD
DGND
DVDD
DVDD
DGND
DGND
DVDD
27
DVDD
DVDD
DGND
DVDD
DGND
DGND
DVDD
DGND
DGND
DVDD
MA16
102
101
MA15
MA14
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
127
128
126
DGND
DVDD
PWRIN
RAVDD
RXI-
RXI+
RAGND
TAGND
TXO-
TXO+
TAVDD
TAGND
TAGND
TAGND
TAVDD
NC
NCNCNC
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10/100Mbps S ingl e Chip L AN Controller
6 Final
Version: DM9102-DS-F03
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T
Pin Description
I = Input, O = Output, I/O = Input/Output, O/D = Open Drain, P = Power
LI = r eset Latch I nput, # = all pi n name wi th # are asserted Low
PCI Bus Interface
Pin No. Pin Name I/O Description
1 PCLK I PCI system clo ck
PCI bus clock that provides timing for DM9102 related to
PCI bus transactions. The clock frequency range is up to
33MHz.
4 GNT# I Bus Grant
This signal is asserted low to indicate that DM9102 has
been granted ownership of the bus by the central arbi ter.
5 REQ# O Bus Request
The DM9102 will assert this signal low to request the
ownership of the bus.
6 NC No Connection
20 IDSEL I Initialization Device Select
This signal is asserted high during Configuration Space
read and write access.
34 FRAME# I/O Cycle Frame
This signal is driven low by the DM9102 master mode to
indicate the beginning and duration of a bus transaction.
37 IRDY# I/O Initiator Ready
This signal is driven low when the master is ready to
complete the current data phase of the transaction. A data
phase is completed on any clock both IRDY# and TRDY#
are sampled asserted.
38 TRDY# I/O Target Ready
This signal is driven low when the target is ready to
complete the current data phase of the transaction. During
a read, it indicates that valid data is asserted. During a
write, it indicates the target is prepared to accept data .
40 DEVSEL# I/O Device Select
The DM9102 asserts the signal low when it recognizes its
target address after FRAME# is asserted. As a bus
master, the DM9102 will sample this signal to insure that
the destination address for the data tran sfer is recognized
by a target.
41 STOP# I/O Stop
This signal is asserted low by the target device to request
the master device to stop the current transaction.
42 PERR# I/O Parity Error
The DM9102 as a master or slave will ass ert this signal
low to indicate a parity error on any incoming data.
43 SERR# I/O System Error
This signal is asserted low when an address parity is
detected wi th PCICS bit31 (detected parity error) Is
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10/100 Mbps Si ngle Chi p LAN Controller
Final 7
Version: DM9102-DS-F3
August 30, 2000
enabled. The system error asserts two clock cycles after
the falling address if an address parity error is detected.
44 PAR I/O Parity
This signal indicates even parity across AD0~AD31 and
C/BE0#~C/BE3# including the PAR pin. This signal is an
output for the master and an input for the slave device. It is
s ta b l e and va l id one cl o c k aft e r the addres s phase.
19
33
45
60
C/BE3#
C/BE2#
C/BE1#
C/BE0#
I/O Bus Command/Byte Enable
During the address phase, these signals de fine the bus
command or the type of bus transaction that will take
place. During the data phase these pins indicate which
byte lanes contain valid data. C/BE0# applies to bit7-0 and
C/BE3# applies to bit31-24.
9~12, 14~17,
22~25,27~30,47,48,
49,52,53,56,57,58,62,
63,64,67,68,71,72,73
AD31~AD0 I/O Address & Data
These are multiplexed address and data bus signals. As a
bus master, the DM9102 will drive address during the first
bus phase. During subsequent phases, the DM9102 will
either read or write data expecting the target to increment
its address pointer. As a target, the DM9102 will decode
each address on the bus and respond if it is the tar get
being addressed.
127 INT# O/D Interrupt Request
This signal will be asserted low when an interrupt condition
as defined in CR5 is set, and the corresponding mask bit
in CR 7 is n ot s et .
128 RST# I System Reset
When this signal is asserted low, DM9102 performs the
internal system reset to its initial state.
Boot ROM and EEPROM Interface (Including Multip lex Mode or Direct Mode):
Multiplex Mode :
Pin No. Pin Name I/O Description
75~82 BPAD0~BPAD7 I/O Boot ROM Address and Data bus
Boot ROM address and Data multiplexed lines bits
0~7. In two consecutive address cycles, these lines
contain the boot RO M address pins 7~2, out_enable
and write_enable of boot ROM in the first cycle; and
these lines contain address pins 15~8 in second cycle.
After the first two cycles, these lines contain data bit
7~0 in consective cycles.
83 BPCS# O Boot ROM Chip Select
Boot ROM or external register chip select signal.
85 BPA0 O,LI Boot ROM address line.
Low address bit0 interfacing to Boot ROM.
86 BPA1/TEST O Boot ROM address line.
Low address bit1 interfacing to Boot ROM.
This bit is also set to enable TEST mode only in
multiplex mode. (debug only)
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10/100Mbps S ingl e Chip L AN Controller
8 Final
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August 30, 2000
87 EEDI I,LI EEPROM Data In
The DM9102 will read the contents of EEPROM serially
through this pin.
88 EEDO O EEPROM Data Out
The DM9102 will use this pin to s erially write op codes,
addresses and data into the EEPROM.
89 EECK O EEPROM Serial Clock
This p in p r ovid e s th e cl oc k for the EEPR OM d ata tra n sfe r.
90 EECS O EEPROM Chip Select
This pin will enable the EEPROM during loading of the
Configuration Data.
92 TEST0 I TEST option cont r ol
This pin are valid only test mode enabled.
In normal operation when in multiplex mode, this pin
are pulled low.
93,94 TEST1,TEST 2 I TEST option control
These two pins are valid only test mode is enabled.
In normal operation when in multiplex mode, these two
pins are pulled low.
99~101 NC In Multiplex mode, these three pins are not connected.
Direct Mode
Pin No. Pin Name I/O Description
75 MD0/EEDI I Boot ROM Data Input/EEDI Data In
This pin is multiplexed by EEDI and MD0.
The DM9102 will read the contents of EEPROM serially
through this pin.
76~82 MD1~MD7 I
Boot ROM Data Input Bus
83 ROMCS O Boot ROM or EEPROM ch ip se lection.
85~87 MA0~MA2 O Boot ROM Address Output Bus
88 MA3/EEDO O Boot ROM Address Output/ E EPRO M Data Out
This pin is multiplexed with MA3 and EEDO.
The DM9102 will use this pin to s erially write op codes,
addresses and data into the EEPROM.
89 MA4/EECK O Boot ROM Address Output/EEPROM Serial Clock
This pin is multiplexed with MA4 and EECK.
This p in p r ovid e s th e cl oc k for the EEPR OM d ata tra n sfe r.
90 MA5 O Boot ROM Address Output Bus
91 MA6/SELROM O/LI Boot ROM Address Output Bus/M ultiplex or Direct
mode selection
It is al so used as multipl ex or d irec t mode selection
at power-up reset. 0 = multiplex mode, 1 = direct
mode.
92~94 MA7~MA9 O Boot ROM Address Output Bus
95~98 M A 10/LEDTRF O Boot ROM Address Output Bus/A c tive LED
When at the time of Boot ROM operation, the LED
maybe flash f ew seconds. LE D Active Low.
When operates as LED pin, if Bi t5 of PHY
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10/100 Mbps Si ngle Chi p LAN Controller
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Version: DM9102-DS-F3
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management regist er 16 i s 0, it is the Activit y LED
and will flash when in transmitting or receiving.
If Bit5 of PHY Management register16 is 1, this pin is
no use
96 MA11/LEDFDX O Boot ROM Address Output/Full-Duplex LED
Indicates Full Duplex mode operation. Active low.
When at the time of Boot ROM operation, the LED
maybe flash few seconds.
97 MA12/LED100M O Boot ROM Address Output/ 100M bps LED
When at the time of Boot ROM operation, the LED
maybe flash f ew seconds. LE D Active Low.
When operates as LED pin, if Bi t5 of PHY
management regist er 16 i s 0, it indicates good link to
100Mbps (defaul t). If Bit5 of PHY management
register16 is 1, it is link and activity LED.
98 MA13/LED10M O Boot ROM Address Output B us/10M bps LED
When at the time of Boot ROM operation, the LED
maybe flash f ew seconds. LE D Active Low.
When operates as LED pin, if Bi t5 of PHY
management regist er 16 i s 0, it indicates good link to
10Mbps (defaul t). If Bit5 of PHY management
register16 is 1, it is link and activity LED.
99~101 MA14~MA 16 O Boot ROM Address Output Bus
LED Pins
Pin No. Pin Name I/O Description
95 LEDTRF O Active LED, Active Low
If Bit5 of PHY management register16 is 0, it is the
Activity LED and will flash when in transmitting or
receiving. (default)
If Bit5 of PHY Management register16 is 1, this pin is
no use.
96 LEDFDX O Full-Duplex LED, Active Low
Indicates Full-Duplex mode operation.
97 LE D100M O 100Mbps LED, Act ive Low
Indicates 100Mbps mode operation.
If Bit5 of PHY management register16 is 0, it indicates
good link to 100Mbps. (default)
If Bit5 of PHY management register16 is 1, it is link
and activity LED.
98 LED10M O 10Mbps LED, A c tive Low.
Indicates 10Mbps mode operation.
If Bit5 of PHY management register16 is 0, it indicates
good link to 10Mbps. (default)
If Bit5 of PHY management register16 is 1, it is link
and activity LED.
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10/100Mbps S ingl e Chip L AN Controller
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Network Interface
Pin No. Pin Name I/O Description
107
108
RXIRX+
I 100M/10Mbps Differenti al Input Pair.
These two pins are differential receive input pair for
100BASE-TX and 10BASE-T. They are capable of
receiving 100BASE-TX MLT-3 or 10BASE-T
Manchester encoded data.
112
113
TXO-
TXO+
O 100M/10Mbps Diff er ential Output Pair.
These two pins are differential output pair for
100BASE-TX and 10BASE-T. This output pair
pr ovides controlled rise and fall times designed to
filter the tr ansmitter output.
Clock Pins
Pin No. Pin Name I/O Description
118 OSCVDD P Analog Power
119 X1/OSC I
Crystal or Oscillator Input. (25MHZ50ppm)
120 X2 O Crystal feedback output pin used for crystal
connection only. Leave this pin open if oscillator is
used.
121 OSCGND P Analog Ground
Miscellaneous Pins
Pin No. Pin Name I/O Description
91 SELROM LI Multiplex mode/Direct mode Selection.
This pin is “reset latch input at power up” to select
Multiplex mode or direct mode.
“0” = multiplex mode (default),
“1” = direct mode. At direct mode, this is also a output
pin which is used by MA6.
102 NC O No Connection
104 BGRES I Band-gap Voltage Reference Resistor.
It connects to a 6200, 1% error toleranc e resistor
between this pin and BGGND pin (pin 105) to p rovide
an accurate current reference for DM9102.
105 BGGND I Ground for Band-gap circuit
122 PWRIN I VDD clamp
This pin is used to identify the D3(cold) power state in
a power management aware system. This pin should
be connected to the PCI power, while other DVDD
pins should be connected to the auxiliary power, if
any. In non-power management aware systems, or
ther e is n o auxiliary power, the DVDD pins and the
PWRIN pins should be connected to the PCI power
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10/100 Mbps Si ngle Chi p LAN Controller
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Power Pins
Pin No. Pin Name I/O Description
106 RAVDD P Analog power for recei ve
109 RAGND P Analog ground for receive
114,115 TAVDD P Analog power for transmit
110,111,116,117 TAGND P Analog ground for transmit
7,8,13,26,35,36,39,54
,55,59,69,70,74,103,
125,126
DGND P Digital ground pins
2,3,18,21,31,32,46,50
,51,61,65,66,84,123,
124
DVDD P Digital power pins
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DM9102
10/100Mbps S ingl e Chip L AN Controller
12 Final
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T
Register Definition
a
PCI Configuration Registers
The definitions of PC I Configuration Registers are
based on the PCI specification revision 2.1 and
provides the initialization and configuration
information to operate the PCI interface in the
DM9102. All registers can be accessed with byte,
word, or double word mode. As defined in PCI
spec ifica tion 2.1, read acc esses to reserve or
unimplemented registers will return a value of “0.”
These registers are to be described in the following
sections.
PCI Configuration Registers Mapp ing :
Description Identifier Address Offset Value of Reset
Identification PCIID 00H 91021282H
Command & Status PCICS 04H 02900007H
Revision PCIRV 08H 02000020H
Miscellaneous PCILT 0CH 00000000H
I/O Base Address PCIIO 10H undefined
Memory Base Address PCIMEM 14H undefined
Reser ved -------- 18H - 28H
Subsystem Identification PCISID 2CH load from SROM
Expansion ROM Base Address PCIROM 30H 00000000H
Capability Pointer CAP_PTR 34H 00000050H
Reser ved -------- 38H
Interrupt & Latency PCIINT 3CH 281401XXH
Device Specific Configuration Register PCIUSR 40H 00000000H
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Vendor IDDevice ID
Status (with bit 4 set to 1) Command
Revision
Latency Timer Cach Line Size
Class Code = 020000h
Header TypeBIST
Bass Address Register CBIO
Bass Address Register CBMA
00H
04H
08H
0CH
10H
14H
18H
1CH
20H
24H
28H
2CH
30H
34H
38H
3CH
Reserved
Subsystem Vendor IDSubsystem ID
Expansion ROM Base Address
Reserved
Reserved
Cap_Ptr
Max_Lat Min_Gnt Interrupt Pin = 1 Interrupt Line
Configuration Register Structure
40H
44H
48H
4CH
Reserved
Device Specific Configuration Register
Key to Default
In the register description that follows, the default
column takes the form <Reset Value>
Where
<Reset Value>:
1 Bit set to logic one
0 Bit set to logic zero
X No default value
<Access Type>:
RO = Read onl y
RW = Read/Write
R/C : means Read / Write & Write "1" for Clear.
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Identification ID (xxxxxx00 - PCIID)
31 16 15 0
Dev_ID
Vend_ID
Device ID
Vendor ID
Bit Default Type Description
16:31 9102h RO The field identifies the particular device. Unique and fixed number for the
DM9102 is 9102h. It is t he product number assigned by DAVICOM.
0:15 1282h RO This field identifies the manuf acturer of the device. Unique and fixed
number for Davicom is 1282h. It is a registered number from SIG.
Command & Status (xxxxxx04 - PCICS)
31 16 15 0
Status Command
Status
Command
Status Register Definition:
31 30 29 28 27
26 25
24 23 22 21 20 16
0 0 1 1
0
0191
Detected Parity Error
Signal For System Error
Master Abort Detected
Target Abort Detected
DEVSEL Timing
Data Parity Error Detected
Slave mode Fast back to Back
New Capability
66MHz Capability
User Definable
Send Target Abort
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Version: DM9102-DS-F3
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Bit Default Type Description
31 0b R/C Detected Parity Error
The DM9102 samples the AD[0:31], C/BE[0:3]#, and the PAR
signal to check parity and to set parity errors. In slave mode,
the parity check falls on command phase and data valid phase
(IRDY# and TR D Y# both active). While in master mode, the
DM9102 will check during each data phase of a memory read
cycle for a parity error During a memory write cycle, if an error
occurs, the PERR# signal will be driven by the target. This bit
is set by the DM9102 and cleared by writing "1". There is no
effect by writing "0".
30 0b R/C Signal For System Error
This bit is set when the SERR# signal is driv en by the DM9102.
This system error occurs when an address parity is detected
under the condition that bit 8 and bit 6 in command register
below are set.
29 0b R/C Master Abort Detected
This bit is set when the DM9102 terminates a master cycle with
the master-abort bus transaction.
28 0b R/C Target Abort Detected
This bit is set when the DM9102 terminates a master cycle due
to a target-abort signal from other targets.
27 0b R/C Send Target Abort (0 For No Implementation)
The DM9102 will never assert the target-abort sequence.
26:2 5 01b R/C DEVSEL Timing (01 Select Medium Timing)
Medium timing of DEVSEL# means the DM9102 will assert
DEVSEL# signal two clocks after FRAME# is sample
“asserted.”
24 0b R/C Data Parity Error Detected
This bit will take effect only when operating as a master and
when a Parity Error Response Bit in command configuration
register is set. It is set under two conditions:
(i) PERR# asserted by the DM9102 in memory data read error,
(ii) PERR# sent from the target due to memory data write error.
23 1b R/C Slave mode Fast Back-To-Back Capable (1 For Good
Capability)
This bit is always reads "1" to indicate that the DM9102 is
capable of accepting fast back-to-back transaction as a slave
mode device.
22 0b R/C User-Definable-Feature Supported (0 For No Support)
21 0b R/C 66 MHz Capable (0 For No Capability)
20 1b R/C New Capabilities
This bit indicates whether this function implements a list of extended
capabilities such as PCI power management. When set this bit
indicates the presence of New Capabilities. A value of 0 means that
this function does not implement New Capabilities.
19:16 0000b RO Reserved
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Command Register Definition:
15 109876543210
Reserved R/W
0
R/W
00
R/W
R/W R/W0
0
Parity Error Response Enable/Disable
I/O Space Access Enable/Disable
Memory Space Access Enable/Disable
Master Device Capability Enable/Disable
SERR# Driver Enable/Disable
Mast Mode Fast Back-To-Back
Address/Data Steeping
VGA Palette snoop
Special Cycle
Memory Write and Invalid
Bit Default Type Description
15:10 000000b RO Reserved
9 0b RO Master Mode Fast Back-To-Back (0 For No Support)
The DM9102 does not support master mode fast back-to-back capability
and will not generate fast back-to-back cycles.
8 0b RW SERR# Driver Enable/Disable
This bit controls the assertion of SERR# signal output. The SE RR# output
will be asserted on detection of an address parity error and if both this bit
and bit 6 are set.
7 0b RO Address/Data Stepping (0 For No Stepping)
6 0b RW Parity Error Response Enable/Disable
Setting this bit will enable the DM9102 to assert PERR# on the detection of
a data parity error and to assert SERR# for reporting address parity error.
5 0b RO VGA Palette Snooping (0 For No Support)
4 0b RO Memory Write and Invalid (0 For No
Implementation)
The DM9102 only generates Memory write cycle.
3 0b RO Special Cycles (0 For No Implementation)
2 1b RW Master Device Capability Enable/Disable
When this bit is set, DM 9102 has the a bility of master mode operation.
1 1b RW Memory Space Access Enable/Disable
This bit controls the ability of memory space access. The memory access
includes memor y mapped I/O access and Boot ROM access. As the system
boots up, this bit will be enabled by BIO S for Boot ROM memory access.
While in normal operation using memory mapped I/O access, this bit should
be set by driver before memory access cycles.
0 1b RW I/O Space Access Enable/Disable
This bit control s t he ability of I/O space access. It will be set by BIOS after
power on.
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Revision ID (xxxxxx08 - PCIRV)
31 078
Revision IDClass Code
Class Code
Revision Major Number
Revision Minor Number
31 078
Revision IDClass Code
Class Code
Revision Major Number
Revision Minor Number
Bit Default Type Description
31:8 020000h RO Class Code (020000h)
This is the standard code for Ether net LAN controller.
7:4 0010b RO Revision Major Number
This is the silicon-major revision number that will increase for the
subsequent versions of the DM9102.
3:0 0000b RO Revision Minor Number
This is the silicon-minor revision number that will increase for the
subsequent versions of the DM9102.
Miscellan eous Function (Xxxxxx0c - PCILT)
31 16 15 0872324
BIST Header Type Latency Timer Cache Line Size
Built-In Self Test
Header Type
Latency Timer For The Bus Master
Cache Line Size For Memory Read
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Bit Default Type Description
31:24 00h RO Built-In- S elf Test (=00h Means No Implement ation)
23:16 00h RO Header Type (= 00h Means single function with Predefined Header Type )
15:8 00h RW Latenc y Timer For The Bus Master.
The latency timer is guaranteed by the system and measured by clock
cycles. When the FRAME# asserted at the beginning of a master period by
the DM9102, the value will be copied into a counter and start counting
down. If the FRAME# is de-a sser ted prior to count expira tion, this value is
meaningless. When the count expires before GNT# is de-asserted, the
master transaction will be terminated as soon as the GNT# is removed.
While GNT# signal is removed and the counter is non-ZERO, the DM9102
will continue with its data transfers until the count expires. The system host
will read MIN_GNT and MAX_LAT registers to determine the latency
requirement for the device and then initialize the latency timer with an
appropriate value.
7:0 00h RO Cache-line Size For Memory Read Mode Selection (00h Means No
Implementation For Use)
I/O Base Address (Xxxxxx10 - PCIIO)
31 0167
1
000000
I/O Base Address
I/O Base Address
PCI I/O Range Indication
I/O or Memory Space Indicator
Bit Default Type Description
31:7 Undef ined RW PCI I/O Base Address
This is the base address value for I/O access cycles. It will be compared to
AD[31:7] in the address phase of bus command cycle for the I/O resource
access.
6:1 000000b RO PCI I/O Range Indication
It indicates that the minimum I/O resource size is 80h.
0 1b RO I/O Space Or Memory Space Base Indicator
Determines that the register maps into the I/O spa ce .( =1 Indicates I/O
Base)
Memory Mapped Base Address (Xxxxxx14 - PCIMEM)
31 0167
000000
Memory Mapped
Base
0
Memory Base Address
Memory Range Indication
I/O or Memory Space Indicator
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Bit Default Type Description
31:7 Undef ined R/W PCI Mem ory Base Address
This is the base address value for Memory access cycles. It will be
compared to AD[31:7] in the address phase of bus command cycle for the
Memory resource access.
6:1 000000b RO PCI Memory Range Indication
It indicates that the m inimum Memory resource size is 80h.
0 0b RO I/O Space Or Memory Space Base Indicator
Determines that the register maps into the memory space(=0 Indicates
Memory Base)
Subsystem Identification (Xxxxxx2c - PCISID)
031
Subsystem ID Subsystem Vendor ID
Subsystem ID
Subsystem Vendor ID
Bit Default Type Description
31:16 XXXX h RO S ubsystem ID
Node number loaded from EEPROM word 1 and differen t from each card.
15:0 XXXX h RO Subsystem Vendor ID
Unique number given by PCI SIG and loaded from EEPROM word 0.
Expansion ROM Base Address (Xxxxxx30 - PCIROM)
31 01
ROM Base Address
R/W
11
10
Reserved
18 17
0000000
ROM Base Address
9
00000000
Bit Default Type Description
31:10 00h RW ROM Base Address With 256K Boundary
PCIROM bit17~10 are hardwired to 0, indicating ROM Size is up to 256K
Size
9:1
000000000b
RO Reserved Bits Read As 0
0 0b RW Expansion ROM Decoder Enable/Disable
If this bit and the memory space access bit are both set to 1, the DM9102
will responds to its expansion ROM.
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10/100Mbps S ingl e Chip L AN Controller
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Capabilities Pointer (Xxxxxx34 - Cap _Ptr)
0 0 000011
Cap_Ptr
Offset 34H
07
Bit Default Type Description
31:8 000000h RO Re served
7:0 01010000b RO C apability Pointer
The Cap_Ptr provides an offset (default is 50h) into the function’s PCI Configuration
Space for th e loca tion o f the f ir st t er m in th e Capabilitie s Linked List. The Cap_Ptr
offset is DOUBLE WORD aligned so the two least s ignificant bits significant bits are
always “0”s
Interrupt & Latency Configuration (Xxxxxx3c - PCIINT)
31 16 15 0872324
MAX_LAT MIN_GNT INT_PIN INT_LINE
Maximum Latency Timer
Minimum Grant
Interrupt Pin
Interrupt Line
Bit Default Type Description
31:24 28h RO Maximum Latency Timer that can be sustained (Read Only and Read As
28h)
23:16 14h RO Minimum Grant
Minimum Length of a Burst Period (Read Only and Read As 14h)
15:8 01h RO Interrupt Pin read as 01h to indicate INTA#
7:0 XXh RO Interr upt Line that Is Routed to the Interrupt Controller
Device Specific Configuration Register (Xxxxxx40 - PCIUSR)
31 30
29
16
15 8 0
Reserved
27 2628 725 24 23
Device Specific
Device Specific
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Version: DM9102-DS-F3
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Bit Default Type Description
31 0b RW Device Specifi c Bit (sleep mode)
30 0b RW Device Specifi c Bit (snooze mode)
29 0b RO When set enable Link Status Change Wake-up Event
28 0b RO When set enable Sample Frame Wake-up Event
27 0b RO When set enable Magic Packet Wak e- up Event
26 0b RO When set, i ndicates link change and Link Status Change Event occurred
25 0b RO When set, indicates the sample frame is received and Sampl e Frame Event
occurred
24 0b RO When set, i ndicates the Magic Packet is received and Magic packet Event
occurred
23:16 00h RO Reserved Bits Read As 0
15:8 00h RW Device Specific
7:0 00h RO Reserved Bits Read As 0
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DM9102
10/100Mbps S ingl e Chip L AN Controller
22 Final
Version: DM9102-DS-F03
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a
Control and Status Registers (CR)
The DM9102 implement 16 control and status
register, which can be a ccessed b y the host. These
CRs are double long word aligned. All CRs are set
to their default values by a hardware or a software
reset unless otherwise specified. All Control and
Status Registers with their definitions and offset
from IO or memory Base Address are shown
below:
Register Description Offset from CSR
Base Address
Default
CR0
System Control Re gister 00H FFC00000
CR1
Transmit Descriptor Poll Demand 08H FFFFFFFF
CR2
Receive Descriptor Poll Demand 10H FFFFFFFF
CR3
Receive Descriptor Base Address Register 18H 00000000
CR4
Transmit Descriptor Base Address Register 20H 00000000
CR5
Network Status Report Register 28H FC000000
CR6
Network Operation Mode Register 30H 02400040
CR7
Interrupt Mask Register 38H FFFE0000
CR8
Statistic al Count er Register 40H 00000000
CR9
External Management Access Register 48H FFF097FF
CR10
Programmi ng ROM Address Register 50H Unpredictable
CR11
General Purpose Timer Register 58H FFFE0000
CR12
PHY Status Register 60H FFFFFFXX
CR13
Access Register 68H XXXXXX00
CR14
Data Register 70H Unpredictable
CR15
Watchdog And Jabber Timer Register 78H FFFFFEC8
Key to Default
In the register description that follows, the default
column takes the form:
<Reset Value>, <Access Type>
Where
<Reset Value>:
1 Bit set to logic one
0 Bit set to logic zero
X No default value
<Access Type>:
RO = Read onl y
RW = Read/Write
WO = Write only
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10/100 Mbps Si ngle Chi p LAN Controller
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Version: DM9102-DS-F3
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1. System Control Register (CR0)
31
30
29 28 27 26
25 24 23
22
21 2019181716 151413 121110
9876543 2 1
0
0
0
00
Bit Name Default Description
21 MRM 0b,RW
Memory Read Multiple
When set, the DM9102 will use memory read multiple command (C/BE3~0 = 1100)
when it initialize the memory read burst transaction as a master device.
When reset, it will use memory read command (C/BE3 ~ 0 = 0110) for the same
master operation.
20 Reserved 0b,RW
Must be Zero
19:17 TXAP 000b,RW
Transmit Automatic polling interval time
When set, the DM9102 w ill poll the transmit descriptor automatically when it is in the
suspend state due to buff er unavailable. T he p o l ling interv al tim e is program mable
based on the table shown below:
Bit 19 Bit 18
Bit 17 Time Interval
0 0 0 No polling
0 0 1 200us
0 1 0 800us
0 1 1 1.6ms
1 0 0 12.8us
1 0 1 25.6us
1 1 0 51.2us
1 1 1 102.4us
16 Reserved 0b,RW
Must be Zero
15:14 ABA 00b,RW
Address Boundary Alignment
When set, the DM9102 will execute each burst cycles to stop at the programmed
address boundary. The address boundary can be progra m med to be 8 , 16, or 3 2
double-word as shown below.
Bit 15 Bit 14
Alignment Boundary
0 0 Reserved
0 1 8-double word
1 0 16-double word
1 1 32-double word
13:8 BL 000000b,
RW
Burst Length
When reset, the DM9102’s burst length in one DMA transfer is limited by the
amount of data in the receive FIFO ( w hen receive ) or the a mount o f free space in
the transmit FIFO (when transmit ). When set, the DMA’s burst length is limited by the
prog ra mme d va lue . Th e p er missibl e v alues are 0, 1, 2, 4, 8, 16, or 32 doublewords.
7 Reserved 0,RW
Must be Zero
6:2 DGW 00000,RW
Descriptor Gap Width
The value of this field defines the ga p width ( count in double-word ) between two
continuous descriptor. It is used in ring-type descriptor structure.
1 Reserved 0,RW
Must be Zero
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Bit Name Default Description
0SR0,RW
Software Res et
When set, the DM9102 will make a internal reset cycle. All consequent action to
DM9102 should wait at least 32 PCI clock cycles to s tart and no necessary to reset this
2. Tran smit Descri ptor Poll Demand (CR1)
31 30
29 28 27
26
25 24
23
22
21 20
19 18 17 161514 13 12 11
10
987
6
54321
0
Bit Name Default Description
31:0 TDP
FFFFFFFF h
,WO
Transmit Descriptor Polling Command
Writing any value to this port will force DM9102 to poll the transmit des criptor. If the
act ing d e scri p tor is no t a v ailabl e, t ransmit process will return to suspend state. If t he
descriptor shows buffer available, transmit process will b e gin th e d at a tr ansfer.
3. Receive Descripto r Poll Demand (CR2)
31 30
29 28 27
26
25 24
23
22
21 20
19 18 17 161514 13 12 11
10
987
6
54321
0
Bit Name Default Description
31:0 RDP FFFFFFFFH
,WO
Receive Descriptor Polling Command
Writing any value to this port will force DM9102 to poll the receive descriptor. If the
act ing d e scri p tor is no t a v ailabl e, r ec eiv e process will r eturn to suspend state. If the
descriptor shows buffer available, receive process will begin the data transfer.
4. Receive Descriptor Base Address (CR3)
31
30
29 28 27
26
25 24 23
22 21 20
191817
16
15
14
13 12
11
10
987654321
0
00
Bit Name Default Description
31:0 RDBA 00000000h
,RW
Receive Descriptor Base Address
This register defines base address of receive descriptor-chain ( or descriptor-ring )
and must be double-word aligned. The receive descriptor- polling command after
CR3 is set will make DM9102 to fetch the descriptor at the Base-Address. In Ringtype structure, the descriptor pointer will go back to the Base-Address after Enddesc riptor o f ring . Bi t1 ,0 mus t be “00” for double word alignment.
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Version: DM9102-DS-F3
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5. Transmit Descriptor Base Address (CR4)
31 30
29 28 27
26
25 24
23
22
21 20
19 18 17 161514 13 12 11
10
987
6
54321
0
00
Bit Name Default Description
31:0 TDBA 00000000h
,RW
Transmit Descriptor Base Address
This register defines base address of transmit descriptor-chain ( or descriptor-ring )
and must be double-word aligned. The transmit descriptor- polling command after
CR4 is set will make DM9102 to fetch the descriptor at the Base-Address.
In Ring-type structure, the descriptor pointer will go back to the Base-Address after
End-descriptor of ring. Bit1,0 must be “00” for double word alignment.
6. Network Status Report Register (CR5)
31
30
29 28 27 26
25 24 23
22
21 2019181716 151413 121110
9876543 2 1
0
Bit Name Default Description
25:23 SBEB 000,RO
System Bus E rror B its
These bits are read only and used to indicate the type of system bus fetal error. Valid
only when System Bus Error is set. The mapping bits are shown belo w.
Bit25 Bit24
Bit23 Bus Error Type
0 0 0 Parity error
0 0 1 Master abort
0 1 0 Slave abort
0 1 1 Reserved
1 X X Reserved
22:20 TXPS 000,RO
Transmit Process State
These bits are read only and used to indicate the state of transmit process.
The mapping table is shown belo w.
Bit22 Bit21
Bit20 Process State
0 0 0 Transmit process stopped
0 0 1 Fetch transmit descriptor
0 1 0 Move Setup Frame from the host memory
0 1 1 Move data from host memory to transmit FIFO
1 0 0 Close descriptor b y clearing owner bit of descript or
1 0 1 Waiting end of transmi t
1 1 0 Transmit end and Close descriptor by writing status
1 1 1 Transmit process suspend
19:17 RXPS 000b,RO
Receive Process State
These bits are read only and used to indicate the state of receive process.
The mapping table is shown belo w.
Bit19 Bit18
Bit17 Process State
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0 0 0 Receive process stopped
0 0 1 Fetch receive descriptor
0 1 0 Waiting for receive packet under buffer availabl e
0 1 1 Move data from receive FIFO to host memor y
1 0 0 Close descriptor by clearing owner bit of descripto r
1 0 1 Close descriptor by writing status
1 1 0 Receive proc ess suspended due to buffer u navailable
1 1 1 Purg e the curr ent f rame from the receive FIFO
bec ause of unava ilable r eceive buffer
16 NIS 0b,RW
Normal Interru pt Su mmary
Normal interrupt includes any of the th ree con ditions :
CR5<0> – TXCI : Transmit Complete Interrupt
CR5<2> – TXD U : Tran sm it Bu ffe r Un a vai lable
CR5<6> – RXCI : Rece ive Complete Interrupt
15 AIS 0b,RW
Abnormal Interrupt Summary
Abnormal interrupt includes any interrupt condition as shown below excluding Normal
Interrupt conditions. They are TXPS(bit1), TXJT(bit3), TXFU(bit5), RXDU(bit7),
RXPS(bit8), RX WT(bit9), TXER(b it10), GPT( bit11), SBE(bit13 ).
13 SBE 0b,RW
System Bus E rror
The PCI system bus errors w ill set this bit. The type of s ystem bus error is shown in
CR5<25:23> .
11 GPT 0b,RW
General-purpose Timer Expired
This bit is set to indicate the gener al-purpose timer (described in CR11) has expired.
10 TXER 0b,RW
Transmit Earl y Interrup t
Transmit Early Interrupt is set when the full packet data has been moved from host
memory into transmit FIFO. It will inform the host to process next s tep before the
trans miss ion end. Tra n smi t complete eve n t CR5<0> wi ll cle ar this bit autom a tically.
9 RXWT 0b,RW
Receive Watchdog Timer Expired
This bit is set to indicate receive watchdog timer has expired.
8 RXPS 0b,RW
Receive Process Stopped
This bit is set to indicate receive process enters the stopped state.
7 RXDU 0b,RW
Receive Buffer Unavailable
This bit is set when the DM9102 fetches the next receive descriptor is still owned by
the h o st. R ece iv e pr oc e ss will be suspended until a new frame enters or th e receive
polling command is set.
6 RXCI 0b,RW
Recei ve C o mplete In te rru pt
This bit is set when a rec eived frame is fully moved into host memory and receive
status has been written to descriptor. Receive process is still running and continues to
fetch next descriptor.
5 TXFU 0b,RW
Transmit FIFO Un der-run
This bit is set when the transmit FIFO has a under-run condition during the packet
transmission. It may happen due to the h eavy load on bus, receive process dominate
in full-duplex, or transmit buffer unavailable before end of pack et. In this case, transmit
process is placed in the suspend state and under-run error TDES0<1> is set.
3 TXJT 0b,RW
Transmit Jabber Timer Expired
This bit is set when the jabber timer expired with the transmitter is still active.
Transmit process will be aborted and placed in the stop state. It also causes transmit
jabber timeout TDES0<14> to assert.
2 TXDU 0b,RW
Transmit Buffer Unavailable
This bit is set when the DM9102 fetches the n ext transmit descriptor that is still
owned by the host. The transmit proce ss will be suspended un ti l th e t r ans mit
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polling command is set or auto-polling timer time-out.
1 TXPS 0b,RW
Transmit Process Stopped
This bit is set to indicate transmit process enters the stopped state.
0 TXCI 0b,RW
Trans mit C o mple te Inte rrup t
This bit is set when a frame is fully transmitted and the transmit status has been w riten
to descriptor ( the TDES1<31> is also asserted). The transmit process is still running
and continues to fetch next descriptor.
Note: Bits 1~16 can be cleared by writing “1”
7. Network Operation Mode Register (CR6)
31 30
29 28 27
26 25 24 23
22
21 20
19 18 17 161514 13 12 11
10
9876543 2 1
0
0
00 1
1 0000 0
0
Bit Name Default Description
30 RXA 0b,RW
Receive All
When set, all incoming packet will be received, regardless the destination address.
The address match is checked according to theCR6<7>, CR6<6>, CR6<4>,
CR6<2>, CR6<0>, and RDES0<30> will show this match.
28:26 Reserved 000b,RW
Must be Zero .
25 Reserved 1b,RW
Must be One.
24:23 Reserved 00b,RW
Must be Zero .
22 TXTM 1b,RW
Transmit Threshold Mode
When set, the transmit threshold mode is 10Mb/s. When reset, the threshold mode
is 100Mb/s. This bit is used together with CR6<15:14> to decide the e xact threshold
leve l.
21 SFT 0b,RW
Store and Forward Transmit
When se t, th e packe t t ra nsmissi on from MAC will be started after a full frame has
been moved from the host memory to transmit FIFO. When reset, the packet
transmission’s start will depend on the threshold value specified in CR6<15:14>
20 STI 0b,RW
Start Transmission Immediately
When th is b it is s et , th e pa cke t t rans mi ssi o n fro m MA C wi l l be s ta r te d im me diat ely
after tr ansmit FIF O’s threshold level reaches 16 bytes, regardless of the setting in
CR6<22> and CR6<15:14>. This mode will make transmit FIFO underrun condition
to happen mor e e a s i ly .
18:19 MBO 00b,RW
Must always write “11” to th es e tw o b its.
17 Reserved 0b,RW
Must be Zero .
16 Reserved 0b,RW
Must be Zero .
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28 Final
Version: DM9102-DS-F03
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15:14 TSB 00b,RW
Threshold Bits
These bits are set tog ether with CR 6<22> (chose 10Mb or 100Mb) and will decide
the exact FIFO threshold level. The packet trans m ission w i ll st a r t after the data level
exceeds the threshold value.
Bit15 Bit14
Threshold(100M
) Threshold(10M)
0 0 128 72
0 1 256 96
1 0 512 128
1 1 Reserved Reserved
13 TXSC 0b,RW
Transmit Start/stop Command
When set, the transmit process w ill begin by fetching the transmit descriptor for
available packet data to be transmitted (running state). If the fetched de scriptor is
owned by the host, the transmit process will enter the suspend state and transmit
buffer unavailable (CR5<2>) is set. Otherwise it will begin to move data from host to
FIFO and transmit out after reaching threshold level.
When reset, the transmit process is placed in the stopped state after completing the
transmission of the current frame.
12 FCM 0b,RW
Force Collision Mode
When set, the transmission process is forced to be the collision status. Meaningful
only in the internal loopback mode.
11:10 LBM 00b,RW
Loopback Mode
These bits de cide two loopback modes besides normal operation. E xternal loopback
mode expects transmitted data back to receive path and makes no collisi on
detection.
Bit11 Bit10
Loopback Mode
0 0 normal
0 1 internal loopback
1 x external loopback
9 FDM 0b,RW
Full-duplex Mode
When auto-negotiation is disable d, this bit is set to make DM9102 operate in the
full-duplex mode. Transmit and receive processes can work simultaneously.
There is no collision detection needed during this mode operation.
7 PAM 0b,RW
Pass All Mu lticas t
When set, any packet with a multicast destination address is received by DM9102.
The packet with a physical address will also be filte red based on the CR6<0> filter
mode setting.
6 PM 1b,RW
Promiscuous mode
When set, any incoming valid frame is received by DM9102, and no matter what the
destination address. The DM9102 is in itia lize d t o thi s mode after reset operation.
5 Reserved 0b,RW
Must be Zero .
4 IAFM 0b,RO
Inverse Address Filtering Mode
It is s et t o i n dicate the DM9102 operate in a Inverse Filtering Mode. This is a read only
bit and mapped from the setup frame together with CR6<2>, CR6<0> setting. That is
it is valid only during perfect filtering mode.
3 PBF 0b,RW
Pass Bad Frame
When set, the DM9102 is indicated to receive the bad frames including runt packets,
truncate d fram es cau s ed by th e FIFO ove rflo w. The bad frame also has
to pass the address filtering if the DM9102 is not set in promiscuous mode.
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2 HOFM 0b,RO
Hash-only Filter Mode
This is a read-only bit and mapped from the set-up frame together with bit4,0 of CR6.
It is s et t o i n dicate the DM9102 operate in a Hash-only Filtering Mode.
1 RXRC 0b,RW
Receive Start/Stop Command
When se t, the re ce ive pr oce s s wil l begi n by fetc hi ng the receive descriptor for
available buffer to store the new-coming packet (placed in the running state). If the
fetched descriptor is owned by the host (no descripto r i s owned by the DM9102),
the receive process will enter the suspend s tate and receive buff er unavailable
CR5<7> sets. Otherwise it runs to wait for the packet’s income. When reset, the
receive process is placed in the stopped state after completing the reception of the
current frame.
0 HPFM 0b,RO
Hash/Perfect Filter Mode
This is a read only bit and mapped from the setup frame together with CR6<4>,
CR6<2>. When reset, the DM9102 does a perf ect address filter of incoming frames
according to the addresses specified in the setup frame. When set, the DM9102
does a imperfect address filtering for the incoming frame with a multicast address
according to the hash table specified in the setup frame. The filtering mode
(perfect/imperfect) for the frame with a physical address will depend on CR6<2>.
8. Interrupt Mask Register (CR7)
31
30
29 28 27
26
25 24 23
22 21 20
191817
16
15
14
13 12
11
10
987654321
0
Bit Name Default Description
16 NISE 0b,RW
Normal Interrupt Summary Enable
This bit is set to enable the interrupt for Normal Interrupt Summary.
Normal interrupt includes three conditions :
CR5<0> – TXCI : Transmit Complete Interrupt
CR5<2> – TXD U : Tran sm it Bu ffe r Un a vai lable
CR5<6> – RXCI : Rece ive Complete Interrupt
15 AISE 0b,RW
Abnormal Interrupt Summary Enable
This bit is set to enable the interrupt for Abnormal Interrupt Summary.
Abnormal interrupt includes all interrupt condition as s hown below excluding Normal
Interrupt conditions. They are TXPS(bit1), TXJT(bit3), TXFU(bit5), RXDU(bit7),
RXPS(bit8), RX WT(bit9), TXER(b it10), GPT( bit11), SBE(bit13 ).
13 SBEE 0b,RW
System Bus Error Enable
When set together with CR7<15>, CR5<13>, it enables the interrupt for System Bus
Error. The type of system bus error is shown in CR5<24:23>.
11 GPTE 0b,RW
General-purpose Timer Expired Enable
This bit is set together with CR7<15>, CR5<11> then it will enable the interrupt for
the condition of the general-purpose timer (described in CR11) expired.
10 TXERE 0b,RW
Transmit Early Interrupt Enable
This bit is set together with CR7<16>, CR5<10> then it enables the interrupt of the
early transmit event.
9 RXWTE 0b,RW
Receive Watchdog Timer Expired Enable
When this bit and CR7<15>, (CR5<9> are set together, it enable the interrupt of the
condition of the receive watchdog timer expired.
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8 RXPSE 0b,RW
Receive Process Stopped Enable
When set together with CR7<15> and CR5<8> . T hi s bit is set to enable the interrupt
of receive process stopped condition.
7 RXDUE 0b,RW
Receive Buffer Unavailable Enable
When this bit and CR7<15>, CR5<7> are set together, it w ill enable the interrupt of
receive buffer unavailable condition.
6 RXCIE 0b,RW
Recei ve C o mplete In te rru pt En ab le
When this bit and CR7<16>, CR5<6> are set together, it w ill enable the interrupt of
receive process completed condition.
5 TXFUE 0b,RW
Transmit FIFO Un der-run Enab le
When set together with CR7<15>, CR5<5>, it wil l enabl e the i nterrupt of the transmit
FIFO under-run condition.
3 TXJTE 0b,RW
Transmit Jabber Timer Expired Enable
When this bit and CR7<15>, CR5<3> are set together, it enables the interrupt of
transmit Jabber Timer Expired condition.
2 TXDUE 0b,RW
Transmit Buffer Unavailable Enable
When this bit and CR7<16>, CR5<2> are set together, the trans mit buffer unavailable
interrupt is enabled.
1 TXPSE 0b,RW
Transmit Process Stopped Enable
When this bit is set together with CR7<15> and CR5<1>, it will enable the interrupt
of the transmit process stopped
0 TXCIE 0b,RW
Trans mit C o mple te Inte rrup t E nab le
When this bit and CR7<16>, CR5<0> are set, tran smit interrupt is enabled.
9. Statistical Coun t er Register (CR8)
31
30
29 28 27
26
25 24 23
22 21 20
191817
16
15
14
13 12
11
10
987654321
0
Bit Name Default Description
31 RXFU 0b,RO
Receive Overflow Counter Overflow
This bit is set when the Purged Packet Counter (RXDU) has an o v erflow condition.
It is a read only register bit.
30:17 RXDU 0000h,RO
Receive Purged Packet Counter
This is a statistic counter to ind icate the purged rec eived pa cket count upon FIFO
overflow.
16 RXPS 0b,RO
Receive Missed Counter Overflow
This bit is set when the Receive Missed Frame Counter (RXCI) has an o verflow
condition. It is a read only register bit.
15:0 RXCI 0000h,RO
Receive Missed Frame Counter
This is a statistic counter to indicate the Receive Missed Frame Count when there is
a host buffer unavailable condition for receive process.
Note : CR8 is cleared after read
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10. PROM & Management Access Register (CR9)
31 30
29 28 27
26
25 24
23
22
21 20
19 18 17 161514 13 12 11
10
987654321
0
7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20
19 18 17 16
14 13 12 11 10159 8
Bit Name Default Description
19 MDIN 0b,RO
MII Management Data_In
This is read only bit to indicate the MDIO input data.
18 MRW 0b,RW
MII Management Read/Write Mode Selection
This bit defines the Read/Write Mode for MII management interface for PHY access.
17 MDOUT 0b,RW
MII Management Data_Out
This bit is used to generate the output data signal for the MDIO pin.
16 MDCLK 0b,RW
MII Management Clock
This bit is used to generate the output clock signal for the MDC pin.
14 MRC 0b,RW
Memory Read Control
This bit is set to perform the read oper ation for the Boot PROM o r EEPROM access.
13 EWC 0b,RW
Memory Write Con trol
This bit is set to perform the write operation for the Boot PROM (Multiplex mode) or
EEPROM acces s.
12 BRS 1b,RW
Boot ROM Selected
This b it is s e t to se lect th e Boo t RO M a c ces s for me mory interface.
11 ERS 0b,RW
EEPROM Selected
This b it is s e t to se lect th e EE PRO M a c ces s for me mory interface.
10 XRS 0b,RW
External Register Selected
This b it is s e t to se lect a n e xtern a l reg is ter.
7:0 DATA FFH,RW
Data input/output of Boot ROM
This field contains the data read from or write to the Boot ROM when the Boot ROM
mode is selected. (CR9<12> = 1)
If EEPROM is selected (CR9<11> = 1), then CR9<3:0> are connected the serial
ROM control pins.
3 CRDOUT 1b,RO
Data_Out from EEPR OM
This bit is set to re flect the sign al status of EEDI pin when EEPROM mode is
selected.
2 CRDIN 0b,RW
Data_In to EEPROM
This bit is set to generate the output sig na l to E E DO pin whe n EEPR OM mod e is
selected.
1 CRCLK 0b,RW
Clock to EE PROM
This bit is set to generate the output clock t o EECLK pi n when EEPROM mode is
selected.
0 CRCS 0b,RW
Chip_Select to EEPROM
This bit is set to generate the output sign al to EEC S pin when EEPROM mode is
selected.
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11. Programming ROM Address Register (CR10)
31
30
29 28 27
26
25 24 23
22 21 20
191817
16
15
14
13 12
11
10
987654321
0
Bit Name Default Description
17:0 BADR Unpredictable
Boot ROM Address
This field contains the address pointer for Boot ROM when the mode of
programming by register is selected.
12. General Purpose Timer Register (CR11)
31 30
29 28 27
26
25 24
23
22
21 20
19 18 17 161514 13 12 11
10
987
6
54321
0
Bit Name Default Description
16 TCON 0b,RW
Continuous Mode of Timer
When this b it is set, th e timer will co ntinuously re-initiated upon the set time is up.
When reset, the timer will be one-shot response after BCLK value is programmed.
15:0 MBCLK 0000h,RW
Mult ip le o f Ba s e Clo c k
This field set the iteration number of base clock. The base clock duration is defined
to be
81.92us --- for MII port/100M is selected
2us --- for M II port/10 M is s elec ted
13. PHY Status Register (CR12)
31
30
29 28 27
26
25 24 23
22 21 20
191817
16
15
14
13 12
11
10
987654321
0
Bit Name Default Description
8 GEPC X b, RW
GEPD B its Con tr ol
When in in it ia liza tio n , thi s bit i s set and the unique “80h” must be w ritten to the
GEPD(7:0). After initialization, this bit is reset and it controls the functional mode of
GEPD in bit0~7.
7 GEPD(7 ) X b, RW General PHY Reset Control
It must be s et to “1” if CR12<8> is set.
When CR12<8> is reset, write “1” to this bit will reset the PHY of the DM9102.
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6:0 GEPD(6:0)
XXXXXXX b
,RW
General PHY Status
When CR12<8> is set at initializati on, it operates the only write operation
and write the unique “0000000” to these seven bits.
After initialization, CR12<8> is reset, write operation is meaningless and
read these seven bits to indicate the PHY status.
These status bits are shown below.
bit 6:UTP-SIG
bit 5:Signal Detection
bit 4:RX-lock
bit 3:Link status (the sam e as bi t2 of PHY Register)
bit 2:Full-duplex
bit 1:Speed 100Mbps lin k
bit 0:Speed 10Mbps lin k
14. Access Register (CR13)
31
30
29 28 27 26
25 24 23
22 21
2019181716 151413 121110
987654321
0
register general definition bit8 ~ 3 R/W
TxFIFO transmit F IFO access port 32h r/w
RxFIFO receive FIFO access port 35h r/w
DiagReset general reset for diagnostic pointer port 38h w
15. Data Register (CR14)
31 30
29 28 27
26
25 24
23
22
21 20
19 18 17 161514 13 12 11
10
987
6
54321
0
16. Watchdog and Jabber Timer Register (CR15)
31 30
29 28 27
26
25 24
23
22
21 20
19 18 17 161514 13 12 11
10
987
6
54321
0
0
Bit Name Default Description
8 Reserved 0b,RW
Must be Zero .
5 TWDR 0b,RW
Time Interval of Watchdog Release
This bit is used to select the time interval between receive Watchdog timer e x pira tion
until re-enabling of the receive channel. When this bit is set, the time interval is 40~48
bits time . When th is bit is re se t, it is 1 6~2 4 b its ti me.
4 TWDE 0b,RW
Watchdog Timer Disable
When set, the Watchdog Timer is disabled. Otherwise it is enabled.
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2 JC 0b,RW
Jabber Clock
When set, the trans mission is cu t off after a range o f 2048 bytes to 2560 bytes is
transmitted.
When re s e t, t ra n s mission fo r the 10Mbps port is cut off after a range of 26ms to
33ms.
When re s e t, t ra n s mission for the 100Mbps port is cut off after a range of 2.6ms to
3.3ms.
1 TUNJ 0b,RW
Transmit Un-jabber Interval
This bit is used to select the time interval between the transmit jabber timer expiration
until re-enabling of the transmit channel. When set, the trans mit channel is released
right after the jabber expiration. When reset, the time interval is 365~420ms for
10Mb/s port and 36.5~42.0ms for 100Mb/s.
0 TJE 0b,RW
Transmit Jabber Disable
When set, the transmit Jabber Timer is disabled. Otherwise it is enabled.
a
PHY Management Register Set
Register Address Register Name Description
0 BMCR Basic Mode Control Register
1 BMSR Basic Mode Status Register
2 PHYIDR1 PHY Identifier Register #1
3 PHYIDR2 PHY Identifier Register #2
4 ANAR Auto-Negotiation Advertisement Register
5 ANLPAR Auto-Negotiation Link Partner Ability Register
6 ANER Auto-Negotiation Expansion Register
7-15 Reserved Reserved
16 DSCR DAVICOM Specified Configuration Register
17 DSCSR DAVICOM Specified Configuration/Status Register
18 10BTCSR 10BASE-T Configuration/Status Registe r
Others Reserved Reserved For Future Use-Do Not Read/Write To These Registers
Key to Default
In the register description that follows, the default
column takes the form:
<Reset Value>, <Access Type> / <Att ribute(s)>
Where
<Reset Value>:
1 Bit set to logic one
0 Bit set to logic zero
X No default value
(PIN#) Value latched in from pin # at reset
<Access Type>:
RO = Read onl y
RW = Read/Write
<Attribute (s)>:
SC = Self clearing
P = Value permanently set
LL = Latching low
LH = Latching high
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Basic Mode Control Register (BMCR) - Register 0
Bit Name Default Description
0.15 Reset 0b, RW/SC Reset:
1=Software res e t
0=Normal operation
This bit sets the status and controls the PHY registers of DM9102
to their default stat es. This bit, which is self-clearing, will keep
returning a value of one until the reset process is completed
0.14 Loopback 0b, RW Loopback:
Loop-back control register
1=Loop-back enabled
0=Normal operation
When in 100Mbps operation mode, setting this bit may cause the
descrambler to lose synchronization and produce a 720ms "dead
time" before any valid data appear at the MII receive outputs
0.13 Speed
Selection
1b, RW Speed Sel ect:
1=100Mbps
0=10Mbps
Link speed may be selected either by this bit or by Autonegotiation. When Auto-negotiation is enabled and bit 12 is set,
this bit will return Auto-negot iation selected media type.
0.12 Auto-
negotiation
Enable
1b, RW Aut o-negotiation Enable:
1= Auto-negotiation enabled: bit 8 and 13 will be in Auto-
negotiation status
0= Auto-negoti ation disabled: bit 8 and 13 will determine the link
speed and mode
0.11 Power Down 0b, RW Power Down:
Setting this bit will power down the whole chip except crystal
oscillator circuit.
1=Power Down
0=Normal Operation
0.10 Isolate (PHYAD=00000b)
,RW
Isolate:
1= Isolates the DM9102 from the MII with the exception of the
serial management.
0= Normal Operation
0.9 Restart Autonegotiation
0b,RW/SC Restart Auto-negotiation:
1= Restart Auto-negot iation. Re-initiates the Auto-negotiation
process. When Auto-negotiation is disabled (bit 12 of this
register cl ear ed) , this bit has no function and it should be
cleared. T his bit is self-clearing and it will keep returning a
value of 1 until Auto-negotiation is initiated by the DM9102.
The operation of the Auto-negotiation process will not be
affected by the management entity that clears this bit
0= Normal Operation
0.8 Duplex Mode 1b,RW Dupl ex Mode:
1= Full Duplex operation. Duplex sel ecti on is allowed when Auto-
negotiation is disabled (bit 12 of this register i s cleared) . With
Auto-negotiation enabled, this bit reflects the duplex capability
selected by Auto-negotiation
0= Normal operation
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0.7 Collision Test 0b,RW Collision Test:
1= Collision Test enabled. When set, this bit will cause the COL
signal to be asserted in response to the assertion of TX_EN
0= Normal Operation
0.6:0.0 Reserved 0000000b,RO Reserved:
Write as 0, ignore on read
Basic Mode Status Register (BMSR) - Register 1
Bit Name Default Description
1.15 100BASE-T4 0b,RO/P 100BASE-T4 Capable:
1=DM9102 is able to perform in 100BASE-T4 mode
0=DM9102 is not able to perform in 100BASE-T4 mode
1.14 100BASE-TX
Full Duplex
1b,RO/P 100BASE-TX FULL DUPLEX CAPABLE:
1= DM9102 able to perform 100BASE-TX in Full Duplex mode
0= DM9102 not able to perform 100BASE-TX in Full Duplex mode
1.13 100BASE-TX
Half Duplex
1b,RO/P 100BASE-TX Half Duplex Capable:
1=DM9102 is able to perform 100BASE-TX i n Half Duplex mode
0=DM9102 is not able to perform 100BASE-TX in Half Duplex mode
1.12 10BASE-T
Full Duplex
1b,RO/P 10BASE-T Full Duplex Capable:
1=DM9102 is able to perform 10BASE-T in Full Duplex mode
0=DM9102 is not able to perform 10BASE-T in Full Duplex mode
1.11 10BASE-T
Half Duplex
1b,RO/P 10BASE-T Ha l f Duplex Capable:
1=DM9102 is able to perform 10BASE-T in Half Duplex mode
0=DM9102 is not able to perform 10BASE-T in Half Duplex mode
1.10-1.7 Reserved 0000b
,RO
Reserved:
Write as 0, ignore on read
1.6 MF Preamble
Suppression
0b,RO MII Frame Preamble Suppression:
1=PHY will accept management frames with preamble suppressed
0=PHY will not accept m anagement frames with preamble
suppressed
1.5 Auto-negotiation
Complete
0b,RO Auto-negotiation Complete:
1=Auto-negot iation process completed
0=Auto-negot iation process not completed
1.4 Remote Fault 0b,
RO/LH
Remote Fault:
1= Remote fault condition detected (cleared on read or by a chip
reset). Fault criteria and detection method is DM9102
implementati on specific. This bit will set after the RF bit in the
ANLPAR (bit 13, register address 05) is set
0= No remote fault condition detected
1.3 Auto-negotiation
Ability
1b,RO/P Auto Configuration Ability:
1=DM9102 able to perform Auto-negotiation
0=DM9102 not able to perform Auto-negotiation
1.2 Link Status 0b
,RO/LL
Link Status:
1=Valid link established (for either 10Mbps or 100Mbps operation)
0=Link not establi shed
The link status bit is implemented with a latching function, so that the
occurrence of a link failure condition causes the Link Status bit to be
cleared and remain cleared until it is read via the management
interface
1.1 Jabber Detect 0b, Jabber Detect:
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RO/LH 1=Jabber condition detected
0=No jabber
This bit is implemented with a latching function. Jabber conditions
will set this bit unless it is cleared by a read to this register through a
management interface or a DM9102 reset. This bit works only in
10Mbps mode
1.0 Extended Capability 1b,RO/P Extended Capability:
1=Extended register capability
0=Basic register capability only
PHY ID Identifier Register #1 (PHYIDR1) - Register 2
The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9102. The Identifier consists
of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model
revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E.
Bit Name Default Description
2.15-2.0 OUI_MSB <0181H> OUI Most Signific ant Bits:
This register stores bi t 3 to 18 of the OUI (00606E) to bit 15 to 0
of this register respe ctively. The most significant two bits of the
OUI are ignored (the IEEE standard refers to these as bit 1 and 2)
PHY Identifier Register #2 (PHYIDR2) - Register 3
Bit Name Default Description
3.15-3.10 OUI_LSB <101110b>
,RO/P
OUI Least Signific ant Bits:
Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this
register respectively
3.9-3.4 VNDR_MDL <000000b>
,RO/P
Vendor Model Num ber:
Six bits of vendor model number mapped to bit 9 to 4 (most
significant bit to bit 9)
3.3-3.0 MDL_REV <0000b>,RO/P Model Revi sion Number:
Four bits of vendor model revision number mapped to bit 3 to 0
(most significant bit to bit 3)
Auto-negotiation Advertisement Regist er ( ANAR) - Register 4
This register contains the adv ertised abi liti es of this DM9102 dev ic e as they will be transmit ted to its link part ner
during Auto-negotiation.
Bit Name Default Description
4.15 NP 0b,RO/P Next Page Indication:
0=No next page available
1=Next page available
The DM9102 has no next page, so this bit is permanently set to 0
4.14 ACK 0b,RO Acknowledge:
1=Link partner ability data reception acknowledged
0=Not acknowledged
The DM9102's Auto-negotiation state machine will automatically
control this bit in the outgoing FLP bursts and set it at the
appropriate time during the Auto-negotiation process. Software
should not attempt to write to this bit.
4.13 RF 0b, RW Remote Fault:
1=Local Device senses a fault condition
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0=No fault detected
4.12-4.11 Reserved 00b, RW Reserv ed:
Write as 0, ignore on read
4.10 FCS 0b, RW Flow Control Support:
1=Controll er chip supports flow control ability
0=Controll er chip doesn’t support flow control abilit y
4.9 T4 0b, RO/P 100BASE-T4 Support:
1=100BASE-T4 supported by the local device
0=100BASE-T4 not s upporte d
The DM9102 does not support 100BASE-T4 so this bit is
permanently set t o 0
4.8 TX_FDX 1b, RW 100BASE-TX Full Duplex Support:
1=100BASE-TX Full Duplex supported by the local device
0=100BASE-TX Full Duplex not supported
4.7 TX_HDX 1b, RW 100BASE-TX Support:
1=100BASE-TX supported by the local device
0=100BASE-TX not supported
4.6 10_FDX 1b, RW 10BASE-T Full Duplex Support:
1=10BASE-T Full Duplex supported by the local device
0=10BASE-T Full Duplex not supported
4.5 10_HDX 1b, RW 10BASE-T Support:
1=10BASE-T supported by the local device
0=10BASE-T not supported
4.4-4.0 Select or <00001b>, RW Protocol Sel ecti on Bit s:
These bits contain the binary encoded protocol selector
supported by this node.
<00001> indicates that this device supports IEEE 802.3
CSMA/CD.
Auto-negotiation Link Partner Ability Register (ANLPAR) - Register 5
This register contains the advertised abilities of the link partner when received during Auto-negotiation.
Bit Name Default Description
5.15 NP 0b, RO Next Page Indication:
0= Link partner, no next page available
1= Link partner, next page available
5.14 ACK 0b, RO Acknowledge:
1=Link partner ability data reception acknowledged
0=Not acknowledged
The DM9102's Auto-negotiation state machine will automatically
control this bit from the incoming FLP bursts. Software should not
attempt to write to this bit.
5.13 RF 0b, RO Remote Fault :
1=Remote fault indicated by link partner
0=No remote fault indicated by link partner
5.12-5.10 Reserved 000b, RO Reserved:
Write as 0, ignore on read
5.9 T4 0b, RO 100BASE-T4 Support:
1=100BASE-T4 supported by the link partner
0=100BASE-T4 not supported by the link partner
5.8 TX_FDX 0b, RO 100BASE-TX Full Duplex Support:
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1=100BASE-TX Full Duplex supported by the link partner
0=100BASE-TX Full Duplex not supported by the link partner
5.7 TX_HDX 0b, RO 100BASE-TX Support:
1=100BASE-TX Half Duplex supported by the link partner
0=100BASE-TX Half Duplex not supported by the link partner
5.6 10_FDX 0b, RO 10BASE-T Full Duplex Support:
1=10BASE-T Full Duplex supported by the link partner
0=10BASE-T Full Duplex not supported by the link partner
5.5 10_HDX 0b, RO 10BASE-T Support:
1=10BASE-T Half Duplex supported by the link partner
0=10BASE-T Half Duplex not supported by the link partner
5.4-5.0 Select or <00000b>, RO Protocol Sel ection Bit s:
Link partner’s binary encoded protocol selector
Auto-N egotiation Ex pansion Regist er (A NER)-Register 6
Bit Name Default Description
6.15-6.5 Reserved 0b, RO Reserved:
Write as 0, ignore on read
6.4 PDF 0b, RO/LH Local Device Parallel Detection Fault:
PDF =1: A fa ult d ete cte d vi a p ar allel de tec tio n fun cti on .
PDF=0: No fault detected via parallel detection function
6.3 LP_NP_ABLE 0b, RO Link Partner Next Page Able:
LP_NP_ABLE=1: Link partner, next page available
LP_NP_ABLE=0: Link partner, no next page
6.2 NP_ABLE 0b,RO/P Local Device Next Page Able:
NP_ABLE=1: DM9102, next page available
NP_ABLE=0: DM9102, no next page
DM9102 does not support this function, so this bit is always 0.
6.1 PAGE_RX 0b, RO/LH New Page Received:
A new link code word page received. This bit will be automatically cleared
when the register (Register 6) is read by management
6.0 LP_AN_ABLE 0b, RO Link Partner Auto-negotiation Able:
A “1” in this bit indicates that the link partner supports Auto-negotiation.
DAVICOM Specified Configuration Register (DSCR) - Register 16
Bit Name Default Description
16.15:16.13 Reserved 0b, RW Reserved
16.12 Reserved 0b, RW This bit must set to be 0.
16.11 Reserved 0b, RW This bit must set to be 0
16.10 TX 1b, RW This bit m ust set to be 1
16.9 UTP 1b, RW UTP Cable Control:
1=The media is a UTP cable, 0=STP
16.8 Reserved 0b, RW Reserved
16.7 F_LINK_100 0b, RW Force Good Link in 100Mbps:
0=Normal 100Mbps operation
1=Force 100Mbps good link status
This bit is useful for diagnostic purposes.
16.6 Reserved 1b, RW T his bit must force d to be 1.
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16.5 LED_CTL 0b,RW LED Mode Select: (control LEDTRF, LED100M, LED10M)
0 = LEDTRF is Activity LED, and LED100M ind icates good link
to 100Mbps, LED10M indicates good link to 10Mbps .
1 = LEDTRF is no use, LED100M, LED10M indicate Link and
Activity. When good links to 100Mbps, LED100M actives and
flashes if any traffic exists. When good links to 10Mbps, LED10M
actives and fl ashes if any traffic exists.
16.4 Reserved 0b,RW This bit must fo r ced to be 0
16.3 SMRST 0b,RW Reset State Machine:
When write 1 to this bit, all state machines of PHY will be reset.
This bit is self-clear after reset is completed.
16.2 MFPSC 0b,RW MF Preamble Suppression Control:
MII frame preamble suppression control bit
1 = MF preamble suppression bit on
0 = MF preamble suppression bit off
16.1 SLEEP 0b,RW Sleep Mode:
Writing a 1 to this bit will cause PHY entering the Sleep mode
and power down all circuit except oscillator and clock generator
circuit. When waking up from Sleep mode (write this bit to 0), the
configuration will go back to the state before sleep; but the state
machine will be reset
16.0 RLOUT 0b,RW Remote Loop out Con t rol:
When this bit is set to 1, the received data will loop out to the
transmit c hannel. This is useful for bit error rate testing
DAVICOM Specified Configuration and Status Register (DSCSR) - Register 17
Bit Name Default Description
17.15 100FDX 1b, RO 100M Full Duplex Operation Mode:
After Auto-negotiation is completed, results will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 100Mbps
Full Duplex mode. The software can read bit[15:12] to see which
mode is selected after Auto-negotiation. T his bit is invalid when it
is not in the Auto-negotiation mode.
17.14 100HDX 1b, RO 100M Half Duplex Operation Mode:
After auto-negotiation is completed, resul ts will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 100Mbps
half-duplex mode. The software can read bit[15:12] to see which
mode is selected after Auto-negotiation. T his bit is invalid when it
is not in the Auto-negotiation mode.
17.13 10FDX 1b, RO 10M Full Duplex Operation Mode:
After auto-negotiation is completed, resul ts will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 10Mbps Full
Duplex mode. The software can read bit[15:12] to see which
mode is selected after Auto-negotiation. T his bit is invalid when it
is not in the Auto-negotiation mode.
17.12 10HDX 1b, RO 10M Half Duplex Operation Mode:
After Auto-negotiation is completed, results will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 10Mbps
Half Duplex mode. The software can read bit[15:12] to see which
mode is selected after Auto-negotiation. T his bit is invalid when it
is not in the Auto-negotiation mode.
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17.11-17.9 Reserved 000b, RW Reserved:
Write as 0, ignore on read
17.8-17.4 PHYAD[4:0] 00001b, RW PHY Address Bit 4:0:
The first PHY address bit transmitted or received is the MSB of
the address (bit 4). A station management entity connected to
multiple PHY entities must know the appropriate address of each
PHY. A PHY address of <00000> will c ause the isolate bit of the
BMCR (bit 10, Register Address 00) to be set.
17.3-17.0 ANMB[3: 0] 0000b, RO Auto-negot iation Monitor Bits:
These bits are for debug only. T he Au to- negotiati on status will
be w r itte n to these bits.
b3 b2 b1 b0
0000In IDLE state
0 0 0 0 Ability match
0010Acknowledge
match
0011Acknowledge match fail
0100Consistency
match
0101Consistency match fail
0110Parallel detects
signal_link_ready
0 1 1 1 Parallel detects signal_link_ready
fail
1000Auto-negotiation completed
succes sfu lly
10BASE-T Configurat ion/Status (10BTCSRCSR) - Regist er 18
Bit Name Default Description
18.15 Reserved 0b, RO Reserved:
Write as 0, ignore on read
18.14 LP_E N 1b, RW Li nk Pul se Enable:
1=Transmission of link pulses enabled
0=Link pulses disabled, good li nk condit ion for ced
This bit is valid only in 10Mbps operation.
18.13 HBE 1b,RW Heartbeat Enable:
1=Heartbeat function enabled
0=Heartbeat function disabled
When the DM9102 is configured for Full Duplex operation, this bit
will be ignored (the collision/heartbeat function is invalid in Full
Duplex mode). It must set to be 1.
18.12 Reserved 0b, RO Reserved:
Write as 0, ignore on read
18.11 JABEN 1b, RW Jabber Enable:
Enables or disables the Jabber function when the DM9102 is in
10BASE-T Full Duplex or 10BASE-T Transceiver Loopback mode
1= Jabber f unction enabled
0= Jabber f unction disabled
18.10 Reserved 0b,RW Reserved
18.9-18.1 Reserved 0b, RO Reserved
18.0 Reserved 0b, RO Reserved
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T
Functional Description
a
System Buffer Management
1. Overview
The data buffers for reception and transmission
which data reside in the host memory. They are
directed with the descriptor lists that are located in
another region of the host memory. All actions for
the buffer management are operated by the
DM9102 in conjunction with the driver. The data
structures and processing algorithms are described
in the following t ext .
2. Data Structure and Descriptor List
There are two types of buffers that reside in the host
memory, the transmit buffer and the receive buffer.
The buffers are composed of many distributed
regions in the host memory. They are linked
together and controlled by the descriptor lists that
reside in another region o f the host memory. The
content of each descriptor includes poi nter to the
buffer, count of the buffer, com mand and status for
the packet to be transmitted or received. Each
descriptor list starts from the address setting of CR3
(receive descriptor base address) and CR4 (transmit
descriptor base address). The descriptor lists have
two types of structure, Ring structure and Chain
structure.
3. Buffer Management: Ring Structure Method
As the Ring structure depicted below, the
descriptors are linked directly one after another.
The first and last descriptor on the list has the
necessary information for the DM9102 to return to
the beginning of the list after the bottom descriptor is
accessed. Each descriptor points to the two buffer
regions and one packet may cross many descriptor
boundaries.
Buffer 1
Buffer 2
Buffer 1
Buffer 2
Descriptor 1
Descriptor N
Packet N
control
buffer address 1
buffer address 2
status
own
buffer 2 length buffer 1 length
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4. Buffer Management: Chain Structure Method
As the Chain structure depicted below, each
descriptor contains two pointers, one point to a
single buffer and the other to the next descriptor
chained. The first descriptor is chained with the last
descriptor under host driver’s control. With this
structure, a descriptor can be allocated anywhere in
host memory and is chained to the next descriptor.
The Chain Structure and the Ring Structure may be
combined to make the buffer structure more flexible.
Buffer 1
Buffer 1
Descriptor 1
Descriptor N
Packet N
control
buffer address 1
status
own
not valid
next descriptor address
buffer 1 length
5. Descriptor List: Buffer Descriptor Format
(a). Receive Descriptor Format
Each receive descriptor has four double-word
entries and may be read or written by the host or the
DM9102. The descriptor for mat is sh own belo w with
a detailed functional description.
31
0
OWN
Status
Control bits
Buffer Address 1
Buffer Address 2
RDES0
RDES1
RDES2
RDES3
Buffer 1 Length
Buffer 2 Length
OWN
Receive Descriptor Format
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RDES0: Owner bit with receive status
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OWN
Frame Length ( FL )
AUN
OWN: 1=owned by DM9102, 0=owned by host
This bit should be reset after packet
reception is com pleted. It will be set by the
host after received data are removed.
FL: Frame length indicating total byte count of
received packet.
AUN: Received address unmatched.
151413121110 9 8 7 6 5 4 3 2 1 0
ES RFCEMFDUE LBOM BD ED TLF LCS FT RWT PLE AE
FOE
EFL
This word-wide content includes status of r ec eived
frame. They are loaded after the received buffer that
belongs to the corresponding descriptor is full. All
status bits are valid only when the last descriptor
(End Descriptor) bit is set.
Bit 15: ES, Error Summary
It is set for the following error conditions:
Descriptor Unavailable Error (DUE =1), Runt
Frame (RF=1), Excessive Frame Length (EFL=1),
Late Collision Seen (LCS=1), CRC error (CE=1),
FIFO Overflow error (FOE=1). Valid only when
ED is se t.
Bit 14: DUE, Descriptor Unavailable Error
It is set when the frame is truncated due to the
buffer unavailable. It is valid only when ED is set.
Bit 13,12: LBOM, Loopback Operation Mode
These two bits show the received frame is
derived from
00 --- normal operation
01 --- internal loopback
10 --- external loopback
11 --- reserved
Bit 11: RF, Runt Frame
It is se t to in dic ate the rec e ived frame has the size
smaller than 64 bytes. Valid onl y when ED is set
and FOE is reset.
Bit 10: MF, Multic ast Frame
It is se t to in dic ate the rec e ived frame has a
multicast address. Valid only when ED is set.
Bit 9: BD, Begi n Descriptor
This bit is set for the descriptor indicating start of a
received frame.
Bit 8: ED, Ending Descriptor
This bit is set for the descriptor indicates end of a
received frame.
Bit 7: EFL, Excessive Fram e Length
It is set to indicate the received frame length
exceeds 1518 bytes. Valid only when ED is set.
Bit 6: LCS: Late Collision Seen
It is set to indicate a late collision found during the
frame reception. Valid o nly when ED is set.
Bit 5: FT, Fr am e Ty pe
It is se t to in dic ate the rec e ived frame is the
Ethernet-type. It is reset to indicate the received
frame is the EEE802.3- type. Valid only when
ED is set
Bit 4: RWT, Receive Watchdog Timeout
It is set to indicate receive Watchdog time-out
during the frame reception. CR5<9> will also be set.
Valid only when ED is set.
Bit 3: PLE, Physical Layer Error
It is set to indicate a physical layer error found
during the frame reception.
Bit 2: AE, Alignment Error
It is se t to in dic ate the rec e ived frame ends with a
non-byte boundary.
Bit 1: CE, CRC Error
It is se t to in dic ate the rec e ived frame ends with a
CRC error. Valid only when ED is set.
Bit 0: FOE, FIFO Ov e rflow Err o r
This bit is valid for Ending Descriptor is set. (ED = 1)
It is set to indicate a FIFO Overflow error happens
during the frame reception.
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RDES1: Descriptor Status and Buffer Size
31 30 29 28 27 26 25 24 23 22
21 ~ 11
10 ~ 0
EOR CE
Buffer 2 Length Buffer 1 Length
Bit 25: EOR, End of Ring
Set to indicate that the descriptor is located
on the bottom of the descriptor list.
Bit 24: CE, Chain Enable
Set to indicate that the second address is the
chained descriptor instead of the other
buffer.
Used as the indication of the Chain structure.
Bit 21-11: Buffer 2 Length
Indicates the size of the second buffer. It
has no meaning in chain type descriptor.
Bit 10-0: Buffer 1 Length
Indicates the siz e of the fi r st buffer in Ring
type structure and single buffe r in Ch ai n
type structure.
RDES2: Buffer 1 Starting Address
Indicates the physical starting address of buffer 1.
31
0
Buffer Address 1
RDES3: Buffer 2 Starting Address
Indicates the physical starting address of buffer 2
under the Ring structure and that of the chained
descriptor under the Chain descriptor structure.
31
0
Buffer Address 2
(b). Transmit Descriptor Format
Each transmit descriptor has four doubleword
content and may be read or written by the host or by
the DM9102. The descriptor format is shown below
with detailed description.
31
0
OWN
Status
Control bits
Buffer Address 1
Buffer Address 2
TDES0
TDES1
TDES2
TDES3
Buffer 2 Length Buffer 1 Length
Transmit Descriptor Format
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TDES0: Owner Bit with Transmit Status
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OWN
Bit 31: OWN,
1=owned by DM9102, 0=owned by host, this
bit should be set when the transmitting buffer
is filled with data and ready to be transmitt ed.
It will be reset by DM9102 after transmitting
the whole data buffer.
151413121110 9 8 7 6 5 4 3 2 1 0
ES
EC
HF
CC
TX
JT
LOC
NC
LC
LF
FUE
DF
This word wide content includes status of transmitt ed
frame. They are loaded after the data buffer that
belongs to the corresponding descriptor is
transmitted.
Bit 15: ES, Error Summary
It is set for the following error conditions:
Transmit Jabber Time-out (TXJT=1), Loss of Carrier
(LOC=1), No C arrier (NC =1), La te Co llision (LC =1),
Excessive Collision (EC=1), FIFO Underrun Error
(FUE=1).
Bit 14: TXJT, Transmit Jabber Time Out
It is se t to in dic ate the tra nsmitted f r ame is truncate d
due to transmit jabber time out condition. The
transmit jabber time out interrupt
CR5<3> is set.
Bit 11: LOC, Loss of Carrier
It is se t to in dic ate the los s of c ar rier during the frame
transmission, not valid in internal loopback mode.
Bit 10: NC, No Carrier
It is se t to in dic ate that n o car rie r signal from
transceiver is found, not valid in internal loopback
mode.
Bit 9: LC, Late Collision
It is s e t t o i n dic at e a c o llisio n oc c ur s a ft er t he c o llisio n
window of 64 bytes. Not valid if FUE is set.
Bit 8: EC, Excessive coll isio n
It is s et t o indic ate the tra nsmission is aborted due to
16 excessive collisions.
Bit 7: HF, Heartbeat Fail
It is set to i ndicate the Heartbeat check failed
after complete transmission. Not valid if FUE is
set. When TDES0< 14> is set, this bit is not
valid.
Bits 6-3: CC, Collision Count
These bits show the number of collision before
transmission. Not valid if excessive collision bit
is also set.
Bit 2: LF, Lin k tes t Fa il
It is se t to in dic ate the link te st fails b e fore the fra me
transmission.
Bit 1: FUE, FIFO Underrun Error
It is s et t o in di cate th e tra nsmissi on aborted due to
transmit FIFO underrun condition.
Bit 0: DF, Deferred
It is s e t to in dicate the frame is d eferred before ready
to transmit.
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TDES1: Transmit buffer control and buffer size
31 30 29 28 27 26 25 24 23 22
21 ~ 11
10 ~ 0
CI ED
BD
FMB1 SETF CAD
EOR CE
PD
FMB0 Buffer 2 Length
Buffer 1 Length
Bit 31: CI, Completion Int er r upt
It is set to enable transmit interrup t after the present frame
has been transmitted. It is valid only when TDES1<30> is
set or when it is a setup frame.
Bit 30: ED, Ending Descriptor
It is se t to in dic ate the pointed buf f er co n tains the
last segment of a frame.
Bit 29: BD, Begin Descriptor
It is se t to in dic ate the pointed buf f er co n tains the
first s eg men t o f a fra me.
Bit 28: FMB1, Filtering Mode Bit 1
This bit is used with FMB0 to indicate the filtering
type when the present frame is a setup frame.
Bit 27: SETF, Setup Frame
It is se t to in dic ate the current frame is a setup
frame.
Bit 26: CAD, CRC Append Disable
It is set to disable the C RC appending at the end of
the transmitted frame. Valid only when
TDES1<29> is set.
Bit 25: EOR, End of Ring Descriptor
It is se t to in dic ate the descriptor is located o n the
bottom of the descriptor list.
Bit 24: CE, Chain Enable
This bit is set to indicate the second address
(TDES3) is the chained descriptor instead of the
other buffer. It is used as the indication of the
Chain structure. When reset, it indicates the Ring
structure.
Bit 23: PD, Padding Disable
This bit is set to disable the padding field for a
packet shorter than 64 bytes.
Bit 22: FMB0, Filtering Mode Bit 0
This bit is used with FMB1 to indicate the filtering type
when the present frame is a setup frame.
FMB1 FMB0 Filtering Type
0 0 Perfect Filtering
0 1 Hash Filtering
1 0 Inverse Filtering
1 1 Hash-Only Filtering
Bits 21-11: B uffer 2 length
Indicates the siz e of second buffer. It has
no meaning with chain structure descriptor
type.
Bit 10-0: Buffer 1 length
Indicates the siz e of the fi r st buffer in Ring
type structure and single buffe r in Ch ai n
type structure.
TDES2 : Buffer 1 Starting Address indicates the physical starting address of buffer 1.
BA1:
31
0
Buffer Address 1
TDES3 :
Buffer 2 Starting Address indicates the physical starting address of buffer 2 under the Ring structure.
BA2:
31
0
Buffer Address 2
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Initialization Procedure
After hardware or software reset, transmit and
receive processes are placed in the STOP state.
The DM9102 can accept the host commands to start
operation. The general procedure for initialization is
described below:
(1) Read/write suitable values for the PCI
configuration registers.
(2) Write CR3 and CR4 to provide the starting
address of eac h descriptor list.
(3) Write CR0 to set global host bus operation
parameters.
(4) Write CR7 to mask unnecessary interrupt
causes.
(5) Write CR6 to set global parameters and start
both the r ecei ve and tr ansmit processes. The
receive and transmit process e s will enter the
running state and attempt to acquire descriptors
from the respective descriptor lists.
(6) Wait for any interrupt.
Data Buffer Processing Algorithm
The data buffer process algori thm is base d on the
cooperation of the host and the DM9102. The host
sets CR3 (receive descriptor base address) and
CR4 (transmit descriptor base address) for the
descriptor list initialization. The DM9102 will start the
data buffer transfer after the descriptor polling and
get the ownership. For detailed processing
procedure, please see below.
1. Receive Data Buffer Processing
The DM9102 always attempts to acquire an extra
descriptor in anticipation of the incoming frames.
Any incoming frame size covers a few buffer regions
and descriptors. The following conditions sat is fy the
descriptor acquisition attempt:
z
When start/stop receive sets immediately after
being placed in the running state.
z
When the DM9102 begins writing frame data to
a data buffer pointed to by the current
descriptor and the buffer ends before the frame
ends.
z
When the DM9102 completes the reception of
a frame and the current receive des criptor is
closed.
z
When receiv e process is suspended due to no
free buffer for the DM9102 and a new frame is
received.
z
When receiv e poll dem and i s i ssued.
After acquiring the free descriptor, the DM9102
processes the incoming frame and places it in
the acquired descriptor's data buffer. When the
whole received frame data has been transferred,
the DM9102 will write the status information to
the last descriptor. The same process will
repeat until it encounters a descriptor flagged
as bein g owned b y the host. If this occ ur s ,
receive process enters the s uspended state and
waits the host to service.
Stop
State
Descriptor
Access
Datat
Transfer
Write
Status
Suspended
Start Receive Command Or
Receive Poll Command
Buffer Available
( OWN bit = 1 )
FIFO Threshold
Reached
Frame Fully
Received
Buffer not
Full
Receive Buffer
Unavailable
New Frame Coming Or
Receive Poll Command
Stop Receive Command or
Reset Command
Buffer Full
Receive Buffer Management State Transition
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2. Tran smit Dat a Buffer Processing
When start/stop tr ansmit c ommand is set and the
DM9102 is in running state, transmit process polls
transmit descriptor list for frames requiring
transmission. When it completes a frame
transmi ssion, the status related to the transmitt ed
frame will be written into the transmit descriptor. If
the DM9102 detects a descriptor flagged as owned
by the host and no transmit buffers are available,
transmit process will be suspended. While in the
running state, transm it process can simultaneously
acquire two frames. A s tr ansmit pr oc ess completes
copying the first frame, it immediately polls the
transmit descriptor list for the second frame. If the
second frame is valid, transmit process copies the
frame before writing the status information of the
first frame.
Both conditions bel ow will make transmit process be
suspended: (i) The DM9102 detects a descriptor
owned by the host. (ii) A frame transmission is
aborted when a locally induced error is detected.
Under either condi tion, the host driver has to service
the condition before the DM9102 can resume.
Stop State
Descriptor
Access
Data
Transfer
Write
Status
Suspended
Buffer Available
( OWN bit = 1 )
Frame Fully Transmited
Start Transmit Command Or
Transmit Poll Command
Under FIFO Threshold
Buffer not Empty
Buffer Empty
Transmit Buffer Unavailable
( Owned By Host )
Transmit Poll Command
Stop Transmit Command Or
Reset Command
Transmit Buffer Management State Transition
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a
Network Function
1. Overview
This chapter will introduce the normal state machine
operation and MAC layer management like collision
backoff algorithm. In transmit mode, the DM9102
initiates a DMA cycle to access data from a transmit
buffer. It prefaces the data with the preamble, the
SFD pattern, and it appends a 32-bit CRC. In
receive mode, the data is de-serialized by receive
mechanism and fed into the internal FIFO. For
detailed process, pl ease see below.
2. Receive Process and State Machine
a. Reception Initiation
As a preamble being d etected on the receive data
lines, the DM9102 synchronizes itself to the data
stream during the preamble and waits for the SFD.
The synchronization process is based on byte
boundary and the SFD byte is 10101011. If the
DM9102 receives a 00 or a 11 after the first 8
preamble bits and before receiving the SFD, the
reception process will be terminated.
b. Address Recognition
After initial synchronization, the DM9102 will
recognize the 6-byte destination address field. The
first bit of the destination address signifies whether it
is a physical address (=0) or a multicast address
(=1). The DM9102 filters the frame based on the
node address of receive address filter setting. If the
frame passes the filter, the subsequent serial data
will be delivered into the host memory.
c. Frame Decapsulat ion
The DM9102 checks the CRC bytes of all received
frames before releasing the frame along with the
CRC to the host processor.
3. Transmit Process and State Machine
a. Transmission Initiati on
Once the host processor prepares a transmit
descriptor for the transmit buffer, the host processor
signals the DM9102 to take it. After the DM9102 has
been notified o f thi s tran smit list , the DM 9102 will
start to mov e the data bytes from the host memory
to the internal transmit FIFO. When transmit FIFO is
adequately filled to the programmed threshold level,
or when there is a full frame buffered into the
transmit FIFO, the DM9102 begins to encapsulate
the frame. The transmit encapsulation is performed
by the transmit state machine, which delays the
actual tra n smiss io n onto the network until the
network has been idle for a minimum interframe gap
time.
b. Frame Encapsulat ion
The transmit data frame encapsulation stream
consists of two parts: Basic frame beginning and
basic frame end. The former contains 56 preamble
bits and SFD, the later, FCS. The basic frame read
from the host memory includes the destination
address, the source address, the type/length field,
and the data field. If the data field is less than 46
bytes, the DM9102 will pad the frame with the
pattern 00 up to 46 bytes.
c. Collision
When concurrent transmissions from two or more
nodes occur (termed; collision), the DM9102 halts
the transmission of data bytes and begins a jam
pattern consisting of AAAAAAAA. At the end of the
jam transmission, it begins the backoff wait time. If
the collision was detected during the preamble
transmission, the jam pattern is transmitted after
completing the preamble. The backoff process is
called truncated binary exponential backoff. The
delay is a random integer multiple of slot times. The
number of slot times of delay before the N
th
retransmission attempt is chosen as a uniformly
distributed random integer in the range:
0 ≤ r < 2
k
k = min ( n, N ) and N=10
4. Physical Layer Overview:
The DM9102 provides 100M/10Mbps dual port
operation. I t provides a direct interface either to
Unshielded Twisted pair Cable UTP5 for 100BASETX Fast Ethernet, or UTP5/ UTP3 Cable f or
10BASE-T Ethernet. In physical level operation, it
consists of the following blocks:
Ƒ
PCS
Ƒ
Clock generator
Ƒ
NRE/NREI, MLT 3 encoder/decoder and driver
Ƒ
MANCHESTER encoder/decoder
Ƒ
10BASE-T filter and driver
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a
Serial Management Interface
The serial management interface uses a simple, twowired serial interface to obtain and control the status
of PHY management register set through an MDC
and MDIO. The Management Data Clock (MDC) is
equipped with a maximum clock rate of 2.5MHz, while
Management Dat a Input /Output (MDIO) works as a
bi-directional, shared by up to 32 devices.
In read/write operation, the management data frame
is 64-bit long start with 32 contiguous logic one bits
(preamble) synchronization clock cycles on MDC. The
Start of Frame Delimiter (SFD) is indicated by a <01>
pattern followed by the operation code (OP):<10>
indicates Read operation and <01> indicates Write
operation. For read operation, a 2-bit turnaround (TA)
filing between Resistor Address field and Data field is
provided for MDIO to avoid contention. “Z” stands for
high impedance state. Following turnaround time, a
16-bit data is read fr om or written onto management
registers.
Management Interface - Read Frame Structure
32 "1"s
0110A4A3A0R4R3R0
Z
0
Idle Preamble SFD Op Code PHY Address Register Address Turn Around Data Idle
Read
Write
MDC
MDIO Read
D15 D14 D1 D0
//
//
Management Interface - Wri te Frame Structure
32 "1"s 0 1 10 A4 A3 A0 R4 R3 R0 1 0 D15 D14 D1 D0
Idle Preamble SFD Op Code PHY Address Register Address Turn Around Data Idle
Write
MDC
MDIO Write
Page 52
DM9102
10/100Mbps S ingl e Chip L AN Controller
52 Final
Version: DM9102-DS-F03
August 30, 2000
T
Configuration ROM Overview
The purpose of Configuration ROM (EEPROM) is to
support the DM9102 information to the driver for the
card. The CROM must support 64 words or more
space for configuration data. The format of the
CROM is as followed:
The format of EEPROM.
Field Name Offset Size
Subsystem ID block 0 18
CROM version 18 1
Controller count 19 1
Controller_0 Information 20 n
Controller_1 Information 20+n m
: (depends on controller count) : :
CRC checksum 126 2
1. Subsystem ID Block
Every card must have a Subsystem ID to indicate
the system vendor information. The content will be
transferred into the PCI configuration space during a
Hardware reset function.
(a)
Vendor ID & Device ID can be s et in EEPRO M
content & auto-loaded to PCI configuration
register after reset. (default value = 1282, 9102)
This function must be selectable for
enable/disable by Auto_Load_Control ( offset 08
of EEPROM) setting to avoid damaging d efault
value due to
(b)
incorrectly auto-load operation.
CRC check circuit of EEPROM contents to de cide
the auto-load operation of Vendor I D & S ub system.
Subsystem Vendor ID
Subsystem ID
Reserved
Reserved
ID_block_CRC
Reserved
Reserved
Reserved
PCI Device ID
PCI Vender ID
NCE
Auto_load_control
0
2
4
6
8
10
12
14
17,16
Byte Offset.Subsystem ID Block
Page 53
DM9102
Final 53
Version: DM9102-DS-F03
August 30, 2000
Byte Offset (0 8): Auto_Load_C ontro l
0347
Bit3~0 : “1010” to enable auto-load of PCI Vendor_ID &
Device_ID, “0” to disable.
Bit7~4 : “1X1X ” to enable auto-load of NCE, to PCI
configuration space.
Byte Offset (09): New_Capabilities_Enable
017
Bit0: Directly mapping to bit20 (New Capabilities) of the
PCICS
Byte Offset (16): ID_BLOCK_CRC
07
This field is implemented to confirm the correct reading of
the EEPROM contents.
2. CROM Version
Current ver sion number is 03.
3. Controller Count
The configurati on ROM supports m ultiple controllers
in one board. Every controller has its unique controller
information block. Controller count indicates the
number of controller s put in the card.
4. Controller_X Information
Each controller has its information block to address its
node ID, GPR control, supported connect media types
(Media Information Block) and other application circuit
information block.
Controller Information Header
ITEM Offset Size
Node Address 0 6
Controller_x Number 6 1
Controller_x Info. Block Offset 7 1
5. Controller Information Body Pointed By Controller_X
Info Block Offset Item In Controller Information Header:
Item Offset Size
Connection Type
Selected
02
GPR Control 2 1
Block Count 3 1
Block_1 4 n
: 4+n m
* Connect Type Selected indicates the default
connect media type selected.
* GPR Control defines the input or output direction of GPR.
There are three types of block:
1. PHY Information Block (type=01)
2. Media Information Block (type=00)
3. Delay Period Block (type=80)
PHY information Block (type=01)
Item Offset Size
Block Length 0 1
Block Type(01) 1 1
PHY Number 2 1
GPR Initial Length(G_i) 3 1
GPR Initial Data 4 G_i
Reset Sequence
Length(R_i)
4+G_i 1
Reset Data 5+G_i R_i
Media Capabilities 5+G_i+R_i 2
Nway Advertisement 7+G_i+R_i 2
FDX Bit Map 9+G_i+R_i 2
TTM Bit Map 11+G_i+R_i 2
Note 1: The defi n itio n of M edia Capabi lities and Nway
Advertisement is the same with 802.3U in
terms of Auto-negotiation.
Page 54
DM9102
10/100Mbps S ingl e Chip L AN Controller
54 Final
Version: DM9102-DS-F03
August 30, 2000
Media Information Block (Type = 00)
ITEM Offset Size
Block Length 0 1
Block Type(00) 1 1
Media Code 2 1
GPR Data 3 1
Command 4 2
Note 1: Media Code: 10BASE_T Half Duplex 00
10 BASE_T Full Duplex 04
100 BASE_T Half Duplex 01
100 BASE_T Full Duplex 05
Note 2: Command Format
Delay Period Block (Type = 80) Define the delay
time unit in us.
ITEM Offset Size
Block Length 0 1
Block Type(80) 1 1
Time Unit 2 2
Page 55
DM9102
10/100 Mbps Si ngle Chi p LAN Controller
Final 55
Version: DM9102-DS-F03
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T
Absolute Maximum Ratings*
Supply Voltage (VCC)...........................-0.5V to 5.5V
Maximum DC Input Voltage (V
IN
) -0.5V to VCC+0.5V
DC Output Voltage (V
OUT
).........-0.5V to VCC +0.5V
Storage Temperature Rang (Tstg) ..-65 to +150
Case Temperature Range……………..…0 to 85
Infrared Solder Reflow Peak Temp. (10 to 20 sec.)
..........................................................220to 225
ESD Rating (Rzap=1.5K, Czap=100Pf) .......... 4000V
Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. These are stress ratings only. Functional
operation of this device at these or any other
conditions above those indicated in the operational
sections of this specification is not im pl ied. Exposure
to absolute maximum rating conditions for extended
periods may aff ect dev ic e reliability.
a
DC Electrical Characteristics
Symbol Parameter Min. T yp. Max. Unit Conditions
V
CC
Supply Voltage 4.75 - 5.25 V -
T
OP
Operation Temperature -20 - 70 C -
V
IL
Input Low Voltage - - 0.8 V -
V
IH
Input High Voltage 2.0 - - V -
V
OL
Output Low Voltage (Iol = 8mA) - - 0.5 V -
V
OH
Output High Voltage (Ioh = -2mA) 2.4 - - V -
I
IL
Input Leakage Current - - 10 uA -
I
DD
Operation Supply Current - 230 250 mA -
I
PD
Power down Supply Current - T/D - uA -
Receiver
Symbol Parameter Min. Typ. Max. Unit
V
ICM
RXI+/RXI- Input Common-Mode Voltage 1.5 2.0 2.5 V
100 Ω termination
Across
Transmitter
I
TD100
100TXO+/- 100BASE-TX Mode
Differential Output Current
19 21 mA Absolute Value
I
TD10
10TX+/- 10BASE-T Differential Output
Current
44 50 56 mA Absolute Value
* -: No defined v a lue
*T/D: To be determined
Page 56
DM9102
10/100Mbps S ingl e Chip L AN Controller
56 Final
Version: DM9102-DS-F03
August 30, 2000
a
AC Electrical Characteristics
z
PCI Clock Specifications Timing
t
HIGH
2.0V
0.8V
t
R
t
F
t
LOW
t
CYCLE
Symbol Parameter Min. Typ. Max. Unit Conditions
t
R
PCI_CLK rising time 4 - - ns -
t
F
PCI_CLK falling time 4 - - ns -
t
CYCLE
Cycle time 30 - - ns -
t
HIGH
PCI_CLK High Time 12 - - ns -
t
LOW
PCI_CLK Low Time 12 - - ns -
z
Other PCI Signa ls Tim ing Diagr am
t
OFF
t
H
t
SU
Input
t
ON
Output
c
LK
2.5V
t
VAL
(max) t
VAL
(min)
Symbol Parameter Min. Typ. Max. Unit Conditions
t
VAL
Clk-To-Si gnal V alid Dealy 2 - 11 ns Cload = 50 pF
t
ON
Float-To-Active Delay From Clk 2 - - ns -
t
OFF
Active-To-Float Dealy From Clk - - 28 ns -
t
SU
Input Signal Valid Setup Time Before Clk 7 - - ns -
t
H
Input Signal Hold Time From Clk 0 - - ns -
Page 57
DM9102
10/100 Mbps Si ngle Chi p LAN Controller
Final 57
Version: DM9102-DS-F03
August 30, 2000
z
Multiplex Mode Boot ROM Timing
t
OH
t
EHQZ
t
ELQV
tAVAV
t
ELQX
Address=<7;2>
oe=1,we=0
Address
<15;8>
Date<7;0>
Valld
t
ADS
t
ADH
t
ADS
t
ADH
BPAD
<7;0>
BPA1
BPCS#
Address<1>
Address<17>
Address<16>
BPA0
Address<0>
Symbol Parameter Min. Type Max. Unit Conditions
T
AVAV
Read Cycle Time - 31 - PCI clock -
t
ELQV
BPCS# To Output Delay 0 - 7 PCI clock -
t
EHQZ
BPCS# Rising Edge To Output High
Impedance
-1-PCI clock -
t
OH
Output Hold From BPCS# 0 - - PCI clock -
t
ADS
Address Setup To Latch Enable High 4 - - PCI clock -
t
ADH
Address Hold From Latch Enable High 4 - - PCI clock -
z
Direct Mode Boot ROM Timing
Frame#
Irdy#
Trdy#
Devsel#
CBEL[3:0]
AD[31:0]
MD[7:0]
MA[17:0]
ROMCS
tCBAD
t1ADL t2ADL t3ADL t4ADL
tADTD
tRC
Page 58
DM9102
10/100Mbps S ingl e Chip L AN Controller
58 Final
Version: DM9102-DS-F03
August 30, 2000
Symbol Parameter Min. Type Max. Unit Conditions
t
RC
Read Cycle Time - 50 - PCI clock -
t
CBAD
Bus Command to first address delay - 18 - PCI cloc k -
t
1ADL
first address lengt h - 8 - PCI clock -
t
2ADL
second address delay - 8 - PCI clock -
t
3ADL
third address delay - 8 - PCI clock -
t
4ADL
fourth address delay - 7 - PCI clock -
t
ADTD
end of address to Tardy active - 1 - PCI clock -
z
EEPROM Timing
ROMCS
EECK
EEDO
tCSKD
tECKC
tEDSP
tECSC
Symbol Parameter Min. Typ. Max. Unit Conditions
t
ECKC
Serial ROM clock EECK period 64 - - P CI clock -
t
ECSC
Read Cycle Time 1792 - - PCI clock -
t
CSKD
Delay from ROMCS High to EECK High 28 - - PCI clock -
t
EDSP
Setup Time of EEDO to EECK 24 - - PCI clock -
z
PHYceiver :
Symbol Parameter Min. Typ. Max. Unit Conditions
Transmitter
t
TR/F
100TXO+/- Differential Rise/Fall Time 3.0 5.0 ns
t
TM
100TXO+/- Differential Rise/Fall Time
Mismatch
-0.5 0.5 ns
t
TDC
100TXO+/- Differential Output Duty Cycle
Distortion
-0.5 0.5 ns
t
T/T
100TXO+/- Differential Output Peak-toPeak Jitter
800 ps
X
OST
100TXO+/- Differential Voltage Overshoot 5 %
Page 59
DM9102
10/100 Mbps Si ngle Chi p LAN Controller
Final 59
Version: DM9102-DS-F03
August 30, 2000
z
Auto-neg ot iation and Fast Link Pulse Timing Dia gram
FAST LINK
PULSES
Clock Pulse Data Pulse Clock Pulse
t
1
t
2
t
3
FLP Burst FLP Burst
t
4
t
5
10TX0+/-
FAST LINK
PULSES
Clock Pulse Data Pulse Clock Pulse
t
1
t
2
t
3
FLP Burst FLP Burst
t
4
t
5
10TX0+/-
Symbol Parameter Min. Typ. Max. Unit Conditions
t
1
Clock/Dat a Pulse Width - 100 - ns
t
2
Clock Pulse To Data Pulse Period - 62.5 - us DATA = 1
t
3
Clock Pulse To Clock Pulse Period - 125 - us
t
4
FLP Burst Width - 2 - ms
t
5
FLP Burst To FLP Burst Period - 13.93 - ms
- Clock/Data Pulses Per Burst 33 33 33 ea
Page 60
DM9102
10/100Mbps S ingl e Chip L AN Controller
60 Final
Version: DM9102-DS-F03
August 30, 2000
Package In form ation
QFP 128L Outline Dimensions
Unit: Inches/mm
L
L1
Detail F
θθθθ
Seating Plane
See Detail F
D
y
0.10
See Detail A
A
A2A
1
y
B
e
138
128
103
65
102
D
D1
E1
E
64
39
With Plating
Base
Metal
Detail A
C
B
Symbol Dimension In Inch Dimension In mm
A 0.134 Max. 3.40 Max.
A1 0.010 Min. 0.25 Min.
A2
0.112± 0.005 2.85± 0.12
B
0.009± 0.002 0.22±0.05
C
0.006± 0.002 0.145± 0.055
D
0.913± 0.007 23.20± 0.20
D1
0.787± 0.004 20.00 ± 0.10
E
0.677± 0.008 17.20± 0.20
E1
0.551± 0.004 14.00± 0.10
e
0.020 BSC 0.5 BSC
L
0.035± 0.006 0.88± 0.15
L1 0.063 BSC 1.60 BSC
y 0.004 Max. 0.10 Max.
θ 0°~1 2 ° 0°~12 °
Note:
1. Dimension D1 and E1 do not include resin fins.
2. All dimensions are based on metric sy stem.
3. General appearance spec. should base itself on final visual inspection spec.
Page 61
DM9102
10/100 Mbps Si ngle Chi p LAN Controller
Final 61
Version: DM9102-DS-F03
August 30, 2000
Ordering Information
Part Number Pin Count Package
DM9102F 128 QFP
Disclaimer
The information appearing in thi s publication i s b e li ev e d to
be accurate. Integ ra t ed circ ui ts sold b y D AV ICOM
Semiconductor are covered by the warranty and patent
inde mn ific a tio n pr ovisio n s stip ulated in the te rms of sale only.
DAVICOM makes no warranty, express, statutory, implied
or by description regarding the information in this publication
or regarding the information in this publication or regarding
the freedom of the described chip(s) from patent
infringement. FURTHER, DAVICOM MAKES NO
WARRANTY OF MERCH ANTABIL ITY OR FITNE SS FOR
ANY PURPOSE. DAVICOM reserves the right to halt
production or alter the specifications and prices at any time
without notice. Accordingly, the reader is cautioned to verify
that th e da t a sheets and othe r information in this publication
are current before p lacing orders. Product s d esc ribed he rein
are intended for use in normal commercial applications.
Applications involving unusual environmental or reliability
requirements, e.g. military equipment or medical life support
equipment, are specifically not reco mmended without
additional processing by DAVICOM for such applications.
Please note that application circuits illustrated in this
document are for reference purposes only.
DAVICOM‘s terms and cond itions printed on the order
acknowledgment govern all s ales by DAVICOM. DAVICOM
will not be bound by any terms inconsistent with these
unless DAVICOM agrees otherwise in writing. Acceptance
of the buyer’s orders shall be based on these terms.
Company Ov erview
DAVICOM Semiconductor, Inc. develops and manufactures
integrated circuits for integration into data communication
products. Our mission is to design and p roduce IC products
that are the industry’s best value for Data, Audio, Video, and
Internet/Intranet applications. To achieve this goal, we have
built an organization that is able to develop chipsets in
response to the evolving technology requirements of our
custo mers w hile s ti ll de liver ing p rod u cts that meet th eir co st
requirements.
Products
We offer only products that satisfy high performance
requirements and which are compatible with major
hardware and software standards. Our currently available
and soon to be released products ar e based on our
proprietary designs and deliver high quality, high
performance chipsets that comply with modem
communication standards and Ethernet networking
standards.
Contact Windows
For additional information about DAVICOM products, contact the sales department at:
Headquarters
Hsin-c hu Off ice:
3F, No. 7-2, Industry E. Rd., IX,
Science-based Park,
Hsin-c hu C ity , Ta iw an , R. O.C .
TEL: 886-3-5798797
FAX: 886-3-5798858
Taipei Sales & Marketing Office:
8F, No. 3, Lane 235, Bao-chiao Rd.,
Hsin -t ien C ity , Ta ip ei, Ta iwa n, R. O.C .
TEL: 886-2-29153030
FAX: 886-2-29157575
Email: sales@davicom.com.tw
Davicom USA
Sunnyvale, California
1135 Kern Ave., Sunnyvale,
CA94085, U.S.A.
TEL: 1-408-7368600
FAX: 1-408-7368688
Email: sales@davicom8.com
WARNING
Conditi ons b ey on d th os e lis t ed for the absolute m axi m u m m ay d estr oy or d am ag e th e products. In addition, conditions for s u s tai ned
periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure,
perfor m ance and/or func t ion.
Page 62
DM9102
10/100Mbps S ingl e Chip L AN Controller
62 Final
Version: DM9102-DS-F03
August 30, 2000
Appendix A
DM9102 SROM Form at
Total Size: 128 Bytes
Field Name Offset
(Bytes)
Size (Bytes) Value
(Hex)
Commentary
Sub-Vendor ID 0 2 0291
ID Bloc k
Sub-Device ID 2 2 8212
Reserved1 4 4 00000000
Auto_Load_Control 8 1 00 Auto-load function definition:
Bit 3..0 = 1010 Æ Auto-Load PCI Vendor
ID/Device ID enabled
Bit 7..4 = 1010 Æ Auto-Load
PMC/PMCSR enabled
(P.S.: For DM9102 E7 and later Bit 7..4 =
1x1x Æ Auto-Load PMC/PMCSR
enabled)
New_Capabilities_Enable (NCE) 9 1 00 Please refer to DM9102 Spec.
PCI Vendor ID 10 2 1282
PCI Device ID 12 2 9102
If Auto-Load PC I Vendor ID/De vice ID funct ion
disabled, the PCI Vendor ID/D evice ID will use
the d e fau lt v a lue s ( 1282h , 9102h ).
Reserved 14 1 00 Please refer to DM9102 Spec.
Reserved 15 1 00 Please refer to DM9102 Spec.
ID_BLOCK_CRC 16 1 - Offset 0..15, 17 ID CRC
Reserved2 17 1 00
SROM Format Version 18 1 03 Version 3.0
Controller Count 19 1 01
IEEE Network Address 20 6 -
Controller Info Header
Controller_0 Dev Number 26 1 00
Controller_0 Info Leaf Offset 27 2 001E Offset 30
Reserved3 29 1 00
Selected Connected Type 30 2 0800
Controller_0 Info Leaf Block
General Purpose Control 32 1 80 MAC CR1 2 Register
Block Count 33 1 06 6 Bloc ks
F(1)+Length 34 1 8E
Block 1 (PHY Info Block)
Type 35 1 01 PHY Information Block
PHY Number 36 1 01 PHY Address
GPR Length 37 1 00
Reset Sequence Length 38 1 02
Reset Sequence 39 2 0080
Media Capabilities 41 2 7800
Nway Advertisement 43 2 01E0
FDX Bit Map 45 2 5000
TTM Bit Map 47 2 1800
Page 63
DM9102
10/100 Mbps Si ngle Chi p LAN Controller
Final 63
Version: DM9102-DS-F03
August 30, 2000
Field Name Offset
(Bytes)
Size (Bytes) Value
(Hex)
Commentary
F(1)+Length 49 1 85
Block 2 (Delay Period Block)
Type 50 1 80 Delay Period Block
Delay Sequence 51 4 40002000 MicroSecond
F(1)+Length 55 1 85
Block 3 (Media Info Block)
Type 56 1 00 Media Information Block
Media Code 57 1 00 10Base-T Half_Duplex
GPR Data 58 1 00
Command 59 2 0087
F(1)+Length 61 1 85
Block 4 (Media Info Block)
Type 62 1 00 Media Information Block
Media Code 63 1 01 100Base-TX Half_Duplex
GPR Data 64 1 00
Command 65 2 0087
F(1)+Length 67 1 85
Block 5 (Media Info Block)
Type 68 1 00 Media Information Block
Media Code 69 1 04 10Base-T Full_Duplex
GPR Data 70 1 00
Command 71 2 0087
F(1)+Length 73 1 85
Block 6 (Media Info Block)
Type 74 1 00 Media Information Block
Media Code 75 1 05 100Base-TX Full_Duplex
GPR Data 76 1 00
Command 77 2 0087
SROM_CRC 126 2 - Offset 0..125 SROM CRC
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