Datasheet ATF1500A-15AI, ATF1500A-15AC, ATF1500A-12JI, ATF1500A-12JC, ATF1500A-12AI Datasheet (ATMEL)

Features

High Density, High Performance Electrically Erasable Complex

•

Programmable Logi c De vic e

– 44-Pin, 32 I/O CPLD
– 7.5 ns Maximum Pin-to-Pin Delay
– Registered Operation Up To 125 MHz
– Fully Connected Input and Feedback Logic Array
– Backward Compatibility with ATF1500/L Software and Hardware

Flexible Logic Macrocell

•

D/T/Latch Configurable Flip Flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate

Advanced Power Management Features

•

– Automatic 3 mA Stand-By (ATF1500AL)
– Pin-Controlled 5 µA Stand-By Mode (Typical)
– Programmable Pin-Keeper Inputs and I/Os

Available in Commercial and Industrial Temperature Ranges

•

Available in 44-Pin PLCC and TQFP Packages

•

Advanced Flash Technology

•

– 100% Tested
– Completely Reprogrammable
– 100 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-Up Immunity

Supported By Popular 3rd Party Tools

•

Security Fuse Feature

•

High
Performance E
PLD

ATF1500A/AL

2

Description

The ATF1500A is a high performance, high density Complex PLD. Built on an
advanced Flash techn ology , it has m aximum pin to pin d elays of 7 .5 ns and suppo rts
sequential logic operati on at speeds up to 125 MHz . With 32 logic macrocells and up
to 36 inputs, it easily integrates log ic from several TTL, SSI, MSI and classic PLDs.
The ATF1500A's global input and feedback architecture simplifies logic placement
and eliminates pinout changes due to design changes.

(continued)

Pin Configurations

Pin
Name Function

CLK Clock
I Logic Inputs

I/O

GCLR

OE1,
OE2

V

CC

PD

Bidirectional
Buffers

Register Reset
(active lo w)

Output Enable
(active lo w)

+5V Supply
Power Down

(active high)

PLCC

Top View

INDEX
CORNER

I/O
I/O
I/O

GND

I/O
I/O
I/O
I/O

VCC

I/O
I/O

44

1
2
3
4
5
6
7
8
9
10
11

12

TQFP

VCC

I/O

I/O

I/O/PD

424340

41

15

13

14

I/O

I/O

I/O

I/O

Top View

16

GCLR/I

OE2/I

39

17

VCC

GND

OE1/I

38

18

I/O

CLK/I

GND

36

37

192021

I/O

I/O

I/O

I/O

34

35

I/O

33

I/O

32

I/O

31

I/O

30
29

VCC

I/O

28

I/O

27

I/O

26

I/O

25

GND

24

I/O

23

22

I/O

I/O

Rev. 0759C–04/98

1

Functional Logic Diagram

(1)

Note: 1. Arrows connecting macrocells indicate direction and groupings of CASIN/CASOUT data flow.

2

ATF1500A/AL

ATF1500A/AL

The ATF1500A has 32 bi-dir ectional I/O pins and 4 dedi­cated input pins. Each dedica ted input pin can also serve
as a global control signal: register clock, register reset or
output enable. Each of these control signals can be
selected for use individually within each macrocell.

Each of the 32 logic macrocells generates a buried feed­back, which goes to th e global bus. Each in put and I/O pin
also feeds into the global bus. Because of this global bus­sing, each of these signals is always available to all 32
macrocells in the device.

Each macrocell also generates a foldback logic term, which
goes to a regional b us . Al l s i gnal s with in a r egional bus are
connected to all 16 macrocells within the region.

Cascade logic between macrocells in the ATF1500A allows
fast, efficient generation of complex logic fu nctions. The
ATF1500A contains 4 such logic chains, each capable of
creating sum term logic with a fan in of up to 40 pr oduct
terms.

Bus Friendly Pin-Keeper Input and I/O’s

All Input and I/O pins on the ATF1500A have programma­ble “data keep er” circuit s. If activat ed, when any pin is
driven high or low and t hen su bsequently left floating, it will
stay at that previous high or low level.

This circuitry prevents un used Input and I/O lines from
floating to inter mediat e volt age leve ls, whic h caus e unnec­essary power consumption and system noise. The keeper
circuits eliminate the need for external pull-up resistors and
eliminate their DC power consumption.

Pin-keeper circuits c an be di sabled. Pr ogramming is co n­trolled in the logic design file. Once the pin-keeper circuits
are disabled, normal termination procedures are required
for unused inputs and I/Os.

Speed/Power Management

The ATF1500A has several built-in sp eed and power man ­agement features. The ATF1500A contain s circuitry that
automaticall y puts t he de vice into a lo w power stand-b y
mode when no logic transitions are occurring. This not only
reduces power consumption duri ng inactive periods, but
also provides a proportional power savings for most appli­cations running at system speeds below 10 MHz.

All ATF1500As also have an optional pin-controlled power
down mode. In this mode, current drops to below 10 µA.
When the power down option is selected, the PD pin is
used to power down the part. The power down option is
selected in the design source file. When enab led, the
device goes into power down wh en the PD pin i s high. In
the power down mode, all internal logic signal s are latched
and held, as are any enabled outputs. All pin transitions are
ignored until the PD is brou ght low. W hen the po wer down
feature is ena bled, the PD c annot be used as a logi c inp ut
or output. However, the PD pin's macrocell may still be
used to generate buried foldb ack and cascade log ic sig­nals.

Each output also has individual slew rate control. This may
be used to reduce system noise by slowing down outputs
that do not need to operate at maximum speed. Outputs
default to slow switching, and may be specified as fast
switching in the design file.

Design Software Support

ATF1500A designs are supported by several 3rd party
tools. Automated fitters allow logic synthesis using a variety
of high level description languages and formats.

Input Diagram

INPUT

ESD

PROTECTION

CIRCUIT

100K

PROGRAMMABLE

OPTION

I/O Diagram

V

CC

OE

DATA

V

CC

I/O

V

CC

100K

PROGRAMMABLE

OPTION

3

ATF1500A/AL Macrocell

ATF1500A Macrocell

The ATF1500A macro cell is flexible enoug h to support
highly complex logic functions operating at high speed. The
macrocell consists of five sections: product terms and prod­uct term select multiplexer; OR/XOR/CASCADE logic; a flip
flop; output select and enable; and logic array inputs.

Product Terms and Select Mux

Each ATF1500A macrocell has fiv e product terms. Each
product term recei v es as its i nputs all signals from both the
global bus and regional bus.

The product term selec t multi plex er (PTMU X) allo cates the
five product terms as needed to the macrocel l logic g ates
and control signals. The PTMUX programming is deter­mined by the design compiler, wh ich sel ects the opti mum
macrocell configuration.

OR/XOR/CASCADE Logic

The ATF1500A macrocell's OR/XOR/CASCADE logic
structure is designed to efficiently support all types of logic.
Within a single mac rocell, all the product terms can be

4

ATF1500A/AL

routed to the OR gate, creating a five input AND/OR sum
term. With the addition of the CASIN from neighboring
macrocells, this can be expanded to as many as 40 product
terms with a very small additional delay.

The macrocell's XOR gate allows efficient implementation
of compare and arithmeti c function s. One inpu t to the XOR
comes from the OR sum term. The other XOR input can be
a product term or a fixed high or low level. For combinato­rial outputs, the fixed level input allows output polarity
selection. For registered functions, the fixed levels allow De
Morgan minimization of the product terms. The XOR gate is
also used to emulate JK type flip flops.

Flip Flop

The ATF1500A's flip flo p has ve ry fl exib le d ata a nd con trol
functions. The data input can come from either the XOR
gate or from a separate product term. Selecting the sepa­rate product term allows creation of a buried registered
feedback within a combinatorial output macrocell.

(continued)

ATF1500A/AL

In addition to D, T, JK and SR operation, the flip flop can
also be configured as a flow-through latch. In this mode,
data passes through when the clock is high and is latched
when the clock is low.

The clock itself ca n be eit her the gl obal CL K pin or an indi ­vidual prod uct term. The flip flop chan ges stat e on the
clock's rising edge. When the CLK pin is used as the clock,
one of the macrocell product terms can be selected as a
clock enable. W hen the clock enab le fu nctio n is act ive and
the enable sign al (prod uct ter m) is lo w, all cloc k edge s are
ignored.

The flip flop's asynchronous reset signal (AR) can be either
the pin global clear (GCLR), a product term, or always off.
AR can also be a logic O R of GCLR with a p roduct te rm.
The asynchronous preset (AP) can be a product term or
always off.

Output Select and Enable

The ATF1500A macro cell out put can be selec ted as reg is­tered or combinatori al. When the output is regis tered, the
same registered s ignal is fed ba ck internall y to the global
bus. When the output is combinatorial, the buried feedback
can be either the same combinatorial signal or it can be the
register output if the separate product term is chosen as
the flip flop input.

The output enable multiplexer (MOE) controls the output
enable signals. Any buf fer can be pe rmanen tly enabled for
simple output operation. Buffers c an also be permanently
disabled to allow use of the pin as an input. In thi s con figu­ration all the macroc ell reso urces are still avai lable, in clud­ing the buried feedback, expander and CASCADE logic.

The output enable for eac h mac rocell can also be s elect ed
as either of the two OE pins or as an individual product
term.

Global/Regional Busses

The global bus contains all Input and I/O pin signals as well
as the buried feed back signal from al l 32 macrocells.
Together with the complemen t of eac h s ign al, t his pr ov id es
a 68 bit bus as input to every product ter m. Having the
entire global bus available to each macrocell eliminates any
potential rout ing prob lems. With this arch itecture d esigns
can be modified without requiring pinout changes.

Each macrocell also generat es a foldback product term.
This signal goes to the regi onal bus , and is a vailabl e to 16
macrocells. The foldback is an inverse polarity of one of the
macrocell's product terms. T he 16 foldb ack terms in ea ch
region allow generation of high fan-in sum terms (up to 21
product terms) with a small additional delay.

5

Absolute Maximum Ratings*

Temperature Under Bias.................................. -40°C to +85°C

Storage Temperature..................................... -65°C to +150°C

Voltage on Any Pin with

Respect to Ground ........................................-2.0V to +7.0V

(1)

Voltage on Input Pins
with Respect to Ground

During Programming....................................-2.0V to +14.0V

Programming Voltage with

Respect to Ground ......................................-2.0V to +14.0V

(1)

(1)

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the dev ice . This is a s tress rating only an d
functional oper ation of the device at these o r any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions f or e xtended periods ma y af fect de vice
reliability .

Note: 1. Minimum voltage is -0.6V dc, which may under-

shoot to -2.0V for pulses of less than 20 ns. Max­imum output pin voltage is Vcc+ 0.75V dc, which
may overshoot to 5.25V for pulses of less than 20
ns.

DC and AC Operating Conditions

Commercial Industrial

Operating Temperature(case) 0°C - 70°C-40°C - 85°C
VCC Power Supply 5V ± 5% 5V ± 10%

DC Characteristics

Symbol Parameter Condition Min Typ Max Units

I

IL

I

IH

(1)

I

CC1

I

CC2

(1)

I

CC3

I

OS

V

IL

V

IH

V

OL

V

OH

Note: 1. All ICC parameters measured with outputs open, and a 16-bit loadable, up/down counter programmed into each region.

Input or I/O
Low Leakage Current

Input or I/O
High Leakage Current

0 ≤ VIN ≤ VIL(max) -10 µA

,min ≤ VIN ≤ V

V

IH

CC

10 µA

Com. 70 mA

ATF1500A
Power Supply Current,
Standby

VCC = MAX,

= 0, V

V

IN

CC

Ind. 100 mA
Com. 3 mA

ATF1500A

Ind. 5 mA

Power Supply Current,
Power Down Mode

Clocked Power Supply
Current

Output Short Circuit
Current

Input Low Voltage

VCC = MAX,

= 0, V

V

IN

VCC = MAX,
V

IN

V

OUT

VCC, min < VCC
< V

CC

= 0, V

CC

ATF1500AL 2 mA/MHz

= 0.5V -130 mA

CC

, max

-0.5 0.8 V

5 µA

Input High Voltage 2.0 VCC + 1 V
Output Low Voltage VCC = MIN IOL = 4 mA 0.45 V

I

= -4 mA 2.4 V

Output High Voltage VCC = MIN

OH

I

= -0.2 mA VCC - .2 V

OH

6

ATF1500A/AL

AC Waveforms

Register AC Characteristics, Input Pin Clock

-7 -10 -12 -15 -20 -25

ATF1500A/AL

Symbol Parameter

(1)

t

COS

t

CFS

t

SIS

t

SFS

t

HS

t

PS

t

WS

F

MAXS

Clock to Output 4.52526282929ns
Clock to Feedback 2 2 2 2 2 2 ns
I, I/O Setup Time 6 8 10 11 14 16 ns
Feedback Setup Time 6 8 10 11 12 13 ns
Input, I/O,

Feedback Hold Time
Clock Period 6 8 9 10 11 12 ns
Clock Width 3 44.555.56 ns
External Feedback

1/(t

+ t

COS

)

SIS

Internal Feedback

+ t

1/(t

SFS

CFS

)

No Feedback 1/(tPS) 166.7 125 111 100 91 83 MHz

t

RPRS

t

RTRS

Reset Pin Recovery
Time

Reset Term Recovery
Time

Note: 1. For slow slew outputs, add t

UnitsMin Max Min Max Min Max Min Max Min Max Min Max

0 00000ns

95 76.9 62.5 52. 6 43 40 MHz

125 100 83.3 76.9 71 66 MHz

2 33455ns

6 9 10 12 13 14 ns

.

SSO

7

Register AC Characteristics, Product Term Clock

-7 -10 -12 -15 -20 -25

Symbol Parameter

(1)

t

COA

t

CFA

t

SIA

t

SFA

t

HA

t

PA

t

WA

Clock to Output 7.51012151820ns
Clock to Feedback 5 7 7 9 12 15 ns
I, I/O Setup Time 3 3 4 4 8 10 ns
Feedback Setup Time 3 3 4 4 12 15 ns
Input, I/O,

Feedback Hold Time
Clock Period 6 8 10 12 24 30 ns
Clock Width 3 4 5 6 12 15 ns
External Feedback

+ t

+ t

COA

CFA

)

)

) 166.7 125 100 83.3 41.7 33.3 MHz

PA

1/(t

F

MAXA

Internal Feedback
1/(t

No Feedback 1/(t

t

RPRA

t

RTRA

Reset Pin
Recovery Time

Reset Term
Recovery Time

SIA

SFA

Note: 1. For slow slew outputs, add t

UnitsMin Max Min Max Min Max Min Max Min Max Min Max

2 34455ns

95.2 76.9 62.5 52.6 38 33.3 MHz

125 100 90.9 76.9 41.7 33.3 MHz

0000 00ns

4566 78ns

.

SSO

8

ATF1500A/AL

AC Characteristics

ATF1500A/AL

-7 -10 -12 -15 -20 -25

Symbol Par ameter

(1)

t

PD

I, I/O or FB to
Non-Registered
Output

t

PD2

t

PD3

I, I/O to Feedback 5 7 8 9 12 14 ns
Feedback to

(1)

Non-Registered
Output

t

PD4

(1)

t

EA

t

ER

t

PZX

t

PXZ

t

PF

(1)

t

PO

Feedback to
Feedback

OE Term to Output
Enable

OE Term to Output
Disable

OE Pin to Output

(1)

Enable
OE Pin to Output

Disable
Preset to Feedback 6 9 9 12 18 20 ns
Preset to Registered

Output

UnitsMin Max Min Max Min Max Min Max Min Max Min Max

27.5310312315320325 ns

27.5310312315320325 ns

5 7 8 9 12 14 ns

27.5310312315320325 ns

27.5210212215220225 ns

25.52 7 2 8 2 9 210211 ns

1.5 5.5 1..5 7 1.5 8 1.5 9 1.5 10 1.5 11 ns

8.51214202325ns

t

RPF

t

RPO

t

RTF

t

RTO

t

CAS

t

SSO

t

FLD

Reset Pin to
Feedback

Reset Pin to

(1)

Registered Output
Reset Term to

Feedback
Reset Term to

(1)

Registered Output
Cascade Logic Delay 0.8 0.8 1 1 1.5 1.5 ns
Slow Slew Output

Adder
Foldback Term Delay 4 5 7 8 10 12 ns

Note: 1. For slow slew outputs, add t

34355.56ns

5.5 7 8 111315ns

6 9 9 121520ns

8.51214202325ns

333444ns

.

SSO

9

P ower Down AC Characteristics

-7 -10 -12 -15 -20 -25

Symbol Parameter

t

IVDH

t

GVDH

t

CVDH

t

DHIX

t

DHGX

t

DHCX

t

DLIV

t

DLGV

t

DLCV

t

DLOV

Valid I, I/O Before
PD High

Valid OE
Before PD High

Valid Clock

Input Don't Care
After PD High

OE Don't Care
After PD High

Clock Don't Care
After PD High

PD Low to Valid I,
I/O

PD Low to Valid
OE

PD Low to Valid
Clock

PD Low to Valid

(1)

Output

(2)

(2)

Before PD High

(2)

(2)

7 1012152025 ns

7 1012152025 ns

7 1012152025 ns

Notes: 1. For slow slew outputs, add t

2. Pin or Product Term.

UnitsMin Max Min Max Min Max Min Max Min Max Min Max

15 20 22 25 30 35 ns

15 20 22 25 30 35 ns

15 20 22 25 30 35 ns

111111µs

111111µs

111111µs

111111µs

.

SSO

Output Test LoadInput Test Waveforms and Measurement Levels

Pin Capacitance

f = 1 MHz, T = 25°C)

C

IN

C

OUT

Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.

10

(1)

Ty p Max Units Conditions

4.5 5.5 pF VIN = 0V

3.5 4.5 pF V

ATF1500A/AL

OUT

= 0V

Power Up Reset

The ATF1500A's registers are designed to reset during
power up. At a point delayed slightly from V

, all registers will be reset to the low state. As a result,

V

RST

crossing

CC

the registered output state will always be low on power-up.
This feature is critical for state machine initialization. How-

ever, due to the asynchronous nature of reset and the
uncertainty of how V

actually rises in the system, the fol-

CC

lowing conditions are required:

1. The V

rise must be monotonic, from below .7 volts,

CC

2. After reset occurs, all input and feedback setup times
must be met before driving the clock signal high, and

3. Signals from which clocks are derived must remain sta­ble during t

PR

.

Power Down Mode

The ATF1500A includes an optional pin controlled power
down feature. When this mode is enabled, the PD pin acts
as the power down pin. When the PD pin is high, the device
supply current is redu ce d to l es s than 10 µA. During pow er
down, all output data and internal log ic states ar e latched
and held. Therefore, all registered and combinatorial output
data remain valid. Any outputs which were in a HI-Z state at
the onset of power do wn will remain at HI-Z. Dur ing power
down, all input signals except the power down pin are
blocked. Input and I/O hold latches remain active to insure
that pins do not f loat to indete rmin ate lev els, fu rther reduc ­ing system power. The power down pin feature is enabled
in the logic design file. Designs using the power down pin
may not use the PD pin logic array input. However, all other
PD pin macrocell resources may still be used, including the
buried feedback and foldback product term array inputs.

Register Preload

The ATF1500A's registers are provided with circuitr y to
allow loading of each register with either a high or a low.
This feature will simplify testing since any state c an be
forced into the register s to control test s equencing. A
JEDEC file with pr eload is gen erated when a sou rce file
with preload vectors is c ompiled. Once downl oaded, the
JEDEC file preload seque nce will be don e automatically
when vectors are ru n by any appr oved pro gramme rs. The
preload mode is ena bled by raising an input pin to a high
voltage level. Contact Atmel PLD Applications for PRE­LOAD pin assignments, timing and voltage requirements.

ATF1500A/AL

Parameter Description Typ Max Units

t

PR

V

RST

Output Slew Rate Control

Each ATF1500A macrocell contains a configuration bit for
each I/O to control its output slew rate. This allows selected
data paths to operat e at m aximu m thr oughpu t while r educ ­ing system noise from outputs that are not speed-critical.
Outputs default to slow edges, and may be individually set
to fast in the design file. Outp ut transiti on times fo r outputs
configured as “slow” have a t

Security Fuse Usage

A single fuse is provided to preven t unauthorized copy ing
of the ATF1500A fuse patterns. Once programmed, fuse
verify and preload are prohibited. However, the 160-bit
User Signature remains accessible.

The security fuse should be programmed last, as its effect
is immediate.

Power-Up
Reset Time

Power-Up
Reset
Voltage

210

3.8 4.5 V

delay add er.

SSO

s

µ

11

12

ATF1500A/AL

ATF1500A/AL

13

14

ATF1500A/AL

Ordering Information

t

PD

(ns)

t

COS

(ns)

F

MAXS

(MHz) Ordering Code Package Operation Range

ATF1500A/AL

7.5 4.5 95 ATF1500A-7AC
ATF1500A-7JC

10 5 76.9 ATF1500A-10AC

ATF1500A-10JC
ATF1500A-10AI

ATF1500A-10JI

12 6 62.5 ATF1500A-12AC

ATF1500A-12JC
ATF1500A-12AI

ATF1500A-12JI

15 8 52.6 ATF1500A-15AC

ATF1500A-15JC
ATF1500A-15AI

ATF1500A-15JI

20 9 40 ATF1500AL-20AC

ATF1500AL-20JC
ATF1500AL-20AI

ATF1500AL-20JI

25 9 43 ATF1500AL-25AC

ATF1500AL-25JC

44A
44J

44A
44J

44A
44J

44A
44J

44A
44J

44A
44J

44A
44J

44A
44J

44A
44J

44A
44J

Commercial

(0°C to 70°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

ATF1500AL-25AI
ATF1500AL-25JI

Package Type

44A 44 Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44J 44 Lead, Plastic J-Leaded Chip Carrier (PLCC)

44A
44J

Industrial

(-40°C to 85°C)

15

Packaging Information

.045(1.14) X 45°

PIN NO.1
IDENTIFY

.045(1.14) X 30° - 45°

.012(.305)
.008(.203)

.021(.533)
.013(.330)

.630(16.0)
.590(15.0)

.043(1.09)
.020(.508)

.120(3.05)

.090(2.29)
.180(4.57)
.165(4.19)

.500(12.7) REF SQ

.032(.813)
.026(.660)

.050(1.27) TYP

.022(.559) X 45° MAX (3X)

.656(16.7)
.650(16.5)

.695(17.7)
.685(17.4)

SQ

SQ

44A

, 44-Lead, Thin (1.0 mm)
Plastic Gull Wing Quad Flat Package (TQFP)
Dimensions in Millimeters and (Inches)*

44J

, 44-Lead, Plastic J-Leaded Chip Carrier (PLCC)

Dimensions in Inches and (Millimeters)

*Controlling dimension: millimeters

© Copyright Atmel Corporation 1997.

Atmel Corporation assumes no responsibility for the use of any circuitr y other than circuitry embodied in an
Atmel Corporation product. No other circuit patent licenses are implied. Atmel Corporation’s products are not
authorized for use as critical components in life support devices or systems.

Atmel Headquarters, 2325 Orchard Parkway, San Jose, CA 95131, TEL [phone], FAX [phone]
Atmel Colorado Springs, 1150 E. Cheyenne Mtn. Blvd., Colorado Springs, CO 80906, TEL [phone], FAX [phone]
Atmel Rousset, Zone Industrielle, 13106 Rousset Cedex, France, TEL [phone], FAX [phone]

Terms and product names in this document may be trademarks of others.

16

ATF1500A/AL

Printed on recycled paper.

0759C–04/98/5M