Datasheet 5380, 53C80 Datasheet (NCR)

NCR

5380-53C80

Interface Chi

SCSI

Design

Manual

NCR Microelectronics Division, Colorado Springs

This

document NCR reserves the functions

contains

right

and

operations described herein world. Therefore, before for

the

information

that

AIIRights

the lat-est

to

modify

using

is

applicable

information

the

this document,

by

Dayton,

NCR Corporation

Ohio

Reserved Printed in U.S.A.

contents

and

current.

available

of

may

consult

not

at

this

material

be marketed

your

the time

of

publication. However,

at

any time. Also,

by

NCR in

NCR representative

all

all parts

or

features,

of

NCR

the

office

TABLE OF CONTENTS

SECTION

1.

2.

3.

4.

5.

6.

7.

8.

PAGE General Description SCSI Background Block Diagram Pin

Description

4.1

4.2 SCSl Interface Signals Electrical Characteristics Internal Registers

6.0 General

6.1

6.1.2 Output Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

6.1.3 Input Data Register

6.2 Initiator Command Register

6.3 Mode Register

6.4 Target Command Register

6.5 Current SCSI Bus Status Register

6.6 Select Enable Register

6.7 Bus and Status Register

6.8 DMA Registers

6.8.1

6.8.2 Start DMA Target Receive

6.8.3 Start DMA Initiator Receive

6.9 Reset Parity/ Interrupt On-Chip SCSI Hardware Support

Interrupts

8.1

8.2

8.3 SCSI Bus Reset

8.4 Parity Error

8.5 Bus Phase Mismatch

8.6 Loss of BSY

Microprocessor Interface Signals

Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

.1

Current SCSI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Start DMA Send

.......................................................................

Selection/ Reselection End

of Process (EOP) Interrupt

.............................................................

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.. " ................

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"

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3 4 5

. 6 8 9

.

10

11 11 13 14 15 15 15 16 16 17 17 17 18

.

19

20

21 21

22

1

9.

10. Data Transfers

11. External Timing Diagrams

Reset Conditions

9.1

9.2

9.3

10.1

10.2 Normal DMA Mode

10.3 Block Mode DMA

10.4 Pseudo DMA Mode

10.5 Halting a DMA Operation

11.1

11.2

11.3 DMA Write (Non-block Mode) Target 11

11.5 DMA Read (Non-block Mode) Target Receive

11.6 DMA Read (Non-block Mode) Initiator Receive

11.7 DMA Write (Block Mode) Target Send

11.8 DMA Read (Block Mode) Target Receive

11.9 Reset

11.10 Arbitration

Hardware Chip Reset SCSI Bus Reset Received SCSI Bus Reset Issued

Programmed

10.5.1 Using the EOP Signal

10.5.2 Bus Phase Mismatch Interrupt

10.5.3 Resetting the DMA MODE Bit CPU Write

CPU Read

.4

DMA Write (Non-block Mode) Initiator Send

...............................................................

.................................................................

110

..............................................................

.............................................................

..................................................................

..............................................................

....................................................

...............................................

..................................................

Transfers

......................................................

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......................................................

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..................................................

...........................................

Send

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23 23 23 23 24 24 24 24 25 25 25 25 25

26 26 27

28 29 30 31 32 33 33

A

1. A2. A3. A4. NCR

A5. NCR 53C80 A6. A7.

NCR 5380 vs. NCR 5385/86 Flowcharts/Software

65C021nterface

5381

SCSIIPLUS* Register

*SCSIIPLUS is a

Reference

APPENDICES

.....................................................

..........................................................

Diagram

Differential

...................................................................

trademark

.......................................................

Pair

Chart

Option

......................................................

of

..............................................

AMPRO

Computers,

2

Inc.

34 35 50 51 54 56 58

SECTION 1

GENERAL DESCRIPTION

The NCR 5380 SCSI interface device is a 40 pin NMOS device designed to accommodate the Small Computer Systems Interface (SCSI) as defined by the ANSI X3T9.2 committee. The NCR 5380 operates in both the initiator and target roles and can therefore be used in host adapter, host port and formatter designs. This device supports arbitration, including reselection. Special high-current open collector output drivers, capable of sinking 48mA at nection to the supported using a 48 pin version of this part, desig-

nated the

SCSI bus. Differential pair operation is

NCR

5381

SCSI INTERFACE

0.5V, allow for direct con-

(refer to Appendix A4).

* Asynchronous, interface to 1.5 MBPS * Supports initiator and target roles

* Parity generation

wI

optional checking

* Supports arbitration * Direct control of all bus signals * High current outputs drive SCSI bus directly

The

NCR

5380

communicates with the system microprocessor as a peripheral device. The chip is led

by reading and writing several internal registers which mapped

required for DMA transfers because the the necessary handshake signals. The interrupts that requires attention. Normal and block mode DMA is provided to match many A CMOS version is to

may be addressed as standard

1/0.

the

available

Appendix

Minimal

MPU when

of

in

a 44·pin PLCC

AS

for

MPUINTERFACE

processor intervention is

it

detects

popular DMA controllers.

the

NCR 5380,

information

a bus

the

or

a 48·pin DIP. Refer

on

the

control-

or

memory

5380

controls

NCR 5380

condition

NCR S3C80

NCR

S3C80.

* Memory or 110 mapped interface * DMA or programmed

1/0

* Normal or block mode DMA * Optional MPU interrupts

BUS

[EOP

READY ORO DACK

lOR

[CS

AO A1

A2

00

RESET IRQ GNo

DMA

CONTROL

REGISTER lOW

~DORESSING

DATA

FUNCTIONAL PIN GROUPING

SCSI DATA BUS

,

cmo

BSY SEL RST

ATN ACK

REO MSG

C7D

110

VoD

...

NCR 5380

07

...

7,

CONTROLS

OBP

SCSI

PINOUT

I

DO OB7

DBS DB5 OB4 OB3 OB2

OB1

DBO

OBP GNo SEL BSY ACK ATN RST I/O

NCR

5380

c/o

MSG REQ

01 02 03 04 05

D6

07

A2

A1 Voo

AO

JaW

A'ESET

~ ~

READYlOR

IRQ ORO

~

3

SECTION 2

SCSI

BACKGROUND

SCSI evolved from the SASI (Shugart Associates Systems Interface) disk by Shugart Associates in the late 1970's. NCR and Shugart jointly approached the

committee in December committee be formed to develop an face standard based on committee divided into two groups so that

be pursued. Associates presented was agreed that a separate group should develop the standard and the established. This group met in April formally changed the name to the Systems Interface

The proposed standard has since been forwarded from the subcommittee and is becoming a major industry standard. organizations such as ECMA (European Computer

Manufactures Association) and ISO (International Standards Organization) will adopt the proposed standard as

NCR Microelectronics announced the NCR 5385, the first product soon-to-be-announced NCR 5386S. The NCR and 5381 were designed to compliment this initial offering. Differences between the product families are described in Appendix A

This design manual is not an SCSI specification and assumes some prior knowledge of the standard. Copies of the proposed standard may be obtained, with pre-payment of

(Small

SCSI protocol controller, in April of 1983. This

X3

Secretariat, Equipment Manufacturers Association 311 Washington, D.C. 20001

Computer

controller interface standard developed

In

February of 1982, NCR and Shugart

ANSC X3T9.2 subcommittee was

(SCSI).

It is expected that other standards

well.

family

First Street, NW, Suite 500

includes

Systems

of

1981

SASI. The ANSC X3T9.3 sub-

SASI as a working document. It

the

1.

Computer

Interface)

ANSC X3T9.3 suband proposed that a

intelligent inter-

of

that year and

Small Computer

NCR

5386

SCSI proposed

$20, from:

and

SASI could

and the

Business

has

5380

Other documents which may be useful are:

• NCR 5386 SCSI Protocol (MC-704)

NCR 5385E/86 SCSI Protocol

• (MC-903)

Guide

• SCSI

These documents may be obtained by contacting your

local NCR Microelectronics sales representative gional sales office.

Eastern Area

NCR Microelectronics Division 400 Suite Woburn, MA

Phone:

Central Area NCR Microelectronics Division 400 Chisholm Place Suite 100

Plano, TX 75075

Phone:

Western Area

NCR Microelectronics Division 3130 De La Cruz Boulevard

Suite

Santa Clara, CA 95054-2410

Phone: (408) 727-6575

Southwest

NCR

1940 Century Park East

Los Angeles, Phone:

Engineering

W.

Cummings Park

2750

01801

(617)

933-0778

(214)

578-9113

209

Area

Microelectronics

CA

(213)

556-5396

Notebook

90067

Controller

Division

Data Sheet

Controller

User's

or

re-

Please include a self-addressed mailing label.

4

,-

I

ORQ,-

IRQ,

Ready

-

EOP

OACK

-

INTERFACE

-

CPU

----

--

CS, lOR,

lOW

Ao,

AI'

-

A2

--

-

I

00-0

7

I

_J

EOP,ORQ

DMA

control

(Start OMA

send, start

OMA target receive, start OMA initiator

receive)

Parity

checking

Reset parity

or interrupt

register

Arbitration

logic

v

Address

decoding

logic

---+-

--1_

ATN, ACK,

RST

Parity

I

generator

I

-----------1

High-current open-collector output drivers I

MSG,REQ

SCSI

BUS

INTERFACE

--t--

I

OBP

DBo-OB7

- -,

I I

_J

SECTION 4

PIN DESCRIPTION

4.1

Microprocessor Interface Signals

Pin Name AO,

A1, A2

#

30,32,33

Description INPUTS

These signals are used with CS, lOR address

all internal registers.

or

lOW

to

ORa

00

...

07

21

26

22

1,40

27

24

...

34

INPUT Chip Select register selected by low signal.

INPUT DMA Acknowledge resets register for input active

OUTPUT

DMA Request indicates that the data register is ready to be read true in the Command Register.

BI-DIRECTIONAL, TRI-STATE

Microprocessor data bus active high

INPUT

The End

DMA transfer. current byte will be requested.

INPUT

110

Read is used to read an internal register selected

by

CS and Data Register when used with DACK. lOR is active low.

enables a read or write

AO,

A1

and A2. CS is an active

ORa

or

output data transfers. DACK is an

low signal.

or

written.

of

Process signal is used to terminate a

will be transferred but no additional bytes

AO,

ORa

occurs only if DMA mode is

It is cleared by DACK.

If asserted during a DMA cycle, the

A1

and A2. It also selects the Input

of

and selects the data

the internal

6

Pin Name lOW

Pin # Description 29 INPUT

110

Write is used to write an internal register selected

CS and

by Data Register when used with DACK. lOW is active low.

AD,

A 1 and A2. It also selects the Output

IRQ

READY

RESET 28

23

25

OUTPUT Interrupt condition or an event compretion.

OUTPUT Ready can be used to control the speed of block mode DMA transfers. This signal goes active to indicate the chip is ready to mains

until the DMA Mode bit is reset. INPUT

Reset clears all registers. It does not force the SCSI signal signal.

Request alerts a microprocessor of

false after a transfer until the last byte is sent or

RST to the active state. RESET is an active low

Power Signals

Pin Name Pin # Description VDD

GND

31

11

+5

VOLTS

GROUND

sendl

receive data and re-

an

error

7

4.2 SCSI Interface Signals

The

following signals are all bi-directional, active low, open collector signals. With 48 rnA sink

capability,

all pins interface directly with the SCSI bus.

Name

14

15

13

18

17

#

Description

Driven ledgment for a In the target role,

the

Driven

condition. This

This signal indicates that the SCSI bus is being used and can be driven device.

A Data information is on the data bus. This signal is received

110

direction indicates input to the initiator. This to distinguish between phases.

by

an initiator,

REal

REa

signal.

by

an initiator, ATN indicates an attention

signal is received in the target role.

signal driven

is a signal driven

by

the initiator.

of

data movement on the SCSI bus. True

ACK

indicates an acknow-

ACK

data transfer handshake.

ACK

is received

by

both the initiator and the target

the target, CID indicates Control

by

a target which controls the

Selection and Reselection

as

a response to

signal is also used

or

DBO

DBP

...

DB7

19

20

16

9

10

12

...

MSG is a signal driven

sage phase. This

Driven by a target, REal

ACK

data transfer handshake. This signal is

received

The dition.

by

the initiator.

RST

signal indicates an SCSI bus

by

the target during the Mes-

signal is received by the initiator.

REa

indicates a request

RESET

for

con-

a

2

These eight

(DBP) form the bit and has the highest priority during the Arbitration phase. Data parity is odd. Parity is and optionally checked. Parity is not arbitration.

SEL

is used

target to

data

bits (DBO-DB7) plus a parity bit

data

bus. DB7 is the most significant

by

an initiator to select a target

reselect an initiator.

always generated

valid during

or

by

a

8

SECTION 5

ELECTRICAL CHARACTERISTICS

OPERATING CONDITIONS

PARAMETER Supply Voltage

Supply Ambient Temperature

Current

INPUT SIGNAL REQUIREMENTS

PARAMETER High-level, Input VIH

Low-level, Input VIL SCSI BUS

High-level Input Current, IIH Low-level Input

All

other High-level Input Current, IIH Low-level Input Current,

pins 2

pins

.•.

20

Current,

IlL

SYMBOL

VOO

100

TA

CONDITIONS

==

VIH

VIL=

VIH= VIL=

5.25 V

0 Volts

5.25 V

0 Volts

MIN

4.75 0

MIN

2.0

-0.3

MAX UNITS

5.25 145

70

MAX UNITS

5.25 Volts

0.8 Volts

50

-50

10

-10

Volts

mAo

°C

"la.

..Lla.

).la. Jla.

OUTPUT SIGNAL REQUIREMENTS

PARAMETER SCSI BUS

Low-level Output VOL

All

other

High-level Output VOH Low-level

Notice: This Some parametric limits are subject

pins 2

..•

20

pins

Output VOL

PRELIMINARY

is

not a final specification.

CONDITIONS

VOO

= 4.75 V

IOL =

VOO

IOH = -3.0mA.

VOO

IOL = 7.0mA.

to

4B.OmA.

= 4.75 V = 4.75 V

change.,

MIN

2.4

MAX UNITS

0.5 Volts

Volts

0.5

Volts

9

SECTION 6

INTERNAL REGISTERS

6.0 General

The NCR 5380 SCSI Interface Device appears as a set of eight registers to the controlling CPU. By reading and writing the appropriate registers, the initiate any any signal on the implement all software. These registers are read (written) by activating

lOR (lOW) pulse. This section describes the opera-

an tion of the internal registers.

SCSI signal names are used to describe the contents of these internal registers. Even though the bus is

active and a zero inactive state.

Address A2 0

0 0 0 W Output Data

0

1

1 1 1 1 1 1 1

SCSI bus activity or may sample and assert

SCSI bus. This allows the user to

or

portions of the SCSI protocol in

CS with an address on

Iowa

one (1) is used to indicate signal assertion

(0) is used to indicate the non-asserted or

A1

AO

0

0 1 1

0

1

1 0 0 R 0

0

0 1 R Bus and Status

1

0 1

0 0 W

1

1 R Reset Parityl

1

1 W Start DMA Initiator Receive

Register Name

RlW R Current SCSI Data

RlW

Initiator Command

R/W

Mode

RlW

Target Command Current

W Select Enable W Start DMA

R Input Data

Start DMA Target Receive

Register Summary

A2-AO

SCSI Bus Status

Send

Interrupts

CPU may

and then issuing

6.1.1

Current SCSI Data

Register-

Address 0 (Read-only)

The Current SCSI Data Register is a read-only register which allows the microprocessor to read the active SCSI data bus. This is accomplished by activating CS with an address on

pulse. If parity checking is enabled, the SCSI bus parity is checked at the beginning of the read cycle. This

register is used during a programmed during arbitration to check for higher priority arbitrating devices. Parity is not guaranteed tion.

Current SCSI Data Register

7

6

A2-AO

5 4

of 000 and issuing an lOR

110

data read or

valid during arbitra-

3

2

o

I I I I I I I I I

DB7

DB6

DB5 DB4

6.1.2 Output Data

Address 0 (write-only)

The Output Data Register is a write-only register that is used

to

send accomplished by either using a normal MPU write, or under DMA control, by using register is also used to assert the proper SCSI bus during the arbitration and selection phases.

data

Output Data Register

DB3··

Register-

to

the

SCSI

lOW and DACK. This

DB2

bus.

I D bits or the

DB1

This

DBO

is

6.1

Data Registers

The data registers are used to transfer SCSI commands, data, status, and message bytes between the microprocessor data bus and the 5380

does not interpret any information that passes through the data registers. The data registers consist of the transparent Current Output Data Register, and the

SCSI bus. The NCR

SCSI Data Register, the

Input Data Register.

7

6

4

5

3

2

1

I I I I I I I I I

DB7

DB6 DB5

10

DB4

DB3

DB2

DB1

o

DBO

6.1.3 Input Data Address 6 (Read-only)

Register-

6.2 Initiator Command Address 1 (Read/Write)

Register-

The Input Data Register is a read-only register that is used to read latched either during a DMA Target receive operation when

ACK (pin 14) goes active itiator receive when REO (pin 20) goes active. The DMA Mode bit (port can be may be read under DMA

Parity is

gister is

7

I I I

L-

-L--OB-6----1--0-B-5-L--O-B-4

O-B-7

latched data from the SCSI bus. Data is

or

during a DMA In-

2,

bit 1) must be set

latched in the Input Data Register. This register

control using lOR and DACK.

optionally checked when the Input Data Re-

loaded.

Input

Data

Register

6 5

4

II

3

I I I I

--I.-=O=B3---l...--=OB=2-L---=O=B=1--'--=O=BO=-'

be~ore

2 o

data

The Initiator Command Register is a read/write register which is used to assert certain

monitor those signals, and to monitor the progress of bus arbitration. Many of these bits are significant when being used as an Initiator; however, most can be used during Target

Initiator

7 6

role operation.

Command

(Register

543

SCSI bus signals, to

only

Register

Read)

2 1 0

I I I I I I I I I

A~~~RT

AlP

7 6 5 4 3 2 0

LA

Initiator

(Register

A~~KRT

A~~T

Command

AS::LRT

Register

Write)

A~~RT

A~Jr

I I I I I I I I I

ASSERT TEST

RST

MOOE

OIFF

ASSERT ASSERT ASSERT ASSERT ASSERT

ENBL

ACK

BSY SEL

ATN

OATA

BUS

11

The following describes the operation of all bits Initiator Command Register.

BIT

7-ASSERT

Whenever a one Command Register, the RST signal (pin 16) is asserted on the asserted until this bit is reset or until RESET (pin 28) occurs. After this bit is set (1), IRQ (pin

23) goes active and ters are reset (except for the interrupt latch and the ASSERT RST bit). Writing a zero (0) to bit 7 of the Initiator Command Register de-asserts the RST signal. Reading this register simply reflects the status of this bit.

BIT

6-AIP

This bit

For this bit to be active, the

0) bus free condition has been detected and that the chip has asserted Output Data Register (port will remain active until the

is

used to determine if arbitration is

must have been set previously.

RST

(1)

is written to bit 7 of the Initiator

SCSI bus. The RST signal will remain

all internal logic and control regis-

(Arbitration in

BSY (pin 13) and the contents of the

Progress-read

ARBITRATE bit (port

It

indicates that a

0)

onto the SCSI bus. AlP

ARBITRATE bit is reset.

an

external

in

progress.

in

bit)

2,

the

bit

BIT 6-TEST MODE (write bit)

This bit may be written during a test environment to disable NCR 5380 from the circuit. Resetting this bit returns the part to normal operation.

BIT

This bit, when active, indicates that the NCR 5380 detected a bus free condition, arbitrated for use of the

bus by asserting bus and lost arbitration due to SEL (pin 12) being asserted by another bus device. For this bit to be active the

BIT

This bit meaningful supports external differential pair transceivers. ENBL should only be asserted if the device is physically connected enabled, the signal TGS (pin serted if the TARGETMODE bit (port orthe TARGETMODE bit

all output drivers, effectively removing the

5-LA

ARBITRATE bit (port

5-DIFF

(Lost

Arbitration-read

BSY (pin 13) and its

ENBL (Differential

is

not used in

the NCR 5381, a 48 pin device which

as

signallGS (pin

bit)

ID

on

2,

bit

0)

must be active.

Enable-write

in

the NCR 5380 and

either an Initiator or as a Target. If

12-NCR

is

reset (0).

14-NCR

5381)

5381) is as-

2,

bit

6)

is

asserted if the

the

dat~

bit)

is

only

DIFF

is set

(1)

BIT

4-ASSERT

This bit

14) on the TARGETMODE bit (port a zero to this bit resets ACK this register simply reflects the status of this bit.

BIT

Writing a one

13) onto the the selection or reselection and resetting this bit creates a

bus disconnect condition. Reading this register simply reflects the status of this bit.

BIT

Writing a one

12) onto the

arbitration has been be de-asserted by resetting this bit to a zero. A read of this register simply reflects the status of this bit.

BIT

ATN (pin 15) may be asserted on the SCSI bus by setting this bit

(port initiator to request a Message that since

same register, a select with ATN may be implemented with one MPU write. ATN may be de-asserted by re-

setting this bit to a zero (0). A read of this register

simply reflects the status of this bit.

BIT

The ASSERT DATA BUS bit, when set, allows the contents of the chip outputs generated and asserted on DBP. bit asserts the DBEN signal (pin 36). Resetting disables the output data bus or the DBEN signal.

When connected as enabled if the TARGETMODE bit (port the received signal signals ASSERT the Target Command Register.

This

operations.

is

used by the bus initiator to assert ACK (pin

3-ASSERT

BSY signal. Asserting BSY indicates a successful

2-ASSERT

1-ASSERT

2,

bit

6)

ASSERT SEL and ASSERT ATN are

O-ASSERT

(CI

D,

C/D,

bit

should

ACK

SCSI bus.

In

order to assert ACK the

2,

bit

6)

must be false. Writing

on

the SCSI bus. Reading

BSY

(1)

into this bit position asserts BSY (pin

SCSI bus. Conversely, a zero

(0)

resets

SEL

(1)

into this bit position asserts SEL (pin

SCSI bus. SEL is normally asserted after

successfully completed. SEL may

ATN

to

a one

(1)

if the TARGETMODE bit

is

false. ATN

is

normally asserted by the

Out bus phase. Note

in

the

DATA BUS

Output Data Register to be enabled as

on

the signals

an

II 0 (pin 17) is false, and the phase

1/0, and MSG) match the contents of the

ASSERT

also

DBO-DB7.

In

Initiator, the outputs are only

110,

and ASSERT

be

set

the NCR

2,

during

Parity is also

5381

this

this bit

bit

6)

is

false,

MSG

in

DMA

send

12

6.3 Mode Register-Address 2 (Read/Write)

The Mode Register is used the chip. This register determines whether the NCR 5380 operates as an initiator or a target, whether DMA transfers are being used, whether parity and whether interrupts are generated on various external conditions. This register may be read to check the

value of these internal control bits. The following

describes the operation of these control bits.

Mode Register

7 6 5 4 3 2

to

control the operation of

is

checked,

0

BIT

4-ENABLE

The ENABLE PARITY INTERRUPT bit, when set (1), will cause an interrupt detected. A parity interrupt will ENABLE enabled

BIT

The ENABLE EOP INTERRUPT, when set (1), causes an interrupt to occur when signal (pin 27) is received from the DMA controller logic.

BIT

PARITY CHECKING bit (bit 5) is also

(1).

3-ENABLE

2-MONITOR

PARITY INTERRUPT

(IRQ) to occur if a parity error is

only be generated if the

EOP INTERRUPT

an

EOP (End of Process)

BUSY

I I I I I I I I ]

BLOCK TARGET ENABLE ENABLE ENABLE MONITOR DMA ARBI-

MODE MODE PARITY PARITY

DMA CHECK-

BIT

7-BLOCK

The

BLOCK characteristics of the DMA DRQ-DACK handshake. When this bit is reset (0) and the DMA active (1), the DMA handshake uses the interlocked handshake and the rising edge of DACK (pin 26)

transferred.

DMA bit set lOR (pin 24) or lOW (pin 29) signifies the end of each byte transferred and DACK

throughout the DMA operation. READY (pin 25) can then

BIT

The TARGETMODE bit allows the NCR 5380 to operate

an

as signals ATN (pin 15) and ACK (pin 14) to be asserted on

the SCSI bus, the T ARGETMODE bit must be reset (0). be

asserted on the SCSI bus, the TARGETMODE bit

must be set (1).

indicates

In

(1)

be

used to request the next transfer.

6-TARGETMODE

as

either an SCSI bus initiator, bit reset (0), or

SCS I bus target device, bit set

In

order for the signals

INTER- INTER-

ING

RUPT RUPT

MODE DMA

MODE

the

block mode operation, BLOCK MODE

and DMA MODE bit set (1), the end of

EOP

BUSY MODE TRATE

DMA

end

CI

bit

controls

MODE bit is

of

each

byte

is

allowed to remain active

(1

).

I n order for the

0,

1/0, MSG and REQ to

the

normal

being

The MONITOR BUSY bit, when true (1), causes interrupt to be generated for BSY (pin 13). When the interrupt loss of BSY, the lower 6 bits of the Initiator Command Register are reset

SCSI bus.

the

(0)

and all signals are removed from

an

unexpected loss of is

generated due to

an

BIT

5-ENABLE

The ENABLE PARITY CHECKING bit determines whether parity errors parity error ignored. Conversely, if this bit be saved.

PARITY CHECKING

will be ignored or saved

latch.

If

this bit

is

reset (0), parity will be

is

set

(1)

parity errors will

in

the

13

BIT

1-DMA

The DMA MODE bit is normally used to enable a DMA transfer and must be set (1) prior to writing ports 5 through transfers. The TARGETMODE bit (port be consistent with writes to port 6 and 7 [i.e. set a write to port 6 and reset control bit true (1) for

REa

(pin 20) and ACK (pin 14) are automatically con-

trolled. The DMA

EOP signal. Any DMA transfer may be stopped by writing a zero into this bit location, however care must be taken not to cause simultaneously.

BSY

Note: Mode bit.

BIT

O-ARBITRATE

The ARBITRATE bit is set (1) to start the arbitration process. Prior to setting this bit the Register should contain the proper value. Only one data bit should be active for SCSI bus arbitration. The NCR condition before entering the arbitration phase. The results of the arbitration phase may be determined by reading the status bits LA and respectively) .

MODE

7.

Ports 5 through 7 are used to start DMA

2,

bit

6)

must

(1)

(0) for a write to port

ASSERT DATA BUS (port

all DMA send operations.

MODE bit is not reset upon the receipt of an

CS and DACK to be active

must be active in order to set the DMA

5380 will wait for a bus free

1,

In

the DMA mode,

SCSI device ID

AlP (port

7].

bit 0) must be

Output Data

1,

bits 5 & 6

for

The

6.4 Target Command

Register-

Address 3 (Read/Write)

When connected as a target device, the Target Command Register allows the MPU to control the

information transfer phase

20) simply by writing this register. The TARGETMODE 2,

bit

6)

bit (port occur. The following table.

SCSI

Bus Phase

Data Out Unspecified Command Message Out Data

In

Unspecified Status 1 Message

When connected as an Initiator with DMA Mode true, if the phase

phase bits in the Target Command Register, a phase mismatch interrupt is generated when goes active.

ASSERT 1/0, ASSERT C/D, and ASSERT MSG bits

must match the corresponding bits Bus Status Register (port 4). The ASSERT

3) has no meaning when operating as an

must be true (1) for bus assertion to

SCSI bus phases are described

Information

In

lines (1/0, CI

In

order to send data as an Initiator, the

andlor

Transfer

to assert

ASSERT ASSERT ASSERT

1/0

0 0 0 0 0 0 0

1

D,

and MSG) do not match the

in

the Current SCSI

SCSI bus REa

Phases

C/D

0

1

0 0 0

REa

Initiator.

(pin

in

the

MSG

1

0

(pin 20)

bit (bit

7

Target

6 5

Command

4

3

Register

2 o

I I I I I I I I I

LAST X X X ASSERT ASSERT ASSERT BYTE REO MSG C/O /I 0

SENT (53C80)

The

NCR

53C80

when the

SCSI bus. This flag DMA when

14

last

bit

in the Bus and Status Register

the

last

uses bit 7

byte

of

this register

of a DMA

is

was

transfer

necessary since

received from the DMA.

to

detennine

is

sent the

only

End

reflects

ASSERT

to

the

of

6.5 Current SCSI Register-Address

Bus

Status

4 (Read-only)

6.7 Bus and Status (Read-only)

Register-Address

5

The Current SCSI Bus Status register is a read-only register which is used to monitor seven control signals plus the data bus parity bit. For example, an mine the current bus phase and to poll REQ for pending data transfers. This register may also be used to determine why a particular interrupt occurred. The following describes the ter.

.----------.-7

I I

L-_--L-_--'--_--'-

6.6 Select Enable

Initiator device can use this register to deter-

Current SCSI Bus Status Regis-

Current

--.--6 5 --,--4...,-------,--3

SCSI

Bus

I I I

__

~_-----'--_--'--_--'

Status Register

--r--2

I

Register-Address

SCSI bus

-,------,0

I I I

_

___'

DBP QUEST

4

(Write-only)

The Select Enable Register is a write-only register

10

which is used as a mask to monitor a single selection attempt. The simultaneous occurrence of the

10

correct interrupt. This interrupt can be disabled by resetting all bits

ING

during selection.

7

bit, BSY false, and SEL true will cause an

in

this register. If the ENABLE PARITY CHECK-

bit (port

2,

bit

5)

is active (1), parity will be checked

Select Enable Register

6

5

4

3

2

during a

o

The Bus and Status Register is a read-only register which can be used to monitor the remaining

control signals not found in the Current SCSI Bus Status Register (A TN & ACK) as well as six status bits. The following describes each bit of the Bus

Status Register individually.

and

Bus

and

7 6 5

Status

4 3

Register

2 o

SCSI

o~her

I I I I I I I I I

END

DMA

OF

DMA

BIT

7-END

The END OF DMA TRANSFER bit is set if EOP (pin

DACK (pin 26), and either lOR (pin 24),

27),

(pin 29) are simultaneously active for at least 100 nsec. Since the EOP signal can occur during the last byte sent to the Output Data Register (port ACK signals should be monitored to insure that the last

byte has been transferred. This bit is reset when the

MODE bit is reset (0) in the Mode Register (port

DMA

2).

The NCR 53C80 bit

(last byte sent) in

Register.

BIT

6-DMA

PARITY INTER- PHASE BUSY

RE-

ERROR RUPT MATCH ERROR

QUEST

OF DMA TRANSFER

REQUEST

RE-

ACTIVE

contains

bit 7 of

a true End

the Target Command

ATN

ACK

or

lOW

0), the REQ and

of

DMA Status

I I I

II

I I I I

The DMA REQUEST bit allows the MPU to sample the output pin ORQ (pin 22). DRQ can be cleared by asserting

MODE bit (bit 1) in the Mode Register (port 2). The DRQ signal does not reset when a phase mismatch

interrupt occurs.

15

OACK (pin 26)

or

by resetting the DMA

BIT

5-PARITY

ERROR

BIT

1-ATN

This bit is set if a parity error occurs during a data receive or a device can

only be set (1) if the ENABLE PARITY CHECK bit

2,

bit

(port reading the Reset Parity/

BIT

This bit is set if an enabled interrupt condition occurs. reflects the current state of the IRQ (pin 23) output and can be cleared by reading the Reset Parity/

Register (port 7).

BIT

The SCSI signals MSG,

17) represent the current information transfer phase. The PHASE MATCH bit indicates whether the current SCSI bus phase matches the lower 3 bits of the Target Command Register. PHASE MATCH is

updated and is only significant when operating as a bus initiator. A Phase Match is required for data transfers to occur on the

BIT

The BUSY ERROR bit is active if of the BSYsignal (pin sitive latch is set whenever the MONITOR BUSY bit (port loss of BSY will disable any SCSI outputs and will reset the DMA MODE bit (port

5)

4-INTERRUPT

3-PHASE

2-BUSY

2,

bit

2)

selection. The PARITY ERROR bit

is active (1). This bit may be cleared by

Interrupt Register (port 7).

REQUEST ACTIVE

Interrupt

MATCH

C/D,

and

I/O

(pins 19,18, and

continuously

SCSI bus.

ERROR

an

unexpected loss

13)

has occurred. This level-sen-

is true and BSY is false.

2,

bit

An

unexpected

1).

This bit reflects the condition of the SCSI bus control

ATN (pin 15). This signal is normally monitored

signal by the target device.

BITO-ACK

This bit reflects the condition of the SCSI bus signal ACK (pin 14). This Signal is normally monitored

It

by the target device.

contr01

6.8 DMA Registers

Three write-only registers are used to initiate all DMA activity. They are Start DMA Send (port 5), Start DMA Target Receive (port ceive (port 7). DMA transfers. Data presented to the Signals and has no effect on the operation. Prior to writing these registers the

MODE bit (bit

DMA

6)

in the Mode Register (port set. The individual registers are briefly described below.

6.8.1

Start DMA

Simply writing these registers starts the

DO-D7

during the register write is meaningless

6)

and Start DMA Initiator Re-

NCR 5380 on

BLOCK MODE DMA bit (bit 7), the

1)

and the TARGETMODE bit (bit

2)

must be appropriately

Send-Address

5

(Write-only)

This register is written to initiate a DMA send, from the DMA to the operations. The DMA MODE bit (port set prior to writing this register.

SCSI bus, for either initiator or target role

2,

bit

1)

must be

16

6.8.2 Start DMA Target

Receive-Address

6 (Write-only)

This register is written to initiate a DMA receive, from

the

SCSI bus to the DMA, for target operation only. The

DMA

MODE bit (bit

6)

in

the Mode Register (port

prior to writing this register.

1)

and the TARGETMODE bit (bit

2)

must both be set (1)

6.8.3 Start DMA Initiator

Receive-Address

This register is written to initiate a DMA receive, from the

SCSI bus to the DMA, for initiator operation only. The DMA MODE bit (bit 1) must be true (1) and the TARGETMODE bit (bit

Register (port 2) prior to writing this register.

6)

7 (Write-only)

must be false (0)

in

the Mode

6.9 Reset Parity I

Interrupt-Address

7

(Read-only)

Reading this register resets the PARITY ERROR bit (bit 5), the BUSY ERROR bit (bit (port 5).

INTERRUPT REQUEST bit (bit 4) and the

2)

in

the Bus and Status Register

17

SECTION 7

ON-CHIP SCSI HARDWARE SUPPORT

The NCR 5380 architecture. The chip allows direct control and monitoring of the

signal. However, portions of the protocol define

each timings which are much too quick for roprocessors to has been provided for DMA transfers, bus arbitration, phase change monitoring, bus disconnection, bus reset, parity generation, parity checking, and device selection/ reselection.

Arbitration is accomplished using a bus-free continuously monitor

least 400 nsec then the SCSI bus is considered free

at

is

easy to use because of its simple

SCSI bus by providing a latch for

traditional mic-

control. Therefore, hardware support

filter to

BSY. If BSY remains inactive for

and arbitration may begin. Arbitration will begin if the bus

is

free, SEL

(port

2,

bit (BSY asserted), an arbitration delay of 2.2 elapse before the data bus can be examined to determine if arbitration has been won. This implemented

The

NCR 5380 is a clockless device. Delays such as bus free implemented using gate delays. These delays may differ between devices because of inherent process variations, but are ANSI X3T9.2 specification (Revision

delay,

is

inactive and the ARBITRATION bit

0)

is

active. Once arbitration has begun

/Lsec

delay must be

in

the controlling software driver.

bus set delay and bus settle delay are

well within the proposed

17).

must

18

SECTION 8

INTERRUPTS

The NCR 5380 provides an interrupt output (IRQ) to indicate a task

completion

ence. The use of interrupts is

or

an abnormal bus occurr-

optional and may be disabled by resetting the appropriate bits in the Mode Register (port 2) or the

When an interrupt occurs, the Bus and and the Current

Select Enable Register (port 4).

Statu~

Register

SCSI Bus Status Register must be read to determine which condition created the interrupt. IRQ (pin 23) can be reset simply by reading the Reset or

Parityl

Interrupt

Register

(port

7)

by an external chip reset (RESET active for 200

nsec).

Assuming the NCR an interrupt will be generated if the chip is selected

5380 has been properly initialized,

or reselected, if an EOP signal occurs during a DMA transfer, if an

SCSI bus reset occurs, if a parity error occurs during a data transfer, if a bus phase mismatch occurs,

8.1

or

if an SCSI bus disconnection occurs.

Selection/ Reselection

The NCR 5380 can generate a select interrupt if SEL

(pin 12) is true (1), its device

false for at least a bus settle delay (400 ns). If

13) is

ID

is true (1) and BSY (pin

1/0

(pin 17) is active this should be considered a reselect

interrupt. The correct ID bit is determined

by

a match

in

the Select Enable Register (port 4). Only a single bit

match is required to generate an interrupt. This interrupt may be

disabled by writing zeros into all bits of the

Select Enable Register.

If parity is supported, parity should also be good during the

selection phase. Therefore, if the ENABLE PARITY BIT (port 2, bit 5) is active, then the PARITY ERROR bit should be checked to insure that a proper selection

has

occurred.

The

ENABLE

PARITY INTERRUPT bit need not be set for this interrupt to be generated.

The proposed more than two device

SCSI specification also requires that no

IDs be active during the selection process. To insure this, the Current SCSI Data Register (port

0) should be read.

The proper values for the Bus and Status Register (port 5) and the Current (port 4) are

displayed below.

SCSI Bus Status Register

Bus and Status Register

7

6 5

END

DMA

OF

DMA QEST

RE-

4

PARTlY INTER- PHASE BUSY ERROR RUPT MATCH ERROR

RE-

QUEST

ACTIVE

2

3

1

o

ATN ACK

Current SCSI Bus Status Register

7 6 5

4

3

2

0

19

8.2 End

of

Process (EOP) Interrupt

An End of Process signal (EOP, pin 27) which occurs during a DMA transfer (DMAMODE true) will set the

OF

END generate an interrupt if ENABLE EOP INTERRUPT bit (port nized (END either

DMA status bit (port

2,

bit 3) is true. The EOP pulse will not be recog-

OF

DMA bit set) unless EOP, DACK and

lOR

or

lOW

are concurrently active for at least

100 nsec. DMA transfers can still occur if

not asserted at the correct time. This interrupt can be disabled by resetting the ENABLE bit.

The proper values for the Bus and Status Register

5)

(port (port 4) for this interrupt are displayed below.

and the Current SCSI Bus Status Register

5,

bit

7)

and will optionally

EOP INTERRUPT

EOP/

was

Bus and Status Register

7

6

END DMA PARITY INTER- PHASE BUSY

OF

RE-

DMA QUEST

ERROR RUPT MATCH ERROR

4

5

RE-

QUEST

ACTIVE

3

2

o

The END block transfer is complete. Receive operations are

complete when there is no data left in the chip and no additional handshakes occurring. The only exception to this is receiving data as an initiator and the target

opts to send additional data for the same phase.

case, REO goes active and the new data is present in

the

rupt will not occur, REO and

to determine that the Target is attempting to send more

data.

For send operations, the END

the DMA finishes its transfer, but the

may still be in progress.

and

connected as an Initiator, a phase change interrupt

can be used to signal the completion of the previous

phase. data for the same phase. will not occur and both REO and to determine when the last byte was transferred.

If using the NCR Target Command Register) may be determine when the

OF

DMA bit is used to determine when a

In

this

Input Data Register. Since a phase mismatch inter-

ACK need to be sampled

OF

DMA bit is set when

SCSI transfer

If connected as a Target, REO

ACK should be sampled until both are false. If

It is possible

forthe

Target to request additional

In this case, a phase change

ACK must be sampled

53C80,

Last Byte Sent (bit 7

of

the

sampled to

last byte has been transferred.

Current SCSI Bus Status Register

7

6

4

5

3 2

o

20

8.3 SCSI Bus Reset

8.4 Parity Error

The NCR 5380 generates an interrupt when the RST signal (pin 16) transitions to true. The device releases all bus signals within a bus clear delay this transition. This interrupt also occurs after setting the

ASSERT RST bit (port

cannot be disabled. (Note: The

in

latched and may not be active when this port is read. For this case, the Bus Reset interrupt may be determined by default.)

The proper values for the Bus and (port 5) and the Current (port 4) are displayed below.

bit 7 of the Current SCS I Bus Status Register

1,

bit 7). This interrupt

SCSI Bus Status Register

(800 nsec) of

RST signal is not

Status Register

Bus and Status Register

7

6 5

0

\ol

END

DMA PARITY INTER- PHASE BUSY

RE-

OF

DMA

QUEST

4

0

I

I I

ERROR RUPT MATCH ERROR

RE-

QUEST

ACTIVE

3

X

I

2

1

0

I

ATN

ACK

An interrupt is generated for a received parity error if the ENABLE

PARITY INTERRUPT (bit Mode Register (port 2). Parity is checked during a read

of the Current

DMA receive operation. A parity error can be detected without generating an interrupt by disabling the ENA-

PARITY INTERRUPT bit and checking the PAR-

BLE ITY ERROR flag (port

The proper values for the Bus and (port 5) and the Current

4)

(port

PARITY CHECK (bit

SCSI Data Register (port 0) and during a

5,

bit 5).

SCSI Bus Status Register

are displayed below.

5)

and the ENABLE

4)

bits are set (1) in the

Status Register

Bus and Status Register

7

6 5

X

I

I 0 I

END

OF

DMA QUEST

I

DMA PARITY INTER-

RE-

ERROR RUPT

4

1

I

ACTIVE

PHASE MATCH

RE-

QUEST

2

3

1

I 0 I X I

BUSY

ERROR

1 0

ATN

X

I

ACK

Current SCSI Bus Status Register

7

6 5

RST BSY

REQ

4

MSG

3

CI

D 110 SEL

Current SCSI Bus Status Register

2

0

DBP

7

6 5

RST BSY

REQ

4

MSG

3

CI

2

D

110

BEL

0

DBP

21

8.5 Bus Phase Mismatch

8.6 Loss of BSY

The SCSI phase lines are comprised of the signals

1/0, CIO and MSG. These signals are compared with

the corresponding bits in the Target Command Register: ASSERT MSG (bit 2). The comparison occurs continually and is reflected in the PHASE MATCH bit (bit 3) of

MODE occurs when true, an interrupt

A phase mismatch prevents the recognition of REO and removes the chip from the bus during an initiator send operation.

even though the

is active.) This interrupt is only significant when con-

nected as an

the

rupt to occur when connected as a Target if another

device is driving the phase

The proper values for the Bus and Status Register

(port

ASSERT

1/0

(bit 0), ASSERT CIO (bit

1)

the Bus and Status Register (port 5). If the OMA

bit (port

2,

bit 1) is active and a phase mismatch

REO (pin 20) transitions from false to

(IRQ) is generated.

(OBO-OB7, OBP will not be driven

ASSERT DATA BUS bit (port

1,

Initiator and may be disabled by resetting

OMA MODE bit. (Note: It is possible for this inter-

lines to a different state.)

5)

and the Current SCSI Bus Status Register

(port 4) are displayed below.

and

bit 0)

If the MONITOR BUSY bit (bit 2)

in

the Mode Register (port 2) is active, an interrupt will be generated if the BSY

signal (pin 13) goes false for at least a bus settle delay (400 nsec). This interrupt may be disabled by resetting the

MONITOR BUSY bit. Register values are

as follows.

Bus and Status Register

7

END

OF

DMA

4

5

6

DMA

PARITY INTER- PHASE BUSY

RE-

ERROR

QUEST

RUPT MATCH ERROR

RE-

QUEST

ACTIVE

3

2 1

ATN

o

ACK

Current SCSI Bus Status Register

7

6

4

5

2

3

o

END

OF

DMA

7

Bus and Status Register

DMA

PARITY INTER- PHASE BUSY

RE-

ERROR

QUEST

RUPT MATCH ERROR

RE-

QUEST

ACTIVE

Current SCSI Bus Status Register

6 5

4

3 2 o

ATN

ACK

22

SECTION 9

RESET CONDITIONS

Three possible reset situations exist with the NCR 5380,

as follows:

9.1

Hardware Chip Reset

When the signal RESET / (pin 28) is active for at least 200 nsec, the NCR 5380 device is re-initialized and all internal logic and control registers are cleared. This is a chip reset only and does not create an reset condition.

9.2 SCSI

When an SCSI RST signal (pin 16) is received, an IRQ interrupt is generated and a chip reset is performed. All internal logic and registers are cleared, except for the IRQ interrupt latch and the ASSERT RST bit (bit

Bus

Reset (RST) Received

SCSI bus

7)

in

the

Initiator Command Register (port 1). (Note: The RST signal may be sampled by reading the Current SCSI Bus Status Register (port 4); however, this signal is not latched and may not be present when this port is read.)

9.3 SCSI Bus Reset (RST) Issued

If the CPU sets the ASSERT RST bit (bit 7) in the Initiator Command Register (port 1), the RST signal (pin 16) goes active on the reset is performed. Again, all internal logic and registers are cleared except for the

ASSERT RST bit (bit

the Register (port 1). The active until the hardware reset occurs.

ASSERT RST bit is reset or until a

SCSI bus and an internal

IRQ interrupt latch and

7)

in the Initiator Command

RST signal will continue to be

23

SECTION 10

DATA TRANSFERS

Data may be transferred between SCSI bus devices in one of four modes: Programmed Block Mode OMA; or Pseudo tions describe these modes in transfers operations active simultaneously.)

10.1

Programmed 110 Transfers

Programmed

transfer. The

shake signals are by reading and writing the appropriate register bits.

This type of transfer is

small blocks of data such as command blocks or message and status bytes.

Initiator send operation would begin by setting the

An

CIO, 1/0, and MSG bits in the Target Command Re-

gisterto the correct state so that a phase match exists. In

addition to the phase match condition, it is necessary for the true and the received to send data.

For each transfer, the data is loaded into the Data Register (port 0). The MPU then waits for the

REO bit (port goes active the PHASE MATCH bit (port checked and the

REO bit is sampled until it becomes false and the

The

MPU resets the transfer.

REO (pin 20) and ACK (pin 14) hand-

ASSERT DATA BUS bit (port

OACK and CS should never be

110

is the most primitive form of data

individually monitored and asserted

normally used when transferring

110

signal to be false for the 5380

4,

bit

5)

to become active. Once REO

ASSERT ACK bit (port

ASSERT ACK bit to complete the

1/0;

Normal OMA;

OMA.

The following sec-

detail. (Note: For all data

1,

bit

0)

to be

Output

5,

bit 3) is

1,

bit 4) is set.

10.2 Normal DMA Mode

10.3 Block Mode DMA

Block Mode allows an external OMA device (Intel 8237 -type DMA) to perform sequential DMA transfer without relinquishing the data bus to the CPU. Holding DACK active prevents access to the system bus. The handshake itself does not increase the transfer rate. Preventing the CPU from sharing the system bus increases the fer rate but also halts the CPU operation.

Block Mode DMA transfers are supported for both Initiator and Target Role operation. When using this mode

of

operation, DRO is asserted

beginning

DACK is asserted and remains asserted throughout the transfer. READY goes active after the pulse goes inactive, effectively replacing the signal.

Care must be taken when using this mode due to the

operation of match interrupt occurs, READY will remain in the inactive state and tNT DMA chip must return control of the bus to the CPU so that the also does not return to the active state when pulse is received. Therefore, you might want to use EOP to insure that the CPU regains bus control after the last DMA byte has been transferred. As non-block DMA mode, the sert ACK a DMA send operation, either an additional byte of data must be written to the NCR to go inactive, or the CPU must reset the DMA Mode bit in the Mode Register.

of

the DMA transfer.

READY.

5380 interrupt can

on

the SCSI bus.

Intel-type CPUs from gaining

OMA trans-

to

signal

In

response

lOW

If,

for example, a phase mis-

will be active. For this condition the

be

serviced. READY

EOP signal does not deas-

To

successfully complete

5380 to allow ACK

to

an

the

DRO,

or

lOR

ORO

EOP

in

the

DMA transfers are normally used for large block

transfers. The

- pin 22) whenever it is ready for a byte transfer. External DMA logic uses this and an lOR or an lOW pulse to the NCR 5380. ORO goes inactive when DACK is asserted and DACK goes inactive sometime after the minimum read or write

pulse width. This process is repeated for every byte. For this unless a transfer is taking place.

Refer to

transfer.

SCSI chip outputs a DMA request (DRO

DRO signal to generate OACK

mode, DACK should not be allowed to cycle

Section 10.5 for information on halting a DMA

Non-block mode DMA transfers end when DACK goes false, whereas block mode transfers end when or lOW becomes inactive after each byte. Since this is the case, DMA transfers may be started sooner a block mode transfer.

To obtain optimum performance in block mode operation, the DMA logic may optionally use the normal DMA mode interlocking handshake. READY is still available to throttle the DMA transfer, but

faster than READY and may be used to start the cycle

sooner.

24

DRO is 30 to 40 nsec

lOR

in

The methods described

DMA Operation"

apply for all DMA operations.

in

Section 10.5 "Halting A

1 0.4 Pseudo DMA Mode

To avoid the tedium of monitoring and asserting the

requestl

grammed 110 transfers, the system may be designed to plemented in

DMA handshake. polling the DMA REO bit (bit Register (port external port or by using it to generate rupt. DMA port read or write data transfer. This MPU readl write is DACK and lOR or lOW signals.

Often, external decoding logic ate the used to generate provide an increased performance transfers.

acknowledge handshake signals for pro-

implement a pseudo DMA mode. This mode

by programming the NCR 5380 to operate

the DMA mode, but using the MPU to emulate the

ORO

(pin 22) may be detected by

6)

in

the Bus and Status

5),

by sampling the signal through

an

Once

ORO

is

detected, the MPU can perform a

externally decoded

NCR 5380 CS signal. This same logic may be

DACK at no extra system cost and

to

generate the appropriate

is

necessary to gener-

in

programmed

is

im-

an

MPU inter-

10

10.5 Halting A DMA Operation

The EOP signal

transfer. A bus phase mismatch or a reset of the DMA

MODE bit (port

for the current bus phase.

is

not the only way

2,

bit

1)

can also terminate a DMA cycle

to

halt a DMA

counter and frees the DMA logic from providing the

EOP signal. If performing

NCR 5380 requires DACK to cycle before ACK

the goes inactive. Since phase changes cannot occur if ACK is active, either DACK must be cycled after the

last byte is sent or the DMA MODE bit must be reset in order to receive the phase mismatch interrupt.

an

initiator send operation,

10.5.3 Resetting the DMA MODE Bit

A DMA operation may be halted at any time simply by resetting the DMA the DMA bus phase mismatch interrupt. The DMA must then be set before writing any of the start DMA registers for subsequent bus phases.

If

resetting the DMA MODE bit

for Target role operation, then care must be taken to

reset this bit at the proper time. target device, the DMA the to prevent an ting this bit causes

last byte received remains

and may be obtained either by performing a

MPU read or by cycling DACK and lOR.

EOP

device.

MODE bit be reset after receiving

last DRO is received and before DACK is asserted

is

easier to use when operating as a Target

MODE bit.

additional REO from occurring. Reset-

DRO to go inactive. However, the

It

is

recommended that

an

EOP or

MODE bit

is

used instead of EOP

If

receiving data as a

MODE bit must be reset once

in

the Input Data Register

normal

In

most cases

10.5.1 Using the EOP Signal

If EOP is used, it should be asserted for at least 100 nsec while DACK and lOR or lOW are simultaneously active. Note, however, that if lOR or lOW is not active an

interrupt will be generated, but the DMA activity will

continue. The

MODE bit. Since the EOP signal can occur during the last byte sent to the Output Data Register (port

REO and ACK signals should be monitored to insure that the

EOP signal does not reset the DMA

last byte has transferred.

0),

the

10.5.2 Bus Phase Mismatch Interrupt

A bus phase mismatch interrupt may be used to halt

the transfer if operating as

method frees the host from maintaining a data

an

Initiator. Using this

length

25

11.1 CPU WRITE

AO

..

2

DO

..

7

NAME DESCRIPTION MIN. TYP. MAX. UNITS T1 T2 T3 T4 T5 T6

SECTION

11

EXTERNAL TIMING DIAGRAMS

11111~~"

___

T_1

__

~~~

______

l-=

~~~_T_2

T3

,

f4=

T5

~

mOI1ll171ZZWIX'-

Address setup to write enable *

Address hold from end write enable

Write enable width * 70

Chip select hold from end of lOW 0 Data setup to end of write enable Data hold time from end of

_______

lOW

T6--.f

*

__

~777777777777711

-Jx7777701777177

20 20

50 30

ns. ns. ns. ns. ns. ns.

* Write enable

11.2 CPU READ

AO

..

DO

..

NAME T1 T2 T3 T4 T5

is

the occurrence of lOW and CS

2

7770lX

14=

7

II

71

77WIlI

DESCRIPTION MIN.

Address setup to read enable * 20

Address hold from end read enable

Chip select hold from end of lOR Data access time from read enable Data hold time from end of

T1

....,

,------r-I4"-T-3

''-

......

r::-r-----r-....JL

~T4=+1

7777777777771171lX~

lOR 20

____

xlllllllllOZ

*T2~

:;j

- I

T5

.....--....,

...J)Q7777ZZ7777Z7Z

TYP.

MAX.

*

* 130

20

0

UNITS

ns. ns. ns. ns.

ns.

* Read enable is the occurrence of lOR and CS

26

11.3 DMA WRITE (NON-BLOCK MODE) TARGET SEND

ORO DACK

DO

..

REO

ACK

DBO

DBP

NAME T1 T2 T3 T4 T5 T6

T7

T8 T9 T10 T11 T12 T13

___

-oJ

I

~T1~~------~-----

\

i4=T3

\

t4=

7

OZZZZZZZIZZZZZZZIII1X

---------------,

~T8~

----------~I

--""\1--

,~.

---------------------_--

__

..

7

~B~YT~E~N~-1~

DESCRIPTION MIN. TYP. ORO DACK Write DACK Data setup to end of write Data Width of ACK true to REO false 25 REO from end of DACK (ACK

-

ACK true to

REO from end of DATA Data setup to REO true (target)

0

....

1

T1

___________

false from DACK true

false to

enable width *

hold from end of lOW 0

hold time from end of lOW

hold from write enable 15

ORO

EOP pulse (note

ORO

____

J..-T7-.:t

f4- T12

true 30

enable *

1)

true (target) 15

ACK (DACK false)

\

T5

.~

~

B_YT-r-E_N

T4

T6---t

__

,------------------

~

false) 30

"'~I----

_____

l

~T2~

I

=:;J

-'XZZZZIZZZZIZ//ZZ

~T9~

~T11~'--

__

--~I

T13

~B~YT~E~N~

100

50 40

100

110 125 140

100 140

20

60

----

MAX.

130

150 110

150

.......

______

UNITS

ns. ns. ns. ns. ns. ns. ns. ns. ns.

1

ns. ns. ns. ns.

_

* Write enable is the occurrence of lOW and DACK

1:

Note

tion of the

EOP, lOW, and DACK must

EOP pulse.

be

concurrently true for at least T7 for proper recogni-

27

11.4 DMA WRITE (NON-BLOCK MODE) INITIATOR SEND

ORO DACK

00

..

DBO

DBP

NAME T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12

..

------------

/I71ZZZ1/ZZ7Z717ZZltK_~B~YT~E~N

7

----------------\ ,-----------------------

"\

--------\

________

7

14=

T8

DESCRIPTION MIN. TYP. ORO DACK false to

Write enable width *

DACK hold from end of lOW

Data setup to end of write Data hold time from end of lOW Width of EOP pulse (note

REO true to ACK true 20 150

REO

false to DACK false to ACK false 25 lOW false to valid SCSI data 100 OAT

A hold from write enable 15

I

~

_____

~BYT~E~N~-1

false from DACK true 130 ns.

I \ I

~T1~~--------~---T~2--~~

J;:

T5

a:.I4

________

T6

.....,

~>qllZII17/l1ZZ771

~T7--.:J

~

...

IT9

~--------~

---14-

T12~

ORO

______

true

~>elllZlllt<

enable *

1)

__

--~---~-T-1-0~

14=

T11*

____

30

100

0 50 40

100

20

140 150

...

)~-------

~BYT~E_N

MAX.

______ _

UNITS

ns. ns. ns. ns. ns.

ns. 160 110 ns.

ns.

ns. ns.

* Write enable is the occurrence of lOW and DACK

Note

1:

of the

EOP, lOW, and DACK must

EOP pulse.

be

concurrently true for at least T7 for proper recognition

28

11.5 DMA READ (NON-BLOCK MODE) TARGET RECEIVE

DRQ DACK

lOR

DO

...

7/

-r/"7"Z-Z:r-lZ""Z""ZZ-rZ-rZr-Zr::IZ

EOP

T11

....

1~.--

8~~'

. 7 < BYTE N

NAME T1 T2 DACK T3 DACK T4

T5

T6 T7 T8 DACK T9 T10 T11 T12

/

T6

\

---t

14=

T2 :::;f

~~_-J~

I~-------------------

J~

/

T3

BYTE N

X/-Z""'Z"'Z-Zr-ZT"'lZ"""'Z""'O""'Z"7"Z""'Z""'Z""Z

______________

I

M

Z""ZZ-rZ

-rzr,z""znZ""7{W~"T'7"":lZMZ"""/Z~b(

t---

T1

\

'---

___

I

\

~------~-~T5~

~T4"

.~

\ I

/

I4=T9~

t---

T10

..)~---

\_----------------------~/

..

a.

.....

I

.....

T12

~

XiZZZZZZllllllllllZOIZZllZZZZZZZ

DESCRIPTION MIN. DRQ false from DACK true 130 ns.

false to DRQ true hold time from end of lOR

Data access time from read

hold time from end of lOR 20

Data

Width of

ACK true to DRQ true

ACK true to REQ false ACK DATA setup time to ACK

DATA

EOP pulse (note

false to REQ true (ACK false)

false to REQ true (DACK false)

hold time from ACK 50

enable * 115 ns.

1)

TYP.

30

0

100

15 100 30 150 25 20 20

110 140

lZZZllllZIZ

MAX.

UNITS

ns. ns.

110

125 150 ns.

ns. ns. ns.

ns. ns.

_

* Read enable is the occurrence of lOR and DACK

1:

EOP,

Note of the

lOR, and DACK must

EOP pulse.

be

concurrently true for at least T6 for proper recognition

29

11.6 DMA READ (NON-BLOCK MODE) INITIATOR RECEIVE

DRO DACK

DO

..

REO

DBO

DBP

NAME T1 T2 T3 T4 T5 T6

T7

T8 T9 T10 T11 T12

I

I4-T1

\

I

\

14=

T4

7

ZZZZZZZ77707ZZZZ0777mZZe;~~

\ I

T9j;~-","""------------'I"'~I----

\~

________________________________

..

T111--1

7

<~

"'14

T12-.J

__

~B~YT~E~N~

DESCRIPTION MIN. TYP. DRO DACK false to DRO true DACK hold time from end of lOR

Data

access Data hold time from end of lOR 20 Width

REO

true to DRO true

DAC K

REO

true to ACK true 20 REO DATA setup time to DAT

A hold time from REO

__

~>eZZZZZZZ7Z7ZZZI7Z1ZZ1Z111ZZ1ZZZZZ771117177

false from DACK true

of

false

time from

EOP

to

AC K false

pulse (note

AC K false

read

(DAC K

REO

enable *

1)

(REO

false)

\

~

'-

/

;JT3

t-

I

-.:t

\4-Ts-.l

BYTE

N

T10

MAX. UNITS

130 ns.

30

0 ns.

115 ns.

100 ns.

140

20 25

15 20 ns.

50

140

150

120

150

160

'XImzzzzz

160 140

T2

r

~

-J'--

ns.

ns. ns. ns. ns.

ns.

*Read enable

Note 1: recogn

EOP,

ition

is

the

occurrence

lOR, and DAC K must be concurrently true for at

of

the

EOP

pu

lse.

of

lOR and DAC K

30

least

T6

for proper

11.7 DMA WRITE (BLOCK MODE) TARGET SEND

DRO DACK

lOW

DO

..

7

EOP

______

REO

..

7

~~

~

-------/

I~

______

ACK

READY

DBO DBP

NAME DESCRIPTION T1 T2 T3

T4 T5 Data T6 Width of T7 T8 T9 T10 ACK true to READY true T11 T12 T13 T14

I

,

1

________ ~ ____________

T10

~B~~E~N~-1~

DRO false from DACK true 130

enable width *

Write Write recovery time

Data setup to end of write

hold time from end of lOW

ACK true to REO from end of lOW (ACK false) REO from end of ACK (lOW false) 20 160

READY true to lOW false

lOW false to READY false DATA Data setup to

.1.

T13 ----.I

EOP pulse (note

REO false

hold from ACK true

REO true

f4-T1~

\

\4=

T2

.1.

T3

~

\

~J

T5~

T9

T12

--I

~T4

T11

~

.1..

,------

T14

-----

__

~>qZZZZI7ZZZO<------~B~~~E~N---------

TYP. MAX. UNITS

MIN.

100 120

enable *

1)

50 40 ns.

100

25 110 125 40 180 ns.

130

20 70

130

20 40 60

170

140

....

~I

ns.

ns. ns.

ns.

ns. ns. ns.

* Write enable

1:

Note

of the

EOP, lOW, and DACK must be concurrently true for at leastT6 for proper recognition

EOP pulse.

is

the occurrence of lOW and DACK

31

11.8 DMA READ (BLOCK MODE) TARGET RECEIVE

DRa DACK

lOR

DO

..

EOP

REa ACK

READY

DBO

..

DBP

7

7 Z

Z Z Z Z 7 7 7 Z Z Z Z Z Z

________________

----\

______

T12~

~---·

7

<

!

J-t-T1

\

J;:

~~

/

1-'T7~

-----~--------~-~!

14=

T9

..

I-

----J!

...

I ..

--T13~

BYTE

N XI 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7

T3 :J;I

T10

=4

,..

!

I.-T4--.!

X,--_....;;;.BYT..;...;...;;;;.E...;..;,N--JYI

T5

~~--------------

~

..........

---

~T8

~

T2

7 Z 7 7 7 Z Z 7

T6

------tl

T11-..!

\_----

----II.~I

..

~1

..

'--

__

'--

I

_

NAME T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13

* Read enable

Note

1:

EOP, lOR, and DACK must be concurrently true for at least T5 for proper recognition

EOPpulse.

of the

TYP.

100

180 110 160

130

125

MAX.

110

190 125

170

140

DESCRIPTION DRa

false from DACK true 130 lOR recovery time 120 Data access time from read enable

hold time from end of lOR 20

Data Width of lOR false to

ACK true to

ACK false to ACK true to READY true 20 READY true to valid data 50

lOR false to READY false 20 DATA setup time to DATA

is

EOP pulse (note

REa

true (ACK false) 30

REa

false

REa

true (lOR false) 20

hold time from ACK

the occurrence of lOR and DACK

1)

ACK 20

*

MIN.

100

25

50

UNITS

ns. ns. ns. ns. ns. ns. ns. ns. ns. ns. ns. ns. ns.

32

11.9 RESET

RESET

NAME T1

11.10 ARBITRATION

~

T1

\'10--------',

DESCRIPTION

Minimum width of reset

MIN. TYP. MAX. UNITS

200

\

~~-T-1-~-----------

ns.

BSY

DBO

ARB

~

T2

-J'-----------1

..

7

L1

7 7 7 7 7 7

71

--------------_1

--------------------------_1

NAME T1 T2 T3

DESCRIPTION Bus clear from SEL true 600 ARBITRATE start from BSY false 1200 Bus clear from BSY false

17

7 7 7 7

f4-

T3

MIN. TYP. MAX. UNITS

\

~'------

2200 ns.

1100

77

ns.

33

APPENDICES

A1. NCR 5380

vs.

NCR

5385/86

The NCR 5380 was designed to provide a low-cost Functional Areas 5380 5385E/86 SCSI interface using a minimum number of parts. Much of the intelligence and some of the features included

in

the NCR 5385E/86have been removed.

In some instances, such as arbitration, this causes the controlling CPU to provide more of the protocol control. The NCR 5385/86 remains appropriate for many applications and will continue to be strongly supported.

The main differences between the NCR 5380 and the NCR 5385E/86 are shown in the following table.

Arbitration

Maximum Transfer Transfer Counter Data Buffering Clock Circuitry

Single-Ended Transceivers

Differential Pair External External

Synchronous Mode

Optional, Automatically Firmware Dependant

1.5 MBPS

Rate

None 24 bits Single Double None Req'd On-chip

(NCR 5381) No Firm

Plans

Invoked

2.0 MBPS

5-10 MHz External

NCR 5386S

34

A2. FLOWCHARTS/SOFTWARE

Flowcharts and sample software drivers are provided as a

guideline to facilitate your firmware development. Firmware will vary depending on the application and the

level of the SCSI protocol being supported. accordance with register definitions, a one (1) designates

signal assertion and a zero (0) designates signal

non-assertion, or the inactive state.

In

35

ARBITRATION AND (RE) SELECTION

ON

WRITE

10

BIT

REGISTER

(PORTO)

SET ARBIT

2, BIT 0)

2.2

/Lsec.

TO

DATA OUTPUT

(PORT

WAIT

ARBITRATION DELAY

~------~--------~*

SET TARGET MODE

2, BIT

(PORT

(PORT 3, Bit 0)

WRITE CONTROLLER'S

AND INITIATOR'S

BITS

TO

REGISTER

SET DIFF. EN, ASRT.

BSY, AND ASRT. DATA

(PORT

RESET ARBIT

(PORT

6)

SET

ItO

DATA OUTPUT

0)

(PORT

BUS

1, BITS

5,

2, BIT 0)

10

3,

0)

*

DIFF. EN

USED IN NCR 5381

NOTE:

ONLY

READ

IF

PRIORITY ID IS

PRESENT

YES

ON

SET SEL

(PORT

WAIT 1.2

(BUS

CLEAR + SETTLE)

* RESELECTION

PORT 0

A HIGHER

1, BIT

/Lsec

ONLY

TO

2)

Min

SEE

CLEAR THE SELECT

ENABLE REGISTER

CLEAR SEL AND ASRT.

DATA

(PORT

RESET BSY

(PORT

SET BSY

(PORT

BUS FLAGS

1,

1, BIT 3)

1,

4)

BIT 3)

BITS 2.0)

INFORMATION

TRANSFER PHASES

36

COMMAND TRANSFER PHASE (TARGET)

SERVICE

MESSAGE

CONDITION

OFF

SET

C/O

FLAG

(PORT 3, BIT 1)

SET

C/O

(PORT 3, BIT 1, 3)

FLAG

REO

= 0

ACK

= 1

REO ACK = 0

OFF

C/

D AND REO FLAGS REO = 1

SET

(PORT 3, BIT 1,3) ACK = 0

READ CURRENT

SCSI

DATA REGISTER

(PORT

0)

SET

C/O CLEAR REO FLAG (PORT 3, BIT 1, 3)

FLAG

REO ACK=

REO = 0 ACK = 0

= 1

1

ON

READ CURRENT

SCSI

DATA REGISTER

(PORT

0)

EXAMINE FUNCTION

CODE

SET COMMAND

LENGTH POINTER

C/O

FLAG

SET

CLEAR-REO FLAG

(PORT

3,

BIT

1,

3)

OFF

= 1

REO ACK = 1

REO = 0 ACK = 1

REO = 0 ACK = 0

NO

YES

ENTER

NEXT PHASE

37

ACCEPT

AN.D RESPOND TO MESSAGE

DATA TRANSFER TO HOST

PROGRAMMED

VIA

ON

1/0

DOWNCOUNT

BYTE

COUNTER

OFF

SET BSY, DIFF.

AND

ASRT. DATA BUS

(PORT

1,

BITS

SET ASRT.110

(PORT

3, BIT 0)

DATA BYTE

WRITE

TO

OUTPUT DATA

REGISTER

(PORTO)

SET

ASRT.

AND REO

(PORT

3, BITS 3, 0)

5,

1/0

EN.

3,

NOTE:

DIFF.

0)

EN ONLY USED

IN

NCR 5381.

REO = 0

AcK=

REO = 1

AcK=O

0

NO

ON

SET ASRT.

RESET REO

(PORT

38

Vc5

3, BITS 3,

REO = 0

ACK=

0)

1

DATA TRANSFER VIA DMA

+

SET-UP DMA CHIP

WITH BASE ADDRESS,

WORD COUNT

OF OPERATION

MODE

AND

SET BSY, DIFF. ASSERT DATA BUS

(PORT

EN.,

1,

BITS

5,

3,

II

SET BLK MODE DMA,

EN.

EOP INT., AND

DMAMODE

(PORT

2,

BITS

7,

3,1)

•

SET

ASRT.

(PORT

SET

1/0

3, BIT 0)

START DMA

(PORT 5)

..

Ir

NOTE: DIFF.

EN

0)

IN

NCR 5381.

ONLY USED

NO

EOP

INTERRUPT?

YES

.,

CHECK ENDING

STATUS

(PORT

5)

STATUS PHAS

,r

39

E

LINE#

LOC

0012101 00002 00003 00004 00005 00006 00007 00008 00009 00010 00011 00012 0012113 00014 0121015 0012116 012112117 012112118 0012119 01211212121 0012121 012112122 0012123 00024 00025 00026 0012127 0012128 0012129 0012130 1210031 001213c: 00033 0012134 12112112135 00036 00037 012112138 0012139 0004121 00041 1210042 00043 00044 00045 00046 00047 0121048 0012149 0012150 00051 00052 00053

00054

0012155

CODE

121000 0000 121000 012100 0000 000121 121000 121000 121000 0000 0000 0000 001210 000121 121000 1211210121 12101210 000121 121000 121000 121000 1211210121 121121121121 000121

I() 0

12t

0

12112100

001Z10

12101210 000121 12101210 000121 12101210 01210121 000121 1211210121 00121121 0000 121000 0000 CI2I121121 CI2I01 C002 CI2I03 CI2I04 CI2I05 C

121121

6 C01216 C007 C025 C025

C026 C027 C027

C033 C233

LINE

NCR

538121 SUPPORTS ASSUMES

DATA TABLE

;

THAT

BLOCK(DBLK),

HAVE

SLFAIL=$01

DISCNT=$02

PRTYER=$03

BUSRST=$04 CHIPFL=$05 MESSAG=$12I6 DIFFPH=$07

;

CJVlDCPL=$00

;

DATAIZ.=$00 CMD=$08 STATUS=$0C

DATA I =$1214 IYIESSO=$18 MESSI=$lC D1SCOI\I=$80 SELECT=$40

;

S5~~8121=$DE00

SDMA=$OE0C

1ID=$DEI2I8 SRST=$DFI2I0 BPNTR=$FB

;*=BPNTR

;

;DATAB

;

.~ORD

*=$C000

TID

ICRVAL

INITFL

OCFLAG

PTYFLG

ATNFLG

;

PHSIDX

XPTPHS

;

COUNT

XCNT

;

CDa

DBLK

STAT

*=*+1

*=*+1 *=*+1

*=*+30

*=*+1

*=*+12

*=*+512

*=*+2

SCSI BOTH

BEEN

DBLK

PROTOCOL

INITIATOR

THE

COMMAND

AND

SPECIFIED

DRIVER

AND

TARGET

BLOCK

THE

EXPECTED PHASE

IN

MEMORY

ROLES

(COB).

SELECTION FAILED STATUS

DISCONNECTED STATUS PARITY SCSI

CHIP

MESSAGE

ERROR

BUS

STATUS

RESET STATUS

FAILURE STATUS

IN

BYTE

BEING

RETND

UNEXPECTED PHASE REQUESTED COMMAND DATA

COMMAND

COMPLETE

OUT

PHASE

MESSAGE

PHASE

STATUS PHASE

DATA MESSAGE MESSAGE FLAG

FLAG 5380

PSEUDO

INIT.

NCR538121 DATA

PROGRAM

;

IN PHASE

OUT

PHASE

IN

PHASE

TO

DISCONNECT

TOWAIT

FOR

ADDRESS SPACE

DMA

ADDRESS

IO EXT.

DEVICE RESET

BLOCK

POINTER

SPACE

;

TARGET

INIT.

C~D

ID

REG.

INITIATOR

OPEN

PARITY ATN

COLL.

FLAG

EXPECTED PHASE EXPECTED PHASE

;

BYTE

CMD

DATA

COUNT

COUNT BLOCK

BLOCK

SELECTION

LATCH

ORIGIN

SPACE

STORAGE

FLAG

INDEX TABLE

MULTIPLIER

STORAGE

STATUS ByTES

40

LINE#

LOC

CODE

LINE

00056

1210056 121012156

001Z157

012112158

Q.~tZtel~i9

0121

QI

00061

012112162

0012163

1210IZ1EA

0012165 121012166 1210067 12112112168

12112106':3

12101217121 12112112171

012112172

0Q)12I73

0121074

00

1217

00076

001Z177

00078

121012179

00080

00081

0012182

1210083

00084

0012185

012112186

12112112187

0121088

00089

12112109121

00091

1210092

1210093

0121094

1Z10el'35

1210096

00097

012109B

01211219'3

0010el

0121101

1210102

0121103

0011214

00105

1Z11211tZ16

0121107

IZItZII1Z18

C235 C237

C239

1:23B

C238

Cc:3B

6

IZI

C23B

C23D

C240

C243

C245

C248

C24A

C24C

C24F

C252

C254

C257

C259

C25C

ei

C25C

C25F

C2E.1

C264

C267

C26A

C26D

C26F C272

C272 C272 C272

C275

C277 C2"17

C278

C27B

C270

C27F

Ci.:::7F

C282

C283

C286

C288

C289

C28C

C28E

C29121

C290

27

C0

33

C0

33

C2

A'3

00

8D

06

AD

00

A9

04

.AE

04

F0

02

09

30

80

02

AE

06

A'3

4Q.~

DD

07

D0

1213

4C

BD

AD

02

29

FE

8D

02

AD

08

8D

0121

AD

02

09

1211

8D

82

2C

0i

50

FB

EA

AD

01

29

20

00

DD

AD

1210

38

ED el8

F0

08

38

ED

08

30

02

D0

CC

eel

DF

C0

DE

C0

C3

DE

53

DE

COBS .WORD

INITIALIZATION

;

START

LDA STA LDA

LDA

LDX

BEQ NOPTY

ORA

NOPTY

STA S5381Z1+2

LDX

LDA

CMP

BNE

3MP

BEGIN

;

IN1T

SCSI

LDA AND

STA

ARB

LDA

STA

LOA ORA STA

HAS BUS

NFREE

GONE

BIT BVC

NOP LOA AND

BNE

CHECK FOR

LDA SEC SBC

BEQ

SEC

SBe BMI

BNE

RECHECK LOST

CDB,DBLK,STAT

#00

PHSIDX SRST

#~1ZI1Z11Z10011Z11Z1

PTYFLG

#'1-0011001210

ZERO

INITIALIZE RESET 53B0NUMBER ENABLE LOAD

IF

ZERO,

OR

IN

STORE

PHSIDX

#SELECT XPTPHS,X

INI,..

TARSEL

BUS

ARBITRATION

S5380+2

#~11111110

S5380+2

lID

S5380+0

85380+2

#'1-0121001211211211

$5380+2

LOAD

GET

COMPARE

;

IF

;

ELSE,WAIT

READ

MASK

;RESET

;BEGIN

;LOAD ;

READ ;SET ;STORE

VAL~E

NOT = BEGIN

MODE

ARB

ARBITRATION

FREE?

5538121+1

NFREE

; BUS F REE

;NO LOOP

;YES,

85380+1

#Y-00100000

INIT

HIGHER

85380+0

lID

WIN

PRIORITY

;LOAD ;MASK ALL ;IF

LOST ARB, RESTART

ID?

;LOAD CURRENT

;SET

CARRY

;SUB

;IF

YOUR

EQUAL

;NOT=,

110

WIN

INIT

;SUBTRACT ;IF

NEG,

;OTHERWISE,

ARBITRATION

ACCUM

PHASE INDEX

MONITOR BSY

PARITY

CHECK

IN

VALUE

FLAG

NO

PARITY PARITY

MODE

~/CURRENT

REGISTER

OF

PHASE INDEX

OF

SEL

FOR TARGET

REG.

BIT

ARBITRATION ARBITRATION ID

INTO

MODE

IN

~j

REG.

MODE

ODR

REG.

UNTIL

WAIT

INIT

AN

CMD

BUT

ARB

REG.

LA

DATA

BIT

ID

FROM

TO

ZERO, WIN

SOMEONE

YOUR

ELSE

ID

RESTART

INT.

BITS

CMD

PHASE

ARBITRATION

SELECT

BIT

BiT

FREE

DELAY

(2.2USE

BIT

REG.

DATA

REG. ARB

IS

ARB-ING

AGAIN

WAS

HIGHER

41

LINE#

LaC

CODE

LINE

12112111219

12112111121 121121111 121121112 121121113 121121114 121121115

00116 1210117

0121118 00119 1210120

C29121

C293

C295

C297

C299

C29C

C29E

C2A0

C2A3

00121. C2A3 121121122

00123 121121124 00125 121121126

012112"' 121121128 12112112'3 1211211312'

0121131 121121132 121121133 121121134 121121135 121121135 121121137

12112113B 121121139

12112114121 121121141 121121142

00143 1210144

00145

0121145

1210147 121121148

00149

012115121

0121151 0121152

0121153 0121154

00155 121121156

00157

0121158

00159

121015121

0121161

121121152

1210153

C2A4

C2A7 C2A'3 C2A9 C2A9

C2A9 C2A9

C2AC C2AE

C2Bl C2B3 8D

C2B6 C2B6

C2B9 C2BC 8D

C2BF C2BF TEST

C2BF C2BF

C2C1 C2C4

C2C6 C2C6 DIFFERENTIAL

C2C€) C2C6

C2C8 C2CB

C2CE C2CE

C2Dl C2D3

C2D6 C2D6 DISABLE

C2D6

C2D8 8D

C2DB

1211

AD

2121

29

0121

C5

A9

I2IC

AE

1215

Fill

02

09 02

BD

1211

EA

AD

1212

0D

DI2I

AD

1212

40

1219

02

80

1211

A9

1213

AO

1218

1210

121121

A9

1215

AE

1213

DI2I

02

09

20

80

01

1211

8D

AD

1212

29

FE

80

1212

A9

1210

1214

AD

1211

DE

CI2I

DE

C0

DE DE DE DE

C0

DE

CI2I

DE

CI2I

DE

CtZI

WIN

WOATN

WAIT

ELSE,

;

SEL

OPNCOL

85380+1

LDA

AND

#~tZIIZ11tZ1lZ1lZ1lZ1tZ1

BNE

INIT

LDA

#~12I012101100

LOX

ATNFLG

SEQ

WOATN

ORA

#~12I0121012101121

STA

S5380+1

1

'J

USEe

.~

NOP

LDA

INITFL

BNE

SEL

TARGET

LDA

8538121+2

ORA

#~tZI11Z11Z11Z1l21tZ10

8538121+2

STA

#$1211

LDA

8TA

S5380+3

LDA

110

ORA

TID

STA

8538121+121

FOR

DIFFERENTIAL

LDA

#~tZI00tZ1I2111Z11

LOX

OCFLAG

BNE

OPNCOL

#";<,0121112112100121

ORA

STA

S5380+1

STA

ICRVAL

RESET ARBITRATION

LDA

8538121+2 ;

#y;.1111111121

AND

S5380+2

8TA

THE

#$00

LDA STA

S5380+4

RELEASE

LDA

BUSY

ICRVAL

RESELECTION

PAIR

BIT

EN

SEL

REGISTER

IF

OR

IN1T.

ALL

LOST

VALUE ATN

ZERO,

IN

ON

ARB,

ATN

SEL LINE

;

LOAD

;MA8K

;IF ;LOAD

;LOAD

;

;TURN

;LOAD IN A

FLAG

;IF

;

READ

;

ENABLE

;SET

SET,

MODE

TARGET

TARGE.T

;ENABLE ASSERT

;SET

ASSERT

LOAD

;

;LOAD

OR

;

INITIATOR

IN

TARGET

INT & TAR

PAIR

DATA

&

;SEL ;LOAD IN A ;IF

.

..

;8ET

;

READ

;

MASK

;RESET

;

FLAG

OR

8EL,

RETAIN

ZERO

GET

DIFF.

IN

MODE

ARB

TO

AVOID

ACCUM.

SELECT

INIT

SET,

DATA VALUE

CMD

REG.

BUT

LA

RESTART

SET

TO

FLAG

W/O

SEL

BIT

SOFTWARE:

PERFORM

REG.

MODE

1/0

I/O

10

ID

ID'S

BUS

BITS

SOFTWARE

OPEN

ENBL BUS, &

OF

REGISTER

BIT

SEL

A

ENABLE

REG

CMD

BIT

BEL

SIGNAL

ATN

FLAG

INIT.

INTO

FLAG

COLLECTOR

BITS

(DIFF.

INIT

INT.

REG.

VALlJE

CMD

SEL

ODR

PAl

REG.

42

LINE#

LOC

CODE

LINE

00164 00165 00166 00167 00168 00169 00170 00171 00172 00173 00174 00175 00176

001T7

00178 00179 00180 00181 00182

00183

00184 00185 00186 00187

00188

00189 00190 00191

00192

00193

00194

00195 00196 00197 00198 00199

00200 00201

00202 00203 00204 00205

00206 00207 00208 00209 00210 00211 00212 00213 00214 00215 00216 00217 00218

C2DE

C2E0

C2E3

29

8D

80

C2E6

C2E8

C2EA

C2ED

A0 A2 2C 70

C2EF

C2EF C2EF C2EF

C2F0 C2F2 C2F3

CA D0 88 D0

C2F5 C2F5

C2F7 C2FA

A9 8D

A2

C2FC 2C C2FF

C301 C302

70 CA 00

C304 C304

C306

A9

60 C307 C307 C307 C307

C30A

C30D

C30F C311 C314 C317 C319 C31C C31F

AD

AE 00 09

8D

8D A9 2D

80

8D C322 C322 C322 C322 C323 C325

CA

F0

4C C328 C328 C328

C328

F7

01

60 FF 04

18

Fe F3

00

00 20 04 06

F8

01

02 08 08 01 01 28 01 01 01

03

20

DE

C0

DE

C0

DE

C0 C0

DE C0

C4

AND

*~11110111

STA

S5380+1

STA

ICRVAL RETAIN ICR

NOW

WAIT

RELD STIM

WAIT

LOY LDX

BIT

BVS

250

400NSEC *$60

#$FF

S5380+4

SLECT

MSEC

AND

DEX

STIM

BNE DEY

BNE

RELD

SELECTION TIMEOUT

#$00

LDA STA

85380+0 #$20

LDX

CHK

BIT

BVS

85380+4 SLECT

DEX

BNE

CriK

SELECTION

LOA

FAILED

#SLFAIL..

RTS

SUCCESSFUL (RE)SELECTION

;

SLECT

LDA

ICRVAL

LDX

INITFL

IF

BNE

ORA

*~00001000

STA

85380+1

STA ICRVAL

IF

LOA

"~00101000

AND

ICRVAL

STA

S5380+1

STA ICRVAL

BEGIN

TRANSFERS

DEX BEQ

PDMA RES

JMP

USE

INITIATOR

PSEUDO

DMA

ROLE

MODE

MA8K

RESET

BEGIN

LOAD

SAMPLE

IF

OUT

BSY

LOOKING

UP X REG

UP

BSY

ACTIVE, SELECTED

DELAY

IF

NOT

ZERO

IF

;

TAR.

RESET

LOAD

CHECK

IF

LOAD

RETURN

GET

;

GET

IF

AND

WRITE

UPDATE

;

MASK

AND

;

RESET SEL & DATA

;

,

UPDATE

DEC

IF

ELSE.,

NOT

Y

DID

ID

200

BSY

St:":T

SELECTION

STATUS IN

TO

VALUE

INIT

INITIATOR

8ET

TO

PRESENT

TO

Rt::SET

WITH

NEW

INITIATOR

ZERO,

INITIATOR

TARGET

BSY

VALUE

FOR

Y

REG

BIT

Zt::RO

NOT

BITS

USEC

AGAIN

CALLING

OF FLAG

BSY

ICR

ROLE

BIT

BSY FOR

FOR

LOOP

RELOAD

RESPOND

COUNTER

OK

ACCUM.

INIT

CMD

J'UMP

IF

TARGET.

ICR

SEL

&

VALUE

BUS

VALUE

FLAG

ROLE

COUNTER

X

TO

SEL

PRGM

REG.

VALUE

DATA

BUS

43

LINE#

LOC

CODE

LINE

00219 0022121 00221 0121222 00223 00224 00225 0121226 1210227

121121228

00229 12112123121 121121231 1210232 121121233

0121234 121121235 121121236 121121237 121121238 121121239 00240 121121241 00242 0121243 00244 121121245 1210246 121121247 00248 0121249 00250 00251 0121252 00253 0121254 00255 00256 00257 121121258 00259 0121260 00261 1210262 0121263 121121264 121121265 121121266 0121267 121121268 121121269 12112127121 121121271 0121272 121121273

C328

C32A

C32D

C33121

C332

C335

C338

C33B

C33E

C341 C344 C344 C344 C344 C347 C349 C34B C34B C34B C34B C34E C35121 C353 C356 C359 C35C C35F C361 C364 C366 C369 C36C C36E C371 C373 C376 C376 C376 C376 C378 C379 C37C C37E C381 C384 C386 C387 C389 C38A C38C C38D C38D C38D C38D

A9

0121

80

03

DE

AD

1212

DE

1219 1212

8D

1212

DE

AE

1216

CI2I

BD

08

CIZ1

8D

25

CIZ1

BD

09

C0

80

26

CI2I

AD

1215

DE

29

10

FI2I

F9

AD

1212

DE

29

FD

8D

1212

DE

AD

1215

DE

AD

1215

DE

AD

05

DE

AD

1215

DE

B0

15

BI2I

15

DE

90

76

90

76

DE

90

76

DE

8121

IZIB

2C

1214

DE

3121

14

4C 8A C3

A9

1212 6121 AD

1211

CIZI

1219 1212

80

1211

DE

80

01

C0

A9

1213

6121

A9

04 6121

A9

05

6121

AD

1212

DE

;

PDMA

NXT

WAIT

;

WAIT

IRQ

RETURN

;

EBUSY EPRTY

BRST FAIL

WAIT

;

TARSEL

LOA

#DATAI2I

STA

S5381Z1+3

LDA

S5380+2

ORA

*~1Z11Z11Z11Z11Z112110;OR

STA

S5381Z1+2

LDX

PHSIDX ;

LDA

XPTPHS+1,X;

STA

COUNT

LOA

XPTPHS+2,X;

STA

XCNT

FOR

PHASE

LDA

S5380+5

AND

"'1-001211012100

BEQ

WAIT

IS

ACTIVE

LDA

S5380+2

AND

""11111101

STA S538121+2

LDA

S538121+5

LSR

BCS

EBUSY LSR BCC

PHSMM LSR

LSR

BCS EPRTY

BIT

S5380+4 BMI

BRST

JMP

FAIL

ERROR

LDA

#DISCNT

RTS

LDA

ICRVAL ORA

#'1-1211211211211211211121 STA

S5380+1 STA ICRVAL LDA

*PRTYER

RTS

LDA

#BUSRST

RTS

LOA

#CHIPFL

RTS

FOR

TARGET LDA

S5380+2

MISMATCH

STATUS

SELECTION

LOAD GET

IN SET LOAD

GET

; STORE IN PHASE

GET

TeR

MOOE

DMA

X W/PHASE

PHASE

COUNT

W/DATA

REGISTER

MODE

BIT

INDEX

COUNT

MULTIPLIER

OUT

• STORE IN MULTIPLIER INT.

SAMPLE

LOOK

IF

GET

RESET RESET GET

SHIFT

LOSS

BUS&STATUS REG.

FOR

INT.

NOT

SET,

MODE

DMA DMA

BUS

WAIT

REG.

MASK MODE

& STATUS

RIGHT 3 TIMES

OF

BUSY

REQ.

BIT

REG

ERROR

SHIFT

IF

CARRY

SHIFT

IF

SET~

GET

CURRENT

IF

BIT 7 SET,

SHOULD

TO

CALLING SET DISCONNECT GET

INIT.

TURN

SET

ATN SET PARITY SET

BUS

SET

CHIP

RETURN

;

GET

MODE

TWICE

NOT

ON

TO

CLEAR,

PARITY

SCSI

GET

PROGRAM

CMD

ATN

SIGNAL

E~ROR

RESET

FAIL

CALLING

REG.

MISMATCH

ERROR

BUS

HERE

FLAG

REG.

ERROR ERROR

PHASE

BYTE

STATUS

RESET

VALUE

PRGM

OCCURED

44

LINE#

LOC

CODE

LINE

00274

tZI0275

00276

00277

00278

00279

0028e,

0121281 00282

00283

C390

C392

C395

C3'38

C39B

C.39E C3A0 C3A2 C3A2 C3A2

0tZI284 C3A2 00285 00286

00287

1210288 00289

C3A2

C3A5 C3A7

C3A9 C3AC

tZI0290 C3AD 0121291

1210292

00293 00294 00295 00296 00297 00298

00299

0030121

00301

00302 00303 00304

00305 1210306

00:~07

0031218

00309

012131121 00311

00312 1210313

00314 00315

1210~31E,

00317

00318 00319 1210320 00321 00322 1210323 00324 1210325 0121326 00327 00328

C3AF

C3Bl

C3B2

C3B4

C3B5

C3B6

C3B8

C3BA

C3BD 4C 9B C3

C3C0 C3C0 C3C0 C3C0

C3C3 C3C5

C3C7 C3CA

C3CC C3CE A9

C3D0 8D C3D3

C3DE, C3D9 4C

C3DC C3DC PHASE

C3DC C3DC

C3DF C3E2

C3E4 C3E7

C3E9 C3EC C3EC C3EC C3EC C3EF C3F2

40

09

02 08 04

05

10

F9

00

09 0121 00

DE DE DE

DE:

DC

DE

8D

AD

80

AD

29

FtZI

AD

A2

A0

AIZ,

CA

F0

05

Fa

90

C8 B0

F5 38 98

1113

E9

30

06 AD

07

DE

05

20

82

04

02

BC

DE

AD

29 F0 AD

29

F0

08

01

DE

01

80

AD

AE

AD

29

DO

F0

C0 STA ICRVAL

07

DE

2D

C4 JMP RES

06

CtZI

1214

DE

1C

07

C0

03 4C B4 C4

B4

84

03

C4

DE

4C

8D

LOOK

CHECK

UP

OUT

CHECK

CI

PHSMM

PHASE

PHSMTH

#~01000000

ORA

STA

S5380+2

LOA

110

STA

S5380+4 S5380+5

LOA

#~0001001210

AND

BEQ

LOOK

THAN

LDA

LDX LDY

FOR

MORE

S5380+0 #$09

#$0121 LSR DEX BEQ

OUT BCC

UP

INY

UP

BCS SEC TVA

#$03

sac

BMI

CI

85380+7

LOA

J'MP

LOOK

INTERRUPT

S538121+5

LDA

#~1ZI011Z101211Z11Z1

AND

BEQ

EPRTY

S5380+4

LDA

#1-00tZ1eltZl010

AND BEQ

FAIL LOA

#1-0000100121

srA

S5380+1

8538121+']

LOA

MISMATCH

PHSIDX

LDX

S5380+4

LDA

AND

#1-1210011100 CMP

XPTPHS, X

BEQ

PHSMTH JMP

DP

MATCHES

CONDITION

EXPECTED

LSR

STA

8538121+3

SET TARGET

TARGET

SET

TARGET

GET STORE

IN

SAMPLE

LOOK

FOR

MODE MODE

10

SELECT ENABLE

BUS&STATUS

REQ

INT

KEEP WAITING

TWO

10'8

READ

SHIFT

INITIALIZE

SHIFT

DECR.

IF

ZERO,

IF

CARRY

IF

GET

SET

PUT Y IN

SUBTRACT 3

IVI

IF

"'OT

WAIT

SAJYlP,-E

MASK

ACTIVE

SCSI

COUNT BIT

SHIFT

NEXT CARRY

INUS,

MINUS,

FOR

AGAIN

PARITY

OATA

BIT

INTO

COUNT DONE NOT

SET,

SET

BUMP

BIT

ACCUM

FROM

OK

RESET

GOOD

BIT

PARITY SELECTION

GET

CURRENT

CHECt{

IF

SET

,

RESET

LOAD

MASK

SEL

NOT

BSY BSY

RETAIN ICR

INTERRUPT

X CURRENT AL.L

COMPARE YES, ELSE,

PHASE

DIFFERENT

SET,

WITH PHASE POINTER

SCSI

FAILURE MASK SEL

COMPLi::':-:E

VALUE

SCSI

BUT

PHASE

TO

XPTED PHASE

MATCHES

PHASE SHIFT

STORE

TO

IN

TCR TCt1

REG.

MASK

BIT

REG.

BUS COUNT

CARRY

BIT

COUNTING

DO

CNT

COUNT

BIT

IRQ.

SELECTION

ERROR

ST.

BUS

STATUS

BlOCS

PHASE

FORMAT

REG.

45

LINE#

LOC

CODE

LINE

121121329

00330 00331 00332 1210333 00334 0121335 0121336 00337 0121338 00339 00340 00341 0121342 121121343 00344 0121345 0121346 00347 0121348 00349 00350 1210351 00352 121121353 1210354 00355 0121356

00357 0121358 00359 0121360 00361 00362

0121363 00364

00365

00366 1210367

00368

00369

00370

0121371

00372

00373

0121374

0121375

00376

0121377

00378

00379

0038121

00381

1210382

00383

C3F5

C3F8

C3FA

C3FD C3FF C3FF C3FF C3FF C402 C404 C407 C40A C40D C40F C412 C415 C417 C419 C419 C419 C419 C41C C41E C421 C424 C42'+ C424 C424 C42-' C42A C42D C42D C42D C42D

C43121 C432 C435 C438

C43B C43E

C441 C444 C444

C447 C449

C44B C44E

C450

C453

C455 C458

C45B

C45E

C461 C463

AD A9 DD

DI2I

AD

29

8D

AD

1219

EJD

AD

29

F0

80

A0

2121

4C

20

80 4C

AD 09

80

AE BD 8D BD 80

AD

29

D0

AE

A9

DO

F0

BD

80

29 FI2I

07

18

07

0B

1211 FD 01 1211 02

0

121

-'

Co

1212 03 1211 I2IB

1217 1210 FE 20

27

0C

20

02

06

1218

25

1219

26

05

02

40

06

80

07 3B 1217 07 1217

1213

01

1D

DE

C0

CI2I DE

C0 DE

DE DE

DE

C4 C3

C5 DE C3

DE

DE C0 C0 C0 C0 C0

DE

C0

CI2I DE

LDA

CMP

BNE

MESSAGE

LOA

AND

STA

5TA

GMR

LDA

ORA

STA

LDA AND BEQ

INITIATOR

;

IDMAI STA

LDY JSR JMP

INITIATOR

;

IDMAO

JSR STA JMP

TARGET

RES

LOA

ORA

8TA

LDX

LDA

STA COUNT

LDA

STA

LDA

AND BNE LDX LOA CMP BEQ LDA

LSR

STA

AND BEQ

S5380+7 #/YIESSO XPTPHS,X GMR

OUT,

RESET

ATN

ICRVAL. GET :j:fY-l111111211 85380+1

ICRVAL 8538121+2 #Y-00000121 1

121 S5380+2 S5380+3 #Y-12I1210000

121

1

IDMAO

DMA

INPUT

85380+7 #121121 DMAIN

NXT

DMA

OUTPUT

DfYlAOUT

SOMA NXT

OPERATION

S5380+2

;

*Y-12I1210121121010;OR S538121+2 PHSIDX XPTPHS+l,X;

XPTPHS+2,X;

;

GET

;

GET

XCNT

S5380+5

#Y-12I001210010

MESSOT

PHSIDX

#DISCON

XPTPHS,

X

DISCTO

XPTPHS,X

S538121+3 STORE

#~000t210001

TOMAO

RESET LOAD WAS

IF

INTERRUPT

MESSOUT

PHASE

NOT

MATCh

MESS. OUT, CONTINUE

INITIATOR MASK TURN

UPDATE GET SET STORE

GET SET

START

PERFORfYI

PREPAF<E

PERFORM

EXTHA

PREPARE

GET

SET

OFF

ATN

OFF

ATN

rCR

VALUE IYIODE DMA

PHASE

I/O

IF

ZEF"<O,

INITIALIZE

MODE

IN

DIYIA

DMA

LOAD

PHASE

STOF<E

COUNT

STORE

GET BUS & !VI

AS

1-<

ATN

ACTIVE

CURRENT

GET

DISCONNECTED VALUE

GET COMPAF<E

IF

=,

PHASE

GET SHIFT

SAVE

IF

ZERO,

REG

MODE

TCR

IN

AGf~

MASK

DMA

INIT.

Rev.

Y

DMA

INPUT

FOR

DMA

wRITE

FOR NEXT PHASE

FOR

REGISTER

MODE

BIT

MODE

W/PHASE

X

COUNT

IN PHASE COUNT BYTE

MULTIPLIER

!VIULTIPLIER

IN

STATUS

ATN

BIT

DO

PHASE

W/PHASE

TCR

TARGET

i\f

BIT OMA

TO

TIME

TO

I

liD

VALUE

MESS.

CiYlD.

BIT

IN

OUTPUT

PHf~SE

ACK

BIT

INDEX

REG.

MESS

VALUE

01

SCONNEC"i

FORMAT

COIYlMAND

OUTPUT

OUT

REG

TO

OUT

INDEX

GO

OFF

PHASE

O

REG.

46

LINE#

LOC

CODE

L.INE

00384 00385 00385 00387

003BB

00389 00390 00391 00392 00393 00394 00395 00396 003'37 00398

00399

00400 00401 00402 00403

00404

00405 00406 00407 00408 00409 00410 00411 00412 00413 00414 00415 00416 00417 00418 00419 00420 00421 00422 00423 00424 00425 00426 00427 00428 00429 00430 00431 00432 00433 00434 00435 00436 00437 00438

C465

C46B

C46A

BD

A0 20

C46D C46D C46D C46D

C470 C472

C475 C477

C47A C470 C47F

2C 50 AD 29

SD

AD 91

4C C4B2 C482 C482 C482 C485 C488 C48A C480

20

AD

29

8D

4C C490 C490 C490 C490 C492 C495 C497

A9

SO A9 60

C49B

C498 C498

C49B

C49A C49D C4A0

C4A3

C4A5

C4A6

C4A9

C4AA

C4AD

C4AE

C4Bl

C4B4

C4B4 C4B4 C4B4

C4B6 C4B9

C4BB A9 C4BO

A9

A9 A9 80 A9

CA 90 CA 90 CA

8E

4C

A9 DO F0

60

06 01 FE

05 FB 02 FD 02 !ZIC

FB

2D

27

02

FD

02

20

1210

01

02

18

18 03 01

07

07 06

82

lC 07 03 07

DE

C4

DE

C4

C5

DE

C4

DE

C0

C0 C0

C4

C0

TARGET

TDMAI

;

LBTDRG!

TARGET

;

TOtr1AO

DMA INPUT

85380+6

STA

L.OY

JSR

HANDLE

85380+5

BIT

ave

LDA AND BTA LOA STA

JI"IP

DIY/A

JSR

DMAOUT LDA AND

#1-11111101 ST'A

'1+01 DMAIN

LAST

LSTDRQ S5:380+2

~1-1111il01

S5:381Zl+~:

SDfYlA

(BPNTR),Y

RES

OUTPUT

S5:380+2

85380+2

JMP RE.S

TARGET DISCONNECT

DISCTD

LOA

s'rA LOA

#00

S5380+1

#OISCNT RTS

MESSOUT

MESSOT

PHASE

#tr1ESSO GET

LOA

LSR

LSR 8TA

85380+3

#1

LOA

DEX

STA XPTPHS.,X

DEX

8TA

XPTPHS, X STORE

OEX STX

PHSIDX JMP

TDMAO

DIFFERENT

;

DP

LOA CMP BEQ LDA

PHASE

#MESSI

XPTPHS, MESSIN #DIFFPH

RTS

BYTE

(TARGET)

X

START Di'l1A

Y

SET PERFORtr1 DMA

TO

PREVENT

LDOK

LOO~'

Gt::T

MASK

FOR TILL

MODE

DiYIH

RESET

Gf::.T

L.Ht3T

EITORE

NI:::XT

DO

PERFOf;:M

Df(iA

GET

MASK

DMH

RESET

DO

ACCUM

RESET

TARGET

TO

ONE,SO

II\j~'UT

EXTRA

ORQ

ON

f<E13

•

I'H:JDE

Di'l1~l

!YlODE

BYTE

L.AST

EW";''E

PHf:),S!::~

OUT

DIYlA

fYiCIDE

MiJDE

f't',OD::::

D!"'IA

PI-lASE

wi Zr::RO

B;:;Y

&

DTHER

BIT

F

BIT

DISCONNECTED STATUS

REYuRN

SHIFT

fYiESSOUT

LOAD

MOVE

STORE

MOVE

"1·0

C~~LLING

OF

TCR

fYlESSi=lGE

FORIYIAT

VALUE

TO

P:-lASE

MULTPLIER/COUNTER

j:.:'OINTER

MULT

I

t='L

I

=:

POINTER

TO

COUNT

MOVE

UPDATE

DMA

DO

LOAD

THIS

IS

IF=,

LO:-=iD

RETN

PH~~SE

TO

I'rl[lVED

PH~~St:::

OwT

VALUE

A

READ

MESSAGE

OF MESSAGE MESSAGE

DIFFERENT

W/UNEXPECTED PHASE

f<CV

1\10

EXTRA

Rt::G!

BIT

CHIi=-)

::<'UiVl

.:'LJT

BIT

81

PRGM

r"<

CDUI\tT

INDE.X

IN ;:::'hASE

PHASE

i~EQ

GN(=~LS

OUT

VAi....uE

.VALuE

!i"\I

P~1ASi:.

~;T

•

S"!"ATUS

47

LINE#

LOC

CODE

LINE

00439 00440 1210441 00442 00443 00444 00445 00446 0121447 0121448 121121449 0045121 00451 00452 0121453 00454 0121455 0121456 1210457 00458 0121459 00460 00461 00462 00453 00464 00465 00465 1210467 00468 1210469 0047121 121121471 0121472 00473 121121474 00475 00476 00477 1210478 0121479 0121480 0121481 0121482 1210483 0121484

00485

0121486

00487

<00488

0121489 1210490

0121491 00492 00493

C4BE C4BE

C4~E

C4BE C4Cl C4C4 C4C7 C4CA C4CD C4CF C401

C4D4

C4D6 C4D9 C4DC

C40F

C4El

C4E3

60 60

80

AD

2'3

F0 F9

AD

09

80

AD

29

00

A9 C4E5 C4E5 C4E5

C4E5

C4E8

C4EA

C4ED

CD

00

AD

29

C4EF 8D

C4F2

C4F5

80

4C C4F8 C4F8 C4F8 C4F8 C4FB C4FD

AE A9

60 C4FE

C4FE

C4FE C4FE C4FE

C500

A9

AA C51211 C501 C501 C51211

C504

C506

C5tZ19

AD

29

8D

8D C50C C50C C50C C50C 2C

C50F

5121 C5i1 C511

C514

AD

91

MESSAGE

07

CtZI

1217

C0 LSR

1213

DE

1217

DE

1214

DE

2121

MESSIN

POLL

LSR 8TA

LOA LDA AND BEQ

01

CI2I 1121 01

DE

1211

C0 STA ICRVAL

1214

DE

STILON

20

F9

1210

LEAVE

06

DE 1211::: 01

C0 EF

DE

01 01

C0 8TA ICRVAL

20

C3

NOT

;

1216

DE

DIFMES

1216

LOA ORA 8TA

LOA AND BNE LOA

ACK

CMP

BNE

LDA

AND

STA

JMP

MESSAGE

LOX LOA

RTS

DMA

INPUT

;

1210

DMAIN

LOA

TAX

ASSERT

LOA

AND

8TA

STA ICRVAL

FOR

BIT

BVC LDA

STA

01 FE 1211 01

05

FB

0C

FB

C0 DE

CI2I

DE

RESET

WAIT

;

REPTi

;

GOl

IN PHASE

S5380+3 85380+7 S538121+4

#~121121100000

POLL

ICRVAL #'1.121121121112112100 85380+1

S538121+4 #'1.12101001211210 STILON #CMDCPL

ACTIVE

MESSAGE

SO

85380+6 OIFMES

ICRVAL

#~1111211111

8538121+1 NXT

COMPLETE,

S5380+6 #MESSAG

#1210

DATA

BUS

ICRVAL

#'1.11111110 85380+1

DRQ

S538121+5

REPT1 SDMA

(BPNTR),Y

SI-HFT LOAD

TCR

RESET

READ

LOOI-'~

IF

GET

OR

CURRENT FOR

ZERO,

CURHENT

IN

ASSERT UPDATE

READ

LOOK

IF

LOAD

CUF~RENT

FOR

NOT

COMMAND CAN

COMj:.:'ARE

IF

NOT

ICR

GET MASK

ACIO{

RESET

UPDATE

TO

GO

RETURN

GET

MESSAGE

LOAD

MESSAGE

RETURN

ZERO

GET

MASK

ACCUM.

X

ICR

ASSERT RESET UPDATE

TEST

READ

IF

FOR

NOT

DMA

8TORE

TO

TeR

INT.

REG! NO

ASSERT

ACK

I

Cf~

NOT

ZERO,

BE

W/MESSA6E

C!'r1D

COMPLTE,

VAL

BIT

ACt<

ICR

NEXT FOR

PHASE

EVALUATION

VALUE

FOR

IYIESSAGE

VALUE

ASSERT

ICR

DRQ

THERE,

PORT

OAT':')

11\1

FORMAT

STATUS

BUS

• REQ.

V(4LUE

ICR

ACK

BUB

STATUS

f<EG!

S-U

LL

COMPLETE

REJECTED

RETN

DAT~~

DATA

STATUS

BUS

LOOP

BUFFER

ON

OIFf".

EVALUATION

BIT

48

LINE#

LOC

CODE

LINE

121121494 121121495 0121496 121121497 121121498 121121499 012150121 0051211 00502 12112151213 012151214 012151215 121121506 0121507 12112151218 00509 12112151121 0121511 1210512 00513 00514 0121515 1210516 00517 121121518 121121519 12112152121 0121521 121121522 0121523 121121524 00525 121121526 0121527 121121528 121121529 121053121 121121531 1210532 0121533 0121534

C516

C517

C51A

C51C

C51D

C520 C522 C524 C527 C527 C527 C527

C529 C52C

C52F C532 C535 C535 C535 C535

C53-' C538

C539 C53C

C53E C54121

C543 C544

C547 C549

C54A C54D

C54F C551

C554 C554

C557 C55A

C55D

C8 CC

25

DI2I

FI2I E8 EC

26 F0

32

E6

Fe 4C

11

A9

1211

00

1211

80

1211 80

1211

80

1215

A9

00 A8 AA

1215

2C 5121

FB B1

FB

8D 0C

C8 CC

25 D0

F0

E8

EC

26

F0

05

E6

FC 4C

3E

EE

1216 EE

06 EE

06 60

INY CPY BNE

COUNT REPT1

C0

INX

CI2I

BUMP

C5

;

OMAOUT C0 DE:

DMA

CPX

XCNT

BEQ

NXTPH8 BPNTR+1

INC JMP GOl

OUTPUT LOA

#r.tZI121121001211211

ORA

ICRVAL

55380+1

8TA C0 8TA ICRVAL DE

LOOK

STA

FOR LDA

55380+5

REQ

OMA

#00 TAY TAX

DE

DE:

REPT GO

BIT BVC LDA

STA

85380+5

REPT

(BPNTR),Y

SOMA

INY

CI2I

CPY BNE

COUNT

REPT

INX

C0

C5

CI2I C0 CI2I

;

NXTPHS

CPX

XCNT

BEQ

NXTPHS

BPNTR+l

INC

JMP

GO

INC PHSIDX PHASE

INC PHSIDX INC PHSIDX RTS

(DRQ)

INCR. POINTER DONE?

NOT

IF ZERO,

COMPARE

IF GREATER GET

SET

OR

ZERO,

CHECK

EQUAL,

MORE

IYiASK

WITH

X

COUNT

THAN

BYTES

ICR

SET ASSERT

UPDATE

START

ZERO

ZERO SAMPLE

IF

GET

;

WRITE

INC COMPARE

IF

COMPAF~E

IF

MORE

SEND

ICR

DMA

ACCUM

Y

X

DRQ

NOT

SET,

BYTE

Y POINTER

WITH

NOT

Y

EQUAL

WI

EQ,

NEXT THAN MORE

INIT

FROM

EQ.

INCR.

256 DATA

POINTER

TO

RETN

INIT

REPEAT

MULTIPLIER

DONE

BYTES

256

VALUE

Dt=lTA

BUS

VALUE

SEND

f<EPEAT

BLOCK

TO

CHIP

BYTE SEND

CNT

MORE

X

MULTIPLIER

PHASE

BLIMP

f'IISB

INDEX

OR

TRGT

BIT

+3

OPERa

BUMP

MSB

49

FROM

ADORES

DECODE

LOGIC

0'1

o

5 -

NCR

65002

IRQ.

-

LSI39

~6

A3 A2

1

AI AO

R/W

-o.l>i~

£12

DO

•

07

-

...

-

~

-

--

-

....

--

~

-

...

--

"'*

.....

r---

yolO

YI

8

V~

----I

" 1J

~

0..-

....

'"

,...,

---

(XXXOH-

XXX7H)

(XXXCH -

XXX FH)

P'

5380

-7

CS

-i-

DACK

~

A2

-;...

AI

AO

~IOR

-

lOW

--

-

~

DO

•

--

-

.....

•

..

--

•

-

•

----

-

-..-.

•

-

--

•

-

07

--

NCR

087

•

D80

DBP

ATN

BSY

AOt<

RST

MSG

SEL

CIO

REO.

;ro

SCSI

BUS

,

'"\.

""\.

"\.

'\..

"\..

"\.

,

"\

, ,

"\..

""\.

"\...

'\...

,

'\...

,

"-

r

"-

r

"-

,

"\...

1

)

1

)

) ) )

)

1

) ) ) )

)

t

-

I~+

(XXX8H -

XXXBH)

5V

U

1

G

~

066600C

y

LS244

A

IRQ

EOP

RESET

+5V

•

)

~

•

SCSI

SIGNAL

TERMINATION

5V

Il+

,------

I

,

I

,

I

,

-------

~

'\

2201\,

,

"\.

~330f\.

.,

________

..1

1-----

A4. NCR 5381-Differential Pair Option

The NCR device, designed to support transceivers. led pinout package. The NCR single-ended device if the SINGLEND signal (pin active.

differential support remain functional.

for The use of the

the Initiator Command Register reflects the only

5381

is

a 48 pin version of the NCR 5380

external differential pair

These external transceivers are control-

with the additional signals provided

5381

may still operate as a

In

single-ended operation, the signals provided

DIFFERENTIAL ENABLE bit (bit

2

SIGNAL NAME

SINGLEND

in

the higher

2)

is

5)

in

software difference between the two parts. When active, this bit is used to assert the TGS

(pin 14) TARGETMODE bit (port TARGETMODE TARGETMODE is true.) As in the NCR 5385/86, IGS is used to enable the external drivers for the signals ACK (pin 17) and ATN (pin 18) and TGS is used to enable the external drivers for the signals

depending

is

false

signals IGS (pin 18) or

on

the

2,

bit

6).

(IGS is active if

and

TGS

CI D (pin 21), MSG (pin 22) and REQ (pin 23).

The signal differences between the NCR 5380 and the

NCR

5381

are as follows:

DESCRIPTION This signal, when active

mode of operation. When inactive, the NCR operates

These input

in

the differential pair mode.

signals will change from input! output pins to

only pins if the SINGLEND signal

(1)

selects the single-ended

is

false.

status

is

active

110

5381

of

the

(pin 20),

if

36

SINGLEND = 1 SINGLEND = 0

#16

PIN PIN

#15

#19

This signal is asserted whenever the ASSERT DATA

1,

bit

0)

BUS bit (port set (1). and PHASE MATCH are true and both TARGETMODE and ble the external transceivers to drive the data bus.

It

is also asserted when ASSERT DATA BUS

110

and the TARGETMODE bit are

are false. This signal is used to ena-

51

Pin 14

SIGNAL NAME TGS

DESCRIPTION This signal is active when the T ARGETMODE bit and

the

DIFFERENTIAL ENABLE bit are true. It is used to

enable the external transceivers to drive 1/0,

CID,

MSG, and REO.

12

48

25

24

38

IGS

ARB

BSYOUT

SELOUT

RSTOUT

SINGLEND

DO

This signal is active when the TARGETMODE bit is false and the DIFFERENTIAL ENABLE bit is true. It is

used to

enable the external transceivers to drive ACK

and ATN.

The

NCR 5380 chip asserts this signal when the ARBITRATION bit is set and the device has detected a bus free condition. device

This

10

on the bus during the arbitration phase.

signal is active whenever BSY is asserted. This

It is used to assert the proper

signal will be inactive at all other times.

This signal is active if the ASSERT SEL bit is true. Conversely, this signal is inactive if the ASSERT SEL bit is reset.

This

signal is active if the ASSERT RST bit is true.

Conversely, this signal is inactive if the ASSERT RST

bit is reset.

•

DBO DBP

IGS

GND

TGS

SELIN

BSYIN

ACK

ATN

C/D

MSG

REO

SELOUT

NCR

5381

PINOUT

II]]

-5V

NI'"

1~1

I

v

100

T

NCR 5381

NOTE.

TGS,

and

NCR

,-------L

F

(3)

DB7

(4)

DB6

(5)

i5Ei5

(6)

DB4

(7)

DB3

(8)

DB2

(9)

DB1

(10)

DBO

(11) DBP (12) IGS

(17) ACK

(18)

ATN

(14) TGS

(22)

MSG

(21)

CID

(20)

liD

(23)

REO

(25)

BSYOOT

(16) BSYIN (24) SELOUT (15) SELIN (36) DBEN (48) ARB

(38) RSTOUT

(19) RSTIN

(2) SINGLEND

5381

3

2

1

74LS138

r--r>

.. ...

Suggested Differential Pair Interface.

1

15

16

~~

~

13

...1...r,

12

~

11

~

10

9

~[Y-

7

~~

~

2

.l.

T

----.

...

10

13

1

4

(2)

74LS04

...

-,.

...

'"

...

-,.

...

....

...

....

...

....

...

'"

...

-,.

...

....

...

~

...

-,.

...

-,.

...

~

....

..

...

..

....

'"

~

F<

~

1

74LSOO

(1/3)

..

...

..

...

..

...

..

...

..

...

..

...

..

...

..

...

....

..

...

-,.

3

6

8

11

3

6

11

4

~

All

signals

DBEN, and ARB have open collector

require

pull-ups.

from

the NCR

5381

-5V

except IGS,

outputs

3

-------;6

4 1

11

3~

~~

3

ttt!~

3

~2

3

~

...

I 2

--~~

'-

~

__

2 I

1

L-

-

1 2 I

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53

AS.

NCR S3C80 PRODUCT INFORMATION

GENERAL:

The

NCR 53C80 CMOS SCSI interface device

tionally equivalent to the

NMOS NCR 5380 device.

is

funcHowever, this chip does not offer pin compatibility. CMOS and NMOS are entirely different processes with

inherently different device characteristics. All

CMOS

devices are designed to prohibit a condition commonly

referred to as 'latch-up'. When the high current 48

drivers

in

the NCR 53C80 switch, noise level is suffi-

rna

ciently high, the output drivers become more prone to

'latch-up'. Therefore, for the

CMOS design, pin compatibility has been foresaken for reliabilty. Four additional ground lines have been added to increase design stability. Having additional ground signals also allows the output buffers to switch more quickly, creating the added benefit of a faster design. This does not imply that the

NMOS device is marginal

in

any

respect. DIFFERENCES:

To

make the device easier to design with, the NCR

53C80

contains some minor modifications.

nation of each

is

listed below.

An

expla-

Improved The

the

REal

ACK Transition Times

NCR 53C80 has improved the response times of

REal

ACK handshake signals. This has

an

overall impact on achievable transfer rates. This performance improvement has been attained by increasing the number of ground lines, using faster giving cell placement priority to the

CMOS cells, and

REal

ACK signal

paths.

Of

An

Prevents The Possibility

Additional ACK From

Occurring The NCR 5380, upon receipt of

the END

DMA requests (DRa). Mode: bit.

OF DMA status bit and prevents additional

It

If receiving data as

an

EOP signal, sets

does not reset the DMA

an

Initiator and the Target continues to request data for the same bus phase, after receiving

an

EOP pulse, the NCR 5380

will assertACK without issuing a DMA request (DRa). The

NCR 53C80 prevents ACK from being asserted

until the device

is

instructed to continue by writing the

Start DMA Initiator Receive register.

PERFORMANCE:

Spurious

the NCR 5380 is not terminated

If

the floating condition

RST Interrupt

on

the SCSI bus,

on

the input of the RST signal

can generate spurious interrupts.

NCR 53C80 contains

The on the

RST signal to prevent

an

internal 30 uamp pull-up

an

interrupt due to

an

un-terminated bus.

True

End Of DMA Status For Send Operations

If sending data to the NCR 5380 and EOP is asserted on

the last byte, the END OF DMA status bit indicates only that the last byte has been received from the DMA device. There been transferred to the

NCR 53C80 uses bit 7 of the Target Command

The

is

no indication that this byte has

SCSI bus.

register to indicate that the last byte of a DMA transfer has been sent to the

SCSI bus.

Even

though early material on the NCR 53C80 has demonstrated better performance than the 5380,

device characterization was not completed

before this section was printed.

PINOUT:

(JJ

~

I~

RESET

IRQ

DRQ

Ec5P

DACK

VSS

READY

AD

Al

A2

os

7

8

9

10

11

12

13

14

15

16

17 18

19

I~

44 43

NCR

53C80

20

21

22 23 24 25 26 27

13

f3

41

42

40

39

DB2

38

DBl

37

DB0

36

VSS

35

DBP

34

REa

33

ACK

32 1/0

31

VSS

30

CID

29

MSG

28

NCR

54

OB71

48

OB61

RSTI

GNO

BSYI

SEll

ATNI

NC

RESETI

IRO

ORO

EOPI

OACKI

6

7

9

10

11

12

2

3

4

5

8

NCR

53C80

47

46

45

44

43

42

41

40

39

38

37

OB51

GNO

OB41

OB31

OB21

NC

OB11

OBOI

GNO

OBPI

REO

GNO

REAOY

AO

A1

A2

NC

CSI

lOWI

lORI

07

06

13

14

15

16

17

18

19

20

21

22

23

36

35

34

33

32

31

30

29

28

27

26

ACK

1/01

GNO

C/OI

MSGI

NC

DO

01

02

03

04

05

24

55

25

VOO

A6.

SCSI/PLUS *

AMPRO Computers, Inc. is proposing a general enhancement to the SCSI specification which allows

the bus to operate as either a single or multi-master

high speed parallel bus, capable of accessing up to 64

SCSI/PLUS DEVICE TYPES

Operating System Processors

and Co-processors

Communication Servers

Display Controllers

System Resources

Real World Interfaces

EXAMPLES

UNIX MS-DOS CP/M

FORTH Lisp

Prolog

Modems Arcnet

Ethernet

SDLC

Mainframe links

Graphics

Text

Touch

Printer

Time-of-day clock

Speech Protocol Converter DBMS Processor

Array Processor

AID

D/A AC & DC Control

modules. This new bus structure is referred to as SCSI/ PLUS. The table below describes the types of devices that may now be added due to the enhanced SCSI specification.

Spooler

I/O

Examples

of SCSI/ PLUS Devices

* SCSI/ PLUS is a trademark of AMPRO Computers.

Inc.

56

SCSI/ PLUS provides three functional additions to the SCSI specification which allow the bus to operate as either a low-cost single master PLUS is a superset of the original specification, and its operation will not interfere with any existing implementation.

To allow for more complex system configurations, SCSI/ PLUS provides Binary Arbitration and Binary Selection phases. The data bus represents a binary address and accommodates compared to eight tion, four device for a SCSI specification, the arbitration phase is optional.

The addition of a master/ slave mode to the specification provides for a cost-effective slave configuration. This mode allows the design of SCSI/ PLUS Targets which have no on-board intelligence. An optional interrupt protocol allows these "dumb" master that they desire service.

To encourage mended board size and interface connector is defined. The preferred board size is the format with the The

41612-

and connector specification, bussed bon

The SCSI/ PLUS architectural concept has inherent advantages backplane architectures. SCSI/ PLUS is CPU-independent, provides across a ribbon formance operation.

loosely coupled distributed system bus or a

I/O

bus. As proposed, SCSI!

64

physical bus devices,

in

the current specification.

logical units may be associated with each bus

total of

targets to asynchronously notify the bus

proposed

Type C connector. By using this form-factor

cable systems may be implemented.

mUlti-master and low-cost Single-master

256

logical bus devices. As

single-master/

board-level interchangability, a recom-

single-wide Eurocard

double-wide card used as an option.

interface

over

flexibility of form factor, operates

cable bus, and allows both high-per-

connector

traditional

is

backplane or rib-

microprocessor

In

the

SCSI

addi-

in

the

mUlti-

DIN

an

The NCR 5380 is face to connect to the flexibility needed to support the defined modifications, and its popularity with SCSI users guarantees adapters.

The NCR 5380 uses the sert the proper device Arbitration and restricted by the number of bits he is

SCSI data bus, the Binary Arbitration and Binary

on the Selection phases can be easily supported. role the Select Enable Register may be used to generate an interrupt if any bit binary address on the 5380 does not restrict this

The ability to support the master/ slave operation requires independent nals by the bus slave devices and recognition by the bus master of the

5380 provides independent Target operation and can interrupt when a bus phase mismatch occurs if operating as an

As in normal SCSI implementations, the use of on-chip

bus transceivers significantly reduces parts count and

provides for a

PLUS

MOS transceivers is the low leakage current. The NCR

5380 maximum

SCSI! PLUS bus load requirements. Up to 64 devices

may occupy

integrated circuits such as the NCR 5380 are used.

plug compatibility with existing host

design.

SCSI/ PLUS bus positions if low-leakage

ideal part for designing an inter-

SCSI/ PLUS. Its simplicity provides

protocol

Output Data Register to as-

ID onto the SCSI bus during the

Selection phases. Since the user is not

allowed to assert

In

a Target

in

this register matches the

SCSI bus. Here again the NCR

implementation.

control over the SCSI control sig-

newly defined bus phase. The NCR

signal control during

be

configured to generate an

Initiator.

highly reliable, cost effective SCSI/

An

additional advantage of on-chip

leakage current of 50 uA meets the

57

A7. REGISTER REFERENCE CHART

READ

CURRENT SCSI DATA (00)

7 6 5

INITIATOR COMMAND REGISTER

7 6

Assert

MODE REGISTER (02)

7 6 5

Block Mode DMA

TARGET COMMAND REGISTER (03)

76543210

432

DB7

...

DBO

(01)

543

Assert BSY

Assert ACK

Lost Arbitration

Arbitration in Progress

RST

432

Enabte

Enable Parity Interrupt

Enable Parity Checking

Target Mode

2

Assert

Monitor

EOI'

o

Assert Data Bus

Assert ATN

SEL

o

Arbitration

DMA Mode

BSY

interrupt

WRITE

OUTPUT DATA REGISTER (00)

76543210

INITIATOR COMMAND REGISTER

7 6 5

Assert

MODE REGISTER (02)

7 6 5 4 3 2

Block Mode DMA

(01)

432

Assert ACK

Differential

Test Mode

RST

Enable Parity Interrupt

Enable Parity Checking

Target Mode

DB0

o

Assert ATN

Assert

SEL

Assert BSY Enable (NCR 5381)

o

Enable EOP interrupt

Last Byte Sent

CURRENT SCSI BUS STATUS (04)

7 6

_BSY

RST BUS

& STATUS REGISTER (05)

76543210

DMA Request

End

of

INPUT DATA REGISTER (06)

76543210

DMA

543

_

REO

(53C80)

MSG

Interrupt Request

Parity Error

C/D

2 0

I

_DBP

_ SEL

I/O

I I

RESET PARITY/INTERRUPT (07)

76543210

[XlXIXIXIXIX

IxlX

I

Last Byte Sent

SELECT ENABLE REGISTER (04)

76543210

START DMA SEND (05)

7 6 5 4 3 2 o

I

xl xl

START DMA TARGET RECEIVE (06)

76543210

I

xl

xl xl

START DMA INITIATOR

I

xlxlxlxlxlxlx

NOTE: X = DON'T CARE

Assert REO

(53C80)

xl

X I

xl

X I X X

X I X I X I X I X I

RECEIVE

(07)

Ix

I

58

,

NCR

Microelectronics 1635 Aeroplaza Drive Logic Products Marketing Colorado Springs,

(303)

596·5612

TELEX 45·2457

CO

or

(800) 525·2252

Division

80916

Sp

·1051

3/86

Datasheet 5380, 53C80 Datasheet (NCR)

Specifications and Main Features

Frequently Asked Questions

User Manual