Datadelay PDU54-100, PDU54-1000, PDU54-1000C4, PDU54-1000M, PDU54-1000MC4 Datasheet

PDU54

4-BIT, ECL-INTERFACED

data



3

1

12

24

13

N/C

N/C

IN

N/C

PROGRAMMABLE DELAY LINE
(SERIES PDU54)

delay
devices, inc.

FEATURES PACKAGES

N/C

• Digitally programmable in 16 delay steps

• Monotonic delay-versus-address variation

• Precise and stable delays

• Input & outputs fully 100K-ECL interfaced & buffered

• Available in 24-pin DIP (600 mil) socket or SMD

PDU54-xx DIP
PDU54-xxM Military DIP

N/C

GND

N/C
N/C
N/C
N/C
N/C

GND

OUT

N/C
N/C

FUNCTIONAL DESCRIPTION

The PDU54-series device is a 4-bit digitally programmable delay line.
The delay, TDA, from the input pin (IN) to the output pin (OUT) depends
on the address code (A3-A0) according to the following formula:

TDA = TD0 + T

INC

* A

24

1
2
3
4
5
6
7
8
9
10
11
12

IN

23

N/C

22

VEE

21

A3

20

N/C

19

N/C

18

A2

17

A1

16

VEE

15

A0

14

N/C

13

N/C

N/C

GND

N/C
N/C
N/C
N/C
N/C

GND

OUT

N/C

PDU54-xxC4 SMD
PDU54-xxMC4 Mil SMD

PIN DESCRIPTIONS

IN Signal Input
OUT Signal Output
A3-A0 Address Bits
VEE -5 Volts
GND Ground

2

23
3
4
5
6
7
8
9
10
11

N/C

22

VEE

21

A3

20

N/C

19

N/C

18

A2

17

A1

16

VEE

15

A0

14

N/C

where A is the address code, T

is the incremental delay of the device, and TD0 is the inherent delay of

INC

the device. The incremental delay is specified by the dash number of the device and can range from
100ps through 3000ps, inclusively. The address is not latched and must remain asserted during normal
operation.

SERIES SPECIFICATIONS

• Total programmed delay tolerance: 5% or 40ps,
whichever is greater

• Inherent delay (TD0): 3.3ns typical

• Address to input setup (T

• Operating temperature: 0° to 85° C

• Temperature coefficient: 100PPM/°C (excludes TD0)

• Supply voltage VEE: -5VDC ± 0.7V

• Power Supply Current: -300ma typical (50Ω to -2V)

• Minimum pulse width: 3ns or 10% of total delay,

• Minimum period: 8ns or 2 x pulse width, whichever

A3-A0

IN

OUT

TD

A

PW

A

i-1

IN

PW

T

OUT

): 2.9ns

AIS

whichever is greater
is greater

OAX

T

AIS

A

i

DASH NUMBER SPECIFICATIONS

Part

Number

PDU54-100
PDU54-200
PDU54-250
PDU54-400
PDU54-500
PDU54-750
PDU54-1000
PDU54-1200
PDU54-1500
PDU54-2000
PDU54-2500
PDU54-3000

NOTE: Any dash number between 100 and 3000

Incremental Delay

Per Step (ps)

100 ± 50
200 ± 60
250 ± 60

400 ± 80
500 ± 100
750 ± 100

1000 ± 200
1200 ± 200
1500 ± 200
2000 ± 400
2500 ± 400
3000 ± 500

not shown is also available.

Total Delay

Change (ns)

1.50

3.00

3.75

6.00

7.50

11.25

15.00

18.00

22.50

30.00

37.50

45.00

Figure 1: Timing Diagram

1997 Data Delay Devices

Doc #98004 DATA DELAY DEVICES, INC. 1

3/18/98 3 Mt. Prospect Ave. Clifton, NJ 07013

PDU54

APPLICATION NOTES

1.270±.010

.015 TYP.

.070 MAX.

.018 TYP.

ADDRESS UPDATE

The PDU54 is a memory device. As such,
special precautions must be taken when
changing the delay address in order to prevent
spurious output signals. The timing restrictions
are shown in Figure 1.

After the last signal edge to be delayed has
appeared on the OUT pin, a minimum time,
T

, is required before the address lines can

OAX

change. This time is given by the following
relation:

T

where A

= max { (Ai - A

OAX

and Ai are the old and new address

i-1

i-1

) * T

INC

, 0 }

codes, respectively. Violation of this constraint
may, depending on the history of the input signal,
cause spurious signals to appear on the OUT
pin. The possibility of spurious signals persists
until the required T

has elapsed.

OAX

INPUT RESTRICTIONS

There are three types of restrictions on input
pulse width and period listed in the AC
Characteristics table. The recommended

conditions are those for which the delay
tolerance specifications and monotonicity are
guaranteed. The suggested conditions are
those for which signals will propagate through the
unit without significant distortion. The absolute
conditions are those for which the unit will
produce some type of output for a given input.

When operating the unit between the
recommended and absolute conditions, the
delays may deviate from their values at low
frequency. However, these deviations will
remain constant from pulse to pulse if the input
pulse width and period remain fixed. In other
words, the delay of the unit exhibits frequency
and pulse width dependence when operated
beyond the recommended conditions. Please
consult the technical staff at Data Delay Devices
if your application has specific high-frequency
requirements.

Please note that the increment tolerances listed
represent a design goal. Although most delay
increments will fall within tolerance, they are not
guaranteed throughout the address range of the
unit. Monotonicity is, however, guaranteed over
all addresses.

PACKAGE DIMENSIONS

20 19 18 1724 23 22 21

1 2 3 4 5 6 7 8

1.100±.010

11 Equal spaces

each .100±.010

Non-Accumulative

PDU54-xx (Commercial DIP)
PDU54-xxM (Military DIP)

16 15 14 13

.580
MAX.

1211109

Lead Material:

.380
MAX.

Nickel-Iron alloy 42
TIN PLATE

.600

±.005

.010

±.002

Doc #98004 DATA DELAY DEVICES, INC. 2

3/18/98 Tel: [phone] Fax: [phone] http://www.datadelay.com