Datadelay PDU14F-1, PDU14F-10, PDU14F-100, PDU14F-100A4, PDU14F-100B4 Datasheet

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PDU14F
Doc #97002 DATA DELAY DEVICES, INC. 1
1/13/97 3 Mt. Prospect Ave. Clifton, NJ 07013
4-BIT PROGRAMMABLE DELAY LINE (SERIES PDU14F)
FEATURES PACKAGES
Monotonic delay-versus-address variation
Two separate outputs: inverting & non-inverting
Precise and stable delays
Input & outputs fully TTL interfaced & buffered
10 T2L fan-out capability
Fits standard 24-pin DIP socket
Auto-insertable
FUNCTIONAL DESCRIPTION
The PDU14F-series device is a 4-bit digitally programmable delay line. The delay, TDA, from the input pin (IN) to the output pins (OUT, OUT/) depends on the address code (A3-A0) according to the following formula:
TDA = TD0 + T
INC
* A
where A is the address code, T
INC
is the incremental delay of the device, and TD0 is the inherent delay of the device. The incremental delay is specified by the dash number of the device and can range from 0.5ns through 100ns, inclusively. The enable pins (EN/) are held LOW during normal operation. These pins must always be in the same state and may be tied together externally. When these signals are brought HIGH, OUT and OUT/ are forced into LOW and HIGH states, respectively. The address is not latched and must remain asserted during normal operation.
SERIES SPECIFICATIONS
Total programmed delay tolerance: 5% or 1ns,
whichever is greater
Inherent delay (TD0): 9ns typical (OUT)
8ns typical (OUT/)
Setup time and propagation delay:
Address to input setup (T
AIS
): 5ns
Disable to output delay (T
DISO
): 6ns typ. (OUT)
Operating temperature: 0° to 70° C
Temperature coefficient: 100PPM/°C (excludes TD0)
Supply voltage VCC: 5VDC ± 5%
Supply current: I
CCH
= 74ma
I
CCL
= 30ma
Minimum pulse width: 10% of total delay
1997 Data Delay Devices
data
delay devices, inc.
3
24 23 22 21 20 19 18 17 16 15 14 13
1 2 3 4 5 6 7 8 9 10 11 12
OUT/
OUT
EN/
GND
N/C
IN
N/C
GND
N/C N/C
EN/
GND
VCC A0 A1 A2 VCC N/C N/C N/C VCC A3 N/C N/C
PDU14F-xx
DIP
PDU14F-xxA4
Gull-Wing
PDU14F-xxB4
J-Lead
PDU14F-xxM
Military DIP
PDU14F-xxMC4
Military Gull-Wing
PIN DESCRIPTIONS
IN Delay Line Input OUT Non-inverted Output OUT/ Inverted Output A0-A3 Address Bits EN/ Output Enable VCC +5 Volts GND Ground
DASH NUMBER SPECIFICATIONS
Part
Number
Incremental Delay
Per Step (ns)
Total Delay
Change (ns)
PDU14F-.5
.5 ± .3 7.5 ± 1.0
PDU14F-1
1 ± .5 15 ± 1.0
PDU14F-2
2 ± .5 30 ± 1.5
PDU14F-3
3 ± 1.0 45 ± 2.3
PDU14F-4
4 ± 1.0 60 ± 3.0
PDU14F-5
5 ± 1.0 75 ± 3.8
PDU14F-10
10 ± 1.5 150 ± 7.5
PDU14F-15
15 ± 1.5 225 ± 11.3
PDU14F-20
20 ± 2.0 300 ± 15.0
PDU14F-30
30 ± 3.0 450 ± 22.5
PDU14F-40
40 ± 4.0 600 ± 30.0
PDU14F-50
50 ± 5.0 750 ± 37.5
PDU14F-100
100 ± 10.0 1,500 ± 75.0
NOTE: Any dash number between .5 and 100 not
shown is also available.
PDU14F
Doc #97002 DATA DELAY DEVICES, INC. 2
1/13/97 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
APPLICATION NOTES
ADDRESS UPDATE
The PDU14F is a memory device. As such, special precautions must be taken when changing the delay address in order to prevent spurious output signals. The timing restrictions are shown in Figure 1.
After the last signal edge to be delayed has appeared on the OUT pin, a minimum time, T
OAX
, is required before the address lines can change. This time is given by the following relation:
T
OAX
= max { (Ai - A
i-1
) * T
INC
, 0 }
where A
i-1
and Ai are the old and new address codes, respectively. Violation of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the OUT pin. The possibility of spurious signals persists until the required T
OAX
has elapsed.
A similar situation occurs when using the EN/ signal to disable the output while IN is active. In this case, the unit must be held in the disabled state until the device is able to “clear” itself. This is achieved by holding the EN/ signal high and the IN signal low for a time given by:
T
DISH
= Ai * T
INC
Violation of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the OUT pin. The
possibility of spurious signals persists until the required T
DISH
has elapsed.
INPUT RESTRICTIONS
There are three types of restrictions on input pulse width and period listed in the AC Characteristics table. The recommended conditions are those for which the delay tolerance specifications and monotonicity are guaranteed. The suggested conditions are those for which signals will propagate through the unit without significant distortion. The absolute conditions are those for which the unit will produce some type of output for a given input.
When operating the unit between the recommended and absolute conditions, the delays may deviate from their values at low frequency. However, these deviations will remain constant from pulse to pulse if the input pulse width and period remain fixed. In other words, the delay of the unit exhibits frequency and pulse width dependence when operated beyond the recommended conditions. Please consult the technical staff at Data Delay Devices if your application has specific high-frequency requirements.
Please note that the increment tolerances listed represent a design goal. Although most delay increments will fall within tolerance, they are not guaranteed throughout the address range of the unit. Monotonicity is, however, guaranteed over all addresses.
T
DISO
T
OAX
T
AENS
T
ENIS
PW
IN
TD
A
PW
OUT
T
DISH
A3-A0
EN/
IN
OUT
OUT/
Figure 1: Timing Diagram
A
i-1
A
i
T
SKEW
T
AIS
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