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PDU13F |
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3-BIT PROGRAMMABLE |
data |
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® |
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3 |
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DELAY LINE |
delay |
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(SERIES PDU13F) |
devices, inc. |
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FEATURES
∙Digitally programmable in 8 delay steps
∙Monotonic delay-versus-address variation
∙Two separate outputs: inverting & non-inverting
∙Precise and stable delays
∙Input & outputs fully TTL interfaced & buffered
∙10 T2L fan-out capability
∙Fits standard 14-pin DIP socket
∙Auto-insertable
PACKAGES
IN |
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1 |
14 |
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VCC |
IN |
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1 |
16 |
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VCC |
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N/C |
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2 |
13 |
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N/C |
N/C |
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15 |
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N/C |
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2 |
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N/C |
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3 |
12 |
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N/C |
N/C |
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3 |
14 |
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N/C |
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OUT |
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4 |
11 |
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N/C |
N/C |
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4 |
13 |
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N/C |
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OUT/ |
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5 |
10 |
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A0 |
OUT |
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5 |
12 |
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N/C |
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EN/ |
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6 |
9 |
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A1 |
OUT/ |
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6 |
11 |
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A0 |
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GND |
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7 |
8 |
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A2 |
EN/ |
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7 |
10 |
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A1 |
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GND |
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8 |
9 |
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A2 |
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PDU13F-xx |
DIP |
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PDU13F-xxA2 Gull-Wing |
PDU13F-xxMC3 |
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PDU13F-xxB2 J-Lead |
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Military Gull-Wing |
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PDU13F-xxM |
Military DIP |
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FUNCTIONAL DESCRIPTION |
PIN DESCRIPTIONS |
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The PDU13F-series device is a 3-bit digitally programmable delay line. |
IN |
Delay Line Input |
The delay, TDA, from the input pin (IN) to the output pins (OUT, OUT/) |
OUT |
Non-inverted Output |
depends on the address code (A2-A0) according to the following formula: |
OUT/ |
Inverted Output |
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A2 |
Address Bit 2 |
TDA = TD0 + TINC * A |
A1 |
Address Bit 1 |
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A0 |
Address Bit 0 |
where A is the address code, TINC is the incremental delay of the device, |
EN/ |
Output Enable |
and TD0 is the inherent delay of the device. The incremental delay is |
VCC |
+5 Volts |
specified by the dash number of the device and can range from 0.5ns |
GND |
Ground |
through 50ns, inclusively. The enable pin (EN/) is held LOW during
normal operation. When this signal is brought HIGH, OUT and OUT/ are forced into LOW and HIGH states, respectively. The address is not latched and must remain asserted during normal operation.
SERIES SPECIFICATIONS
∙Total programmed delay tolerance: 5% or 1ns,
whichever is greater
∙Inherent delay (TD0): 6ns typical (OUT)
5.5ns typical (OUT/)
∙Setup time and propagation delay: Address to input setup (TAIS): 6ns
Disable to output delay (TDISO): 6ns typ. (OUT)
∙Operating temperature: 0° to 70° C
∙Temperature coefficient: 100PPM/°C (excludes TD0)
∙Supply voltage VCC: 5VDC ± 5%
∙Supply current: ICCH = 45ma
ICCL = 20ma
∙Minimum pulse width: 20% of total delay
DASH NUMBER SPECIFICATIONS
Part |
Incremental Delay |
Total Delay |
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Number |
Per Step (ns) |
Change (ns) |
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PDU13F-.5 |
.5 ± .3 |
3.5 ± 1.0 |
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PDU13F-1 |
1 |
± .4 |
7 ± 1.0 |
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PDU13F-2 |
2 |
± .4 |
14 |
± 1.0 |
PDU13F-3 |
3 |
± .5 |
21 |
± 1.1 |
PDU13F-5 |
5 |
± .6 |
35 |
± 1.8 |
PDU13F-10 |
10 |
± 1.0 |
70 |
± 3.5 |
PDU13F-15 |
15 |
± 1.3 |
105 ± 5.3 |
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PDU13F-20 |
20 |
± 1.5 |
140 ± 7.0 |
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PDU13F-40 |
40 |
± 2.0 |
280 |
± 14.0 |
PDU13F-50 |
50 |
± 2.5 |
350 |
± 17.5 |
NOTE: Any dash number between .5 and 50 not shown is also available.
©1997 Data Delay Devices
Doc #97001 |
DATA DELAY DEVICES, INC. |
1 |
1/10/97 |
3 Mt. Prospect Ave. Clifton, NJ 07013 |
PDU13F
APPLICATION NOTES
ADDRESS UPDATE |
possibility of spurious signals persists until the |
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required TDISH has elapsed. |
The PDU13F is a memory device. As such, |
INPUT RESTRICTIONS |
special precautions must be taken when |
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changing the delay address in order to prevent |
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spurious output signals. The timing restrictions |
There are three types of restrictions on input |
are shown in Figure 1. |
pulse width and period listed in the AC |
After the last signal edge to be delayed has |
Characteristics table. The recommended |
conditions are those for which the delay |
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appeared on the OUT pin, a minimum time, |
tolerance specifications and monotonicity are |
TOAX, is required before the address lines can |
guaranteed. The suggested conditions are |
change. This time is given by the following |
those for which signals will propagate through the |
relation: |
unit without significant distortion. The absolute |
TOAX = max { (Ai - A i-1) * TINC , 0 } |
conditions are those for which the unit will |
produce some type of output for a given input. |
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where A i-1 and Ai are the old and new address |
When operating the unit between the |
codes, respectively. Violation of this constraint |
recommended and absolute conditions, the |
may, depending on the history of the input signal, |
delays may deviate from their values at low |
cause spurious signals to appear on the OUT |
frequency. However, these deviations will |
pin. The possibility of spurious signals persists |
remain constant from pulse to pulse if the input |
until the required TOAX has elapsed. |
pulse width and period remain fixed. In other |
A similar situation occurs when using the EN/ |
words, the delay of the unit exhibits frequency |
and pulse width dependence when operated |
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signal to disable the output while IN is active. In |
beyond the recommended conditions. Please |
this case, the unit must be held in the disabled |
consult the technical staff at Data Delay Devices |
state until the device is able to “clear” itself. This |
if your application has specific high-frequency |
is achieved by holding the EN/ signal high and |
requirements. |
the IN signal low for a time given by: |
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TDISH = Ai * TINC |
Please note that the increment tolerances listed |
represent a design goal. Although most delay |
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Violation of this constraint may, depending on |
increments will fall within tolerance, they are not |
guaranteed throughout the address range of the |
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the history of the input signal, cause spurious |
unit. Monotonicity is, however, guaranteed over |
signals to appear on the OUT pin. The |
all addresses. |
A2-A0 |
A i-1 |
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Ai |
TAENS |
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TOAX |
TAIS |
EN/ |
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TENIS |
PWIN |
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TDISH |
IN |
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TDA |
PWOUT |
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TDISO |
OUT
TSKEW
OUT/
Figure 1: Timing Diagram
Doc #97001 |
DATA DELAY DEVICES, INC. |
2 |
1/10/97 |
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com |