DADD PDU1032H-5, PDU1032H-5C4, PDU1032H-5M, PDU1032H-5MC4, PDU1032H-6, PDU1032H-6C4, PDU1032H-6M, PDU1032H-6MC4, PDU1032H-8, PDU1032H-8C4, PDU1032H-8M, PDU1032H-8MC4, PDU1032H-15M, PDU1032H-15MC4, PDU1032H-1C4, PDU1032H-1M, PDU1032H-1MC4, PDU1032H-2, PDU1032H-20, PDU1032H-20C4, PDU1032H-20MC4, PDU1032H-2C4, PDU1032H-0.5, PDU1032H-0.5C4, PDU1032H-0.5M, PDU1032H-0.5MC4, PDU1032H-1, PDU1032H-10, PDU1032H-2M, PDU1032H-2MC4, PDU1032H-3, PDU1032H-3C4, PDU1032H-3M, PDU1032H-3MC4, PDU1032H-4, PDU1032H-4C4, PDU1032H-4M, PDU1032H-4MC4, PDU1032H-10C4, PDU1032H-10M, PDU1032H-10MC4, PDU1032H-12, PDU1032H-12C4, PDU1032H-12M, PDU1032H-12MC4, PDU1032H-15, PDU1032H-15C4 Datasheet

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DADD PDU1032H-5, PDU1032H-5C4, PDU1032H-5M, PDU1032H-5MC4, PDU1032H-6, PDU1032H-6C4, PDU1032H-6M, PDU1032H-6MC4, PDU1032H-8, PDU1032H-8C4, PDU1032H-8M, PDU1032H-8MC4, PDU1032H-15M, PDU1032H-15MC4, PDU1032H-1C4, PDU1032H-1M, PDU1032H-1MC4, PDU1032H-2, PDU1032H-20, PDU1032H-20C4, PDU1032H-20MC4, PDU1032H-2C4, PDU1032H-0.5, PDU1032H-0.5C4, PDU1032H-0.5M, PDU1032H-0.5MC4, PDU1032H-1, PDU1032H-10, PDU1032H-2M, PDU1032H-2MC4, PDU1032H-3, PDU1032H-3C4, PDU1032H-3M, PDU1032H-3MC4, PDU1032H-4, PDU1032H-4C4, PDU1032H-4M, PDU1032H-4MC4, PDU1032H-10C4, PDU1032H-10M, PDU1032H-10MC4, PDU1032H-12, PDU1032H-12C4, PDU1032H-12M, PDU1032H-12MC4, PDU1032H-15, PDU1032H-15C4 Datasheet

PDU1032H

5-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU1032H)

data 3 ® delay

devices, inc.

FEATURES

Digitally programmable in 32 delay steps

Monotonic delay-versus-address variation

Precise and stable delays

Input & outputs fully 10KH-ECL interfaced & buffered

Fits 32-pin DIP socket

PACKAGES

GND

 

1

32

 

GND

 

 

 

 

 

 

 

N/C

1

24

 

N/C

 

 

 

ENB

 

2

31

 

OUT

N/C

2

23

 

N/C

 

 

 

 

 

 

OUT

3

22

 

A2

 

 

 

 

 

 

GND

4

21

 

A1

 

 

 

 

 

 

ENB

5

20

 

VEE

 

 

 

 

 

 

N/C

6

19

 

A0

 

 

 

 

 

 

N/C

7

18

 

N/C

A0

 

7

26

 

A1

N/C

8

17

 

N/C

 

 

GND

9

16

 

A4

 

 

 

 

 

 

 

VEE

 

8

25

 

A2

ENB

10

15

 

VEE

 

 

 

GND

 

9

24

 

GND

N/C

11

14

 

A3

 

 

IN

12

13

 

N/C

 

 

 

 

 

 

 

IN

 

11

 

 

 

PDU1032H-xxC4

SMD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PDU1032H-xxMC4 Mil SMD

A3

 

15

 

 

 

PDU1032H-xx

DIP

 

 

 

 

 

 

 

 

 

 

VEE

 

16

17

 

A4

PDU1032H-xxM Mil DIP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FUNCTIONAL DESCRIPTION

PIN DESCRIPTIONS

The PDU1032H-series device is a 5-bit digitally programmable delay line.

IN

Signal Input

The delay, TDA, from the input pin (IN) to the output pin (OUT) depends

OUT

Signal Output

on the address code (A4-A0) according to the following formula:

A0-A4

Address Bits

 

ENB

Output Enable

TDA = TD0 + TINC * A

VEE

-5 Volts

 

GND

Ground

where A is the address code, TINC is the incremental delay of the device, and TD0 is the inherent delay of the device. The incremental delay is specified by the dash number of the device and can range from 0.5ns through 20ns, inclusively. The enable pin (ENB) is held LOW during normal operation. When this signal is brought HIGH, OUT is forced into a LOW state. The address is not latched and must remain asserted during normal operation.

SERIES SPECIFICATIONS

Total programmed delay tolerance: 5% or 2ns,

whichever is greater

Inherent delay (TD0): 5.5ns typical for dash numbers

up to 5, greater for larger #’s

Setup time and propagation delay: Address to input setup (TAIS): 3.6ns

Disable to output delay (TDISO): 1.7ns typical

Operating temperature: 0° to 70° C

Temperature coefficient: 100PPM/°C (excludes TD0)

Supply voltage VEE: -5VDC ± 5%

Power Dissipation: 615mw typical (no load)

Minimum pulse width: 20% of total delay

DASH NUMBER SPECIFICATIONS

Part

Incremental Delay

Total

Number

Per Step (ns)

Delay (ns)

PDU1032H-.5

0.5 ± 0.3

15.5 ± 2.0

PDU1032H-1

1.0 ± 0.5

31

± 2.0

PDU1032H-2

2.0 ± 0.5

62

± 3.1

PDU1032H-3

3.0 ± 1.0

93

± 4.6

PDU1032H-4

4.0 ± 1.0

124 ± 6.2

PDU1032H-5

5.0 ± 1.0

155 ± 7.8

PDU1032H-6

6.0 ± 1.0

186 ± 9.3

PDU1032H-8

8.0 ± 1.0

248

± 12.4

PDU1032H-10

10.0 ± 1.5

310

± 15.5

PDU1032H-12

12.0 ± 1.5

372

± 18.6

PDU1032H-15

15.0 ± 1.5

465

± 23.2

PDU1032H-20

20.0 ± 2.0

620

± 31.0

NOTE: Any dash number between .5 and 20 not shown is also available.

©1997 Data Delay Devices

Doc #97045

DATA DELAY DEVICES, INC.

1

12/17/97

3 Mt. Prospect Ave. Clifton, NJ 07013

PDU1032H

APPLICATION NOTES

ADDRESS UPDATE

The PDU1032H is a memory device. As such, special precautions must be taken when changing the delay address in order to prevent spurious output signals. The timing restrictions are shown in Figure 1.

After the last signal edge to be delayed has appeared on the OUT pin, a minimum time, TOAX, is required before the address lines can change. This time is given by the following relation:

TOAX = max { (Ai - A i-1) * TINC , 0 }

where A i-1 and Ai are the old and new address codes, respectively. Violation of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the OUT pin. The possibility of spurious signals persists until the required TOAX has elapsed.

A similar situation occurs when using the ENB signal to disable the output while IN is active. In this case, the unit must be held in the disabled state until the device is able to “clear” itself. This is achieved by holding the ENB signal high and the IN signal low for a time given by:

TDISH = Ai * TINC

Violation of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the OUT pin. The

possibility of spurious signals persists until the required TDISH has elapsed.

INPUT RESTRICTIONS

There are three types of restrictions on input pulse width and period listed in the AC Characteristics table. The recommended conditions are those for which the delay tolerance specifications and monotonicity are guaranteed. The suggested conditions are those for which signals will propagate through the unit without significant distortion. The absolute conditions are those for which the unit will produce some type of output for a given input.

When operating the unit between the recommended and absolute conditions, the delays may deviate from their values at low frequency. However, these deviations will remain constant from pulse to pulse if the input pulse width and period remain fixed. In other words, the delay of the unit exhibits frequency and pulse width dependence when operated beyond the recommended conditions. Please consult the technical staff at Data Delay Devices if your application has specific high-frequency requirements.

Please note that the increment tolerances listed represent a design goal. Although most delay increments will fall within tolerance, they are not guaranteed throughout the address range of the unit. Monotonicity is, however, guaranteed over all addresses.

A4-A0

A i-1

Ai

TAENS

TOAX

TAIS

ENB

 

 

TENIS

PWIN

TDISH

IN

 

 

TDA

PWOUT

TDISO

OUT

 

 

 

Figure 1: Timing Diagram

Doc #97045

DATA DELAY DEVICES, INC.

2

12/17/97

Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

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