Cypress Semiconductor CY7C466A-25PTC, CY7C466A-25JC, CY7C460A-10PC, CY7C460A-10JC, CY7C462A-10PTC Datasheet
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Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs
CY7C460A/CY7C462A
CY7C464A/CY7C466A
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 4, 1999
Features
• High-speed, low-power, fir st-in first-out (FIFO)
memories
• 8K x 9 FIFO (CY7C460A)
• 16K x 9 FIFO (CY7C462A)
• 32K x 9 FIFO (CY7C464A)
• 64K x 9 FIFO (CY7C466A)
• 10-ns access times, 20- ns read/write cycl e ti mes
• High-speed 50-MHz read/write independent of
depth/width
• Low operat i n g power
—I
CC
= 60 mA
—I
SB
=8 mA
• Asynchr onous read/write
• Empty and Full flags
• Half Full flag (in standalone mode)
• Retransmit (in standalone mode)
• TTL-compatible
• Width and Depth Expansion Capabili ty
•
5V ± 10% supply
• PLCC, LCC, 300-mil and 600-mil DIP packaging
• Three-state outputs
• Pin compatibl e density upgrade to CY7C42X/ 46X family
• Pin compatible and functionall y equival ent to IDT7205,
IDT7206, IDT7207, IDT7208
Functional Description
The CY7C460A, CY7C462A, CY7C4 64A, and CY7C46 6A are
respectivel y , 8K , 16K, 32K, and 64K words b y 9-bit wi de first-in
first-out (FIFO) memories. Each FIFO memory is organized
such that the data is read in the same sequential order that it
was written. Full and Empty flags are provi ded to pre ven t over run and underrun. Three additional pins are also provided to
facilitate unlimited expansion in width, depth, or both. The
depth expansi on technique st eers the cont rol signals fr om one
device to another by passing tokens.
The read and write operations may be asynchronous; each
can occur at a rate of up to 50 M Hz. The write ope ration o ccurs
when the Write (W
) signal is LOW. Read occurs when Read
(R
) goes LOW. The nine data outputs go to the high-imped-
ance state when R
is HIGH.
A Half Full (HF
) output flag is pr ovi ded that i s val id in th e standalone (single device) and width expansion configurations. In
the depth expan sion configur ation, this pin pro vides the expan sion out (XO
) info rmation tha t is used t o tell the ne xt FIFO tha t
it will be activated.
In the standalone and width expansion configur ati ons, a LOW
on the Retransmit (RT
) input causes the FIFOs to retransmit
the data. Read Enab le ( R
) and Write Enab le (W) must bot h be
HIGH during a retransmit cycle, and then R
is used to access
the data.
The CY7C460A, CY7C462A, CY7C4 64A, and CY7C46 6A are
fabricated usi ng Cy press’s adv anced 0.5µ RAM3 CMOS tech nology. Input ESD protection is greater than 2000V and
latch-up is prevented by careful layout and the use of guard
rings.
32K x
LogicBlock Diagram
Pin
Configurations
1
2
3
4
5
6
7
8
9
10
11
12
15
16
17
18
19
20
24
23
22
21
13
14
25
28
27
26
Top View
DIP
W
D
8
D
3
D
2
D
1
D
0
XI
FF
Q
0
Q
1
Q
2
GND
V
CC
D
4
FL/RT
MR
EF
XO/HF
Q
7
R
PLCC/LCC
Top View
Q
3
Q
8
D
5
D
6
D
7
Q
6
Q
5
Q
4
4 3 2 1 32 31 30
14 15 16 17 18 19 20
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
FL
/RT
MR
EF
XO/HF
Q
7
D
6
Q
6
D
7
NC
READ
CONTROL
WRITE
CONTROL
WRITE
POINTER
RESET
LOGIC
EXPANSION
LOGIC
RAM ARRAY
8K x 9
16K x 9
9
DATAINPUTS
(D
0
−
D8)
THREE–
STATE
BUFFERS
DATAOUTPUTS
(Q0-Q8)
W
READ
POINTER
FLAG
LOGIC
R
XI
EF
FF
XO/HF
MR
FL/RT
D
2
D
1
D
0
XI
FF
Q
0
Q
1
NC
Q
2
DDWNCVDD
3
8
cc45
Q
Q
GND
NC
R
Q
Q
3
8
4
5
C46XA–1
C46XA–2
C46XA–3
7C460A
7C462A
7C464A
7C460A
7C462A
7C464A
64K x 9
7C466A
7C466A
DUAL PORT
CY7C460A/CY7C462A
CY7C464A/CY7C466A
2
Maximum Ratings
(Above which the useful life may be impaired. F or user guidelines, not tested.)
Storage Temperature. .. ............. .. ............. .. .–65
°
C to +150°C
Ambient Temperature with
Power Applied.............................................–55
°
C to +125°C
Supply Voltage to Ground Potential...............–0.5V to +7.0V
DC V oltage Applied to Outputs
in High Z State............................................... –0.5V to +7.0V
DC Input Voltage............................................–0.5V to +7.0V
Power Dissipation ..........................................................1.0W
Output Current, into Outputs (LOW)............................20 mA
Static Discharge Voltage.................... .. ............. .. .. ....>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Selection Guide
7C460A-10
7C462A-10
7C464A-10
7C466A-10
7C460A-15
7C462A-15
7C464A-15
7C466A-15
7C460A-25
7C462A-25
7C464A-25
7C466A-25
Frequency (MHz) 50 40 28.5
Maximum Access Time (ns) 10 15 25
Operating Range
Range
Ambient
Temperature
V
CC
Commercial 0°C to + 70°C 5V ± 10%
Industrial –40°C to +85°C 5V ± 10%
Military
[1]
–55°C to +125°C 5V ± 10%
Electrical Characteristics
Over the Operating Range
[2]
Parameter Description Tes t Condi ti ons
7C460A/462A/464A/466A
(-10,-15,-25)
UnitMin. Max.
V
OH
Output HIGH Voltage VCC = Min., IOH = −2.0 mA 2.4 V
V
OL
Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 V
V
IH
Input HIGH Voltage 2.2 V
CC
V
V
IL
Input LOW Voltage
−0.5
0.8 V
I
IX
Input Leakage Current GND < VI < V
CC
–10 +10
µA
I
OZ
Output Leakage Current R > VIH, GND < VO < V
CC
–10 +10
µA
I
CC
Operating Current VCC = Max.,
I
OUT
= 0 mA, Freq. = 20 MHz
60 mA
I
SB
Standby Current All Inpu ts = VIH min. 8 mA
Capacitance
[4]
Parameter Description Test Conditions Max. Unit
C
IN
Input Capacitance TA = 25°C, f = 1 MHz,
V
CC
= 4.5V
10 pF
C
OUT
Output Capacitance 12 pF
Notes:
1. T
A
is the “instant on” case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 1 second.
4. Tested initially and after any design or process changes that may affect these parameters.
CY7C460A/CY7C462A
CY7C464A/CY7C466A
3
AC Test Loads and Waveforms
3.0V
5V
OUTPUT
R1 500
Ω
R2
333
Ω
30pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤
5ns
≤
5
ns
5V
OUTPUT
R1 500
Ω
R2
333
Ω
5pF
INCLUDING
JIG AND
SCOPE
OUTPUT 2V
Equivalent to: THÉ VENIN EQUIVALENT
(b)
C460A–4
C460A–5
C460A–6
(a)
ALL INPUT PULSES
200
Ω
Switching Characteristics
Over the Operati ng Range
[2, 5]
Parameter Description
7C460A-10
7C462A-10
7C464A-10
7C466A-10
7C460A-15
7C462A-15
7C464A-15
7C466A-15
7C460A-25
7C462A-25
7C464A-25
7C466A-25
UnitMin. Max. Min. Max. Min. Max.
t
RC
Read Cycle Time 20 25 35 ns
t
A
Access Time 10 15 25 ns
t
RR
Read Recovery Time 10 10 10 ns
t
PR
Read Pulse Width 10 15 25 ns
t
LZR
Read LOW to Low Z 3 3 3 ns
t
DVR
[6]
Data Valid After Read HIGH 3 3 3 ns
t
HZR
[6]
Read HIGH to High Z 15 15 18 ns
t
WC
Write Cycle Time 20 25 35 ns
t
PW
Write Pulse Width 10 15 25 ns
t
HWZ
Write HIGH to Low Z 5 5 5 ns
t
WR
Write Recovery Time 10 10 10 ns
t
SD
Data Set-Up Time 9 9 9 ns
t
HD
Data Hold Time 0 0 0 ns
t
MRSC
MR Cycle Time 20 25 35 ns
t
PMR
MR Pulse Width 10 15 25 ns
t
RMR
MR Recovery Time 10 10 10 ns
t
RPW
Read HIGH to MR HIGH 10 15 25 ns
t
WPW
Write HIGH to MR HIGH 10 15 25 ns
t
RTC
Retransmit Cyc le Ti me 20 25 35 ns
t
PRT
Retransmit Pulse W idt h 10 15 25 ns
t
RTR
Retransmit Reco very Time 10 10 10 ns
t
EFL
MR to EF LOW 20 25 35 ns
t
HFH
MR to HF HIGH 20 25 35 ns
t
FFH
MR to FF HIGH 20 25 35 ns
t
REF
Read LOW to EF LOW 10 15 25 ns
t
RFF
Read HIGH to FF HIGH 10 15 25 ns
Notes:
5. Test conditions assume signal transmission time of 5 ns or less, timing reference levels of 1.5V and output loading of the specified I
OL/IOH
and 30-pF load
capacitance, as in part (a) of AC Test Loads, unless otherwise specified.
6. t
HZR
and t
DVR
use capacitance loading as in part (b) of AC Test Loads.
CY7C460A/CY7C462A
CY7C464A/CY7C466A
4
t
WEF
Write HIGH to EF HIGH 10 15 25 ns
t
WFF
Write LOW to FF LOW 10 15 25 ns
t
WHF
Write LOW to HF LOW 10 15 35 ns
t
RHF
Read HIGH to HF HIGH 10 15 35 ns
t
RAE
Effective Read from Write
HIGH
10 15 25 ns
t
RPE
Effective Rea d P ulse Wi dth
After EF
HIGH
10
15 25 ns
t
WAF
Effective Write from Read
HIGH
10 15 25 ns
t
WPF
Effective Write Pulse
Width After FF
HIGH
10
15 25 ns
t
XOL
Expansion Out LOW
Delay from Clock
10 15 25 ns
t
XOH
Expansion Out HIGH
Delay from Clock
10 15 25 ns
Switching Characteristics
Over the Operati ng Range
[2, 5]
(continued)
Parameter Description
7C460A-10
7C462A-10
7C464A-10
7C466A-10
7C460A-15
7C462A-15
7C464A-15
7C466A-15
7C460A-25
7C462A-25
7C464A-25
7C466A-25
UnitMin. Max. Min. Max. Min. Max.
CY7C460A/CY7C462A
CY7C464A/CY7C466A
5
Switching Waveforms
[7]
Notes:
7. A HIGH-to-LOW transition of either the write or read strobe causes a HIGH-to-LOW transition of the responding flag. Correspondingly, a LOW- to-HIGH strobe
transition causes a LOW-to-HIGH flag transition.
8. W
and R = VIH around the rising edge of MR.
9. t
MSRC
= t
PMR
+ t
RMR
Asynchronous Read and Write
C460A–7
DATA VALIDDATA VALID
DATA VALID DATA VALID
t
SD
t
HD
t
RC
t
PR
t
A
t
RR
t
A
t
LZR
t
DVR
t
HZR
t
WC
t
PW
t
WR
R
Q
0
−
Q
8
W
D
0
−
D
8
t
SD
t
HD
t
PW
Master Reset
MR
R,W
HF
FF
EF
t
MRSC
t
PMR
t
EFL
t
HFH
t
FFH
t
RPW
t
WPW
t
RMR
C460A–8
[9]
[8]
HALF FULL+1HALF FULL HALF FULL
W
R
HF
t
WHF
t
RHF
HalfFullFlag
C460A–9
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