Consumer Microcircuits Limited FX009ALS, FX009ALG, FX009AJ Datasheet

Features/Applications

CML Semiconductor Products

PRODUCT INFORMATION

Low-Noise Digitally Controlled

FX009A

Amplifier Array

Publication D/009A/3 July 1994

8 Digitally Controlled Low-Noise
Amplifiers

15 Gain/Attenuation Steps
7 Trimmers, with a ± 3dB Range in

0.43dB Steps
1 'Volume' Trimmer, with a ± 14dB

Range in 2.0dB Steps

SERIAL CLOCK INPUT

SERIAL DATA INPUT

V

DD

V

BIAS

Ch1

Ch2

Ch3

1

2

3

16

12345678

16-LINE STEP CONTROLS TO AMPLIFIERS 1 to 8

OUTPUT MUTE - POWERSAVE*

V

BIAS

*

V

BIAS

*

8 - BIT

SERIAL DATA INPUT

AND

LINE DECODERS

8-Bit Serial Data Control
Output Mute/Powersave Function
Audio and Data Gain Control

Applications
Cellular, PMR, PABX Applications

LOAD/LATCH

LOAD/LATCH

V

5

*

V

BIAS

*

6

SS

Ch5

Ch6

FX009A

V

BIAS

*

7

Ch7

V

4

Ch4

BIAS

*

V

BIAS

4321 56 7

CONTROLLED AUDIO OUTPUT LINES

Fig.1 Functional Block Diagram

Brief Description

The FX009A Digitally Adjustable Amplifier Array is
intended to replace trimmer potentiometers and volume
controls in Cellular, PMR, Telephony and
Communications applications where d.c., voice or data
signals need adjustment.

The FX009A is a low-noise single-chip LSI consisting
eight digitally controlled amplifier stages, each with 15
distinct gain/attenuation steps. Control of each
individual amplifier is by an 8-bit serial data stream.
Seven of the amplifier stages offer a +/-3dB range in
steps of 0.43dB, whilst the remaining amplifier offers a
+/-14dB range in steps of 2dB, and is intended for
volume control applications. Each amplifier includes a
16th 'Mute' state which sets the output to bias (VDD/2)
and powersaves the entire section. Minimum current
drain may be achieved by muting all eight sections.

V

BIAS

*

V

8 - VOLUME

BIAS

8

Ch8

This product replaces the need for manual trimming of
audible signals by using the host microprocessor to
digitally control the set-up of all audio levels.

Applications include:

(i) Control, adjustment and set-up of communications
equipment by an Intelligent ATE without manual
intervention – eg. Deviation, Microphone and L/S
Level, Rx Audio Level etc.

(ii) Automatic Dynamic Compensation of drift caused
by variations in temperature, linearity, etc.

(iii)Fully automated servicing and re-alignment.
The FX009A is a low-power, single 5-volt CMOS

device available in both 24-pin DIL and SMD package
versions.

1

Pin Number Function

FX009A

J

FX009A

LG/LS

1

1

Serial Clock : This external clock pulse input is used to “clock in” the Control Data.

See Figure 4, Data Load Timing. This input has an internal 1MΩ pullup resistor.

2

2

Load/Latch : Governs the loading and execution of the control data. During serial

data loading this input should be kept at a logical '0' to ensure that data rippling past
the latches has no effect. When all 8 bits have been loaded, this input should be
strobed '0' ⇒ '1' ⇒ '0' to latch the new data in. Data is executed on the falling edge
of the strobe. If the Load/Latch input is used this pin should be left open circuit. This
input has an internal 1MΩ pullup resistor.

3

3

Load/Latch : The inverted Load/Latch input. This function governs the loading and

execution of the control data. During serial data loading this input should be kept at a
logical '1' to ensure that data rippling past the latches has no effect. When all 8 bits

have been loaded, this input should be strobed '1' - '0' - '1' to latch the new data in.
Data is executed on the rising edge of the strobe. If the Load/Latch input is used this
pin should be left open circuit. This input has an internal 1MΩ pulldown resistor.

4

4

Ch1 Input :

Analogue Inputs :

These individual amplifier inputs are self-biasing, a.c. input

5

5

Ch2 Input :

analogue signals must be capacitively coupled to these pins,
as shown in Figure 2.

6
7
8

6
7
8

Ch3 Input :
Ch4 Input :
V

: The output of the on-chip bias circuitry, held at VDD/2. This pin should be

BIAS

decoupled to VSS as shown in Figure 2.

In the powersave modes the inputs are biased at VDD/2.
Note that amplifiers Ch1 to Ch8 are 'inverting amplifiers.'

9
10
11
12
13
14
15
16
17
18
19
20
21
22

9
10
11
12
13
14
15
16
17
18
19
20
21
22

Ch5 Input :

Analogue Inputs :
Ch6 Input :
Ch7 Input :
Ch8 Input :
VSS : Negative supply rail (GND).
Ch8 Output :
Ch7 Output :

Analogue Outputs :

The individual "Gain Controlled" amplifier outputs.

Ch1 to Ch7 range from -3dB to +3dB in 0.43dB steps, Ch8

Ch6 Output :

could be utilized as a volume control, ranging from -14dB to

+14dB in 2.0dB steps.

Ch5 Output :

In the powersave mode the selected output is biased at VDD/2.
No internal connection. Do not use.

Ch4 Output :
Ch3 Output :

Analogue Outputs

Note that amplifiers Ch1 to Ch8 are 'inverting amplifiers.'

Ch2 Output :
Ch1 Output :

23
24

23
24

VDD : Positive supply rail. A single +5-volt power supply is required.
Control Data Input : Operation of the 8 amplifier channels (Ch1 – Ch8) is controlled

by the 8 bits of data entered serially at this pin . The data is entered (bit 7 to bit 0) on
the rising edge of the external Serial Clock. The data format is described in Tables 1,
2 and Figure 4. This input has an internal 1MΩ pullup resistor.

2