Compaq DH-64BAA-AA - AlphaServer - ES40, AlphaServer ES40 Technical Brief
Compaq AlphaServer ES40 Systems
Technical Summary
Contents
System Overview 1
Features and Benefits 2
Third-Generation Alpha Chip 2
Chip Operation
Alpha 21264 Features
Model Variants 3
CPU Upgrades 3
System Packaging 3
Chassis, Pedestal View
Chassis, Tower View
Rackmount Chassis
Architecture 4
System Block Diagram
System Board 5
Component and Connector Locations
Processor Module 6
Processor Configuration Rules
Memory 6
Memory Options
Memory Configuration
Memory Motherboard
Memory Performance Considerations
Memory Arrays and Sets on Memory Motherboards
System I/O 8
Block Diagram of I/O Control
I/O Implementation
I/O Configuration Rules
I/O Ports
System Control 9
Storage 9
Fibre Channel
RAID (Redundant Array of Independent Disks)
Server Management 9
Operational Management
Platform Management
Error Reporting
Security 10
Reliability and Availability Features 10
Processor Features
Memory Features
I/O Features
System Features
Installation and Maintenance 11
Clustering 11
PCI to Memory Channel Interconnect
Operating System Support
Performance and Benchmarking 12
Sources of Performance Information
Information for CompaqPartners
Service and Support 12
Hardware Warranty
Software Warranty
Compaq AlphaServer ES40 System Diagrams 13
System Features at a Glance 14
Physical Characteristics 15
Electrical Characteristics 15
Compaq AlphaServer ES40 Systems
The Compaq AlphaServer ES40systemisahighperformance, scalable enterprise server for business, technical,
and scientific applications. With its flexible design, it can
go in an office environment or computer room. It performs
as a high-capacity database server, high-performance application server, Network File System (NFS) server, or
Internet server.
Compaq AlphaServer products use the 64-bit Alpha RISC
architecture that supports multiple operating systems:
System Overview
The Compaq AlphaServer ES40 uses the third-generation
Alpha 21264 processor. Two speeds are available, the EV67
chip, whichrunsat667 MHz andthe EV68 chip,which runs
at 833 MHz. The switch-based system interconnect exploits
the full potential of the 21264 chip.
The system is available in three packages: a standalone tower, a
pedestal system with expanded storage capacity, and a rackmount system. Two models are available: an entry-level system
that supports 16 DIMMs (16 GB) and 6 PCI slots or a system
that supports 32 DIMMs (32 GB) and 10 PCI slots. Each system
variant is available with up to four processors.
Tru64 UNIX, OpenVMS, and Linux operating systems. The
AlphaServer ES40 system integrates into your current
operating environment and anticipates future needs with
upgrade capabilities.
For more information on Compaq AlphaServer ES40
systems, see:
http://www.compaq.com/alphaserver/servers.html
.
The chassis used in the tower is rotated 90 degrees and
installed in a pedestal enclosure or in a cabinet. Each chassis
provides space for up to twelve 1-inch Ultra3 disks. Up to
three BA36R StorageWorks shelves, or up to two Ultra3
Universal StorageWorks shelves can be installedin the
pedestal system; and up to six BA36R StorageWorks shelves,
or up to eight Ultra3 Universal StorageWorks shelves (singlebus or split-bus) can be installed in a cabinet.
Systems can be purchased with Tru64 UNIX or OpenVMS
operating systems installed. Or theycan bepurchased without
any operating system,allowing customers to install Linux.
Rackmount
Pedestal
Tower
PK0212
1
Featuresand Benefits
• Leadership 64-Bit Architecture
The Alpha 64-bit architecture was introduced with the Alpha
21064 chip in 1992 and now the 21264, builds upon that
proven architecture.
• Performance
The Alpha 21264 chip, the world’s fastest microprocessor, is
offered with a switch-based interconnect that supports four
processors. This switch-based system provides a memory
bandwidth of up to 5.2 Gbytes/sec (peak) using two 256-bit
memory buses running at 83 MHz.
• Scalability
An entry-level system (Model 1) offers one processor, 512
MB memory, and 6 PCI slots. Model 2, can have 32 GB
memory, and 10 I/O slots. The pedestal system provides
space for another 21 disks using BA36R StorageWorks
shelves, or 28 disks using Universal StorageWorks shelves.
beyond the 12 in the chassis. The cabinet can house up to four
systems and/or additional disks. All variants support up to
four processors.
Internal to each chip is a 64-Kbyte instruction cache (I-cache)
and a 64-Kbyte data cache (D-cache).
• I-cache. 64 Kbytes, two-way set-associative, virtually
addressed cache with 64-byte blocks
• D-cache. 64 Kbytes, two-way set-associative, virtually
indexed, physically tagged, writeback cache with 64-byte
blocks
Chip Operation
Several key design choices were made in the chip architecture
to maximize performance: Four instructions are fetched each
cycle, and then how those instructions are handled boosts the
speed of execution. Register renaming assigns a unique
storagelocation with each write reference to a register,
avoiding register dependencies that can be a potential
bottleneck to processor performance.
Another design feature, out-of-order execution, permits
instructions to execute in an order different from the order that
the instructions are fetched. In effect, instructions execute as
quickly as possible. This allows for faster execution, since
critical path computations are started and completed as soon as
possible.
• Reliability and Availability
The AlphaServer ES40 uses the latest technologies to achieve
redundancy, error correction, and fault management. The
system has redundant fans and power supplies; fans, power
supplies, and disks can be hot plugged. The remote
management console (RMC) monitors, sends alerts, and
records possible error conditions. The RMC can be accessed
even if the system is completely down.
• ES40 Workstation
The system is also offered as a workstation and is calledthe
AlphaStation ES40.
Third-Generation Alpha Chip
The third generation of the Alpha microprocessor, the Alpha
21264, is a superscalar superpipelined implementation of the
Alpha architecture. The first offering of this chip was known
as EV6. These systems are offered with the EV67 chip (.28
micron) and the EV68 chip (.18 micron). Each chiphas over
15.2 million transistors. In our discussion here, the Alpha
21264 designation applies to all variants of the chip.
Designed for performance, the 21264 achieves this goal by
carefully studied and simulated architectural and circuit
analysis. The 21264 memory system also enables the high
performance levels. On-chip and off-chip caches provide for
very low latency data access, which allows for very high
bandwidthdataaccess. (InES40systemsthesizeoftheoffchip cache is 8 MB running at 222 MHz (dual data rate cache)
for EV67 and 8 MB running at 277 MHz DDR for EV68.)
In addition, the Alpha 21264 employs speculative execution to
maximize performance. It speculatively fetches and executes
instructions even though it may not know immediately
whether the instruction will be on thefinal execution path.
This is particularly useful, for instance, when the 21264
predicts branch directions and speculatively executes down the
predicted path. The sophisticated branch prediction in the
21264 coupled with the speculative and dynamic execution
extractsmaximum instruction parallelism from applications.
For more information about the chip, see:
http://www.compaq.com/alphaserver/download/ev6chip.pdf
Alpha 21264 Features
.
• Out-of-order instruction execution
• Large (64 Kbyte) on-chip data and instruction caches
• Improved branch prediction through intuitive execution
• Register renaming
• Increased bandwidth for high-speed access to second-
levelcacheandsystemmemory
• Motion video instructions
• Square root and divide instructions
• All instructions are 32 bits long and have a regular
instruction format
• Floating-point unit, supports DIGITAL and IEEE
floating-point datatypes
• 80 integerregisters, 64 bits wide
• 72 floating-point registers, 64 bits wide
2
Model Variants
AlphaServer ES40 systems are offeredin twomodels. The
entry-level model provides connectors for four DIMMs on
each of the memory motherboards (MMBs) and connectors for
six PCI options on the PCI backplane.
Model 1 Model 2
1–4 CPUs 1–4 CPUs
Up to 16 GB memory Up to 32 GB memory
6PCIslots 10PCIslots
To upgrade from Model 1, you replace the PCI backplane and
the four memory motherboards. A Model 2 system has eight
DIMMs on each MMB (32 total) and 10 PCI slots.
CPU Upgrades
Upgrading from the 500 to 667 or 883 MHz processors
requires that the system board (54-25385-01) be a minimum
revision of E05.
SystemPackaging
Allsystemvariantsusethesamechassis,withspacefortwo
disk cages in the front. Each cage holds up to six 1-inch
Ultra3 SCSI disks.
Chassis, Tower View
In the tower enclosure, the chassis is rotated 90 degrees, with
the control panel and removable media bays keeping their
same horizontal position as in the pedestal/rack system.
The chassis has a compartment for the CPUs and memory and
another one for the PCI I/O cards. The control panel, CD-ROM
and floppydrives, and two additional removable media bays are
in the front,along with space for up to two disk cages. The
power supplies are in the rear.
Chassis, Pedestal View
Additional storage is available in the pedestal enclosure. The
chassis is mounted over a box that can house up to three BA36R
StorageWorks shelves (two in the front and one in the rear), or
up to two Ultra3 Universal (single-bus or split-bus)
StorageWorks shelves.
CPUs and
Memory
Fans
IO
PK3245
Rackmount Chassis
When installed in a cabinet, the chassis has the same
orientation as that used in the pedestal. The chassis can be
mounted in the 67-inch or 79-inch M-series cabinet, which is a
19-inch wide RETMA cabinet. Each system requires 14
inches (8U) of vertical space. With the maximum number of
systems in a cabinet (four), there can be two StorageWorks
shelves. When the maximum number of disks is desired (six
shelves), there can be three systems. (These numbers are for
the H9A15 79-inch cabinet.)
Fans
Control Panel
and Drives
PK3243
3
Architecture
This s ystem is designedto maximizethe potential of the
Alpha 21264 chip. The traditional bus interconnect has been
replaced by a switch-based interconnect system. With a bus
design, the processors, memory, and I/O modules share the
bus. As the number of bus users increases, the transactions
interfere with one another, increasing latency and decreasing
aggregate bandwidth. However, with a switch-based system
there is no degradation in performance as the number of
CPUs, memory, and I/O users increase. Although the users
increase, the speed is maintained.
With a switch-based, or point-to-point interconnect, the
performance remains constant, even though thenumber of
transactions multiplies. The switched system interconnect
uses a set of complex chips that route the traffic over multiple
paths. The chipset consists of one C-chip, two P-chips, and
eight D-chips.
System Block Diagram
Command, Address, and Control lines for each Memory Array
• C-chip. Provides the commandinterface from the CPUs
and main memory. Although there is only one C-chip in
the system, it allows each CPU to do transactions
simultaneously.
• D-chips. Provide the data path for the CPUs, main
memory, and I/O.
• P-chips. Provide the interface to two independent 64-bit
33 MHz PCI buses.
This chipset is similar to that used in the AlphaServer DS20
system; however, this chipset supports up to four CPUs and up
to 32 Gbytes memory. Interleaving occurs when at least two
memoryarrays are used.
Two 256-bit memory buses support four memory arrays,
yielding a 5.2 Gbytes/sec system bandwidth. Transactions are
ECC protected. Upon the receipt of data, the receiver checks
for data integrity and corrects any errors.
First
CPU
CPUs
B-cache
C-chip
Control lines for D-chips
bus
AP
C
P-chip
P-chip
64 bit PC
PAD
Bus
CPU
Data
Bus
8 D-chips
64 bit PC
I
I
Memory
Data
Bus
1 or 2
Memory
Arrays
1 or 2
Memory
Arrays
1400A-99
KW
P
4
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