Compaq AlphaServer DS10 Systems
Technical Summary
Contents
1
System Overview Features and Benefits
2
Third-Generation Alpha Chip
Chip Operation Alpha 21264 Features
3 Architecture
System Block Diagram
4
System Board
Component and Connector Locations
5 Memory
Memory Options Memory Configuration
Memory Performance Considerations
6
System I/O
Block Diagram of I/O Control PCI Slots
I/O Ports
7
System Control
Control Panel
Storage
RAID (Redundant Array of Independent Disks)
8
Server Management
Operational Management Platform Management Error Reporting
Security
Reliability and Availability Features
Processor Features
Memory Features I/O Features System Features
9 Clustering
PCI to Memory Channel Interconnect Operating System Support
Performance
Sources of Performance Information Information for Compaq Partners
10
Service and Support
Hardware Warranty Software Warranty
11
Compaq AlphaServer DS10 System Diagrams
12
System Features at a Glance
13
Physical Characteristics
Compaq AlphaServer DS10 Systems
The Compaq AlphaServer DS10 system is an entry-level system offering 64-bit computing with the Alpha processor. This single processor system is ideal for ISP/Internet applications, telecom applications, software development, and replicated site applications. The 3-U system box can be mounted in a cabinet or used on a desktop.
Compaq AlphaServer products use the 64-bit Alpha RISC architecture that supports multiple operating systems:
Tru64 UNIX, OpenVMS, and Linux.
For more information on Compaq AlphaServer DS10 systems, see
http://www.compaq.com/alphaserver
System Overview
The Compaq AlphaServer DS10 systems are available with the 600 MHz Alpha chip, the 21264A (marketed as 600 MHz but it actually runs at 616 MHz). Memory begins at 256 Mbytes and can be increased to 2 Gbytes. Second-level cache is 2 Mbytes. The switch-based system interconnect exploits the full potential of the Alpha chip.
The system measures 17 x 19 x 5 inches (3U) and can be placed on a desktop or rackmounted in a choice of three M- series cabinets, along with additional disks. In the largest cabinet (79 inches) up to 12 systems can be installed, or if more storage is desired, there can be up to 6 StorageWorks shelves and up to 8 systems. A rackmount slide kit is included with each system.
Six drive bays are available for storage devices. Each system includes a CD-ROM and floppy; a 5.25-inch removable media device can be added. With four 1-inch disks, there can be 218 GB of storage in the system box.
There are four full-length PCI slots: three 64-bit slots and one 32-bit slot. Integrated on the system board are two 10/100 Mbit fast Ethernet controllers, an IDE controller, two serial ports, one parallel port, remote management console, and keyboard and mouse ports.
Systems can be purchased with the Tru64 UNIX or OpenVMS operating systems installed. Or they can be purchased without any operating system, allowing customers to install Linux.
Features and Benefits
•Performance
The Alpha chip, the world’s fastest microprocessor, is offered with a switch-based interconnect that supports one 600 MHz processor and up to 2 Gbytes of memory. This switch-based system provides a memory bandwidth of up to 1.3 Gbytes/sec (peak) using a 128-bit memory bus running at 77 MHz. The peak I/O bandwidth is 250 Mbyes/sec.
•Multiple Operating Systems
No other server offers the flexibility of running so many operating systems: Tru64 UNIX, OpenVMS, and Linux. It’s ideal as a development tool as well as a Web server or file server, or for remote applications or E-commerce applications.
•Package and Price
All the features of AlphaServers are now available in a package that goes anywhere at a price attractive to everyone. Start with one and then add to your base as your needs demand. Use the DS10 as a dedicated system or set up a cluster.
•DS10 Workstations
The 600 MHz system is also offered as a workstation and is called the AlphaStation DS10.
1
Third-Generation Alpha Chip
The third generation of the Alpha microprocessor, the Alpha 21264, is a superscalar, superpipelined implementation of the Alpha architecture. The first offering of this chip, which was manufactured using the CMOS-6 process, was known as EV6 and now the EV67 (21264A) chip is available, which uses the CMOS-7 process. Over 15.2 million transistors are on one die.
In our discussion here, the Alpha 21264 designation applies to the EV6 and the EV67 chips, unless we need to distinguish between the two. Designed for performance, the Alpha 21264 achieves this goal by carefully studied and simulated architectural and circuit analysis. The 21264 memory system also enables the high performance levels. On-chip and off-chip caches provide for very low latency data access, which allows for very high bandwidth data access. The 21264A 2-Mbyte off-chip cache runs at 205 MHz.
Internal to each chip is a 64-Kbyte instruction cache (I-cache) and a 64-Kbyte data cache (D-cache).
•I-cache. 64 Kbytes, two-way set-associative, virtually addressed cache with 64-byte blocks
•D-cache. 64 Kbytes, two-way set-associative, virtually indexed, physically tagged, writeback cache with 64-byte blocks
Chip Operation
Several key design choices were made in the chip architecture to maximize performance: Four instructions are fetched each cycle, and then how those instructions are handled boosts the speed of execution. Register renaming assigns a unique storage location with each write reference to a register, avoiding register dependencies that can be a potential bottleneck to processor performance.
Another design feature, out-of-order execution, permits instructions to execute in an order different from the order that the instructions are fetched. In effect, instructions execute as soon as possible. This allows for faster execution since critical path computations are started and completed as soon as possible.
In addition, the Alpha 21264 employs speculative execution to maximize performance. It speculatively fetches and executes instructions even though it may not know immediately whether the instruction will be on the final execution path. This is particularly useful, for instance, when the 21264 predicts branch directions and speculatively executes down the predicted path. The sophisticated branch prediction in the 21264 coupled with the speculative and dynamic execution extracts the most instruction parallelism from applications.
For more information about the chip, see http://www.compaq.com/alphaserver/download/ev6chip.pdf
Alpha 21264 Features
•Out-of-order instruction execution
•Large (64 Kbyte) on-chip data and instruction caches
•Improved branch prediction through intuitive execution
•Register renaming
•Increased bandwidth for high-speed access to second-level cache and system memory
•Motion video instructions
•Square root and divide instructions
•All instructions are 32 bits long and have a regular instruction format
•Floating-point unit, supports DIGITAL and IEEE floatingpoint data types
•80 integer registers, 64 bits wide
•72 floating-point registers, 64 bits wide
2
Architecture
The traditional bus interconnect has been replaced by a switchbased interconnect system. With a bus design, the processors, memory, and I/O modules share the bus. As the number of bus users increases, the transactions interfere with one another, increasing latency and decreasing aggregate bandwidth. However, with a switch-based system there is no degradation in performance as the number of CPUs, memory, and I/O users increase. Although the users increase, the speed is maintained.
With a switch-based, or point-to-point interconnect, the performance remains constant, even though the number of transactions multiplies. The switched system interconnect uses a set of complex chips that route the traffic over multiple paths.
The chipset consists of one C-chip, one P-chip, and two D- chips.
•C-chip. Provides the command interface from the CPU.
•D-chips. Provide the data path for the CPU, main memory, and I/O.
•P-chip. Provides the interface to the PCI bus.
This chipset, similar to those used in the AlphaServer DS20 and ES40 systems, supports up to one CPU and up to 2 Gbytes memory. Interleaving occurs when at least two memory arrays are used.
The PAD bus, the interface between the P-chip and the D- chips, is 32 data bits with 4 check bits. The 128-bit memory bus supports two memory arrays, yielding a 1.3 Gbyte/sec system bandwidth. Transactions are ECC protected. Upon the receipt of data, the receiver checks for data integrity and corrects any errors.
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System Block Diagram |
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Control lines for D-chips |
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