Compal LA-9332P Viking 18, Alienware M18x Schematic

A

B

C

D

E

MODEL NAME :

1 1

PCB NO :

BOM P/N :

LA-9332P

4619KU31L01

Viking 18

Compal Confidential

2 2

Viking 18

Schematic Document

Rev: X02

3 3

2012-11-19

@ : Nopop Component

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/05/14 2013/05/13

2012/05/14 2013/05/13

2012/05/14 2013/05/13

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Title

Title

Title

Cover Sheet

Cover Sheet

Cover Sheet

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

\\tperdfs1\CIS\SPEC\BAS40-04_SOT23-3.pdf

\\tperdfs1\CIS\SPEC\BAS40-04_SOT23-3.pdf

\\tperdfs1\CIS\SPEC\BAS40-04_SOT23-3.pdf

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

E

1 56Friday, December 14, 2012

1 56Friday, December 14, 2012

1 56Friday, December 14, 2012

0.1

0.1

0.1

A

B

C

D

E

FFS

LVDS Conn.

1 1

P.33

LVDS Mux

PI3LVD1012

HDMI to LVDS SW

STDP6038

LVDS Mux
PI3LVD1012

P.42 P.41

P.37

HDMI Redriver

PS121

HDMI Redriver

PS121

HDMI 1.3 Input
HDMI 1.4a Output

2 2

Conn.

P.35

miniDP Conn.

P.30

Mini Card #1(Half)

WLAN/WiMax
BT4.0+LE/WiGig

P.51

DMC

Display MiniCard

P.51

HDMI SW

TS3DV621

DP Redriver

PS8330

HDMI Redriver

PS121

P.37

HDMI MUX

P.36 P.36

P.35

P.31

PS8271

mDP MUX
MAX14998

HDMI MUX

P.39

PS8271

P.31

P.39

eDP to LVDS

RTD2136

P.40

DP/HDMI

LVDS

HDMI

DP1.2

MXM III
Conn.

P.16

MXM III
Conn.

P.17

USB2.0
PCI-E 2.0

USB2.0
PCI-E 2.0

2-lane eDP

HDMI

DP1.1

DP/HDMI

PEGx 8

Gen 3

4C 47W/57W

PEGx 8

G

en 3

Lynx Point

BGA 695 Balls

Intel

Haswell

Processor

Scoket G3
rPGA-947

P.5, 6, 7, 8, 9, 10,
11

Intel

PCH

HM87

DMI x4

100MHz
5GT/s

Memory Bus DDRIII

Dual Channel

1.35V DDRIII 1600 MHz

USB3.0
USB 2.0

USB3.0
USB 2.0

USB3.0
USB 2.0

USB3.0
USB 2.0

USB2.0

USB2.0

SATA 3.0

3 3

RJ45 Conn.

P.46

9 in 1 Conn.

LAN(GbE)
E2201 Killer

Card Reader

RTS5209

Card Reader Board

P.46

PCI-E 2.0

SATA 3.0

PCI-E 2.0

SATA 3.0

SATA 3.0

P.17, 18, 19, 20, 21, 22, 23, 24,
25

SPI ROM

RTC conn.

Power On/Off CKT.

4 4

DC/DC Interface CKT.

Power Circuit DC/DC

P.55

P.56

P.37

A

8MB

ENE KC3810

B

P.20

P.43

VPK MCU

SPI

Int.KBD

VPK Daughter Board

LPC Bus

ENE KB9012

Touch Pad

P.49

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

C

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Issued Date

Issued Date

HD Audio

P.43

Subwoofer
TI TPA3111D

2012/02/28 2013/02/27

2012/02/28 2013/02/27

2012/02/28 2013/02/27

P.48

LNG3DMTR

204pin DDRIII SO-DIMM x4

BANK 0, 1, 2, 3

USB3.0 Rediver

USB3.0 Rediver

SATA Rediver

PS8520BT

SATA Rediver

PS8520BT

SATA Rediver ODD Conn.

PS8520BT

PS8713

PS8713

P.52

P.52

P.49

P.49

P.50

Audio Codec
ALC3661

TI
TPA3113D2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Fan Control

P.49 P.6

ADM1032

P.12, 13, 14,
15

USB 3.0/USB 2.0 Conn.

( USB Charger Port )

USB 3.0/USB 2.0 Conn.

USB 3.0/USB 2.0 Conn.

USB 3.0/USB 2.0 Conn.

Digital Camera

AlienFX/ELC

HDD Conn. 1

HDD Conn. 2

HDD Conn. 3

In ODD Bay (In place of ODD)

Mini Card #3(Full)
mSATA

Front L/R + HP1 +MIC

Center/Subwoofer + HP2

Rear L/R

P.47

P.48

Array Mics

Int. Speaker (2.5W*2)

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

CPU XDP

P.54

Conn.

Block Diagram

Block Diagram

Block Diagram

LA-9332P

LA-9332P

LA-9332P

P.52

P.52

P.52

P.53

P.57

P.48,49

P.49

P.49

P.50

P.50

P.47

P.47

P.47

P.57

P.48

P.50

Audio Daughter Board

E

0.1

0.1

2 56Friday, December 14, 2012

2 56Friday, December 14, 2012

2 56Friday, December 14, 2012

0.1

A

B

C

D

E

Compal Confidential

Project Code : VAS10

File Name : LA-9332P

1 1

Camera

LA-9332P M/B

44 pin

LCD Panel

Coaxial/Wire Combo

FFC

LS-9335P

POWER BUTTON/B

on/off SW

Led x 1

2 2

FFC

6 pin

LS-9336P
INDICATOR/B

Led-HDD

Led-Wireless

Led-CapsLock

S-933GP

L

Hall Sensor /B

FFC

20 pin

LS-933FP

4 pin

LS-9337P
CardReader /B

Card Slot

Audio /B

FFC

30 pin

KSI/KSO

3 3

VPK Keyboard

Backlight / 8 Pressure-sense Analog Signals

30 pin

40 pin

B To B conn.

22pin

LS-9338P

VPK Daughter/B

VPK MCU MAX7313

FFC

16 pin

FFC

60 pin

PWM

Key Pad

6 pin
10 pin

Hot Key

Wire

12pin

LS-XXXXP

LOGO /B

Led x 2

20 pin

Coaxial

HDD3/ODD

HDD in ODD Bay Cable

6pin

6pin

6pin

Wire

Wire

Wire

LS-933HP

Right Tron Light

LS-933IP

Left Tron Light

LS-933JP

Front Right Tron Light

HDD conn.

20pin

6pin

FPC

20 pin

Wire

LS-933KP

Front Left Tron Light

HDD1/HDD2

6pin 6pin6pin

WireWireWire

Touch Pad

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

LS-9333P LS-9331P LS-9332P

Alien head badge/B Alien Slits-L Light/BAlien Slits-R Light/B

Led x 2Led x 2 Led x 2

Compal Secret Data

Compal Secret Data

2011/06/02 2012/06/02

2011/06/02 2012/06/02

2011/06/02 2012/06/02

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

Block Diagram

Block Diagram

E

3 56Friday, December 14, 2012

3 56Friday, December 14, 2012

3 56Friday, December 14, 2012

0.1

0.1

0.1

A

+1.35V

+

1.05V

ON

OFF

OFF

Issued Date

Issued Date

Issued Date

USB 3.0 PORT

1

2

4

5

6

+5VS

+3VS

+1.5VS

+1.05VS

+0.675VS

+3VMXM

+5VMXM

+VCC_CORE

+1.35V_CPU_VDDQ

ONON

OFF

OFF

DESTINATION

DD1

H

HDD2

ODD

mSATA

MINI CARD-1 WLAN

MINI CARD-2 DMC

2012/05/28 2013/05/27

2012/05/28 2013/05/27

2012/05/28 2013/05/27

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

100K +/- 5%Ra

0
1
2
3
4
5
6
7 NC

Rb V min

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%

100K +/- 5%
200K +/- 5%

0 0 V

AD_BID

0.168 V

0.375 V 0.503 V
0

.634 V

0.958 V

1.372 V

1.851 V 2.200 V

2.433 V

V typ

AD_BID

0 V 0.155 V

0.250 V

0.819 V

1.185 V

1.650 V

3.300 V

V

AD_BID

0.362 V

0.621 V

0.945 V

1.359 V

1.838 V

2.420 V

3.300 V

max

EC AD3

0x00-0x0C
0x0D-0x1C
0x1D-0x30
0x31-0x49
0x4A-0x69
0x6A-0x8E
0x8F-0xBB
0xBC-0xFF

POWER STATES

RUN

Signal

State

S0 (Full ON) / M0

S5 (SOFT OFF) / M-OFF

SLP
S3#

HIGH

LOW HIGH

LOW

SLP

SLP
S4#

HIGH ON

LOW LOW LOW LOW ON

S5#

HIGH

S4
STATE#

HIGHHIGH

HIGH LOW ONS3 (Suspend to RAM) / M-OFF

LOW

SLP
M#

HIGH

LOW ONLOW LOWS4 (Suspend to DISK) / M-OFF

ALWAYS
PLANE

SUS
PLANE

ON

O

FF

Symbol Note :

: means Digital Ground

1 1

CLKOUT_PCIE0

CLKOUT_PCIE1

CLKOUT_PCIE2

CLK

CLKOUT_PCIE3

CLKOUT_PCIE4

CLKOUT_PCIE5

CLKOUT_PCIE6

CLKOUT_PCIE7

CLKOUT_PEG_A

SMBUS Control Table

SOURCE

EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK2
EC_SMB_DA2

PCH_SML0CLK PCH
PCH_SML0DATA

PCH_SML1CL K
PCH_SML1DA TA

MEM_SMBCLK
MEM_SMBDAT A

KB9012

KB9012

PCH

PCH

DMC

WLAN BATT DIMM

V

: means Analog Ground

DESTINATIONDIFFERENTIAL

MINI CARD-1 WLAN

MINI CARD-2 DMC

10/100/1G LAN

CARD READER

None

None

None

None

MXM

V

V

FLEX CLOCKS DESTINATION

CLKOUTFLEX0

CLKOUTFLEX1

CLKOUTFLEX2

CLKOUTFLEX3

Thermal

4028

Sensor

V

V

2136

FFS MXM

V

V

PLANE

ON ON

OFFOFF OFF

CLKOUT

PCI0

PCI1

PCI2

PCI3

PCI4

VPK MCU

VV

CLOCKS

OFFOFFON

OFFOFF

PCH_LOOPBACK

EC

0port debug card

8

None

None

BOARD ID Table

Board ID

0
1
2
3
4
5
6
7

PM TABLE

power
plane

State

S0 ON

S3

S5 S4/AC

S5 S4/AC don't exist

None

None

None

None

DESTINATION

XDP

Charger6038

TP mSATA

V

V

V

V V

PCB Revision

0.1 (SSI)

0.2 (PT)

0.3 (ST)

0.4 (QT)

1.0 (MP)

+5VALW

+3VALW

+3VLP

+

3V_PCH

ON OFF

ON

OFF

SATAIII

SATA0

SATA1

SATA2

SATA3

SATA4/PCIE LANE1

SATA5/PCIE LANE2

Link

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

A

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

Connetion

JUSB1 (Right side)

JUSB2 (Right side)

NA3

NA

JUSB3 (Left side)

JUSB4 (Left side)

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

USB2.0

PCI EXPRESS

Lane 1/USB3.0 Port 3

Lane 2/USB3.0 Port 4

Lane 3

Lane 4

Lane 5

Lane 6

Lane 7

Lane 8

USB PORT#0DESTINATION

JUSB1(USB3.0 P1)

JUSB2(USB3.0 P2)

1

JUSB3(USB3.0 P5)

2

JUSB4(USB3.0 P6)

3

JMINI1 (WLAN)

4

JMINI2 (DMC)

5

AlienFX/ELC

6

7

None

N

8

9

10

11

12

13

one

None

None

None

LVDS CAMERA

VPK K/B

DESTINATION

None

None

10/100/1G LAN

CARD READER

None

None

None

None

Compal Electronics, Inc.

Title

Title

Title

Notes List

Notes List

Notes List

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-9332P

LA-9332P

LA-9332P

Date: Sheet of

Date: Sheet of

Date: Sheet of

4 56Friday, December 14, 2012

4 56Friday, December 14, 2012

4 56Friday, December 14, 2012

0.1

0.1

0.1

5

4

3

2

1

D D

Haswell rPGA EDS

Haswell rPGA EDS

JCPU1A

JCPU1A

PEG_RCOMP

DMI_CRX_PTX_N017
DMI_CRX_PTX_N117
DMI_CRX_PTX_N217
DMI_CRX_PTX_N317

DMI_CRX_PTX_P017
DMI_CRX_PTX_P117
DMI_CRX_PTX_P217
DMI_CRX_PTX_P317

DMI_CTX_PRX_N017
DMI_CTX_PRX_N117
DMI_CTX_PRX_N217

C C

FDI_CSYNC17
FDI_INT17

B B

DMI_CTX_PRX_N317

DMI_CTX_PRX_P017
DMI_CTX_PRX_P117
DMI_CTX_PRX_P217
DMI_CTX_PRX_P317

@

@

RC3 0_0402_1%

RC3 0_0402_1%
RC87 0_0402_1%

RC87 0_0402_1%

@

@

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

12
12

FDI_CSYNC_R
FDI_INT_R

D21

DMI_RXN_0

C21

DMI_RXN_1

B21

DMI_RXN_2

A21

DMI_RXN_3

D20

DMI_RXP_0

C20

DMI_RXP_1

B20

DMI_RXP_2

A20

DMI_RXP_3

D18

DMI_TXN_0

C17

DMI_TXN_1

B17

DMI_TXN_2

A17

DMI_TXN_3

D17

DMI_TXP_0

C18

DMI_TXP_1

B18

DMI_TXP_2

A18

DMI_TXP_3

H29

FDI_CSYNC

J29

FDI_INT

I

I

NTEL_HASWELL_HA SWELL

NTEL_HASWELL_HA SWELL

CONN@

CONN@

DMI FDI

DMI FDI

1 OF 9

1 OF 9

PEG_RXN_0
PEG_RXN_1
PEG_RXN_2
PEG_RXN_3
PEG_RXN_4
PEG_RXN_5
PEG_RXN_6

PEG

PEG

PEG_RXN_7
PEG_RXN_8

PEG_RXN_9
PEG_RXN_10
PEG_RXN_11
PEG_RXN_12
PEG_RXN_13
PEG_RXN_14
PEG_RXN_15

PEG_RXP_0
PEG_RXP_1
PEG_RXP_2
PEG_RXP_3
PEG_RXP_4
PEG_RXP_5
PEG_RXP_6
PEG_RXP_7
PEG_RXP_8

PEG_RXP_9
PEG_RXP_10
PEG_RXP_11
PEG_RXP_12
PEG_RXP_13
PEG_RXP_14
PEG_RXP_15

PEG_TXN_0

PEG_TXN_1

PEG_TXN_2

PEG_TXN_3

PEG_TXN_4

PEG_TXN_5

PEG_TXN_6

PEG_TXN_7

PEG_TXN_8

PEG_TXN_9

PEG_TXN_10
PEG_TXN_11
PEG_TXN_12
PEG_TXN_13
PEG_TXN_14
PEG_TXN_15

PEG_TXP_0

PEG_TXP_1

PEG_TXP_2

PEG_TXP_3

PEG_TXP_4

PEG_TXP_5

PEG_TXP_6

PEG_TXP_7

PEG_TXP_8

PEG_TXP_9

PEG_TXP_10
PEG_TXP_11
PEG_TXP_12
PEG_TXP_13
PEG_TXP_14
PEG_TXP_15

PEG_COMP

CAD Note:
Trace width=12 mils ,Spacing=15mil
Max length= 400 mils.

E23

PEG_COMP

M29

PEG_GTX_C_HRX_N0

K28

PEG_GTX_C_HRX_N1

M31

PEG_GTX_C_HRX_N2

L30

PEG_GTX_C_HRX_N3

M33

PEG_GTX_C_HRX_N4

L32

PEG_GTX_C_HRX_N5

M35

PEG_GTX_C_HRX_N6

L34

PEG_GTX_C_HRX_N7

E29

PEG_GTX_C_HRX_N8

D28

PEG_GTX_C_HRX_N9

E31

PEG_GTX_C_HRX_N10

D30

PEG_GTX_C_HRX_N11

E35

PEG_GTX_C_HRX_N12

D34

PEG_GTX_C_HRX_N13

E33

PEG_GTX_C_HRX_N14

E32

PEG_GTX_C_HRX_N15

L29

PEG_GTX_C_HRX_P0

L28

PEG_GTX_C_HRX_P1

L31

PEG_GTX_C_HRX_P2

K30

PEG_GTX_C_HRX_P3

L33

PEG_GTX_C_HRX_P4

K32

PEG_GTX_C_HRX_P5

L35

PEG_GTX_C_HRX_P6

K34

PEG_GTX_C_HRX_P7

F29

PEG_GTX_C_HRX_P8

E28

PEG_GTX_C_HRX_P9

F31

PEG_GTX_C_HRX_P10

E30

PEG_GTX_C_HRX_P11

F35

PEG_GTX_C_HRX_P12

E34

PEG_GTX_C_HRX_P13

F33

PEG_GTX_C_HRX_P14

D32

PEG_GTX_C_HRX_P15

H35

PEG_HTX_GRX_N0

H34

PEG_HTX_GRX_N1

J33

PEG_HTX_GRX_N2

H32

PEG_HTX_GRX_N3

J31

PEG_HTX_GRX_N4

G30

PEG_HTX_GRX_N5

C33

PEG_HTX_GRX_N6

B32

PEG_HTX_GRX_N7

B31

PEG_HTX_GRX_N8

A30

PEG_HTX_GRX_N9

B29

PEG_HTX_GRX_N10

A28

PEG_HTX_GRX_N11

B27

PEG_HTX_GRX_N12

A26

PEG_HTX_GRX_N13

B25

PEG_HTX_GRX_N14

A24

PEG_HTX_GRX_N15

J35

PEG_HTX_GRX_P0

G34

PEG_HTX_GRX_P1

H33

PEG_HTX_GRX_P2

G32

PEG_HTX_GRX_P3

H31

PEG_HTX_GRX_P4

H30

PEG_HTX_GRX_P5

B33

PEG_HTX_GRX_P6

A32

PEG_HTX_GRX_P7

C31

PEG_HTX_GRX_P8

B30

PEG_HTX_GRX_P9

C29

PEG_HTX_GRX_P10

B28

PEG_HTX_GRX_P11

C27

PEG_HTX_GRX_P12

B26

PEG_HTX_GRX_P13

C25

PEG_HTX_GRX_P14

B24

PEG_HTX_GRX_P15

Near MXM Connector

+VCOMP_OUT

12

RC224.9_0402_1%~D RC224.9_0402_1%~D

1 2

CC1 0.22U_0402_16V7K~DCC1 0.22U_0402_16V7K~D

1 2

CC2 0.22U_0402_16V7K~DCC2 0.22U_0402_16V7K~D

1 2

CC3 0.22U_0402_16V7K~DCC3 0.22U_0402_16V7K~D

1 2

CC4 0.22U_0402_16V7K~DCC4 0.22U_0402_16V7K~D

1 2

CC5 0.22U_0402_16V7K~DCC5 0.22U_0402_16V7K~D

1 2

CC13 0.22U_0402_16V7K~DCC13 0.22U_0402_16V7K~D

1 2

CC6 0.22U_0402_16V7K~DCC6 0.22U_0402_16V7K~D

1 2

CC7 0.22U_0402_16V7K~DCC7 0.22U_0402_16V7K~D

1 2

CC8 0.22U_0402_16V7K~DCC8 0.22U_0402_16V7K~D

1 2

CC9 0.22U_0402_16V7K~DCC9 0.22U_0402_16V7K~D

1 2

CC10 0.22U_0402_16V7K~DCC10 0.22U_0402_16V7K~D

1 2

CC11 0.22U_0402_16V7K~DCC11 0.22U_0402_16V7K~D

1 2

CC12 0.22U_0402_16V7K~DCC12 0.22U_0402_16V7K~D

1 2

CC14 0.22U_0402_16V7K~DCC14 0.22U_0402_16V7K~D

1 2

CC15 0.22U_0402_16V7K~DCC15 0.22U_0402_16V7K~D

1 2

CC16 0.22U_0402_16V7K~DCC16 0.22U_0402_16V7K~D

1 2

CC17 0.22U_0402_16V7K~DCC17 0.22U_0402_16V7K~D

1 2

CC18 0.22U_0402_16V7K~DCC18 0.22U_0402_16V7K~D

1 2

CC19 0.22U_0402_16V7K~DCC19 0.22U_0402_16V7K~D

1 2

CC20 0.22U_0402_16V7K~DCC20 0.22U_0402_16V7K~D

1 2

CC21 0.22U_0402_16V7K~DCC21 0.22U_0402_16V7K~D

1 2

CC22 0.22U_0402_16V7K~DCC22 0.22U_0402_16V7K~D

1 2

CC23 0.22U_0402_16V7K~DCC23 0.22U_0402_16V7K~D

1 2

CC24 0.22U_0402_16V7K~DCC24 0.22U_0402_16V7K~D

1 2

CC25 0.22U_0402_16V7K~DCC25 0.22U_0402_16V7K~D

1 2

CC26 0.22U_0402_16V7K~DCC26 0.22U_0402_16V7K~D

1 2

CC27 0.22U_0402_16V7K~DCC27 0.22U_0402_16V7K~D

1 2

CC28 0.22U_0402_16V7K~DCC28 0.22U_0402_16V7K~D

1 2

CC29 0.22U_0402_16V7K~DCC29 0.22U_0402_16V7K~D

1 2

CC30 0.22U_0402_16V7K~DCC30 0.22U_0402_16V7K~D

1 2

CC31 0.22U_0402_16V7K~DCC31 0.22U_0402_16V7K~D

1 2

CC32 0.22U_0402_16V7K~DCC32 0.22U_0402_16V7K~D

1 2

CC33 0.22U_0402_16V7K~DCC33 0.22U_0402_16V7K~D

1 2

CC34 0.22U_0402_16V7K~DCC34 0.22U_0402_16V7K~D

1 2

CC35 0.22U_0402_16V7K~DCC35 0.22U_0402_16V7K~D

1 2

CC36 0.22U_0402_16V7K~DCC36 0.22U_0402_16V7K~D

1 2

CC37 0.22U_0402_16V7K~DCC37 0.22U_0402_16V7K~D

1 2

CC38 0.22U_0402_16V7K~DCC38 0.22U_0402_16V7K~D

1 2

CC39 0.22U_0402_16V7K~DCC39 0.22U_0402_16V7K~D

1 2

CC40 0.22U_0402_16V7K~DCC40 0.22U_0402_16V7K~D

1 2

CC41 0.22U_0402_16V7K~DCC41 0.22U_0402_16V7K~D

1 2

CC42 0.22U_0402_16V7K~DCC42 0.22U_0402_16V7K~D

1 2

CC43 0.22U_0402_16V7K~DCC43 0.22U_0402_16V7K~D

1 2

CC44 0.22U_0402_16V7K~DCC44 0.22U_0402_16V7K~D

1 2

CC45 0.22U_0402_16V7K~DCC45 0.22U_0402_16V7K~D

1 2

CC46 0.22U_0402_16V7K~DCC46 0.22U_0402_16V7K~D

1 2

CC47 0.22U_0402_16V7K~DCC47 0.22U_0402_16V7K~D

1 2

CC48 0.22U_0402_16V7K~DCC48 0.22U_0402_16V7K~D

1 2

CC49 0.22U_0402_16V7K~DCC49 0.22U_0402_16V7K~D

1 2

CC50 0.22U_0402_16V7K~DCC50 0.22U_0402_16V7K~D

1 2

CC51 0.22U_0402_16V7K~DCC51 0.22U_0402_16V7K~D

1 2

CC52 0.22U_0402_16V7K~DCC52 0.22U_0402_16V7K~D

1 2

CC53 0.22U_0402_16V7K~DCC53 0.22U_0402_16V7K~D

1 2

CC54 0.22U_0402_16V7K~DCC54 0.22U_0402_16V7K~D

1 2

CC55 0.22U_0402_16V7K~DCC55 0.22U_0402_16V7K~D

1 2

CC56 0.22U_0402_16V7K~DCC56 0.22U_0402_16V7K~D

1 2

CC57 0.22U_0402_16V7K~DCC57 0.22U_0402_16V7K~D

1 2

CC58 0.22U_0402_16V7K~DCC58 0.22U_0402_16V7K~D

1 2

CC59 0.22U_0402_16V7K~DCC59 0.22U_0402_16V7K~D

1 2

CC60 0.22U_0402_16V7K~DCC60 0.22U_0402_16V7K~D

1 2

CC61 0.22U_0402_16V7K~DCC61 0.22U_0402_16V7K~D

1 2

CC62 0.22U_0402_16V7K~DCC62 0.22U_0402_16V7K~D

1 2

CC63 0.22U_0402_16V7K~DCC63 0.22U_0402_16V7K~D

1 2

CC64 0.22U_0402_16V7K~DCC64 0.22U_0402_16V7K~D

PEG_GTX_HRX_N0
PEG_GTX_HRX_N1
PEG_GTX_HRX_N2
PEG_GTX_HRX_N3
PEG_GTX_HRX_N4
PEG_GTX_HRX_N5
PEG_GTX_HRX_N6
PEG_GTX_HRX_N7
PEG_GTX_HRX_N8
PEG_GTX_HRX_N9
PEG_GTX_HRX_N10
PEG_GTX_HRX_N11
PEG_GTX_HRX_N12
PEG_GTX_HRX_N13
PEG_GTX_HRX_N14
PEG_GTX_HRX_N15
PEG_GTX_HRX_P0
PEG_GTX_HRX_P1
PEG_GTX_HRX_P2
PEG_GTX_HRX_P3
PEG_GTX_HRX_P4
PEG_GTX_HRX_P5
PEG_GTX_HRX_P6
PEG_GTX_HRX_P7
PEG_GTX_HRX_P8
PEG_GTX_HRX_P9
PEG_GTX_HRX_P10
PEG_GTX_HRX_P11
PEG_GTX_HRX_P12
PEG_GTX_HRX_P13
PEG_GTX_HRX_P14
PEG_GTX_HRX_P15
PEG_HTX_C_GRX_N0
PEG_HTX_C_GRX_N1
PEG_HTX_C_GRX_N2
PEG_HTX_C_GRX_N3
PEG_HTX_C_GRX_N4
PEG_HTX_C_GRX_N5
PEG_HTX_C_GRX_N6
PEG_HTX_C_GRX_N7
PEG_HTX_C_GRX_N8

PEG_HTX_C_GRX_N9
PEG_HTX_C_GRX_N10
PEG_HTX_C_GRX_N11
PEG_HTX_C_GRX_N12
PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_N14
PEG_HTX_C_GRX_N15

PEG_HTX_C_GRX_P0

PEG_HTX_C_GRX_P1

PEG_HTX_C_GRX_P2

PEG_HTX_C_GRX_P3

PEG_HTX_C_GRX_P4

PEG_HTX_C_GRX_P5

PEG_HTX_C_GRX_P6

PEG_HTX_C_GRX_P7

PEG_HTX_C_GRX_P8

PEG_HTX_C_GRX_P9
PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_P11
PEG_HTX_C_GRX_P12
PEG_HTX_C_GRX_P13
PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_P15

PEG_GTX_HRX_P[0..15] 29,30
PEG_GTX_HRX_N[0..15] 29,30

PEG_HTX_C_GRX_P[0..15] 29,30
PEG_HTX_C_GRX_N[0..15] 29,30

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/05/28 2013/05/27

2012/05/28 2013/05/27

2012/05/28 2013/05/27

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Title

Title

Title

CPU (1/7) DMI,PEG

CPU (1/7) DMI,PEG

CPU (1/7) DMI,PEG

ize Document Number Rev

Size Document Number Rev

Size Document Number Rev

S

Custom

Custom

Custom

LA-9332P

LA-9332P

LA-9332P

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

1

5 56Friday, December 14, 2012

5 56Friday, December 14, 2012

5 56Friday, December 14, 2012

0.1

0.1

0.1

5

4

3

2

1

SM_DRAMPWROK with DDR Power Gating Topology

+3VALW

100K_0402_5%~D

100K_0402_5%~D

+3VALW

@

@

12

12

1 2

@

@

H_THERMTRIP#21

CLK_CPU_DPLL#18

CLK_CPU_SSC_DPLL#18

CLK_CPU_SSC_DPLL18

UC1

UC1

NC

VCC
A
GND3Y

H_THERMTRIP#

H_CATERR#

H_PROCHOT#

H_PROCHOT#43,57

H_PM_SYNC17

H_CPUPWRGD21

CLK_CPU_DPLL18

CLK_CPU_DMI#18

CLK_CPU_DMI18

+VCCIO_OUT

RC2010K_0402_5%~D @RC2010K_0402_5%~D @

RC2110K_0402_5%~D @RC2110K_0402_5%~D @

5

4

12

@

@

RC89

RC89

5

1

P

B

2

A

G

3

RC94 0_0402_5%~DRC94 0_0402_5%~D

RUN_ON_CPU1.5VS3#10,56

RC57 56_0402_5%~DRC57 56_0402_5%~D
RC134 0_0402_1%@RC134 0_0402_1%@

place RC134 near CPU

1 2

RC25 0_0402_1%

RC25 0_0402_1%

RC51 0_0402_1%@RC51 0_0402_1%@
RC52 0_0402_1%@RC52 0_0402_1%@
RC43 0_0402_1%@RC43 0_0402_1%@
RC22 0_0402_1%@RC22 0_0402_1%@
RC15 0_0402_1%@RC15 0_0402_1%@
RC13 0_0402_1%@RC13 0_0402_1%@

+3VS

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

1

@

@

CC140

CC140

2

PCH_PLTRST#_BUF

CC156

@ CC156

@

1 2

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

4

O

UC2

UC2

74AHC1G09GW_TSSOP5~D@

74AHC1G09GW_TSSOP5~D@

12

1 2
1 2

@

@

12
12
12
12
12
12

+1.05VS

1K_0402_1%~D

1K_0402_1%~D

12

RC17

RC17

@

@

RC10 43_0402_5%~D

RC10 43_0402_5%~D

20K_0402_5%~D

20K_0402_5%~D

12

RC11

RC11

@

@

D D

C C

B B

Deep S3

1.35V_SUS_PWRGD59

SYS_PWROK17

PM_DRAM_PWRGD17

RC97 0_0402_5%~D

RC97 0_0402_5%~D

RC88 0_0402_5%~DRC88 0_0402_5%~D

+3V_PCH

RC18 200_0402_1%~D

RC18 200_0402_1%~D

+VCCIO_OUT

1 2

RC136 56_0402_5%~D@RC136 56_0402_5%~D@

1 2

RC128 49.9_0402_1%~D@RC128 49.9_0402_1%~D@

1 2

RC44 62_0402_5%~DRC44 62_0402_5%~D

CPU_SSC_DPLL

CPU_SSC_DPLL#

1 2

1 2

SSC CLOCK TERMINATION, IF NOT USED, stuff RC20,RC21

Buffered reset to CPU

@

@

1

PLT_RST#17,43,44,51,53

CAD Note:
PLACE PULL-UP RESISTOR WITHIN 2 INCH OF THE CPU

2

SN74LVC1G07DCKR_SC70-5~D

SN74LVC1G07DCKR_SC70-5~D

RUNPWROK_AND

H_PECI21,43

1 2

@

@

+1.35V_CPU_VDDQ

39_0402_5%~D

39_0402_5%~D

@RC64

@

RC64

SSM3K7002FU_SC70-3~D

SSM3K7002FU_SC70-3~D

1 2

13

D

D

@

@

2

QC1

QC1

G

G

S

S

H_CATERR#
H_PECI

T66PAD~D @T66PAD~D @

H_PROCHOT#_R
H_THERMTRIP#_R

H_PM_SYNC

VCCPWRGOOD_0_R

PM_DRAM_PWRGD_CPU
CPU_PLTRST#_R

CPU_DPLL#

CPU_DPLL

CPU_SSC_DPLL#
CPU_SSC_DPLL
CPU_DMI#
CPU_DMI

CPU_PLTRST#21

1.8K_0402_1%

1.8K_0402_1%

12

RC16

RC16

RC28 0_0402_5%~DRC28 0_0402_5%~D

3.3K_0402_1%~D

3.3K_0402_1%~D

12

RC14

RC14

AP32

AN32
AR27
AK31
AM30
AM35

AT28
AL34

AC10

AT26

RC54 0_0402_5%~D@RC54 0_0402_5%~D@

RC53 0_0402_1%@RC53 0_0402_1%@

12

SKTOCC

CATERR
PECI
RSVD
PROCHOT
THERMTRIP

PM_SYNC
PWRGOO D
SM_DRAMPW ROK
PLTRSTIN

G28

DPLL_REF _CLKN

H28

DPLL_REF _CLKP

F27

SSC_DPLL _REF_CLKN

E27

SSC_DPLL _REF_CLKP

D26

BCLKN

E26

BCLKP

CONN@

CONN@

12

12

PM_DRAM_PWRGD_CPU

Haswell rPGA EDS

Haswell rPGA EDS

JCPU1B

JCPU1B

MISC

MISC

THERMAL

THERMAL

PWR

PWR

INTEL_HASWELL_HASWELL

INTEL_HASWELL_HASWELL

CPU_PLTRST#_R

+3V_PCH

SM_RCOMP_ 0
SM_RCOMP_ 1
SM_RCOMP_ 2

DDR3

DDR3

SM_DRAMRST

PRDY

PREQ

TCK
TMS

TRST

JTAG

JTAG

TDI
TDO
DBR

BPM_N_0
BPM_N_1

CLOCK

CLOCK

BPM_N_2
BPM_N_3
BPM_N_4
BPM_N_5
BPM_N_6
BPM_N_7

2 OF 9

2 OF 9

CAD Note:

Avoid stub in the PWRGD path

while placing resistors RC25 & RC130

RC125 1K_0402_1%~D@RC125 1K_0402_1%~D@

PBTN_OUT#17,43

CPU_PWR_DEBUG10

PCH_SMBDATA12,13,14,15,19,49,50,51,53

PCH_SMBCLK12,13,14,15,19,49,50,51,53

AP3

SM_RCOMP0

AR3

SM_RCOMP1

AP2

SM_RCOMP2

AN3

DDR3_DRAMRST#_CPU

AR29

XDP_PRDY#

AT29

XDP_PREQ#

AM34

XDP_TCLK

AN33

XDP_TMS

AM33

XDP_TRST#

AM31

XDP_TDI_R

AL33

XDP_TDO_R

AP33

XDP_DBRESET#_R

AR30

XDP_OBS0_R

AN31

XDP_OBS1_R

AN29

XDP_OBS2_R

AP31

XDP_OBS3_R

AP30

XDP_OBS4_R

AN28

XDP_OBS5_R

AP29

XDP_OBS6_R

AP28

XDP_OBS7_R

VCCPWRGOOD_0_R

1 2

+VCCIO_OUT

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

1

1

@

@

CC65

CC65

CC66

@

@

CC66

2

2

Place near JXDP1

SYS_PWROK_XDP

RC5 need to close to JCPU1

H_CPUPWRGD H_CPUPWRGD_XDP

IMVP_PWRGD17,43,62

RC50 0_0402_1%@RC50 0_0402_1%@
RC36 0_0402_1%@RC36 0_0402_1%@
RC46 0_0402_1%@RC46 0_0402_1%@
RC47 0_0402_1%@RC47 0_0402_1%@
RC48 0_0402_1%@RC48 0_0402_1%@
RC23 0_0402_1%@RC23 0_0402_1%@
RC24 0_0402_1%@RC24 0_0402_1%@
RC26 0_0402_1%@RC26 0_0402_1%@

RC30 0_0402_1%@RC30 0_0402_1%@
RC31 0_0402_1%@RC31 0_0402_1%@

1 2

RC5 1K_0402_1%~D@RC5 1K_0402_1%~D@

1 2

RC6 0_0402_5%~D@RC6 0_0402_5%~D@

1 2

RC8 0_0402_5%~D@RC8 0_0402_5%~D@

1 2

RC12 0_0402_5%~D@RC12 0_0402_5%~D@

1 2

RC126 0_0402_5%~D@RC126 0_0402_5%~D@

1 2

RC127 0_0402_5%~D@RC127 0_0402_5%~D@

DDR3_DRAMRST#_CPU 12

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2

T68 PAD~D@T68 PAD~D@
T69 PAD~D@T69 PAD~D@
T70 PAD~D@T70 PAD~D@
T71 PAD~D@T71 PAD~D@
T72 PAD~D@T72 PAD~D@
T73 PAD~D@T73 PAD~D@

CFG39

RC56

RC56

XDP_PRDY#_R
XDP_PREQ#_R

XDP_TCLK_R

XDP_TMS_R

XDP_TRST#_R

XDP_TDI
XDP_TDO
XDP_DBRESET#

XDP_OBS0
XDP_OBS1

For ESD concern, please put near CPU

10K_0402_5%~D

10K_0402_5%~D

12

RC135

RC135

CRB Rev 0.7 is depop

DDR3 COMPENSATION SIGNALS

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil

XDP_PREQ#_R
XDP_PRDY#_R

CFG0

CFG09

CFG1

CFG19

CFG2

CFG29

12

CFG3_R

1K_0402_1%~D@

1K_0402_1%~D@

XDP_OBS0
XDP_OBS1

CFG4

CFG49

CFG5

CFG59

CFG6

CFG69

CFG7

CFG79

CFD_PWRBTN#_XDP

SYS_PWROK_XDP

DDR_XDP_SMBDAT_R1
DDR_XDP_SMBCLK_R1

XDP_TCLK_R

XDP_DBRESET# 17

1 2

RC45 100_0402_1%~DRC45 100_0402_1%~D

1 2

RC55 75_0402_1%~DRC55 75_0402_1%~D

1 2

RC49 100_0402_1%~DRC49 100_0402_1%~D

+VCCIO_OUT +VCCIO_OUT

JXDP1

JXDP1

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A 0

11

OBSDATA_A 1

13

GND4

15

OBSDATA_A 2

17

OBSDATA_A 3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B 0

29

OBSDATA_B 1

31

GND10

33

OBSDATA_B 2

35

OBSDATA_B 3

37

GND12

39

PWRGOO D/HOOK0

41

HOOK1

43

VCC_OBS_ AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01-L-D-A

SAMTE_BSH-030-01-L-D-A

ITPCLK#/HO OK5

RESET#/HOO K6

CRB Rev 0.7 no pull up

GND1
OBSFN_C0
OBSFN_C1

GND3

OBSDATA_C0
OBSDATA_C1

GND5

OBSDATA_C2
OBSDATA_C3

GND7
OBSFN_D0
OBSFN_D1

GND9

OBSDATA_D0
OBSDATA_D1

GND11
OBSDATA_D2
OBSDATA_D3

GND13

ITPCLK/HOOK 4

VCC_OBS_ CD

DBR#/HOOK 7

GND15

TRST#

GND17

CONN@

CONN@

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46

XDP_RST#_RCPU_PWR_DEBUG_R

48

XDP_DBRESET#

50
52
54
56
58
60

XDP_TDO
XDP_TRST#_R
XDP_TDI
XDP_TMS_R
CFG3_R

XDP_DBRESET#

XDP_TMS

XDP_TDI

XDP_PREQ#

XDP_TDO

XDP_TCLK

XDP_TRST#

TD0

TDI

TMS

CFG17

CFG17 9

CFG16

CFG16 9

CFG8

CFG8 9

CFG9

CFG9 9

CFG10

CFG10 9

CFG11

CFG11 9

CFG19

CFG19 9

CFG18

CFG18 9

CFG12

CFG12 9

CFG13

CFG13 9

CFG14

CFG14 9

CFG15

CFG15 9

CLK_XDP
CLK_XDP#

1 2

RC144 0_0402_5%~D@RC144 0_0402_5%~D@

1 2

RC145 0_0402_5%~D

RC145 0_0402_5%~D

@

@

RC9 1K_0402_1%~D@RC9 1K_0402_1%~D@

PU/PD for JTAG signals

12

RC19 1K_0402_1%~DRC19 1K_0402_1%~D

12

RC27 51_0402_1%~D@RC27 51_0402_1%~D@

12

RC29 51_0402_1%~D@RC29 51_0402_1%~D@

12

RC32 51_0402_1%~D@RC32 51_0402_1%~D@

12

RC35 51_0402_1%~D@RC35 51_0402_1%~D@

12

RC42 51_0402_1%~D@RC42 51_0402_1%~D@

12

RC41 51_0402_1%~DRC41 51_0402_1%~D

12

CPU_PLTRST#_R

+1.05VS

+3VS

CLK_CPU_ITP 18
CLK_CPU_ITP# 18

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/05/28 2013/05/27

2012/05/28 2013/05/27

2012/05/28 2013/05/27

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Title

Title

Title

CPU (2/7) PM,XDP,CLK

CPU (2/7) PM,XDP,CLK

CPU (2/7) PM,XDP,CLK

ize Document Number Rev

Size Document Number Rev

Size Document Number Rev

S

Custom

Custom

Custom

LA-9332P

LA-9332P

LA-9332P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

6 56Friday, December 14, 2012

6 56Friday, December 14, 2012

6 56Friday, December 14, 2012

0.1

0.1

0.1

5

JCPU1C

D D

C C

B B

A A

DDR_A_D[0..63]12,14

+V_SM_VREF

+DIMM0_1_VREF

+DIMM0_1_CA

0.022U_0402_25V7K~D

0.022U_0402_25V7K~D

24.9_0402_1%

24.9_0402_1%

+DIMM0_1_CA

CC137

CC137

RC150

RC150

1

2

12

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

RC147

RC147

1 2

2_0402_1%~D

2_0402_1%~D

AR15

AT14
AM14
AN14

AT15
AR14
AN15
AM15

AM9

AN9

AM8

AN8
AR9
AT9
AR8
AT8

AK9

AK6
AJ10
AK10

AK7

AF4

AF5

AF1

AF2

AG4

AG5

AG1

AG2

D12

D11

AM3

AJ9

AJ6

AJ7

J1
J2
J5
H5
H2
H1
J4
H4
F2
F1
D2
D3
D1
F3
C3
B3
B5
E6
A5
D6
D5
E5
B6
A6

E12

B11
A11
E11

B12
A12

F16
F13

+1.35V

1K_0402_1%~D

1K_0402_1%~D

12

1K_0402_1%~D

1K_0402_1%~D

12

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
SM_VREF
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

CONN@

CONN@

RC96

RC96

RC82

RC82

JCPU1C

3 OF 9

I

3 OF 9

I

+DIMM0_1_CA_CPU

4

Haswell rPGA EDS

Haswell rPGA EDS

RSVD_AC7
SA_CK_N_0
SA_CK_P_0

SA_CKE_0
SA_CK_N_1
SA_CK_P_1

SA_CKE_1
SA_CK_N_2
SA_CK_P_2

SA_CKE_2
SA_CK_N_3
SA_CK_P_3

SA_CKE_3

SA_CS_N_0
SA_CS_N_1
SA_CS_N_2
SA_CS_N_3

SA_ODT_0

SA_ODT_1

SA_ODT_2

SA_ODT_3

SA_BS_0
SA_BS_1
SA_BS_2

RSVD_V10

SA_RAS

SA_WE

SA_CAS

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_MA_15

SA_DQS_N_0
SA_DQS_N_1
SA_DQS_N_2
SA_DQS_N_3
SA_DQS_N_4
SA_DQS_N_5
SA_DQS_N_6
SA_DQS_N_7
SA_DQS_P_0
SA_DQS_P_1
SA_DQS_P_2
SA_DQS_P_3
SA_DQS_P_4
SA_DQS_P_5
SA_DQS_P_6
SA_DQS_P_7

NTEL_HASWELL_HA SWELL

NTEL_HASWELL_HA SWELL

+DIMM0_1_VREF

CC138

CC138

0.022U_0402_25V7K~D

0.022U_0402_25V7K~D

RC151

RC151

24.9_0402_1%

24.9_0402_1%

3

+V_SM_VREF

CC139

CC139

RC149

RC149

24.9_0402_1%

24.9_0402_1%

DDR_B_D[0..63]13,15

RC146

RC146

1 2

1

2_0402_1%~D

2_0402_1%~D

2

12

+1.35V

12

12

1K_0402_1%~D

1K_0402_1%~D

RC86

RC86

1K_0402_1%~D

1K_0402_1%~D

RC78

RC78

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AR18

AT18
AM17
AM18
AR17

AT17
AN17
AN18

AT12
AR12
AN12
AM11

AT11
AR11
AM12
AN11

AR5
AR6
AM5
AM6

AT5

AT6
AN5
AN6

AJ4

AK4

AJ1

AJ2
AM1
AN1

AK2

AK1

L2

M2

L4

M4

L1

M1

L5

M5

G7

J8
G8
G9

J7

J9

G10

J10

A8
B8
A9
B9
D8
E8
D9
E9

E15
D15
A15
B15
E14
D14
A14
B14

+V_SM_VREF_CNT

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

CONN@

CONN@

AC7
U4

M_CLK_DDR#0

V4

M_CLK_DDR0

AD9

DDR_CKE0_DIMMA

U3

M_CLK_DDR#1

V3

M_CLK_DDR1

AC9

DDR_CKE1_DIMMA

U2

M_CLK_DDR#4

V2

M_CLK_DDR4

AD8

DDR_CKE4_DIMMC

U1

M_CLK_DDR#5 DDR_CKE6_DIMMD

V1

M_CLK_DDR5

AC8

DDR_CKE5_DIMMC

M7

DDR_CS0_DIMMA#

L9

DDR_CS1_DIMMA#

M9

DDR_CS4_DIMMC#

M10

DDR_CS5_DIMMC#

M8

M_ODT0

L7

M_ODT1

L8

M_ODT4

L10

M_ODT5

V5

DDR_A_BS0

U5

DDR_A_BS1

AD1

DDR_A_BS2

V10
U6

DDR_A_RAS#

U7

DDR_A_WE#

U8

DDR_A_CAS#

V8

DDR_A_MA0

AC6

DDR_A_MA1

V9

DDR_A_MA2

U9

DDR_A_MA3

AC5

DDR_A_MA4

AC4

DDR_A_MA5

AD6

DDR_A_MA6

AC3

DDR_A_MA7

AD5

DDR_A_MA8

AC2

DDR_A_MA9

V6

DDR_A_MA10

AC1

DDR_A_MA11

AD4

DDR_A_MA12

V7

DDR_A_MA13

AD3

DDR_A_MA14

AD2

DDR_A_MA15

AP15

DDR_A_DQS#0

AP8

DDR_A_DQS#1

AJ8

DDR_A_DQS#2

AF3

DDR_A_DQS#3

J3

DDR_A_DQS#4

E2

DDR_A_DQS#5

C5

DDR_A_DQS#6

C11

DDR_A_DQS#7

AP14

DDR_A_DQS0

AP9

DDR_A_DQS1

AK8

DDR_A_DQS2

AG3

DDR_A_DQS3

H3

DDR_A_DQS4

E3

DDR_A_DQS5

C6

DDR_A_DQS6

C12

DDR_A_DQS7

RC148

RC148

1 2

1

2_0402_1%~D

2_0402_1%~D

2

12

T67 PAD~D@T67 PAD~D@

M_CLK_DDR#0 14
M_CLK_DDR0 14
DDR_CKE0_DIMMA 14
M_CLK_DDR#1 14
M_CLK_DDR1 14
DDR_CKE1_DIMMA 14
M_CLK_DDR#4 12
M_CLK_DDR4 12
DDR_CKE4_DIMMC 1 2
M_CLK_DDR#5 12 DDR_CKE6_DIMMD 13
M_CLK_DDR5 12
DDR_CKE5_DIMMC 1 2

DDR_CS0_DIMMA# 14
DDR_CS1_DIMMA# 14
DDR_CS4_DIMMC# 12
DDR_CS5_DIMMC# 12
M_ODT0 14
M_ODT1 14
M_ODT4 12
M_ODT5 12
DDR_A_BS0 12,14
DDR_A_BS1 12,14
DDR_A_BS2 12,14

DDR_A_RAS# 12,14

DDR_A_WE# 12,14

DDR_A_CAS# 12,14

DDR_A_MA[0..15] 12,14

DDR_A_DQS#[0..7] 12,14

DDR_A_DQS[0..7] 12,14

+1.35V

1K_0402_1%~D

1K_0402_1%~D

12

RC95

RC95

+DIMM0_1_VREF_CPU

1K_0402_1%~D

1K_0402_1%~D

12

RC81

RC81

0.022U_0402_25V7K~D

0.022U_0402_25V7K~D

2

JCPU1D

JCPU1D

I

I

NTEL_HASWELL_HA SWELL

NTEL_HASWELL_HA SWELL

4 OF 9

4 OF 9

Haswell rPGA EDS

Haswell rPGA EDS

SB_CKN0

SB_CK0

SB_CKE_0

SB_CKN1

SB_CK1

SB_CKE_1

SB_CKN2

SB_CK2

SB_CKE_2

SB_CKN3

SB_CK3

SB_CKE_3

SB_CS_N_0
SB_CS_N_1
SB_CS_N_2
SB_CS_N_3

SB_ODT_0
SB_ODT_1
SB_ODT_2
SB_ODT_3

SB_BS_0
SB_BS_1
SB_BS_2

SB_RAS

SB_WE

SB_CAS

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_MA_15

SB_DQS_N_0
SB_DQS_N_1
SB_DQS_N_2
SB_DQS_N_3
SB_DQS_N_4
SB_DQS_N_5
SB_DQS_N_6
SB_DQS_N_7
SB_DQS_P_0
SB_DQS_P_1
SB_DQS_P_2
SB_DQS_P_3
SB_DQS_P_4
SB_DQS_P_5
SB_DQS_P_6
SB_DQS_P_7

RSVD

RSVD

AG8
Y4

M_CLK_DDR#2

AA4

M_CLK_DDR2

AF10

DDR_CKE2_DIMMB

Y3

M_CLK_DDR#3

AA3

M_CLK_DDR3

AG10

DDR_CKE3_DIMMB

Y2

M_CLK_DDR#6

AA2

M_CLK_DDR6

AG9
Y1

M_CLK_DDR#7

AA1

M_CLK_DDR7

AF9

DDR_CKE7_DIMMD

P4

DDR_CS2_DIMMB#

R2

DDR_CS3_DIMMB#

P3

DDR_CS6_DIMMD#

P1

DDR_CS7_DIMMD#

R4

M_ODT2

R3

M_ODT3

R1

M_ODT6

P2

M_ODT7

R7

DDR_B_BS0

P8

DDR_B_BS1

AA9

DDR_B_BS2

R10
R6

DDR_B_RAS#

P6

DDR_B_WE#

P7

DDR_B_CAS#

R8

DDR_B_MA0

Y5

DDR_B_MA1

Y10

DDR_B_MA2

AA5

DDR_B_MA3

Y7

DDR_B_MA4

AA6

DDR_B_MA5

Y6

DDR_B_MA6

AA7

DDR_B_MA7

Y8

DDR_B_MA8

AA10

DDR_B_MA9

R9

DDR_B_MA10

Y9

DDR_B_MA11

AF7

DDR_B_MA12

P9

DDR_B_MA13

AA8

DDR_B_MA14

AG7

DDR_B_MA15

AP18

DDR_B_DQS#0

AP11

DDR_B_DQS#1

AP5

DDR_B_DQS#2

AJ3

DDR_B_DQS#3

L3

DDR_B_DQS#4

H9

DDR_B_DQS#5

C8

DDR_B_DQS#6

C14

DDR_B_DQS#7

AP17

DDR_B_DQS0

AP12

DDR_B_DQS1

AP6

DDR_B_DQS2

AK3

DDR_B_DQS3

M3

DDR_B_DQS4

H8

DDR_B_DQS5

C9

DDR_B_DQS6

C15

DDR_B_DQS7

T76 PAD~D@T76 P AD~D@

M_CLK_DDR#2 15
M_CLK_DDR2 15
DDR_CKE2_DIMMB 15
M_CLK_DDR#3 15
M_CLK_DDR3 15
DDR_CKE3_DIMMB 15
M_CLK_DDR#6 13
M_CLK_DDR6 13

M_CLK_DDR#7 13
M_CLK_DDR7 13
DDR_CKE7_DIMMD 13

DDR_CS2_DIMMB# 15
DDR_CS3_DIMMB# 15
DDR_CS6_DIMMD# 13
DDR_CS7_DIMMD# 13

M_ODT2 15
M_ODT3 15
M_ODT6 13
M_ODT7 13
DDR_B_BS0 13,15
DDR_B_BS1 13,15
DDR_B_BS2 13,15

DDR_B_RAS# 13,15

DDR_B_WE# 13,15

DDR_B_CAS# 13,15

DDR_B_MA[0..15] 13,15

DDR_B_DQS#[0..7] 13,15

DDR_B_DQS[0..7] 13,15

1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/05/28 2013/05/27

2012/05/28 2013/05/27

2012/05/28 2013/05/27

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Title

Title

Title

CPU (3/7) DDRIII

CPU (3/7) DDRIII

CPU (3/7) DDRIII

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-9332P

LA-9332P

LA-9332P

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

1

7 56Friday, December 14, 2012

7 56Friday, December 14, 2012

7 56Friday, December 14, 2012

0.1

0.1

0.1

5

4

3

2

1

COMPENSATION PU FOR eDP

+VCOMP_OUT

EDP_COMP

D D

Haswell rPGA EDS

Haswell rPGA EDS

CPU_HDMI_N236
CPU_HDMI_P236
CPU_HDMI_N136
CPU_HDMI_P136

HDMI

mDP

C C

DMC

CPU_HDMI_N036
CPU_HDMI_P036
CPU_HDMI_N336
CPU_HDMI_P336

CPU_mDP_N031

CPU_mDP_P031

CPU_mDP_N131

CPU_mDP_P131

CPU_mDP_N231

CPU_mDP_P231

CPU_mDP_N331

CPU_mDP_P331

CPU_DPD_DMC_N039
CPU_DPD_DMC_P039
CPU_DPD_DMC_N139
CPU_DPD_DMC_P139
CPU_DPD_DMC_N239
CPU_DPD_DMC_P239
CPU_DPD_DMC_N339
CPU_DPD_DMC_P339

CPU_HDMI_N2
CPU_HDMI_P2
CPU_HDMI_N1
CPU_HDMI_P1
CPU_HDMI_N0
CPU_HDMI_P0
CPU_HDMI_N3
CPU_HDMI_P3

CPU_mDP_N0
CPU_mDP_P0
CPU_mDP_N1
CPU_mDP_P1
CPU_mDP_N2
CPU_mDP_P2
CPU_mDP_N3
CPU_mDP_P3

CPU_DPD_DMC_N0
CPU_DPD_DMC_P0
CPU_DPD_DMC_N1
CPU_DPD_DMC_P1
CPU_DPD_DMC_N2
CPU_DPD_DMC_P2
CPU_DPD_DMC_N3
CPU_DPD_DMC_P3

T28

DDIB_TXBN_0

U28

DDIB_TXBP_0

T30

DDIB_TXBN_1

U30

DDIB_TXBP_1

U29

DDIB_TXBN_2

V29

DDIB_TXBP_2

U31

DDIB_TXBN_3

V31

DDIB_TXBP_3

T34

DDIC_TXCN_0

U34

DDIC_TXCP_0

U35

DDIC_TXCN_1

V35

DDIC_TXCP_1

U32

DDIC_TXCN_2

T32

DDIC_TXCP_2

U33

DDIC_TXCN_3

V33

DDIC_TXCP_3

P29

DDID_TXDN_0

R29

DDID_TXDP_0

N28

DDID_TXDN_1

P28

DDID_TXDP_1

P31

DDID_TXDN_2

R31

DDID_TXDP_2

N30

DDID_TXDN_3

P30

DDID_TXDP_3

INTEL_HASWELL_HAS WELL

INTEL_HASWELL_HAS WELL

CONN@

CONN@

JCPU1H

JCPU1H

eDP

eDP

EDP_AUXN
EDP_AUXP

EDP_HPD

EDP_RCOMP

RSVD

EDP_TXN_0

EDP_TXP_0

EDP_TXN_1

EDP_TXP_1

FDI_TXN_0
FDI_TXP_0
FDI_TXN_1
FDI_TXP_1

DDI

DDI

8 OF 9

8 OF 9

M27
N27
P27
E24
R27

P35
R35
N34
P34
P33
R33
N32
P32

CPU_EDP_AUX#
CPU_EDP_AUX
EDP_HPD
EDP_COMP

CPU_EDP_N0
CPU_EDP_P0
CPU_EDP_N1
CPU_EDP_P1

T77PAD~D @T77PAD~D @

CPU_EDP_N0 40
CPU_EDP_P0 40
CPU_EDP_N1 40
CPU_EDP_P1 40

CPU_EDP_AUX# 40
CPU_EDP_AUX 40

CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.

12

RC124.9_0402_1%~D RC124.9_0402_1%~D

+VCCIO_OUT

12

10K_0402_5%~D

B B

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/05/28 2013/05/27

2012/05/28 2013/05/27

2012/05/28 2013/05/27

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

HPD INVERSION FOR EDP

CPU_EDP_HPD#40

2

100K_0402_5%~D

100K_0402_5%~D

12

RC75

RC75

Title

Title

Title

CPU (4/7) FDI,eDP,DDI

CPU (4/7) FDI,eDP,DDI

CPU (4/7) FDI,eDP,DDI

ize Document Number Rev

Size Document Number Rev

Size Document Number Rev

S

Custom

Custom

Custom

LA-9332P

LA-9332P

LA-9332P

Date: Sheet of

Date: Sheet of

Date: Sheet of

10K_0402_5%~D
RC65

RC65

EDP_HPD

BSS138_SOT23~D

BSS138_SOT23~D

13

D

D

QC10

QC10

2

G

G

S

S

Compal Electronics, Inc.

8 56Friday, December 14, 2012

8 56Friday, December 14, 2012

1

8 56Friday, December 14, 2012

0.1

0.1

0.1

5

4

3

2

1

CFG STRAPS for CPU

CFG2

D D

PEG Static Lane Reversal - CFG2 is for the 16x

1:(Default) Normal Operation; Lane #

CFG2

definition matches socket pin map definition
0:Lane Reversed

Haswell rPGA EDS

Haswell rPGA EDS

T103PAD~D@T103PAD~D@
T80 PAD~D@T80 PAD~D@
T78 PAD~D@T78 PAD~D@

T110PAD~D@T110PAD~D@
T81 PAD~D@T81 PAD~D@

T79 PAD~D@T79 PAD~D@

C C

B B

RC60 49.9_0402_1%~DRC60 49.9_0402_1%~D

RC58 49.9_0402_1%~DRC58 49.9_0402_1%~D

RC59 49.9_0402_1%~DRC59 49.9_0402_1%~D

12

H_CPU_TESTLO

12

CFG_RCOMP

12

H_CPU_RSVD

T101PAD~D@T101PAD~D@

T83 PAD~D@T83 PAD~D@
T108PAD~D@T108PAD~D@

+VCC_CORE

T82 PAD~D@T82 PAD~D@
T94 PAD~D@T94 PAD~D@

T85 PAD~D@T85 PAD~D@

T84 PAD~D@T84 PAD~D@ T95PAD~D @T95PAD~D @
T86 PAD~D@T86 PAD~D@

CFG06
CFG16
CFG26
CFG36
CFG46
CFG56
CFG66
CFG76
CFG86
CFG96
CFG106
CFG116
CFG126
CFG136
CFG146
CFG156

H_CPU_RSVD

H_CPU_TESTLO

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

AD10

W29
W28

W33
AL30
AL29

AL25

W30

W31

W34

AT20

AR20
AP20
AP22

AT22

AN22

AT25

AN23
AR24

AT23

AN20
AP24
AP26
AN25
AN26
AP25

AT1

RSVD_TP

AT2

RSVD_TP
RSVD

A34

RSVD_TP

A35

RSVD_TP

RSVD
RSVD

G26

RSVD
RSVD
RSVD
RSVD

F25

VCC

C35

RSVD_TP

B35

RSVD_TP

RSVD_TP

RSVD
RSVD
TESTLO

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15

CONN@

CONN@

I

I

NTEL_HASWELL_HA SWELL

NTEL_HASWELL_HA SWELL

JCPU1I

JCPU1I

RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP

CFG_RCOMP

CFG_16
CFG_18
CFG_17
CFG_19

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

RSVD

RSVD
RSVD

RSVD

RSVD_TP

RSVD_TP
RSVD_TP

RSVD
RSVD

RSVD
RSVD

9 OF 9

9 OF 9

C23
B23
D24
D23

AT31

CFG_RCOMP

AR21

CFG16

AR23

CFG18

AP21

CFG17

AP23

CFG19

AR33
G6
AM27
AM26
F5
AM2
K6

E18

U10
P10

B1

NC

A2
AR1

E21
E20

AP27
AR26

AL31
AL32

T99PAD~D @T99PAD~D @
T90PAD~D @T90PAD~D @
T87PAD~D @T87PAD~D @
T88PAD~D @T88PAD~D @

CFG16 6
CFG18 6
CFG17 6
CFG19 6

T91PAD~D @T91PAD~D @
T104PAD~D @T104PAD~D @
T92PAD~D @T92PAD~D @
T89PAD~D @T89PAD~D @
T93PAD~D @T93PAD~D @

T111PAD~D @T111PAD~D @

T96PAD~D @T96PAD~D @

T98PAD~D @T98PAD~D @
T97PAD~D @T97PAD~D @

T100PAD~D @T100PAD~D @
T109PAD~D @T109PAD~D @

T102PAD~D @T102PAD~D @
T107PAD~D @T107PAD~D @

T105PAD~D @T105PAD~D @
T106PAD~D @T106PAD~D @

CFG4

1 : Disabled; No Physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

CFG4

Display Port Presence Strap

CFG6

CFG5

PCIE Port Bifurcation Straps
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2

CFG[6:5]

disabled
01: Reserved - (Device 1 function 1 disabled ; function

2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CFG7

1K_0402_1%~D

1K_0402_1%~D

12

@RC76

@

RC76

1K_0402_1%~D

1K_0402_1%~D

12

RC77

RC77

1K_0402_1%~D

1K_0402_1%~D

1K_0402_1%~D

1K_0402_1%~D

12

12

@RC92

@

RC90

RC90

RC92

1K_0402_1%~D

1K_0402_1%~D

12

@RC91

@

RC91

PEG DEFER TRAINING

1: (Default) PEG Train immediately

A A

CFG7

following xxRESETB de assertion

0: PEG Wait for BIOS for training

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/05/28 2013/05/27

2012/05/28 2013/05/27

2012/05/28 2013/05/27

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Title

Title

Title

CPU (5/7) RSVD,CFG

CPU (5/7) RSVD,CFG

CPU (5/7) RSVD,CFG

ize Document Number Rev

Size Document Number Rev

Size Document Number Rev

S

Custom

Custom

Custom

LA-9332P

LA-9332P

LA-9332P

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

1

9 56Friday, December 14, 2012

9 56Friday, December 14, 2012

9 56Friday, December 14, 2012

0.1

0.1

0.1

5

D D

C C

B B

+1.35V_CPU_VDDQ Source

1 2

@

SUSP#43,56,59,60,61

CPU1.5V_S3_GATE43

SVID ALERT

VIDALERT_N62

SVID DATA

VIDSOUT62

VCC_SENSE

VCCSENSE62

130_0402_1%~D

130_0402_1%~D

@

RC93 0_0402_5%~D

RC93 0_0402_5%~D

1 2

@

@

RC79 0_0402_5%~D

RC79 0_0402_5%~D

+VCCIO_OUT

75_0402_1%~D

75_0402_1%~D

12

RC61

RC61

+VCCIO_OUT

1

12

RC63

RC63

VCCSENSE

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

+VCC_CORE

12

2

100_0402_1%~D

100_0402_1%~D

RC66

RC66

+3VALW

100K_0402_5%~D

100K_0402_5%~D

12

RC74

RC74

@

@

61

2

CAD Note: Place the PU resistors close to CPU
RC60 close to CPU 300 - 1500mils

12

H_CPU_SVIDALRT#

RC6943_0402_5%~D RC6943_0402_5%~D

CAD Note: Place the PU resistors close to CPU

CC192

CC192

RC63 close to CPU 300 - 1500mils

@

@

VIDSOUT

1

CC193

CC193

2

@

@

CAD Note: RC67 SHOULD BE PLACED CLOSE TO CPU

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

12

RC67

VCCSENSE_R

@RC67

@

0_0402_1%

0_0402_1%

CAD Note: RC68 SHOULD BE PLACED CLOSE TO CPU

VSSSENSE

VSSSENSE62

100_0402_1%~D

100_0402_1%~D

12

RC70

RC70

RC68

12

VSSSENSE_R

@RC68

@

0_0402_1%

0_0402_1%

RUN_ON_CPU1.5VS3#

DMN66D0LDW-7_SOT363-6~D

DMN66D0LDW-7_SOT363-6~D

QC4A

QC4A

@

@

CC194

4

RUN_ON_CPU1.5VS3# 56,6

@CC194

@

1 2

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

VSSSENSE_R 11

B+_BIAS

330K_0402_5%~D

330K_0402_5%~D

@

@

5

12

RC72

RC72

3

4

@

@

RUN_ON_CPU1.5VS3RUN_ON_CPU1.5VS3

DMN66D0LDW-7_SOT363-6~D

DMN66D0LDW-7_SOT363-6~D

QC4B

QC4B

+1.35V

1 2

PAD-OPEN 4x4m

PAD-OPEN 4x4m

1 2

PAD-OPEN 4x4m

PAD-OPEN 4x4m

@

@

QC3

QC3

AO4304L_SO8

AO4304L_SO8

8
7
6
5

4

0.022U_0402_25V7K~D

0.022U_0402_25V7K~D

1M_0402_5%~D

1M_0402_5%~D

12

RC143

RC143

1

@

@

2

+1.05VS

RC4 0_0603_5%~D@RC 4 0_0603_5%~D@

RESISTOR STUFFING OPTIONS ARE
PROVIDED FOR TESTING PURPOSES

+1.35V_CPU_VDDQ

CC136

CC136

JP4

JP4

JP5

JP5

1
2
3

@

@

@

@

@

@

+1.35V_CPU_VDDQ

1

@

@

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

CC180

CC180

2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

CC181

CC181

1

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

12

CC135

CC135

12

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

CC170

CC170

2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

CC182

CC182

1

2

C_0805NEW

C_0805NEW

3

+1.35V_CPU_VDDQ+1.35V

20K_0402_5%~D

20K_0402_5%~D

@RC73

@

RC73

+VCCIO_OUT

VDDQ DECOUPLING

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

1

CC169

CC169

2

2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

CC183

CC183

1

1

2

2

C_0805NEW

C_0805NEW

C_0805NEW

C_0805NEW

2

Haswell rPGA EDS

Haswell rPGA EDS

+1.35V_CPU_VDDQ

+VCC_CORE

AB11

AE11

AH11

AL27
AK27

AL35

AN35

AL16

AL13

AM28
AM29
AL28

AP35

AP34
AT35
AR35
AR32
AL26
AT34
AL22
AT33
AM21
AM25
AM22
AM20
AM24
AL19
AM23
AT32

W11

W32

K27
L27
T27
V27

AB2
AB5
AB8

AE2
AE5
AE8

K11
N11

N8

T11

T2
T5
T8

W2
W5
W8

N26
K26

E17

A23
F22

J27

H27

Y25
Y26
Y27
Y28
Y29
Y30
Y31
Y32
Y33
Y34
Y35

RSVD
RSVD
RSVD
RSVD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

RSVD
VCC
RSVD
RSVD

VCC_SENS E
RSVD
VCCIO_OUT
VCCIO2PCH
VCCIOA_O UT
RSVD
RSVD
VSS
RSVD

VIDALERT
VIDSCLK
VIDSOUT

VSS
PWR_DE BUG
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

I

I

CONN@

CONN@

T113 PAD~D@T113 PAD~D@
T114 PAD~D@T114 PAD~D@
T112 PAD~D@T112 PAD~D@
T116 PAD~D@T116 PAD~D@

+1.35V

+1.05VS

150_0402_5%~D

150_0402_5%~D

12

RC80

RC80

CPU_PWR_DEBUG

10K_0402_5%~D

10K_0402_5%~D

12

@

@

RC71

RC71

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

@

@

@

@

@

1

1

CC161

CC161

CC168

CC168

CC162

CC162

2

2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

CC184

CC184

CC185

CC185

CC186

CC186

1

1

2

2

C_0805NEW

C_0805NEW

C_0805NEW

C_0805NEW

@

@

@

1

1

CC164

CC164

CC163

CC163

2

2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

CC188

CC188

CC187

CC187

1

1

2

2

C_0805NEW

C_0805NEW

C_0805NEW

C_0805NEW

@

@

12

CC151 0.1U_0402_10V7K~D

CC151 0.1U_0402_10V7K~D

12

CC152 0.1U_0402_10V7K~D

CC152 0.1U_0402_10V7K~D

@

@

T115 PAD~D@T115 PAD~D@

+VCC_CORE

T151 PAD~D@T151 PAD~D@
T152 PAD~D@T152 PAD~D@

T153 PAD~D@T153 PAD~D@

+VCCIO_OUT

T156 PAD~D@T156 PAD~D

@

+VCOMP_OUT

T160 PAD~D@T160 PAD~D@
T159 PAD~D@T159 PAD~D@
T177 PAD~D@T177 PAD~D@
T154 PAD~D@T154 PAD~D@

VIDSCLK62

CPU_PWR_DEBUG6

T157 PAD~D@T157 PAD~D@
T158 PAD~D@T158 PAD~D@
T162 PAD~D@T162 PAD~D@
T163 PAD~D@T163 PAD~D@

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

330U_D2_2VM_R6M~D

330U_D2_2VM_R6M~D

1

@

@

CC167

1

2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

1

2

C_0805NEW

C_0805NEW

CC167

1

+

+

CC165

CC165

CC166

CC166

2

2

@

@

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

CC189

CC189

CC191

CC191

CC190

CC190

1

1

2

2

C_0805NEW

C_0805NEW

C_0805NEW

C_0805NEW

1

+

+

2

330U_D2_2VM_R6M~D

330U_D2_2VM_R6M~D

CC171

CC171

VCCSENSE_R

H_CPU_SVIDALRT#
VIDSCLK
VIDSOUT

JCPU1E

JCPU1E

NTEL_HASWELL_HASWELL

NTEL_HASWELL_HASWELL

5 OF 9

5 OF 9

1

+VCC_CORE

AA26

VCC

AA28

VCC

AA34

VCC

AA30

VCC

AA32

VCC

AB26

VCC

AB29

VCC

AB25

VCC

AB27

VCC

AB28

VCC

AB30

VCC

AB31

VCC

AB33

VCC

AB34

VCC

AB32

VCC

AC26

VCC

AB35

VCC

AC28

VCC

AD25

VCC

AC30

VCC

AD28

VCC

AC32

VCC

AD31

VCC

AC34

VCC

AD34

VCC

AD26

VCC

AD27

VCC

AD29

VCC

AD30

VCC

AD32

VCC

AD33

VCC

AD35

VCC

AE26

VCC

AE32

VCC

AE28

VCC

AE30

VCC

AG28

VCC

AG34

VCC

AE34

VCC

AF25

VCC

AF26

VCC

AF27

VCC

AF28

VCC

AF29

VCC

AF30

VCC

AF31

VCC

AF32

VCC

AF33

VCC

AF34

VCC

AF35

VCC

AG26

VCC

AH26

VCC

AH29

VCC

AG30

VCC

AG32

VCC

AH32

VCC

AH35

VCC

AH25

VCC

AH27

VCC

AH28

VCC

AH30

VCC

AH31

VCC

AH33

VCC

AH34

VCC

AJ25

VCC

AJ26

VCC

AJ27

VCC

AJ28

VCC

AJ29

VCC

AJ30

VCC

AJ31

VCC

AJ32

VCC

AJ33

VCC

AJ34

VCC

AJ35

VCC

G25

VCC

H25

VCC

J25

VCC

K25

VCC

L25

VCC

M25

VCC

N25

VCC

P25

VCC

R25

VCC

T25

VCC

U25

VCC

U26

VCC

V25

VCC

V26

VCC

W26

VCC

W27

VCC

@

@

@

@

@

@

@

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

@

@

@

Compal Secret Data

Compal Secret Data

2012/05/28 2013/05/27

2012/05/28 2013/05/27

2012/05/28 2013/05/27

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Title

Title

Title

CPU (6/7) PWR

CPU (6/7) PWR

CPU (6/7) PWR

ize Document Number Rev

Size Document Number Rev

Size Document Number Rev

S

Custom

Custom

Custom

LA-9332P

LA-9332P

LA-9332P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

10 56Friday, December 14, 2012

10 56Friday, December 14, 2012

10 56Friday, December 14, 2012

0.1

0.1

0.1

5

Haswell rPGA EDS

D D

C C

B B

Haswell rPGA EDS

A10

VSS

A13

VSS

A16

VSS

A19

VSS

A22

VSS

A25

VSS

A27

VSS

A29

VSS

A3

VSS

A31

VSS

A33

VSS

A4

VSS

A7

VSS

AA11

VSS

AA25

VSS

AA27

VSS

AA31

VSS

AA29

VSS

AB1

VSS

AB10

VSS

AA33

VSS

AA35

VSS

AB3

VSS

AC25

VSS

AC27

VSS

AB4

VSS

AB6

VSS

AB7

VSS

AB9

VSS

AC11

VSS

AD11

VSS

AC29

VSS

AC31

VSS

AC33

VSS

AC35

VSS

AD7

VSS

AE1

VSS

AE10

VSS

AE25

VSS

AE29

VSS

AE3

VSS

AE27

VSS

AE35

VSS

AE4

VSS

AE6

VSS

AE7

VSS

AE9

VSS

AF11

VSS

AF6

VSS

AF8

VSS

AG11

VSS

AG25

VSS

AE31

VSS

AG31

VSS

AE33

VSS

AG6

VSS

AH1

VSS

AH10

VSS

AH2

VSS

AG27

VSS

AG29

VSS

AH3

VSS

AG33

VSS

AG35

VSS

AH4

VSS

AH5

VSS

AH6

VSS

AH7

VSS

AH8

VSS

AH9

VSS

AJ11

VSS

AJ5

VSS

AK11

VSS

AK25

VSS

AK26

VSS

AK28

VSS

AK29

VSS

AK30

VSS

AK32

VSS

E19

VSS

NTEL_HASWELL_HA SWELL

NTEL_HASWELL_HA SWELL

I

I

CONN@

CONN@

JCPU1F

JCPU1F

4

AK34

VSS

AK5

VSS

AL1

VSS

AL10

VSS

AL11

VSS

AL12

VSS

AL14

VSS

AL15

VSS

AL17

VSS

AL18

VSS

AL2

VSS

AL20

VSS

AL21

VSS

AL23

VSS

E22

VSS

AL3

VSS

AL4

VSS

AL5

VSS

AL6

VSS

AL7

VSS

AL8

VSS

AL9

VSS

AM10

VSS

AM13

VSS

AM16

VSS

AM19

VSS

E25

VSS

AM32

VSS

AM4

VSS

AM7

VSS

AN10

VSS

AN13

VSS

AN16

VSS

AN19

VSS

AN2

VSS

AN21

VSS

AN24

VSS

AN27

VSS

AN30

VSS

AN34

VSS

AN4

VSS

AN7

VSS

AP1

VSS

AP10

VSS

AP13

VSS

AP16

VSS

AP19

VSS

AP4

VSS

AP7

VSS

W25

VSS

AR10

RSVD

AR13

VSS

AR16

VSS

AR19

VSS

AR2

VSS

AR22

VSS

AR25

VSS

AR28

VSS

AR31

VSS

AR34

VSS

AR4

VSS

AR7

VSS

AT10

VSS

AT13

VSS

AT16

VSS

AT19

VSS

AT21

VSS

AT24

VSS

AT27

VSS

AT3

VSS

AT30

VSS

AT4

VSS

AT7

VSS

B10

VSS

B13

VSS

B16

VSS

B19

VSS

B2

VSS

B22

VSS

6 OF 9

6 OF 9

3

Haswell rPGA EDS

Haswell rPGA EDS

B34

B4
B7

C1
C10
C13
C16
C19

C2
C22
C24
C26
C28
C30
C32
C34

C4

C7
D10
D13
D16
D19
D22
D25
D27
D29
D31
D33
D35

D4

D7

E1
E10
E13
E16

E4

E7
F10
F11
F12
F14
F15
F17
F18
F20
F21
F23
F24
F26
F28
F30
F32
F34

F4

F6

F7

F8

F9

G1
G11

G2
G27
G29

G3
G31
G33
G35

G4

G5
H10
H26

H6

H7

J11
J26
J28
J30
J32
J34

J6

K1

CONN@

CONN@

JCPU1G

JCPU1G

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RSVD
VSS
VSS
VSS
VSS
VSS

NTEL_HASWELL_HA SWELL

NTEL_HASWELL_HA SWELL

I

I

VSS_SENSE

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
RSVD
RSVD
RSVD
RSVD

RSVD

7 OF 9

7 OF 9

K10
K2
K29
K3
K31
K33
K35
K4
K5
K7
K8
K9
L11
L26
L6
M11
M26
M28
M30
M32
M34
M6
N1
N10
N2
N29
N3
N31
N33
N35
N4
N5
N6
N7
N9
P11
P26
P5
R11
R26
R28
R30
R32
R34
R5
T1
T10
T29
T3
T31
T33
T35
T4
T6
T7
T9
U11
U27
V11
V28
V30
V32
V34
W1
W10
W3
W35
W4
W6
W7
W9
Y11
H11
AL24
F19
T26
AK35
AK33

2

VSSSENSE_R 10

T120PAD~D @T120PAD~D @

1

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/05/28 2013/05/27

2012/05/28 2013/05/27

2012/05/28 2013/05/27

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Title

Title

Title

CPU (7/7) VSS

CPU (7/7) VSS

CPU (7/7) VSS

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-9332P

LA-9332P

LA-9332P

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

1

11 56Friday, December 14, 2012

11 56Friday, December 14, 2012

11 56Friday, December 14, 2012

0.1

0.1

0.1

5

D D

DDR_A_DQS#[0..7]14,7

DDR_A_D[0..63]14,7

DDR_A_DQS[0..7]14,7

DDR_A_MA[0..15]14,7

Layout Note:
Place near JDIMMA

C C

B B

A A

+1.35V

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD3

CD3

2

2

@

@

+1.35V

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

@

@

CD7

CD7

1

1

2

2

Layout Note:
Place near JDIMMA.203,204

+0.675VS

1

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD4

CD4

CD5

CD5

CD6

CD6

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD10

CD10

CD8

CD8

CD9

CD9

1

1

1

2

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD17

CD17

SA0

1

0

0

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD18

CD18

2

2

SA1

001

DIMA0

1

DIMB0

DIMA1

1

DIMB1

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

330U_SX_2VY~D

330U_SX_2VY~D

@CD13

@

CD11

CD11

CD19

CD19

1

CD74

CD74

CD13

1

1

+

+

2

2

2

@

@

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CD20

CD20

2

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

All VREF traces should
have 20 mil trace width

CD14

CD14

+3VS

RD38

RD38

1 2

RD21

@RD21

@

1 2

4

@

@

RD39

@ RD39

@

10K_0402_5%~D

10K_0402_5%~D

1 2

+3VS

RD22

RD22
0_0402_1%

0_0402_1%

1 2

+DIMM0_1_VREF_CPU

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1

CD1

CD1

@

@

2

DDR_CKE4_DIMMC7

DDR_A_BS214,7

M_CLK_DDR47
M_CLK_DDR#47

DDR_A_BS014,7

DDR_A_WE#14,7

DDR_A_CAS#14,7

DDR_CS5_DIMMC#7

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

CD21

CD21

1

2

3

JDIMMA H=9.2mm

JDIMA0

JDIMA0

VREF_DQ1VSS1

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

DDR_A_D0
DDR_A_D1

1

CD2

CD2

2

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9 DDR_A_D13

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_D26
DDR_A_D27

DDR_CKE4_DIMMC

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

M_CLK_DDR4
M_CLK_DDR#4

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13
DDR_CS5_DIMMC#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

+0.675VS

CD22

CD22

1

2

3

VSS2

5

DQ0

7

DQ1
VSS49DQS#0

11

DM0
VSS513VSS6

15

DQ2

17

DQ3
VSS719VSS8

21

DQ8

23

DQ9
VSS925VSS10
DQS#127DM1
DQS129RESET#
VSS1131VSS12
DQ1033DQ14
DQ1135DQ15
VSS1337VSS14
DQ1639DQ20
DQ1741DQ21
VSS1543VSS16
DQS#245DM2
DQS247VSS17
VSS1849DQ22
DQ1851DQ23
DQ1953VSS19
VSS2055DQ28
DQ2457DQ29
DQ2559VSS21
VSS2261DQS#3

63

DM3
VSS2365VSS24
DQ2667DQ30
DQ2769DQ31
VSS2571VSS26

CKE073CKE1
VDD175VDD2

77

NC1

79

BA2
VDD381VDD4
A12/BC#83A11

85

A9
VDD587VDD6

89

A8

91

A5
VDD793VDD8

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

TYCO_2-2013311-1

TYCO_2-2013311-1

CONN@

CONN@

VSS3

DQS0

DQ12
DQ13

DQS3

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

VTT2

2

+1.35V

1K_0402_5%~D

1K_0402_5%~D

12

RD27

RD27

@

@

CRB Rev 0.7 is depop

1 2

RD29 0_0402_5%~DRD29 0_0402_5%~D

All VREF traces should
have 20 mil trace width

TOP

CH B0

BOT

CH A0

DDR3_DRAMRST#_CPU 6DDR3_DRAMRST#_R13,14,15

(H9.2)CH A1

(H5.2)CH B1

(H5.2)

(H9.2)

+V_SM_VREF_CNT

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

CD15

CD15

1

2

DDR3_DRAMRST#_R

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

CD16

CD16

1

2

CPU

+1.35V+1.35V

2
4

DQ4
DQ5

DQ6
DQ7

A15
A14

CK1

BA1

S0#

NC2

DM4

DM6

SDA
SCL

DDR_A_D4

6

DDR_A_D5

8
10

DDR_A_DQS#0

12

DDR_A_DQS0

14
16

DDR_A_D6

18

DDR_A_D7

20
22

DDR_A_D12

24
26
28
30

DDR3_DRAMRST#_R

32
34

DDR_A_D14

36

DDR_A_D15

38
40

DDR_A_D20DDR_A_D16

42

DDR_A_D21

44
46
48
50

DDR_A_D22

52

DDR_A_D23

54
56

DDR_A_D28

58

DDR_A_D29

60
62

DDR_A_DQS#3

64

DDR_A_DQS3

66
68

DDR_A_D30

70

DDR_A_D31

72

74

DDR_CKE5_DIMMC

76
78

DDR_A_MA15

80

DDR_A_MA14

82
84

DDR_A_MA11

86

DDR_A_MA7

A7

88
90

DDR_A_MA6

A6

92

DDR_A_MA4

A4

94
96

DDR_A_MA2

A2

98

DDR_A_MA0

A0

100
102

M_CLK_DDR5

104

M_CLK_DDR#5

106
108

DDR_A_BS1

110

DDR_A_RAS#

112
114

DDR_CS4_DIMMC#

116

M_ODT4

118
120

M_ODT5

122
124
126
128
130

DDR_A_D36

132

DDR_A_D37

134
136
138
140

DDR_A_D38

142

DDR_A_D39

144
146

DDR_A_D44

148

DDR_A_D45

150
152

DDR_A_DQS#5

154

DDR_A_DQS5

156
158

DDR_A_D46

160

DDR_A_D47

162
164

DDR_A_D52

166

DDR_A_D53

168
170
172
174

DDR_A_D54

176

DDR_A_D55

178
180

DDR_A_D60

182

DDR_A_D61

184
186

DDR_A_DQS#7

188

DDR_A_DQS7

190
192

DDR_A_D62

194

DDR_A_D63

196
198

M_THERMAL#

200
202
204

206

G2

+0.675VS

DDR_CKE5_DIMMC 7

M_CLK_DDR5 7

M_CLK_DDR#5 7

DDR_A_BS1 14,7
DDR_A_RAS# 14,7

DDR_CS4_DIMMC# 7

M_ODT4 7

M_ODT5 7

M_THERMAL# 13,14,15,43

PCH_SMBDATA 13,14,15,19,49,50,51,53,6

PCH_SMBCLK 13,14,15,19,49,50,51,53,6

(Std)

(Std)

(Rev)

(Rev)

1

DIMM A1

DIMM B1

DIMM B0

DIMM A0

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/05/28 2013/05/27

2012/05/28 2013/05/27

2012/05/28 2013/05/27

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Title

Title

Title

DDRIII DIMMA

DDRIII DIMMA

DDRIII DIMMA

ize Document Number Rev

Size Document Number Rev

Size Document Number Rev

S

Custom

Custom

Custom

LA-9332P

LA-9332P

LA-9332P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

12 56Friday, December 14, 2012

12 56Friday, December 14, 2012

12 56Friday, December 14, 2012

0.1

0.1

0.1

5

4

3

2

1

D D

+DIMM0_1_CA_CPU

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

CD23

CD23

1

@

RD24

RD24

10K_0402_5%~D

10K_0402_5%~D

1 2

+3VS

RD41

@ RD41

@

10K_0402_5%~D

10K_0402_5%~D

1 2

@

2

DDR_CKE6_DIMMD7

M_CLK_DDR67
M_CLK_DDR#67

DDR_B_CAS#15,7

DDR_CS7_DIMMD#7

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

1

2

All VREF traces should
have 20 mil trace width

DDR_B_DQS#[0..7]15,7

DDR_B_D[0..63]15,7

DDR_B_DQS[0..7]15,7

DDR_B_MA[0..15]15,7

Layout Note:
Place near JDIMMB

C C

B B

A A

+1.35V

@

@

+1.35V

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

2

+0.675VS

CD29

CD29

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD25

CD25

CD26

CD26

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD31

CD31

CD30

CD30

1

1

1

2

2

2

Layout Note:
Place near JDIMMB.203,204

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD40

CD40

CD39

CD39

2

2

SA0

SA1

001

DIMA0

1

DIMB0

1

DIMA1

0

1

DIMB1

0

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD28

CD28

CD27

CD27

2

2

@

@

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD33

CD33

CD32

CD32

1

1

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

@

@

CD41

CD41

CD42

CD42

2

2

330U_SX_2VY~D

330U_SX_2VY~D

@CD35

@

1

CD34

CD34

CD35

CD36

CD36

1

+

+

2

2

+3VS

RD40

RD40

10K_0402_5%~D

10K_0402_5%~D

1 2

RD23

@RD23

@

10K_0402_5%~D

10K_0402_5%~D

1 2

DDR_B_D0
DDR_B_D1

CD24

CD24

1

DDR_B_D2

2

DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D27

DDR_CKE6_DIMMD

DDR_B_BS2

DDR_B_BS215,7

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

M_CLK_DDR6
M_CLK_DDR#6

DDR_B_MA10
DDR_B_BS0

DDR_B_BS015,7

DDR_B_WE#

DDR_B_WE#15,7

DDR_B_CAS#

DDR_B_MA13
DDR_CS7_DIMMD#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_D58
DDR_B_D59

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

CD43

CD43

CD44

CD44

1

2

JDIMMB H=5.2mm

+1.35V +1.35V

JDIMB0

JDIMB0

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1
VSS49DQS#0

11

DM0
VSS513VSS6

15

DQ2

17

DQ3
VSS719VSS8

21

DQ8

23

DQ9
VSS925VSS10
DQS#127DM1
DQS129RESET#
VSS1131VSS12
DQ1033DQ14
DQ1135DQ15
VSS1337VSS14
DQ1639DQ20
DQ1741DQ21
VSS1543VSS16
DQS#245DM2
DQS247VSS17
VSS1849DQ22
DQ1851DQ23
DQ1953VSS19
VSS2055DQ28
DQ2457DQ29
DQ2559VSS21
VSS2261DQS#3

63

DM3
VSS2365VSS24
DQ2667DQ30
DQ2769DQ31
VSS2571VSS26

CKE073CKE1
VDD175VDD2

77

NC1

79

BA2
VDD381VDD4
A12/BC#83A11

85

A9
VDD587VDD6

89

A8

91

A5
VDD793VDD8

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

+0.675VS

203

VTT1

205

G1

TYCO_2-2013290-1

TYCO_2-2013290-1

CONN@

CONN@

VSS3

DQS0

DQ12
DQ13

DQS3

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

VTT2

2
4

DQ4
DQ5

DQ6
DQ7

A15
A14

CK1

BA1

S0#

NC2

DM4

DM6

SDA
SCL

DDR_B_D4

6

DDR_B_D5

8
10

DDR_B_DQS#0

12

DDR_B_DQS0

14
16

DDR_B_D6

18

DDR_B_D7

20
22

DDR_B_D12

24

DDR_B_D13

26
28
30

DDR3_DRAMRST#_R

32
34

DDR_B_D14

36

DDR_B_D15

38
40

DDR_B_D20

42

DDR_B_D21

44
46
48
50

DDR_B_D22

52

DDR_B_D23

54
56

DDR_B_D28

58

DDR_B_D29

60
62

DDR_B_DQS#3

64

DDR_B_DQS3

66
68

DDR_B_D30

70

DDR_B_D31

72

74

DDR_CKE7_DIMMD

76
78

DDR_B_MA15

80

DDR_B_MA14

82
84

DDR_B_MA11

86

DDR_B_MA7

A7

88
90

DDR_B_MA6

A6

92

DDR_B_MA4

A4

94
96

DDR_B_MA2

A2

98

DDR_B_MA0

A0

100
102

M_CLK_DDR7

104

M_CLK_DDR#7

106
108

DDR_B_BS1

110

DDR_B_RAS#

112
114

DDR_CS6_DIMMD#

116

M_ODT6

118
120

M_ODT7

122
124
126
128
130

DDR_B_D36

132

DDR_B_D37

134
136
138
140

DDR_B_D38

142

DDR_B_D39

144
146

DDR_B_D44

148

DDR_B_D45

150
152

DDR_B_DQS#5

154

DDR_B_DQS5

156
158

DDR_B_D46

160

DDR_B_D47

162
164

DDR_B_D52

166

DDR_B_D53

168
170
172
174

DDR_B_D54

176

DDR_B_D55

178
180

DDR_B_D60

182

DDR_B_D61

184
186

DDR_B_DQS#7

188

DDR_B_DQS7

190
192

DDR_B_D62

194

DDR_B_D63

196
198

M_THERMAL#

200
202
204

206

G2

+0.675VS

DDR3_DRAMRST#_R 12,14,15

DDR_CKE7_DIMMD 7

M_CLK_DDR7 7

M_CLK_DDR#7 7

DDR_B_BS1 15,7
DDR_B_RAS# 15,7

DDR_CS6_DIMMD# 7

M_ODT6 7

+V_SM_VREF_CNT

M_ODT7 7

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

CD37

CD37

1

1

2

2

M_THERMAL# 12,14,15,43

PCH_SMBDATA 12,14,15,19,49,50,51,53,6

PCH_SMBCLK 12,14,15,19,49,50,51,53,6

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

CD38

CD38

CPU

All VREF traces should
have 20 mil trace width

TOP

BOT

CH B0

CH A0

(H9.2)CH A1

(H5.2)CH B1

(H5.2)

(H9.2)

(Std)

(Std)

(Rev)

(Rev)

DIMM A1

DIMM B1

DIMM B0

DIMM A0

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/05/28 2013/05/27

2012/05/28 2013/05/27

2012/05/28 2013/05/27

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Title

Title

Title

DDRIII DIMMB

DDRIII DIMMB

DDRIII DIMMB

ize Document Number Rev

Size Document Number Rev

Size Document Number Rev

S

Custom

Custom

Custom

LA-9332P

LA-9332P

LA-9332P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

13 56Friday, December 14, 2012

13 56Friday, December 14, 2012

13 56Friday, December 14, 2012

0.1

0.1

0.1

5

4

3

2

1

D D

All VREF traces should
have 20 mil trace width

DDR_A_DQS#[0..7]12,7

DDR_A_D[0..63]12,7

DDR_A_DQS[0..7]12,7

DDR_A_MA[0..15]12,7

Layout Note:
Place near JDIMMC

C C

B B

A A

+1.35V

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD12

CD12

2

2

+1.35V

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD56

CD56

1

1

2

2

@

@

Layout Note:
Place near JDIMMC.203,204

+0.675VS

1

2

SA0

1

0

0

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD54

CD54

CD59

CD59

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD64

CD64

SA1

001

1

1

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD47

CD47

CD63

CD63

2

2

@

@

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD46

CD46

CD62

CD62

1

1

1

2

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD51

CD51

2

2

DIMA0

DIMB0

DIMA1

DIMB1

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

330U_SX_2VY~D

330U_SX_2VY~D

@CD61

@

CD45

CD45

1

CD61

CD49

CD49

CD75

CD75

1

1

2

1

@

@

CD57

CD57

2

+

+

2

2

RD25

10K_0402_5%~D

10K_0402_5%~D

RD42

RD42

0_0402_1% @

0_0402_1% @

+3VS

@RD25

@

1 2

1 2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD55

CD55

RD43

@ RD43

@

10K_0402_5%~D

10K_0402_5%~D

1 2

+3VS

RD26

RD26

@

@

0_0402_1%

0_0402_1%

1 2

+DIMM0_1_VREF_CPU

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1

CD50

CD50

@

@

2

DDR_CKE0_DIMMA7

DDR_A_BS212,7

M_CLK_DDR07
M_CLK_DDR#07

DDR_A_BS012,7

DDR_A_WE#12,7

DDR_A_CAS#12,7

DDR_CS1_DIMMA#7

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

CD48

CD48

1

2

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

DDR_A_D0
DDR_A_D1

1

CD53

CD53

2

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9 DDR_A_D13

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13
DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

CD60

CD60

1

2

JDIMMC H=9.2mm

JDIMA1

JDIMA1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1
VSS49DQS#0

11

DM0
VSS513VSS6

15

DQ2

17

DQ3
VSS719VSS8

21

DQ8

23

DQ9
VSS925VSS10
DQS#127DM1
DQS129RESET#
VSS1131VSS12
DQ1033DQ14
DQ1135DQ15
VSS1337VSS14
DQ1639DQ20
DQ1741DQ21
VSS1543VSS16
DQS#245DM2
DQS247VSS17
VSS1849DQ22
DQ1851DQ23
DQ1953VSS19
VSS2055DQ28
DQ2457DQ29
DQ2559VSS21
VSS2261DQS#3

63

DM3
VSS2365VSS24
DQ2667DQ30
DQ2769DQ31
VSS2571VSS26

CKE073CKE1
VDD175VDD2

77

NC1

79

BA2
VDD381VDD4
A12/BC#83A11

85

A9
VDD587VDD6

89

A8

91

A5
VDD793VDD8

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

+0.675VS

203

VTT1

205

G1

TYCO_2-2013310-1

TYCO_2-2013310-1

CONN@

CONN@

VSS3

DQS0

DQ12
DQ13

DQS3

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

VTT2

+1.35V+1.35V

2
4

DQ4
DQ5

DQ6
DQ7

A15
A14

CK1

BA1

S0#

NC2

DM4

DM6

SDA
SCL

DDR_A_D4

6

DDR_A_D5

8
10

DDR_A_DQS#0

12

DDR_A_DQS0

14
16

DDR_A_D6

18

DDR_A_D7

20
22

DDR_A_D12

24
26
28
30

DDR3_DRAMRST#_R

32
34

DDR_A_D14

36

DDR_A_D15

38
40

DDR_A_D20DDR_A_D16

42

DDR_A_D21

44
46
48
50

DDR_A_D22

52

DDR_A_D23

54
56

DDR_A_D28

58

DDR_A_D29

60
62

DDR_A_DQS#3

64

DDR_A_DQS3

66
68

DDR_A_D30

70

DDR_A_D31

72

74

DDR_CKE1_DIMMA

76
78

DDR_A_MA15

80

DDR_A_MA14

82
84

DDR_A_MA11

86

DDR_A_MA7

A7

88
90

DDR_A_MA6

A6

92

DDR_A_MA4

A4

94
96

DDR_A_MA2

A2

98

DDR_A_MA0

A0

100
102

M_CLK_DDR1

104

M_CLK_DDR#1

106
108

DDR_A_BS1

110

DDR_A_RAS#

112
114

DDR_CS0_DIMMA#

116

M_ODT0

118
120

M_ODT1

122
124
126
128
130

DDR_A_D36

132

DDR_A_D37

134
136
138
140

DDR_A_D38

142

DDR_A_D39

144
146

DDR_A_D44

148

DDR_A_D45

150
152

DDR_A_DQS#5

154

DDR_A_DQS5

156
158

DDR_A_D46

160

DDR_A_D47

162
164

DDR_A_D52

166

DDR_A_D53

168
170
172
174

DDR_A_D54

176

DDR_A_D55

178
180

DDR_A_D60

182

DDR_A_D61

184
186

DDR_A_DQS#7

188

DDR_A_DQS7

190
192

DDR_A_D62

194

DDR_A_D63

196
198

M_THERMAL#

200
202
204

206

G2

+0.675VS

DDR3_DRAMRST#_R 12,13,15

DDR_CKE1_DIMMA 7

M_CLK_DDR1 7

M_CLK_DDR#1 7

DDR_A_BS1 12,7
DDR_A_RAS# 12,7

DDR_CS0_DIMMA# 7

M_ODT0 7

M_ODT1 7

+V_SM_VREF_CNT

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

CD52

CD52

1

2

M_THERMAL# 12,13,15,43

PCH_SMBDATA 12,13,15,19,49,50,51,53,6

PCH_SMBCLK 12,13,15,19,49,50,51,53,6

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

CD58

CD58

1

2

All VREF traces should
have 20 mil trace width

CPU

TOP

BOT

CH B0

CH A0

(H9.2)CH A1

(H5.2)CH B1

(H5.2)

(H9.2)

(Std)

(Std)

(Rev)

(Rev)

DIMM A1

DIMM B1

DIMM B0

DIMM A0

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/05/28 2013/05/27

2012/05/28 2013/05/27

2012/05/28 2013/05/27

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Title

Title

Title

DDRIII DIMMC

DDRIII DIMMC

DDRIII DIMMC

ize Document Number Rev

Size Document Number Rev

Size Document Number Rev

S

Custom

Custom

Custom

LA-9332P

LA-9332P

LA-9332P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

14 56Friday, December 14, 2012

14 56Friday, December 14, 2012

14 56Friday, December 14, 2012

0.1

0.1

0.1

5

4

3

2

1

D D

All VREF traces should
have 20 mil trace width

DDR_B_DQS#[0..7]13,7

DDR_B_D[0..63]13,7

DDR_B_DQS[0..7]13,7

DDR_B_MA[0..15]13,7

Layout Note:
Place near JDIMMD

+1.35V

@

@

+1.35V

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

2

+0.675VS

SA0

1

0

0

CD67

CD67

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD80

CD80

CD82

CD82

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD87

CD87

CD81

CD81

1

1

1

2

2

2

Layout Note:
Place near JDIMMD.203,204

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD89

CD89

CD77

CD77

2

2

SA1

001

DIMA0

1

DIMB0

DIMA1

1

DIMB1

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

@

@

CD71

CD71

CD78

CD78

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD79

CD79

1

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

@

@

1

CD86

CD86

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD65

CD65

1

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CD85

CD85

2

330U_SX_2VY~D

330U_SX_2VY~D

@CD70

@

1

CD70

CD68

CD68

CD88

CD88

1

+

+

2

2

+3VS

RD31

@RD31

@

10K_0402_5%~D

10K_0402_5%~D

RD44

RD44

@

@

0_0402_1%

0_0402_1%

C C

B B

A A

1 2

1 2

+DIMM0_1_CA_CPU

RD32

RD32

10K_0402_5%~D

10K_0402_5%~D

1 2

+3VS

RD45

@ RD45

@

10K_0402_5%~D

10K_0402_5%~D

1 2

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

@

@

CD84

CD84

1

2

DDR_CKE2_DIMMB7

M_CLK_DDR27
M_CLK_DDR#27

DDR_B_CAS#13,7

DDR_CS3_DIMMB#7

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

1

2

DDR_B_D0
DDR_B_D1

CD76

CD76

1

DDR_B_D2

2

DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_BS213,7

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

M_CLK_DDR2
M_CLK_DDR#2

DDR_B_MA10
DDR_B_BS0

DDR_B_BS013,7

DDR_B_WE#

DDR_B_WE#13,7

DDR_B_CAS#

DDR_B_MA13
DDR_CS3_DIMMB#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_D58
DDR_B_D59

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

CD66

CD66

CD69

CD69

1

2

JDIMMD H=5.2mm

+1.35V

JDIMB1

JDIMB1

3
5
7

11

15
17

21
23

63

77
79

85

89
91

95
97

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201

+0.675VS

203

205

TYCO_2-2013289-1

TYCO_2-2013289-1

CONN@

CONN@

VREF_DQ1VSS1
VSS2
DQ0
DQ1

VSS3
VSS49DQS#0
DM0

DQS0
VSS513VSS6
DQ2
DQ3
VSS719VSS8
DQ8

DQ12
DQ9

DQ13
VSS925VSS10
DQS#127DM1
DQS129RESET#
VSS1131VSS12
DQ1033DQ14
DQ1135DQ15
VSS1337VSS14
DQ1639DQ20
DQ1741DQ21
VSS1543VSS16
DQS#245DM2
DQS247VSS17
VSS1849DQ22
DQ1851DQ23
DQ1953VSS19
VSS2055DQ28
DQ2457DQ29
DQ2559VSS21
VSS2261DQS#3
DM3

DQS3
VSS2365VSS24
DQ2667DQ30
DQ2769DQ31
VSS2571VSS26

CKE073CKE1
VDD175VDD2
NC1
BA2
VDD381VDD4
A12/BC#83A11
A9
VDD587VDD6
A8
A5
VDD793VDD8
A3
A1
VDD999VDD10
CK0
CK0#

CK1#
VDD11

VDD12
A10/AP
BA0

RAS#

VDD13

VDD14
WE#
CAS#

ODT0

VDD15

VDD16
A13

ODT1
S1#
VDD17

VDD18

NCTEST

VREF_CA

VSS27

VSS28

DQ32

DQ36
DQ33

DQ37
VSS29

VSS30
DQS#4
DQS4

VSS31
VSS32

DQ38

DQ34

DQ39

DQ35

VSS33
VSS34

DQ44

DQ40

DQ45

DQ41

VSS35
VSS36

DQS#5

DM5

DQS5

VSS37

VSS38
DQ42

DQ46

DQ43

DQ47

VSS39

VSS40
DQ48

DQ52

DQ49

DQ53

VSS41

VSS42
DQS#6
DQS6

VSS43
VSS44

DQ54

DQ50

DQ55

DQ51

VSS45
VSS46

DQ60

DQ56

DQ61

DQ57

VSS47
VSS48

DQS#7

DM7

DQS7

VSS49

VSS50
DQ58

DQ62

DQ59

DQ63

VSS51

VSS52
SA0

EVENT#
VDDSPD
SA1
VTT1

VTT2

G1

+1.35V

2
4

DQ4
DQ5

DQ6
DQ7

A15
A14

CK1

BA1

S0#

NC2

DM4

DM6

SDA
SCL

DDR_B_D4

6

DDR_B_D5

8
10

DDR_B_DQS#0

12

DDR_B_DQS0

14
16

DDR_B_D6

18

DDR_B_D7

20
22

DDR_B_D12

24

DDR_B_D13

26
28
30

DDR3_DRAMRST#_R

32
34

DDR_B_D14

36

DDR_B_D15

38
40

DDR_B_D20

42

DDR_B_D21

44
46
48
50

DDR_B_D22

52

DDR_B_D23

54
56

DDR_B_D28

58

DDR_B_D29

60
62

DDR_B_DQS#3

64

DDR_B_DQS3

66
68

DDR_B_D30

70

DDR_B_D31

72

74

DDR_CKE3_DIMMB

76
78

DDR_B_MA15

80

DDR_B_MA14

82
84

DDR_B_MA11

86

DDR_B_MA7

A7

88
90

DDR_B_MA6

A6

92

DDR_B_MA4

A4

94
96

DDR_B_MA2

A2

98

DDR_B_MA0

A0

100
102

M_CLK_DDR3

104

M_CLK_DDR#3

106
108

DDR_B_BS1

110

DDR_B_RAS#

112
114

DDR_CS2_DIMMB#

116

M_ODT2

118
120

M_ODT3

122
124
126
128
130

DDR_B_D36

132

DDR_B_D37

134
136
138
140

DDR_B_D38

142

DDR_B_D39

144
146

DDR_B_D44

148

DDR_B_D45

150
152

DDR_B_DQS#5

154

DDR_B_DQS5

156
158

DDR_B_D46

160

DDR_B_D47

162
164

DDR_B_D52

166

DDR_B_D53

168
170
172
174

DDR_B_D54

176

DDR_B_D55

178
180

DDR_B_D60

182

DDR_B_D61

184
186

DDR_B_DQS#7

188

DDR_B_DQS7

190
192

DDR_B_D62

194

DDR_B_D63

196
198

M_THERMAL#

200
202
204

206

G2

+0.675VS

DDR3_DRAMRST#_R 12,13,14

DDR_CKE3_DIMMB 7

M_CLK_DDR3 7

M_CLK_DDR#3 7

DDR_B_BS1 13,7
DDR_B_RAS# 13,7

DDR_CS2_DIMMB# 7

M_ODT2 7

+V_SM_VREF_CNT

M_ODT3 7

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

CD72

CD72

1

1

2

2

CPU

M_THERMAL# 12,13,14,43

PCH_SMBDATA 12,13,14,19,49,50,51,53,6

PCH_SMBCLK 12,13,14,19,49,50,51,53,6

CD83

CD83

All VREF traces should
have 20 mil trace width

TOP

CH B0

BOT

CH A0

(H9.2)CH A1

(H5.2)CH B1

(H5.2)

(H9.2)

(Std)

(Std)

(Rev)

(Rev)

DIMM A1

DIMM B1

DIMM B0

DIMM A0

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/05/28 2013/05/27

2012/05/28 2013/05/27

2012/05/28 2013/05/27

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Title

Title

Title

DDRIII DIMMD

DDRIII DIMMD

DDRIII DIMMD

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-9332P

LA-9332P

LA-9332P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

15 56Friday, December 14, 2012

15 56Friday, December 14, 2012

15 56Friday, December 14, 2012

0.1

0.1

0.1

5

+RTC_CELL

12

4

330K_0402_1%~D

330K_0402_1%~D

RH38

RH38

3

2

1

D D

INTVRMEN - INTEGRATED SUS 1.05V VRM
ENABLE
High - Enable Internal VRs
Low - Enable External VRs

+3VS

RH35 10K_0402_5%~D@ RH35 10K_0402_5%~D@

NO REBOOT STRAP

DISABLED WHEN LOW (DEFAULT)
ENABLED WHEN HIGH

C C

+3VS

RH355 100K_0402_5%~D

RH355 100K_0402_5%~D

CMOS_CLR1

Shunt Clear CMOS

Open

ME_CLR1

Shunt Clear ME RTC Registers

Open

HDA_SYNC Isolation Circuit

B B

A A

W=20mils

12

1 2

1 2

@

@

CMOS setting

Keep CMOS

TPM setting

Keep ME RTC Registers

1

CH12

CH12
1U_0603_10V6K

1U_0603_10V6K

2

5

PCH_INTVRMEN

330K_0402_1%~D

330K_0402_1%~D

@RH39

@

RH39

HDA_SPKR

PCH_GPIO33

1M_0402_5%~D

1M_0402_5%~D

RH31

RH31

1 2

+3V_PCH

RH287 1K_0402_1%~D@RH287 1K_0402_1%~D@

FLASH DESCRIPTOR SECURITY OVERRIDE

LOW = DESABLED (DEFAULT)
HIGH = ENABLED

1

@

@

ME1 SHORT PADS~D

ME1 SHORT PADS~D

+5VS

G

G

2

13

PCH_AZ_SYNCPCH_AZ_SYNC_Q

D

S

D

S

QH8

QH8

SSM3K7002FU_SC70-3~D

SSM3K7002FU_SC70-3~D

+RTC_CELL

1 2

PCH_AZ_SDOUT

+RTC_CELL

2

1

2

1 2

CH5 1U_0402_6.3V6K~DCH5 1U_0402_6.3V6K~D

+3V_PCH

RH286

CH2

CH2

1 2

1 2

12

PCH_RTCX1_R

CH3

CH3

18P_0402_50V8J~D

18P_0402_50V8J~D

1 2

RH22 20K_0402_5%~DRH22 20K_0402_5%~D

1 2

RH11 1M_0402_5%~DRH11 1M_0402_5%~D

1 2

RH23 20K_0402_5%~DRH23 20K_0402_5%~D

1

CH4

CH4

CMOS place near DIMM

0_0603_5%~D

0_0603_5%~D

12

RH288

RH288

+3.3V_ALW_PCH_JTAG PCH_JTAG_TMS

@

@

18P_0402_50V8J~D

18P_0402_50V8J~D

2

1

2

@

@

CMOS1 SHORT PADS~D

CMOS1 SHORT PADS~D

1 2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

RH59 51_0402_1%~DRH59 51_0402_1%~D

1 2

RH44 210_0402_1%~D

RH44 210_0402_1%~D

@

@

1 2

RH45 210_0402_1%~D

RH45 210_0402_1%~D

@

@

1 2

RH46 210_0402_1%~D

RH46 210_0402_1%~D

@

@

RH286

1 2

12

YH1

YH1

32.768KHZ_12.5PF_Q13FC1350000~D

32.768KHZ_12.5PF_Q13FC1350000~D

PCH_AZ_CODEC_SDIN045

HDA_SDO43

RH50 1K_0402_1%~DRH50 1K_0402_1%~D

PCH_mDP_HPD17,31

100_0402_1%~D

100_0402_1%~D

100_0402_1%~D

100_0402_1%~D

100_0402_1%~D

100_0402_1%~D

12

12

12

RH47

RH47

RH48

RH48

RH49

RH49

0_0402_1%@

0_0402_1%@

HDA_SPKR45

T175 PAD~D

T175 PAD~D

HDA for Codec

1 2

PCH_AZ_CODEC_SDOUT45

PCH_AZ_CODEC_SYNC45

PCH_AZ_CODEC_RST#45

PCH_AZ_CODEC_BITCLK45

1

2

4

RH29 33_0402_5%~DRH29 33_0402_5%~D

RH56 33_0402_5%~DRH56 33_0402_5%~D

RH27 33_0402_5%~DRH27 33_0402_5%~D

RH26 33_0402_5%~DRH26 33_0402_5%~D

27P_0402_50V8J~D

27P_0402_50V8J~D

@CH101

@

CH101

1 2

1 2

1 2

PCH_AZ_SDOUT

PCH_AZ_SYNC_Q

PCH_AZ_RST#

PCH_AZ_BITCLK

PCH_RTCX1

12

RH2

RH2
10M_0402_5%~D

10M_0402_5%~D

PCH_RTCX2

SRTCRST#

INTRUDER#

PCH_INTVRMEN

PCH_RTCRST#

PCH_AZ_BITCLK

PCH_AZ_SYNC

HDA_SPKR

PCH_AZ_RST#

PCH_AZ_CODEC_SDIN0

1 2

PCH_AZ_SDOUT

PCH_GPIO33

PCH_mDP_HPD

PCH_JTAG_TCK

PCH_JTAG_TDI

PCH_JTAG_TDO

@

@

1 2

RH289 0_0402_1%

RH289 0_0402_1%

@

@

T122 PAD~D

T122 PAD~D

@

@

PCH_TP25

PCH_JTAG_RST

3

PCH_GPIO21

BBS_BIT0_R

PCH_SATALED#

LPT_PCH_M_EDS

UH1A

UH1A

B5

RTCX1

B4

RTCX2

B9

SRTCRST#

A8

INTRUDER#

G10

INTVRMEN

D9

RTCRST#

B25

HDA_BCLK

A22

HDA_SYNC

AL10

SPKR

C24

HDA_RST#

L22

HDA_SDI0

K22

HDA_SDI1

G22

HDA_SDI2

F22

HDA_SDI3

A24

HDA_SDO

B17

DOCKEN#/G PIO33

C22

HDA_DOCK_ RST#/GPIO13

AB3

JTAG_TCK

AD1

JTAG_TMS

AE2

JTAG_TDI

AD3

JTAG_TDO

F8

TP25

C26

TP22

AB6

TP20

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

LPT_PCH_M_EDS

JTAGRTC AZALIA

JTAGRTC AZALIA

LYNXPOINT_BGA695

LYNXPOINT_BGA695

BC8

TP9

TP8

SATA_PRX_DTX_N0

BE8

SATA_PRX_DTX_P0

AW8

SATA_PTX_DRX_N0

AY8

SATA_PTX_DRX_P0

BC10

SATA_PRX_DTX_N1

BE10

SATA_PRX_DTX_P1

AV10

SATA_PTX_DRX_N1

AW10

SATA_PTX_DRX_P1

BB9
BD9

AY13
AW13

BC12
BE12

AR13
AT13

BD13

SATA_ODD_PRX_DTX_N4

BB13

SATA_ODD_PRX_DTX_P4

AV15

SATA_ODD_PTX_DRX_N4

AW15

SATA_ODD_PTX_DRX_P4

BC14

MSATA_PRX_DTX_N5

BE14

MSATA_PRX_DTX_P5

AP15

MSATA_PTX_DRX_N5

AR15

MSATA_PTX_DRX_P5

AY5

SATA_COMP

AP3

PCH_SATALED#

AT1

PCH_GPIO21

AU2

BBS_BIT0_R

BD4

SATA_IREF

BA2

BB2

0_0402_1%

0_0402_1%

@ RH41

@

T161PAD~D @T161PAD~D @

T155PAD~D @T155PAD~D @

5

5

SATA

SATA

SATA_RXN_ 0
SATA_RXP_ 0

SATA_TXN_0
SATA_TXP_0

SATA_RXN_ 1
SATA_RXP_ 1

SATA_TXN_1
SATA_TXP_1

SATA_RXN_ 2
SATA_RXP_ 2

SATA_TXN_2
SATA_TXP_2

SATA_RXN_ 3
SATA_RXP_ 3

SATA_TXN_3
SATA_TXP_3

SATA_RXN4 /PERN1

SATA_RXP4 /PERP1

SATA_TXN4/P ETN1
SATA_TXP4/P ETP1

SATA_RXN5 /PERN2

SATA_RXP5 /PERP2

SATA_TXN5/P ETN2
SATA_TXP5/P ETP2

SATA_RCOMP

SATALED#

SATA0GP/G PIO21

SATA1GP/G PIO19

SATA_IREF

SATA Impedance Compensation

1 OF 11

1 OF 11

Compal Secret Data

Compal Secret Data

2012/05/28 2013/05/27

2012/05/28 2013/05/27

2012/05/28 2013/05/27

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

SATA_COMP

CAD note:
Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.

SATA_PRX_DTX_N0 49
SATA_PRX_DTX_P0 49

SATA_PTX_DRX_N0 49
SATA_PTX_DRX_P0 49

SATA_PRX_DTX_N1 49
SATA_PRX_DTX_P1 49

SATA_PTX_DRX_N1 49
SATA_PTX_DRX_P1 49

SATA_ODD_PRX_DTX_N4 50
SATA_ODD_PRX_DTX_P4 50

SATA_ODD_PTX_DRX_N4 50
SATA_ODD_PTX_DRX_P4 50

MSATA_PRX_DTX_N5 50
MSATA_PRX_DTX_P5 50

MSATA_PTX_DRX_N5 50
MSATA_PTX_DRX_P5 50

PCH_SATALED# 48

12

RH41

1 2

1 2

+3VS

RH3010K_0402_5%~D RH3010K_0402_5%~D

12

RH524. 7K_0402_5%~D RH524.7K_0402_5%~D

RH5510K_0402_5%~D RH5510K_0402_5%~D

HDD1(Master)

HDD2(Slave)

ODD/HDD3 Bay

mSATA

+1.5VS

+1.5VS

1 2

RH407.5K_0402_1%~D RH407.5K_0402_1%~D

Compal Electronics, Inc.

Title

Title

Title

PCH (1/9) RTC,HDA,SATA,XDP

PCH (1/9) RTC,HDA,SATA,XDP

PCH (1/9) RTC,HDA,SATA,XDP

ize Document Number Rev

Size Document Number Rev

Size Document Number Rev

S

Custom

Custom

Custom

LA-9332P

LA-9332P

LA-9332P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

0.1

0.1

16 56Friday, December 14, 2012

16 56Friday, December 14, 2012

16 56Friday, December 14, 2012

0.1

5

D D

+3V_PCH

1 2

RH318 10K_0402_5%~D@RH318 10K_0402_5%~D@

RH153 10K_0402_5%~DR H153 10K_0402_5%~D

@

@

RH148 10K_0402_5%~D

RH148 10K_0402_5%~D

RH177 10K_0402_5%~DR H177 10K_0402_5%~D

RH172 10K_0402_5%~DR H172 10K_0402_5%~D

+3VS

RH138 8.2K_0402_5%~DRH138 8.2K_0402_5%~D

RH152 8.2K_0402_5%~D@RH152 8.2K_0402_5%~D@

DMI_CTX_PRX_N05
DMI_CTX_PRX_N15

DMI_CTX_PRX_N25
DMI_CTX_PRX_N35

DMI_CTX_PRX_P05

+1.5VS

+1.5VS

SG_AMD_BKL42,43

SYS_PWROK6

PCH_PWROK43

SUSPWRDNACK43

PBTN_OUT#43,6

+PCH_VCCDSW3_3

IMVP_PWRGD43, 6,62

10K_0402_5%

10K_0402_5%

ACIN29,43,47,57,64

DMI_CTX_PRX_P15

DMI_CTX_PRX_P25
DMI_CTX_PRX_P35

DMI_CRX_PTX_N05
DMI_CRX_PTX_N15

DMI_CRX_PTX_N25
DMI_CRX_PTX_N35

DMI_CRX_PTX_P05
DMI_CRX_PTX_P15

DMI_CRX_PTX_P25
DMI_CRX_PTX_P35

R1899

R1899

2

RH330 0_0402_5%~D

RH330 0_0402_5%~D

C C

PM_DRAM_PWRGD6

PCH_RSMRST#43

B B

A A

SUS_STAT#

1 2

1 2

1 2

1 2

1 2

1 2

SUSPWRDNACK

PCIE_WAKE#

PCH_WAKE#

PCH_RI#

PM_CLKRUN#

ME_RESET#

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1

DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1

DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1

DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1

DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

0_0402_1%

0_0402_1%

12

DMI_IREF

RH43

RH43

@

@

T139 PAD~D@ T139 PAD~D@

T123 PAD~D@ T123 PAD~D@

1 2

RH204 7.5K_0402_1%~DRH204 7.5K_0402_1%~D

1 2

RH114 0_0402_5%~D@RH114 0_0402_5%~D@

@

@

1 2

@

@

RH193 0_0402_1%

RH193 0_0402_1%

1 2

@

@

RH144 0_0402_1%

RH144 0_0402_1%

1 2

RH149 0_0402_1%

RH149 0_0402_1%

1 2

RH320 0_0402_5%~DRH320 0_0402_5%~D

1 2

RH185 0_0402_5%~DRH185 0_0402_5%~D

1 2

RH200 0_0402_5%~DRH200 0_0402_5%~D

1 2

RH163 0_0402_1%@RH163 0_0402_1%@

1 2

RH156 8.2K_0402_5%~DRH156 8.2K_0402_5%~D

T140 PAD~D@T140 PAD~D@

+3VS

1

CH41

CH41

@

@

0.1U_0402_16V7K

0.1U_0402_16V7K

2

5

1

PCH_PWROK

+3V_PCH

12

61

DMN66D0LDW-7_SOT363-6~D

DMN66D0LDW-7_SOT363-6~D
QH13A

QH13A

IN1

2

IN2

+3V_PCH

12

R1900

R1900
10K_0402_5%

10K_0402_5%

ACIN_PCH

34

DMN66D0LDW-7_SOT363-6~D

DMN66D0LDW-7_SOT363-6~D

5

QH13B

QH13B

VCC

GND

3

1 2

@

@

5

DMI_RCOMP

SUSACK#_R

SYS_RESET#

SYS_PWROK_R

PCH_PWROK_R

PM_APWROK_R

PM_DRAM_PWRGD_R

PCH_RSMRST#_R

ME_SUS_PWR_ACK_R

SIO_PWRBTN#_R

ACIN_PCH

PCH_BATLOW#

PCH_RI#

UH9

UH9

4

SYS_PWROK

OUT

MC74VHC1G08DFT2G_SC70-5

MC74VHC1G08DFT2G_SC70-5

XDP_DBRESET#6

UH1B

UH1B

AW22

DMI_RXN_0

AR20

DMI_RXN_1

AP17

DMI_RXN_2

AV20

DMI_RXN_3

AY22

DMI_RXP_0

AP20

DMI_RXP_1

AR17

DMI_RXP_2

AW20

DMI_RXP_3

BD21

DMI_TXN_0

BE20

DMI_TXN_1

BD17

DMI_TXN_2

BE18

DMI_TXN_3

BB21

DMI_TXP_0

BC20

DMI_TXP_1

BB17

DMI_TXP_2

BC18

DMI_TXP_3

BE16

DMI_IREF

AW17

TP12

AV17

TP7

AY17

DMI_RCOMP

R6

SUSACK#

AM1

SYS_RESE T#

AD7

SYS_PW ROK

F10

PWROK

AB7

APWROK

H3

DRAMPWR OK

J2

RSMRST#

J4

SUSWAR N#/SUSPWR NACK/GPIO30

K1

PWRBTN#

E6

ACPRESEN T/GPIO31

K7

BATLOW# /GPIO72

N4

RI#

AB10

TP21

D2

SLP_W LAN#/GPIO2 9

RH328 1K_0402_1%~D@RH328 1K_0402_1%~D@

LYNXPOINT_BGA695

LYNXPOINT_BGA695

1 2

4

@

@

1 2

RH195 0_0402_1%

RH195 0_0402_1%

ME_SUS_PWR_ACK_R SUSACK#_R

LPT_PCH_M_EDS

LPT_PCH_M_EDS

DMI

DMI

1 2

RH323 0_0402_5%~DRH323 0_0402_5%~D

5

5

FDI

FDI

SYS_RESET#

FDI_RXN_0

FDI_RXN_1

FDI_RXP_0

FDI_RXP_1

FDI_CSYNC

FDI_INT

FDI_IREF

FDI_RCOMP

System Power

System Power

Management

Management

BBS_BIT1

4 OF 11

4 OF 11

DSWVRME N

DPWROK

CLKRUN#

SUS_STAT#/G PIO61

SUSCLK/G PIO62

SLP_S5# /GPIO63

SLP_S4#

SLP_S3#

SLP_SUS #

PMSYNCH

SLP_LAN #

GNT1#/GPIO51
(BBS_BIT1)

WAKE#

SLP_A#

0 1 Reserved (NAND)

1 0

*

GPIO51 has internal pull up.

4

AJ35

AL35

AJ36

AL36

AV43

TP16

AY45

TP5

AV45

TP15

AW44

TP10

AL39

FDI_CSYNC

AL40

FDI_INT

AT45

FDI_IREF

AU42

TP17

AU44

TP13

AR44

FDI_RCOMP

C8

DSWODVREN

L13

PCH_DRWROK_R

K3

AN7

PM_CLKRUN#

U7

SUS_STAT#

Y6

SUSCLK_R

Y7

PM_SLP_S5#

C6

PM_SLP_S4#

H1

PM_SLP_S3#

F3

F1

PM_SLP_SUS#

AY3

H_PM_SYNC

G5

Boot BIOS Strap

SATA1GP/GPIO19
(BBS_BIT0)

00 LPC

11 SPI

+3VS

1 2

@

@

RV122 2.2K_0402_5%~D

RV122 2.2K_0402_5%~D

1 2

RV123 2.2K_0402_5%~D@R V123 2.2K_0402_5%~D@

FDI_CSYNC 5

FDI_INT 5

@

12

RH420_0402_1%@RH420_0402_1%

T145PAD~D @T145PAD~D @

T146PAD~D @T146PAD~D @

12

RH2067.5K_0402_1%~D RH2067.5K_0402_1%~D

RH167

RH167

1 2
1 2

RH186 0_0402_5%~D@RH186 0_0402_5%~D@

1 2

RH192 0_0402_5%~D@RH192 0_0402_5%~D@

T129 PAD~D@T129 PAD~D@

T143 PAD~D@T143 PAD~D@

PM_SLP_S5# 43,47

T125 PAD~D

T125 PAD~D

PM_SLP_S4# 43

PM_SLP_S3# 43,47

T128 PAD~D

T128 PAD~D

PM_SLP_SUS# 43

T127 PAD~D

T127 PAD~D

H_PM_SYNC 6

Boot BIOS Location

PCI

3

PCH_DPC_MDP_CLK

PCH_DPC_MDP_DAT

+1.5VS

+1.5VS

PCH_RSMRST#_R

0_0402_5%~D

0_0402_5%~D

PCH_DPWROK 43

PCIE_WAKE#PCH_WAKE#

@

@

@

@

@

@

3

2

LPT_PCH_M_EV

HDMI_IN_PWMSEL#42

PCIE_WAKE# 43,44,51

T126 PAD~D@T126 PAD~D@

1 2

RH139 649_0402_1%~DRH139 649_0402_1%~D

WL_OFF#51

PCH_EDP_PWM

PCI_PIRQA#

PCI_PIRQB#

PCI_PIRQC#

PCI_PIRQD#

DGPU_HOLD_RST#

DGPU_SELECT#

BBS_BIT1

HDMI_IN_PWMSEL#

WL_OFF#

+3V_MXM

DGPU_HOLD_RST#

+RTC_CELL

330K_0402_1%~D

330K_0402_1%~D

RH191

RH191

PCH_EDP_PWM40

DGPU_SELECT#31,36,42

MXM_RST43

1 2

DSWODVREN

330K_0402_1%~D

330K_0402_1%~D

@RH178

@

RH178

12

0_0402_5%~D@

0_0402_5%~D@

1 2

RH198 0_0402_5%~D@RH198 0_0402_5%~D@

LPT_PCH_M_EV

L

L

YNXPOINT_BGA695

YNXPOINT_BGA695

+3VS

5

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

1

P

B

2

A

G

TC7SH08FU_SSOP5~D

TC7SH08FU_SSOP5~D

3

T45

VGA_BLU E

U44

VGA_GRE EN

V45

VGA_RED

M43

VGA_DDC_ CLK

M45

VGA_DDC_ DATA

N42

VGA_HSYNC

N44

VGA_VSYN C

U40

DAC_IREF

U39

VGA_IRTN

N36

EDP_BKL TCTL

K36

EDP_BKL TEN

G36

EDP_VDDE N

H20

PIRQA#

L20

PIRQB#

K17

PIRQC#

M20

PIRQD#

A12

GPIO50

B13

GPIO52

C12

GPIO54

C10

GPIO51

A10

GPIO53

AL6

GPIO55

1 2

RH211 100K_0402_5%~DRH211 100K_0402_5%~D
RH202 0_0402_5%~D@RH202 0_0402_5%~D@

1 2

RH168

RH168

MXM_RST_A

PCH_PLTRST#

O

LVDSCRT

LVDSCRT

CH147

CH147

1 2

4

PCI

PCI

5 OF 11

5 OF 11

MXM_RST_A

@

@

PLTRST_VGA#

UH6

UH6

DISPLAY

DISPLAY

5UH1E

5UH1E

DDPB_CTRLDA TA

DDPC_CTRLDATA

DDPD_CTRLDATA

+3V_MXM

DDPB_CTRLCL K

DDPC_CTRLCLK

DDPD_CTRLCLK

DDPB_AUX N

DDPC_AUXN

DDPD_AUXN

DDPB_AUX P

DDPC_AUXP

DDPD_AUXP

DDPB_HPD

DDPC_HPD

DDPD_HPD

PIRQE#/G PIO2

PIRQF#/GP IO3

PIRQG#/G PIO4

PIRQH#/GP IO5

PME#

PLTRST#

PCH_PLTRST#

RH215

RH215
100K_0402_5%~D

100K_0402_5%~D

@

@

1 2

12

RH196

RH196
100K_0402_5%~D

100K_0402_5%~D

1 2

DSWODVREN - ON DIE DSW VR ENABLE

HIGH = ENABLED (DEFAULT)
LOW = DISABLED

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/05/28 2013/05/27

2012/05/28 2013/05/27

2012/05/28 2013/05/27

A16 SWAP OVERRIDE STRAP

STP_A16OVR

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

LOW = A16 SWAP OVERRIDE
HIGH = DEFAULT

2

R40

PCH_DPB_HDMI_CLK

R39

PCH_DPB_HDMI_DAT

R35

PCH_DPC_MDP_CLK

R36

PCH_DPC_MDP_DAT

N40

PCH_DPD_CLK

N38

PCH_DPD_DAT

H45

K43

PCH_mDP_AUXN

J42

H43

K45

PCH_mDP_AUXP

J44

K40

PCH_HDMI_HPD

K38

PCH_mDP_HPD

H39

PCH_DMC_HPD

G17

BT_ON#

F17

DP_CBL_DET

L15

ODD_DA#

M15

FFS_INT1

AD10

Y11

PCH_PLTRST#

+3VS

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

5

1

P

B

O

2

A

G

TC7SH08FU_SSOP5~D

TC7SH08FU_SSOP5~D

3

PLTRST_VGA# 29, 30

1

PCH_DPB_HDMI_CLK 36

PCH_DPB_HDMI_DAT 36

PCH_DPC_MDP_CLK 31

PCH_DPC_MDP_DAT 31

PCH_DPD_CLK 39

PCH_DPD_DAT 39

PCH_mDP_AUXN 31

PCH_mDP_AUXP 31

PCH_HDMI_HPD 36

PCH_mDP_HPD 16,31

PCH_DMC_HPD 39

BT_ON# 51

DP_CBL_DET 31

ODD_DA# 50

FFS_INT1 49

T124 PAD~D@ T124 PAD~D@

CH144

CH144

1 2

@

@

4

PLT_RST

UH3

UH3

Title

Title

Title

ize Document Number Rev

Size Document Number Rev

Size Document Number Rev

S

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

+3VS

12

RH367

RH367
10K_0402_5%~D

10K_0402_5%~D

@

@

12

RH201

RH201
100K_0402_5%~D

100K_0402_5%~D

@

@

@

@

@

@

@

@

12

12

12

12

12

12

12

12

12

12

12

12

PCH_RSMRST#

PCH_HDMI_HPD

PCH_DMC_HPD

PM_CLKRUN#

BT_ON#

ODD_DA#

WL_OFF#

HDMI_IN_PWMSEL#

PCI_PIRQA#

PCI_PIRQB#

PCI_PIRQC#

PCI_PIRQD#

DGPU_HOLD_RST#

RH194 10K_0402_5%~DRH194 10K_0402_5%~D

RV462 100K_0402_5%~D

RV462 100K_0402_5%~D

RV461 100K_0402_5%~D

RV461 100K_0402_5%~D

1 2

RH351 10K_0402_5%~D

RH351 10K_0402_5%~D

Compal Electronics, Inc.

PCH (2/9) DMI,FDI,PM,DP,CRT

PCH (2/9) DMI,FDI,PM,DP,CRT

PCH (2/9) DMI,FDI,PM,DP,CRT

LA-9332P

LA-9332P

LA-9332P

1

HDMI

mDP

DMC

PLT_RST# 43,44,51,53, 6

+3VS

RH3668.2K_0402_5%~D RH3668.2K_0402_5%~D

RH3658.2K_0402_5%~D RH3658.2K_0402_5%~D

RH3628.2K_0402_5%~D RH3628.2K_0402_5%~D

RH3528.2K_0402_5%~D RH3528.2K_0402_5%~D

RH3248.2K_0402_5%~D RH3248.2K_0402_5%~D

RH3258.2K_0402_5%~D RH3258.2K_0402_5%~D

RH3268.2K_0402_5%~D RH3268.2K_0402_5%~D

RH3298.2K_0402_5%~D RH3298.2K_0402_5%~D

RH32710K_0402_5%~D

RH32710K_0402_5%~D

17 56Friday, December 14, 2012

17 56Friday, December 14, 2012

17 56Friday, December 14, 2012

0.1

0.1

0.1

5

4

3

2

1

D D

+3V_PCH

12

RH76

RH76
10K_0402_5%~D

10K_0402_5%~D

LPT_PCH_M_EDS

LPT_PCH_M_EDS

2 OF 11

2 OF 11

5

5

CLKOUT_PE G_A

CLKOUT_PE G_A_P

PEGA_CL KRQ#/GPIO47

CLKOUT_PE G_B

CLKOUT_PE G_B_P

PEGB_CL KRQ#/GPIO56

CLKOUT_DMI

CLKOUT_DMI_ P

CLKOUT_DP

CLKOUT_DP_ P

CLKOUT_DPNS

CLKOUT_DPNS _P

CLKIN_DMI

CLKIN_DMI_ P

CLKIN_GND

CLKIN_GND _P

CLKIN_DOT96 N
CLKIN_DOT96 P

CLKIN_SA TA

CLKIN_SA TA_P

REFCLK14 IN

CLKIN_33 MHZLOOPBACK

XTAL25_IN

XTAL25_O UT

CLKOUTFLEX 0/GPIO64

CLKOUTFLEX 1/GPIO65

CLKOUTFLEX 2/GPIO66

CLKOUTFLEX 3/GPIO67

ICLK_IREF

TP19
TP18

DIFFCLK_B IASREF

AB35

AB36

AF6

Y39

Y38

U4

AF39

CLK_CPU_DMI#

AF40

CLK_CPU_DMI

AJ40

CLK_CPU_SSC_DPLL#

AJ39

CLK_CPU_SSC_DPLL

AF35

CLK_CPU_DPLL#

AF36

CLK_CPU_DPLL

AY24

CLK_BUF_DMI#

AW24

CLK_BUF_DMI

AR24

CLK_BUF_BCLK#

AT24

CLK_BUF_BCLK

H33

CLK_BUF_DOT96#

G33

CLK_BUF_DOT96

BE6

CLK_BUF_CKSSCD#

BC6

CLK_BUF_CKSSCD

F45

CLK_PCH_14M

D17

CLK_PCI_LPBACK

AL44
AM43

C40

F38

DMC_PCH_DET#

F36

PCH_GPIO66

F39

CAM_DET#

AM45

ICLK_IREF

AD39
AD38

AN44

PCH_CLK_BIASREF

CLK_PEG_PCH#

CLK_PEG_PCH

PEG_CLKREQ_R#

MXM2_PEG_PCH#

MXM2_PEG_PCH

MXM2_CLKREQ_R#

XTAL25_IN
XTAL25_OUT

CAM_DET#
DMC_PCH_DET#
PCH_GPIO66

CLK_PEG_PCH# 29

CLK_PEG_PCH 29

MXM2_PEG_PCH# 30

MXM2_PEG_PCH 30

CLK_CPU_DMI# 6

CLK_CPU_DMI 6

CLK_CPU_SSC_DPLL# 6
CLK_CPU_SSC_DPLL 6

CLK_CPU_DPLL# 6
CLK_CPU_DPLL 6

T176PAD~D @T176PAD~D @

CAM_DET# 42

1 2

T149PAD~D @T149PAD~D @
T150PAD~D @T150PAD~D @

1 2

DMC_PCH_DET# 51

RH540_0402_1% @ RH540_0402_1% @

+1.5VS

+1.05V_+1.5V_RUN

RH2087.5K_0402_1%~D RH2087.5K_0402_1%~D

RPH2RPH2

1 8
2 7
3 6
4 5

+3VS

UH1C

@

@

RH307 0_0402_1%

+3V_PCH

+3VS

+3VS

+3V_PCH

+3V_PCH

+3V_PCH

+3V_PCH

+3V_PCH

RH307 0_0402_1%

RH308 0_0402_1%

RH308 0_0402_1%
RH142 10K_0402_5%~DR H142 10K_0402_5%~D

RH99 0_0402_1%

RH99 0_0402_1%
RH98 0_0402_1%@RH98 0_0402_1%@
RH145 10K_0402_5%~DRH145 10K_0402_5%~D

RH158 0_0402_1%@RH158 0_0402_1%@

RH147 0_0402_1%@RH147 0_0402_1%@

RH28 10K_0402_5%~DRH28 10K_0402_5%~D

RH129 0_0402_1%@RH129 0_0402_1%@
RH124 0_0402_1%@RH124 0_0402_1%@

MiniWLAN
(Mini Card 1)

DMC (Mini Card 2)

10/100/1G LAN

C C

Card Reader

CLK_PCIE_MINI1#51

CLK_PCIE_MINI151

MINI1CLK_REQ#51

CLK_PCIE_MINI2#51

CLK_PCIE_MINI251

MINI2CLK_REQ#51

CLK_PCIE_LAN#44

CLK_PCIE_LAN44

LANCLK_REQ#44

CLK_PCIE_CD#53

CLK_PCIE_CD53

CDCLK_REQ#53

Thunder Bolt

DGPU_PWROK29,31

CLK_CPU_ITP#6

CLK_CPU_ITP6

CLK_PCI_LPBACK CLK_PCI0

CLK_PCI_LPC43

CLK_DEBUG51

B B

CLK_PCI_LPC CLK_PCI1

12

@

@

12
12

@

@

12
12
12

12

12

1 2

12
12

RH126 10K_0402_5%~DR H126 10K_0402_5%~D

RH128 10K_0402_5%~D

RH128 10K_0402_5%~D

RH132 10K_0402_5%~D

RH132 10K_0402_5%~D

RH133 10K_0402_5%~D

RH133 10K_0402_5%~D

RH127 10K_0402_5%~DR H127 10K_0402_5%~D

RH280 0_0402_1%@RH280 0_0402_1%@

RH281 0_0402_1%@RH281 0_0402_1%@

RH169 22_0402_5%~DRH169 22_0402_5%~D

RH111 22_0402_5%~DRH111 22_0402_5%~D

RH151 22_0402_5%~DRH151 22_0402_5%~D

12

12

@

@

12

@

@

12

@

@

12

12

12

12

12

12

PCIE_MINI1#

PCIE_MINI1

MINI1CLK_REQ#

PCIE_MINI2#
PCIE_MINI2

MINI2CLK_REQ#

PCIE_LAN#

PCIE_LAN

LANCLK_REQ#

PCIE_EXP#
PCIE_EXP
EXPCLK_REQ#

CLK_BCLK_ITP#

CLK_BCLK_ITP

CLK_PCI2CLK_DEBUG

CLK_PCI3

T142 PAD~D@ T142 PAD~D@

CLK_PCI4

T138 PAD~D@ T138 PAD~D@

UH1C

Y43

CLKOUT_PCIE _N_0

Y45

CLKOUT_PCIE _P_0

AB1

PCIECLKRQ 0#/GPIO73

AA44

CLKOUT_PCIE _N_1

AA42

CLKOUT_PCIE _P_1

AF1

PCIECLKRQ 1#/GPIO18

AB43

CLKOUT_PCIE _N_2

AB45

CLKOUT_PCIE _P_2

AF3

PCIECLKRQ 2#/GPIO20/ SMI#

AD43

CLKOUT_PCIE _N_3

AD45

CLKOUT_PCIE _P_3

T3

PCIECLKRQ 3#/GPIO25

AF43

CLKOUT_PCIE _N_4

AF45

CLKOUT_PCIE _P_4

V3

PCIECLKRQ 4#/GPIO26

AE44

CLKOUT_PCIE _N5

AE42

CLKOUT_PCIE _P_5

AA2

PCIECLKRQ 5#/GPIO44

AB40

CLKOUT_PCIE _N_6

AB39

CLKOUT_PCIE _P_6

AE4

PCIECLKRQ 6#/GPIO45

AJ44

CLKOUT_PCIE _N_7

AJ42

CLKOUT_PCIE _P_7

Y3

PCIECLKRQ 7#/GPIO46

AH43

CLKOUT_ITPXD P

AH45

CLKOUT_ITPXD P_P

D44

CLKOUT_33 MHZ0

E44

CLKOUT_33 MHZ1

B42

CLKOUT_33 MHZ2

F41

CLKOUT_33 MHZ3

A40

CLKOUT_33 MHZ4

CLOCK SIGNAL

CLOCK SIGNAL

LYNXPOINT_BGA695

LYNXPOINT_BGA695

RH378

RH378

10K_0402_5%~D

10K_0402_5%~D

+3V_PCH

12

8.2P_0402_50V8D~D

8.2P_0402_50V8D~D

CH18

CH18

+3V_MXM

12

2

D

D

RH125

RH125
10K_0402_5%~D

10K_0402_5%~D

2

1

+3V_MXM

12

RH235

RH235

1K_0402_5%

1K_0402_5%

5

G

G

43

D

D

S

G

G

16

S

S

QH11A

QH11A
DMN66D0LDW-7

DMN66D0LDW-7

RH237 0_0402_5%@RH237 0_0402_5%@

10K_0402_5%~D

10K_0402_5%~D

RH309 0_0402_1%@RH309 0_0402_1%@

RH131 1M_0402_5%~DRH131 1M_0402_5%~D

25MHZ_10PF_Q22FA2380049900~D

25MHZ_10PF_Q22FA2380049900~D

3

4

QH11B

QH11B
DMN66D0LDW-7

DMN66D0LDW-7

1 2

+3V_MXM1

RH379

RH379

12

1 2

YH4

YH4

IN

OUT

GND

GND

CLK_BUF_DMI
CLK_BUF_DMI#
CLK_BUF_BCLK
CLK_BUF_BCLK#

CLK_BUF_DOT96#
CLK_BUF_DOT96

CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD

CLK_PCH_14M

S

12

2

G

G

D

D

1

2

PEG_CLKREQ# 29

12

RH236

RH236

@

@

10K_0402_5%~D

10K_0402_5%~D

+3V_MXM1

12

RH240

RH240

1K_0402_5%

1K_0402_5%

5

G

G

43

D

D

S

S

QH12B

QH12B
DMN66D0LDW-7

DMN66D0LDW-7

16

S

S

QH12A

QH12A
DMN66D0LDW-7

DMN66D0LDW-7

1 2

RH238 0_0402_5%@RH238 0_0402_5%@

XTAL25_IN_R

8.2P_0402_50V8D~D

8.2P_0402_50V8D~D

CH19

CH19

2

1

RPH1RPH1

1 8
2 7
3 6
4 5

1 2

RH143 10K_0402_5%~DRH143 10K_0402_5%~D

1 2

RH130 10K_0402_5%~DRH130 10K_0402_5%~D

1 2

RH146 10K_0402_5%~DRH146 10K_0402_5%~D

1 2

RH155 10K_0402_5%~DRH155 10K_0402_5%~D

1 2

RH205 10K_0402_5%~DRH205 10K_0402_5%~D

MXM2_CLKREQ# 30

12

RH239

RH239

@

@

10K_0402_5%~D

10K_0402_5%~D

CLOCK TERMINATION for FCIM and need close to PCH

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/05/28 2013/05/27

2012/05/28 2013/05/27

2012/05/28 2013/05/27

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Title

Title

Title

PCH (3/9) CLK

PCH (3/9) CLK

PCH (3/9) CLK

ize Document Number Rev

Size Document Number Rev

Size Document Number Rev

S

Custom

Custom

Custom

LA-9332P

LA-9332P

LA-9332P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

18 56Friday, December 14, 2012

18 56Friday, December 14, 2012

18 56Friday, December 14, 2012

0.1

0.1

0.1

5

4

3

+3VS

2

1

RH304

RH304

2.2K_0402_5%~D

2.2K_0402_5%~D

QH9A

QH9A

LPT_PCH_M_EDS

LPT_PCH_M_EDS

SPILPC

SPILPC

+3VS

12

SMBus

SMBus

C-Link

C-Link

Thermal

Thermal

12

RH310

RH310

2.2K_0402_5%~D

2.2K_0402_5%~D

PCH_SMBCLK 12,13,14,15,49,50,51,53,6

PCH_SMBDATA 12,13,14,15,49,50,51,53,6

SMBALERT#/GPIO11

SMBCLK

SMBDATA

SML0ALERT#/GPIO60

SML0CLK

SML0DATA

SML1ALERT#/PCHHOT#/GPIO74

SML1CLK/GPIO58

SML1DATA/GPIO75

CL_CLK

CL_DATA

CL_RST#

TD_IREF

TP1

TP2

TP4

TP3

N7

PCH_LID_SW_IN#

R10

MEM_SMBCLK

U11

MEM_SMBDATA

N8

DDR_HVREF_RST_PCH

U8

SML0CLK

R7

SML0DATA

H6

PCH_GPIO74

K6

SML1CLK

N11

SML1DATA

AF11

AF10

AF7

BA45

BC45

BE43

BE44

AY43

PCH_TD_IREF

1 2

RH322 8.2K_0402_1%RH322 8.2K_0402_1%

SML1CLK

SML1DATA

@

@

1 2

RH368 0_0402_1%

RH368 0_0402_1%

1 2

RH369 0_0402_5%~D

RH369 0_0402_5%~D

@

@

T130PA D~D @T130PAD~D @

T133PAD~D @T133PAD~D @

T131PA D~D @T131PAD~D @

T132PA D~D @T132PAD~D @

3

QH10B

QH10B

DMN66D0LDW-7

DMN66D0LDW-7

EC_LID_OUT# 43

LID_SW_IN# 43,45,47,48,53

+3VS

2

@

3

QH9B

QH9B

1 2

1 2

UH1D

UH1D

LAD_0

LAD_1

LAD_2

LAD_3

LFRAME#

LDRQ0#

LDRQ1#/GPIO23

SERIRQ

SPI_CLK

SPI_CS0#

SPI_CS1#

SPI_CS2#

SPI_MOSI

SPI_MISO

SPI_IO2

SPI_IO3

5

@

6 1

DMN66D0LDW-7_SOT363-6~D

DMN66D0LDW-7_SOT363-6~D

4

D D

+3VS

1 2

RH337 10K_0402_5%~DRH337 10K_0402_5%~D

C C

B B

SERIRQ

T169PAD~D@T169PAD~D

@

T168PA D~D@T168PA D~D

@

T167PAD~D@T167PAD~D

@

T166PA D~D@T166PA D~D

@

T165PA D~D@T165PA D~D

@

T164PAD~D@T164PAD~D

@

MEM_SMBCLK

@

MEM_SMBDATA

LPC_AD043,51

LPC_AD143,51

LPC_AD243,51

LPC_AD343,51

LPC_FRAME#43,51

SERIRQ43

LPC_AD0

LPC_AD1

LPC_AD2

LPC_AD3

LPC_FRAME#

SERIRQ

PCH_SPI_CLK

PCH_SPI_CS0#

PCH_SPI_SI

PCH_SPI_SO

PCH_SPI_DO2

PCH_SPI_DO3

@

DMN66D0LDW-7_SOT363-6~D

DMN66D0LDW-7_SOT363-6~D

RH380 0_0402_5%~DRH380 0_0402_5%~D

RH381 0_0402_5%~DRH381 0_0402_5%~D

A20

C20

A18

C18

B21

D21

G20

AL11

AJ11

AJ7

AL7

AJ10

AH1

AH3

AJ4

AJ2

6 1

5

4

QH10A

QH10A

2

DMN66D0LDW-7

DMN66D0LDW-7

EC_SMB_CK2 30,40,43,53,54

EC_SMB_DA2 30,40,43,53,54

MEM_SMBCLK

MEM_SMBDATA

DDR_HVREF_RST_PCH

PCH_GPIO74

SML1CLK

SML1DATA

SML0CLK

SML0DATA

@

@

@

@

1 2

1 2

+3V_PCH

12

RH3022.2K_0402_5%~D

RH3022.2K_0402_5%~D

12

RH3032.2K_0402_5%~D

RH3032.2K_0402_5%~D

12

RH3001K_0402_1%~D RH3001K_0402_1%~D

12

RH30110K_0402_5%~D R H30110K_0402_5%~D

RH2982.2K_0402_5%~D RH2982.2K_0402_5%~D

RH2992.2K_0402_5%~D RH2992.2K_0402_5%~D

+3V_PCH

12

RH3052.2K_0402_5%~D RH3052.2K_0402_5%~D

12

RH3062.2K_0402_5%~D RH3062.2K_0402_5%~D

VCC

/HOLD

CLK

3 OF 11 5

3 OF 11 5

+3V_PCH

8

7

6

PCH_SPI_CLK_RPCH_SPI_DO2_R

5

PCH_SPI_SI_R

DIO

CH56

CH56

1 2

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

RH374 15_0402_5%RH374 15_0402_5%

RH376 15_0402_5%RH376 15_0402_5%

RH377 15_0402_5%RH377 15_0402_5%

1515

1 2

1 2

1 2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

PCH_SPI_DO3PCH_SPI_DO3_R

PCH_SPI_CLK

PCH_SPI_SI

Compal Secret Data

Compal Secret Data

2012/05/28 2013/05/27

2012/05/28 2013/05/27

2012/05/28 2013/05/27

3

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

PCH_SPI_CLK

RH60

RH60

@

@

33_0402_5%~D

33_0402_5%~D

1 2

22P_0402_50V8J~D

22P_0402_50V8J~D

1

@

@

CH8

CH8

2

Reserve for EMI please
close to UH14

2

Title

Title

Title

PCH (4/9) SPI, SMBUS,LPC

PCH (4/9) SPI, SMBUS,LPC

PCH (4/9) SPI, SMBUS,LPC

S

ize Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-9332P

LA-9332P

LA-9332P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

19 56Friday, December 14, 2012

19 56Friday, December 14, 2012

19 56Friday, December 14, 2012

0.1

0.1

0.1

L

L

YNXPOINT_BGA695

YNXPOINT_BGA695

+3V_PCH

A A

1K

1 2

RH370 1K_0402_1%~DRH370 1K_0402_1%~D

RH371 1K_0402_1%~DRH371 1K_0402_1%~D

5

PCH_SPI_DO3_R

1 2

PCH_SPI_DO2_R

PCH_SPI_CS0# PCH_SPI_CS0#_R

PCH_SPI_SO PCH_SPI_SO_R

PCH_SPI_DO2

RH373 0_0402_5%~DRH373 0_0402_5%~D

RH372 15_0402_5%RH372 15_0402_5%

RH375 15_0402_5%RH375 15_0402_5%

1 2

1 2

1 2

+3V_PCH

1 2

3.3K_0402_5%

3.3K_0402_5%

@

@

RH58

RH58

200 MIL SO8

64Mb Flash ROM

UH14

UH14

1

/CS

2

DO

3

/WP

4

GND

EN25Q64-104HIP SOP8

EN25Q64-104HIP SOP8

4

5

D D

PCIE_PRX_GLANTX_N144

10/100/1G LAN

CARD READER

C C

MiniWLAN (Mini Card 1)

MiniDMC (Mini Card 2)

B B

PCIE_PRX_GLANTX_P144

PCIE_PTX_GLANRX_N144
PCIE_PTX_GLANRX_P144

PCIE_PRX_CARDTX_N453
PCIE_PRX_CARDTX_P453

PCIE_PTX_CARDRX_N453
PCIE_PTX_CARDRX_P453

PCIE_PRX_WLANTX_N551
PCIE_PRX_WLANTX_P551

PCIE_PTX_WLANRX_N551
PCIE_PTX_WLANRX_P551

PCIE_PRX_WANTX_N651
PCIE_PRX_WANTX_P651

PCIE_PTX_WANRX_N651
PCIE_PTX_WANRX_P651

1 2

CH149 0.1U_0402_25V6K~DCH149 0.1U_0402_25V6K~D

1 2

CH150 0.1U_0402_25V6K~DCH150 0.1U_0402_25V6K~D

1 2

CH153 0.1U_0402_25V6K~DCH153 0.1U_0402_25V6K~D

1 2

CH154 0.1U_0402_25V6K~DCH154 0.1U_0402_25V6K~D

PCIE_PRX_WLANTX_N5
PCIE_PRX_WLANTX_P5

PCIE_PTX_WLANRX_N5
PCIE_PTX_WLANRX_P5

PCIE_PRX_WANTX_N6
PCIE_PRX_WANTX_P6

PCIE_PTX_WANRX_N6
PCIE_PTX_WANRX_P6

+1.5VS

RH51 0_0402_1%

RH51 0_0402_1%

+1.5VS

RH210 7.5K_0402_1%~DRH210 7.5K_0402_1%~D

1 2

1 2

4

PCIE_PRX_GLANTX_N1
PCIE_PRX_GLANTX_P1

PCIE_PTX_GLANRX_N1_C
PCIE_PTX_GLANRX_P1_C

PCIE_PRX_CARDTX_N4
PCIE_PRX_CARDTX_P4

PCIE_PTX_CARDRX_N4_C
PCIE_PTX_CARDRX_P4_C

@

@

PCH_PCIE_IREF

T134 PAD~D@ T134 PAD~D@

T136 PAD~D@ T136 PAD~D@

PCH_PCIE_RCOMP

AW31

AW33

AW36

AW38

AY31

BE32
BC32

AT31
AR31

BD33
BB33

AY33

BE34
BC34

AT33
AR33

BE36
BC36

AV36

BD37
BB37

AY38

BC38
BE38

AT40
AT39

BE40
BC40

AN38
AN39

BD42
BD41

BE30

BC30

BB29

BD29

UH1I

UH1I

PERN1/USB 3RN3
PERP1/US B3RP3

PETN1/USB3 TN3
PETP1/USB 3TP3

PERN2/USB 3RN4
PERP2/US B3RP4

PETN2/USB3 TN4
PETP2/USB 3TP4

PERN_3
PERP_3

PETN_3
PETP_3

PERN_4
PERP_4

PETN_4
PETP_4

PERN_5
PERP_5

PETN_5
PETP_5

PERN_6
PERP_6

PETN_6
PETP_6

PERN_7
PERP_7

PETN_7
PETP_7

PERN_8
PERP_8

PETN_8
PETP_8

PCIE_IREF

TP11

TP6

PCIE_RCOM P

LYNXPOINT_BGA695

LYNXPOINT_BGA695

LPT_PCH_M_EDS

LPT_PCH_M_EDS

PCIe

PCIe

9 OF 11 5

9 OF 11 5

3

B37

USB2N0
USB2P0
USB2N1
USB2P1
USB2N2
USB2P2
USB2N3
USB2P3
USB2N4
USB2P4
USB2N5
USB2P5
USB2N6
USB2P6
USB2N7
USB2P7
USB2N8
USB2P8
USB2N9
USB2P9

USB2N10

USB2P10

USB2N11

USB2P11

USB2N12

USB2P12

USB

USB

USB2N13

USB2P13

USB3RN1
USB3RP1
USB3TN1

USB3TP1
USB3RN2
USB3RP2
USB3TN2

USB3TP2
USB3RN5
USB3RP5
USB3TN5

USB3TP5
USB3RN6
USB3RP6
USB3TN6

USB3TP6

USBRBIAS #

USBRBIAS

OC0#/GPI O59
OC1#/GPI O40
OC2#/GPI O41
OC3#/GPI O42
OC4#/GPI O43

OC5#/GPI O9
OC6#/GPI O10
OC7#/GPI O14

USB20_N0

D37

USB20_P0

A38

USB20_N1

C38

USB20_P1

A36

USB20_N2

C36

USB20_P2

A34

USB20_N3

C34

USB20_P3

B33

USB20_N4

D33

USB20_P4

F31

USB20_N5

G31

USB20_P5

K31

USB20_N6

L31

USB20_P6

G29
H29
A32
C32
A30
C30
B29
D29
A28
C28
G26

USB20_N12

F26

USB20_P12

F24

USB20_N13

G24

USB20_P13

AR26

USB3RN1

AP26

USB3RP1

BE24

USB3TN1

BD23

USB3TP1

AW26

USB3RN2

AV26

USB3RP2

BD25

USB3TN2

BC24

USB3TP2

AW29

USB3RN5

AV29

USB3RP5

BE26

USB3TN5

BC26

USB3TP5

AR29

USB3RN6

AP29

USB3RP6

BD27

USB3TN6

BE28

USB3TP6

K24

USBRBIAS

K26

M33

TP24

L33

TP23

P3

USB_OC0#

V1

USB_OC1#

U2

USB_OC2#

P1

USB_OC3#

M3

USB_OC4#

T1

USB_OC5#

N2

USB_OC6#

M1

USB_OC7#

USB20_N0 52
USB20_P0 52
USB20_N1 52
USB20_P1 52
USB20_N2 53
USB20_P2 53
USB20_N3 53
USB20_P3 53
USB20_N4 51
USB20_P4 51
USB20_N5 51
USB20_P5 51
USB20_N6 47
USB20_P6 47

USB20_N12 42
USB20_P12 42
USB20_N13 53
USB20_P13 53

USB3RN1 52
USB3RP1 52

USB3TN1 52

USB3TP1 52
USB3RN2 52
USB3RP2 52

USB3TN2 52

USB3TP2 52
USB3RN5 53
USB3RP5 53

USB3TN5 53

USB3TP5 53
USB3RN6 53
USB3RP6 53

USB3TN6 53

USB3TP6 53

T135PAD~D @T135PAD~D @
T137PAD~D @T137PAD~D @

USB_OC0# 52
USB_OC1# 52
USB_OC2# 53
USB_OC3# 53

JUSB1

JUSB2

JUSB3

JUSB4

Mini Card(WLAN)

Mini Card(DMC)

ELC LED

IR sensor

eDP Camera

LVDS Camera

VPK K/B

P1: JUSB1

P2: JUSB2

P5: JUSB3

P6: JUSB4

2

USBRBIAS

22.6_0402_1%~D

22.6_0402_1%~D

12

RH160

RH160

CAD NOTE:
Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15 mils.

1

+3V_PCH

USB_OC0#
USB_OC1#
USB_OC3#
USB_OC4#

USB_OC5#
USB_OC6#
USB_OC7#
USB_OC2#

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/05/28 2013/05/27

2012/05/28 2013/05/27

2012/05/28 2013/05/27

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

1 2

RH154 10K_0402_5%~DRH154 10K_0402_5%~D

1 2

RH159 10K_0402_5%~DRH159 10K_0402_5%~D

1 2

RH173 10K_0402_5%~DRH173 10K_0402_5%~D

1 2

RH180 10K_0402_5%~DRH180 10K_0402_5%~D

1 2

RH183 10K_0402_5%~DRH183 10K_0402_5%~D

1 2

RH188 10K_0402_5%~DRH188 10K_0402_5%~D

1 2

RH189 10K_0402_5%~DRH189 10K_0402_5%~D

1 2

RH190 10K_0402_5%~DRH190 10K_0402_5%~D

Compal Electronics, Inc.

Title

Title

Title

PCH (5/9) PCIE,USB

PCH (5/9) PCIE,USB

PCH (5/9) PCIE,USB

ize Document Number Rev

Size Document Number Rev

Size Document Number Rev

S

Custom

Custom

Custom

LA-9332P

LA-9332P

LA-9332P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

20 56Friday, December 14, 2012

20 56Friday, December 14, 2012

20 56Friday, December 14, 2012

0.1

0.1

0.1

5

4

3

2

1

D D

C C

B B

+3VS

1 2

RH270 10K_0402_5%~DR H270 10K_0402_5%~D

1 2

RH271 10K_0402_5%~DR H271 10K_0402_5%~D

1 2

RH164 10K_0402_5%~DR H164 10K_0402_5%~D

RH179 10K_0402_5%~DR H179 10K_0402_5%~D

1 2

RH267 10K_0402_5%~DR H267 10K_0402_5%~D

1 2

RH57 20K_0402_5%~DRH57 20K_0402_5%~D

1 2

RH256 10K_0402_5%~DR H256 10K_0402_5%~D

1 2

RH257 10K_0402_5%~DR H257 10K_0402_5%~D

1 2

RH258 10K_0402_5%~DR H258 10K_0402_5%~D

+3V_PCH

RH187 10K_0402_5%~DR H187 10K_0402_5%~D

1 2

RH354 1K_0402_1%~DRH354 1K_0402_1%~D

RH264 10K_0402_5%~DR H264 10K_0402_5%~D

RH269 10K_0402_5%~DRH269 10K_0402_5%~D

+3V_PCH

4.7K_0402_5%~D

4.7K_0402_5%~D

RH53

RH53

1 2

PCH_GPIO28

1K_0402_1%~D

1K_0402_1%~D

12

@RH353

@

RH353

PLL ON DIE VR ENABLE

ENABLED - HIGH(DEFAULT)
DISABLED - LOW

DMC_RADIO_OFF#

DGPU_EDIDSEL#

DGPU_HPD_INT#

12

STP_PCI#

VGA_PRSNT_R# EC_SCI#

VGA_PRSNT_L#

GPIO22

LVDS_CAB_DET#

EDP_CAB_DET#

12

HDD2_DETECT#

MXM2_PRSNT_R#

12

ODD_EN#

12

PCH_GPIO27

+3VS

RH272 10K_0402_5%~DRH272 10K_0402_5%~D

RH266 10K_0402_5%~DRH266 10K_0402_5%~D

RH265 10K_0402_5%~D@RH265 10K_0402_5%~D@

RH268 10K_0402_5%~D@RH268 10K_0402_5%~D@

1 2

DGPU_BKL_PWM_SEL#42

12

12

12

DMC_RADIO_OFF#51

DGPU_EDIDSEL#31,36,42

DGPU_HPD_INT#36,39

MXM2_PRSNT_R#30

MXM2_PCH_PWROK30

VGA_PRSNT_R#29

VGA_PRSNT_L#29

HDD2_DETECT#49

LVDS_CAB_DET#42

WiGi_RADIO_DIS#51

PCH_GPIO16

KB_DET#

PCH_GPIO16

KB_DET#

EC_SCI#43

EC_SMI#43

EDP_DETECT#41

PCH_GPIO2730

ODD_EN#50

ODD_DETECT#50

FFS_INT249,50

KB_DET#53

DMC_RADIO_OFF#

DGPU_EDIDSEL#

DGPU_HPD_INT#

EC_SMI#

MXM2_PRSNT_R#

PCH_GPIO16

GPIO22

PCH_GPIO27

PCH_GPIO28

STP_PCI#

ODD_EN#

ODD_DETECT#

PCH_GPIO37

VGA_PRSNT_R#

VGA_PRSNT_L#

FFS_INT2

KB_DET#

HDD2_DETECT#

DGPU_BKL_PWM_SEL#

EDP_CAB_DET#

LVDS_CAB_DET#

UH1F

UH1F

AT8

BMBUSY#/GP IO0

F13

TACH1/GPIO1

A14

TACH2/GPIO6

G15

TACH3/GPIO7

Y1

GPIO8

K13

LAN_PHY_P WR_CTRL/GPI O12

AB11

GPIO15

AN2

SATA4GP/G PIO16

C14

TACH0/GPIO1 7

BB4

SCLOCK/G PIO22

Y10

GPIO24

R11

GPIO27

AD11

GPIO28

AN6

GPIO34

AP1

GPIO35/N MI#

AT3

SATA2GP/G PIO36

AK1

SATA3GP/G PIO37

AT7

SLOAD/GP IO38

AM3

SDATAOUT0/GP IO39

AN4

SDATAOUT1/GP IO48

AK3

SATA5GP/G PIO49

U12

GPIO57

C16

TACH4/GPIO6 8

D13

TACH5/GPIO6 9

G13

TACH6/GPIO7 0

H15

TACH7/GPIO7 1

BE41

VSS

BE5

VSS

C45

VSS

A5

VSS

YNXPOINT_BGA695

YNXPOINT_BGA695

L

L

LPT_PCH_M_EDS

LPT_PCH_M_EDS

GPIO

GPIO

NCTF

NCTF

6 OF 11 5

6 OF 11 5

CPU/Misc

CPU/Misc

RCIN#

PROCPW RGD

THRMTRIP#

PLTRST_PROC#

GATEA20

KB_RST#

AN10

GATEA20

TP14

AY1

RH184

RH184

@

AT6

AV3

AV1

AU4

N10

A2
A41
A43
A44
B1
B2
B44
B45
BA1
BC1
BD1
BD2
BD44
BD45
BE2
BE3
D1
E1
E45
A4

@

KB_RST#

H_CPUPWRGD

PCH_THRMTRIP#_R

CPU_PLTRST#

PECI

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

12

0_0402_5%~D

0_0402_5%~D

GATEA20 43

H_PECI 43,6

KB_RST# 43

H_CPUPWRGD 6

CPU_PLTRST# 6

1 2

RH262390_0402_5% RH262390_0402_5%

H_THERMTRIP# 6

+3VS

12

RH16110K_0402_5%~D RH16110K_0402_5%~D

12

RH20310K_0402_5%~D RH20310K_0402_5%~D

Config

USB X4,PCIEX8,SATAX6

*

A A

5

GPIO16,49

11

01USB X6,PCIEX8,SATAX4

SATA2GP/GPIO36 , SATA3GP/GPIO37 SAMPLED AT RISING EDGE OF PWROK.
WEAK INTERNAL PULL-DOWN.(WEAK INTERNAL PULL-DOWN IS DISABLED AFTER
PLRST_N DE-ASSERTS).
NOTE: THIS SIGNAL SHOLD NOT BE PULLED HIGH WHEN STRAP IS SAMPLED.

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/05/28 2013/05/27

2012/05/28 2013/05/27

2012/05/28 2013/05/27

+3VS

RH171 200K_0402_5%

RH171 200K_0402_5%

Compal Secret Data

Compal Secret Data

Compal Secret Data

12

RH176 1K_0402_1%~DRH176 1K_0402_1%~D

1 2

@

@

12

@

@

RH174 10K_0402_5%~D

RH174 10K_0402_5%~D

12

RH181 10K_0402_5%~DR H181 10K_0402_5%~D

Deciphered Date

Deciphered Date

Deciphered Date

2

ODD_DETECT#

PCH_GPIO37

ODD_DETECT#

PCH_GPIO37

Compal Electronics, Inc.

Title

Title

Title

PCH (6/9) GPIO,MISC,NTFC

PCH (6/9) GPIO,MISC,NTFC

PCH (6/9) GPIO,MISC,NTFC

ize Document Number Rev

Size Document Number Rev

Size Document Number Rev

S

Custom

Custom

Custom

LA-9332P

LA-9332P

LA-9332P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

21 56Friday, December 14, 2012

21 56Friday, December 14, 2012

21 56Friday, December 14, 2012

0.1

0.1

0.1