COMPAL LA-9331P Schematics

A

B

C

D

E

MODEL NAME :

1 1

PCB NO :

BOM P/N :

LA-9331P

4619KL31L01

RANGER 17

Compal Confidential

2 2

RANGER 17

Schematic Document

Rev: X00

3 3

2012-06-22

@ : Nopop Component

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Cover Sheet

Size Document Number Rev

Custom

LA-9331P

D

Date: Sheet of

E

1 61Friday, June 22, 2012

0.1

A

B

C

D

E

eDP to LVDS

RTD2136

P.37

eDP deMux

PS8338

FFS

P.28

HDMI

Intel

Haswell

4-lane eDP

LNG3DMTR

P.46

Fan Control
EMC1412

P.51

CPU XDP
Conn.

P.7

P.30

LVDS Mux
PI3LVD1012

eDP MUX

PS8321

P.38

P.29

LVDS Conn.

eDP Conn.

1 1

P.39 P.39

P.30

LVDS Mux
PI3LVD1012

eDP MUX

PS8321

Processor

DP/HDMI

LVDS to DP SW
STDP4028

HDMI to LVDS SW

STDP6038

HDMI Redriver

HDMI 1.3 Input
HDMI 1.4a Output

2 2

Conn.

miniDP Conn.

Mini Card #1(Half)

WLAN/WiMax
BT4.0+LE/WiGig

DMC

P.32

DP Redriver

P.27

P.48

PS8330

HDMI Redriver

PS121

PS121

HDMI SW

TS3DV421

P.35

L

VDS Mux

PI3LVD1012

P.34

HDMI MUX

P.33 P.33

P.32

P.27

PS8271

HDMI MUX

.36

P

PS8271

P.31

P.36

Display MiniCard

P.48

3 3

RJ45 Conn.

USB3.0 Daughter Board

P.50

9 in 1 Conn.

Card Reader Board

LAN(GbE)
E2201 Killer

Card Reader

RTS5209

P.41

P.50

SPI ROM

RTC conn.

Power On/Off CKT.

4 4

DC/DC Interface CKT.

Power Circuit DC/DC

P.54, 55, 56, 57, 58, 59, 60, 61

P.52

53

P.

A

8MB

ENE KC3810

B

eDP

LVDS

HDMI

DP1.2

DP/HDMI

P.20

P.40

VPK MCU

VPK Daughter Board

MXM III
Conn.

P.26

USB2.0
PCI-E 2.0

USB2.0
PCI-E 2.0

PCI-E 2.0

PCI-E 2.0

Int.KBD

PEGx16

SPI

Gen 3

4

C 47W/57W

Scoket G3
rPGA-947

P.6, 7, 8, 9, 10, 11, 12

DMI x4

100MHz
5GT/s

Intel

Lynx Point

PCH

HM87

BGA 695 Balls

P.17, 18, 19, 20, 21, 22, 23, 24, 25

LPC Bus

ENE KB9012

ouch Pad

T

P.50

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

C

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

Memory Bus DDRIII

Dual Channel

1.35V DDRIII 1600 MHz

USB3.0
USB 2.0

USB3.0
USB 2.0

USB3.0
USB 2.0

USB3.0
USB 2.0

204pin DDRIII SO-DIMM x4

BANK 0, 1, 2, 3

USB3.0 Rediver

USB3.0 Rediver

USB3.0 Rediver

USB3.0 Rediver

P.49

PS8713

P.49

PS8713

PS8713

PS8713

USB3.0 Daughter Board

USB2.0

USB2.0

USB2.0

USB2.0

SATA 3.0

SATA 3.0

SATA 3.0

SATA Rediver

PS8520BT

SATA Rediver

PS8520BT

SATA Rediver

PS8520BT

P.46

P.47

P.47

HD Audio

P.40

Audio Codec
ALC3661

TI
TPA3113D2

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

D

P.13, 14, 15, 16

USB 3.0/USB 2.0 Conn.

( USB Charger Port )

USB 3.0/USB 2.0 Conn.

P.49

P.49

USB 3.0/USB 2.0 Conn.

USB 3.0/USB 2.0 Conn.

P.50

with eDP Panel

Digital Camera

Digital Camera

AlienFX/ELC

3D IR

HDD Conn. 1

HDD Conn. 2

HDD Conn. 3

In ODD Bay (In place of ODD)

ODD Conn.

Mini Card #3(Full)SATA 3.0
mSATA

Combo Jack

( iPhone & Nokia compatible)

Headphone Jack

Headphone Jack

P.42

P.43

Array Mics

Array Mics

Int. Speaker (2.5W*4)

Title

Size Document Number Rev

Custom

Date: Sheet of

P.30

54

P.

P.45,46

P.52

P.46

P.46

P.47

P.47

P.47

P.42

P.42

P.42

P.30

P.39

P.43

Block Diagram

LA-9331P

with LVDS Panel

Camera with eDP Panel

Camera with LVDS Panel

E

2 61Friday, June 22, 2012

0.1

A

B

C

D

E

Compal Confidential

Project Code : VAS00
File Name : LA-9331P

1 1

LS-9335P
POWER BUTTON/B

on/off SW

Led x 2

L

S-9336P

INDICATOR/B

Led-HDD

2 2

3 3

Led-Wireless

Led-CapsLock

To M/B

Hot Bar

FFC

6 pin

Lid

Tron Light

FFC

20 pin

LS-9337P
CardReader /B

Card Slot

KSI/KSO

30 pin

VPK Keyboard

40 pin

Backlight / 8 Pressure-sense Analog Signals

To USB30/B

FFC

30 pin

22 pin

HDD2 conn.

LS-9338P
VPK Daughter/B

VPK MCU MAX7313

FFC

16 pin

Touch Pad

4 pin

FFC

FFC

60 pin

PWM

Key Pad

22 pin

HDD1 conn.

Wire

12pin

6 pin
10 pin

Hot Key

Hot Bar

LS-9334P

LOGO /B

Led x 2

6pin

Hot Bar Hot Bar

LS-9333P LS-9331P LS-9332P

Alien head badge/B Alien Slits-L Light/BAlien Slits-R Light/B

Led x 2Led x 2 Led x 2

L R

Wire

6pin

LS-933BP
Tron L/B

Led x 1

4 4

Wire

10pin

To M/B

Wire

6pin

LS-933CP
Tron R/B

Led x 1

50pin
B To B conn.

WireWireWire

6pin6pin

44 pin

Coaxial/Wire Combo

20 pin

LF-XXXXP

FPC

50pin
B To B conn.

LA-9331P M/B

Camera

LCD Panel

HDD3ODD

HDD in ODD Bay Cable

RJ45

USB3.0

USB3.0

LS-9339P
USB30 /B

A

LS-933DP
Tron FL/B

Led x 1

LS-933EP
Tron FR/B

Led x 1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

E

3 61Friday, June 22, 2012

0.1

A

+1.35V

+1.05V

ON

OFF

OFF

Issued Date

USB 3.0 PORT

1

2

4

5

6

+5VS

+3VS

+1.5VS

+1.05VS

+0.675VS

+3VMXM

+5VMXM

+VCC_CORE

+1.35V_CPU_VDDQ

ONON

OFF

OFF

DESTINATION

D1

HD

HDD2

ODD

mSATA

MINI CARD-1 WLAN

MINI CARD-2 DMC

2012/06/22 2013/06/21

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

100K +/- 5%Ra

0
1
2
3
4
5
6
7 NC

Rb V min

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%

100K +/- 5%
200K +/- 5%

0 0 V

AD_BID

0.168 V

0.375 V 0.503 V

0.634 V

0.958 V

1.372 V

1.851 V

2.433 V

V typ

AD_BID

0 V 0.155 V

0.250 V

0.819 V

1.185 V

1.650 V

2.200 V

3.300 V

V

AD_BID

0.362 V

0.621 V

0.945 V

1.359 V

1.838 V

2.420 V

3.300 V

max

EC AD3

0x00-0x0C
0x0D-0x1C
0x1D-0x30
0x31-0x49
0x4A-0x69
0x6A-0x8E
0x8F-0xBB
0xBC-0xFF

POWER STATES

RUN

Signal

State

S0 (Full ON) / M0

S5 (SOFT OFF) / M-OFF

SLP
S3#

HIGH

LOW HIGH

LOW

SLP

SLP
S4#

HIGH ON

LOW LOW LOW LOW ON

S5#

HIGH

S4
STATE#

HIGHHIGH

HIGH LOW ONS3 (Suspend to RAM) / M-OFF

LOW

SLP
M#

HIGH

LOW ONLOW LOWS4 (Suspend to DISK) / M-OFF

ALWAYS
PLANE

SUS
PLANE

ON

OFF

Symbol Note :

: means Digital Ground

1 1

CLKOUT_PCIE0

CLKOUT_PCIE1

CLKOUT_PCIE2

CLK

CLKOUT_PCIE3

CLKOUT_PCIE4

CLKOUT_PCIE5

CLKOUT_PCIE6

CLKOUT_PCIE7

CLKOUT_PEG_A

SMBUS Control Table

SOURCE

EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK2
EC_SMB_DA2

PCH_SML0CLK PCH
PCH_SML0DATA

PCH_SML1CL K
PCH_SML1DA TA

MEM_SMBCLK
MEM_SMBDAT A

KB9012

KB9012

PCH

PCH

DMC

WLAN BATT DIMM

V

: means Analog Ground

DESTINATIONDIFFERENTIAL

MINI CARD-1 WLAN

MINI CARD-2 DMC

10/100/1G LAN

CARD READER

None

None

None

one

N

MXM

V

V

FLEX CLOCKS DESTINATION

CLKOUTFLEX0

CLKOUTFLEX1

CLKOUTFLEX2

CLKOUTFLEX3

Thermal

4028

Sensor

V

V

2136

FFS MXM

V

V

PLANE

ON ON

OFFOFF OFF

CLKOUT

PCI0

PCI1

PCI2

PCI3

PCI4

VPK MCU

VV

CLOCKS

OFFOFFON

OFFOFF

PCH_LOOPBACK

EC

80port debug card

None

None

BOARD ID Table

Board ID

0
1
2
3
4
5
6
7

PM TABLE

power
plane

State

S0 ON

S3

S5 S4/AC

S5 S4/AC don't exist

None

None

None

None

DESTINATION

XDP

Charger6038

TP mSATA

V

V

V

V V

PCB Revision

0.1 (SSI)

0.2 (PT)

0.3 (ST)

0.4 (QT)

1.0 (MP)

+5VALW

+3VALW

+3VLP

+3V_PCH

ON OFF

ON

OFF

SATAIII

SATA0

SATA1

SATA2

SATA3

SATA4/PCIE LANE1

SATA5/PCIE LANE2

Link

Security Classification

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

Connetion

JUSB1 (Left side)

JUSB2 (Left side)

NA3

NA

JUSB3 (Right side)

JUSB4 (Right side)

Compal Secret Data

Deciphered Date

USB2.0

PCI EXPRESS

Lane 1/USB3.0 Port 3

Lane 2/USB3.0 Port 4

Lane 3

Lane 4

Lane 5

Lane 6

Lane 7

Lane 8

USB PORT#0DESTINATION

JUSB1(USB3.0 P1)

JUSB2(USB3.0 P2)

1

JUSB3(USB3.0 P5)

2

JUSB4(USB3.0 P6)

3

JMINI1 (WLAN)

4

JMINI2 (DMC)

5

6

AlienFX/ELC

IR SENSOR

7

No

8

9

10

11

12

13

ne

None

None

e

DP CAMERA

LVDS CAMERA

PK K/B

V

DESTINATION

None

None

10/100/1G LAN

CARD READER

None

None

None

None

Compal Electronics, Inc.

Title

Notes List

Size Document Number Rev

Custom

LA-9331P

Date: Sheet of

4 61Friday, June 22, 2012

0.1

5

SMBUS Address [TBD]

R10

PCH

D D

U11

U8

R7

MEM_SMBCLK

MEM_SMBDATA

SML0CLK

SML0DATA

N11K6

SML1CLK

SML1DATA

+3VS

SCL2

SDA2

QH9B

EC_SMB_CK2

EC_SMB_DA2

2.2K

+3VS

2.2K

79

80

EC_SMB_CK2

EC_SMB_DA2

0 Ω

0 Ω

QH9A

C C

KBC

B B

KB9012

2.2K

2.2K

77

SCL1

SDA1

A A

EC_SMB_CK1

78 EC_SMB_DA1

EC_SMB_CK2_R

EC_SMB_DA2_R

0 Ω

0 Ω

+3VALW_EC

4

2K

2.

2.2K

2.2K

2.2K

2.2K

2.2K

+3VS

+3V_MXM

+3V_PCH

+3V_PCH

+3V_PCH

QV2B

CSCL

CSDA

QV2A

22 Ω

22 Ω

VPK_SMB_CK2

VPK_SMB_DA2

QV8

QV6

100 Ω

100 Ω

+3VS

0 Ω

0 Ω

0 Ω

0 Ω

0 Ω0 Ω

CLK_SMB

DAT_SMB

QH9A

H9B

Q

4.7K

4.7K

CIICSCL

CIICSDA

EC_HDMI_DAT_R

EC_HDMI_CLK_R

EC_HDMI_CLK

EC_HDMI_DAT

4.7K

4.7K

VGA_SMB_CK1

VGA_SMB_DA1

MXM_CURI2C_CLK

MXM_CURI2C_DATA

+DVCC33

4.7K

4.7K

+3V_MXM

3

2.2K

2.2K

111

RTD2136S

112

+3VS

LVDS transfer DP

B14

STDP4028

C13

HDMI IN

72

STDP6038

71

VPK

43

MSP430F5508

42

Thermal sensor

8

ADM1032

7

Thermal sensor

8

ADM1032

7

70

MXM1 CONN

68

MXM Current Monitor

5

HPA00900

6

4

5

BATT CONN

+3VS

PCH_SMBCLK

PCH_SMBDATA

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [0FFFFh to 0FF80h]

MXM FAN CONTROL

SMBUS Address [100_1100]

SYSTEM FAN CONTROL

SMBUS Address [100_1100]

SMBUS Address []

SMBUS Address []

SMBUS Address []

2

0 Ω

0 Ω

DDR_XDP_SMBCLK_R1

DDR_XDP_SMBDAT_R1

0 Ω

MINI2_SMBCLK

MINI2_SMBDATA

0 Ω

202

200

202

200

202

200

202

200

4

6

30

32

30

32

15

16

DIMM1

DIMM2

DIMM3

DIMM4

53

51

G sensor

LNG3DM

Touch pad

XDP

mSATA

DMC

1

SMBUS Address [A2]

SMBUS Address [A6]

SMBUS Address [A0]

SMBUS Address [A4]

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

0 Ω

0 Ω

PU700

5

4

SMBUS Address [000_1001]

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

2012/06/22 2013/06/21

3

Compal Secret Data

Deciphered Date

Custom

2

Compal Electronics, Inc.

Title

SMBus block diagram

Size Document Number Rev

LA-9331P

Date: Sheet of

1

5 61Friday, June 22, 2012

0.1

5

4

3

2

1

D D

Haswell rPGA EDS

JCPU1A

PEG_RCOMP

DMI_CRX_PTX_N0<17>
DMI_CRX_PTX_N1<17>
DMI_CRX_PTX_N2<17>
DMI_CRX_PTX_N3<17>

DMI_CRX_PTX_P0<17>
DMI_CRX_PTX_P1<17>
DMI_CRX_PTX_P2<17>
DMI_CRX_PTX_P3<17>

DMI_CTX_PRX_N0<17>
DMI_CTX_PRX_N1<17>
DMI_CTX_PRX_N2<17>

C C

FDI_CSYNC<17>
FDI_INT<17>

B B

DMI_CTX_PRX_N3<17>

DMI_CTX_PRX_P0<17>
DMI_CTX_PRX_P1<17>
DMI_CTX_PRX_P2<17>
DMI_CTX_PRX_P3<17>

RC3 0_0402_5%~D
RC87 0_0402_5%~D

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

12
12

FDI_CSYNC_R
FDI_INT_R

D21

DMI_RXN_0

C21

DMI_RXN_1

B21

DMI_RXN_2

A21

DMI_RXN_3

D20

DMI_RXP_0

C20

DMI_RXP_1

B20

DMI_RXP_2

A20

DMI_RXP_3

D18

DMI_TXN_0

C17

DMI_TXN_1

B17

DMI_TXN_2

A17

DMI_TXN_3

D17

DMI_TXP_0

C18

DMI_TXP_1

B18

DMI_TXP_2

A18

DMI_TXP_3

H29

FDI_CSYNC

J29

FDI_INT

IN

TEL_HASWELL_HAS WELL

CONN@

DMI FDI

1 OF 9

PEG_RXN_0
PEG_RXN_1
PEG_RXN_2
PEG_RXN_3
PEG_RXN_4
PEG_RXN_5
PEG_RXN_6

PEG

PEG_RXN_7
PEG_RXN_8

PEG_RXN_9
PEG_RXN_10
PEG_RXN_11
PEG_RXN_12
PEG_RXN_13
PEG_RXN_14
PEG_RXN_15

PEG_RXP_0
PEG_RXP_1
PEG_RXP_2
PEG_RXP_3
PEG_RXP_4
PEG_RXP_5
PEG_RXP_6
PEG_RXP_7
PEG_RXP_8

PEG_RXP_9
PEG_RXP_10
PEG_RXP_11
PEG_RXP_12
PEG_RXP_13
PEG_RXP_14
PEG_RXP_15

PEG_TXN_0

PEG_TXN_1

PEG_TXN_2

PEG_TXN_3

PEG_TXN_4

PEG_TXN_5

PEG_TXN_6

PEG_TXN_7

PEG_TXN_8

PEG_TXN_9

PEG_TXN_10
PEG_TXN_11
PEG_TXN_12
PEG_TXN_13
PEG_TXN_14
PEG_TXN_15

PEG_TXP_0

PEG_TXP_1

PEG_TXP_2

PEG_TXP_3

PEG_TXP_4

PEG_TXP_5

PEG_TXP_6

PEG_TXP_7

PEG_TXP_8

PEG_TXP_9

PEG_TXP_10
PEG_TXP_11
PEG_TXP_12
PEG_TXP_13
PEG_TXP_14
PEG_TXP_15

PEG_COMP

CAD Note:
Trace width=12 mils ,Spacing=15mil
Max length= 400 mils.

PEG_COMP

E23

PEG_GTX_C_HRX_N0

M29

PEG_GTX_C_HRX_N1

K28

PEG_GTX_C_HRX_N2

M31

PEG_GTX_C_HRX_N3

L30

PEG_GTX_C_HRX_N4

M33

PEG_GTX_C_HRX_N5

L32

PEG_GTX_C_HRX_N6

M35

PEG_GTX_C_HRX_N7

L34

PEG_GTX_C_HRX_N8

E29

PEG_GTX_C_HRX_N9

D28

PEG_GTX_C_HRX_N10

E31

PEG_GTX_C_HRX_N11

D30

PEG_GTX_C_HRX_N12

E35

PEG_GTX_C_HRX_N13

D34

PEG_GTX_C_HRX_N14

E33

PEG_GTX_C_HRX_N15

E32

PEG_GTX_C_HRX_P0

L29

PEG_GTX_C_HRX_P1

L28

PEG_GTX_C_HRX_P2

L31

PEG_GTX_C_HRX_P3

K30

PEG_GTX_C_HRX_P4

L33

PEG_GTX_C_HRX_P5

K32

PEG_GTX_C_HRX_P6

L35

PEG_GTX_C_HRX_P7

K34

PEG_GTX_C_HRX_P8

F29

PEG_GTX_C_HRX_P9

E28

PEG_GTX_C_HRX_P10

F31

PEG_GTX_C_HRX_P11

E30

PEG_GTX_C_HRX_P12

F35

PEG_GTX_C_HRX_P13

E34

PEG_GTX_C_HRX_P14

F33

PEG_GTX_C_HRX_P15

D32

PEG_HTX_GRX_N0

H35

PEG_HTX_GRX_N1

H34

PEG_HTX_GRX_N2

J33

PEG_HTX_GRX_N3

H32

PEG_HTX_GRX_N4

J31

PEG_HTX_GRX_N5

G30

PEG_HTX_GRX_N6

C33

PEG_HTX_GRX_N7

B32

PEG_HTX_GRX_N8

B31

PEG_HTX_GRX_N9

A30

PEG_HTX_GRX_N10

B29

PEG_HTX_GRX_N11

A28

PEG_HTX_GRX_N12

B27

PEG_HTX_GRX_N13

A26

PEG_HTX_GRX_N14

B25

PEG_HTX_GRX_N15

A24

PEG_HTX_GRX_P0

J35

PEG_HTX_GRX_P1

G34

PEG_HTX_GRX_P2

H33

PEG_HTX_GRX_P3

G32

PEG_HTX_GRX_P4

H31

PEG_HTX_GRX_P5

H30

PEG_HTX_GRX_P6

B33

PEG_HTX_GRX_P7

A32

PEG_HTX_GRX_P8

C31

PEG_HTX_GRX_P9

B30

PEG_HTX_GRX_P10

C29

PEG_HTX_GRX_P11

B28

PEG_HTX_GRX_P12

C27

PEG_HTX_GRX_P13

B26

PEG_HTX_GRX_P14

C25

PEG_HTX_GRX_P15

B24

Near MXM Connector

+VCOMP_OUT

12

RC224.9_0402_1%~D

CC1 0.22U_0402_16V7K~D

1 2

CC2 0.22U_0402_16V7K~D

1 2

CC3 0.22U_0402_16V7K~D

1 2

CC4 0.22U_0402_16V7K~D

1 2

CC5 0.22U_0402_16V7K~D

1 2

CC13 0.22U_0402_16V7K~D

1 2

CC6 0.22U_0402_16V7K~D

1 2

CC7 0.22U_0402_16V7K~D

1 2

CC8 0.22U_0402_16V7K~D

1 2

CC9 0.22U_0402_16V7K~D

1 2

CC10 0.22U_0402_16V7K~D

1 2

CC11 0.22U_0402_16V7K~D

1 2

CC12 0.22U_0402_16V7K~D

1 2

CC14 0.22U_0402_16V7K~D

1 2

CC15 0.22U_0402_16V7K~D

1 2

CC16 0.22U_0402_16V7K~D

1 2

CC17 0.22U_0402_16V7K~D

1 2

CC18 0.22U_0402_16V7K~D

1 2

CC19 0.22U_0402_16V7K~D

1 2

CC20 0.22U_0402_16V7K~D

1 2

CC21 0.22U_0402_16V7K~D

1 2

CC22 0.22U_0402_16V7K~D

1 2

CC23 0.22U_0402_16V7K~D

1 2

CC24 0.22U_0402_16V7K~D

1 2

CC25 0.22U_0402_16V7K~D

1 2

CC26 0.22U_0402_16V7K~D

1 2

CC27 0.22U_0402_16V7K~D

1 2

CC28 0.22U_0402_16V7K~D

1 2

CC29 0.22U_0402_16V7K~D

1 2

CC30 0.22U_0402_16V7K~D

1 2

CC31 0.22U_0402_16V7K~D

1 2

CC32 0.22U_0402_16V7K~D

1 2

CC33 0.22U_0402_16V7K~D

1 2

CC34 0.22U_0402_16V7K~D

1 2

CC35 0.22U_0402_16V7K~D

1 2

CC36 0.22U_0402_16V7K~D

1 2

CC37 0.22U_0402_16V7K~D

1 2

CC38 0.22U_0402_16V7K~D

1 2

CC39 0.22U_0402_16V7K~D

1 2

CC40 0.22U_0402_16V7K~D

1 2

CC41 0.22U_0402_16V7K~D

1 2

CC42 0.22U_0402_16V7K~D

1 2

CC43 0.22U_0402_16V7K~D

1 2

CC44 0.22U_0402_16V7K~D

1 2

CC45 0.22U_0402_16V7K~D

1 2

CC46 0.22U_0402_16V7K~D

1 2

CC47 0.22U_0402_16V7K~D

1 2

CC48 0.22U_0402_16V7K~D

1 2

CC49 0.22U_0402_16V7K~D

1 2

CC50 0.22U_0402_16V7K~D

1 2

CC51 0.22U_0402_16V7K~D

1 2

CC52 0.22U_0402_16V7K~D

1 2

CC53 0.22U_0402_16V7K~D

1 2

CC54 0.22U_0402_16V7K~D

1 2

CC55 0.22U_0402_16V7K~D

1 2

CC56 0.22U_0402_16V7K~D

1 2

CC57 0.22U_0402_16V7K~D

1 2

CC58 0.22U_0402_16V7K~D

1 2

CC59 0.22U_0402_16V7K~D

1 2

CC60 0.22U_0402_16V7K~D

1 2

CC61 0.22U_0402_16V7K~D

1 2

CC62 0.22U_0402_16V7K~D

1 2

CC63 0.22U_0402_16V7K~D

1 2

CC64 0.22U_0402_16V7K~D

1 2

PEG_GTX_HRX_N0
PEG_GTX_HRX_N1
PEG_GTX_HRX_N2
PEG_GTX_HRX_N3
PEG_GTX_HRX_N4
PEG_GTX_HRX_N5
PEG_GTX_HRX_N6
PEG_GTX_HRX_N7
PEG_GTX_HRX_N8

PEG_GTX_HRX_N9
PEG_GTX_HRX_N10
PEG_GTX_HRX_N11
PEG_GTX_HRX_N12
PEG_GTX_HRX_N13
PEG_GTX_HRX_N14
PEG_GTX_HRX_N15

PEG_GTX_HRX_P0

PEG_GTX_HRX_P1

PEG_GTX_HRX_P2

PEG_GTX_HRX_P3

PEG_GTX_HRX_P4

PEG_GTX_HRX_P5

PEG_GTX_HRX_P6

PEG_GTX_HRX_P7

PEG_GTX_HRX_P8

PEG_GTX_HRX_P9

PEG_GTX_HRX_P10

PEG_GTX_HRX_P11

PEG_GTX_HRX_P12

PEG_GTX_HRX_P13

PEG_GTX_HRX_P14

PEG_GTX_HRX_P15

PEG_HTX_C_GRX_N0

PEG_HTX_C_GRX_N1

PEG_HTX_C_GRX_N2

PEG_HTX_C_GRX_N3

PEG_HTX_C_GRX_N4

PEG_HTX_C_GRX_N5

PEG_HTX_C_GRX_N6

PEG_HTX_C_GRX_N7

PEG_HTX_C_GRX_N8

PEG_HTX_C_GRX_N9
PEG_HTX_C_GRX_N10
PEG_HTX_C_GRX_N11
PEG_HTX_C_GRX_N12
PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_N14
PEG_HTX_C_GRX_N15

PEG_HTX_C_GRX_P0

PEG_HTX_C_GRX_P1

PEG_HTX_C_GRX_P2

PEG_HTX_C_GRX_P3

PEG_HTX_C_GRX_P4

PEG_HTX_C_GRX_P5

PEG_HTX_C_GRX_P6

PEG_HTX_C_GRX_P7

PEG_HTX_C_GRX_P8

PEG_HTX_C_GRX_P9
PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_P11
PEG_HTX_C_GRX_P12
PEG_HTX_C_GRX_P13
PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_P15

PEG_GTX_HRX_P[0..15] <29>
PEG_GTX_HRX_N[0..15] <29>

PEG_HTX_C_GRX_P[0..15] <29>
PEG_HTX_C_GRX_N[0..15] <29>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

CPU (1/7) DMI,PEG

ze Document Number Rev

Si

Custom

LA-9331P

2

Date: Sheet of

1

6 61Friday, June 22, 2012

0.1

5

4

3

2

1

SM_DRAMPWROK with DDR Power Gating Topology

+3V_PCH

100K_0402_5%~D

+3V_PCH

CLK_CPU_SSC_DPLL#<18>

CLK_CPU_SSC_DPLL<18>

UC1

NC
A
GND3Y

12

H_THERMTRIP#

H_CATERR#

H_PROCHOT#

H_PROCHOT#<43,63>

H_THERMTRIP#<21>

H_PM_SYNC<17>

H_CPUPWRGD<21>

CLK_CPU_DPLL#<18>

CLK_CPU_DPLL<18>

CLK_CPU_DMI#<18>

CLK_CPU_DMI<18>

RC2010K_0402_5%~D @

RC2110K_0402_5%~D @

VCC

12

+VCCIO_OUT

+3VS

5

PCH_PLTRST#_BUF

4

@

RC89

RUN_ON_CPU1.5VS3#<10,56>

1

2

CC156

1 2

0.1U_0402_25V6K~D

5

1

P

B

4

O

2

A

G

UC2

74AHC1G09GW_TSSOP5~D

3

12

RC94 0_0402_5%~D

@

RC57 56_0402_5%~D

1 2

RC134 0_0402_5%~D

1 2

place RC134 near CPU

1 2

RC25 0_0402_5%~D

RC51 0_0402_5%~D
RC52 0_0402_5%~D
RC43 0_0402_5%~D
RC22 0_0402_5%~D
RC15 0_0402_5%~D
RC13 0_0402_5%~D

0.1U_0402_25V6K~D

+1.05VS

1K_0402_1%~D

12

CC140

20K_0402_5%~D

12

12
12
12
12
12
12

RC17

RC10 43_0402_5%~D

RC11

D D

SYS_PWROK<17>

PM_DRAM_PWRGD<17>

C C

B B

SSC CLOCK TERMINATION, IF NOT USED, stuff RC20,RC21

RC88 0_0402_5%~D

+3V_PCH

RC18 200_0402_1%~D

+VCCIO_OUT

1 2

RC136 56_0402_5%~D@

1 2

RC128 49.9_0402_1%~D@

1 2

RC44 62_0402_5%~D

CPU_SSC_DPLL

CPU_SSC_DPLL#

1 2

1 2

1 2

Buffered reset to CPU

1

PLT_RST#<17,43,44,51,53>

2

SN74LVC1G07DCKR_SC70-5~D

RUNPWROK_AND

2

H_PECI<21,43>

1 2

CPU_PLTRST#< 21>

+1.35V_CPU_VDDQ

39_0402_5%~D

@

RC64

SSM3K7002FU_SC70-3~D

1 2

13

D

@

QC1

G

S

H_CATERR#
H_PECI

T66PAD~D @

H_PROCHOT#_R
H_THERMTRIP#_R

H_PM_SYNC
VCCPWRGOOD_0_R
PM_DRAM_PWRGD_CPU
CPU_PLTRST#_R

CPU_DPLL#
CPU_DPLL
CPU_SSC_DPLL#
CPU_SSC_DPLL
CPU_DMI#
CPU_DMI

1.8K_0402_1%

12

RC16

12

RC28 0_0402_5%~D

3.3K_0402_1%~D

12

RC14

AP32

SKTOCC

AN32

CATERR

AR27

PECI

AK31

RSVD

AM30

PROCHOT

AM35

THERMTRIP

AT28

PM_SYNC

AL34

PWRGOO D

AC10

SM_DRAMPW ROK

AT26

PLTRSTIN

G28

DPLL_REF _CLKN

H28

DPLL_REF _CLKP

F27

SSC_DPLL _REF_CLKN

E27

SSC_DPLL _REF_CLKP

D26

BCLKN

E26

BCLKP

CONN@

RC54 0_0402_5%~D@

12

RC53 0_0402_5%~D

12

PM_DRAM_PWRGD_CPU

Haswell rPGA EDS

JCPU1B

MISC

THERMAL

PWR

INTEL_HASWELL_HASWELL

CPU_PLTRST#_R

SM_RCOMP_ 0
SM_RCOMP_ 1
SM_RCOMP_ 2

DDR3

SM_DRAMRST

PRDY

PREQ

TCK
TMS

TRST

JTAG

TDI
TDO
DBR

BPM_N_0
BPM_N_1

CLOCK

BPM_N_2
BPM_N_3
BPM_N_4
BPM_N_5
BPM_N_6
BPM_N_7

2 OF 9

CAD Note:

Avoid stub in the PWRGD path

while placing resistors RC25 & RC130

+3V_PCH

1 2

RC125 1K_0402_1%~D@

PBTN_OUT#<17,43>

CPU_PWR_DEBUG<10>

PCH_SMBDATA<12,13,14,15,19,49,50,51,53>

PCH_SMBCLK<12,13,14,15,19,49,50,51,53>

SM_RCOMP0

AP3

SM_RCOMP1

AR3

SM_RCOMP2

AP2

DDR3_DRAMRST#_CPU

AN3

XDP_PRDY#

AR29

XDP_PREQ#

AT29

XDP_TCLK

AM34

XDP_TMS

AN33

XDP_TRST#

AM33

XDP_TDI_R

AM31

XDP_TDO_R

AL33

XDP_DBRESET#_R

AP33

XDP_OBS0_R

AR30

XDP_OBS1_R

AN31

XDP_OBS2_R

AN29

XDP_OBS3_R

AP31

XDP_OBS4_R

AP30

XDP_OBS5_R

AN28

XDP_OBS6_R

AP29

XDP_OBS7_R

AP28

For ESD concern, please put near CPU

VCCPWRGOOD_0_R

+VCCIO_OUT

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

1

1

CC65

CC66

2

2

Place near JXDP1

SYS_PWROK_XDP

RC5 need to close to JCPU1

H_CPUPWRGD H_CPUPWRGD_XDP

RC5 1K_0402_1%~D

1 2

RC6 0_0402_5%~D

1 2

RC8 0_0402_5%~D

1 2

RC12 0_0402_5%~D

IMVP_PWRGD<17,43,62>

RC50 0_0402_5%~D
RC36 0_0402_5%~D
RC46 0_0402_5%~D
RC47 0_0402_5%~D
RC48 0_0402_5%~D
RC23 0_0402_5%~D
RC24 0_0402_5%~D
RC26 0_0402_5%~D

RC30 0_0402_5%~D
RC31 0_0402_5%~D
RC33 0_0402_5%~D
RC34 0_0402_5%~D
RC37 0_0402_5%~D
RC40 0_0402_5%~D
RC38 0_0402_5%~D
RC39 0_0402_5%~D

10K_0402_5%~D

12

RC135

1 2

RC126 0_0402_5%~D

1 2

RC127 0_0402_5%~D

1 2

DDR3_DRAMRST#_CPU <12>

1 2
1 2
1 2
1 2
1 2
1 2
1 2

12

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

CRB Rev 0.7 is depop

CFG0<9>
CFG1<9>

CFG2<9>
CFG3<9>

CFG4<9>
CFG5<9>

CFG6<9>
CFG7<9>

XDP_PRDY#_R
XDP_PREQ#_R
XDP_TCLK_R
XDP_TMS_R
XDP_TRST#_R
XDP_TDI
XDP_TDO
XDP_DBRESET#

XDP_OBS0
XDP_OBS1

DDR3 COMPENSATION SIGNALS

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil

+VCCIO_OUT +VCCIO_OUT

XDP_PREQ#_R
XDP_PRDY#_R

CFG0
CFG1

CFG2
CFG3

XDP_OBS0
XDP_OBS1

CFG4
CFG5

CFG6
CFG7

CFD_PWRBTN#_XDP

SYS_PWROK_XDP

DDR_XDP_SMBDAT_R1
DDR_XDP_SMBCLK_R1

XDP_TCLK_R

XDP_DBRESET# <17>

RC45 100_0402_1%~D

1 2

RC55 75_0402_1%~D

1 2

RC49 100_0402_1%~D

1 2

JXDP1

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A 0

11

OBSDATA_A 1

13

GND4

15

OBSDATA_A 2

17

OBSDATA_A 3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B 0

29

OBSDATA_B 1

31

GND10

33

OBSDATA_B 2

35

OBSDATA_B 3

37

GND12

39

PWRGOO D/HOOK0

41

HOOK1

43

VCC_OBS_ AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01-L-D-A

GND1
OBSFN_C0
OBSFN_C1

GND3

OBSDATA_C0
OBSDATA_C1

GND5

OBSDATA_C2
OBSDATA_C3

GND7
OBSFN_D0
OBSFN_D1

GND9

OBSDATA_D0
OBSDATA_D1

GND11
OBSDATA_D2
OBSDATA_D3

GND13

ITPCLK/HOOK 4

ITPCLK#/HO OK5

VCC_OBS_ CD

RESET#/HOO K6

DBR#/HOOK 7

GND15

TD0

TRST#

TDI

TMS

GND17

CONN@

CRB Rev 0.7 no pull up

2

CFG17

4

CFG16

6
8

CFG8

10

CFG9

12
14

CFG10

16

CFG11

18
20

CFG19

22

CFG18

24
26

CFG12

28

CFG13

30
32

CFG14

34

CFG15

36
38

CLK_XDP

40

CLK_XDP#

42
44

XDP_RST#_RCPU_PWR_DEBUG_R

46

XDP_DBRESET#

48
50

XDP_TDO

52

XDP_TRST#_R

54

XDP_TDI

56

XDP_TMS_R

58
60

PU/PD for JTAG signals

XDP_DBRESET#_R

XDP_TMS

XDP_TDI_R

XDP_PREQ#

XDP_TDO_R

XDP_TCLK

XDP_TRST#

CFG17 <9>
CFG16 <9>

CFG8 <9>
CFG9 <9>

CFG10 <9>
CFG11 <9>

CFG19 <9>
CFG18 <9>

CFG12 <9>
CFG13 <9>

CFG14 <9>
CFG15 <9>

RC144 0_0402_5%~D

1 2

RC145 0_0402_5%~D

1 2

CPU_PLTRST#_R

12

RC9 1K_0402_1%~D

RC19 1K_0402_1%~D

12

RC27 51_0402_1%~D@

12

RC29 51_0402_1%~D

12

RC32 51_0402_1%~D@

12

RC35 51_0402_1%~D

12

RC42 51_0402_1%~D

12

RC41 51_0402_1%~D

12

+1.05VS

+3VS

CLK_CPU_ITP <18>
CLK_CPU_ITP# <18>

CAD Note:
PLACE PULL-UP RESISTOR WITHIN 2 INCH OF THE CPU

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU (2/7) PM,XDP,CLK

ze Document Number Rev

Si

Custom

LA-9331P

Date: Sheet of

1

7 61Friday, June 22, 2012

0.1

5

4

3

2

1

D D

C C

B B

A A

DDR_A_D[0..63]<12,14>

+V_SM_VREF

+DIMM0_1_VREF

+DIMM0_1_CA

+DIMM0_1_CA +DIMM0_1_VREF

1 2

1

CC137

0.022U_0402_25V7K~D

24.9_0402_1%

RC150

2

12

5

RC147

0_0402_5%

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

+1.35V

1K_0402_1%~D

12

1K_0402_1%~D

12

AR15

AT14
AM14
AN14

AT15
AR14
AN15
AM15

AM9
AN9
AM8
AN8
AR9

AT9

AR8

AT8
AJ9

AK9

AJ6

AK6
AJ10
AK10

AJ7

AK7

AF4
AF5
AF1

AF2
AG4
AG5
AG1
AG2

J1
J2
J5
H5
H2
H1
J4
H4
F2
F1
D2
D3
D1
F3
C3
B3
B5
E6
A5
D6
D5
E5
B6

A6
E12
D12
B11
A11
E11
D11
B12
A12

AM3

F16
F13

RC96

+DIMM0_1_CA_CPU

RC82

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
SM_VREF
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

CONN@

JCPU1C

3 OF 9

Haswell rPGA EDS

RSVD_AC7
SA_CK_N_0
SA_CK_P_0

SA_CKE_0
SA_CK_N_1
SA_CK_P_1

SA_CKE_1
SA_CK_N_2
SA_CK_P_2

SA_CKE_2
SA_CK_N_3
SA_CK_P_3

SA_CKE_3

SA_CS_N_0
SA_CS_N_1
SA_CS_N_2
SA_CS_N_3

SA_ODT_0

SA_ODT_1

SA_ODT_2

SA_ODT_3

SA_BS_0
SA_BS_1
SA_BS_2

RSVD_V10

SA_RAS

SA_WE

SA_CAS

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_MA_15

SA_DQS_N_0
SA_DQS_N_1
SA_DQS_N_2
SA_DQS_N_3
SA_DQS_N_4
SA_DQS_N_5
SA_DQS_N_6
SA_DQS_N_7
SA_DQS_P_0
SA_DQS_P_1
SA_DQS_P_2
SA_DQS_P_3
SA_DQS_P_4
SA_DQS_P_5
SA_DQS_P_6
SA_DQS_P_7

TEL_HASWELL_HAS WELL

IN

CC138

0.022U_0402_25V7K~D

RC151

24.9_0402_1%

4

Haswell rPGA EDS

SB_CKN0

SB_CK0

SB_CKE_0

SB_CKN1

SB_CK1

SB_CKE_1

SB_CKN2

SB_CK2

SB_CKE_2

SB_CKN3

SB_CK3

SB_CKE_3

SB_CS_N_0
SB_CS_N_1
SB_CS_N_2
SB_CS_N_3

SB_ODT_0
SB_ODT_1
SB_ODT_2
SB_ODT_3

SB_BS_0
SB_BS_1
SB_BS_2

SB_RAS

SB_CAS

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_MA_15

SB_DQS_N_0
SB_DQS_N_1
SB_DQS_N_2
SB_DQS_N_3
SB_DQS_N_4
SB_DQS_N_5
SB_DQS_N_6
SB_DQS_N_7
SB_DQS_P_0
SB_DQS_P_1
SB_DQS_P_2
SB_DQS_P_3
SB_DQS_P_4
SB_DQS_P_5
SB_DQS_P_6
SB_DQS_P_7

TEL_HASWELL_HAS WELL

2

RSVD

RSVD

SB_WE

AG8
Y4
AA4
AF10
Y3
AA3
AG10
Y2
AA2
AG9
Y1
AA1
AF9

P4
R2
P3
P1

R4
R3
R1
P2
R7
P8
AA9

R10
R6
P6
P7

R8
Y5
Y10
AA5
Y7
AA6
Y6
AA7
Y8
AA10
R9
Y9
AF7
P9
AA8
AG7

AP18
AP11
AP5
AJ3
L3
H9
C8
C14
AP17
AP12
AP6
AK3
M3
H8
C9
C15

4 OF 9

JCPU1D

I

N

0.022U_0402_25V7K~D

Issued Date

3

DDR_B_D[0..63]<13,15>

+V_SM_VREF

CC139

RC149

24.9_0402_1%

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

RC146

1 2

0_0402_5%

1

2

12

2012/06/22 2013/06/21

AR18

SB_DQ_0

AT18

SB_DQ_1

AM17

SB_DQ_2

AM18

SB_DQ_3

AR17

SB_DQ_4

AT17

SB_DQ_5

AN17

SB_DQ_6

AN18

SB_DQ_7

AT12

SB_DQ_8

AR12

SB_DQ_9

AN12

SB_DQ_10

AM11

SB_DQ_11

AT11

SB_DQ_12

AR11

SB_DQ_13

AM12

SB_DQ_14

AN11

SB_DQ_15

AR5

SB_DQ_16

AR6

SB_DQ_17

AM5

SB_DQ_18

AM6

SB_DQ_19

AT5

SB_DQ_20

AT6

SB_DQ_21

AN5

SB_DQ_22

AN6

SB_DQ_23

AJ4

SB_DQ_24

AK4

SB_DQ_25

AJ1

SB_DQ_26

AJ2

SB_DQ_27

AM1

SB_DQ_28

AN1

SB_DQ_29

AK2

SB_DQ_30

AK1

SB_DQ_31

L2

SB_DQ_32

M2

SB_DQ_33

L4

SB_DQ_34

M4

SB_DQ_35

L1

SB_DQ_36

M1

SB_DQ_37

L5

SB_DQ_38

M5

SB_DQ_39

G7

SB_DQ_40

J8

SB_DQ_41

G8

SB_DQ_42

G9

SB_DQ_43

J7

SB_DQ_44

J9

SB_DQ_45

G10

SB_DQ_46

J10

SB_DQ_47

A8

SB_DQ_48

B8

SB_DQ_49

A9

SB_DQ_50

B9

SB_DQ_51

D8

SB_DQ_52

E8

SB_DQ_53

D9

SB_DQ_54

E9

SB_DQ_55

E15

SB_DQ_56

D15

SB_DQ_57

A15

SB_DQ_58

B15

SB_DQ_59

E14

SB_DQ_60

D14

SB_DQ_61

A14

SB_DQ_62

B14

SB_DQ_63

CONN@

+1.35V

1K_0402_1%~D

12

RC86

+V_SM_VREF_CNT

1K_0402_1%~D

12

RC78

Compal Secret Data

Deciphered Date

+1.35V

12

12

T67 PAD~D@

M_CLK_DDR#0 <14>
M_CLK_DDR0 <14>
DDR_CKE0_DIMMA <14>
M_CLK_DDR#1 <14>
M_CLK_DDR1 <14>
DDR_CKE1_DIMMA <14>
M_CLK_DDR#4 <12>
M_CLK_DDR4 <12>
DDR_CKE4_DIMMC <12>
M_CLK_DDR#5 <12> DDR_CKE6_DIMMD <13>
M_CLK_DDR5 <12>
DDR_CKE5_DIMMC <12>

DDR_CS0_DIMMA# <14>
DDR_CS1_DIMMA# <14>
DDR_CS4_DIMMC# <12>
DDR_CS5_DIMMC# <12>
M_ODT0 <14>
M_ODT1 <14>
M_ODT4 <12>
M_ODT5 <12>
DDR_A_BS0 <12,14>
DDR_A_BS1 <12,14>
DDR_A_BS2 <12,14>

DDR_A_RAS# <12,14>

DDR_A_WE# <12,14>

DDR_A_CAS# <12,14>

DDR_A_MA[0..15] <12,14>

DDR_A_DQS#[0..7] <12,14>

DDR_A_DQS[0..7] <12,14>

1K_0402_1%~D

RC95

+DIMM0_1_VREF_CPU

1K_0402_1%~D

RC81

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

AC7

M_CLK_DDR#0

U4

M_CLK_DDR0

V4

DDR_CKE0_DIMMA

AD9

M_CLK_DDR#1

U3

M_CLK_DDR1

V3

DDR_CKE1_DIMMA

AC9

M_CLK_DDR#4

U2

M_CLK_DDR4

V2

DDR_CKE4_DIMMC

AD8

M_CLK_DDR#5 DDR_CKE6_DIMMD

U1

M_CLK_DDR5

V1

DDR_CKE5_DIMMC

AC8

DDR_CS0_DIMMA#

M7

DDR_CS1_DIMMA#

L9

DDR_CS4_DIMMC#

M9

DDR_CS5_DIMMC#

M10

M_ODT0

M8

M_ODT1

L7

M_ODT4

L8

M_ODT5

L10

DDR_A_BS0

V5

DDR_A_BS1

U5

DDR_A_BS2

AD1

V10

DDR_A_RAS#

U6

DDR_A_WE#

U7

DDR_A_CAS#

U8

DDR_A_MA0

V8

DDR_A_MA1

AC6

DDR_A_MA2

V9

DDR_A_MA3

U9

DDR_A_MA4

AC5

DDR_A_MA5

AC4

DDR_A_MA6

AD6

DDR_A_MA7

AC3

DDR_A_MA8

AD5

DDR_A_MA9

AC2

DDR_A_MA10

V6

DDR_A_MA11

AC1

DDR_A_MA12

AD4

DDR_A_MA13

V7

DDR_A_MA14

AD3

DDR_A_MA15

AD2

DDR_A_DQS#0

AP15

DDR_A_DQS#1

AP8

DDR_A_DQS#2

AJ8

DDR_A_DQS#3

AF3

DDR_A_DQS#4

J3

DDR_A_DQS#5

E2

DDR_A_DQS#6

C5

DDR_A_DQS#7

C11

DDR_A_DQS0

AP14

DDR_A_DQS1

AP9

DDR_A_DQS2

AK8

DDR_A_DQS3

AG3

DDR_A_DQS4

H3

DDR_A_DQS5

E3

DDR_A_DQS6

C6

DDR_A_DQS7

C12

RC148

1 2

0_0402_5%

1

2

12

M_CLK_DDR#2
M_CLK_DDR2
DDR_CKE2_DIMMB
M_CLK_DDR#3
M_CLK_DDR3
DDR_CKE3_DIMMB
M_CLK_DDR#6
M_CLK_DDR6

M_CLK_DDR#7
M_CLK_DDR7
DDR_CKE7_DIMMD

DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
DDR_CS6_DIMMD#
DDR_CS7_DIMMD#

M_ODT2
M_ODT3
M_ODT6
M_ODT7

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

Title

Size Document Number Rev

Custom

Date: Sheet of

T76 PAD~D@

M_CLK_DDR#2 <15>
M_CLK_DDR2 <15>
DDR_CKE2_DIMMB <15>
M_CLK_DDR#3 <15>
M_CLK_DDR3 <15>
DDR_CKE3_DIMMB <15>
M_CLK_DDR#6 <13>
M_CLK_DDR6 <13>

M_CLK_DDR#7 <13>
M_CLK_DDR7 <13>
DDR_CKE7_DIMMD <13>

DDR_CS2_DIMMB# <15>
DDR_CS3_DIMMB# <15>
DDR_CS6_DIMMD# <13>
DDR_CS7_DIMMD# <13>

M_ODT2 <15>
M_ODT3 <15>
M_ODT6 <13>
M_ODT7 <13>
DDR_B_BS0 <13,15>
DDR_B_BS1 <13,15>
DDR_B_BS2 <13,15>

DDR_B_RAS# <13,15>

DDR_B_WE# <13,15>

DDR_B_CAS# <13,15>

DDR_B_MA[0..15] <13,15>

DDR_B_DQS#[0..7] <13,15>

DDR_B_DQS[0..7] <13,15>

Compal Electronics, Inc.

CPU (3/7) DDRIII

LA-9331P

1

8 61Friday, June 22, 2012

0.1

5

4

3

2

1

COMPENSATION PU FOR eDP

+VCOMP_OUT

EDP_COMP

D D

CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.

12

RC124.9_0402_1%~D

Haswell rPGA EDS

CPU_HDMI_N0<36>
CPU_HDMI_P0<36>
CPU_HDMI_N1<36>
CPU_HDMI_P1<36>

HDMI

C C

DMC

B B

CPU_HDMI_N2<36>
CPU_HDMI_P2<36>
CPU_HDMI_N3<36>
CPU_HDMI_P3<36>

CPU_DPD_DMC_N0<39>
CPU_DPD_DMC_P0<39>
CPU_DPD_DMC_N1<39>
CPU_DPD_DMC_P1<39>
CPU_DPD_DMC_N2<39>
CPU_DPD_DMC_P2<39>
CPU_DPD_DMC_N3<39>
CPU_DPD_DMC_P3<39>

CPU_HDMI_N0
CPU_HDMI_P0
CPU_HDMI_N1
CPU_HDMI_P1
CPU_HDMI_N2
CPU_HDMI_P2
CPU_HDMI_N3
CPU_HDMI_P3

CPU_DPD_DMC_N0
CPU_DPD_DMC_P0
CPU_DPD_DMC_N1
CPU_DPD_DMC_P1
CPU_DPD_DMC_N2
CPU_DPD_DMC_P2
CPU_DPD_DMC_N3
CPU_DPD_DMC_P3

T28

DDIB_TXBN_0

U28

DDIB_TXBP_0

T30

DDIB_TXBN_1

U30

DDIB_TXBP_1

U29

DDIB_TXBN_2

V29

DDIB_TXBP_2

U31

DDIB_TXBN_3

V31

DDIB_TXBP_3

T34

DDIC_TXCN_0

U34

DDIC_TXCP_0

U35

DDIC_TXCN_1

V35

DDIC_TXCP_1

U32

DDIC_TXCN_2

T32

DDIC_TXCP_2

U33

DDIC_TXCN_3

V33

DDIC_TXCP_3

P29

DDID_TXDN_0

R29

DDID_TXDP_0

N28

DDID_TXDN_1

P28

DDID_TXDP_1

P31

DDID_TXDN_2

R31

DDID_TXDP_2

N30

DDID_TXDN_3

P30

DDID_TXDP_3

INTEL_HASWELL_HAS WELL

CONN@

JCPU1H

eDP

EDP_AUXN
EDP_AUXP

EDP_HPD

EDP_RCOMP

RSVD

EDP_TXN_0

EDP_TXP_0

EDP_TXN_1

EDP_TXP_1

FDI_TXN_0
FDI_TXP_0
FDI_TXN_1
FDI_TXP_1

DDI

8 OF 9

M27
N27
P27
E24
R27

P35
R35
N34
P34
P33
R33
N32
P32

CPU_EDP_AUX#
CPU_EDP_AUX
EDP_HPD
EDP_COMP

CPU_EDP_N0
CPU_EDP_P0
CPU_EDP_N1
CPU_EDP_P1
CPU_EDP_N2
CPU_EDP_P2
CPU_EDP_N3
CPU_EDP_P3

T77PAD~D @

CPU_EDP_N0 <31>
CPU_EDP_P0 <31>
CPU_EDP_N1 <31>
CPU_EDP_P1 <31>
CPU_EDP_N2 <31>
CPU_EDP_P2 <31>
CPU_EDP_N3 <31>
CPU_EDP_P3 <31>

CPU_EDP_AUX# <31>
CPU_EDP_AUX < 31>

HPD INVERSION FOR EDP

CPU_EDP_HPD#<31>

100K_0402_5%~D

12

RC75

+VCCIO_OUT

2

G

12

10K_0402_5%~D
RC65

EDP_HPD

BSS138_SOT23~D

13

D

QC10

S

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

CPU (4/7) FDI,eDP,DDI

ze Document Number Rev

Si

Custom

LA-9331P

2

Date: Sheet of

1

9 61Friday, June 22, 2012

0.1

5

4

3

2

1

CFG STRAPS for CPU

CFG2

D D

PEG Static Lane Reversal - CFG2 is for the 16x

1:(Default) Normal Operation; Lane #

CFG2

definition matches socket pin map definition
0:Lane Reversed

Haswell rPGA EDS

T103PAD~D@
T80 PAD~D@
T78 PAD~D@

T110PAD~D@
T81 PAD~D@

T79 PAD~D@

C C

B B

RC60 49.9_0402_1%~D

RC58 49.9_0402_1%~D

RC59 49.9_0402_1%~D

H_CPU_TESTLO

12

CFG_RCOMP

12

H_CPU_RSVD

12

T101PAD~D@

T83 PAD~D@
T108PAD~D@

+VCC_CORE

T82 PAD~D@
T94 PAD~D@

T85 PAD~D@

T84 PAD~D@
T86 PAD~D@

CFG0<6>
CFG1<6>
CFG2<6>
CFG3<6>
CFG4<6>
CFG5<6>
CFG6<6>
CFG7<6>
CFG8<6>
CFG9<6>
CFG10<6>
CFG11<6>
CFG12<6>
CFG13<6>
CFG14<6>
CFG15<6>

H_CPU_RSVD

H_CPU_TESTLO

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

AD10

W29
W28

W33
AL30
AL29

AL25

W30

W31

W34

AT20

AR20
AP20
AP22

AT22

AN22

AT25

AN23
AR24

AT23

AN20
AP24
AP26
AN25
AN26
AP25

AT1

RSVD_TP

AT2

RSVD_TP
RSVD

A34

RSVD_TP

A35

RSVD_TP

RSVD
RSVD

G26

RSVD
RSVD
RSVD
RSVD

F25

VCC

C35

RSVD_TP

B35

RSVD_TP

RSVD_TP

RSVD
RSVD
TESTLO

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15

CONN@

IN

TEL_HASWELL_HAS WELL

JCPU1I

RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP

CFG_RCOMP

CFG_16
CFG_18
CFG_17
CFG_19

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

RSVD

RSVD
RSVD

RSVD

RSVD_TP

RSVD_TP
RSVD_TP

RSVD
RSVD

RSVD
RSVD

9 OF 9

C23
B23
D24
D23

CFG_RCOMP

AT31

CFG16

AR21

CFG18

AR23

CFG17

AP21

CFG19

AP23

AR33
G6
AM27
AM26
F5
AM2
K6

E18

U10
P10

B1

NC

A2
AR1

E21
E20

AP27
AR26

AL31
AL32

T99PAD~D @
T90PAD~D @
T87PAD~D @
T88PAD~D @

CFG16 <6>
CFG18 <6>
CFG17 <6>
CFG19 <6>

T91PAD~D @
T104PAD~D @
T92PAD~D @
T89PAD~D @
T93PAD~D @
T95PAD~D @
T111PAD~D @

T96PAD~D @

T98PAD~D @
T97PAD~D @

T100PAD~D @
T109PAD~D @

T102PAD~D @
T107PAD~D @

T105PAD~D @
T106PAD~D @

CFG4

1 : Disabled; No Physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

CFG4

Display Port Presence Strap

CFG6

CFG5

PCIE Port Bifurcation Straps
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2

CFG[6:5]

disabled
01: Reserved - (Device 1 function 1 disabled ; function

2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CFG7

1K_0402_1%~D

12

@

RC76

1K_0402_1%~D

12

RC77

1K_0402_1%~D

1K_0402_1%~D

12

12

@

RC90

@

RC92

1K_0402_1%~D

12

@

RC91

PEG DEFER TRAINING

1: (Default) PEG Train immediately

A A

CFG7

following xxRESETB de assertion

0: PEG Wait for BIOS for training

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

CPU (5/7) RSVD,CFG

ze Document Number Rev

Si

Custom

LA-9331P

2

Date: Sheet of

1

10 61Friday, June 22, 2012

0.1

5

4

3

2

1

+VCC_CORE

AA26

VCC

AA28

VCC

AA34

VCC

AA30

VCC

AA32

VCC

AB26

VCC

AB29

VCC

AB25

VCC

AB27

VCC

AB28

VCC

AB30

VCC

AB31

VCC

AB33

VCC

AB34

VCC

AB32

VCC

AC26

VCC

AB35

VCC

AC28

VCC

AD25

VCC

AC30

VCC

AD28

VCC

AC32

VCC

AD31

VCC

AC34

VCC

AD34

VCC

AD26

VCC

AD27

VCC

AD29

VCC

AD30

VCC

AD32

VCC

AD33

VCC

AD35

VCC

AE26

VCC

AE32

VCC

AE28

VCC

AE30

VCC

AG28

VCC

AG34

VCC

AE34

VCC

AF25

VCC

AF26

VCC

AF27

VCC

AF28

VCC

AF29

VCC

AF30

VCC

AF31

VCC

AF32

VCC

AF33

VCC

AF34

VCC

AF35

VCC

AG26

VCC

AH26

VCC

AH29

VCC

AG30

VCC

AG32

VCC

AH32

VCC

AH35

VCC

AH25

VCC

AH27

VCC

AH28

VCC

AH30

VCC

AH31

VCC

AH33

VCC

AH34

VCC

AJ25

VCC

AJ26

VCC

AJ27

VCC

AJ28

VCC

AJ29

VCC

AJ30

VCC

AJ31

VCC

AJ32

VCC

AJ33

VCC

AJ34

VCC

AJ35

VCC

G25

VCC

H25

VCC

J25

VCC

K25

VCC

L25

VCC

M25

VCC

N25

VCC

P25

VCC

R25

VCC

T25

VCC

U25

VCC

U26

VCC

V25

VCC

V26

VCC

W26

VCC

W27

VCC

AB11

AE11

AH11

AL27
AK27

AL35

AN35

AL16

AL13

AM28
AM29
AL28

AP35

AP34
AT35
AR35
AR32
AL26
AT34
AL22
AT33
AM21
AM25
AM22
AM20
AM24
AL19
AM23
AT32

K27
L27
T27
V27

AB2
AB5
AB8

AE2
AE5
AE8

K11
N11

N8

T11

T2
T5
T8

W11

W2
W5
W8

N26
K26

E17

A23
F22

W32

J27

H27

Y25
Y26
Y27
Y28
Y29
Y30
Y31
Y32
Y33
Y34
Y35

Haswell rPGA EDS

RSVD
RSVD
RSVD
RSVD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

RSVD
VCC
RSVD
RSVD

VCC_SENS E
RSVD
VCCIO_OUT
VCCIO2PCH
VCCIOA_O UT
RSVD
RSVD
VSS
RSVD

VIDALERT
VIDSCLK
VIDSOUT

VSS
PWR_DE BUG
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

TEL_HASWELL_HASWELL

IN

CONN@

JCPU1E

5 OF 9

D D

C C

B B

+1.35V_CPU_VDDQ Source

SUSP#<43,56,59,61>

CPU1.5V_S3_GATE<43>

SVID ALERT

VIDALERT_N<62>

SVID DATA

VIDSOUT<62>

VCC_SENSE

VCCSENSE<62>

VSSSENSE<62>

1 2

RC93 0_0402_5%~D@

1 2

RC79 0_0402_5%~D

+VCCIO_OUT

75_0402_1%~D

12

RC61

+VCCIO_OUT

110_0402_1%~D

12

RC63

+VCC_CORE

100_0402_1%~D

12

RC66

VCCSENSE

VSSSENSE

100_0402_1%~D

12

RC70

+3VALW

100K_0402_5%~D

12

RC74

RUN_ON_CPU1.5VS3#

61

QC4A

DMN66D0LDW-7_SOT363-6~D

2

CAD Note: Place the PU resistors close to CPU
RC60 close to CPU 300 - 1500mils

H_CPU_SVIDALRT#

12

RC6943_0402_5%~D

CAD Note: Place the PU resistors close to CPU
RC63 close to CPU 300 - 1500mils

VIDSOUT

CAD Note: RC67 SHOULD BE PLACED CLOSE TO CPU

VCCSENSE_R

12

RC670_0402_5%~D

CAD Note: RC68 SHOULD BE PLACED CLOSE TO CPU

VSSSENSE_R

12

RC680_0402_5%~D

VSSSENSE_R <11>

B+_BIAS

330K_0402_5%~D

12

RC72

RUN_ON_CPU1.5VS3RUN_ON_CPU1.5VS3

34

QC4B

DMN66D0LDW-7_SOT363-6~D

5

RUN_ON_CPU1.5VS3# <6,56>

+1.35V

QC3

AO4304L_SO8

8
7
6
5

4

0.022U_0402_25V7K~D

1M_0402_5%~D

12

RC143

1

2

+1.05VS

RC4 0_0603_5%~D@

RESISTOR STUFFING OPTIONS ARE
PROVIDED FOR TESTING PURPOSES

+1.35V_CPU_VDDQ

CC136

1
2
3

1

2

1

2

+1.35V_CPU_VDDQ

10U_0603_6.3V6M~D

12

CC135

1

2

12

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

CC180

2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

CC181

1

2

C_0805NEW

20K_0402_5%~D

@

RC73

+VCCIO_OUT

VDDQ DECOUPLING

10U_0603_6.3V6M~D

1

1

CC169

CC170

2

2

22U_0805_6.3V6M~D

CC183

CC182

1

1

2

2

C_0805NEW

T113 PAD~D@
T114 PAD~D@
T112 PAD~D@
T116 PAD~D@

+1.35V

CC151 0.1U_0402_10V7K~D

12

CC152 0.1U_0402_10V7K~D

12

T115 PAD~D@

+VCC_CORE

T151 PAD~D@
T152 PAD~D@

T153 PAD~D@

+VCCIO_OUT

T156 PAD~D@

+VCOMP_OUT

T160 PAD~D@
T159 PAD~D@

+1.05VS

10K_0402_5%~D

12

@

RC80

CPU_PWR_DEBUG

10K_0402_5%~D

12

@

RC71

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

CC168

2

22U_0805_6.3V6M~D

CC184

1

2

C_0805NEW

C_0805NEW

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

1

CC161

CC162

2

2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

CC186

CC185

1

1

2

2

C_0805NEW

C_0805NEW

10U_0603_6.3V6M~D

1

1

CC163

CC164

CC165

2

2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

CC189

CC187

CC188

1

1

2

2

C_0805NEW

C_0805NEW

T168 PAD~D@
T154 PAD~D@

VIDSCLK<62>

CPU_PWR_DEBUG<6>

T157 PAD~D@
T158 PAD~D@
T162 PAD~D@
T163 PAD~D@

10U_0603_6.3V6M~D

330U_D2_2VM_R6M~D

1

CC167

1

+

CC166

2

2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

CC190

CC191

1

1

2

2

C_0805NEW

C_0805NEW

+1.35V_CPU_VDDQ

VCCSENSE_R

H_CPU_SVIDALRT#
VIDSCLK
VIDSOUT

+VCC_CORE

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

CPU (6/7) PWR

ze Document Number Rev

Si

Custom

LA-9331P

Date: Sheet of

1

11 61Friday, June 22, 2012

0.1

5

4

3

2

1

AA11
AA25
AA27
AA31
AA29

AB10
AA33
AA35

AC25
AC27

AC11
AD11
AC29
AC31
AC33
AC35

AE10
AE25
AE29

AE27
AE35

AF11

AG11
AG25
AE31
AG31
AE33

AH10

AG27
AG29

AG33
AG35

AJ11

AK11
AK25
AK26
AK28
AK29
AK30
AK32

A10
A13
A16
A19
A22
A25
A27
A29

A31
A33

AB1

AB3

AB4
AB6
AB7
AB9

AD7
AE1

AE3

AE4
AE6
AE7
AE9

AF6
AF8

AG6
AH1

AH2

AH3

AH4
AH5
AH6
AH7
AH8
AH9

AJ5

E19

A3

A4
A7

Haswell rPGA EDS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

IN

CONN@

JCPU1F

TEL_HASWELL_HAS WELL

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

RSVD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

6 OF 9

AK34
AK5
AL1
AL10
AL11
AL12
AL14
AL15
AL17
AL18
AL2
AL20
AL21
AL23
E22
AL3
AL4
AL5
AL6
AL7
AL8
AL9
AM10
AM13
AM16
AM19
E25
AM32
AM4
AM7
AN10
AN13
AN16
AN19
AN2
AN21
AN24
AN27
AN30
AN34
AN4
AN7
AP1
AP10
AP13
AP16
AP19
AP4
AP7
W25
AR10
AR13
AR16
AR19
AR2
AR22
AR25
AR28
AR31
AR34
AR4
AR7
AT10
AT13
AT16
AT19
AT21
AT24
AT27
AT3
AT30
AT4
AT7
B10
B13
B16
B19
B2
B22

D D

C C

B B

Haswell rPGA EDS

B34

VSS

B4

VSS

B7

VSS

C1

VSS

C10

VSS

C13

VSS

C16

VSS

C19

VSS

C2

VSS

C22

VSS

C24

VSS

C26

VSS

C28

VSS

C30

VSS

C32

VSS

C34

VSS

C4

VSS

C7

VSS

D10

VSS

D13

VSS

D16

VSS

D19

VSS

D22

VSS

D25

VSS

D27

VSS

D29

VSS

D31

VSS

D33

VSS

D35

VSS

D4

VSS

D7

VSS

E1

VSS

E10

VSS

E13

VSS

E16

VSS

E4

VSS

E7

VSS

F10

VSS

F11

VSS

F12

VSS

F14

VSS

F15

VSS

F17

VSS

F18

VSS

F20

VSS

F21

VSS

F23

VSS

F24

VSS

F26

VSS

F28

VSS

F30

VSS

F32

VSS

F34

VSS

F4

VSS

F6

VSS

F7

VSS

F8

VSS

F9

VSS

G1

VSS

G11

VSS

G2

VSS

G27

VSS

G29

VSS

G3

VSS

G31

VSS

G33

VSS

G35

VSS

G4

VSS

G5

VSS

H10

VSS

H26

VSS

H6

VSS

H7

VSS

J11

VSS

J26

VSS

J28

RSVD

J30

VSS

J32

VSS

J34

VSS

J6

VSS

K1

VSS

TEL_HASWELL_HAS WELL

IN

CONN@

JCPU1G

RSVD
RSVD
RSVD
RSVD

VSS_SENSE

RSVD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

7 OF 9

K10
K2
K29
K3
K31
K33
K35
K4
K5
K7
K8
K9
L11
L26
L6
M11
M26
M28
M30
M32
M34
M6
N1
N10
N2
N29
N3
N31
N33
N35
N4
N5
N6
N7
N9
P11
P26
P5
R11
R26
R28
R30
R32
R34
R5
T1
T10
T29
T3
T31
T33
T35
T4
T6
T7
T9
U11
U27
V11
V28
V30
V32
V34
W1
W10
W3
W35
W4
W6
W7
W9
Y11
H11
AL24
F19
T26
AK35
AK33

VSSSENSE_R <10>

T120PAD~D @

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

CPU (7/7) VSS

Size Document Number Rev

Custom

LA-9331P

2

Date: Sheet of

1

12 61Friday, June 22, 2012

0.1

5

D D

DDR_A_DQS#[0..7]<7,14>

DDR_A_D[0..63]<7, 14>

DDR_A_DQS[0..7]<7,14>

DDR_A_MA[0..15]<7,14>

Layout Note:
Place near JDIMMA

C C

B B

A A

+1.35V

1U_0402_6.3V6K~D

1

1

CD3

2

2

+1.35V

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD7

1

1

2

2

Layout Note:
Place near JDIMMA.203,204

+0.675VS

1

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD4

CD8

1

2

1U_0402_6.3V6K~D

CD17

SA0

1

0

0

1U_0402_6.3V6K~D

1

1

CD5

CD6

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD10

CD9

1

1

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD18

2

2

SA1

001

DIMM1A

1

DIMMB

DIMMC

1

DIMMD

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

330U_SX_2VY~D

@

1

CD13

CD11

CD74

1

1

2

1

CD19

2

+

2

2

1U_0402_6.3V6K~D

CD20

10K_0402_5%~D

10K_0402_5%~D

All VREF traces should
have 20 mil trace width

CD14

+3VS

RD38

1 2

RD21

@

1 2

4

RD39

@

10K_0402_5%~D

1 2

+3VS

RD22

10K_0402_5%~D

1 2

+DIMM0_1_VREF_CPU

2.2U_0402_6.3V6M

1

CD1

2

DDR_CKE4_DIMMC<7>

DDR_A_BS2<7,14>

M_CLK_DDR4<7>
M_CLK_DDR#4<7>

DDR_A_BS0<7,14>

DDR_A_WE#<7,14>

DDR_A_CAS#<7,14>

DDR_CS5_DIMMC#<7>

0.1U_0402_25V6K~D

CD21

1

1

2

2

3

JDIMMA H=4mm

JDIMM1

1

VREF_DQ

0.1U_0402_25V6K~D

DDR_A_D0
DDR_A_D1

1

CD2

2

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9 D DR_A_D13

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_D26
DDR_A_D27

DDR_CKE4_DIMMC DDR_CKE5_DIMMC

DDR_A_BS2

DDR_A_MA3

M_CLK_DDR4
M_CLK_DDR#4

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13
DDR_CS5_DIMMC#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59

2.2U_0402_6.3V6M

CD22

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

TYCO_2-2013022-1

CONN@

DQS0#

DQS0

DQ12
DQ13

RESET#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3

DQ30
DQ31

CKE1

CK1#

RAS#

ODT0

ODT1

VREF_CA

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5

DQ46
DQ47

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7

DQ62
DQ63

EVENT#

GND2

BOSS2

2

VSS

4

DQ4

6

DQ5

8

VSS

10
12
14

VSS

16

DQ6

18

DQ7

20

VSS

22
24
26

VSS

28

DM1

30
32

VSS

34
36
38

VSS

40
42
44

VSS

46

DM2

48

VSS

50
52
54

VSS

56
58
60

VSS

62
64
66

VSS

68
70
72

VSS

74
76

VDD

78

A15

80

A14

82

VDD

84

A11

86

A7

88

VDD

90

A6

92

A4

94

VDD

96

A2

98

A0

100

VDD

102

CK1

104
106

VDD

108

BA1

110
112

VDD

114

S0#

116
118

VDD

120
122

NC

124

VDD

126
128

VSS

130
132
134

VSS

136

DM4

138

VSS

140
142
144

VSS

146
148
150

VSS

152
154
156

VSS

158
160
162

VSS

164
166
168

VSS

170

DM6

172

VSS

174
176
178

VSS

180
182
184

VSS

186
188
190

VSS

192
194
196

VSS

198
200

SDA

202

SCL

204

VTT

206
208

+1.35V+1.35V

DDR_A_D4
DDR_A_D5

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D6
DDR_A_D7

DDR_A_D12

DDR3_DRAMRST#_R

DDR_A_D14
DDR_A_D15

DDR_A_D20DDR_A_D16
DDR_A_D21

DDR_A_D22
DDR_A_D23

DDR_A_D28
DDR_A_D29

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D31

DDR_A_MA15
DDR_A_MA14

DDR_A_MA11DDR_A_MA12
DDR_A_MA7DDR_A_MA9

DDR_A_MA6DDR_A_MA8
DDR_A_MA4DDR_A_MA5

DDR_A_MA2
DDR_A_MA0DDR_A_MA1

M_CLK_DDR5
M_CLK_DDR#5

DDR_A_BS1
DDR_A_RAS#

DDR_CS4_DIMMC#
M_ODT4

M_ODT5

DDR_A_D36
DDR_A_D37

DDR_A_D38
DDR_A_D39

DDR_A_D44
DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D46
DDR_A_D47

DDR_A_D52
DDR_A_D53

DDR_A_D54
DDR_A_D55

DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

M_THERMAL#

+0.675VS+0.675VS

DDR_CKE5_DIMMC <7>

M_CLK_DDR5 <7>

M_CLK_DDR#5 <7>

DDR_A_BS1 <7,14>

DDR_A_RAS# <7, 14>

DDR_CS4_DIMMC# <7>

M_ODT4 <7>

M_ODT5 <7>

1

2

M_THERMAL# <13,14,15,43>

PCH_SMBDATA <6,13,14,15,19,49,50,51,53>

PCH_SMBCLK <6,13,14,15,19,49,50,51,53>

+V_SM_VREF_CNT

2.2U_0402_6.3V6M

0.1U_0402_25V6K~D

CD15

1

2

2

DDR3_DRAMRST#_R

CD16

+1.35V

@

1 2

RD29 1K_0402_5%~D

All VREF traces should
have 20 mil trace width

CPU

1K_0402_5%~D

12

RD27

CRB Rev 0.7 is depop

2(H8)

JDIMMA(H4)

3(H5.2)
4(H9.2)

1

DDR3_DRAMRST#_CPU <6>DDR3_DRAMRST#_R<13,14,15>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

DDRIII DIMMA

Size Document Number Rev

Custom

LA-9331P

Date: Sheet of

1

13 61Friday, June 22, 2012

0.1

5

4

3

2

1

D D

+DIMM0_1_CA_CPU

0.1U_0402_25V6K~D

2.2U_0402_6.3V6M

CD23

1

All VREF traces should
have 20 mil trace width

DDR_B_DQS#[0..7]<7,15>

DDR_B_D[0..63]<7, 15>

DDR_B_DQS[0..7]<7,15>

DDR_B_MA[0..15]<7,15>

Layout Note:
Place near JDIMMB

C C

B B

A A

+1.35V

+1.35V

1

2

+0.675VS

10U_0603_6.3V6M~D

CD29

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD26

CD25

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD31

CD30

1

1

1

2

2

2

Layout Note:
Place near JDIMMB.203,204

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD39

CD40

2

2

SA0

SA1

001

DIMMA

1

DIMMB

1

DIMMC

0

1

DIMMD

0

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD27

CD28

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD32

CD33

1

1

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD41

CD42

2

2

330U_SX_2VY~D

@

1

CD36

CD34

CD35

1

+

2

2

+3VS

RD40

10K_0402_5%~D

1 2

RD23

@

10K_0402_5%~D

1 2

RD24

10K_0402_5%~D

1 2

+3VS

RD41

@

10K_0402_5%~D

1 2

2

DDR_CKE6_DIMMD<7>

DDR_B_BS2<7,15>

M_CLK_DDR6<7>
M_CLK_DDR#6<7>

DDR_B_BS0<7,15>

DDR_B_WE#<7,15>

DDR_B_CAS#<7,15>

DDR_CS7_DIMMD#<7>

0.1U_0402_25V6K~D

1

2

DDR_B_D0
DDR_B_D1

CD24

1

DDR_B_D2

2

DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D27

DDR_CKE6_DIMMD

DDR_B_BS2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

M_CLK_DDR6
M_CLK_DDR#6

DDR_B_MA10
DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

DDR_B_MA13
DDR_CS7_DIMMD#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_D58
DDR_B_D59

2.2U_0402_6.3V6M

CD43

CD44

1

2

JDIMMB H=4mm

+1.35V

+0.675VS

JDIMM2

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

SUYIN_600025HB204G251ZL

CONN@

DQS0#

DQS0

DQ12
DQ13

RESET#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3

DQ30
DQ31

CKE1

CK1#

RAS#

ODT0

ODT1

VREF_CA

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5

DQ46
DQ47

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7

DQ62
DQ63

EVENT#

GND2

BOSS2

+1.35V

2

VSS
DQ4
DQ5
VSS

VSS
DQ6
DQ7
VSS

VSS
DM1

VSS

VSS

VSS
DM2
VSS

VSS

VSS

VSS

VSS

VDD

A15
A14

VDD

A11

VDD

VDD

VDD
CK1

VDD
BA1

VDD

S0#

VDD

VDD

VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
DM6
VSS

VSS

VSS

VSS

VSS

SDA
SCL

VTT

DDR_B_D4

4

DDR_B_D5

6
8

DDR_B_DQS#0

10

DDR_B_DQS0

12
14

DDR_B_D6

16

DDR_B_D7

18
20

DDR_B_D12

22

DDR_B_D13

24
26
28

DDR3_DRAMRST#_R

30
32

DDR_B_D14

34

DDR_B_D15

36
38

DDR_B_D20

40

DDR_B_D21

42
44
46
48

DDR_B_D22

50

DDR_B_D23

52
54

DDR_B_D28

56

DDR_B_D29

58
60

DDR_B_DQS#3

62

DDR_B_DQS3

64
66

DDR_B_D30

68

DDR_B_D31

70
72

DDR_CKE7_DIMMD

74
76

DDR_B_MA15

78

DDR_B_MA14

80
82

DDR_B_MA11

84

DDR_B_MA7

86

A7

88

DDR_B_MA6

90

A6

DDR_B_MA4

92

A4

94

DDR_B_MA2

96

A2

DDR_B_MA0

98

A0

100

M_CLK_DDR7

102

M_CLK_DDR#7

104
106

DDR_B_BS1

108

DDR_B_RAS#

110
112

DDR_CS6_DIMMD#

114

M_ODT6

116
118

M_ODT7

120
122

NC

124
126
128

DDR_B_D36

130

DDR_B_D37

132
134
136
138

DDR_B_D38

140

DDR_B_D39

142
144

DDR_B_D44

146

DDR_B_D45

148
150

DDR_B_DQS#5

152

DDR_B_DQS5

154
156

DDR_B_D46

158

DDR_B_D47

160
162

DDR_B_D52

164

DDR_B_D53

166
168
170
172

DDR_B_D54

174

DDR_B_D55

176
178

DDR_B_D60

180

DDR_B_D61

182
184

DDR_B_DQS#7

186

DDR_B_DQS7

188
190

DDR_B_D62

192

DDR_B_D63

194
196

M_THERMAL#

198
200
202
204

206
208

+0.675VS

DDR3_DRAMRST#_R <12,14,15>

DDR_CKE7_DIMMD <7>

M_CLK_DDR7 <7>

M_CLK_DDR#7 <7>

DDR_B_BS1 <7,15>
DDR_B_RAS# <7, 15>

DDR_CS6_DIMMD# <7>

M_ODT6 <7>

+V_SM_VREF_CNT

M_ODT7 <7>

2.2U_0402_6.3V6M

CD37

1

2

M_THERMAL# <12,14,15,43>

PCH_SMBDATA <6,12,14,15,19,49,50,51,53>

PCH_SMBCLK <6,12,14,15,19,49,50,51,53>

0.1U_0402_25V6K~D

CD38

1

2

All VREF traces should
have 20 mil trace width

CPU

JDIMMB(H8)

1(H4)

3(H5.2)
4(H9.2)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

DDRIII DIMMB

Size Document Number Rev

Custom

LA-9331P

Date: Sheet of

1

14 61Friday, June 22, 2012

0.1

5

4

3

2

1

D D

All VREF traces should
have 20 mil trace width

DDR_A_DQS#[0..7]<7,12>

DDR_A_D[0..63]<7, 12>

DDR_A_DQS[0..7]<7,12>

DDR_A_MA[0..15]<7,12>

Layout Note:
Place near JDIMMC

C C

B B

A A

+1.35V

1U_0402_6.3V6K~D

1

1

CD12

2

2

+1.35V

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD56

1

1

2

2

Layout Note:
Place near JDIMMC.203,204

+0.675VS

1

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD54

CD63

CD47

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

330U_SX_2VY~D

@

CD45

1

CD75

CD46

CD62

CD59

1

2

1U_0402_6.3V6K~D

1

CD64

2

SA0

SA1

001

1

1

0

1

0

CD49

CD61

1

1

1

1

+

2

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CD57

CD51

2

DIMMA

DIMMB

DIMMC

DIMMD

2

2

RD25

10K_0402_5%~D

RD42

10K_0402_5%~D

+3VS

@

1 2

1 2

1U_0402_6.3V6K~D

1

CD55

2

RD43

@

10K_0402_5%~D

1 2

+3VS

RD26

10K_0402_5%~D

1 2

+DIMM0_1_VREF_CPU

2.2U_0402_6.3V6M

1

CD50

2

DDR_CKE0_DIMMA<7>

DDR_A_BS2<7,12>

M_CLK_DDR0<7>

DDR_A_BS0<7,12>

DDR_A_WE#<7,12>

DDR_A_CAS#<7,12>

DDR_CS1_DIMMA#<7>

0.1U_0402_25V6K~D

CD48

1

2

0.1U_0402_25V6K~D

DDR_A_D0
DDR_A_D1

1

CD53

2

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9 D DR_A_D13

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA DDR_CKE1_DIMMA

DDR_A_BS2

DDR_A_MA3

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13
DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59

2.2U_0402_6.3V6M

CD60

1

2

JDIMMC H=5.2mm

JDIMM3

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

+0.675VS

203

VTT

205

GND1

207

BOSS1

LCN_DAN06-K4526-0103

CONN@

DQS0#

DQS0

DQ12
DQ13

RESET#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3

DQ30
DQ31

CKE1

CK1#

RAS#

ODT0

ODT1

VREF_CA

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5

DQ46
DQ47

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7

DQ62
DQ63

EVENT#

GND2

BOSS2

+1.35V+1.35V

2

VSS
DQ4
DQ5
VSS

VSS
DQ6
DQ7
VSS

VSS
DM1

VSS

VSS

VSS
DM2
VSS

VSS

VSS

VSS

VSS

VDD

A15
A14

VDD

A11

VDD

VDD

VDD
CK1

VDD
BA1

VDD

S0#

VDD

VDD

VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
DM6
VSS

VSS

VSS

VSS

VSS

SDA
SCL

VTT

DDR_A_D4

4

DDR_A_D5

6
8

DDR_A_DQS#0

10

DDR_A_DQS0

12
14

DDR_A_D6

16

DDR_A_D7

18
20

DDR_A_D12

22
24
26
28

DDR3_DRAMRST#_R

30
32

DDR_A_D14

34

DDR_A_D15

36
38

DDR_A_D20DDR_A_D16

40

DDR_A_D21

42
44
46
48

DDR_A_D22

50

DDR_A_D23

52
54

DDR_A_D28

56

DDR_A_D29

58
60

DDR_A_DQS#3

62

DDR_A_DQS3

64
66

DDR_A_D30

68

DDR_A_D31

70
72

74
76

DDR_A_MA15

78

DDR_A_MA14

80
82

DDR_A_MA11DDR_A_MA12

84

DDR_A_MA7DDR_A_MA9

86

A7

88

DDR_A_MA6DDR_A_MA8

90

A6

DDR_A_MA4DDR_A_MA5

92

A4

94

DDR_A_MA2

96

A2

DDR_A_MA0DDR_A_MA1

98

A0

100

M_CLK_DDR1

102

M_CLK_DDR#1

104
106

DDR_A_BS1

108

DDR_A_RAS#

110
112

DDR_CS0_DIMMA#

114

M_ODT0

116
118

M_ODT1

120
122

NC

124
126
128

DDR_A_D36

130

DDR_A_D37

132
134
136
138

DDR_A_D38

140

DDR_A_D39

142
144

DDR_A_D44

146

DDR_A_D45

148
150

DDR_A_DQS#5

152

DDR_A_DQS5

154
156

DDR_A_D46

158

DDR_A_D47

160
162

DDR_A_D52

164

DDR_A_D53

166
168
170
172

DDR_A_D54

174

DDR_A_D55

176
178

DDR_A_D60

180

DDR_A_D61

182
184

DDR_A_DQS#7

186

DDR_A_DQS7

188
190

DDR_A_D62

192

DDR_A_D63

194
196

M_THERMAL#

198
200
202
204

206
208

+0.675VS

DDR3_DRAMRST#_R <12,13,15>

DDR_CKE1_DIMMA <7>

M_CLK_DDR1 <7>

M_CLK_DDR#1 <7>M_CLK_DDR#0<7>

DDR_A_BS1 <7,12>
DDR_A_RAS# <7, 12>

DDR_CS0_DIMMA# <7>

M_ODT0 <7>

M_ODT1 <7>

+V_SM_VREF_CNT

2.2U_0402_6.3V6M

CD52

1

2

M_THERMAL# <12,13,15,43>

PCH_SMBDATA <6,12,13,15,19,49,50,51,53>

PCH_SMBCLK <6,12,13,15,19,49,50,51,53>

0.1U_0402_25V6K~D

1

2

CD58

All VREF traces should
have 20 mil trace width

CPU

2(H8)
1(H4)

JDIMMC(H5.2)

4(H9.2)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

DDRIII DIMMC

ze Document Number Rev

Si

Custom

LA-9331P

Date: Sheet of

1

15 61Friday, June 22, 2012

0.1

5

4

3

2

1

D D

All VREF traces should
have 20 mil trace width

DDR_B_DQS#[0..7]<7,13>

DDR_B_D[0..63]<7, 13>

DDR_B_DQS[0..7]<7,13>

DDR_B_MA[0..15]<7,13>

Layout Note:
Place near JDIMMD

+1.35V

+1.35V

10U_0603_6.3V6M~D

1

2

+0.675VS

CD67

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD80

CD82

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD87

CD81

1

1

1

2

2

2

Layout Note:
Place near JDIMMD.203,204

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD89

CD77

2

2

SA0

SA1

001

DIMMA

1

DIMMB

1

DIMMC

0

1

DIMMD

0

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD71

CD78

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD79

1

2

1U_0402_6.3V6K~D

1

CD86

2

10U_0603_6.3V6M~D

330U_SX_2VY~D

@

1

CD88

CD65

1

2

1U_0402_6.3V6K~D

1

CD85

2

CD68

CD70

1

+

2

2

+3VS

RD31

@

10K_0402_5%~D

RD44

10K_0402_5%~D

C C

B B

A A

1 2

1 2

+DIMM0_1_CA_CPU

RD32

10K_0402_5%~D

1 2

+3VS

RD45

@

10K_0402_5%~D

1 2

2.2U_0402_6.3V6M

0.1U_0402_25V6K~D

DDR_B_D0

CD84

1

2

DDR_CKE2_DIMMB<7>

M_CLK_DDR2<7>
M_CLK_DDR#2<7>

DDR_B_CAS#<7,13>

DDR_CS3_DIMMB#<7>

0.1U_0402_25V6K~D

1

2

DDR_B_D1

CD76

1

DDR_B_D2

2

DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_BS2<7,13>

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

M_CLK_DDR2
M_CLK_DDR#2

DDR_B_MA10
DDR_B_BS0

DDR_B_BS0<7,13>

DDR_B_WE#

DDR_B_WE#<7,13>

DDR_B_CAS#

DDR_B_MA13
DDR_CS3_DIMMB#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_D58
DDR_B_D59

2.2U_0402_6.3V6M

CD69

CD66

1

2

JDIMMD H=9.2mm

+1.35V

JDIMM4

3
5
7

11

15
17

21
23

63

77
79

85

89
91

95
97

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201

+0.675VS

203

205

FOX_AS0A626-UARN-7F
CO

VREF_DQ1VSS1
VSS2
DQ0
DQ1

VSS3
VSS49DQS#0
DM0

DQS0
VSS513VSS6
DQ2
DQ3
VSS719VSS8
DQ8

DQ12
DQ9

DQ13
VSS925VSS10
DQS#127DM1
DQS129RESET#
VSS1131VSS12
DQ1033DQ14
DQ1135DQ15
VSS1337VSS14
DQ1639DQ20
DQ1741DQ21
VSS1543VSS16
DQS#245DM2
DQS247VSS17
VSS1849DQ22
DQ1851DQ23
DQ1953VSS19
VSS2055DQ28
DQ2457DQ29
DQ2559VSS21
VSS2261DQS#3
DM3

DQS3
VSS2365VSS24
DQ2667DQ30
DQ2769DQ31
VSS2571VSS26

CKE073CKE1
VDD175VDD2
NC1
BA2
VDD381VDD4
A12/BC#83A11
A9
VDD587VDD6
A8
A5
VDD793VDD8
A3
A1
VDD999VDD10
CK0
CK0#

CK1#
VDD11

VDD12
A10/AP
BA0

RAS#

VDD13

VDD14
WE#
CAS#

ODT0

VDD15

VDD16
A13

ODT1
S1#
VDD17

VDD18

NCTEST

VREF_CA

VSS27

VSS28

DQ32

DQ36
DQ33

DQ37
VSS29

VSS30
DQS#4
DQS4

VSS31
VSS32

DQ38

DQ34

DQ39

DQ35

VSS33
VSS34

DQ44

DQ40

DQ45

DQ41

VSS35
VSS36

DQS#5

DM5

DQS5

VSS37

VSS38
DQ42

DQ46

DQ43

DQ47

VSS39

VSS40
DQ48

DQ52

DQ49

DQ53

VSS41

VSS42
DQS#6
DQS6

VSS43
VSS44

DQ54

DQ50

DQ55

DQ51

VSS45
VSS46

DQ60

DQ56

DQ61

DQ57

VSS47
VSS48

DQS#7

DM7

DQS7

VSS49

VSS50
DQ58

DQ62

DQ59

DQ63

VSS51

VSS52
SA0

EVENT#
VDDSPD
SA1
VTT1

VTT2

G1

NN@

+1.35V

2

DDR_B_D4

4

DQ4
DQ5

DQ6
DQ7

A15
A14

CK1

BA1

S0#

NC2

DM4

DM6

SDA

SCL

DDR_B_D5

6
8

DDR_B_DQS#0

10

DDR_B_DQS0

12
14

DDR_B_D6

16

DDR_B_D7

18
20

DDR_B_D12

22

DDR_B_D13

24
26
28

DDR3_DRAMRST#_R

30
32

DDR_B_D14

34

DDR_B_D15

36
38

DDR_B_D20

40

DDR_B_D21

42
44
46
48

DDR_B_D22

50

DDR_B_D23

52
54

DDR_B_D28

56

DDR_B_D29

58
60

DDR_B_DQS#3

62

DDR_B_DQS3

64
66

DDR_B_D30

68

DDR_B_D31

70
72

DDR_CKE3_DIMMB

74
76

DDR_B_MA15

78

DDR_B_MA14

80
82

DDR_B_MA11

84

DDR_B_MA7

86

A7

88

DDR_B_MA6

90

A6

DDR_B_MA4

92

A4

94

DDR_B_MA2

96

A2

DDR_B_MA0

98

A0

100

M_CLK_DDR3

102

M_CLK_DDR#3

104
106

DDR_B_BS1

108

DDR_B_RAS#

110
112

DDR_CS2_DIMMB#

114

M_ODT2

116
118

M_ODT3

120
122
124
126
128

DDR_B_D36

130

DDR_B_D37

132
134
136
138

DDR_B_D38

140

DDR_B_D39

142
144

DDR_B_D44

146

DDR_B_D45

148
150

DDR_B_DQS#5

152

DDR_B_DQS5

154
156

DDR_B_D46

158

DDR_B_D47

160
162

DDR_B_D52

164

DDR_B_D53

166
168
170
172

DDR_B_D54

174

DDR_B_D55

176
178

DDR_B_D60

180

DDR_B_D61

182
184

DDR_B_DQS#7

186

DDR_B_DQS7

188
190

DDR_B_D62

192

DDR_B_D63

194
196

M_THERMAL#

198
200
202
204

206

G2

+0.675VS

DDR3_DRAMRST#_R <12,13,14>

DDR_CKE3_DIMMB <7>

M_CLK_DDR3 <7>

M_CLK_DDR#3 <7>

DDR_B_BS1 <7,13>
DDR_B_RAS# <7, 13>

DDR_CS2_DIMMB# <7>

M_ODT2 <7>

+V_SM_VREF_CNT

M_ODT3 <7>

2.2U_0402_6.3V6M

CD72

1

2

M_THERMAL# <12,13,14,43>

PCH_SMBDATA <6,12,13,14,19,49,50,51,53>

PCH_SMBCLK <6,12,13,14,19,49,50,51,53>

CD83

All VREF traces should
have 20 mil trace width

CPU

2(H8)
1(H4)

3(H5.2)

JDIMMD(H9.2)

0.1U_0402_25V6K~D

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

DDRIII DIMMD

Size Document Number Rev

Custom

LA-9331P

Date: Sheet of

1

16 61Friday, June 22, 2012

0.1

5

+RTC_CELL

12

4

330K_0402_1%~D

RH38

3

2

1

D D

INTVRMEN - INTEGRATED SUS 1.05V VRM
ENABLE
High - Enable Internal VRs
Low - Enable External VRs

+3VS

RH35 10K_0402_5%~D@

NO REBOOT STRAP

DISABLED WHEN LOW (DEFAULT)
ENABLED WHEN HIGH

C C

+3VS

RH355 100K_0402_5%~D

CMOS_CLR1

Shunt Clear CMOS

Open

ME_CLR1

Shunt Clear ME RTC Registers

Open

HDA_SYNC Isolation Circuit

B B

RTC Battery

+3VLP

A A

W=20mils

W=20mils

330K_0402_1%~D

12

1 2

1 2

CMOS setting

Keep CMOS

TPM setting

Keep ME RTC Registers

+RTCBATT

1 2

W=20mils

2

3

1

1

CH12
1U_0603_10V6K

2

5

PCH_INTVRMEN

@

RH39

HDA_SPKR

PCH_GPIO33

+5VS

S

1M_0402_5%~D

SSM3K7002FU_SC70-3~D

RH31

1 2

RH34
1K_0402_5%

DH1
BAT54CW_SOT323-3

+RTC_CELL

+3V_PCH

1 2

RH287 1K_0402_1%~D@

FLASH DESCRIPTOR SECURITY OVERRIDE

LOW = DESABLED (DEFAULT)
HIGH = ENABLED

+RTC_CELL

1

1

@

ME1 SHORT PADS~D

1 2

CH5 1U_0402_6.3V6K~D

G

2

PCH_AZ_SYNCPCH_AZ_SYNC_Q

13

D

QH8

PCH_AZ_SDOUT

CH2

PCH_RTCX1_R

1 2

18P_0402_50V8J~D

RH22 20K_0402_5%~D

1 2

RH11 1M_0402_5%~D

1 2

RH23 20K_0402_5%~D

1 2

2

2

+3V_PCH

0_0603_5%~D

12

RH288

1

CH4

CMOS place near DIMM

+3.3V_ALW_PCH_JTAG PCH_JTAG_TMS

18P_0402_50V8J~D

2

1

2

@

CMOS1 SHORT PADS~D

1 2

1U_0402_6.3V6K~D

RH59 51_0402_1%~D

12

RH44 210_0402_1%~D

1 2

@

RH45 210_0402_1%~D

1 2

@

RH46 210_0402_1%~D

1 2

@

CH3

1 2

12

YH1

32.768KHZ_12.5PF_Q13FC1350000~D

HDA for Codec

PCH_AZ_SDOUT

PCH_AZ_CODEC_SDOUT<45>

PCH_AZ_CODEC_SYNC<45>

PCH_AZ_CODEC_RST#<45>

PCH_AZ_CODEC_BITCLK<45>

4

1 2

RH29 33_0402_5%~D

1 2

RH56 33_0402_5%~D

1 2

RH27 33_0402_5%~D

1 2

RH26 33_0402_5%~D

27P_0402_50V8J~D

@

CH101

1

2

PCH_AZ_SYNC_Q

PCH_AZ_RST#

PCH_AZ_BITCLK

1 2

RH286 0_0402_5%~D

HDA_SPKR<45>

PCH_AZ_CODEC_SDIN0<45>

HDA_SDO<43>

100_0402_1%~D

12

RH48

1 2

RH50 1K_0402_1%~D

DP_PCH_HPD<30>

100_0402_1%~D

100_0402_1%~D

12

12

RH49

RH47

PCH_JTAG_TCK

PCH_JTAG_TDI

PCH_JTAG_TDO

RH289 0_0402_5%~D

12

RH2
10M_0402_5%~D

PCH_RTCX2

SRTCRST#

INTRUDER#

PCH_INTVRMEN

PCH_RTCRST#

PCH_AZ_BITCLK

PCH_AZ_SYNC

HDA_SPKR

PCH_AZ_RST#

PCH_AZ_CODEC_SDIN0

PCH_AZ_SDOUT

PCH_GPIO33

DP_PCH_HPD

1 2

T122 PAD~D@

PCH_RTCX1

3

PCH_TP25

PCH_GPIO21

BBS_BIT0_R

PCH_SATALED#

UH1A

B5

RTCX1

B4

RTCX2

B9

SRTCRST#

A8

INTRUDER#

G10

INTVRMEN

D9

RTCRST#

B25

HDA_BCLK

A22

HDA_SYNC

AL10

SPKR

C24

HDA_RST#

L22

HDA_SDI0

K22

HDA_SDI1

G22

HDA_SDI2

F22

HDA_SDI3

A24

HDA_SDO

B17

DOCKEN#/G PIO33

C22

HDA_DOCK_ RST#/GPIO13

AB3

JTAG_TCK

AD1

JTAG_TMS

AE2

JTAG_TDI

AD3

JTAG_TDO

F8

TP25

C26

TP22

AB6

TP20

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

LPT_PCH_M_EDS

JTAGRTC AZALIA

LYNXPOINT_BGA695

5

SATA

SATA_RXN4 /PERN1
SATA_RXP4 /PERP1

SATA_TXN4/P ETN1
SATA_TXP4/P ETP1

SATA_RXN5 /PERN2
SATA_RXP5 /PERP2

SATA_TXN5/P ETN2
SATA_TXP5/P ETP2

SATA0GP/G PIO21

SATA1GP/G PIO19

SATA_RXN_ 0
SATA_RXP_ 0

SATA_TXN_0
SATA_TXP_0

SATA_RXN_ 1
SATA_RXP_ 1

SATA_TXN_1
SATA_TXP_1

SATA_RXN_ 2
SATA_RXP_ 2

SATA_TXN_2
SATA_TXP_2

SATA_RXN_ 3
SATA_RXP_ 3

SATA_TXN_3
SATA_TXP_3

SATA_RCOMP

SATALED#

SATA_IREF

TP9

TP8

BC8

SATA_PRX_DTX_P0

BE8

SATA_PTX_DRX_N0

AW8

SATA_PTX_DRX_P0

AY8

SATA_PRX_DTX_N1

BC10

SATA_PRX_DTX_P1

BE10

SATA_PTX_DRX_N1

AV10

SATA_PTX_DRX_P1

AW10

SATA_ODD_PRX_DTX_N2

BB9

SATA_ODD_PRX_DTX_P2

BD9

SATA_ODD_PTX_DRX_N2

AY13

SATA_ODD_PTX_DRX_P2

AW13

MSATA_PRX_DTX_N3

BC12

MSATA_PRX_DTX_P3

BE12

MSATA_PTX_DRX_N3

AR13

MSATA_PTX_DRX_P3

AT13

PCIE_PRX_WLANTX_N1

BD13

PCIE_PRX_WLANTX_P1

BB13

PCIE_PTX_WLANRX_N1

AV15

PCIE_PTX_WLANRX_P1

AW15

PCIE_PRX_WANTX_N2

BC14

PCIE_PRX_WANTX_P2

BE14

PCIE_PTX_WANRX_N2

AP15

PCIE_PTX_WANRX_P2

AR15

SATA_COMP

AY5

PCH_SATALED#

AP3

PCH_GPIO21

AT1

BBS_BIT0_R

AU2

SATA_IREF

BD4

BA2

BB2

T161PAD~D @

T155PAD~D @

SATA_PRX_DTX_N0

SATA Impedance Compensation

1 OF 11

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

2

SATA_COMP

CAD note:
Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.

SATA_PRX_DTX_N0 <49>
SATA_PRX_DTX_P0 <49>

SATA_PTX_DRX_N0 <49>
SATA_PTX_DRX_P0 <49>

SATA_PRX_DTX_N1 <49>
SATA_PRX_DTX_P1 <49>

SATA_PTX_DRX_N1 <49>
SATA_PTX_DRX_P1 <49>

SATA_ODD_PRX_DTX_N2 <50>
SATA_ODD_PRX_DTX_P2 <50>

SATA_ODD_PTX_DRX_N2 <50>
SATA_ODD_PTX_DRX_P2 <50>

MSATA_PRX_DTX_N3 <50>
MSATA_PRX_DTX_P3 <50>

MSATA_PTX_DRX_N3 <50>
MSATA_PTX_DRX_P3 <50>

PCIE_PRX_WLANTX_N1 <51>
PCIE_PRX_WLANTX_P1 <51>

PCIE_PTX_WLANRX_N1 <51>

PCIE_PTX_WLANRX_P1 <51>

PCIE_PRX_WANTX_N2 <51>
PCIE_PRX_WANTX_P2 <51>

PCIE_PTX_WANRX_N2 <51>
PCIE_PTX_WANRX_P2 <51>

PCH_SATALED# <48>

12

RH410_0402_5%

1 2

1 2

+3VS

RH3010K_0402_5%~D

12

RH524.7K_0402_5%~D

RH5510K_0402_5%~D

HDD1(Master)

HDD2(Slave)

ODD/HDD3 Bay

mSATA

MiniWLAN (Mini Card 1)

MiniDMC (Mini Card 2)

+1.5VS

+1.5VS

1 2

RH407.5K_0402_1%~D

Compal Electronics, Inc.

Title

PCH (1/9) RTC,HDA,SATA,XDP

ze Document Number Rev

Si

Custom

LA-9331P

Date: Sheet of

1

17 61Friday, June 22, 2012

0.1

5

D D

+3V_PCH

1 2

RH318 10K_0402_5%~D@

1 2

RH153 10K_0402_5%~D

1 2

RH148 10K_0402_5%~D

1 2

RH172 10K_0402_5%~D

+3VS

1 2

RH138 8.2K_0402_5%~D

1 2

RH152 8.2K_0402_5%~D@

DMI_CTX_PRX_N0<5>
DMI_CTX_PRX_N1<5>

DMI_CTX_PRX_N2<5>
DMI_CTX_PRX_N3<5>

DMI_CTX_PRX_P0<5>

C C

PM_DRAM_PWRGD<6>

PCH_RSMRST#<43>

B B

A A

SUSPWRDNACK<43>

+PCH_VCCDSW3_3

DMI_CTX_PRX_P1<5>

DMI_CTX_PRX_P2<5>
DMI_CTX_PRX_P3<5>

DMI_CRX_PTX_N0<5>
DMI_CRX_PTX_N1<5>

DMI_CRX_PTX_N2<5>
DMI_CRX_PTX_N3<5>

DMI_CRX_PTX_P0<5>
DMI_CRX_PTX_P1<5>

DMI_CRX_PTX_P2<5>
DMI_CRX_PTX_P3<5>

+1.5VS

+1.5VS

SG_AMD_BKL<42,43>

SYS_PWROK<6>

PCH_PWROK<43>

PBTN_OUT#<6, 43>

10K_0402_5%

ACIN<29,43,47,57,63>

SUS_STAT#

SUSPWRDNACK

PCIE_WAKE#

PCH_RI#

PM_CLKRUN#

ME_RESET#

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1

DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1

DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1

DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1

DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_IREF

12

RH43 0_0402_5%

T139 PAD~D@

T123 PAD~D@

1 2

RH204 7.5K_0402_1%~D

1 2

RH114 0_0402_5%~D@

1 2

RH193 0_0402_5%~D

1 2

RH144 0_0402_5%~D

1 2

RH149 0_0402_5%~D

1 2

RH320 0_0402_5%~D

1 2

RH185 0_0402_5%~D

1 2

RH200 0_0402_5%~D

1 2

RH163 0_0402_5%~D

1 2

RH156 8.2K_0402_5%~D

IMVP_PWRGD<6, 43,62>

+3V_PCH

12

R1899

61

2

5

SUSACK#_R

SYS_RESET#

SYS_PWROK_R

PCH_PWROK_R

PM_APWROK_R

PM_DRAM_PWRGD_R

PCH_RSMRST#_R

ME_SUS_PWR_ACK_R

ACIN_PCH

PCH_BATLOW#

T140 PAD~D@

1

CH41

0.1U_0402_16V7K

2

PCH_PWROK

1

2

+3V_PCH

12

R1900
10K_0402_5%

ACIN_PCH

34

DMN66D0LDW-7_SOT363-6~D

5

QH13B

DMN66D0LDW-7_SOT363-6~D
QH13A

DMI_RCOMP

SIO_PWRBTN#_R

PCH_RI#

+3VS

IN1

IN2

XDP_DBRESET#<6>

UH1B

AW22

DMI_RXN_0

AR20

DMI_RXN_1

AP17

DMI_RXN_2

AV20

DMI_RXN_3

AY22

DMI_RXP_0

AP20

DMI_RXP_1

AR17

DMI_RXP_2

AW20

DMI_RXP_3

BD21

DMI_TXN_0

BE20

DMI_TXN_1

BD17

DMI_TXN_2

BE18

DMI_TXN_3

BB21

DMI_TXP_0

BC20

DMI_TXP_1

BB17

DMI_TXP_2

BC18

DMI_TXP_3

BE16

DMI_IREF

AW17

TP12

AV17

TP7

AY17

DMI_RCOMP

R6

SUSACK#

AM1

SYS_RESE T#

AD7

SYS_PW ROK

F10

PWROK

AB7

APWROK

H3

DRAMPWR OK

J2

RSMRST#

J4

SUSWAR N#/SUSPWR NACK/GPIO30

K1

PWRBTN#

E6

ACPRESEN T/GPIO31

K7

BATLOW# /GPIO72

N4

RI#

AB10

TP21

D2

SLP_W LAN#/GPIO2 9

5

UH8

VCC

SYS_PWROK

4

OUT

GND

MC74VHC1G08DFT2G_SC70-5

3

RH199 8.2K_0402_5%~D@

LYNXPOINT_BGA695

4

RH357 0_0402_5%~D

1 2

+3VS

CH143

@

1 2

5

0.1U_0402_25V6K~D

1

P

B

4

ME_RESET#

12

ME_SUS_PWR_ACK_R SUSACK#_R

LPT_PCH_M_EDS

DMI

O

2

A

G

UH13

@

74AHC1G09GW_TSSOP5~D

3

1 2

RH323 0_0402_5%~D

5

FDI_RXN_0

FDI_RXN_1

FDI_RXP_0

FDI

FDI_RXP_1

FDI_CSYNC

FDI_INT

FDI_IREF

FDI_RCOMP

System Power

Management

BBS_BIT1

1K_0402_1%~D

12

4 OF 11

@

RH342

DSWVRME N

DPWROK

CLKRUN#

SUS_STAT#/G PIO61

SUSCLK/G PIO62

SLP_S5# /GPIO63

SLP_S4#

SLP_S3#

SLP_SUS #

PMSYNCH

SLP_LAN #

GNT1#/GPIO51
(BBS_BIT1)

WAKE#

SLP_A#

0 1 Reserved (NAND)

1 0

*

GPIO51 has internal pull up.

4

SYS_RESET#

AJ35

AL35

AJ36

AL36

AV43

TP16

AY45

TP5

AV45

TP15

AW44

TP10

FDI_CSYNC

AL39

FDI_INT

AL40

FDI_IREF

AT45

AU42

TP17

AU44

TP13

FDI_RCOMP

AR44

DSWODVREN

C8

PCH_DRWROK_R

L13

PCIE_WAKE#

K3

PM_CLKRUN#

AN7

SUS_STAT#

U7

Y6

PM_SLP_S5#

Y7

PM_SLP_S4#

C6

PM_SLP_S3#

H1

F3

PM_SLP_SUS#

F1

H_PM_SYNC

AY3

G5

Boot BIOS Strap

SATA1GP/GPIO19
(BBS_BIT0)

00 LPC

11 SPI

T144PAD~D @

T141PAD~D @

T147PAD~D @

T148PAD~D @

FDI_CSYNC <5>

FDI_INT <5>

12

RH420_0402_5%

T145PAD~D @

T146PAD~D @

12

RH2067.5K_0402_1%~D

RH167 0_0402_5%~D

1 2
1 2

RH186 0_0402_5%~D@

PCIE_WAKE# <43,44,51>

T129 PAD~D@

T126 PAD~D@

PM_SLP_S5# <43,47>

T125 PAD~D

PM_SLP_S4# <43>

PM_SLP_S3# <43,47>

T128 PAD~D

PM_SLP_SUS# <43>

T127 PAD~D

H_PM_SYNC <6>

Boot BIOS Location

PCI

+1.5VS

+1.5VS

@

3

PCH_EDP_PWM<40>

DGPU_SELECT#<32,36,42>

HDMI_IN_PWMSEL#<42>

PCH_RSMRST#_R

PCH_DPWROK <43>

@

@

DSWODVREN

DSWODVREN - ON DIE DSW VR ENABLE

HIGH = ENABLED (DEFAULT)
LOW = DISABLED

Security Classification

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

RH139 649_0402_1%~D

PCH_EDP_PWM

PCI_PIRQA#

PCI_PIRQB#

PCI_PIRQC#

PCI_PIRQD#

DGPU_SELECT#

BBS_BIT1

HDMI_IN_PWMSEL#

WL_OFF#

WL_OFF#<51>

DGPU_HOLD_RST#<43>

+RTC_CELL

330K_0402_1%~D

RH191

1 2

330K_0402_1%~D

@

RH178

1 2

Issued Date

2

T45

VGA_BLU E

U44

VGA_GRE EN

V45

VGA_RED

M43

VGA_DDC_ CLK

M45

VGA_DDC_ DATA

N42

VGA_HSYNC

N44

VGA_VSYN C

U40

DAC_IREF

U39

VGA_IRTN

N36

EDP_BKL TCTL

K36

EDP_BKL TEN

G36

EDP_VDDE N

H20

PIRQA#

L20

PIRQB#

K17

PIRQC#

M20

PIRQD#

A12

GPIO50

B13

GPIO52

C12

GPIO54

C10

GPIO51

A10

GPIO53

AL6

GPIO55

DGPU_HOLD_RST#

PCH_PLTRST#

LY

NXPOINT_BGA695

+3VS

5

1

P

B

2

A

G

3

LPT_PCH_M_EV

0.1U_0402_25V6K~D

O

TC7SH08FU_SSOP5~D

LVDSC RT

CH147

1 2

4

PCI

UH6

5UH1E

DISPLAY

5 OF 11

PLTRST_VGA#

DDPB_CTRLCL K

DDPB_CTRLDA TA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPB_AUX N

DDPC_AUXN

DDPD_AUXN

DDPB_AUX P

DDPC_AUXP

DDPD_AUXP

DDPB_HPD

DDPC_HPD

DDPD_HPD

PIRQE#/G PIO2

PIRQF#/GP IO3

PIRQG#/G PIO4

PIRQH#/GP IO5

PCH_PLTRST#

+3V_MXM

RH215
100K_0402_5%~D

@

1 2

12

RH196
100K_0402_5%~D

PME#

PLTRST#

A16 SWAP OVERRIDE STRAP

STP_A16OVR

2012/06/22 2013/06/21

LOW = A16 SWAP OVERRIDE
HIGH = DEFAULT

Compal Secret Data

Deciphered Date

2

PCH_DPB_HDMI_CLK

R40

PCH_DPB_HDMI_DAT

R39

R35

R36

PCH_DPD_CLK

N40

PCH_DPD_DAT

N38

H45

K43

J42

H43

K45

J44

PCH_HDMI_HPD

K40

K38

PCH_DMC_HPD

H39

BT_ON#

G17

DP_CBL_DET

F17

ODD_DA#

L15

FFS_INT1

M15

AD10

PCH_PLTRST#

Y11

+3VS

5

1

P

B

2

A

G

3

PLTRST_VGA# <29>

1

PCH_DPB_HDMI_CLK <36>

PCH_DPB_HDMI_DAT <36>

PCH_DPD_CLK <39>

PCH_DPD_DAT <39>

PCH_HDMI_HPD <36>

PCH_DMC_HPD <39>

BT_ON# <51>

DP_CBL_DET <30>

ODD_DA# <50>

FFS_INT1 <49>

T124 PAD~D@

CH144

1 2

0.1U_0402_25V6K~D

PLT_RST

4

O

UH3

TC7SH08FU_SSOP5~D

Title

Size Document Number Rev

Custom

Date: Sheet of

+3VS

12

RH367
10K_0402_5%~D

@

PLT_RST# <6,43,44,51,53>

+3VS

12

RH3668.2K_0402_5%~D

12

RH3658.2K_0402_5%~D

12

RH3628.2K_0402_5%~D

12

RH3528.2K_0402_5%~D

12

RH3248.2K_0402_5%~D

12

RH3258.2K_0402_5%~D

12

RH3268.2K_0402_5%~D

12

RH3298.2K_0402_5%~D

12

RH32710K_0402_5%~D @

PM_CLKRUN#

BT_ON#

ODD_DA#

WL_OFF#

HDMI_IN_PWMSEL#

PCI_PIRQA#

PCI_PIRQB#

PCI_PIRQC#

PCI_PIRQD#

DGPU_HOLD_RST#

RH351 10K_0402_5%~D@

12

RH201
100K_0402_5%~D

1 2

Compal Electronics, Inc.

PCH (2/9) DMI,FDI,PM,DP,CRT

LA-9331P

1

18 61Friday, June 22, 2012

HDMI

DMC

0.1

5

D D

+3V_PCH

+3VS

+3VS

+3V_PCH

+3V_PCH

+3V_PCH

+3V_PCH

+3V_PCH

RH307 0_0402_5%~D

RH308 0_0402_5%~D
RH142 10K_0402_5%~D

RH99 0_0402_5%~D
RH98 0_0402_5%~D
RH145 10K_0402_5%~D

RH158 0_0402_5%~D

RH147 0_0402_5%~D

1 2

RH28 10K_0402_5%~D

RH129 0_0402_5%~D
RH124 0_0402_5%~D

RH126 10K_0402_5%~D

RH128 10K_0402_5%~D

RH132 10K_0402_5%~D

RH133 10K_0402_5%~D

RH127 10K_0402_5%~D

RH280 0_0402_5%~D

RH281 0_0402_5%~D

RH169 22_0402_5%~D

RH111 22_0402_5%~D

RH151 22_0402_5%~D

MiniWLAN (Mini Card 1)

DMC (Mini Card 2)

10/100/1G LAN

C C

B B

Card Reader

CLK_PCI_LPC<43>

CLK_PCIE_MINI1#<51>

CLK_PCIE_MINI1<51>

MINI1CLK_REQ#<51>

CLK_PCIE_MINI2#<51>

CLK_PCIE_MINI2<51>

MINI2CLK_REQ#<51>

CLK_PCIE_LAN#<44>

CLK_PCIE_LAN<44>

LANCLK_REQ#<44>

CLK_PCIE_CD#<53>

CLK_PCIE_CD<53>

CDCLK_REQ#<53>

CLK_CPU_ITP#<6>

CLK_CPU_ITP<6>

CLK_PCI_LPBACK CLK_PCI0

CLK_DEBUG<51>

CLK_PCI_LPC CLK_PCI1

4

LYNXPOINT_BGA695

LPT_PCH_M_EDS

2 OF 11

UH1C

12

12
12

12
12
12

12

12

12
12

12

12

12

12

12

12

12

12

12

12

PCIE_MINI1#

PCIE_MINI1

MINI1CLK_REQ#

PCIE_MINI2#
PCIE_MINI2

MINI2CLK_REQ#

PCIE_LAN#

PCIE_LAN

LANCLK_REQ#

PCIE_EXP#
PCIE_EXP
CDCLK_REQ#

CLK_BCLK_ITP#

CLK_BCLK_ITP

T142 PAD~D@

T138 PAD~D@

CLK_PCI2CLK_DEBUG

CLK_PCI3

CLK_PCI4

Y43

CLKOUT_PCIE _N_0

Y45

CLKOUT_PCIE _P_0

AB1

PCIECLKRQ 0#/GPIO73

AA44

CLKOUT_PCIE _N_1

AA42

CLKOUT_PCIE _P_1

AF1

PCIECLKRQ 1#/GPIO18

AB43

CLKOUT_PCIE _N_2

AB45

CLKOUT_PCIE _P_2

AF3

PCIECLKRQ 2#/GPIO20/ SMI#

AD43

CLKOUT_PCIE _N_3

AD45

CLKOUT_PCIE _P_3

T3

PCIECLKRQ 3#/GPIO25

AF43

CLKOUT_PCIE _N_4

AF45

CLKOUT_PCIE _P_4

V3

PCIECLKRQ 4#/GPIO26

AE44

CLKOUT_PCIE _N5

AE42

CLKOUT_PCIE _P_5

AA2

PCIECLKRQ 5#/GPIO44

AB40

CLKOUT_PCIE _N_6

AB39

CLKOUT_PCIE _P_6

AE4

PCIECLKRQ 6#/GPIO45

AJ44

CLKOUT_PCIE _N_7

AJ42

CLKOUT_PCIE _P_7

Y3

PCIECLKRQ 7#/GPIO46

AH43

CLKOUT_ITPXD P

AH45

CLKOUT_ITPXD P_P

D44

CLKOUT_33 MHZ0

E44

CLKOUT_33 MHZ1

B42

CLKOUT_33 MHZ2

F41

CLKOUT_33 MHZ3

A40

CLKOUT_33 MHZ4

CLOCK SIGNAL

3

5

CLKOUT_PE G_A

CLKOUT_PE G_A_P

PEGA_CL KRQ#/GPIO47

CLKOUT_PE G_B

CLKOUT_PE G_B_P

PEGB_CL KRQ#/GPIO56

CLKOUT_DMI

CLKOUT_DMI_ P

CLKOUT_DP

CLKOUT_DP_ P

CLKOUT_DPNS

CLKOUT_DPNS _P

CLKIN_DMI

CLKIN_DMI_ P

CLKIN_GND

CLKIN_GND _P

CLKIN_DOT96 N
CLKIN_DOT96 P

CLKIN_SA TA

CLKIN_SA TA_P

REFCLK14 IN

CLKIN_33 MHZLOOPBACK

XTAL25_IN

XTAL25_O UT

CLKOUTFLEX 0/GPIO64

CLKOUTFLEX 1/GPIO65

CLKOUTFLEX 2/GPIO66

CLKOUTFLEX 3/GPIO67

ICLK_IREF

DIFFCLK_B IASREF

TP19
TP18

AB35

AB36

AF6

Y39

Y38

U4

CLK_CPU_DMI#

AF39

CLK_CPU_DMI

AF40

CLK_CPU_SSC_DPLL#

AJ40

CLK_CPU_SSC_DPLL

AJ39

CLK_CPU_DPLL#

AF35

CLK_CPU_DPLL

AF36

CLK_BUF_DMI#

AY24

CLK_BUF_DMI

AW24

CLK_BUF_BCLK#

AR24

CLK_BUF_BCLK

AT24

CLK_BUF_DOT96#

H33

CLK_BUF_DOT96

G33

CLK_BUF_CKSSCD#

BE6

CLK_BUF_CKSSCD

BC6

CLK_PCH_14M

F45

CLK_PCI_LPBACK

D17

AL44
AM43

C40

DMC_PCH_DET#

F38

PCH_GPIO66

F36

CAM_DET#

F39

ICLK_IREF

AM45

AD39
AD38

PCH_CLK_BIASREF

AN44

CLK_PEG_PCH#

CLK_PEG_PCH

PEG_CLKREQ#

RH76 10K_0402_5%~D

XTAL25_IN
XTAL25_OUT

CAM_DET#

DMC_PCH_DET#

PCH_GPIO66

CLK_PEG_PCH# <29>

CLK_PEG_PCH <29>

PEG_CLKREQ# <29>

1 2

12

+3V_PCH

RH12510K_0402_5%~D

CLK_CPU_DMI# <6>

CLK_CPU_DMI <6>

CLK_CPU_SSC_DPLL# <6>
CLK_CPU_SSC_DPLL <6>

CLK_CPU_DPLL# <6>
CLK_CPU_DPLL <6>

T176PAD~D @

DMC_PCH_DET# <51>

CAM_DET# <33,42>

1 2

RH54 0_0402_5%

T149PAD~D @
T150PAD~D @

1 2

RH2087.5K_0402_1%~D

1 2

1 2

1 2

+3V_PCH

+1.5VS

+1.05V_+1.5V_RUN

RH21610K_0402_5%~D

RH21710K_0402_5%~D

RH21810K_0402_5%~D

2

CLK_BUF_DMI#
CLK_BUF_DMI

CLK_BUF_BCLK#
CLK_BUF_BCLK

CLK_BUF_DOT96#
CLK_BUF_DOT96

CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD

CLK_PCH_14M

RH74 10K_0402_5%~D

1 2

RH75 10K_0402_5%~D

1 2

RH105 10K_0402_5%~D

1 2

RH157 10K_0402_5%~D

1 2

RH143 10K_0402_5%~D

1 2

RH130 10K_0402_5%~D

1 2

RH146 10K_0402_5%~D

1 2

RH155 10K_0402_5%~D

1 2

RH205 10K_0402_5%~D

1 2

CLOCK TERMINATION for FCIM and need close to PCH

RH309 0_0402_5%~D

1 2

RH131 1M_0402_5%~D

YH4

25MHZ_10PF_Q22FA2380049900~D

3

8.2P_0402_50V8D~D

2

CH18

1

+3VS

OUT

4

GND

GND

1

12

IN

XTAL25_IN_R

1

2

8.2P_0402_50V8D~D

CH19

2

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PCH (3/9) CLK

ze Document Number Rev

Si

Custom

LA-9331P

Date: Sheet of

1

19 61Friday, June 22, 2012

0.1

5

D D

+3VS

1 2

RH337 10K_0402_5%~D

C C

B B

SERIRQ

LPC_AD0<43,51>

LPC_AD1<43,51>

LPC_AD2<43,51>

LPC_AD3<43,51>

LPC_FRAME#<43,51>

PANEL_SW<31,34>

SERIRQ<4 3>

LPC_AD0

LPC_AD1

LPC_AD2

LPC_AD3

LPC_FRAME#

PANEL_SW

SERIRQ

PCH_SPI_CLK

PCH_SPI_CS0#

PCH_SPI_SI

PCH_SPI_SO

PCH_SPI_DO2

PCH_SPI_DO3

A20

C20

A18

C18

B21

D21

G20

AL11

AJ11

AJ7

AL7

AJ10

AH1

AH3

AJ4

AJ2

4

MEM_SMBCLK

MEM_SMBDATA

UH1D

LAD_0

LAD_1

LAD_2

LAD_3

LFRAME#

LDRQ0#

LDRQ1#/GPIO23

SERIRQ

SPI_CLK

SPI_CS0#

SPI_CS1#

SPI_CS2#

SPI_MOSI

SPI_MISO

SPI_IO2

SPI_IO3

3

SML1CLK

+3VS

2

6 1

QH9A

5

3 4

LPT_PCH_M_EDS

SMBus

SPILPC

C-Link

Thermal

DMN66D0LDW-7_SOT363-6~D

QH9B
DMN66D0LDW-7_SOT363-6~D

SML0ALERT#/GPIO60

SML1ALERT#/PCHHOT#/GPIO74

+3VS

RH304

2.2K_0402_5%~D

SMBALERT#/GPIO11

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK/GPIO58

SML1DATA/GPIO75

CL_CLK

CL_DATA

CL_RST#

TD_IREF

12

TP1

TP2

TP4

TP3

12

RH310

2.2K_0402_5%~D

PCH_LID_SW_IN#

N7

MEM_SMBCLK

R10

MEM_SMBDATA

U11

DDR_HVREF_RST_PCH

N8

SML0CLK

U8

SML0DATA

R7

PCH_GPIO74

H6

SML1CLK

K6

SML1DATA

N11

AF11

AF10

AF7

BA45

BC45

BE43

BE44

PCH_TD_IREF

AY43

RH322 8.2K_0402_1%

PCH_SMBCLK <6 ,12,13,14,15,49,50,51,53>

RH368 0_0402_5%~D

RH369 0_0402_5%~D

1 2

SML1DATA

PCH_SMBDATA <6,12,13,14,15,49,50,51,53>

1 2

1 2

@

T130PAD~D @

T133PAD~D @

T131PAD~D @

T132PAD~D @

3 4

EC_LID_OUT# <43>

LID_SW_IN# <43,47,48,53>

2

+3VS

2

6 1

QH10A

5

DMN66D0LDW-7_SOT363-6~D

QH10B
DMN66D0LDW-7_SOT363-6~D

EC_SMB_CK2 <40,43,53,54>

EC_SMB_DA2 <40,43,53,54>

MEM_SMBCLK

MEM_SMBDATA

DDR_HVREF_RST_PCH

PCH_GPIO74

SML1CLK

SML1DATA

SML0CLK

SML0DATA

1 2

1 2

1

+3V_PCH

12

RH3022.2K_0402_5%~D

12

RH3032.2K_0402_5%~D

12

RH3001K_0402_1%~D

12

RH30110K_0402_5%~D

RH2982.2K_0402_5%~D

RH2992.2K_0402_5%~D

+3V_PCH

12

RH3052.2K_0402_5%~D

12

RH3062.2K_0402_5%~D

VCC

/HOLD

CLK

3 OF 11 5

+3V_PCH

8

7

PCH_SPI_CLK_RPCH_SPI_DO2_R

6

PCH_SPI_SI_R

5

DIO

CH56

1 2

0.1U_0402_25V6K~D

RH374 33_0402_5%~D

1 2

RH376 33_0402_5%~D

1 2

RH377 33_0402_5%~D

1 2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

Issued Date

PCH_SPI_DO3PCH_SPI_DO3_R

PCH_SPI_CLK

PCH_SPI_SI

2012/06/22 2013/06/21

3

Compal Secret Data

Deciphered Date

PCH_SPI_CLK

RH60

@

33_0402_5%~D

1 2

22P_0402_50V8J~D

1

@

CH8

2

Reserve for EMI please
close to UH14

2

Title

PCH (4/9) SPI, SMBUS,LPC

ze Document Number Rev

Si

Custom

LA-9331P

Date: Sheet of

1

20 61Friday, June 22, 2012

0.1

LY

NXPOINT_BGA695

+3V_PCH

1 2

RH370 3.3K_0402_5%~D

1 2

RH371 3.3K_0402_5%~D

PCH_SPI_CS0# PCH_SPI_CS 0#_R

PCH_SPI_SO PCH_SPI_SO_R

PCH_SPI_DO2

PCH_SPI_DO3_R

PCH_SPI_DO2_R

RH373 0_0402_5%~D

1 2

RH372 33_0402_5%~D

1 2

RH375 33_0402_5%~D

1 2

+3V_PCH

3.3K_0402_5%

1 2

@

RH58

200 MIL SO8

64Mb Flash ROM

UH14

1

/CS

2

DO

3

/WP

4

GND

64M EN25Q64-104HIP_SO8

EON

A A

5

4

5

D D

4

3

2

1

UH1I

AW31

PERN1/USB 3RN3

AY31

PERP1/US B3RP3

BE32

PETN1/USB3 TN3

BC32

PETP1/USB 3TP3

AT31

PERN2/USB 3RN4

AR31

PERP2/US B3RP4

BD33

PETN2/USB3 TN4

BB33

PCIE_PRX_GLANTX_N1<44>

10/100/1G LAN

CARD READER

C C

B B

PCIE_PRX_GLANTX_P1<44>

PCIE_PTX_GLANRX_N1<44>
PCIE_PTX_GLANRX_P1<44>

PCIE_PRX_CARDTX_N4<53>
PCIE_PRX_CARDTX_P4<53>

PCIE_PTX_CARDRX_N4<53>
PCIE_PTX_CARDRX_P4<53>

CH149 0.1U_0402_25V6K~D

1 2

CH150 0.1U_0402_25V6K~D

1 2

CH153 0.1U_0402_25V6K~D

1 2

CH154 0.1U_0402_25V6K~D

1 2

+1.5VS

+1.5VS

PCIE_PRX_GLANTX_N1
PCIE_PRX_GLANTX_P1

PCIE_PTX_GLANRX_N1_C
PCIE_PTX_GLANRX_P1_C

PCIE_PRX_CARDTX_N4
PCIE_PRX_CARDTX_P4

PCIE_PTX_CARDRX_N4_C
PCIE_PTX_CARDRX_P4_C

PCH_PCIE_IREF

1 2

RH51 0_0402_5%

T134 PAD~D@

T136 PAD~D@

PCH_PCIE_RCOMP

1 2

RH210 7.5K_0402_1%~D

AW33

AW36

AW38

AY33

BE34
BC34

AT33
AR33

BE36
BC36

AV36

BD37
BB37

AY38

BC38
BE38

AT40
AT39

BE40
BC40

AN38
AN39

BD42
BD41

BE30

BC30

BB29

BD29

PETP2/USB 3TP4

PERN_3
PERP_3

PETN_3
PETP_3

PERN_4
PERP_4

PETN_4
PETP_4

PERN_5
PERP_5

PETN_5
PETP_5

PERN_6
PERP_6

PETN_6
PETP_6

PERN_7
PERP_7

PETN_7
PETP_7

PERN_8
PERP_8

PETN_8
PETP_8

PCIE_IREF

TP11

TP6

PCIE_RCOM P

LPT_PCH_M_EDS

LYNXPOINT_BGA695

PCIe

USB

9 OF 11 5

USB2N0
USB2P0
USB2N1
USB2P1
USB2N2
USB2P2
USB2N3
USB2P3
USB2N4
USB2P4
USB2N5
USB2P5
USB2N6
USB2P6
USB2N7
USB2P7
USB2N8
USB2P8
USB2N9

USB2P9
USB2N10
USB2P10
USB2N11
USB2P11
USB2N12
USB2P12
USB2N13
USB2P13

USB3RN1
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USB3RN5
USB3RP5
USB3TN5
USB3TP5
USB3RN6
USB3RP6
USB3TN6
USB3TP6

USBRBIAS #

USBRBIAS

OC0#/GPI O59
OC1#/GPI O40
OC2#/GPI O41
OC3#/GPI O42
OC4#/GPI O43

OC5#/GPI O9
OC6#/GPI O10
OC7#/GPI O14

USB20_N0

B37

USB20_P0

D37

USB20_N1

A38

USB20_P1

C38

USB20_N2

A36

USB20_P2

C36

USB20_N3

A34

USB20_P3

C34

USB20_N4

B33

USB20_P4

D33

USB20_N5

F31

USB20_P5

G31

USB20_N6

K31

USB20_P6

L31

USB20_N7

G29

USB20_P7

H29
A32
C32
A30
C30
B29
D29

USB20_N11

A28

USB20_P11

C28

USB20_N12

G26

USB20_P12

F26

USB20_N13

F24

USB20_P13

G24

USB3RN1

AR26

USB3RP1

AP26

USB3TN1

BE24

USB3TP1

BD23

USB3RN2

AW26

USB3RP2

AV26

USB3TN2

BD25

USB3TP2

BC24

USB3RN5

AW29

USB3RP5

AV29

USB3TN5

BE26

USB3TP5

BC26

USB3RN6

AR29

USB3RP6

AP29

USB3TN6

BD27

USB3TP6

BE28

USBRBIAS

K24
K26

M33

TP24

L33

TP23

USB_OC0#

P3

USB_OC1#

V1

USB_OC2#

U2
P1

USB_OC4#

M3

USB_OC5#

T1

USB_OC6#

N2

USB_OC7#

M1

USB20_N0 <52>
USB20_P0 <52>
USB20_N1 <52>
USB20_P1 <52>
USB20_N2 <53>
USB20_P2 <53>
USB20_N3 <53>
USB20_P3 <53>
USB20_N4 <51>
USB20_P4 <51>
USB20_N5 <51>
USB20_P5 <51>
USB20_N6 <47>
USB20_P6 <47>
USB20_N7 <55>
USB20_P7 <55>

USB20_N11 <33>
USB20_P11 <33>
USB20_N12 <42>
USB20_P12 <42>
USB20_N13 <53>
USB20_P13 <53>

USB3RN1 <52>
USB3RP1 <52>

USB3TN1 <52>

USB3TP1 <52>
USB3RN2 <52>
USB3RP2 <52>

USB3TN2 <52>

USB3TP2 <52>
USB3RN5 <53>
USB3RP5 <53>

USB3TN5 <53>

USB3TP5 <53>
USB3RN6 <53>
USB3RP6 <53>

USB3TN6 <53>

USB3TP6 <53>

T135PAD~D @
T137PAD~D @

USB_OC0# <52>
USB_OC1# <52>
USB_OC2# <53>
USB_OC3# <53>

JUSB1

JUSB2

JUSB3

JUSB4

Mini Card(WLAN)

Mini Card(DMC)

ELC LED

IR sensor

eDP Camera

LVDS Camera

VPK K/B

P1: JUSB1

P2: JUSB2

P5: JUSB3

P6: JUSB4

USBRBIAS

22.6_0402_1%~D

12

RH160

CAD NOTE:
Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15 mils.

+3V_PCH

USB_OC0#
USB_OC1#USB_OC3#
USB_OC3#
USB_OC4#

USB_OC5#
USB_OC6#
USB_OC7#
USB_OC2#

RPH1

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%~D

RPH2

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%~D

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PCH (5/9) PCIE,USB

ze Document Number Rev

Si

Custom

LA-9331P

Date: Sheet of

1

21 61Friday, June 22, 2012

0.1

5

4

3

2

1

D D

C C

B B

+3VS

1 2

RH270 10K_0402_5%~D

1 2

RH271 10K_0402_5%~D

1 2

RH164 10K_0402_5%~D

RH179 10K_0402_5%~D

1 2

RH267 10K_0402_5%~D

1 2

RH57 20K_0402_5%~D

1 2

RH256 10K_0402_5%~D

1 2

RH257 10K_0402_5%~D

1 2

RH258 10K_0402_5%~D

+3V_PCH

RH187 10K_0402_5%~D

1 2

RH354 1K_0402_1%~D

RH182 10K_0402_5%~D

RH264 10K_0402_5%~D

RH269 10K_0402_5%~D@

+3V_PCH

4.7K_0402_5%~D

RH53

1 2

PCH_GPIO28

1K_0402_1%~D

12

@

RH353

PLL ON DIE VR ENABLE

ENABLED - HIGH(DEFAULT)
DISABLED - LOW

DMC_RADIO_OFF#

DGPU_EDIDSEL#

DGPU_HPD_INT#

STP_PCI#

12

VGA_PRSNT_R# EC_SCI#

VGA_PRSNT_L#

PCH_GPIO22

LVDS_CAB_DET#

EDP_CAB_DET#

HDD_DET#

12

PCH_GPIO15

ODD_EN#

12

PCH_GPIO35

12

PCH_GPIO27

12

+3VS

RH272 10K_0402_5%~D@

RH266 10K_0402_5%~D

RH265 10K_0402_5%~D

RH268 10K_0402_5%~D@

1 2

DMC_RADIO_OFF#<51>

DGPU_EDIDSEL#<32,36,42>

DGPU_HPD_INT#<36,39>

EC_SCI#<43>

EC_SMI#<43>

EDP_DETECT#<41>

ODD_EN#<50>

PCH_GPIO35<36>

ODD_DETECT#<50>

VGA_PRSNT_R#<29>

VGA_PRSNT_L#<29>

FFS_INT2<49,50>

HDD_DET#< 49>

DGPU_BKL_PWM_SEL#<42>

EDP_CAB_DET#<33>

LVDS_CAB_DET#<42>

WiGi_RADIO_DIS#<51>

1 2

RH162 0_0402_5%~D

PCH_GPIO16

PCH_GPIO49

12

PCH_GPIO16

12

PCH_GPIO49

12

DMC_RADIO_OFF#

DGPU_EDIDSEL#

DGPU_HPD_INT#

EC_SMI#

EDP_DETECT#

PCH_GPIO15

PCH_GPIO16

PCH_GPIO22

ODD_EN#

PCH_GPIO27

PCH_GPIO28

STP_PCI#

PCH_GPIO35

ODD_DETECT#

PCH_GPIO37

VGA_PRSNT_R#

VGA_PRSNT_L#

FFS_INT2

PCH_GPIO49

HDD_DET#

DGPU_BKL_PWM_SEL#

EDP_CAB_DET#EDP_CAB_DET#

LVDS_CAB_DET#

WiGi_RADIO_DIS#

TP_VSS_NCTF

UH1F

AT8

BMBUSY#/GP IO0

F13

TACH1/GPIO1

A14

TACH2/GPIO6

G15

TACH3/GPIO7

Y1

GPIO8

K13

LAN_PHY_P WR_CTRL/GPI O12

AB11

GPIO15

AN2

SATA4GP/G PIO16

C14

TACH0/GPIO1 7

BB4

SCLOCK/G PIO22

Y10

GPIO24

R11

GPIO27

AD11

GPIO28

AN6

GPIO34

AP1

GPIO35/N MI#

AT3

SATA2GP/G PIO36

AK1

SATA3GP/G PIO37

AT7

SLOAD/GP IO38

AM3

SDATAOUT0/GP IO39

AN4

SDATAOUT1/GP IO48

AK3

SATA5GP/G PIO49

U12

GPIO57

C16

TACH4/GPIO6 8

D13

TACH5/GPIO6 9

G13

TACH6/GPIO7 0

H15

TACH7/GPIO7 1

BE41

VSS

BE5

VSS

C45

VSS

A5

VSS

NXPOINT_BGA695

LY

LPT_PCH_M_EDS

GPIO

NCTF

6 OF 11 5

CPU/Misc

PROCPW RGD

THRMTRIP#

PLTRST_PROC#

TP14

RCIN#

GATEA20

KB_RST#

GATEA20

AN10

RH184

AY1

AT6

AV3

AV1

AU4

N10

A2
A41
A43
A44
B1
B2
B44
B45
BA1
BC1
BD1
BD2
BD44
BD45
BE2
BE3
D1
E1
E45
A4

@

KB_RST#

H_CPUPWRGD

PCH_THRMTRIP#_R

CPU_PLTRST#

PCH_VSS_A44

PCH_VSS_B45

PCH_VSS_BD1

PECI

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

12

0_0402_5%~D

GATEA20 <43>

H_PECI <6, 43>

KB_RST# <43>

H_CPUPWRGD <6>

CPU_PLTRST# <6>

1 2

0_0402_5%~D

0_0402_5%~D

RH262390_0402_5%

@

RH166

RH165

H_THERMTRIP# <6>

1 2

PCH_VSS_A44

1 2

0_0402_5%~D

0_0402_5%~D

+5VALW+5VS

@

RH175

RH168

12

RH16110K_0402_5%~D

12

RH20310K_0402_5%~D

1 2

PCH_VSS_B45

1 2

+3VS

PCH_VSS_BD1

0_0402_5%~D

RH170

1 2

Config

USB X4,PCIEX8,SATAX6

*

A A

5

GPIO16,49

11

01USB X6,PCIEX8,SATAX4

SATA2GP/GPIO36 , SATA3GP/GPIO37 SAMPLED AT RISING EDGE OF PWROK.
WEAK INTERNAL PULL-DOWN.(WEAK INTERNAL PULL-DOWN IS DISABLED AFTER
PLRST_N DE-ASSERTS).
NOTE: THIS SIGNAL SHOLD NOT BE PULLED HIGH WHEN STRAP IS SAMPLED.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/06/22 2013/06/21

+3VS

1 2

RH176 200K_0402_5%

1 2

RH171 200K_0402_5%@

RH174 10K_0402_5%~D@

RH181 10K_0402_5%~D

Compal Secret Data

Deciphered Date

2

12

12

ODD_DETECT#

PCH_GPIO37

ODD_DETECT#

PCH_GPIO37

Compal Electronics, Inc.

Title

PCH (6/9) GPIO,MISC,NTFC

ze Document Number Rev

Si

Custom

LA-9331P

Date: Sheet of

1

22 61Friday, June 22, 2012

0.1

5

D D

4

3

2

1

BLM18PG181SN1_0603~D

10U_0603_6.3V6M~D

1

CH156

2

+1.05VS

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CH46

CH45

2

LH1

12

+3V_PCH

0.1U_0402_10V7K~D

1

2

+1.05V_+1.5V_RUN

1

2

10U_0603_6.3V6M~D

1

CH44

2

1 2

+3VS

0.1U_0402_10V7K~D

1

2

CH60

+1.05V_+1.5V_RUN

1

10U_0603_6.3V6M~D

2

@

CH85

+PCH_USB_DCPSUS3

1

2

RH2110_0603_5%~D

+1.05V_+1.5V_RUN

+1.05VS

1U_0402_6.3V6K~D

1

CH48

2

CH38

+1.05V_+1.5V_RUN

10U_0603_6.3V6M~D

1

10U_0603_6.3V6M~D

2

@

CH83

+PCH_USB_DCPSUS1

1U_0402_6.3V6K~D

1

2

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

@

1

CH40

2

+1.5VS

10U_0603_6.3V6M~D

@

1

CH81

2

@

CH82

+1.05V

12

1 2

RH3600_0402_5%~D @

+1.05V

RH2090_0603_5%~D @

@

CH61

@

CH39

+VCCADAC

0.1U_0402_10V7K~D

0.01U_0402_16V7K~D

1

1

CH80

CH57

2

2

LPT_PCH_M_EDS

CRT DAC

FDI

HVCMOS

Core

USB3

PCIe/DMI

SATA

VCCMPHY

LY

NXPOINT_BGA695

+1.5VS +1.05V_+1.5V_RUN

7 OF 11 5

RH197 0_0603_5%~D

RH198 0_0603_5%~D@

VCCADAC1_ 5

VSS

VCCADACBG 3_3

VCCVRM

VCCIO

VCCIO

VCC3_3_R 30
VCC3_3_R 32

DCPSUS1

VCCSUS3_ 3
VCCSUS3_ 3

DCPSUS3
DCPSUS3

VCCIO
VCCVRM
VCCVRM

VCCVRM

VCCIO

VCCVRM

VCCIO

VCCIO

VCCIO

VCCIO

VCCIO

VCCIO

VCCIO

12

12

P45

P43

M31

BB44

AN34

AN35

R30
R32

+PCH_USB_DCPSUS1

Y12

AJ30
AJ32

+PCH_USB_DCPSUS3

AJ26
AJ28
AK20
AK26
AK28

BE22

AK18

AN11

AK22

AM18
AM20
AM22
AP22
AR22
AT22

+3VS

+1.05VS

+1.05VS

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

1

CH86

CH47

2

2

2

AA24
AA26
AD20
AD22
AD24
AD26
AD28
AE18
AE20
AE22
AE24
AE26
AG18
AG20
AG22
AG24

AA18

Y26

U14

U18
U20
U22
U24
V18
V20
V22
V24
Y18
Y20
Y22

UH1G

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

DCPSUSBYP
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW

+1.05VS

C C

B B

+1.05VS

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

1

1

2

+1.05V

+PCH_VCCDSW_R

1

CH33

CH31

CH32

CH30

2

2

2

1

2

1U_0402_6.3V6K~D

CH35

+PCH_VCCDSW

1U_0402_6.3V6K~D

1

CH36

2

+PCH_VCCDSW

22U_0805_6.3V6M~D

1

CH64

2

C_0805NEW

1 2

RH37 5.11_0402_1%~D@

1U_0402_6.3V6K~D

@

CH34

2

PCH Power Rail Table

Voltage Rail

VCCADAC1_5 1.5V 0.070 A

VCCADAC3_3 0.0133 A3.3V

VCCCLK3_3 0.055 A

VCCSUSHDA 3.3V 0.01 A

VCCSUS3_3 3.3V 0.261 A

VCCDSW3_3 3.3V 0.015 A

V_PROC_IO 1.05V 0.004 A

Voltage S0 Iccmax Current (A)

VCC 1.05V 1.29 A

VCCIO 1.05V 3.629 A

VCCCLK 0.306 A1.05V

3.3V

VCCVRM 0.179 A1.5V

VCC3_3 3.3V 0.133 A

VCCASW 1.05V 0.67 A

VCCSPI 3.3V 0.022 A

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PCH (7/9) Power

Size Document Number Rev

Custom

LA-9331P

Date: Sheet of

1

23 61Friday, June 22, 2012

0.1

5

4

3

2

1

D D

LY

NXPOINT_BGA695

LPT_PCH_M_EDS

USB

ICC

8 OF 11 5

Fuse

Thermal

GPIO/LPC

Azalia

RTC

CPU

SPI

VCCSUS3_ 3
VCCSUS3_ 3

VCCDSW3 _3

DCPSST

VCC3_3
VCC3_3
VCC3_3

VCCIO

VCCSUSHDA

VCCSUS3_ 3

VCCRTC

DCPRTC
DCPRTC

V_PROC_I O
V_PROC_I O

VCCSPI

VCCASW

VCCASW

VCCVRM

VCC3_3

VCC3_3

+3V_PCH

R20
R22

+PCH_VCCDSW3_3

A16

+PCH_VCCSST

AA14

AE14
AF12
AG14

U36

CH84 0.1U_0402_10V7K~D

+1.05VS

A26

K8

A6

+PCH_DCPRTC

P14
P16

+PCH_VPROC

AJ12
AJ14

AD12

+PCH_VCCCFUSE

P18

VCC

P20

VCC

L17

R18

AW40

AK30

AK32

+1.05V

+1.5VS

AF34

AP45

AD34

AA30
AA32

AD35

AG30
AG32

AD36

AE30
AE32

M24

M29

M26

R24
R26
R28
U26

U35

L24

U30
V28
V30
Y30

Y35

Y32

L29

L26

U32
V32

UH1H

VCCSUS3_ 3
VCCSUS3_ 3
VCCSUS3_ 3
VCCSUS3_ 3

VSS

VCCUSBPL L

VCC3_3

VCCIO
VCCIO
VCCIO
VCCIO

DCPSUS2

VCCVRM

VCC

VCCCLK

VCCCLK3_ 3

VCCCLK3_ 3

VCCCLK3_ 3
VCCCLK3_ 3

VCCCLK3_ 3
VCCCLK3_ 3

VCCCLK

VCCCLK
VCCCLK

VCCCLK

VCCCLK
VCCCLK

VCCCLK

VCCCLK
VCCCLK

+3V_PCH

0.1U_0402_10V7K~D

+1.05VS

1

CH66

0.1U_0402_10V7K~D

2

+1.05V

RH361 0_0402_5%~D@

C C

1 2

+PCH_USB_DCPSUS2

+3VS

1

CH62

0.1U_0402_10V7K~D

2

1U_0402_6.3V6K~D

@

1

CH87

+1.05VS

CH63

1

2

1

2

1U_0402_6.3V6K~D

CH37

+1.05V_+1.5V_RUN

1

2

10U_0603_6.3V6M~D

CH42

+PCH_VCCCLK3_3

+PCH_USB_DCPSUS2

+PCH_VCC

+PCH_VCCCLK

2

+PCH_VCCCLK

+1.05VS_VCC+1.05VS

LH100

1 2

4.7UH_LQM18FN4R7M00D_20%~D

1 2

RH207 0_0603_5%~D

+PCH_VCC+PCH_VCC

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

CH51

CH55

1

1

2

2

Place near pin AP45

B B

+1.05VS

1 2

RH214 0_0805_5%~D

+PCH_VCCCLK

1

2

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

@

CH49

CH43

1

2

1U_0402_6.3V6K~D

CH50

1

2

1U_0402_6.3V6K~D

CH77

1

2

1U_0402_6.3V6K~D

CH78

1

2

1U_0402_6.3V6K~D

CH79

1

2

1 2

CH70

1 2

0.1U_0402_10V7K~D

+3V_PCH

+PCH_VCCDSW3_3

0.1U_0402_10V7K~D

1

2

0.1U_0402_10V7K~D

1

2

1U_0402_6.3V6K~D

1

CH74

2

+3VS

0.1U_0402_10V7K~D

1

CH76

2

12

+3V_PCH

RH2130_0402_5%~D @

12

+3VALW

CH155

+3V_PCH

+RTC_CELL

1U_0402_6.3V6K~D

0.1U_0402_10V7K~D

1

1

CH69

CH68

2

2

+PCH_VPROC

0.1U_0402_10V7K~D

1

2

+PCH_VCCCFUSE

RH2530_0402_5%~D

+3VS

+3V_PCH

1U_0402_6.3V6K~D

1

CH59

0.1U_0402_10V7K~D

1

CH65

2

0.1U_0402_10V7K~D

1

CH90

2

2

CH67

+1.05VS

12

12

12

RH2190_0805_5%~D

RH2200_0805_5%~D

RH2210_0805_5%~D @

+3VS

+1.05VS

0.1U_0402_10V7K~D

1U_0402_6.3V6K~D

1

1

CH72

CH73

1

CH71

2

2

1U_0402_6.3V6K~D

CH75

2

Place near pin AP45 Place near pin Y32,AA30,AA32 Place near pin AD34 Place near pin AD35,AD36 Place near pin AG30,AG32,AE30,AE32

+3VS

1 2

RH212 0_0805_5%~D

A A

+PCH_VCCCLK3_3

1U_0402_6.3V6K~D

CH52

1

2

1U_0402_6.3V6K~D

CH54

1

2

1U_0402_6.3V6K~D

CH53

1

2

1U_0402_6.3V6K~D

CH58

1

2

Place near pin M29 Place near pin L29 Place near pin L26,M26 Place near pin U32,V32

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PCH (8/9) Power

Size Document Number Rev

Custom

LA-9331P

Date: Sheet

1

of

24 61Friday, June 22, 2012

0.1

5

D D

4

3

2

1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AJ6

VSS

AJ8

VSS
VSS
VSS
VSS
VSS
VSS

AL2

VSS
VSS
VSS

LY

LPT_PCH_M_EDS

UH1K

NXPOINT_BGA695

B19

VSS

B23

VSS

B27

VSS

B31

VSS

B35

VSS

B39

VSS

B7

VSS

BA40

VSS

BD11

VSS

BD15

VSS

BD19

VSS

AY36

VSS

AT43

VSS

BD31

VSS

BD35

VSS

BD39

VSS

BD7

VSS

D25

VSS

AV7

VSS

F15

VSS

F20

VSS

F29

VSS

F33

VSS

BC16

VSS

D4

VSS

G2

VSS

G38

VSS

G44

VSS

G8

VSS

H10

VSS

H13

VSS

H17

VSS

H22

VSS

H24

VSS

H26

VSS

H31

VSS

H36

VSS

H40

VSS

H7

VSS

K10

VSS

K15

VSS

K20

VSS

K29

VSS

K33

VSS

BC28

VSS

511 OF 11

LPT_PCH_M_EDS

UH1J

AL34

VSS

AL38

VSS

AL8

VSS

AM14

VSS

AM24

VSS

AM26

VSS

AM28

VSS

AM30

VSS

AM32

VSS

AM16

VSS

AN36

VSS

AN40

VSS

AN42

VSS

AN8

VSS

AP13

C C

B B

AP24
AP31
AP43

AR2
AK16
AT10
AT15
AT17
AT20
AT26
AT29
AT36
AT38

AV13
AV22
AV24
AV31
AV33
BB25
AV40

AV6

AW2

AY10
AY15
AY20
AY26
AY29

D42

F43

AY7
B11
B15

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

LY

NXPOINT_BGA695

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

K39
L2
L44
M17
M22
N12
N35
N39
N6
P22
P24
P26
P28
P30
P32
R12
R14
R16
R2
R34
R38
R44
R8
T43
U10
U16
U28
U34
U38
U42
U6
V14
V16
V26
V43
W2
W44
Y14
Y16
Y24
Y28
Y34
Y36
Y40
Y8

510 OF 11

AA16
AA20
AA22
AA28

AA4
AB12
AB34
AB38

AB8

AC2
AC44
AD14
AD16
AD18
AD30
AD32
AD40

AD6

AD8
AE16
AE28
AF38

AF8
AG16

AG2
AG26
AG28
AG44

AJ16
AJ18
AJ20
AJ22
AJ24
AJ34
AJ38

AK14
AK24
AK43
AK45

AL12

BC22
BB42

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PCH (9/9) Power

Size Document Number Rev

Custom

LA-9331P

2

Date: Sheet of

1

25 61Friday, June 22, 2012

0.1

5

4

3

2

1

+3V_MXM

PEG_HTX_C_GRX_N[0..15]

PEG_HTX_C_GRX_P[0..15]

PEG_GTX_HRX_N[0..15]

PEG_GTX_HRX_P[0..15]

+5V_MXM

12

0.1U_0402_16V4Z~D

10U_0603_6.3V6M~D

1

1

CV6

2

2

100mil(2.5A, 5VIA)

RV78 0_0402_5%~D

1 2

VGA_HDMI_CEC

VGA_LCD_DAT
VGA_LCD_CLK

RV93 0_0402_5%~D

1 2

PEG_GTX_HRX_N15
PEG_GTX_HRX_P15

PEG_GTX_HRX_N14
PEG_GTX_HRX_P14

PEG_GTX_HRX_N13
PEG_GTX_HRX_P13

PEG_GTX_HRX_N12
PEG_GTX_HRX_P12

PEG_GTX_HRX_N11
PEG_GTX_HRX_P11

PEG_GTX_HRX_N10
PEG_GTX_HRX_P10

PEG_GTX_HRX_N9
PEG_GTX_HRX_P9

PEG_GTX_HRX_N8
PEG_GTX_HRX_P8

PEG_GTX_HRX_N7
PEG_GTX_HRX_P7

PEG_GTX_HRX_N6
PEG_GTX_HRX_P6

PEG_GTX_HRX_N5
PEG_GTX_HRX_P5

PEG_GTX_HRX_N4
PEG_GTX_HRX_P4

PEG_GTX_HRX_N3
PEG_GTX_HRX_P3

1 2

CV12

@

.1U_0402_16V7K~D

1 2

CV7

+5V_MXM

VGA_DISABLE#

+3V_MXM

VGA_LCD_CLK

RV63 4.3K_0402_5%

VGA_LCD_DAT
DGPU_PWROK
VGA_HDMI_CEC
VGA_DISABLE#

E1 E2

E3 E4

VGA_WAKE#

PWR_SR C
PWR_SR C
PWR_SR C
PWR_SR C
PWR_SR C
PWR_SR C
PWR_SR C
PWR_SR C
PWR_SR C

PRSNT_R#

PWR_GO OD

PWR_EN

PWR_LE VEL

TH_OVERT#

TH_ALERT#

TH_PWM

SMB_DAT
SMB_CLK

PEX_TX15 #

PEX_TX15

PEX_TX14 #

PEX_TX14

PEX_TX13 #

PEX_TX13

PEX_TX12 #

PEX_TX12

PEX_TX11 #

PEX_TX11

PEX_TX10 #

PEX_TX10

PEX_TX9#

PEX_TX9

PEX_TX8#

PEX_TX8

PEX_TX7#

PEX_TX7

PEX_TX6#

PEX_TX6

PEX_TX5#

PEX_TX5

PEX_TX4#

PEX_TX4

PEX_TX3#

PEX_TX3

B+_MXM

JMXM1A

1

PWR_SR C

3

PWR_SR C

5

PWR_SR C

7

PWR_SR C

9

PWR_SR C

11

PWR_SR C

13

PWR_SR C

15

PWR_SR C

17

PWR_SR C

19

GND

21

GND

23

GND

25

GND

27

GND

29

GND

31

GND

33

GND

35

GND

37

5V

39

5V

41

5V

43

5V

45

5V

47

GND

49

GND

51

GND

53

GND

55

PEX_STD_S W#

57

VGA_DISA BLE#

59

PNL_PW R_EN

61

PNL_BL_ EN

63

PNL_BL_ PWM

65

HDMI_CEC

67

DVI_HPD

69

LVDS_DDC_ DAT

71

LVDS_DDC_ CLK

73

GND

75

OEM

77

OEM

79

OEM

81

OEM

83

GND

85

PEX_RX1 5#

87

PEX_RX1 5

89

GND

91

PEX_RX1 4#

93

PEX_RX1 4

95

GND

97

PEX_RX1 3#

99

PEX_RX1 3

101

GND

103

PEX_RX1 2#

105

PEX_RX1 2

107

GND

109

PEX_RX1 1#

111

PEX_RX1 1

113

GND

115

PEX_RX1 0#

117

PEX_RX1 0

119

GND

121

PEX_RX9 #

123

PEX_RX9

125

GND

127

PEX_RX8 #

129

PEX_RX8

131

GND

133

PEX_RX7 #

135

PEX_RX7

137

GND

139

PEX_RX6 #

141

PEX_RX6

143

GND

145

PEX_RX5 #

147

PEX_RX5

149

GND

151

PEX_RX4 #

153

PEX_RX4

155

GND

157

PEX_RX3 #

159

PEX_RX3

161

GND

JAE_MM70-314-310B1-1-R300

CONN@

1

2

UV5

1

VIN+

2

VIN-

3

SDA

GND

4

SCL

VS

HPA00900AIDCNR_SOT23-8

8

A1

7

A0

6
5

1 2

RV65 4.3K_0402_5%

1 2

RV67

RV68 10K_0402_5%~D

1 2

RV69 10K_0402_5%~D@

1 2

RV75 10K_0402_5%~D@

1 2

2
4
6
8
10
12
14
16
18

20

GND

22

GND

24

GND

26

GND

28

GND

30

GND

32

GND

34

GND

36

GND

38
40

WAKE#

42
44
46

RSVD

48

RSVD

50

RSVD

52

RSVD

54
56
58
60
62

GPIO0

64

GPIO1

66

GPIO2

68
70
72

GND

74

OEM

76

OEM

78

OEM

80

OEM

82

GND

84
86
88

GND

90
92
94

GND

96
98
100

GND

102
104
106

GND

108
110
112

GND

114
116
118

GND

120
122
124

GND

126
128
130

GND

132
134
136

GND

138
140
142

GND

144
146
148

GND

150
152
154

GND

156
158
160

GND

For B+_MXM
slave address : 1000010
please placemnet near R-sense

B+_MXM_A1
B+_MXM_A0
MXM_CURI2C_DATA
MXM_CURI2C_CLK

10K_0402_5%~D

12

400mil(10A)

10U_1206_25V6M~D

1

CV1

2

VGA_PRSNT_R#
VGA_WAKE#
DGPU_PWROK
DGPU_PWR_EN

AC_BATT#
VGA_TH_OVERT#

VGA_SMB_DA1
VGA_SMB_CK1

SYSTEM

VGA_PS_0
VGA_PS_1
VGA_PS_2

PEG_HTX_C_GRX_N15
PEG_HTX_C_GRX_P15

PEG_HTX_C_GRX_N14
PEG_HTX_C_GRX_P14

PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_P13

PEG_HTX_C_GRX_N12
PEG_HTX_C_GRX_P12

PEG_HTX_C_GRX_N11
PEG_HTX_C_GRX_P11

PEG_HTX_C_GRX_N10
PEG_HTX_C_GRX_P10

PEG_HTX_C_GRX_N9
PEG_HTX_C_GRX_P9

PEG_HTX_C_GRX_N8
PEG_HTX_C_GRX_P8

PEG_HTX_C_GRX_N7
PEG_HTX_C_GRX_P7

PEG_HTX_C_GRX_N6
PEG_HTX_C_GRX_P6

PEG_HTX_C_GRX_N5
PEG_HTX_C_GRX_P5

PEG_HTX_C_GRX_N4
PEG_HTX_C_GRX_P4

PEG_HTX_C_GRX_N3
PEG_HTX_C_GRX_P3

MXM_CURI2C_CLK
MXM_CURI2C_DATA

AC_BATT#

B+_MXM

68P_0402_50V8J~D

680P_0603_50V7K~D

CV2

1

1

2

CV3

2

2

1

EC_AC_BAT#<43>

VGA_PRSNT_R# <21>

DGPU_PWROK <30,43>
DGPU_PWR_EN <43,56>

1 2

RV79 10K_0402_5%~D

0_0402_5%~D

RV92

1 2

+3V_MXM

@

RV83

0_0402_5%~D

1 2

@

RV85

0_0402_5%~D

1 2

Place CV9, CV10, CV11
close MXM connector

VGA_PS_0

CV9 0.01U_0402_16V7K~D@

VGA_PS_1

CV10 0.01U_0402_16V7K~D@

VGA_PS_2

CV11 0.01U_0402_16V7K~D@

VGA_SMB_DA1

RV900_0402_5%~D

12

VGA_SMB_CK1

RV910_0402_5%~D

12

0.1U_0603_25V7K~D

CV4

ACIN<17,43,47,57,63>

RV94 0_0402_5%~D

CLK_PEG_PCH#<18>
CLK_PEG_PCH<18>

+3V_MXM

4.7U_0805_10V4Z~D

1

CV8

2

FB_CLAMP_TGL_REQ# <43>

VGA_PS_0

12
12
12

RV64 3.3K_0402_5%@

1 2

RV66 3.3K_0402_5%@

1 2

RV70 10K_0402_5%~D

J13

PAD-OPEN 4x4m

+3VALW

1

2

5

UV4

1

B

VCC

Y

2

A

G

MC74VHC1G09DFT2G_SC70-5

3

@

1 2

+3VMXM

@

12

HDMI

12

CV5

0.1U_0402_25V6K~D

AC_BATT#

4

RV76 0_0402_5%~D

1 2

RV77 0_0402_5%~D

1 2

LVDS_MXM_TZCLK-<41>
LVDS_MXM_TZCLK+<41>

LVDS_MXM_TZOUT2-<41>
LVDS_MXM_TZOUT2+<41>

LVDS_MXM_TZOUT1-<41>
LVDS_MXM_TZOUT1+<41>

LVDS_MXM_TZOUT0-<41>
LVDS_MXM_TZOUT0+<41>

GPU_HDMI_TXD2-<36>
GPU_HDMI_TXD2+<36>

GPU_HDMI_TXD1-<36>
GPU_HDMI_TXD1+<36>

GPU_HDMI_TXD0-<36>
GPU_HDMI_TXD0+<36>

GPU_HDMI_TXC-<36>
GPU_HDMI_TXC+<36>

GPU_HDMI_SDATA<36>

GPU_HDMI_SCLK<36>

DMC

VGA_DPD_AUXN/DDC<39>
VGA_DPD_AUXP/DDC<39>

+5VMXM

PEG_HTX_C_GRX_N[0..15]<5>

PEG_HTX_C_GRX_P[0..15]<5>

PEG_GTX_HRX_N[0..15]<5>

PEG_GTX_HRX_P[0..15]<5>

J12

@

PAD-OPEN 4x4m

D D

Add R7 increase NV MXM PEG Sw ing

C C

RV80 10K_0402_5%~D@
RV81 36K_0402_1%@

1 2
1 2

+3V_MXM

+3V_MXM

SPDIF_OUT

DGPU_ENVDD<42>
DGPU_BKL_EN<42>
VGA_PNL_PWM<42>

VGA_LCD_DAT<42>
VGA_LCD_CLK<42>

LVDS DDC Module have 4.7K Pull-UP

FB_CLAMP<43>

RV82

10K_0402_5%~D

1 2

B+_MXM_A0

RV84

@

10K_0402_5%~D

1 2

+3V_MXM

RV86

@

B B

10K_0402_5%~D

1 2

B+_MXM_A1

RV87

10K_0402_5%~D

1 2

VIN+<63>

RV88 0_0402_5%~D

VIN-<63>

RV89 0_0402_5%~D

+3V_MXM +3VALW

10K_0402_5%~D

RV71

VGA_TH_OVERT#

PEG_GTX_HRX_N2
PEG_GTX_HRX_P2

PEG_GTX_HRX_N1
PEG_GTX_HRX_P1

PEG_GTX_HRX_P0

LVDS TZ

VGA_DPD_N0<39>
VGA_DPD_P0<39>

VGA_DPD_N1<39>
VGA_DPD_P1<39>

VGA_DPD_N2<39>
VGA_DPD_P2<39>

VGA_DPD_N3<39>
VGA_DPD_P3<39>

VGA_PRSNT_L#<21>

(Pull-UP 10K at PCH)

12

G

2

S

SSM3K7002F_SC59-3~D

CLK_PEG_PCH#_R
CLK_PEG_PCH_R

LVDS_MXM_TZCLK­LVDS_MXM_TZCLK+

LVDS_MXM_TZOUT2­LVDS_MXM_TZOUT2+

LVDS_MXM_TZOUT1­LVDS_MXM_TZOUT1+

LVDS_MXM_TZOUT0­LVDS_MXM_TZOUT0+

GPU_HDMI_TXD2­GPU_HDMI_TXD2+

GPU_HDMI_TXD1­GPU_HDMI_TXD1+

GPU_HDMI_TXD0­GPU_HDMI_TXD0+

GPU_HDMI_TXC­GPU_HDMI_TXC+

GPU_HDMI_SDATA
GPU_HDMI_SCLK

VGA_DPD_N0
VGA_DPD_P0

VGA_DPD_N1
VGA_DPD_P1

VGA_DPD_N2
VGA_DPD_P2

VGA_DPD_N3
VGA_DPD_P3

D

13

QV7

10K_0402_5%~D

12

RV72

TH_OVERT# <43>

JMXM1B

163

GND

165

PEX_RX2 #

167

PEX_RX2

169

GND

171

PEX_RX1 #

173

PEX_RX1

175

GND

177

PEX_RX0 #

179

PEX_RX0

181

GND

183

PEX_REFC LK#

185

PEX_REFC LK

187

GND

189

RSVD

191

RSVD

193

RSVD

195

RSVD

197

RSVD

199

LVDS_UCL K#

201

LVDS_UCL K

203

GND

205

LVDS_UTX3 #

207

LVDS_UTX3

209

GND

211

LVDS_UTX2 #

213

LVDS_UTX2

215

GND

217

LVDS_UTX1 #

219

LVDS_UTX1

221

GND

223

LVDS_UTX0 #

225

LVDS_UTX0

227

GND

229

DP_C_L0#

231

DP_C_L0

233

GND

235

DP_C_L1#

237

DP_C_L1

239

GND

241

DP_C_L2#

243

DP_C_L2

245

GND

247

DP_C_L3#

249

DP_C_L3

251

GND

253

DP_C_AUX #

255

DP_C_AUX

257

RSVD

259

RSVD

261

RSVD

263

RSVD

265

RSVD

267

RSVD

269

RSVD

271

RSVD

273

RSVD

275

RSVD

277

RSVD

279

RSVD

281

GND

283

DP_A_L0 #

285

DP_A_L0

287

GND

289

DP_A_L1 #

291

DP_A_L1

293

GND

295

DP_A_L2 #

297

DP_A_L2

299

GND

301

DP_A_L3 #

303

DP_A_L3

305

GND

307

DP_A_AUX #

309

DP_A_AUX

310

PRSNT_L#

311

GND

JAE_MM70-314-310B1-1-R300

CONN@

EC_SMB_DA1<43>

EC_SMB_CK1<43>

PEX_TX2#

PEX_TX2

PEX_TX1#

PEX_TX1

PEX_TX0#

PEX_TX0

PEX_CLK _REQ#

PEX_RST#
VGA_DDC_ DAT
VGA_DDC_ CLK

VGA_VSYN C
VGA_HSYNC

VGA_RED

VGA_GRE EN

VGA_BLU E

LVDS_LCL K#

LVDS_LCL K

LVDS_LTX3 #

LVDS_LTX3

LVDS_LTX2 #

LVDS_LTX2

LVDS_LTX1 #

LVDS_LTX1

LVDS_LTX0 #

LVDS_LTX0

DP_D_L0#

DP_D_L0

DP_D_L1#

DP_D_L1

DP_D_L2#

DP_D_L2

DP_D_L3#

DP_D_L3

DP_D_AUX #

DP_D_AUX

DP_C_HPD

DP_D_HPD

RSVD
RSVD
RSVD

DP_B_L0 #

DP_B_L0

DP_B_L1 #

DP_B_L1

DP_B_L2 #

DP_B_L2

DP_B_L3 #

DP_B_L3

DP_B_AUX #

DP_B_AUX

DP_B_HPD

DP_A_HPD

162

GND

164
166
168

GND

170
172
174

GND

176
178
180

GND

182
184
186
188
190
192
194

GND

196
198
200
202

GND

204
206
208

GND

210
212
214

GND

216
218
220

GND

222
224
226

GND

228
230
232

GND

234
236
238

GND

240
242
244

GND

246
248
250

GND

252
254
256

GND

258
260
262
264
266
268
270
272

GND

274
276
278

GND

280
282
284

GND

286
288
290

GND

292
294
296

GND

298
300
302
304
306

3V3

308

3V3

312

GND

+3V_MXM

2

DGS

1 3

QV6

SSM3K7002F_SC59-3~D

PEG_HTX_C_GRX_N2
PEG_HTX_C_GRX_P2

PEG_HTX_C_GRX_N1
PEG_HTX_C_GRX_P1

PEG_HTX_C_GRX_N0PEG_GTX_HRX_N0
PEG_HTX_C_GRX_P0

PEG_CLKREQ#
PLTRST_VGA#

CRT

LVDS_MXM_TXCLK­LVDS_MXM_TXCLK+

LVDS_MXM_TXOUT2­LVDS_MXM_TXOUT2+

LVDS_MXM_TXOUT1­LVDS_MXM_TXOUT1+

LVDS_MXM_TXOUT0­LVDS_MXM_TXOUT0+

MXM_TX0N
MXM_TX0P

MXM_TX1N
MXM_TX1P

MXM_TX2N
MXM_TX2P

MXM_TX3N
MXM_TX3P

MXM_DPB_AUXN/DDC
MXM_DPB_AUXP/DDC
VGA_HDMI_DET
MXM_DPB_HPD

VGA_DPC_N0
VGA_DPC_P0

VGA_DPC_N1
VGA_DPC_P1

VGA_DPC_N2
VGA_DPC_P2

VGA_DPC_N3
VGA_DPC_P3

VGA_DPC_AUXN/DDC
VGA_DPC_AUXP/DDC
VGA_DPC_HPD
VGA_DMC_HPD

+3V_MXM

40mil(1A)

2

DGS

1 3

QV8

SSM3K7002F_SC59-3~D

LVDS_MXM_TXCLK- <41>
LVDS_MXM_TXCLK+ <41>

LVDS TX

LVDS_MXM_TXOUT2- < 41>
LVDS_MXM_TXOUT2+ <41>

LVDS_MXM_TXOUT1- < 41>
LVDS_MXM_TXOUT1+ <41>

LVDS_MXM_TXOUT0- < 41>
LVDS_MXM_TXOUT0+ <41>

MXM_TX0N <32>
MXM_TX0P <32>

MXM_TX1N <32>
MXM_TX1P <32>

MXM_TX2N <32>
MXM_TX2P <32>

MXM_TX3N <32>
MXM_TX3P <32>

VGA_HDMI_DET <36>
MXM_DPB_HPD < 32>

VGA_DPC_N0 <30>
VGA_DPC_P0 <30>

VGA_DPC_N1 <30>
VGA_DPC_P1 <30>

VGA_DPC_N2 <30>
VGA_DPC_P2 <30>

VGA_DPC_N3 <30>
VGA_DPC_P3 <30>

VGA_DPC_HPD <30>
VGA_DMC_HPD <39>

+3V_MXM+3V_MXM

4.7K_0402_5%~D

4.7K_0402_5%~D

12

12

RV74

RV73

VGA_SMB_DA1

VGA_SMB_CK1

PEG_CLKREQ# <18>
PLTRST_VGA# <17>

MXM_DPB_AUXN/DDC <32>
MXM_DPB_AUXP/DDC <32>

VGA_DPC_AUXN/DDC <30>
VGA_DPC_AUXP/DDC <30>

eDP

mDP

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

MXMIII Connector

ze Document Number Rev

Si

Custom

LA-9331P

Date: Sheet of

1

26 61Friday, June 22, 2012

0.1

5

4

3

2

1

DP Redriver

+3VS

25

36

1

6

UV6

VGA_DPC_P0

CV13 0.1U_0402_10V6K~D

12

CV15 0.1U_0402_10V6K~D

12

CV17 0.1U_0402_10V6K~D

12

CV19 0.1U_0402_10V6K~D

12

CV21 0.1U_0402_10V6K~D

12

CV23 0.1U_0402_10V6K~D

12

CV25 0.1U_0402_10V6K~D

12

CV27 0.1U_0402_10V6K~D

12

0.1U_0402_10V6K~D
CV31
CV32

0.1U_0402_10V6K~D

VGA_DPC_HPD

12

RV398 100K_0402_5%~D

RV984.7K_0402_5%~D @

12

RV994.7K_0402_5%~D @

12

RV1004.7K_0402_5%~D @

12

RV1014.7K_0402_5%~D

12

RV10210K_0402_1%~D

12

RV1044.7K_0402_5%~D @

12

RV1054.7K_0402_5%~D @

12

RV1064.7K_0402_5%~D @

12

RV1084.7K_0402_5%~D @

12

VGA_DPC_HPD

VGA_DPC_P0<29>
VGA_DPC_N0<29>
VGA_DPC_P1<29>
VGA_DPC_N1<29>
VGA_DPC_P2<29>
VGA_DPC_N2<29>
VGA_DPC_P3<29>
VGA_DPC_N3<29>

DP_POWER_DOWN#

DP_POWER_DOWN#

UV37

4

RV655

D D

+3VS

C C

SN74AHC1G08DCKR_SC70-5

VGA_DPC_HPD<29>

B B

DP_PEQ
DP_CFG1_INPUT

DP_CFG0

DP_RST#

DP_PEQ
DP_CFG1_INPUT
DP_CFG0

VGA_DPC_AUXP/DDC<29>
VGA_DPC_AUXN/DDC<29>

+3VS

5

P

IN1

O

IN2

G

3

@

VGA_DPC_N0
VGA_DPC_P1
VGA_DPC_N1
VGA_DPC_P2
VGA_DPC_N2
VGA_DPC_P3
VGA_DPC_N3

CV487

0.1U_0402_16V4Z~D

1 2

1

DGPU_PWROK <29,43>

DP_PCH_HPD

2

0_0402_5%~D

12

VGA_DPC_AUXP/DDC
VGA_DPC_AUXN/DDC

CPU_MXM_MDP_P0_R
CPU_MXM_MDP_N0_R
CPU_MXM_MDP_P1_R
CPU_MXM_MDP_N1_R
CPU_MXM_MDP_P2_R
CPU_MXM_MDP_N2_R
CPU_MXM_MDP_P3_R
CPU_MXM_MDP_N3_R

RV1034.99K_0402_1%

1 2

DP_PCH_HPD<16>

VGA_DPC_AUXP/DDC
VGA_DPC_AUXN/DDC

CPU_MXM_MDP_AUXP_L_C

12

CPU_MXM_MDP_AUXN_L_C

12

100K_0402_5%~D

MDP_CAB_DET

2

G

DP_PEQ
DP_CFG0

MDP_CAB_DET

DP_PCH_HPD

+3VS

12

RV117

13

D

QV9
BSS138_SOT23~D

S

38
39
41
42
44
45
47
48

3

4
5

26

7

8

9

33
34

30
29

VGA_DPC_AUXN/DDC
VGA_DPC_AUXP/DDC

MDP_CAB_DET#

IN0p
IN0n
IN1p
IN1n
IN2p
IN2n
IN3p
IN3n

I2C_ADDR

SCL_CTL/PE Q
SDA_CTL/CFG 0

PD#

REXT

CAD_SRC

HPD_SRC

SCL_DDC
SDA_DDC

AUX_SRCP
AUX_SRCN

12

VCC4

VCC532VCC6

VCC1

VCC2

VCC3

GND3

GND118GND2

31

24

UV8

2

1A
2A51B

1

1OE#

7

CBTD3306PW_TSSOP8

CPU_MXM_MDP_P0_C

23

OUT0p

CPU_MXM_MDP_N0_C

22

OUT0n

CPU_MXM_MDP_P1_C

20

OUT1p

CPU_MXM_MDP_N1_C

19

OUT1n

CPU_MXM_MDP_P2_C

17

OUT2p

CPU_MXM_MDP_N2_C

16

OUT2n

CPU_MXM_MDP_P3_C

14

OUT3p

CPU_MXM_MDP_N3_C

13

OUT3n

DP_CFG1_INPUT

40

CFG1

46

NC

DP_RST#

35

RST#

CAB_DET_SINKDP_POWER_DOWN#

10

CAD_SNK

HPD_SINK

AUX_SNKP
AUX_SNKN

CEXT

EPAD

49

PS8330BQFN48GTR2-A0_QFN48_7X7

VCC

2B

GND42OE#

NC2

NC3

NC4

NC5

+5VS

8

3

6

11

CPU_MXM_MDP_AUXP

28

CPU_MXM_MDP_AUXN

27

2
15
21
37
43

0.1U_0402_16V4Z~D

CV41

1

2

DISP_HPD_SINK

CV14 0.1U_0402_10V6K~D

12

CV16 0.1U_0402_10V6K~D

12

CV18 0.1U_0402_10V6K~D

12

CV20 0.1U_0402_10V6K~D

12

CV22 0.1U_0402_10V6K~D

12

CV24 0.1U_0402_10V6K~D

12

CV26 0.1U_0402_10V6K~D

12

CV28 0.1U_0402_10V6K~D

12

CV29 2.2U_0402_6.3V6M~D

12

1 2

C

+3VS

+3VS

4.7K_0402_5%~D

4.7K_0402_5%~D

RV116

RV115

1 2

1 2

DP_CBL_DET<17>

1 2

1.5A_6V_1206L150PR~D

RV114 0_1206_5%~D@

0_0402_5%

1 2

RV118

+3VS_DP

CV302.2U_0402_6.3V6M~D

CPU_MXM_MDP_AUXN

CPU_MXM_MDP_AUXP

o-lay

FV4

12

DISP_HPD_SINK
CPU_MXM_MDP_P0
CAB_DET_SINK
CPU_MXM_MDP_N0
DISP_CEC

CPU_MXM_MDP_P1
CPU_MXM_MDP_P3
CPU_MXM_MDP_N1
CPU_MXM_MDP_N3

CPU_MXM_MDP_P2
CPU_MXM_MDP_AUXP
CPU_MXM_MDP_N2
CPU_MXM_MDP_AUXN

CPU_MXM_MDP_P0
CPU_MXM_MDP_N0
CPU_MXM_MDP_P1
CPU_MXM_MDP_N1
CPU_MXM_MDP_P2
CPU_MXM_MDP_N2
CPU_MXM_MDP_P3
CPU_MXM_MDP_N3

RV112 100K_0402_5%~D

RV113 100K_0402_5%~D

1 2

+3VS_DP

Need apply CIS part

CV35

10U_0603_6.3V6M~D

1

1

2

2

+3VS_DP

12

0.1U_0402_25V6K~D

22U_0805_6.3V6M~D

CV36

.1U_0402_16V7K~D

CV38

CV37

1

1

2

2

Mini DP CONN

JMDP1

1

GND

2

HPD

3

LANE0_P

4

CONFIG1

5

LANE0_N

6

CONFIG2

7

GND

8

GND

9

LANE1_P

10

LANE3_P

11

LANE1_N

12

LANE3_N

13

GND

14

GND

15

LANE2_P

16

AUX_CH_P

17

LANE2_N
AUX_CH_N
GND
DP_PWR20GND4

PS_613002-020121

CONN@

GND1
GND2
GND3

18
19

21
22
23
24

RV121

@

DISP_HPD_SINK

1 2

1M_0402_5%~D

RV124

CAB_DET_SINK

1 2

1M_0402_5%~D

VGA_DPC_AUXP/DDC

VGA_DPC_AUXN/DDC

A A

DMN66D0LDW-7_SOT363-6~D

5

RV127

100K_0402_5%~D

4

QV5B

12

100K_0402_5%~D

12

61

QV5A
DMN66D0LDW-7_SOT363-6~D

34

5

RV126

2

DP_MXM_CARD_SEL <32,43>

MXM_MFG_SEL

0

1 ATI

GPU Source

NVDIA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

2

RV125

DISP_CEC

1 2

5.1M_0402_5%

Compal Electronics, Inc.

Title

Mini DP/Thunder Bolt power

ze Document Number Rev

Si

Custom

LA-9331P

Date: Sheet of

1

27 61Friday, June 22, 2012

0.1

A

B

C

D

E

CPU to EDP & LVDS MUX

+3VS

1 1

CV314

0.1U_0402_16V4Z

CV315

CV312

0.01U_0402_16V7K

CV313

0.01U_0402_16V7K

1

1

2

2

+3VS

+3VS

+3VS

+3VS

+3VS

CPU_EDP_P0
CPU_EDP_N0

CPU_EDP_P1
CPU_EDP_N1

CPU_EDP_P2
CPU_EDP_N2

CPU_EDP_P3
CPU_EDP_N3

CPU_EDP_P0<8>
CPU_EDP_N0<8>

CPU_EDP_P1<8>
CPU_EDP_N1<8>

CPU

2 2

HPD_GPU

CPU_EDP_HPD# PEQ

3 3

CTL_EN

PL1

PL0

CFG_0

CFG_1

4 4

CPU_EDP_P2<8>
CPU_EDP_N2<8>

CPU_EDP_P3<8>
CPU_EDP_N3<8>

CPU_EDP_AUX<8>
CPU_EDP_AUX#<8>

RV403 100K_0402_5%@

1 2

RV404 100K_0402_5%

1 2

@

1 2

RV505 4.7K_0402_5%

1 2

RV506 4.7K_0402_5%

@

1 2

RV507 4.7K_0402_5%

1 2

RV508 4.7K_0402_5%

@

1 2

RV510 4.7K_0402_5%

@

1 2

RV509 4.7K_0402_5%

@

1 2

RV511 4.7K_0402_5%

@

1 2

RV522 4.7K_0402_5%

CPU_EDP_AUX CPU_EDP_AUXP
CPU_EDP_AUX#

1 2

CV340 0.1U_0402_16V7K

1 2

CV339 0.1U_0402_16V7K

1 2

CV342 0.1U_0402_16V7K

1 2

CV341 0.1U_0402_16V7K

1 2

CV344 0.1U_0402_16V7K

1 2

CV343 0.1U_0402_16V7K

1 2

CV346 0.1U_0402_16V7K

1 2

CV345 0.1U_0402_16V7K

CPU_EDP_HPD#<8>

Auto test enable; Internal pull down at ~150K Ohm, 3.3V I/O.
L: Auto test disable & input offset cancellation enable (default)
H: Auto test enable & input offset cancellation enable
M: Auto test disable & input offset cancellation disable

Automatic EQ disable; Internal pull down at ~150K Ohm, 3.3V IO
L: Automatic EQ enable (default)
H: Automatic EQ disable

Chip operational mode configuration;
Internal pull down at ~150K Ohm, 3.3V I/O.
L: Control switching mode (default)
H: Automatic switching mode

Chip operational mode configuration;
Internal pull down at ~150K Ohm, 3.3V I/O.
L: Automatic power down enable (default)
H: Automatic power down disable

1

2

CV1050.1U_0402_10V6K~D

12

CV1060.1U_0402_10V6K~D

12

0.1U_0402_16V4Z

CV316

1

1

2

2

CPU_EDP_C_P0
CPU_EDP_C_N0

CPU_EDP_C_P1
CPU_EDP_C_N1

CPU_EDP_C_P2
CPU_EDP_C_N2

CPU_EDP_C_P3
CPU_EDP_C_N3

HPD_GPU

CPU_EDP_HPD#

CTL_EN
PL1
PL0

CPU_EDP_AUXN

CFG_0
CFG_1
PC10
PC11
PC20
PC21

0.1U_0402_16V4Z

UV7

5

VDD33

21

VDD33

30

VDD33

51

VDD33

57

VDD33

6

IN_D0p

7

IN_D0n

9

IN_D1p

10

IN_D1n

12

IN_D2p

13

IN_D2n

15

IN_D3p

16

IN_D3n

4

IN_CA_DET

3

IN_HPD

2

I2C_CTL_EN

1

Pl1/SCL_CTL

60

Pl0/SDA_CTL

22

IN_DDC_SCL

23

IN_DDC_SDA

24

IN_AUXp

25

IN_AUXn

59

CFG0

58

CFG1

56

PC10

55

PC11

54

PC20

53

PC21

11

GND

19

GND

52

GND

61

PAD(GND)

PS8338BQFN60GTR-A0_QFN60_5X9

PC10

PC20

PC11

PC21

PEQ

OUT1_D0p
OUT1_D0n

OUT1_D1p
OUT1_D1n

OUT1_D2p
OUT1_D2n

OUT1_D3p
OUT1_D3n

OUT2_D0p
OUT2_D0n

OUT2_D1p
OUT2_D1n

OUT2_D2p
OUT2_D2n

OUT2_D3p
OUT2_D3n

OUT1_AUXp_SCL

OUT1_AUXn_SDA

OUT2_AUXp_SCL

OUT2_AUXn_SDA

OUT1_CA_DET

OUT1_HPD

OUT2_CA_DET

OUT2_HPD

SW

PEQ

PD
CEXT
REXT

4.99K_0402_1%

@

1 2

RV512 4.7K_0402_5%

@

1 2

RV513 4.7K_0402_5%

@

1 2

RV514 4.7K_0402_5%

@

1 2

RV515 4.7K_0402_5%

@

1 2

RV516 4.7K_0402_5%

@

1 2

RV520 4.7K_0402_5%

@

1 2

RV521 4.7K_0402_5%

@

1 2

RV517 4.7K_0402_5%

@

1 2

RV518 4.7K_0402_5%

1 2

RV519 4.7K_0402_5%

50
49

47
46

45
44

42
41

40
39

37
36

35
34

32
31

26
27

28
29

43
48

33
38

18
8
14
17
20

CPU_EDP_AUX_C
CPU_EDP_AUX#_C

8338_EDP_AUX
8338_EDP_AUX#

8338_CA_DET
2136_HPD#

8338_CA_DET
8338_EDP_HPD#

SW

PWDN

12

RV504

CPU_EDP_P0_S
CPU_EDP_N0_S

CPU_EDP_P1_S
CPU_EDP_N1_S

8338_EDP_P0_S
8338_EDP_N0_S

8338_EDP_P1_S
8338_EDP_N1_S

8338_EDP_P2_S
8338_EDP_N2_S

8338_EDP_P3_S
8338_EDP_N3_S

@

1

CV317

2.2U_0402_6.3V6M

2

+3VS

+3VS

+3VS

+3VS

+3VS

1 2

CV323 0.1U_0402_16V7K

1 2

CV324 0.1U_0402_16V7K

1 2

CV325 0.1U_0402_16V7K

1 2

CV326 0.1U_0402_16V7K

1 2

CV331 0.1U_0402_16V7K

1 2

CV332 0.1U_0402_16V7K

1 2

CV333 0.1U_0402_16V7K

1 2

CV334 0.1U_0402_16V7K

1 2

CV335 0.1U_0402_16V7K

1 2

CV336 0.1U_0402_16V7K

1 2

CV337 0.1U_0402_16V7K

1 2

CV338 0.1U_0402_16V7K

CPU_EDP_AUX_C <40>
CPU_EDP_AUX#_C <40>

8338_EDP_AUX <32>
8338_EDP_AUX# <32>

2136_HPD# <40>

8338_EDP_HPD# <32>

T143PAD~D

QV54 SSM3K7002FU_SC70-3

12

13

D

2

G

S

AUX interception disable for Port y (y = 1, 2). Internal pull
down at ~150K Ohm, 3.3V I/O;
L: AUX interception enable, driver configuration is set by
link training (default)
H: AUX interception disable, driver output with fixed 800mV
and 0dB
M: AUX interception disable, driver output with fixed 400mV
and 0dB

Output swing adjustment for Port y (y = 1, 2).
Internal pull down at ~150K Ohm, 3.3V I/O;
L: default
H: +20%
M: -16.7%

Programmable input equalization levels; Internal pull down at
~150K Ohm, 3.3V I/O.
L: default, LEQ, compensate channel loss up to 11.5dB @
HBR2
H: HEQ, compensate channel loss up to 14.5dB @ HBR2
M: LLEQ, compensate channel loss up to 8.5dB @ HBR2

RV41610K_0402_5%

CPU_EDP_P0_C
CPU_EDP_N0_C

CPU_EDP_P1_C
CPU_EDP_N1_C

8338_EDP_P0
8338_EDP_N0

8338_EDP_P1
8338_EDP_N1

8338_EDP_P2
8338_EDP_N2

8338_EDP_P3
8338_EDP_N3

+3VS

PANEL_SW <19,34>

CPU_EDP_P0_C <40>
CPU_EDP_N0_C <40>

CPU_EDP_P1_C <40>
CPU_EDP_N1_C <40>

8338_EDP_P0 <32>
8338_EDP_N0 <32>

8338_EDP_P1 <32>
8338_EDP_N1 <32>

8338_EDP_P2 <32>
8338_EDP_N2 <32>

8338_EDP_P3 <32>
8338_EDP_N3 <32>

SEL PANEL_SW

LVDS Panel

L

eDP Panel

H

8338_CA_DET

CPU_EDP_HPD#

LVDS Panel

e

DP Panel

RV405 1M_0402_5%~D

1 2

RV503 100K_0402_5%@

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

Title

CPU to EDP & LVDS MUX

ze Document Number Rev

Si

Custom

LA-9331P

D

Date: Sheet of

E

28 61Friday, June 22, 2012

0.1

5

D D

4

3

2

1

CPU & MXM SW for EDP

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

CV62

CV61

1

1

2

2

DP_IN3_PEQ#
DP_IN4_PEQ#
DP_IN3_AEQ#
DP_IN4_AEQ#

MXM_C_TX0P

CV650.1U_0402_10V6K~D

MXM_TX0P<29>
MXM_TX0N<29>

MXM_DPB_AUXP/DDC<29>
MXM_DPB_AUXN/DDC<29>

8338_EDP_P0<31>
8338_EDP_N0<31>
8338_EDP_P1<31>
8338_EDP_N1<31>
8338_EDP_P2<31>
8338_EDP_N2<31>
8338_EDP_P3<31>
8338_EDP_N3<31>

8338_EDP_AUX<31>
8338_EDP_AUX#<31>

MXM_TX1P<29>
MXM_TX1N<29>
MXM_TX2P<29>
MXM_TX2N<29>
MXM_TX3P<29>
MXM_TX3N<29>

MXM_DPB_AUXP/DDC

MXM_DPB_AUXN/DDC

RV138

100K_0402_5%~D

DMN66D0LDW-7_SOT363-6~D

QV1B

MXM_DPB_HPD<29>
8338_EDP_HPD#<31>

12

34

MXM

C C

PS8338

B B

12
12
12
12
12
12
12
12

CV730.1U_0402_10V6K~D

12

CV740.1U_0402_10V6K~D

12

12
12
12
12
12
12
12
12

12
12

12

RV137

100K_0402_5%~D

61

QV1A
DMN66D0LDW-7_SOT363-6~D

2

5

MXM_C_TX0N

CV660.1U_0402_10V6K~D

MXM_C_TX1P

CV670.1U_0402_10V6K~D

MXM_C_TX1N

CV680.1U_0402_10V6K~D

MXM_C_TX2P DP_IN4_PEQ#

CV690.1U_0402_10V6K~D

MXM_C_TX2N

CV700.1U_0402_10V6K~D

MXM_C_TX3P

CV710.1U_0402_10V6K~D

MXM_C_TX3N

CV720.1U_0402_10V6K~D

MXM_DPB_AUXP/DDC_C
MXM_DPB_AUXN/DDC_C

8338_EDP_P0_C

CV750.1U_0402_10V6K~D

8338_EDP_N0_C

CV760.1U_0402_10V6K~D

8338_EDP_P1_C

CV770.1U_0402_10V6K~D

8338_EDP_N1_C

CV780.1U_0402_10V6K~D

8338_EDP_P2_C

CV3080.1U_0402_10V6K~D

8338_EDP_N2_C

CV3070.1U_0402_10V6K~D

8338_EDP_P3_C

CV3050.1U_0402_10V6K~D

8338_EDP_N3_C

CV3060.1U_0402_10V6K~D

8338_EDP_AUX_C

CV790.1U_0402_10V6K~D

8338_EDP_AUX#_C

CV800.1U_0402_10V6K~D

DP_MXM_CARD_SEL <30,43>

MXM_MFG_SEL

UV9

54

VDD

31

VDD

49

IN2_PEQ/ SDA_CTL

50

IN1_PEQ/ SCL_CTL

3

IN1_AEQ#

51

IN2_AEQ#

52

IN1_D0p

53

IN1_D0n

55

IN1_D1p

56

IN1_D1n

1

IN1_D2p

2

IN1_D2n

4

IN1_D3p

5

IN1_D3n

24

IN1_AUXp

23

IN1_AUXn

20

IN1_SCL

19

IN1_SDA

7

IN2_D0p

8

IN2_D0n

10

IN2_D1p

11

IN2_D1n

13

IN2_D2p

14

IN2_D2n

15

IN2_D3p

16

IN2_D3n

26

IN2_AUXp

25

IN2_AUXn

22

IN2_SCL

21

IN2_SDA

6

IN1_HPD

9

IN2_HPD

PS8321QFN56GTR-A0_QFN56_7X7

GPU Source

0

1

NVDIA

ATI

SW_AUX

OUT_AUXp_ SCL
OUT_AUXn_ SDA

AC_AUXp
AC_AUXn

I2C_CTL_EN

CFG_OUTPUT

CA_DET

OUT_D0p
OUT_D0n
OUT_D1p

OUT_D1n
OUT2_D2p
OUT2_D2n

OUT_D3p

OUT_D3n

SW_ML/ I2C_ADDR

CFG_HPD
OUT_HPD

REXT
CEXT

GND
GND
Epad

PD

47

CPU_MXM_EDP_AUXP

28

CPU_MXM_EDP_AUXN

27

CPU_MXM_EDP_AUXP_L

30

CPU_MXM_EDP_AUXN_L

29

37

CFG_OUTPUT_1

34

44

CPU_MXM_EDP_A0P

42

CPU_MXM_EDP_A0N

41

CPU_MXM_EDP_A1P

39

CPU_MXM_EDP_A1N

38

CPU_MXM_EDP_A2P

36

CPU_MXM_EDP_A2N

35

CPU_MXM_EDP_A3P

33

CPU_MXM_EDP_A3N

32

DGPU_SELECT#

48

CFG_HPD_1

46

LV_DP_HPD

43

18
17

45
12
57
40

AUX_SEL/SEL1&2

DGPU_EDIDSEL# <21,36,42>

CV63 0.1U_0402_10V6K~D

12

CV64 0.1U_0402_10V6K~D

12

RV406 1M_0402_5%~D

1 2

CPU_MXM_EDP_A0P <33>
CPU_MXM_EDP_A0N <33>
CPU_MXM_EDP_A1P <33>
CPU_MXM_EDP_A1N <33>
CPU_MXM_EDP_A2P <33>
CPU_MXM_EDP_A2N <33>
CPU_MXM_EDP_A3P <33>
CPU_MXM_EDP_A3N <33>

DGPU_SELECT# <17,36,42>

LV_DP_HPD <33>

2.2U_0402_6.3V6M~D

4.99K_0402_1%

12

CV81

1

RV134

2

IN1 PS8838

0

IN2

1

SourceChanel

MXM

CPU_MXM_EDP_AUXP <33>

CPU_MXM_EDP_AUXN <33>

+3VS+3VS

+3VS+3VS

+3VS+3VS

@

1 2

12

DP_IN3_AEQ#

DP_IN4_AEQ#

RV131

@

4.7K_0402_1%~D

1 2

12

RV133

@

4.7K_0402_1%~D

RV136

4.7K_0402_1%~D

CFG_HPD_1

RV140

4.7K_0402_1%~D

RV128 4.7K_0402_1%~D

RV129 4.7K_0402_1%~D

INy_AEQ# (y=1, 2),Automatic RX equalization enable
L:Disable input automatic equalization
H:Enable input automatic equalization

INy_PEQ(y = 1, 2),Programmable input
equalization level setting
L:Low EQ setting (LEQ), default
H:High EQ setting (HEQ)
M:No EQ

CFG_OUTPUT: output configuration
L:Output is tracking DPCD register setting (auto interception)
H:Output swing level fixed at 600mV and no pre-emphasis
M:Output swing level is fixed at 400mV and no pre-emphasis

@

CFG_HPD,HPD switching configuration
L:HPD is switched by SW_ML
H:HPD is switched by SW_AUX
M:HPD is switched with overlap

RV130

4.7K_0402_1%~D

1 2

DP_IN3_PEQ#

12

RV132

4.7K_0402_1%~D

RV135

4.7K_0402_1%~D

1 2

CFG_OUTPUT_1

12

RV139

4.7K_0402_1%~D

12

12

@

@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

eDP SW-CPU & MXM

ze Document Number Rev

Si

Custom

LA-9331P

Date: Sheet of

1

29 61Friday, June 22, 2012

0.1

5

4

3

2

1

D D

C C

B B

A A

+EDPVDD

0.1U_0402_16V4Z~D

10U_0805_10V4Z~D

CV83

1

1

CV82

2

2

Close to JEDP1

LCDVDD_ON<34,41,42>

EC_ENVDD<42,43>

Back light power

Inverter power

LV1

@

1 2

FBMA-L11-201209-221LMA30T_0805

80 mil

JEDP1

45

CONNTST

MGND1

46

MGND2

47

LANE1_N

MGND3

48

LANE1_P

MGND4

49

MGND5

50

LANE0_N

MGND6

51

LANE0_P

MGND7

52

MGND8

53

AUX_CH_P

MGND9

54

AUX_CH_N

MGND10

55

MGND11

56

LCD_VCC

MGND12

57

LCD_VCC

MGND13

LCD_VCC

BL_GND

BL_GND
BL_PW R
BL_PW R
BL_PW R
BL_PW R

BL_GND

BL_GND
BL_PW M

SMBUS_CL K

SMBUS_DA TA

ALS_VCC
ALS_INT#

CAM_MIC_CB L_DET#

USB_VCC

MIC_CLK
MIC_GND
MIC_DAT

PWR_LE D
BATT2_LED
BATT1_LED

CONNTST

I-PEX_20505-044E-011G~D

CONN@

0.1U_0402_16V4Z~D

CV84

1

2

0_0402_5%~D

0_0402_5%~D

+INVPWR_B+B+

GND

GND

GND

GND

TEST

GND

HPD

GND

USB+

USB-

GND

GND

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

0.1U_0402_16V4Z~D

100_0402_5%~D

12

RV149

CV85

1

2

61

QV4A
DMN66D0LDW-7_SOT363-6~D

2

RV154

1 2

RV156

1 2

@

80 mil

1000P_0402_50V7K~D

1

CV94

2

LCD_BKL_EN<43>

EDP_A0P_CONN
EDP_A0N_CONN

EDP_A1P_CONN
EDP_A1N_CONN

EDP_A2P_CONN
EDP_A2N_CONN

EDP_A3P_CONN
EDP_A3N_CONN

EDP_AUX+_CONN
EDP_AUX-_CONN

EDP_HPD
LCD_TEST

USB20_N11_CONN
USB20_P11_CONN

DMIC_CLK_CONN
DMIC0_CONN

EDP_CAB_DET#

CAM_DET# EDP_A1P_CONN
DISPOFF#

1 2

CV116

0.1U_0603_50V4Z~D

47K_0402_5%~D

12

RV150

200K_0402_5%

12

RV152

34

QV4B
DMN66D0LDW-7_SOT363-6~D

5

B+

12

FDC654P-G_SSOT-6~D

S

4 5

RV157
100K_0402_5%~D

1 2

RV158 47K_0402_5%~D

Panel backlight power control by EC

3

PWR_SRC_ON

FDC654P: P CHANNAL

+3VS

1 2

RV159 100K_0402_5%~D

1 2

RV160 100K_0402_5%~D

1 2

RV162 100K_0402_5%~D

RV163 1M_0402_5%~D

LCD_TEST <42,43>

EDP_CAB_DET# <21>

CAM_DET# <18,42>
DISPOFF# <42>

+3VS_CAM

+EDPVDD

+INVPWR_B+

0.1U_0402_16V4Z~D

eDP POWER

W=60mils

+EDPVDD+INVPWR_B++EDPVDD +5VS

RV151

220K_0402_1%

<BOM Structure>

QV11

G

@

FDS4435BZ_SO8~D

8
7

4.7U_0805_10V4Z~D

6
5

1

CV86

2

12

D

80 mil

6

2
1

QV12
SSM3K7002FU_SC70-3~D

D

S

1 3

G

2

EDP_AUX-

EDP_HPD

EDP_AUX+

EDP_CAB_DET#_R

12

USB20_P11_CONN

USB20_N11_CONN

+3VS

12

RV166

@

10K_0402_5%~D

1 2

BLM18BB221SN1D_2P~D

QV10

1
2
3

4

0.1U_0603_25V7K~D

2

CV88

1

1

CV93

0.1U_0603_50V4Z~D

2

DV3

1

V I/O

Ground2V BUS

3

V I/O

IP4223CZ6_SO6~D

LV6

Reserve

+3VS

+EDPVDD

+3VS_CAM

1

1

2

CV115

0.1U_0402_16V4Z~D

2

CV114

4.7U_0805_10V4Z~D

1

2

+INVPWR_B+

CV107 0.1U_0402_16V4Z~D

CV108 0.1U_0402_16V4Z~D

V I/O

V I/O

1

2

USB20_P11<20>

USB20_N11<20>

+3VS

12

RV141

4.7K_0402_1%~D

CFG_HPD_2

12

RV145

@

CV87

4.7K_0402_1%~D

CFG_HPD,HPD swi tching configu ration
L:HPD is swit ched by SW_ML
H:HPD is swit ched by SW_AUX
M:HPD is swit ched with over lap

+3VS

RV153 4.7K_0402_1%~D@

RV155 4.7K_0402_1%~D@

INy_AEQ# (y=1, 2),Automatic R X equalization enable
L:Disable inp ut automatic e qualization
H:Enable inpu t automatic eq ualization

12

12

4028

4028_EDP_AUXP<38>
4028_EDP_AUXN<38>

CPU/MXM

CPU_MXM_EDP_AUXP<32>
CPU_MXM_EDP_AUXN<32>

EDP_HPD

12

DISPOFF#

12

DP_4028_HPD<38>
LV_DP_HPD<32>

Close to JEDP1

DMIC0_CONN

6

5

4

INV_PWM <42>

CV113

120P_0402_50VNPO~D

DMIC_CLK_CONN

DMIC0<42,45>

DMIC_CLK<42, 45>

@

USB20_P11

USB20_N11

+5VS

LV4

1 2

BLM18BB221SN1D_2P~D

LV5

1 2

BLM18BB221SN1D_2P~D

RV171 0_0402_5%~D

1 2

LV9

1

1

4

4

DLW21SN900SQ2L_0805_4P~D

RV175 0_0402_5%~D

1 2

@

2

2

3

3

@

CPU_MXM_EDP_A0P<32>
CPU_MXM_EDP_A0N<32>
CPU_MXM_EDP_A1P<32>
CPU_MXM_EDP_A1N<32>
CPU_MXM_EDP_A2P<32>
CPU_MXM_EDP_A2N<32>
CPU_MXM_EDP_A3P<32>
CPU_MXM_EDP_A3N<32>

+3VS

4.7K_0402_1%~D

1 2

DP_IN5_PEQ#

12

4.7K_0402_1%~D

INy_PEQ(y = 1, 2),Programmabl e input
equ alization leve l setting
L:Low EQ sett ing (LEQ), def ault
H:High EQ set ting (HEQ)
M:No EQ

DP_IN5_AEQ#

DP_IN6_AEQ#

4028_EDP_L0P<38>
4028_EDP_L0N<38>
4028_EDP_L1P<38>
4028_EDP_L1N<38>
4028_EDP_L2P<38>
4028_EDP_L2N<38>
4028_EDP_L3P<38>
4028_EDP_L3N<38>

DMIC0_CONN

12

CV111

@

10P_0402_50V8J~D

DMIC_CLK_CONN

12

CV112

@

10P_0402_50V8J~D

USB20_P11_CONN

USB20_N11_CONN

+3VS +3VS

RV142

@

RV143

@

4.7K_0402_1%~D

1 2

DP_IN6_PEQ#

@

0.1U_0402_16V4Z~D

CV89

1

2

DP_IN5_PEQ#
DP_IN6_PEQ#
DP_IN5_AEQ#
DP_IN6_AEQ#

4028_EDP_L0P
4028_EDP_L0N
4028_EDP_L1P
4028_EDP_L1N
4028_EDP_L2P
4028_EDP_L2N
4028_EDP_L3P
4028_EDP_L3N

1 2
1 2

CPU_MXM_EDP_A0P
CPU_MXM_EDP_A0N
CPU_MXM_EDP_A1P
CPU_MXM_EDP_A1N
CPU_MXM_EDP_A2P
CPU_MXM_EDP_A2N
CPU_MXM_EDP_A3P
CPU_MXM_EDP_A3N

CPU_MXM_EDP_AUXP
CPU_MXM_EDP_AUXN

EDP_A0P

EDP_A1P

EDP_A2P

12

4.7K_0402_1%~D

0.1U_0402_16V4Z~D

1

2

4028_EDP_AUXP_C

CV970.1U_0402_10V7K~D

4028_EDP_AUXN_C

CV990.1U_0402_10V7K~D

RV147

@

+3VS

CV90

RV165 0_0402_5%~D@

1 2

LV3

1 2

DLW21SN670HQ2L_4P~D

RV168 0_0402_5%~D@

1 2

RV170 0_0402_5%~D@

1 2

LV8

1 2

DLW21SN670HQ2L_4P~D

RV173 0_0402_5%~D@

1 2

RV174 0_0402_5%~D@

1 2

LV10

1 2

DLW21SN670HQ2L_4P~D

RV176 0_0402_5%~D@

1 2

RV146

RV144

@

4.7K_0402_1%~D

1 2

CFG_OUTPUT_2

12

RV148

4.7K_0402_1%~D

CFG_OUTPUT: out put configurat ion
L:Output is t racking DPCD r egister setting (auto intercep tion)
H:Output swin g level fixed at 600mV and no pre-emphasis
M:Output swin g level is fix ed at 400mV and no pre-emphasi s

CPU/GPU & 4028 SW for DPB

UV10

54

VDD

31

VDD

49

IN2_PEQ/ SDA_CTL

50

IN1_PEQ/ SCL_CTL

3

IN1_AEQ#

51

IN2_AEQ#

52

IN1_D0p

53

IN1_D0n

55

IN1_D1p

56

IN1_D1n

1

IN1_D2p

2

IN1_D2n

4

IN1_D3p

5

IN1_D3n

24

IN1_AUXp

23

IN1_AUXn

20

IN1_SCL

19

IN1_SDA

7

IN2_D0p

8

IN2_D0n

10

IN2_D1p

11

IN2_D1n

13

IN2_D2p

14

IN2_D2n

15

IN2_D3p

16

IN2_D3n

26

IN2_AUXp

25

IN2_AUXn

22

IN2_SCL

21

IN2_SDA

6

IN1_HPD

9

IN2_HPD

PS8321QFN56GTR-A0_QFN56_7X7

EDP_A0P_CONN

34

EDP_A0N_CONNEDP_A0N

34

EDP_A1N_CONNEDP_A1N

EDP_A2P_CONN

34

EDP_A2N_CONNEDP_A2N

OUT_AUXp_ SCL
OUT_AUXn_ SDA

SW_ML/ I2C_ADDR

SW_AUX

AC_AUXp
AC_AUXn

I2C_CTL_EN

CFG_OUTPUT

CA_DET

OUT_D0p
OUT_D0n
OUT_D1p

OUT_D1n
OUT2_D2p
OUT2_D2n

OUT_D3p

OUT_D3n

CFG_HPD
OUT_HPD

REXT
CEXT

47

28
27

EDP_AUX+_C

30

EDP_AUX-_C

29

37

CFG_OUTPUT_2

34

EDP_CAB_DET#_R

44

EDP_A0P_L

42

EDP_A0N_L

41

EDP_A1P_L

39

EDP_A1N_L

38

EDP_A2P_L

36

EDP_A2N_L

35

EDP_A3P_L

33

EDP_A3N_L

32

HDMI_IN_SELECT#

48

CFG_HPD_2

46

EDP_HPD

43

18
17

45

GND

12

GND

57

Epad

40

PD

EDP_A3P

EDP_AUX+

HDMI_IN_SELECT# <42,43>

CV91 0.1U_0402_10V7K~D

1 2

CV92 0.1U_0402_10V7K~D

1 2

2.2U_0402_6.3V6M~D

1

CV110

2

RV164 0_0402_5%~D@

LV2

1 2

DLW21SN670HQ2L_4P~D

RV167 0_0402_5%~D@

RV169 0_0402_5%~D@

LV7

1 2

DLW21SN670HQ2L_4P~D

RV172

4.99K_0402_1%

12

RV161

1 2

1 2

1 2

1 2

CV950.1U_0402_10V7K~D

1 2

CV960.1U_0402_10V7K~D

1 2

CV980.1U_0402_10V7K~D

1 2

CV1000.1U_0402_10V7K~D

1 2

CV1010.1U_0402_10V7K~D

1 2

CV1020.1U_0402_10V7K~D

1 2

CV1030.1U_0402_10V7K~D

1 2

CV1040.1U_0402_10V7K~D

1 2

AUX_SEL/SEL1&2

0

EDP_A3P_CONN

34

EDP_A3N_CONNEDP_A3N

EDP_AUX+_CONN

34

EDP_AUX-_CONNEDP_AUX-

0_0402_5%~D@

EDP_AUX+
EDP_AUX-

EDP_A0P
EDP_A0N
EDP_A1P
EDP_A1N
EDP_A2P
EDP_A2N
EDP_A3P
EDP_A3N

SourceChanel

4028

BACPU/MXM1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

eDP SW-eDP CONN

Size Document Number Rev

Custom

LA-9331P

Date: Sheet of

1

30 61Friday, June 22, 2012

0.1

5

4

3

2

1

STDP6038 to EDP & LVDS MUX

D D

UV31

SLE1

2

LVDS_TXOUT0-<42>
LVDS_TXOUT0+<42>

EDP_TXOUT0-<38>
EDP_TXOUT0+<38>

LVDS_TXOUT1-<42>

LVDS_TXOUT1+<42>

EDP_TXOUT1-<38>

EDP_TXOUT1+<38>

LVDS_TXOUT2-<42>
LVDS_TXOUT2+<42>

EDP_TXOUT2-<38>
EDP_TXOUT2+<38>

LVDS_TXCLK-<4 2>

LVDS_TXCLK+<42>

EDP_TXCLK-<38>

C C

B B

LCDVDD_ON<33,41,42>

EDP_TXCLK+<38>

LVDS PANEL
eDP PANEL

LVDS_TZOUT0-<42>
LVDS_TZOUT0+<42>

EDP_TZOUT0-<38>
EDP_TZOUT0+<38>

LVDS_TZOUT1-<42>

LVDS_TZOUT1+<42>

EDP_TZOUT1-<38>

EDP_TZOUT1+<38>

LVDS_TZOUT2-<42>
LVDS_TZOUT2+<42>

EDP_TZOUT2-<38>
EDP_TZOUT2+<38>

LVDS_TZCLK-<42>

LVDS_TZCLK+<42>

EDP_TZCLK-<38>

EDP_TZCLK+<38>

G

S

QV29
SSM3K7002F_SC59-3~D

Output

+3VS

12

RV397

100K_0402_5%~D

2

D

13

0B1

1

1B1

80

0B2

79

1B2

78

2B1

77

3B1

76

2B2

75

3B2

73

4B1

72

5B1

71

4B2

70

5B2

68

6B1

67

7B1

66

6B2

65

7B2

64

8B1

63

9B1

62

8B2

61

9B2

60

10B1

59

11B1

58

10B2

57

11B2

56

12B1

55

13B1

54

12B2

53

13B2

51

14B1

50

15B1

49

14B2

48

15B2

46

16B1

45

17B1

44

16B2

43

17B2

42

18B1

41

19B1

40

18B2

39

19B2

3

GND1

13

GND2

20

GND3

21

GND4

31

GND5

38

GND6

52

GND7

74

GND8

25

OE2#

7

OE1#

PI3LVD1012BE_BQSOP80

SEL2

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8

A0
A1

A2
A3

A4
A5

A6
A7

A8
A9

A10
A11

A12
A13

A14
A15

A16
A17

A18
A19

PANEL_SW

16

5
6

8
9

11
12

14
15

17
18

PANEL_SW <19,31>

LVDS_6038_TXOUT0- <37>
LVDS_6038_TXOUT0+ <37>

LVDS_6038_TXOUT1- <37>
LVDS_6038_TXOUT1+ <37>

LVDS_6038_TXOUT2- <37>
LVDS_6038_TXOUT2+ <37>

LVDS_6038_TXCLK- <37>
LVDS_6038_TXCLK+ <37>

Input

PANEL_SW

34

23
24

26
27

29
30

32
33

35
36

4
10
19
22
28
37
47
69

1

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

CV311

1

2

LVDS_6038_TZOUT0- <37>
LVDS_6038_TZOUT0+ <37>

LVDS_6038_TZOUT1- <37>
LVDS_6038_TZOUT1+ <37>

LVDS_6038_TZOUT2- <37>
LVDS_6038_TZOUT2+ <37>

LVDS_6038_TZCLK- <37>
LVDS_6038_TZCLK+ <37>

+3VS

4.7U_0603_6.3V6K~D

CV309

CV310

1

2

Issued Date

Y

LVDS

eDP

3

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

2

Title

STDP6038 to EDP & LVDS MUX

ze Document Number Rev

Si

Custom

LA-9331P

Date: Sheet of

1

31 61Friday, June 22, 2012

0.1

PANEL_SW

L
H

A A

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

1 1

B

C

D

+5VALW

E

QV13
SI3456DDV-T1-GE3_TSOP6~D

D

6

+3.3VS

UV11

42

VDD

BTMDSCLK-

40

0.1U_0402_16V4Z~D

10U_1206_16V4Z

0.1U_0402_16V4Z~D

CV120

CV119

1

1

1

2

2

2

HDMI_IN_OUT_TXC-_R
HDMI_IN_OUT_TXC+_R
HDMI_IN_OUT_TXD0-_R

HDMI CONN

2 2

HDMI_SW<43>

HDMI_IN_OUT_TXD0+_R
HDMI_IN_OUT_TXD1-_R
HDMI_IN_OUT_TXD1+_R
HDMI_IN_OUT_TXD2-_R
HDMI_IN_OUT_TXD2+_R

HDMI_SW

+1.5VS

CV121

VDD

BTMDSCLK+

30

VDD

20

VDD

18

VDD

16

VDD

8

VDD

2

VDD

ATMDSCLK-

ATMDSCLK+

15

TMDSCLK-

14

TMDSCLK+

12

TMDS0-

11

TMDS0+

7

TMDS1-

6

TMDS1+

4

TMDS2-

3

TMDS2+

9

SEL

43

GND_PAD

TS3DV421RUAR_WQFN42_9X3P5

SEL OUTPUT

L

H

UV12

HDMI_IN_OUT_SDATA
HDMI_IN_OUT_SCLK
HDMI_IN_OUT_HPD
HDMI_IN_OUT_DDC

HDMI_SW

3 3

Vcc

4

1A

7

1B1

2A

9

1B2

3A

12

2B1

4A

2B2

15

3B1

OE#

1

S

3B2
4B1

8

GND

4B2

SN74CBT3257CPWR_TSSOP16~D

SEL OUTPUT

L

H

BMTDS0-

BTMDS0+

BTMDS1-

BMTDS1+

BTMDS2-

BTMDS2+

ATMDS0-

ATMDS0+

ATMDS1-

ATMDS1+

ATMDS2-

ATMDS2+

A

B

16

2
3
5
6
11
10
14
13

B1

B2

22
23
24
25
26
27
28
29

31
32
33
34
35
36
37
38

39

VSS

41

VSS

21

VSS

19

VSS

17

VSS

13

VSS

10

VSS

5

VSS

1

VSS

+5VS

DVI_SDATA
HDMI_DAT
DVI_SCLK
HDMI_CLK
HDMI_SINK_HPD_R
HDMI_IN_HPD_R

HDMI_IN_DET#

HDMI_IN_CK­HDMI_IN_CK+
HDMI_IN_D0­HDMI_IN_D0+
HDMI_IN_D1­HDMI_IN_D1+
HDMI_IN_D2­HDMI_IN_D2+

HDMI_OUT_TXC­HDMI_OUT_TXC+
HDMI_OUT_TXD0­HDMI_OUT_TXD0+
HDMI_OUT_TXD1­HDMI_OUT_TXD1+
HDMI_OUT_TXD2­HDMI_OUT_TXD2+

+1.5VS

1

2

HDMI_IN_CK- < 37>
HDMI_IN_CK+ <37>
HDMI_IN_D0- <37>
HDMI_IN_D0+ <37>
HDMI_IN_D1- <37>
HDMI_IN_D1+ <37>
HDMI_IN_D2- <37>
HDMI_IN_D2+ <37>

HDMI_OUT_TXC- <36>
HDMI_OUT_TXC+ <36>
HDMI_OUT_TXD0- <36>
HDMI_OUT_TXD0+ <36>
HDMI_OUT_TXD1- <36>
HDMI_OUT_TXD1+ <36>
HDMI_OUT_TXD2- <36>
HDMI_OUT_TXD2+ <36>

0.1U_0402_16V4Z~D

10U_1206_16V4Z

CV123

CV124

1

1

2

2

DVI_SDATA <36>
HDMI_DAT <37>

DVI_SCLK <36>
HDMI_CLK <37>

HDMI_SINK_HPD_R <36>
HDMI_IN_HPD_R <37>

HDMI_IN_DET# <37>

HDMI_IN_OUT_DDC<43>

HDMI_IN_OUT_HPD<43>

0.1U_0402_16V4Z~D

CV125

STDP6038

CPU/MXM

+5VS

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

CV127

CV126

1

1

2

2

+5VS

4.7K_0402_5%~D

RV120

1 2

HDMI_IN_OUT_DDC

HDMI_IN_OUT_HPD

12

RV119

100K_0402_5%~D

RV180 0_0402_5%~D@

HDMI_IN_OUT_TXD2+_R

HDMI_IN_OUT_TXD2-_R

HDMI_IN_OUT_TXD1-_R

HDMI_IN_OUT_TXD1+_R

HDMI_IN_OUT_TXD0+_R

HDMI_IN_OUT_TXD0-_R

HDMI_IN_OUT_TXC-_R

HDMI_IN_OUT_TXC+_R

DLW21SN900HQ2L_0805_4P~D

2

3

RV181 0_0402_5%~D@

RV182 0_0402_5%~D@

DLW21SN900HQ2L_0805_4P~D

3

2

RV183 0_0402_5%~D@

RV186 0_0402_5%~D@

DLW21SN900HQ2L_0805_4P~D

RV187 0_0402_5%~D@

RV188 0_0402_5%~D@

DLW21SN900HQ2L_0805_4P~D

RV189 0_0402_5%~D@

Reserve for EMI please close to JHDMI2

1 2

2

3

1 2

1 2

3

2

1 2

1 2

2

2

3

3

1 2

1 2

3

3

2

2

1 2

HDMI_OUT_EN<43>

UART_TX_6038<37>
UART_RX_6038<37>

PCH_PWR_EN

SSM3K7002FU_SC70-3~D

HDMI_IN_OUT_TXC-

HDMI_IN_OUT_TXC+

HDMI_IN_OUT_TXD0-

HDMI_IN_OUT_TXD0+

HDMI_IN_OUT_TXD1-

HDMI_IN_OUT_TXD1+

HDMI_IN_OUT_TXD2-

HDMI_IN_OUT_TXD2+

PCH_PWR_EN<43,56>

LV11

LV12

LV13

LV14

1

1

4

4

4

4

1

1

1

1

4

4

4

4

1

1

HDMI_IN_OUT_TXD2+

HDMI_IN_OUT_TXD2-

HDMI_IN_OUT_TXD1-

HDMI_IN_OUT_TXD1+

HDMI_IN_OUT_TXD0+

HDMI_IN_OUT_TXD0-

HDMI_IN_OUT_TXC-

HDMI_IN_OUT_TXC+

20120531 EMI ADD

CV117

10U_0603_6.3V6M~D

1

2

1 2

RV177
102K_0402_1%

2

G

QV14

RV184 0_0402_5%~D

1 2

RV185 0_0402_5%~D

1 2

CV349 3.3P_0402_50V8C~D

CV350 3.3P_0402_50V8C~D

CV351 3.3P_0402_50V8C~D

CV352 3.3P_0402_50V8C~D

CV353 3.3P_0402_50V8C~D

CV354 3.3P_0402_50V8C~D

CV355 3.3P_0402_50V8C~D

CV356 3.3P_0402_50V8C~D

S

2
1

G

3

RV178

0_0402_5%~D

1

13

0.1U_0603_50V7K~D

D

2

S

HDMI Input/Output Connector

HDMI_IN_OUT_HPD

HDMI_IN_OUT_DDC
HDMI_IN_OUT_SDATA
HDMI_IN_OUT_SCLK
HDMI_UART_TX
HDMI_UART_RX
HDMI_IN_OUT_TXC-

HDMI_IN_OUT_TXC+
HDMI_IN_OUT_TXD0-

HDMI_IN_OUT_TXD0+
HDMI_IN_OUT_TXD1-

HDMI_IN_OUT_TXD1+
HDMI_IN_OUT_TXD2-

HDMI_IN_OUT_TXD2+

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

+HDMI_5V_OUT

45

@

RV179

0_0402_5%~D

CV122

+HDMI_5V_OUT

1

CV118

1U_0402_6.3V6K~D

2

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

SUYIN_100042GR019M23UZL

CONN@

Part Number Description

RO0000002HM

20

GND

21

GND

22

GND

23

GND

ROYALTY HDMI W/LOGO46@

HDMI W/Logo:RO0000002HM

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

HDMI In/Out SW/Connector

Size Document Number Rev

Custom

LA-9331P

Date: Sheet of

E

32 61Friday, June 22, 2012

0.1

5

+3VS

RV402 4.7K_0402_5%~D@

1 2

RV401 4.7K_0402_5%~D@

1 2

RV191 4.7K_0402_5%~D

1 2

RV192 4.7K_0402_5%~D@

1 2

RV194 4.7K_0402_5%~D@

1 2

RV195 4.7K_0402_5%~D@

D D

1 2

RV197 4.7K_0402_5%~D

1 2

RV199 4.7K_0402_5%~D

1 2

RV201 4.7K_0402_5%~D

1 2

RV202 4.7K_0402_5%~D

1 2

HDMI_PWDN

HDMI_DDCBUF

HDMI_CFG_HPD

HDMI_IN2_PEQ

HDMI_IN1_PEQ

.1U_0402_16V7K~D

1

1

CV133

2

2

Close to U3 VCC pins

PS8271
PEQ=L, Middle level receiving equalization selection
PEQ=H, High level receiving equalization selection
PEQ=M, Low level receiving equalization selection

PS121
When DDCBUF_EN# is HIGH, the DDC channel is disabled,
SCL/SDA and SCLZ/SDAZ are disconnected

GPU_HDMI_TXD2-<29>
GPU_HDMI_TXD2+<29>
GPU_HDMI_TXD1-<29>

MXM

C C

CPU

B B

A A

GPU_HDMI_TXD1+<29>
GPU_HDMI_TXD0-<29>
GPU_HDMI_TXD0+<29>
GPU_HDMI_TXC-<29>
GPU_HDMI_TXC+<29>

CPU_HDMI_N2< 8>
CPU_HDMI_P2<8>
CPU_HDMI_N1< 8>
CPU_HDMI_P1<8>
CPU_HDMI_N0< 8>
CPU_HDMI_P0<8>
CPU_HDMI_N3< 8>
CPU_HDMI_P3<8>

+3VS

+3V_MXM

0.01U_0402_16V7K~D

DGPU_EDIDSEL#<21, 32,42>

PCH_GPIO35<21>

SN74AHC1G08DCKR_SC70-5

DGPU_EDIDSEL#

+5VS +HDMI_5V_OUT

DV7

BAT1000-7-F_SOT23-3~D

NC

3
2 1

1U_0603_10V6K~D

@

CV158

1

2

DGPU_SELECT#< 17,32,42>

PCH_GPIO35

SN74AHC1G08DCKR_SC70-5

DGPU_SELECT# DGPU_SEL#

GPU_HDMI_TXD2­GPU_HDMI_TXD2+
GPU_HDMI_TXD1­GPU_HDMI_TXD1+
GPU_HDMI_TXD0­GPU_HDMI_TXD0+
GPU_HDMI_TXC­GPU_HDMI_TXC+ GPU_HDMI_TXC+_C

CPU_HDMI_N2
CPU_HDMI_P2
CPU_HDMI_N1
CPU_HDMI_P1
CPU_HDMI_N0
CPU_HDMI_P0
CPU_HDMI_N3
CPU_HDMI_P3

+3VS

CV154

12

5

1

IN1

2

IN2

UV15

3

@

W=40mils

+HDMI_5V

5A_125V_R451005.MRL~D

CV159

12

0.01U_0402_16V7K~D

1

2

UV16

@

5

CV145 .1U_0402_16V7K~D
CV146 .1U_0402_16V7K~D
CV147 .1U_0402_16V7K~D
CV148 .1U_0402_16V7K~D
CV149 .1U_0402_16V7K~D
CV150 .1U_0402_16V7K~D
CV151 .1U_0402_16V7K~D
CV152 .1U_0402_16V7K~D

PCH_DPB_HDMI_DAT

RV2072.2K_0402_5%~D

12

PCH_DPB_HDMI_CLK

RV2102.2K_0402_5%~D

12

GPU_HDMI_SDATA

RV2162.2K_0402_5%~D

12

GPU_HDMI_SCLK

RV2202.2K_0402_5%~D

12

P

DGPU_EDIDSEL#_R

4

O

G

RV2270_0402_5%~D

12

FV5

1 2

@

RV2280_1206_5%~D

12

+3VS

5

P

IN1

DGPU_SEL#

4

O

IN2

G

3

RV2290_0402_5%~D

12

CV136 .1U_0402_16V7K~D

12

CV137 .1U_0402_16V7K~D

12

CV138 .1U_0402_16V7K~D

12

CV139 .1U_0402_16V7K~D

12

CV140 .1U_0402_16V7K~D

12

CV141 .1U_0402_16V7K~D

12

CV142 .1U_0402_16V7K~D

12

CV143 .1U_0402_16V7K~D

12

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

VGA_HDMI_DET<29>
PCH_HDMI_HPD<17>

GPU_HDMI_SCLK<29>

GPU_HDMI_SDATA< 29>
PCH_DPB_HDMI_CLK<17>
PCH_DPB_HDMI_DAT<17>

DGPU_EDIDSEL#_R <39>

1U_0603_10V4Z~D

1

CV157

2

DGPU_SEL# <39>

4

+3VS

MMST3904-7-F_SOT323-3~D

.1U_0402_16V7K~D

10U_0603_6.3V6M~D

CV135

1

CV134

2

GPU_HDMI_TXD2-_C
GPU_HDMI_TXD2+_C
GPU_HDMI_TXD1-_C
GPU_HDMI_TXD1+_C
GPU_HDMI_TXD0-_C
GPU_HDMI_TXD0+_C
GPU_HDMI_TXC-_C

CPU_HDMI_N2_C
CPU_HDMI_P2_C
CPU_HDMI_N1_C
CPU_HDMI_P1_C
CPU_HDMI_N0_C
CPU_HDMI_P0_C
CPU_HDMI_N3_C
CPU_HDMI_P3_C

GPU_HDMI_SCLK
GPU_HDMI_SDATA
PCH_DPB_HDMI_CLK
PCH_DPB_HDMI_DAT

DGPU_EDIDSEL#_R
DGPU_SEL#

HDMI_IN1_PEQ
HDMI_IN2_PEQ

2.2U_0603_10V7K~D
CV153

499_0402_1%~D

1

2

8/25 change RV53
from 430 to
499ohm

4

12

RV218

HDMI_SW_DETECT

44
45
47
48

11
12
13
14
16
17

46
10
41
42
19
20

22
21

15

23
24

18
43
49

+3VS

C

QV15

@

2

B

E

3 1

10K_0402_5%~D

RV196 0_0402_5%~D

@

RV200

1 2

DGPU_HPD_INT#<21,39>

UV14

IN1_D1n
IN1_D1p
IN1_D2n
IN1_D2p

1

IN1_D3n

2

IN1_D3p

4

IN1_D4n

5

IN1_D4p

8

IN2_D1n

9

IN2_D1p
IN2_D2n
IN2_D2p
IN2_D3n
IN2_D3p
IN2_D4n
IN2_D4p

IN1_HPD
IN2_HPD
IN1_SCL
IN1_SDA
IN2_SCL
IN2_SDA

SW_DDC
SW_MAI N

3

IN1_PEQ
IN2_PEQ

CEXT
REXT

GND
GND
PAD

PS8271QFN48GTR-A1_QFN48_7X7

RV193

@

200K_0402_5%

1 2

1 2

MXM PCH

DGPU_HPD_INT#

0Y1HDMI_SW_DET

IN2IN1

200K_0402_5%

RV198

1 2

2

QV16

DGS

1 3

SSM3K7002F_SC59-3~D

VDD
VDD

PWDN_A SQ

CFG_HPD

DDCBUF

PRE_EMI

RTERM

OUT_D1n
OUT_D1p
OUT_D2n
OUT_D2p
OUT_D3n
OUT_D3p
OUT_D4n
OUT_D4p

OUT_HPD

OUT_SCL

OUT_SDA

3

+3VS

6
31

25

28

40
34
7

36
35
33
32
30
29
27
26

39
38
37

3

2

+3VS

12

RV190

LV15

MBK1608221YZF_2P

1 2

1

2

3

HDMI_PWDN

HDMI_CFG_HPD

HDMI_DDCBUF

HDMI_TXD2­HDMI_TXD2+
HDMI_TXD1­HDMI_TXD1+
HDMI_TXD0­HDMI_TXD0+
HDMI_TXC­HDMI_TXC+

HDMI_SW_DETECT
HDMI_SW_SCL
HDMI_SW_SDA

HDMI_SINK_HPD

220P_0402_50V7K~D

+5VS

@

Issued Date

1

2

RV204

4.7K_0402_5%~D

1 2

RV399

4.7K_0402_5%~D

1 2

CV132

BAV99-7-F_SOT23-3

DV4

@

Security Classification

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

100K_0402_5%~D

HDMI_OE#

1

D

QV17

SSM3K7002F_SC59-3~D

2

G

S

3

HDMI_SINK_HPD_R<35>

RV203 4.7K_0402_5%~D

+3VS

+3VS

@

PS121 CFG0/ CFG1
SCLZ/SDAZ output voltage select;
CFG1:0=00 LOW-level input voltage: <0.40V LOW-level output voltage: 0.60V
PS121 PC0/PC1/PC2
Inputs equalization control, default inputs equalization setting at 12 dB
000: 12 dB, 001: 16 dB, 010: 10 dB, 011: 7 dB
100: 1.5 dB, 101: 4 dB, 110: 9 dB, 111: 7 dB

DVI_SDATA_R
DVI_SCLK_R DVI_SCLK

2012/06/22 2013/06/21

+3VS

HDMI_SINK_HPD_R

1 2

+3VS

+HDMI_5V_OUT

1.5K_0402_5%

RV223

1.5K_0402_5%

12

Compal Secret Data

HDMI_TXD2+
HDMI_TXD2­HDMI_TXD1+
HDMI_TXD1­HDMI_TXD0+
HDMI_TXD0­HDMI_TXC+
HDMI_TXC-

HDMI_DDCBUF

HDMI_OE#

DVI_SDATA_R
DVI_SCLK_R

HDMI_CFG1
HDMI_CFG0

HDMI_PC0
HDMI_PC1

HDMI_PC2

RV205499_0402_1%~D

12

CV1442.2U_0402_6.3V6M~D

12

RV224

12

1 2

RV225 0_0402_5%~D

1 2

RV226 0_0402_5%~D

Deciphered Date

2

Place LC Filter
closed to JHDMI

UV13

38

IN1p

39

IN1n

41

IN2p

42

IN2n

44

IN3p

45

IN3n

47

IN4p

48

IN4n

2

POW

30

HPD_SINK

26

I2C_CTL_EN #

32

NC/DDCBUF_E N#

25

NC/OE#

8

SDA

9

SCL

34

SDA_CTL/CFG 1

35

SCL_CTL/CFG 0

3

I2C_ADDR0 /PC0

4

I2C_ADDR1 /PC1

1

GND/PC2

6

REXT

10

CEXT

CV155

@

+3VS

11

15

VCC1

GND3

GND15GND212GND837GND9

18

RV2064.7K_0402_5%~D @

12

RV2084.7K_0402_5%~D @

12

RV2094.7K_0402_5%~D

12

RV2114.7K_0402_5%~D @

12

RV2124.7K_0402_5%~D

12

RV2132.2K_0402_5%~D

12

RV2142.2K_0402_5%~D

12

RV2154.7K_0402_5%~D @

12

RV2174.7K_0402_5%~D @

12

RV2194.7K_0402_5%~D @

12

RV2214.7K_0402_5%~D @

12

RV2224.7K_0402_5%~D @

12

DAN217T146_SC59-3

10P_0402_50V8J~D

1

CV156

@

2

VCC2

GND424GND631GND5

33

46

21

VCC4

VCC540VCC6

VCC3

GND7

36

27

HDMI_CFG1
HDMI_CFG0
HDMI_PC0
HDMI_PC1
HDMI_PC2
HDMI_SW_SDA
HDMI_SW_SCL

HDMI_CFG1
HDMI_CFG0
HDMI_PC0
HDMI_PC1

HDMI_PC2

DV5

@

10P_0402_50V8J~D

1

2

23

OUT1p

22

OUT1n

20

OUT2p

19

OUT2n

17

OUT3p

16

OUT3n

14

OUT4p

13

OUT4n

7

HPD

29

SDAZ

28

SCLZ

GND10

PS121QFN48G_QFN48_7X7

43

49

2

2

3

1

1

Close to UV2 VCC pins

0.01U_0402_16V7K~D

1

CV128

2

HDMI_OUT_TXD2+
HDMI_OUT_TXD2­HDMI_OUT_TXD1+
HDMI_OUT_TXD1­HDMI_OUT_TXD0+
HDMI_OUT_TXD0­HDMI_OUT_TXC+
HDMI_OUT_TXC-

HDMI_SINK_HPD

HDMI_SW_SDA
HDMI_SW_SCL

+HDMI_5V_OUT

3

DV6

@

DAN217T146_SC59-3

1

DVI_SDATA

Title

e Document Number Rev

Siz

Custom

LA-9331P

Date: Sheet of

HDMI_OUT_TXD2+ <35>
HDMI_OUT_TXD2- <35>
HDMI_OUT_TXD1+ <35>
HDMI_OUT_TXD1- <35>
HDMI_OUT_TXD0+ <35>
HDMI_OUT_TXD0- <35>
HDMI_OUT_TXC+ <35>
HDMI_OUT_TXC- <35>

DVI_SDATA <35>
DVI_SCLK <35>

Compal Electronics, Inc.

HDMI SW-CPU & MXM/Re-driver

+3VS

0.01U_0402_16V7K~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

1

1

1

CV131

CV129

CV130

2

2

2

CONN

1

33 61Friday, June 22, 2012

0.1

5

4

3

2

1

+3.3VS_AVDD

+3.3V_DVDD

+3.3V_DVDD

EC_HDMI_DAT
EC_HDMI_CLK
HDMI_SW_DAT
HDMI_SW_CLK

1 2

RV276 300_0402_1%

HDMI_IN_CK-_R
HDMI_IN_CK+_R
HDMI_IN_D0-_R
HDMI_IN_D0+_R
HDMI_IN_D1-_R
HDMI_IN_D1+_R
HDMI_IN_D2-_R
HDMI_IN_D2+_R

HDMI_IN_SW_HPD

BS_RESERVED_R
BS_SPI_R
BS_I2C_SRC_R

BS_I2C_ON_R

HDMI_SPI_CS#
HDMI_SPI_CLK
HDMI_SPI_SO
HDMI_SPI_SI

+3.3V_AVDD_LVTX

0.1U_0603_25V7K~D

2

CV170

1

+3.3V_AVDD_RPLL

22U_0805_6.3VAM~D

1

CV181

2

XTAL
TCLK

LV16

1 2

BLM18BD601SN1D_0603~D

D D

+3VS +3.3V_DVDD

LV21

1 2

BLM18BD601SN1D_0603~D

+3.3VS_AVDD+3VS

0.1U_0603_25V7K~D

22U_0805_6.3VAM~D

1

2

1

2

0.1U_0603_25V7K~D

CV160

2

2

CV161

CV162

1

1

22U_0805_6.3VAM~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

2

2

CV178

CV177

1

1

Close to respective power Pins

10P_0402_50V8J~D

HDMI_IN_EN<43>

HDMI_IN_CK-<35>

HDMI_IN_CK+<35>

HDMI_IN_D0-<35>

HDMI_IN_D0+<35>

HDMI_IN_D1-<35>

HDMI_IN_D1+<35>

HDMI_IN_D2-<35>

HDMI_IN_D2+<35>

TCLK

+3.3V_DVDD

HDMI_IN_CK­HDMI_IN_CK+
HDMI_IN_D0­HDMI_IN_D0+
HDMI_IN_D1­HDMI_IN_D1+
HDMI_IN_D2­HDMI_IN_D2+

+3.3VS_AVDD

I2S_DAT/SPDIF_IN<45>

BS_INTERFACE_SEL1
BS_INTERFACE_SEL0
BS_UART_FUNCTION_SEL

5

C C

B B

A A

+3.3VS_AVDD

0.1U_0603_25V7K~D

0.1U_0402_16V4Z~D
BLM18BD601SN1D_0603~D

2

2

CV163

CV164

Can not place large capacitor to

1

1

prevent pulse happened when LVDS
power switch off/on

0.1U_0603_25V7K~D

+3.3VS_AVDD

2

CV179

CV180

1

AVDD_RPLL pin10 C610 0.1uF
to AVSS_RPLL pin7

+3.3V_AVDD_RPLL

10P_0402_50V8J~D

1

CV192

2

YV1

1
2

G1

27MHZ_10PF_X3S027000BA1H-U~D

+3.3V_DVDD

2.2K_0402_5%~D

RV261

4700P_0402_25V7K~D

CV197

CV193

1

2

3
4

G2

1 2

HDMI_RST#

RV264 10K_0402_5%~D

1 2

1

2

12

4.7K_0402_5%~D
RV409

12

4.7K_0402_5%~D@
RV410

RV278 10_0402_5%~D

1 2

RV279 10_0402_5%~D

1 2

RV280 10_0402_5%~D

1 2

RV281 10_0402_5%~D

1 2

RV284 10_0402_5%~D

1 2

RV286 10_0402_5%~D

1 2

RV288 10_0402_5%~D

1 2

RV289 10_0402_5%~D

1 2

RV291 249_0402_1%~D

1 2

RV293 0_0402_5%~D@

1 2

RV295 0_0402_5%~D

1 2

RV296 0_0402_5%~D

1 2

RV297 0_0402_5%~D

1 2

LV17

1 2

LV23

1 2

BLM18BD601SN1D_0603~D

+3.3V_AVDD_RPLL

+3.3V_AVDD_LVTX

XTAL

CV195 0.1U_0402_16V4Z~D

1 2

CV196 0.1U_0402_16V4Z~D

1 2

CV198 0.1U_0402_16V4Z~D

1 2

CV199 0.1U_0402_16V4Z~D

1 2

CV200 0.1U_0402_16V4Z~D

1 2

CV201 0.1U_0402_16V4Z~D

1 2

CV202 0.1U_0402_16V4Z~D

1 2

CV203 0.1U_0402_16V4Z~D

1 2

1 2

CV204 0.1U_0402_16V4Z~D

HDMI_IN_EN

T60PAD~D @
T58PAD~D @

+1.2V_AVDD

+1.2VS_HDMI +1.2V_AVDD

LV18

1 2

BLM18BD601SN1D_0603~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

2

2

CV172

CV171

1.2V
TDC 0.52A

1

1

0.1U_0603_25V7K~D

2

Peak Current 0.73A
OCP current 3.5A

+1.2VS_HDMI +1.2V_DVDD

LV22

1 2

BLM18AG601SN1D_0603~D

CV182

1

RV250 22_0402_5%

EC_SMB_CK2_R<43> EC_HDMI_CLK <38>

UV1

10

VDDA_3V3

11

AVDD_OUT_3 3

23

AVDD_OUT_3 3

80

HDMI_VDDA_ 3V3

86

HDMI_VDDA_ 3V3

90

ADC_AVDD_ 3V3

100

ADC_AVDD_ 3V3

38

RVDD_33

109

RVDD_33

128

RVDD_33

8

XTAL

9

TCLK

36

NC

4

RESETn

125

STI_TM2

92

ADC_A_N

93

ADC_A_P

95

ADC_B_N

96

ADC_B_P

98

ADC_C_N

99

ADC_C_P

105

HSYNC_IN

106

VSYNC_IN

70

VEDID_VDD _3V3

71

A_I2C_SD A

72

A_I2C_SC L

73

D1_I2C_S DA / GPIO_2 8

74

D1_I2C_S CL / GPIO_2 9

44

D2_I2C_S DA / GPIO_2 4

45

D2_I2C_S CL / GPIO_2 5

111

GPIO_44 / S_I2C_SCL

112

GPIO_43 / S_I2C_SDA

48

DPRX_AUX N

49

DPRX_AUX P

53

DPRX_ML_ L0P

54

DPRX_ML_ L0N

56

DPRX_ML_ L1P

57

DPRX_ML_ L1N

59

DPRX_ML_ L2P

60

DPRX_ML_ L2N

62

DPRX_ML_ L3P

63

DPRX_ML_ L3N

51

DPRX_REX T

43

DPRX_HPD_ OUT / GPO_5

75

HDMI_RXCN

76

HDMI_RXCP

78

HDMI_RX0N

79

HDMI_RX0P

81

HDMI_RX1N

82

HDMI_RX1P

84

HDMI_RX2N

85

HDMI_RX2P

87

HDMI_REXT

113

HDMI_HPD / G PIO_22

114

HDMI_CEC / G PIO_23

39

I2S_0 (S/ PDIF) / GPO_1 2(BS_RESERV ED)

40

I2S_AUMCL K / GPO_13 (BS_SPI_FUN_ SEL)

41

I2S_W S / GPO_14 (BS_I2C_SRC_ SEL)

42

I2S_SCLK / GPO_15(B S_I2C_ON_S PI_EN)

65

SPI_CSn / IRQ_IN / GPO _8

66

SPI_CLK / GPO_9(BS_ INTERFACE_SEL 1)

67

SPI_DI / G PO_10(BS_ INTERFACE_SEL 0)

68

SPI_DO / GPO_11(BS_ UART_FUNCTION_SE L)

47

DPRX_VSS D

55

DPRX_VSS A

61

DPRX_VSS A

77

HDMI_VSSA

83

HDMI_VSSA

STDP6038-AC_PQFP128_20X14~D

1 2

RV251 22_0402_5%

1 2

UART_TX / TTL_SYNC 1 / GPO_7(B S_XTAL_TCLK_S EL)

HDMI

4

22U_0805_6.3VAM~D

2

1

CV165

1

2

0.1U_0603_25V7K~D

22U_0805_6.3VAM~D

1

2

CV184

CV183

2

1

EC_HDMI_CLK
EC_HDMI_DAT

O_CH0N_L V / TTL_D29 / GP IO_67
O_CH0P_L V / TTL_D28 / G PIO_66
O_CH1N_L V / TTL_D27 / GP IO_65
O_CH1P_L V / TTL_D26 / G PIO_64
O_CH2N_L V / TTL_D25 / GP IO_63
O_CH2P_L V / TTL_D24 / G PIO_62
O_CLKN_L V / TTL_D23 / G PIO_61
O_CLKP_ LV / TTL_D22 / G PIO_60
O_CH3N_L V / TTL_D21 / GP IO_59
O_CH3P_L V / TTL_D20 / G PIO_58

LVDS

E_CH0N_L V / TTL_D19 / GP IO_57
E_CH0P_L V / TTL_D18 / G PIO_56
E_CH1N_L V / TTL_D17 / GP IO_55
E_CH1P_L V / TTL_D16 / G PIO_54
E_CH2N_L V / TTL_D15 / GP IO_53
E_CH2P_L V / TTL_D14 / G PIO_52
E_CLKN_L V / TTL_D13 / G PIO_51

E_CLKP_ LV / TTL_D12 / G PIO_50
E_CH3N_L V / TTL_D11 / GP IO_49
E_CH3P_L V / TTL_D10 / G PIO_48

PBIAS / TTL_ D9 / GPO_4

PPOWE R / TTL_D8 / GPO _3

GPO_2 / TTL_D7 / PWM2 (BS_OCM_BOO T_SEL)

STI_TM1 / PW M1 / TTL_D6 / G PO_1

GPO_0 / PWM0 / TTL_D5 (BS_OSC_SE L)

TTL_D4 / GPIO _21(BS_I2C _DEV_ID2)
TTL_D3 / GPIO _20(BS_I2C _DEV_ID1)
TTL_D2 / GPIO _19(BS_I2C _DEV_ID0)

TTL_D1 / GPIO 18 / M_I2C_ SCL

TTL_D0 / GPIO 17 / M_I2C_ SDA

TTL_CKOUT / GP IO16(BS_EXTK EY_EN)

UART_RX / TTL_S YNC2 / GPO_6

LBADC_IN4 / GPIO_35

LBADC_IN3 / GPIO_34
LBADC_IN2 / GPIO_33 / TTL_SYNC4
LBADC_IN1 / GPIO_32 / TTL_SYNC3

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

2

CV166

1

0.1U_0603_25V7K~D

2

2

CV185

1

1

ADC_DVDD_ 1V2

DPRX_VDDD _1V2

DPRX_VDDA _1V2
DPRX_VDDA _1V2
DPRX_VDDA _1V2

VDDA_1V2

VBUFC_RPL L

ADC_VSSA
ADC_VSSA
ADC_VSSA
ADC_VSSD

2

CV167

1

0.1U_0603_25V7K~D

CVDD_12
CVDD_12
CVDD_12
CVDD_12

GPIO_45

VSSA_33

LVVSS
LVVSS

CRVSS
CRVSS
CRVSS
CRVSS

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

2

CV168

CV169

1

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

2

2

CV187

CV186

1

1

EC_HDMI_DAT <38>EC_SMB_DA2_R<43>

116
108
46
35

88

50

64
58
52

6

33
32
31
30
29
28
27
26
25
24

21
20
19
18
17
16
15
14
13
12

3
2

1
127
126
124
123
122

DHMI_IN_NV_CLK_R

121

DHMI_IN_NV_DAT_R

120

119
118
117

5

RV287 10K_0402_5%~D

103

HDMI_PLUG_IN_CAB_DET

104

RV290 10K_0402_5%~D

101

RV292 10K_0402_5%~D

102

110

7

34
22

115
107
69
37

97
94
91
89

RV234

CV176

0.1U_0603_25V7K~D

2

CV188

CV189

1

+1.2V_DVDD

+1.2V_AVDD

LVDS_6038_TXOUT0­LVDS_6038_TXOUT0+
LVDS_6038_TXOUT1­LVDS_6038_TXOUT1+
LVDS_6038_TXOUT2­LVDS_6038_TXOUT2+
LVDS_6038_TXCLK­LVDS_6038_TXCLK+

LVDS_6038_TZOUT0­LVDS_6038_TZOUT0+
LVDS_6038_TZOUT1­LVDS_6038_TZOUT1+
LVDS_6038_TZOUT2­LVDS_6038_TZOUT2+
LVDS_6038_TZCLK­LVDS_6038_TZCLK+

HDMI_IN_BKL_EN
HDMI_IN_ENVDD

BS_OCM_BOOT_SEL
HDMI_IN_AUD_CODEC
HDMI_IN_PWM
BS_I2C_DEV_ID2
BS_I2C_DEV_ID1
BS_I2C_DEV_ID0

1 2

RV274 0_0402_5%~D

BS_EXTKEY_EN
UART_TX_6038
UART_RX_6038

HDMI_TOGGLE <43>

+5VS+3VS

1U_0402_6.3V6K~D

CV174

1

12

2

0_0402_5%~D

1

2

10U_0805_4VAM~D

LVDS_6038_TXOUT0- <34>
LVDS_6038_TXOUT0+ < 34>
LVDS_6038_TXOUT1- <34>
LVDS_6038_TXOUT1+ < 34>
LVDS_6038_TXOUT2- <34>
LVDS_6038_TXOUT2+ < 34>
LVDS_6038_TXCLK- <34>
LVDS_6038_TXCLK+ <34>

LVDS_6038_TZOUT0- <34>
LVDS_6038_TZOUT0+ <34>
LVDS_6038_TZOUT1- <34>
LVDS_6038_TZOUT1+ <34>
LVDS_6038_TZOUT2- <34>
LVDS_6038_TZOUT2+ <34>
LVDS_6038_TZCLK- <34>
LVDS_6038_TZCLK+ <34>

HDMI_IN_BKL_EN <42>
HDMI_IN_ENVDD <42>

RV270 0_0402_5%~D

1 2

1 2

RV273 0_0402_5%~D

1 2

RV395 0_0402_5%~D

1 2

RV396 0_0402_5%~D

BS_XTAL_TCLK_SEL

UART_TX_6038 <35>
UART_RX_6038 <35>

12

12
12

3

+3.3V_DVDD

+1.2VS_A+1.2VS

12

15_0402_5%~D

@

RV244

15P_0402_50V8J~D

1

@

CV190

2

22U_0805_6.3VAM~D

CV173

1

2

RV230 10K_0402_5%~D

RV232 10K_0402_5%~D

RV233 10K_0402_5%~D

RV235 10K_0402_5%~D

RV237 10K_0402_5%~D

RV238 10K_0402_5%~D

RV239 10K_0402_5%~D

RV240 10K_0402_5%~D

RV242 10K_0402_5%~D

RV243 10K_0402_5%~D

RV245 10K_0402_5%~D

RV246 10K_0402_5%~D

RV247 10K_0402_5%~D

RV248 10K_0402_5%~D

RV249 10K_0402_5%~D

RV231 100K_0402_5%~D

1 2

UV17

NC

VDD

VIN

VOUT

EN

ADJ

PGOOD

GND
GND

RT9025-25PSP_SO8

5

6

7

8
9

4

3

2

1

+1.2VS_HDMI

.1U_0402_16V7K~D

12

CV175

LV19

BLM18AG601SN1D_0603~D

10K_0402_5%~D

12

RV236

20K_0402_5%~D

12

RV241

12

BLM18AG601SN1D_0603~D

HDMI_SPI_CLK_R

For 4028

LV20

12

2Mbit

HDMI_SPI_CS# HDMI_SPI_CS#_R
HDMI_SPI_SO

+3.3V_DVDD

EDID_WP

1 2

HDMI_IN_AUDIO_CODEC <45>

HDMI_IN_PWM <42>

BS_OSC_SEL

DHMI_IN_NV_CLK
DHMI_IN_NV_DAT

+5VS

0.1U_0402_16V4Z~D

CV207

1

4.7K_0402_5%~D

2

1 2

UART_RX_6038

HDMI_IN_HPD

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2

B

RV26822_0402_5%

DHMI_IN_NV_CLK <42>
DHMI_IN_NV_DAT <42>

RV282

1 2

RV29422_0402_5%

2012/06/22 2013/06/21

12

1 2

RV253 15_0402_5%~D

1 2

RV255 10K_0402_5%~D

C

E

3 1

+HDMI_5V_OUT

2

B

HDMI_SPI_SO_R

+3.3V_DVDD

4.7K_0402_1%~D

12

+HDMI_5V_OUT

1SS355TE-17_SOD323-2

0.1U_0402_16V4Z~D

MMST3904-7-F_SOT323-3~D

QV18

RV283

1K_0402_1%~D

1 2

MMST3904-7-F_SOT323-3~D

HDMI_IN_HPD_R

QV20

C

E

3 1

Compal Secret Data

Deciphered Date

2

@

RV258

1
2
3
4

RV252

15_0402_5%~D

1
2
3
4

1

221

DV8

CV205

UV20

E0

VCC

E1

WC

SCL

E2

SDA

VSS

CAT24C02WI-GT3A_SO8

2Kbit

HDMI_PLUG_IN_CAB_DET

HDMI_IN_HPD_R <35>

SPI ROM

UV18

S#
Q
W#
VSS

MX25L2006EM1I-12G_SOP8

1

2

VCC

RESET#

C
D

16KBit
NVRAM

UV19

1

E0

VCC

2

E1

WC

3

SCL

E2

4

SDA

VSS

CAT24C16WI-GT3_SO8

1

221

DV9 1SS355TE-17_SOD323-2

+5VS_HDMI_IN_EDID

4.7K_0402_1%~D

12

RV265

8
7

HDMI_SW_CLK

6

HDMI_SW_DAT

5

+3.3V_DVDD

10K_0402_5%~D

12

RV275

<BOM Structure>

RV277 33K_0402_5%

.1U_0402_16V7K~D

CV206

1

8
7
6
5

12

2

HDMI_IN_SW_HPD

+HDMI_5V_OUT

HDMI_IN_CAB_DET#

HDMI_SPI_SI_R HDMI_SPI_SI

+3.3V_DVDD

8
7
6
5

+5VS

4.7K_0402_1%~D

4.7K_0402_1%~D

12

RV266

RV267

RV269 22_0402_5%
RV271 100_0402_1%~D
RV272 100_0402_1%~D

12

1

BAV99-7-F_SOT23-3
DV10

2

3

RV298 0_0402_5%~D

1 2

BS_UART_FUNCTION_SEL

+3.3V_DVDD

.1U_0402_16V7K~D

2

CV191

BS_I2C_DEV_ID2

BS_I2C_DEV_ID1

BS_I2C_DEV_ID0

BS_RESERVED_R

BS_SPI_R

BS_I2C_SRC_R

BS_I2C_ON_R

BS_EXTKEY_EN

BS_OCM_BOOT_SEL

BS_INTERFACE_SEL1

BS_INTERFACE_SEL0

BS_XTAL_TCLK_SEL

BS_OSC_SEL

HDMI_IN_AUD_CODEC

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1

RV25410K_0402_5%~D

12

1 2
1 2

0.1U_0402_16V4Z~D

1

CV194

<BOM Structure>

4.7K_0402_1%~D

12

RV259

HDMI_SPI_CLKHDMI_SPI_CLK_R

RV25615_0402_5%~D
RV25715_0402_5%~D

4.7K_0402_1%~D

12

RV260

2

RV262 22_0402_5%

1 2

RV263 22_0402_5%

1 2

1 2
1 2
1 2

2KBit

HDMI_IN_CAB_DET#

SSM3K7002FU_SC70-3~D

MBK1608221YZF_2P

@

Title

e Document Number Rev

Siz

Custom

Date: Sheet of

QV19

LV24

12

HDMI_IN_DET#

Compal Electronics, Inc.

HDMI to LVDS-STDP6038

LA-9331P

DHMI_IN_NV_CLK_R
DHMI_IN_NV_DAT_R

EDID_WP
HDMI_CLK
HDMI_DAT

HDMI_IN_CAB_DET# <43>

+HDMI_5V_OUT

13

D

2

G

S

HDMI_IN_HPDHDMI_IN_HPD

220P_0402_50V7K~D

1

CV208

2

HDMI_IN_DET# <35>

1

HDMI_CLK <35>
HDMI_DAT <35>

100K_0402_5%~D

RV285

12

34 61Friday, June 22, 2012

0.1

5

4

3

2

1

D D

C C

B B

TX_XTAL TX_TCLK

+1.2VS_A

0.1U_0603_25V7K~D
RV300 240_0402_1%

CV216

2

1

4028_EDP_AUXN<33>
4028_EDP_AUXP<33>

4028_EDP_L0N<33>
4028_EDP_L0P<33>
4028_EDP_L1N<33>
4028_EDP_L1P<33>
4028_EDP_L2N<33>
4028_EDP_L2P<33>
4028_EDP_L3N<33>
4028_EDP_L3P<33>

+AVDD_3V3

10P_0402_50V8J~D

10P_0402_50V8J~D

2

2

CV232

1

1

123

4

G2

G1

YV2

27MHZ_10PF_X3S027000BA1H-U~D

EDP_TZOUT0-<34>
EDP_TZOUT0+<34>

EDP_TZOUT1-<34>
EDP_TZOUT1+<34>

EDP_TZOUT2-<34>
EDP_TZOUT2+<34>

EDP_TZCLK-<34>
EDP_TZCLK+<34>

DP_4028_HPD<33>

CV233

EDP_TZOUT0­EDP_TZOUT0+

EDP_TZOUT1­EDP_TZOUT1+

EDP_TZOUT2­EDP_TZOUT2+

EDP_TZCLK­EDP_TZCLK+

UV2C

EC_HDMI_CLK_R

I2S_0/GP IO_8

I2S_1/GP IO_9
I2S_2/GP IO_10
I2S_3/GP IO_11

GPIO_1/B OOT2

GPIO_2/B OOT5

GPIO_3/B OOT6

M8
L9

L11
M12

J10
H11

K10
J11

C13

EC_HDMI_DAT_R

B14

I2C_SCL

B13

I2C_SDA

A13

UART_TX

C2

UART_RX

B1

AUX_UART_TX

B12

AUX_UART_RX

A12

D2
F5
F4
D3

C1

E4

3D_VIDEO

E3

F12

NC1

G12

NC2

D11

NC3

E11

NC4

B2

NC5

B3

NC6

GPIO_0/BOOT3

E5

GPIO_1/BOOT2

D4

GPIO_2/BOOT5

G10

GPIO_3/BOOT6

F11

EDP_TXOUT0-<34>
EDP_TXOUT0+<34>

EDP_TXOUT1-<34>
EDP_TXOUT1+<34>

EDP_TXOUT2-<34>
EDP_TXOUT2+<34>

EDP_TXCLK-<34>
EDP_TXCLK+<34>

12

2.7K_0402_5%

47P_0402_50V8J~D

4028_EDP_L0N
4028_EDP_L0P
4028_EDP_L1N
4028_EDP_L1P
4028_EDP_L2N
4028_EDP_L2P
4028_EDP_L3N
4028_EDP_L3P

+3VS

12

RV303

2

CV243

1

DP_4028_HPD

4028_EDP_AUXN
4028_EDP_AUXP

M10

M11

M13
M14

G13
G14

C11

DPTX_REXT

C12

DPTX_HPD_IN /GPIO_23

C10

DPTX_AUXN

D10

DPTX_AUXP

B6

DPTX_ML_L 0N

C6

DPTX_ML_L 0P

A7

DPTX_ML_L 1N

B7

DPTX_ML_L 1P

A8

DPTX_ML_L 2N

B8

DPTX_ML_L 2P

B9

DPTX_ML_L 3N

C9

DPTX_ML_L 3P

TX_XTAL

B4

TX_XTAL

TX_TCLK

C4

TX_TCLK

RESET

E6

RESETn

SPI_DI_4028

D13

SPI_DO_4028
SPI_CLK_4028
SPI_CSN_4028

IRQ/BOOT7 I2C_SCL

P8

N8

N9
M9

L10

N11

P12
N12

P13
N13

L12
L13

K12
K11

J12
J13

H13
H14

SPI_DI/HO ST_D1/GPO_19

C14

SPI_DO/HO ST_D0/GPO_2 0

E12

SPI_CLK/ HOST_CLK/GPIO _18

F10

SPI_CSn/ HOST_CS/GPIO_ 17

G4

IR_IN/GPIO _6

D12

IRQ/BOOT7/G PIO_12

RV3140_0402_5%~D

12

C3

VBUFC_RPL L

RV3170_0402_5%~D

12

F3

TESTMODE0

RV3210_0402_5%~D

G3

12

TESTMODE1

UV2B

O0_LVRX _CH0N_VIDIN23
O0_LVRX _CH0P_VIDIN2 2

O0_LVRX _CH1N_VIDIN21
O0_LVRX _CH1P_VIDIN2 0

O0_LVRX _CH2N_VIDIN19
O0_LVRX _CH2P_VIDIN1 8

O0_LVRX _CLKN_VIDIN1 7
O0_LVRX _CLKP_VIDIN 16

O0_LVRX _CH3N_VIDIN15
O0_LVRX _CH3P_VIDIN1 4

O0_LVRX _CH4N_VIDIN3
O0_LVRX _CH4P_VIDIN2

O1_LVRX _CH0N_VIDIN23
O1_LVRX _CH0P_VIDIN2 2

O1_LVRX _CH1N_VIDIN21
O1_LVRX _CH1P_VIDIN2 0

O1_LVRX _CH2N_VIDIN19
O1_LVRX _CH2P_VIDIN1 8

O1_LVRX _CLKN_VIDIN1 7
O1_LVRX _CLKP_VIDIN 16

O1_LVRX _CH3N_VIDIN15
O1_LVRX _CH3P_VIDIN1 4

O1_LVRX _CH4N_VIDIN3
O1_LVRX _CH4P_VIDIN2

O0_LVRX _CH5N_VIDIN_C LK

O0_LVRX _CH5P_VIDIN_ DE

O1_LVRX _CH5N_VIDIN_C LK

O1_LVRX _CH5P_VIDIN_ DE

AUX_I2C_ SCL/GPIO_1 5

AUX_I2C_ SDA_GPIO_1 6

I2C_SCL/G PIO_24

I2C_SDA/G PIO_25

UART_TX/BOOT1 /GPIO_13

UART_RX/GPI O_14

eDP

AUX_UART_TX/ BOOT4/GPIO_2 1

AUX_UART_RX /GPIO_22

I2S_BCLK /GPIO_7

I2S_W CLK/GPIO_4

CLK_OUT/GP IO_5/BOOT0

SYS, Audio & DPTX

PWM0/G PIO_0/BOOT3

STDP4028-AB_LFBGA164

O0_LVRX _CH6N_VIDIN24

O0_LVRX _CH6P_VIDIN2 5

O0 & O1 LVDS Input

O1_LVRX _CH6N_VIDIN24

O1_LVRX _CH6P_VIDIN2 5

STDP4028-AB_LFBGA164

RV299 0_0402_5%~D@
RV301 0_0402_5%~D@

UART_TX
UART_RX

0.1U_0402_16V4Z~D

CV228

1

2

0.1U_0402_16V4Z~D

@

CV242

1

2

+3VS

RV305 4.7K_0402_5%~D

1 2

RV308 4.7K_0402_5%~D

1 2

RV309 4.7K_0402_5%~D

1 2

RV310 4.7K_0402_5%~D

1 2

RV311 4.7K_0402_5%~D

1 2

RV312 4.7K_0402_5%~D

1 2

RV313 4.7K_0402_5%~D

1 2

RV315 4.7K_0402_5%~D

1 2

RV316 4.7K_0402_5%~D@

1 2

RV318 4.7K_0402_5%~D

1 2

RV319 4.7K_0402_5%~D

1 2

RV320 4.7K_0402_5%~D

1 2

RV322 4.7K_0402_5%~D@

1 2

RV323 4.7K_0402_5%~D

1 2

EDP_TXOUT0-

EDP_TXOUT0+

EDP_TXOUT1-

EDP_TXOUT1+

EDP_TXOUT2-

EDP_TXOUT2+

EDP_TXCLK­EDP_TXCLK+

12
12

+5VS

4.7K_0402_5%~D

RV302

1 2

UART_RX

+5VS

4.7K_0402_5%~D

@

RV304

EC_HDMI_CLK <37>

EC_HDMI_DAT <37>

+1.2VS_A +VDD_RPLL_1V2

BLM18AG601SN1D_0603~D

+1.2VS_A

BLM18AG601SN1D_0603~D

1 2

AUX_UART_RX

3D_VIDEO
AUX_UART_TX
GPIO_3/BOOT6

I2C_SDA
EC_HDMI_DAT_R
EC_HDMI_CLK_R

UART_TX

AUX_UART_TX

GPIO_0/BOOT3

GPIO_1/BOOT2

GPIO_2/BOOT5

GPIO_3/BOOT6

IRQ/BOOT7

VEGA STDP4028 DPTx BootStraps

UV2A

P2

E0_LVRX _CH0N_VIDIN13

N2

E0_LVRX _CH0P_VIDIN1 2

P3

E0_LVRX _CH1N_VIDIN11

N3

E0_LVRX _CH1P_VIDIN1 0

N4

E0_LVRX _CH2N_VIDIN9

M4

E0_LVRX _CH2P_VIDIN8

M5

E0_LVRX _CLKN_VIDIN7

L5

E0_LVRX _CLKP_VIDIN 6

N6

E0_LVRX _CH3N_VIDIN5

M6

E0_LVRX _CH3P_VIDIN4

P7

E0_LVRX _CH4N_VIDIN1

N7

E0_LVRX _CH4P_VIDIN0

G1

E1_LVRX _CH0N_VIDIN13

G2

E1_LVRX _CH0P_VIDIN1 2

H1

E1_LVRX _CH1N_VIDIN11

H2

E1_LVRX _CH1P_VIDIN1 0

J2

E1_LVRX _CH2N_VIDIN9

J3

E1_LVRX _CH2P_VIDIN8

K3

E1_LVRX _CLKN_VIDIN7

K4

E1_LVRX _CLKP_VIDIN 6

L2

E1_LVRX _CH3N_VIDIN5

L3

E1_LVRX _CH3P_VIDIN4

M1

E1_LVRX _CH4N_VIDIN1

M2

E1_LVRX _CH4P_VIDIN0

+3VS

LV26

12

1

2

LV28

12

1

2

E0_LVRX _CH5N_VIDIN_V SYNC
E0_LVRX _CH5P_VIDIN_ HSYNC

E0_LVRX _CH6N_VIDIN26
E0_LVRX _CH6P_VIDIN2 7

LVDS

E1_LVRX _CH5N_VIDIN_V SYNC
E1_LVRX _CH5P_VIDIN_ HSYNC

E1_LVRX _CH6N_VIDIN26
E1_LVRX _CH6P_VIDIN2 7

STDP4028-AB_LFBGA164

LV25

12

BLM18AG601SN1D_0603~D

1

2

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

22U_0805_6.3VAM~D

2

CV217

1

+AVDD_LVRX_1V2

22U_0805_6.3VAM~D

2

CV229

1

CV218

0.1U_0603_25V7K~D

CV230

2

1

0.1U_0603_25V7K~D

2

1

M7
L6

M3
L4

BLM18AG601SN1D_0603~D

CV219

+3VS

CV231

1

2

10K_0402_5%~D

RV306

E0 & E1 LVDS Input

J5
H4

J4
K5

0.1U_0603_25V7K~D

22U_0805_6.3VAM~D

2

CV210

CV209

1

+3VS

0.1U_0603_25V7K~D

22U_0805_6.3VAM~D

CV234

2

1

12

SPI_CSN_4028
SPI_DI_4028

+1.2VS

+3VS

+1.2VS_A

+AVDD_3V3

+VDD_RPLL_1V2

+AVDD_LVRX_1V2

+AVDD_OUT_LV_33

0.1U_0603_25V7K~D

2

CV211

1

LV27

0.1U_0603_25V7K~D

2

CV235

1

E7
E8
K6
K9

G11

G5

B11

C7
C8
D9

D6
D5

A3

L7

H12

H3

L8

N1

N14

12

+1.2VS_A

CV236

UV2D

PVDD1
PVDD1
PVDD1
PVDD1

PVDD21

PVDD22

DPTX_VDDA_ 1V2
DPTX_VDDA_ 1V2
DPTX_VDDA_ 1V2
DPTX_VDDA_ 1V2

VDDA_3V3
VDD33_TX

VDD_RPLL

AVDD_LVR X_12

AVDD_OUT_L VRX_33
AVDD_OUT_L VRX_33
AVDD_OUT_L VRX_33
AVDD_OUT_L VRX_33
AVDD_OUT_L VRX_33

+AVDD_OUT_LV_33

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

2

2

2

CV212

CV213

1

1

1

+AVDD_3V3

0.1U_0603_25V7K~D

22U_0805_6.3VAM~D

1

2

CV221

CV220

2

1

0.1U_0603_25V7K~D

22U_0805_6.3VAM~D

2

1

CV238

CV237

1

2

2Mbit

UV3

1

S#

2

Q

RESET#

3

W#

4

VSS

MX25L2006EM1I-12G_SOP8

STDP4028-AB_LFBGA164

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

2

CV214

CV215

1

+1.2VS

0.1U_0603_25V7K~D

2

1

2

1

VCC

C
D

PWR & GND

CV222

0.1U_0603_25V7K~D

1

2

2

CV239

1

8
7
6
5

DPTX_VSSA
DPTX_VSSA
DPTX_VSSA
DPTX_VSSA

22U_0805_6.3VAM~D

CV223

0.1U_0603_25V7K~D

CV240

0.1U_0402_16V4Z~D

SPI_CLK_4028
SPI_DO_4028

PVSS3
PVSS3

PVSS3
PVSS3
PVSS3
PVSS3
PVSS3
PVSS3
PVSS3
PVSS3
PVSS3
PVSS3
PVSS3
PVSS3
PVSS3
PVSS3
PVSS3
PVSS3

VSS_RPL L

0.1U_0603_25V7K~D

2

1

0.1U_0603_25V7K~D

2

1

CV244

VSSA_TX

AVSS_LV RX_12

AVSS_OU T_LVRX

AVSS_OU T_LVRX
AVSS_OU T_LVRX
AVSS_OU T_LVRX
AVSS_OU T_LVRX
AVSS_OU T_LVRX
AVSS_OU T_LVRX

CV224

CV241

20mils

1

2

A1
A14

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

D7
D8
E9
E10

A2

C5

K7

P1

F2
F13
H10
H5
K8
P14

2

1

CV227

CV226

CV225

1

1

+3VS

10K_0402_5%~D

12

RV307

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

2

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

LVDS to eDP-STDP4028

e Document Number Rev

Siz

Custom

LA-9331P

Date: Sheet of

1

35 61Friday, June 22, 2012

0.1

5

4

3

2

1

UV22

38

IN1p

39

IN1n

41

IN2p

42

IN2n

44

IN3p

45

IN3n

47

IN4p

48

IN4n

2

POW

30

HPD_SINK

26

I2C_CTL_EN #

32

NC/DDCBUF_E N#

25

NC/OE#

8

SDA

9

SCL

34

SDA_CTL/CFG 1

35

SCL_CTL/CFG 0

3

I2C_ADDR0 /PC0

4

I2C_ADDR1 /PC1

1

GND/PC2

RV62499_0402_1%~D

6

REXT

CV2682.2U_0402_6.3V6M~D

10

CEXT

+3VS

Compal Secret Data

+3VS

+3VS

11

15

VCC1

GND3

GND15GND212GND837GND9

18

Deciphered Date

2

33

21

VCC4

VCC2

VCC3

GND424GND631GND5

36

27

46

VCC540VCC6

OUT1p
OUT1n
OUT2p
OUT2n
OUT3p
OUT3n
OUT4p
OUT4n

HPD

SDAZ

SCLZ

GND7

GND10

PS121QFN48G_QFN48_7X7

43

49

RV3544.7K_0402_5%~D @

12

RV3554.7K_0402_5%~D @

12

RV3564.7K_0402_5%~D

12

RV3574.7K_0402_5%~D @

12

RV3584.7K_0402_5%~D

12

RV3592.2K_0402_5%~D

12

RV3602.2K_0402_5%~D

12

RV3614.7K_0402_5%~D @

12

RV3624.7K_0402_5%~D @

12

RV3634.7K_0402_5%~D @

12

RV3644.7K_0402_5%~D @

12

RV3654.7K_0402_5%~D @

12

CPU_MXM_DMC_P0

23

CPU_MXM_DMC_N0

22

CPU_MXM_DMC_P1

20
19

CPU_MXM_DMC_P2

17

CPU_MXM_DMC_N2

16

CPU_MXM_DMC_P3

14

CPU_MXM_DMC_N3

13

DMC_SINK_HPD

7

DP_DMC_AUXN

29

DP_DMC_AUXP

28

DMC_CFG1
DMC_CFG0
DMC_PC0
DMC_PC1
DMC_PC2
DP_DMC_AUXP
DP_DMC_AUXN

DMC_CFG1
DMC_CFG0
DMC_PC0
DMC_PC1

DMC_PC2

Close to UV2 VCC pins

0.01U_0402_16V7K~D

1

CV263

2

Title

Size Document Number Rev

Custom

Date: Sheet of

+3VS

0.1U_0402_16V4Z~D

0.01U_0402_16V7K~D

0.1U_0402_16V4Z~D

1

1

1

CV265

CV266

CV264

2

2

2

CPU_MXM_DMC_P0 <51>
CPU_MXM_DMC_N0 <51>
CPU_MXM_DMC_P1 <51>
CPU_MXM_DMC_N1 <51>
CPU_MXM_DMC_P2 <51>
CPU_MXM_DMC_N2 <51>
CPU_MXM_DMC_P3 <51>
CPU_MXM_DMC_N3 <51>

Compal Electronics, Inc.

DP SW for DMC

LA-9331P

1

36 61Friday, June 22, 2012

0.1

PCH_DPD_CLK

+3V_MXM

RV327 2.2K_0402_5%~D

RV330 2.2K_0402_5%~D

D D

VGA_DPD_P0<29>
VGA_DPD_N0<29>
VGA_DPD_P1<29>

MXM

CPU

VGA_DPD_AUXP/DDC<29>
VGA_DPD_AUXN/DDC<29>

C C

VGA_DPD_N1<29>
VGA_DPD_P2<29>
VGA_DPD_N2<29>
VGA_DPD_P3<29>
VGA_DPD_N3<29>

CPU_DPD_DMC_P0<8>
CPU_DPD_DMC_N0<8>
CPU_DPD_DMC_P1<8>
CPU_DPD_DMC_N1<8>
CPU_DPD_DMC_P2<8>
CPU_DPD_DMC_N2<8>
CPU_DPD_DMC_P3<8>
CPU_DPD_DMC_N3<8>

VGA_DMC_HPD<29>
PCH_DMC_HPD<17>

PCH_DPD_CLK<17>

PCH_DPD_DAT<17>

VGA_DPD_AUXN/DDC

1 2

CV247 0.1U_0402_10V6K~D
CV248 0.1U_0402_10V6K~D
CV249 0.1U_0402_10V6K~D
CV250 0.1U_0402_10V6K~D
CV251 0.1U_0402_10V6K~D
CV252 0.1U_0402_10V6K~D
CV253 0.1U_0402_10V6K~D
CV254 0.1U_0402_10V6K~D

CV255 0.1U_0402_16V4Z~D
CV256 0.1U_0402_16V4Z~D
CV257 0.1U_0402_16V4Z~D
CV258 0.1U_0402_16V4Z~D
CV259 0.1U_0402_10V7K~D
CV260 0.1U_0402_10V7K~D
CV261 0.1U_0402_10V7K~D
CV262 0.1U_0402_10V7K~D

RV346 10K_0402_5%~D
RV347 10K_0402_5%~D

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

PCH/GPU AUX&LANE SW for DPB

UV21

6

VDD

31

VDD

DMC_PWDN

25

VGA_DPD_SW_P0
VGA_DPD_SW_N0
VGA_DPD_SW_P1
VGA_DPD_SW_N1
VGA_DPD_SW_P2
VGA_DPD_SW_N2
VGA_DPD_SW_P3
VGA_DPD_SW_N3

CPU_DPD_SW_P0
CPU_DPD_SW_N0
CPU_DPD_SW_P1
CPU_DPD_SW_N1
CPU_DPD_SW_P2
CPU_DPD_SW_N2
CPU_DPD_SW_P3
CPU_DPD_SW_N3

12
12

DGPU_EDIDSEL#_R< 36>
DGPU_SEL#< 36>

VGA_DMC_HPD_R
PCH_DMC_HPD_R

DGPU_EDIDSEL#_R

DGPU_SEL#

DMC_IN1_PEQ
DMC_IN2_PEQ

2.2U_0603_6.3V6K~D

CV267

1

2

44

IN1_D1n

45

IN1_D1p

47

IN1_D2n

48

IN1_D2p

1

IN1_D3n

2

IN1_D3p

4

IN1_D4n

5

IN1_D4p

8

IN2_D1n

9

IN2_D1p

11

IN2_D2n

12

IN2_D2p

13

IN2_D3n

14

IN2_D3p

16

IN2_D4n

17

IN2_D4p

46

IN1_HPD

10

IN2_HPD

41

IN1_SCL

42

IN1_SDA

19

IN2_SCL

20

IN2_SDA

22

SW_DDC

21

SW_MAI N

3

IN1_PEQ

15

IN2_PEQ

23

CEXT

24

12

REXT

18

GND

43

GND

49

PAD

PS8271QFN48GTR-A1_QFN48_7X7

499_0402_1%~D

RV348

PWDN_A SQ

CFG_HPD

DDCBUF

PRE_EMI

RTERM

OUT_D1n
OUT_D1p
OUT_D2n
OUT_D2p
OUT_D3n
OUT_D3p
OUT_D4n
OUT_D4p

OUT_HPD

OUT_SCL
OUT_SDA

28

40
34
7

36
35
33
32
30
29
27
26

39
38
37

DMC_CFG_HPD

DMC_DDCBUF
DMC_PRE_EMI

DMC_SW_P0
DMC_SW_N0
DMC_SW_P1
DMC_SW_N1
DMC_SW_P2
DMC_SW_N2
DMC_SW_P3
DMC_SW_N3

VGA_DPD_AUXP/DDC

1 2

10U_0603_6.3V6M~D

1

2

RV338
RV339
RV340
RV341
RV342
RV343
RV344
RV345

DMC_SW_DETECT
DP_DMC_AUXP
DP_DMC_AUXN

+3VS

CV245

2

1

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

0.1U_0402_16V4Z~D

CV246

0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D

PCH_DPD_DAT
DMC_PWDN
DMC_CFG_HPD
DMC_DDCBUF

DMC_PRE_EMI
DMC_IN1_PEQ
DMC_IN2_PEQ

DMC_PWDN

DMC_CFG_HPD

DMC_DDCBUF

DMC_PRE_EMI

DMC_IN1_PEQ

DMC_IN2_PEQ

DP_DMC_ML0P
DP_DMC_ML0N
DP_DMC_ML1P
DP_DMC_ML1N
DP_DMC_ML2P
DP_DMC_ML2N
DP_DMC_ML3P
DP_DMC_ML3N

SEL0Y

IN1

IN2

1

220P_0402_50V7K~D

CV269

1

2

2

G

Place LC Filter
closed to JHDMI

1

CV270

@

2

+3VS

12

RV349
100K_0402_5%~D

DMC_OE#

1

D

QV23

SSM3K7002F_SC59-3~D

S

3

DAN217T146_SC59-3

10P_0402_50V8J~D

10P_0402_50V8J~D

1

CV271

@

2

+HDMI_5V_OUT

2

3

2

3

DV13

DV12

@

@

DAN217T146_SC59-3

1

1

CPU_MXM_DMC_AUXN

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

B B

MMST3904-7-F_SOT323-3~D

DMC_SW_DETECT

A A

5

+3VS

@

1

2

1.5K_0402_5%

LV29

MBK1608221YZF_2P

1 2

BAV99-7-F_SOT23-3

DV11

3

+5VS

+HDMI_5V_OUT

RV366

RV367

1.5K_0402_5%

12

12

RV368 0_0402_5%~D
RV369 0_0402_5%~D

DMC_SINK_HPD

1 2
1 2

RV350

@

C

DGPU_HPD_INT#<21,36>

2

B

E

3 1

10K_0402_5%~D

RV351 0_0402_5%~D

@

RV353

1 2

200K_0402_5%

1 2

1 2

DGPU_HPD_INT#

200K_0402_5%

RV352

1 2

2

QV22

DGS

1 3

SSM3K7002F_SC59-3~D

DMC_SDATA_R
DMC_SCLK_R CPU_MXM_DMC_AUXP

4

QV21

@

RV30 2.2K_0402_5%~D

12

RV31 2.2K_0402_5%~D

12

RV324 4.7K_0402_5%~D@

1 2

RV325 4.7K_0402_5%~D@

1 2

RV326 4.7K_0402_5%~D

1 2

RV328 4.7K_0402_5%~D@

1 2

RV329 4.7K_0402_5%~D

1 2

RV331 4.7K_0402_5%~D

1 2

RV332 4.7K_0402_5%~D@

1 2

RV333 4.7K_0402_5%~D@

1 2

RV334 4.7K_0402_5%~D@

1 2

RV335 4.7K_0402_5%~D@

1 2

RV336 4.7K_0402_5%~D

1 2

RV337 4.7K_0402_5%~D

1 2

DP_DMC_ML0P
DP_DMC_ML0N
DP_DMC_ML1P
DP_DMC_ML1N
DP_DMC_ML2P
DP_DMC_ML2N
DP_DMC_ML3P
DP_DMC_ML3N CPU_MXM_DMC_N1

+3VS

1 2

DP_DMC_HPD

DMC_DDCBUF

DMC_OE#

DMC_SDATA_R
DMC_SCLK_R

DMC_CFG1
DMC_CFG0

DMC_PC0
DMC_PC1

DMC_PC2

12

12

DP_DMC_HPD<51>

RV61 4.7K_0402_5%~D

+3VS

PS121 CFG0/ CFG1
SCLZ/SDAZ output voltage select;
CFG1:0=00 LOW-level input voltage: <0.40V LOW-level output voltage: 0.60V
PS121 PC0/PC1/PC2
Inputs equalization control, default inputs equalization setting at 12 dB
000: 12 dB, 001: 16 dB, 010: 10 dB, 011: 7 dB
100: 1.5 dB, 101: 4 dB, 110: 9 dB, 111: 7 dB

CPU_MXM_DMC_AUXN <51>
CPU_MXM_DMC_AUXP <51>

2012/06/22 2013/06/21

5

D D

+AVCC33 +DVCC33

10U_0603_6.3V6M

0.1U_0402_16V4Z

1

2

LVDS@

CV277

0.1U_0402_16V4Z

1

CV278

2

Close to 5 pin

LVDS@

1

CV276

2

C C

LVDS@

10U_0603_6.3V6M

0.1U_0402_16V4Z

1

1

CV279

CV280

2

2

Close to LV10Close to LV9 Close to 22 pin

LVDS@

LVDS@

0.1U_0402_16V4Z

22U_0805_6.3V6M

1

CV281

2

Close to 18 pin

LVDS@

LVDS@

1

CV282

2

Vendor advise reserve it

@

RV14 0_ 0402_5%

1 2

TL_BKOFF#_R

+3VS_RT

BKOFF#<42,43>

B B

+3VS_RT

2

CSDA

QV2A
DMN66D0LDW-7_SOT363-6~D

LVDS@

LVDS@

RV12 0_ 0402_5%

1 2

CV284

0.1U_0402_16V7K

1 2

LVDS@

5

2

P

B

4

Y

1

A

G

UV25

61

LVDS@

3

MC74VHC1G08DFT2G SC70 5P

EC_SMB_DA2

5

EC_SMB_CK2CSCL

34

QV2B
DMN66D0LDW-7_SOT363-6~D

LVDS@

ENBKL <42,43>

TL_INVT_BL <42>

EC_SMB_DA2 <19,43,53,54>

EC_SMB_CK2 <19,43,53,54>

0.1U_0402_16V4Z

LVDS@

4

+3VS_RT+3VS

30mil 30mil

1 2

RV7 0_0805_5%

LVDS@

+3VS_RT

+SWR_V12

1

CV283

2

+3VS_RT

12

RV16

100K_0402_5%

LVDS@

CPU_EDP_AUX#_C
CPU_EDP_AUX_C

12

RV19

100K_0402_5%

LVDS@

AUX termination

CSCL
CSDA

CPU_EDP_AUX_C<31>
CPU_EDP_AUX#_C<31>

CPU_EDP_P0_C<31>
CPU_EDP_N0_C<31>

CPU_EDP_P1_C<31>
CPU_EDP_N1_C<31>

2136_HPD#<31>

PCH_EDP_PWM<17>

EDID_DATA

EDID_CLK

CSCL

CSDA

3

+1.2VS

60 mils

+SWR_V12

LVDS@

1 2

RV8 0_0805_5%

LVDS@
LVDS@

LV30

FBMA-L11-201209-221LMA30T_0805

LV31

FBMA-L11-201209-221LMA30T_0805

LV32

1 2

4.7UH_PG031B-4R7MS_1.1A_20%

1 2

RV9 12K_0402_1%

LVDS@

RV11 0_0402_5%

1 2

RV20 0_0402_5%

1 2

LVDS@
LVDS@

MIIC_SCL

+DVCC33

12

+AVCC33

12

+SW_LX

LVDS@

CPU_EDP_P0_C
CPU_EDP_N0_C

CPU_EDP_P1_C
CPU_EDP_N1_C

CPU_EDP_AUX_C
CPU_EDP_AUX#_C

2136_HPD#

PCH_EDP_PWM

+DVCC33

1 2

1 2

LVDS@

RV52 4.7K_0402_5%

1 2

LVDS@

RV21 4.7K_0402_5%

1 2

RV47 4.7K_0402_5%LVD S@

1 2

RV51 4.7K_0402_5%LVD S@

1 2

22U_0805_6.3V6M

Close to LV11

LVDS@

+DVCC33

MIIC_SCL
MIIC_SDA

CIICSCL
CIICSDA

RV50

4.7K_0402_5%

LVDS@

RV18

4.7K_0402_5%

LVDS@

1

2

40 mils

60 mils

60 mils

CV272

0.1U_0402_16V4Z

1

2

LVDS@

22

18

17

15

43

11

10

21

12

48
47

13
14

EEPROM

ROMLESS

+DVCC33

CV273

5

7
8

9

4
3

1

2

0.1U_0402_16V4Z

Close to 11 pin

LVDS@

UV24

0.1U_0402_16V4Z

1

CV274

2

Close to 43 pin

RTD2136S

PVCC

SWR_VDD

DP_V33

SWR_LX

SWR_VCCK

VCCK

DP_V12

LANE0P
LANE0N

LANE1P
LANE1N

AUX-CH_P
AUX-CH_N

DP_HPD

PWMIN
TESTMODE
DP_REXT

MIICSCL0
MIICSDA0

CIICSCL1
CIICSDA1

RTD2136S-VE-CG_QFN48_6X6

PWR

DP

OTHERS

1

CV275

2

TXOC+

TXOC-

TXO0+

TXO0-

TXO1+

TXO1-

TXO2+

TXO2-

TXO3+

TXO3-

TXEC+

TXEC-

TXE0+

TXE0-

LVDSGND

TXE1+

TXE1-

TXE2+

TXE2-

TXE3+

TXE3-

MIICSCL1
MIICSDA1

PANEL_VCC

PWMOUT

BL_EN

DP_GND

MIIC_SDA

LVDS@

GND

PAD

2

35
36

41
42

39
40

37
38

33
34

25
26

31
32

29
30

27
28

23
24

46
45

20
19
44

6

16

RV15 0_0402_5%

49

+DVCC33

1 2

1 2

MIIC_SCL
MIIC_SDA

EDID_CLK
EDID_DATA

LVDS_ACLK
LVDS_ACLK#

LVDS_A0
LVDS_A0#

LVDS_A1
LVDS_A1#

LVDS_A2
LVDS_A2#

LVDS_BCLK
LVDS_BCLK#

LVDS_B0
LVDS_B0#

LVDS_B1
LVDS_B1#

LVDS_B2
LVDS_B2#

EDID_CLK
EDID_DATA

TL_ENVDD
TL_INVT_PWM
TL_BKOFF#_R

LVDS@

1 2

RV45

4.7K_0402_5%

LVDS@

RV46

4.7K_0402_5%

@

RV23

LVDS@

1 2

RV24

LVDS@

1 2

RV25 0_ 0402_5%LVDS@

1 2

RV26 0_ 0402_5%LVDS@

1 2

LVDS_ACLK <41>
LVDS_ACLK# <41>

LVDS_A0 <41>
LVDS_A0# < 41>

LVDS_A1 <41>
LVDS_A1# < 41>

LVDS_A2 <41>
LVDS_A2# < 41>

LVDS_BCLK <41>
LVDS_BCLK# <41>

LVDS_B0 <41>
LVDS_B0# < 41>

LVDS_B1 <41>
LVDS_B1# < 41>

LVDS_B2 <41>
LVDS_B2# < 41>

TL_ENVDD <42,43>
TL_INVT_PWM <42>

0_0402_5%

FW_ROM_SCL
FW_ROM_SDA

0_0402_5%

EDID_CLK <42>
EDID_DATA <42>

+DVCC33

8
7
6
5

Addr: A8 (1010 100X)

Pull-Low 100K

Pull-Low 100K

Pull-Low 100KPull-Low 100K

TL_BKOFF#_R

100K_0402_5%

1

EEROM

UV23

A0

VCC

A1

WP
SCL

A2

SDA

GND

CAT24C64WI-GT3_SO8

LVDS@

12

RV22

LVDS@

1
2
3
4

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

Title

Translator RTD2136S

ze Document Number Rev

Si

Custom

LA-9331P

2

Date: Sheet of

1

37 61Friday, June 22, 2012

0.1

5

4

3

2

1

STDP6038 SW STDP4028 PCH/GPU AUX for LVDS

D D

G

2

D

13

LVDS_A0#
LVDS_A0

LVDS_MXM_TXOUT0­LVDS_MXM_TXOUT0+

LVDS_A1#
LVDS_A1

LVDS_MXM_TXOUT1­LVDS_MXM_TXOUT1+

LVDS_A2#
LVDS_A2

LVDS_MXM_TXOUT2­LVDS_MXM_TXOUT2+

LVDS_ACLK#
LVDS_ACLK

LVDS_MXM_TXCLK­LVDS_MXM_TXCLK+

Input

LVDS_B0#
LVDS_B0

LVDS_MXM_TZOUT0­LVDS_MXM_TZOUT0+

LVDS_B1#
LVDS_B1

LVDS_MXM_TZOUT1­LVDS_MXM_TZOUT1+

LVDS_B2#
LVDS_B2

LVDS_MXM_TZOUT2­LVDS_MXM_TZOUT2+

LVDS_BCLK#
LVDS_BCLK

LVDS_MXM_TZCLK­LVDS_MXM_TZCLK+

+3VS

12

RV370

100K_0402_5%~D

LVDS_A0#<40>

LVDS_A0<40>

LVDS_MXM_TXOUT0-<29>

LVDS_MXM_TXOUT0+<29>

LVDS_A1#<40>

LVDS_A1<40>

LVDS_MXM_TXOUT1-<29>

LVDS_MXM_TXOUT1+<29>

LVDS_A2#<40>

LVDS_A2<40>

LVDS_MXM_TXOUT2-<29>

LVDS_MXM_TXOUT2+<29>

LVDS_ACLK#<40>

LVDS_ACLK<40>

LVDS_MXM_TXCLK-<29>

LVDS_MXM_TXCLK+<29>

LVDS_B0#<40>

LVDS_B0<40>

LVDS_MXM_TZOUT0-<29>

LVDS_MXM_TZOUT0+<29>

LVDS_B1#<40>

LVDS_B1<40>

LVDS_MXM_TZOUT1-<29>

LVDS_MXM_TZOUT1+<29>

LVDS_B2#<40>

LVDS_B2<40>

LVDS_MXM_TZOUT2-<29>

LVDS_MXM_TZOUT2+<29>

LVDS_BCLK#<40>

LVDS_BCLK<40>

LVDS_MXM_TZCLK-<29>

LVDS_MXM_TZCLK+<29>

LCDVDD_ON<33,34,42>

RTD2136
DGPU_MXM

S

QV24
SSM3K7002F_SC59-3~D

C C

B B

UV26

SLE1

2

0B1

1

1B1

80

0B2

79

1B2

78

2B1

77

3B1

76

2B2

75

3B2

73

4B1

72

5B1

71

4B2

70

5B2

68

6B1

67

7B1

66

6B2

65

7B2

64

8B1

63

9B1

62

8B2

61

9B2

60

10B1

59

11B1

58

10B2

57

11B2

56

12B1

55

13B1

54

12B2

53

13B2

51

14B1

50

15B1

49

14B2

48

15B2

46

16B1

45

17B1

44

16B2

43

17B2

42

18B1

41

19B1

40

18B2

39

19B2

3

GND1

13

GND2

20

GND3

21

GND4

31

GND5

38

GND6

52

GND7

74

GND8

25

OE2#

7

OE1#

PI3LVD1012BE_BQSOP80

SEL2

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8

A0
A1

A2
A3

A4
A5

A6
A7

A8
A9

A10
A11

A12
A13

A14
A15

A16
A17

A18
A19

16

LVDS_MUX_TXOUT0-

5

LVDS_MUX_TXOUT0+

6

LVDS_MUX_TXOUT1-

8

LVDS_MUX_TXOUT1+

9

LVDS_MUX_TXOUT2-

11

LVDS_MUX_TXOUT2+

12

LVDS_MUX_TXCLK-

14

LVDS_MUX_TXCLK+

15

17
18

34

LVDS_MUX_TZOUT0-

23

LVDS_MUX_TZOUT0+

24

LVDS_MUX_TZOUT1-

26

LVDS_MUX_TZOUT1+

27

LVDS_MUX_TZOUT2-

29

LVDS_MUX_TZOUT2+

30

LVDS_MUX_TZCLK-

32

LVDS_MUX_TZCLK+

33

35
36

4
10
19
22
28
37
47
69

EDP_DETECT#

EDP_DETECT#

0.1U_0402_16V4Z~D

1

2

0.1U_0402_16V4Z~D

CV286

CV285

1

2

EDP_DETECT# <21>

LVDS_MUX_TXOUT0- <42>

LVDS_MUX_TXOUT0+ <42>

LVDS_MUX_TXOUT1- <42>
LVDS_MUX_TXOUT1+ <42>

LVDS_MUX_TXOUT2- <42>

LVDS_MUX_TXOUT2+ <42>

LVDS_MUX_TXCLK- <42>
LVDS_MUX_TXCLK+ <42>

Output

LVDS_MUX_TZOUT0- <42>

LVDS_MUX_TZOUT0+ < 42>

LVDS_MUX_TZOUT1- <42>
LVDS_MUX_TZOUT1+ <42>

LVDS_MUX_TZOUT2- <42>

LVDS_MUX_TZOUT2+ < 42>

LVDS_MUX_TZCLK- <42>
LVDS_MUX_TZCLK+ <42>

+3VS

4.7U_0603_6.3V6K~D

CV287

1

2

SEL

L
H

A A

5

4

Y

RTD2136

DGPU_MXM

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

LVDS SW- 1 to 2 & GPU/PCH

ze Document Number Rev

Si

Custom

LA-9331P

Date: Sheet of

1

38 61Friday, June 22, 2012

0.1

5

LCD Backlight Selector

DGPU_SELECT#

HDMI_IN_PWMSEL#<17>

D D

EC_INV_PWM<43>

VGA_PNL_PWM<29>
HDMI_IN_PWM<37>
TL_INVT_PWM<40 >

EC_INV_PWM<43>
DGPU_BKL_EN<29>

HDMI_IN_BKL_EN<37>

TL_INVT_BL<40>

SG_AMD_BKL<17,43>

S1 S0 Y

RV375 0_040 2_5%~D@

1 2

0_0402_5%~D

RV377

1 2

RV400 0_040 2_5%~D@

1 2

1 2

RV378 0_0402_5%~D

1A 2A

1B1 2B1

1B2 2B2

1

0

DHMI_IN_NV_CLK<37>

DHMI_IN_NV_DAT<37>

VGA_LCD_CLK<29>

VGA_LCD_DAT<29>

EDID_DATA<40>

DGPU_SELECT#

DGPU_EDIDSEL#<21,32,36>

EDID_CLK<40>

1B3 2B3

1B4 2B4

RV382

@

0_0402_5%~D

1 2

RV383

0_0402_5%~D

1 2

VGA_LCD_CLK

EDID_CLK

VGA_LCD_DAT
DHMI_IN_NV_DAT
EDID_DATA

1 1

C C

B B

RV372 0 _0402_5%~D@

RV374 0 _0402_5%~D

VGA_EC_PWM
HDMI_IN_PWM
TL_INVT_PWM

HDMI IN (D)

DSC1000

HDMI IN (I)

UMA

DGPU_EDIDSEL_R#

UV29

6

1B1

5

1B2

4

1B3

3

1B4

10

2B1

11

2B2

12

2B3

13

2B4

1

1OE

SN74CB3Q3253PWR_TSSOP16

1 2

1 2

UV28

6

1B1

VCC

5

1B2

4

1B3

S0

3

S1

1B4

10

2B1

1A

11

2B2

2A

12

2B3

13

2B4

2OE

1

1OE

GND

SN74CB3Q3253PWR_TSSOP16

LCD DDC Selector

+3VS

16

VCC

HDMI_IN_SELECT#DHMI_IN_NV_CLK

14

S0

DGPU_EDIDSEL_R#

2

S1

I2CC_SCL

7

1A

I2CC_SDA

9

2A

15

2OE

8

GND

HDMI_IN_PWM_SELECT#

0.1U_0402_16V4Z~D

+3VS

1

CV288

2

16

HDMI_IN_PWM_SELECT#

14
2

INV_PWM

7

ENBKL

9

15

8

0.1U_0402_16V4Z~D

CV293

1

2

S1 S0 Y

1

0

1 1

LCD POWER

+LCDVDD

100_0603_5%~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

CV302

1

2

A A

LCDVDD_ON

EC_ENVDD<33,43>

12

RV388

CV303

1

2

61

QV3A
DMN66D0LDW-7_ SOT363-6~D

2

RV3910_04 02_5%~D

1 2

RV3930_0402_5%~D @

1 2

5

100K_0402_5%~D

12

+5VALW

47K_0402_5%~D

12

RV387

34

5

RV394

+LCDVDD

4.7U_0805_10V4Z~D

CV300

QV3B
DMN66D0LDW-7_ SOT363-6~D

W=60mils

SI2301CDS-T1-GE3_SOT23-3~D

1 3

1

2

RV390

12

220K_0402_1%

QV28

D

100K_0402_5%~D

100K_0402_5%~D

12

12

RV379

1A 2A

1B1 2B1

1B2 2B2

1B3 2B3

1B4 2B4

S

G

2

.047U_0402_16V7K~D

CV304

1

2

4

+3VS

12

@

10K_0402_5%~D

RV380

+3VS

4.7U_0805_10V4Z~D

1

CV301

2

4

RV376

3

PCH/GPU MUX & 6038 MUX SW for LVDS

UV27

DGPU_BKL_PWM_SEL# <21>

INV_PWM <33>
ENBKL <40,43>

HDMI IN (D)

DSC1000

H

DMI IN (I)

UMA

DGPU_ENVDD<29>

HDMI_IN_ENVDD<37>

TL_ENVDD<40,43>

S0S1 Y

0

0

1 DSC

0

0111

LVDS_MUX_TXOUT0-<41>
LVDS_MUX_TXOUT0+<41>

LVDS_TXOUT0-<34>
LVDS_TXOUT0+<34>

LVDS_MUX_TXOUT1-<41>
LVDS_MUX_TXOUT1+<41>

LVDS_TXOUT1-<34>
LVDS_TXOUT1+<34>

LVDS_MUX_TXOUT2-<41>
LVDS_MUX_TXOUT2+<41>

LVDS_TXOUT2-<34>
LVDS_TXOUT2+<34>

LVDS_MUX_TXCLK-<41>
LVDS_MUX_TXCLK+<41>

LVDS_TXCLK-<34>
LVDS_TXCLK+< 34>

LVDS_MUX_TXOUT0­LVDS_MUX_TXOUT0+

LVDS_TXOUT0­LVDS_TXOUT0+

LVDS_MUX_TXOUT1­LVDS_MUX_TXOUT1+

LVDS_TXOUT1­LVDS_TXOUT1+

LVDS_MUX_TXOUT2­LVDS_MUX_TXOUT2+

LVDS_TXOUT2­LVDS_TXOUT2+

LVDS_MUX_TXCLK­LVDS_MUX_TXCLK+

LVDS_TXCLK­LVDS_TXCLK+

CPU/MXM(MUX) Input
HDMI IN(1:2)

LVDS_MUX_TZOUT0­LVDS_MUX_TZOUT0+ TZOUT0+

LVDS_TZOUT0­LVDS_TZOUT0+

LVDS_MUX_TZOUT1­LVDS_MUX_TZOUT1+

LVDS_TZOUT1­LVDS_TZOUT1+

LVDS_MUX_TZOUT2­LVDS_MUX_TZOUT2+

LVDS_TZOUT2­LVDS_TZOUT2+

LVDS_MUX_TZCLK­LVDS_MUX_TZCLK+

LVDS_TZCLK­LVDS_TZCLK+

+3VS

12

RV385

100K_0402_5%~D

D

13

16

VCC

14

S0

2

S1

7

1A

9

2A

15

2OE

8

GND

LCDVDD_ON

QV27
SSM3K7002F_SC59-3~D

SN74CB3Q3253PWR_TSSOP16

1A 2A

1B1 2B1

1B2 2B2

1B3 2B3

1B4 2B4

LVDS_MUX_TZOUT0-< 41>
LVDS_MUX_TZOUT0+<41>

LVDS_TZOUT0-<34>
LVDS_TZOUT0+<34>

LVDS_MUX_TZOUT1-< 41>
LVDS_MUX_TZOUT1+<41>

LVDS_TZOUT1-<34>
LVDS_TZOUT1+<34>

LVDS_MUX_TZOUT2-< 41>
LVDS_MUX_TZOUT2+<41>

LVDS_TZOUT2-<34>
LVDS_TZOUT2+<34>

LVDS_MUX_TZCLK-<41>
LVDS_MUX_TZCLK+<41>

LVDS_TZCLK-<34>
LVDS_TZCLK+<34>

S

6
5
4
3

10
11
12
13

1

G

2

UV30

1B1
1B2
1B3
1B4

2B1
2B2
2B3
2B4

1OE

HDMI IN

HDMI IN

UMA

+3VS +3VS

1

0.1U_0402_16V4Z~D

2

DGPU_SELECT#

LCDVDD_ON

2

0B1

1

1B1

80

0B2

79

1B2

78

2B1

77

3B1

76

2B2

75

3B2

73

4B1

72

5B1

71

4B2

70

5B2

68

6B1

67

7B1

66

6B2

65

7B2

64

8B1

63

9B1

62

8B2

61

9B2

60

10B1

59

11B1

58

10B2

57

11B2

56

12B1

55

13B1

54

12B2

53

13B2

51

14B1

50

15B1

49

14B2

48

15B2

46

16B1

45

17B1

44

16B2

43

17B2

42

18B1

41

19B1

40

18B2

39

19B2

3

GND1

13

GND2

20

GND3

21

GND4

31

GND5

38

GND6

52

GND7

74

GND8

25

OE2#

7

OE1#

PI3LVD1012BE_BQSOP80

CV299

3

12

RV386

@

10K_0402_5%~D

HDMI_IN_SELECT#

DGPU_SELECT# <17,32,36>

LCDVDD_ON <33,34,41>

USB20_P12<20>

USB20_N12<20>

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL,
TRADE SECRET, AND OTHER PROPRIETARY INFORMATION
OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN
AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS
SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT
DELL'S EXPRESS WRITTEN CONSENT.

USB20_P12 USB20_P12_CONN

HDMI_IN_SELECT#_R

16

SLE1

TXOUT0-

5

A0

TXOUT0+

6

A1

TXOUT1-

8

A2

TXOUT1+

9

A3

TXOUT2-

11

A4

TXOUT2+

12

A5

TXCLK-

14

A6

TXCLK+

15

A7

17

A8

18

A9

34

SEL2

23

A10

24

A11

26

A12

27

A13

29

A14

30

A15

32

A16

33

A17

35

A18

36

A19

4

VDD1

10

VDD2

19

VDD3

22

VDD4

28

VDD5

37

VDD6

47

VDD7

69

VDD8

RV389 0 _0402_5%~D

1 2

LV33

4

4

1

1

DLW21SN900SQ2L_ 0805_4P~D

RV392 0 _0402_5%~D

1 2

Output

HDMI_IN_SELECT#_R

TZOUT0-

TZOUT1­TZOUT1+

TZOUT2­TZOUT2+

TZCLK­TZCLK+

0.1U_0402_16V4Z~D

CV296

1

2

@

3

3

2

2

@

2

+3VS

12

RV371

10K_0402_5%~D

1 2

0_0402_5%~D

SEL

+3VS

0.1U_0402_16V4Z~D

CV297

1

2

DMIC_CLK

1

@

CV322

10P_0402_50V8J~D

2

USB20_N12_CONNUSB20_N12

2

RV373

L
H

1

2

@

4.7U_0603_6.3V6K~D

CV298

HDMI_IN_SELECT# <33,43>

USB20_P12_CONN

USB20_N12_CONN

EN_CAM<43>

Y

B1

B2

LVDS Conn.

JLVDS1

55
54
53
52
51
50
49
48
47
46
45

44

GND11
GND10

43

GND9

42

GND8

41

GND7

40
39

GND6

38

GND5

37

GND4

36

GND3

35

GND2

34

GND1

33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2

JAE_FI-TD44SB-E-R750~D

CONN@

1

1

DV14

0.1U_0402_16V4Z~D

2

1

2

1

V I/O

Ground2V BUS

3

V I/O

IP4223CZ6_SO6~D

CV289

G

V I/O

V I/O

SI2301CDS-T1-GE3_SOT23-3~D

100K_0402_5%~D

12

RV381

SSM3K7002F_SC59-3~D

1

D

QV26

S

3

6

5

+5VS

4

QV25

S

G

2

+3VS_CAM+3VS

D

13

0.1U_0402_16V4Z~D
10U_0805_10V4Z~D

CV290

2

1

1

2

EN_CAM control circuit

+LCDVDD

0.1U_0402_16V4Z~D

CV294

1

2

1

@

CV318

10P_0402_50V8J~D

2

1

@

CV320

10P_0402_50V8J~D

2

+3VS
+LCDVDD

@

LV34

1 2

10U_0805_10V4Z~D

CV295

1

2

DISPOFF#BKOFF#

1

@

CV319

10P_0402_50V8J~D

2

1

@

CV321

10P_0402_50V8J~D

2

Close to JLVDS1

BKOFF#<40,43>

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

+3VS

0.1U_0402_16V4Z~D

CV292

1

2

RV384 0_0402_5%~D

TXOUT0­TXOUT0+

TXOUT1­TXOUT1+

TXOUT2­TXOUT2+

TXCLK­TXCLK+

TZOUT0­TZOUT0+

TZOUT1­TZOUT1+

TZOUT2­TZOUT2+

TZCLK­TZCLK+

I2CC_SCL
I2CC_SDA

USB20_N12_CONN
USB20_P12_CONN

CAM_DET#
DMIC_CLK
DMIC0
DISPOFF#
INV_PWM
LVDS_CAB_DET#

LCD_TEST

=60mils

W

W=80mils

@

1 2

CAM_DET# <18,33 >

DMIC_CLK < 33,45>
DMIC0 <33,4 5>

DISPOFF# <33>

LVDS_CAB_DET# <21>

+3VS_CAM

LCD_TEST <33,43>

+INVPWR_B+ B+

FBMA-L11-201209- 221LMA30T_0805

DELL CONFIDENTIAL/PROPRIETARY

Title

ze Document Number Rev

Si

Date: Sheet of

Compal Electronics, Inc.

LVDS SW- 6038/SYSTEM & CONN

LA-9331P

1

39 61Friday, June 22, 201 2

CV291

0.1

5

4

3

2

1

+3VS

RE36 10K_0402_5%~D

1 2

RE38 10K_0402_5%~D

1 2

RE42 10K_0402_5%~D

1 2

RE43 2.2K_0402_5%~D

1 2

RE45 2.2K_0402_5%~D

1 2

+3VALW_EC

RE46 2.2K_0402_5%~D

1 2

RE48 2.2K_0402_5%~D

D D

KSI0
KSI1
KSI2
KSI3

C C

B B

A A

KSI4
KSI5
KSI6
KSI7

KSO0
KSO1
KSO2
KSO3

1 2

RE49 47K_0402_5%~D

1 2

RE50 47K_0402_5%~D

1 2

RE51 10K_0402_5%~D

1 2

RE52 1K_0402_1%~D@

1 2

RE53 100K_0402_5%~D

1 2

RE54 4.7K_0402_5%~D

1 2

RE57 4.7K_0402_5%~D

1 2

RE58 10K_0402_5%~D

1 2

RE59 10K_0402_5%~D
RE60 10K_0402_5%~D@

1 2

EC_ESB_CLK

RE61 0_0402_5%~D

KSO[0..17]<53>

RP1

KSI0_EC

1 8

KSI1_EC

2 7

KSI2_EC

3 6

KSI3_EC

4 5

0_0804_8P4R_5%

RP3

KSI4_EC

1 8

KSI5_EC

2 7

KSI6_EC

3 6

KSI7_EC

4 5

0_0804_8P4R_5%

RP5

KSO0_EC

1 8

KSO1_EC

2 7

KSO2_EC

3 6

KSO3_EC

4 5

0_0804_8P4R_5%

KSO16

RE115 0_0402_5%~D

1 2

KSO17

RE116 0_0402_5%~D

1 2

H_PROCHOT#

1

3

USBCHG_DET#<52>

5

12

1 2

KSI[0..7]<53>

KSO4
KSO5
KSO6
KSO7

KSO8

KSO9
KSO10
KSO11

KSO12
KSO13
KSO14
KSO15

D

G

SSM3K7002F_SC59-3~D

S

QE22

BKOFF#
EC_SCI#
M_THERMAL#
EC_SMB_CK2
EC_SMB_DA2

EC_SMB_CK1
EC_SMB_DA1
KSO1
KSO2
EC_MUTE#
EC_SMI#
DEPOP#
EC_ESB_CLK
EC_ESB_DAT
LID_SW_IN#
EN_WOL#
EAPD#_R

EC_ESB_CLK_R

KSI[0..7]

KSO[0..17]

RP2

1 8
2 7
3 6
4 5

0_0804_8P4R_5%

RP4

1 8
2 7
3 6
4 5

0_0804_8P4R_5%

RP6

1 8
2 7
3 6
4 5

0_0804_8P4R_5%

KSO16_EC
KSO17_EC

1 2

RE80 0_0402_5%~D

H_PROCHOT#_EC

2

DE83
BAT54CW_SOT323-3

3

1

2

KSO4_EC
KSO5_EC
KSO6_EC
KSO7_EC

KSO8_EC

KSO9_EC
KSO10_EC
KSO11_EC

KSO12_EC
KSO13_EC
KSO14_EC
KSO15_EC

12

RE87
100K_0402_5%~D

USBCHG_DET_PWR_EN#

RE88
150K_0402_1%~D

1 2

+3VALW

+3VALW_EC +3VALW _EC

47K_0402_5%~D

RE55

1 2

EC_RST# RST#

0.1U_0402_16V4Z~D

CE43

1

2

EC_SMB_CK2_R<37>

EC_SMB_DA2_R<37>

VR_HOT# <62>H_PROCHOT#<6,63>

RE85 10K_0402_5%~D

1 2

1 2

RE37 0_0805_1%

47K_0402_5%~D

12

2

1

EC_SMB_CK1<29>
EC_SMB_DA1<29>

PM_SLP_S3#<17,47>
PM_SLP_S5#<17,47>

+3VALW_EC

USBCHG_DET_EC#

+3VLPVL

RE86
100K_0402_5%~D

1 2

13

D

2

G

S

@

1

CE35

2

0.1U_0402_16V7K

RE56

.1U_0402_16V7K~D

CE44

CLK_PCI_LPC

12

RE66

@

33_0402_5%~D

22P_0402_50V8J~D

1

@

CE45

2

Reserve for
EMI please
close to UE1

RE75 0_0402_5%~D

1 2

RE76 0_0402_5%~D

1 2

EC_SMB_CK2<19,40,53,54>

EC_SMB_DA2<19,40,53,54>

RE77 0_0402_5%~D

1 2

RE78 0_0402_5%~D

1 2

EC_SMI#<21>

PS_ID<57>

SUSPWRDNACK<17>

SYSTEM_FAN_FB<54>

MXM1_FAN_FB<53>

E51TXD_P80DATA<50>

E51RXD_P80CLK<50>

PCH_PWROK<17>

WLES ON/OFF LED#<53>

SG_AMD_BKL<17,42>

FB_CLAMP_TGL_REQ#<29>

FB_CLAMP<29>

RE89 10K_0402_5%~D

USBCHG_DET_D <58>

QE321
SSM3K7002FU_SC70-3~D

LE3
FBMA-L11-160808-800LMT_0603

0.1U_0402_16V7K

LPC_FRAME#<19,51>

CLK_PCI_LPC<18>

4

0.1U_0402_16V7K

1

1

CE31

2

GATEA20<21>
KB_RST#<21>
SERIRQ<19>

LPC_AD3<19,51>
LPC_AD2<19,51>
LPC_AD1<19,51>
LPC_AD0<19,51>

PLT_RST#<6,17,44,51,53>

EC_SCI#<21>

ACOFF<63>

1 2

1

CE32

CE34

2

2

0.1U_0402_16V7K

1000P_0402_50V7K

GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

CLK_PCI_LPC
PLT_RST#
EC_RST#
EC_SCI#
ACOFF

KSI0_EC
KSI1_EC
KSI2_EC
KSI3_EC
KSI4_EC
KSI5_EC
KSI6_EC
KSI7_EC
KSO0_EC
KSO1_EC
KSO2_EC
KSO3_EC
KSO4_EC
KSO5_EC
KSO6_EC
KSO7_EC
KSO8_EC
KSO9_EC
KSO10_EC
KSO11_EC
KSO12_EC
KSO13_EC
KSO14_EC
KSO15_EC
KSO16_EC
KSO17_EC

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

PM_SLP_S3#_R

PM_SLP_S5#_R
EC_SMI#
PS_ID
EC_ESB_CLK_R
EC_ESB_DAT
SUSPWRDNACK

SYSTEM_FAN_FB
MXM1_FAN_FB
E51TXD_P80DATA
E51RXD_P80CLK
PCH_PWROK EC_ON
WLES ON/OFF LED#
SG_AMD_BKL

FB_CLAMP_TGL_REQ#
FB_CLAMP

PCH_PWROK

+3VALW_EC +EC_VCCA

2

2

CE37

CE36

1000P_0402_50V7K

1

1

UE1

1

GATEA20/G PIO00

2

KBRST#/GP IO01

3

SERIRQ

4

LPC_FRAME #

5

LPC_AD3

7

LPC_AD2

8

LPC_AD1

10

LPC & MISC

LPC_AD0

12

CLK_PCI_ EC

13

PCIRST#/GPI O05

37

EC_RST#

20

EC_SCII#/ GPIO0E

38

GPIO1D

55

KSI0/GPI O30

56

KSI1/GPI O31

57

KSI2/GPI O32

58

KSI3/GPI O33

59

KSI4/GPI O34

60

KSI5/GPI O35

61

KSI6/GPI O36

62

KSI7/GPI O37

39

KSO0/GP IO20

40

KSO1/GP IO21

41

KSO2/GP IO22

42

KSO3/GP IO23

43

KSO4/GP IO24

44
45
46
47
48
49
50
51
52
53
54
81
82

77
78
79
80

14
15
16
17
18
19
25
28
29
30
31
32
34
36

122
123

KSO5/GP IO25
KSO6/GP IO26
KSO7/GP IO27
KSO8/GP IO28
KSO9/GP IO29
KSO10/G PIO2A
KSO11/G PIO2B
KSO12/G PIO2C
KSO13/G PIO2D
KSO14/G PIO2E
KSO15/G PIO2F
KSO16/G PIO48
KSO17/G PIO49

EC_SMB_C K1/GPIO44
EC_SMB_D A1/GPIO45
EC_SMB_C K2/GPIO46
EC_SMB_D A2/GPIO47

6

PM_SLP_ S3#/GPIO04
PM_SLP_ S5#/GPIO07
EC_SMI#/G PIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PW M/GPIO11
FAN_SPEE D1/GPIO14
EC_PME#/ GPIO15
EC_TX/GPIO 16
EC_RX/GP IO17
PCH_PW ROK/GPIO18
SUSP_LE D#/GPIO19
NUM_LED#/ GPIO1A

XCLKI/GP IO5D
XCLKO/GP IO5E

Int. K/B
Matrix

1 2

9

22

33

EC_VDD/VCC

EC_VDD/VCC

PWM Output

DA Output

PS2 Interface

SPI Device Interface

SM Bus

GPIO

GND/GND

11

24

RE44
0_0402_5%

KB930@

1 2

67

96

125

111

EC_VDD0

EC_VDD/VCC

EC_VDD/VCC

EC_VDD/VCC

EC_VDD/AVCC

BATT_TEMP/AD0 /GPIO38

AD Input

CPU1.5V_ S3_GATE/GPX IOA00

WOL_E N/GPXIOA01

VCIN0_PH/ GPXIOD00

SPI Flash ROM

ENBKL/AD 6/GPIO40

PECI_KB9 30/AD7/GPI O41

BATT_CHG_LE D#/GPIO52

CAPS_LE D#/GPIO53

GPIO

BATT_LOW _LED#/GPIO5 5

PM_SLP_ S4#/GPIO59

EC_RSMRST#/ GPXIOA03
EC_LID_O UT#/GPXIOA04

PROCHOT_IN/G PXIOA05

H_PROCHOT#_ EC/GPXIOA0 6

VCOUT0_PH/G PXIOA07

GPO

PBTN_OUT#/GP XIOA09

PCH_APW ROK/GPXIO A10

SA_PGOO D/GPXIOA11

GPI

LID_SW #/GPXIOD04

PECI_KB9 012/GPXIO D07

GND/GND

GND/GND

AGND/AGND

GND/GND

GND0

35

69

94

20mil

113

ECAGND

LE44
FBMA-L11-160808-800LMT_0603

1 2

1

0.1U_0402_16V7K
CE33

ECAGND

2

@

1 2

RE47 0_0402_1%

Reserved for KB9012

21

GPIO0F

23

BEEP#/G PIO10

26

GPIO12

27

ACOFF/GPI O13

63
64

AD1/GPIO 39

AD3/GPIO 3B
AD4/GPIO 42

IREF/GPIO 3E

EAPD/GPI O4D

SPIDI/GPI O5B
SPIDO/GP IO5C
SPICLK/G PIO58

SPICS#/G PIO5A

SYSON/GPI O56
VR_ON/GP IO57

GPXIOD06

V18R

65
66
75
76

68
70
71
72

83
84
85
86
87
88

97
98
99
109

119
120
126
128

73
74
89
90
91
92
93
95
121
127

100
101
102
103
104
105
106
107
108

110
112
114
115
116
117
118

124

ADP_I/AD2 /GPIO3A

IMON/AD5/G PIO43

DAC_BRIG/ GPIO3C

EN_DFAN1/ GPIO3D

CHGVADJ/G PIO3F

EC_MUTE#/GP IO4A

USB_EN#/ GPIO4B

CAP_INT#/G PIO4C

TP_CLK/GP IO4E

TP_DATA/GPIO 4F

ME_EN/GP XIOA02

FSTCHG/GPIO 50

PWR_LE D#/GPIO54

BKOFF#/G PXIOA08

AC_IN/GPX IOD01

EC_ON/GP XIOD02

ON/OFF/GP XIOD03

SUSP#/GP XIOD05

KB9012QF-A3_LQFP128_14X14

Security Classification

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

+3VLP

EN_TPLED#
BEEP#
SYSTEM_FAN_PWM
MXM1_FAN_PWM

BATT_TEMP
EAPD#_R
ADP_I
AD_BID0
USBCHG_DET_EC#
ENBKL

RE68 0_0402_5%~D

M_THERMAL#
EC_ENVDD
LCD_TEST

EC_MUTE#
IMVP_PWRGD
LCD_BKL_EN
EC_LID_OUT#
TP_CLK
TP_DATA

CPU1.5V_S3_GATE
EN_WOL#
HDA_SDO
VCIN0_PH

PWRSHARE_EN_EC#
PWRSHARE_OE#
VPK_EN
3V_F347_ON

KB_DET#_EC
PCIE_WAKE#_EC
PCH_DPWROK
BATT_CHG_LED#
CAPS_LED#
PWR_LED#
BATT_LOW_LED#
SYSON
IMVP_VR_ON
PM_SLP_S4#_R

PCH_RSMRST#

VCIN1_PH
H_PROCHOT#_EC
VCOUT0_PH#
BKOFF#
PBTN_OUT#
PCH_PWR_EN
VPK_DET#

ACIN

ON/OFF
LID_SW_IN#
SUSP#
USB_PWR_EN#
EC_PECI

+V18R

12

RE114 0_0402_5%~D
RE82 0_0402_5%~D

RE81 0_0402_5%~D

CE47

RE74 43_0402_1%

4.7U_0805_10V4Z~D

1

CE48

2

Issued Date

EC_ESB_CLK

@

33_0402_5%~D

22P_0402_50V8J~D

1 2

@

CE39

1

2

EN_TPLED# <48>
BEEP# <45>
SYSTEM_FAN_PWM <54>
MXM1_FAN_PWM <53>

ADP_I <57,63>

ENBKL <40, 42>

ODD_EJECT# <50>
M_THERMAL# <12,13, 14,15>
EC_ENVDD <33,42>
LCD_TEST <33,42>

EC_MUTE# <45>
IMVP_PWRGD <6, 17,62>
LCD_BKL_EN <33>
EC_LID_OUT# <19>
TP_CLK <53>

TP_DATA <53>

CPU1.5V_S3_GATE <10>

EN_WOL# <44>

HDA_SDO < 16>

VCIN0_PH <57>

PWRSHARE_EN_EC# <52>
PWRSHARE_OE# <52>
VPK_EN <53>

3V_F347_ON <47>

1 2
1 2

PCH_DPWROK <17>
BATT_CHG_LED# <47>
CAPS_LED# <53>
PWR_LED#
BATT_LOW_LED# <47>
SYSON <56, 59,60>
IMVP_VR_ON <62>

1 2

PCH_RSMRST# <17>

VCIN1_PH <57>

VCOUT0_PH# <58>
BKOFF# <40,42>
PBTN_OUT# <6,17>

PCH_PWR_EN <35,56>
VPK_DET# <53>

100P_0402_50V8J~D

12

ACIN <17,29,47,57, 63>

EC_ON <58>

ON/OFF <55>

LID_SW_IN# <19,47,48,53>

SUSP# <10,56,59,61>

USB_PWR_EN# <52,53>

1 2

Please place RE74
close to EC with in 750mil

12

CE51 47P_0402_50V8J~D

@

HDMI_IN_SELECT#<33,42>

HDMI_IN_CAB_DET#<37>

DGPU_HOLD_RST#<17>

HDMI_IN_OUT_DDC<35>

2012/06/22 2013/06/21

ECAGND

12

CE42 100P_0402_50V8J~D

RE63 0_0402_5%~D@

12

RE64 0_0402_5%~D

12

KB_DET# <53>

PCIE_WAKE# <17, 44,51>

PM_SLP_S4# <17>

H_PECI <6,21>

EC_ESB_CLK

HDMI_TOGGLE<37>

DGPU_PWR_EN<29,56>

DGPU_PWROK<29,30>

HDMI_TOGGLE

RST#

EC_ESB_DAT

DEPOP#_EC

HDMI_IN_SELECT#

HDMI_IN_CAB_DET#

DGPU_PWR_EN

DGPU_PWROK

DGPU_HOLD_RST#

HDMI_IN_OUT_DDC

Compal Secret Data

Deciphered Date

2

ECAGND <57>

BATT_TEMP <57,63>
PM_SLP_SUS# <17>
EAPD# <45>

1

2

3

4

5

6

7

8

9

10

11

12

RE40

Reserve for EMI
please close to UE2

DEPOP#_EC

*

PCH_PWR_EN H_PROCHOT#_EC need add

TH_OVERT#< 29>

UE2

ESB_CLK

GPIO00

RST#

ESB_DAT

GPIO01

GPIO02

GPIO03

GPIO04

GPIO05

GPIO06

GPIO07/C AS_CLK

GND

KC3810_QFN24_4X4

RE79 0_0402_5%~D

GPIO08/C AS_DAT

GPIO0C/P WM0

GPIO0D/P WM1

GPIO0E/P WM2

GPIO0F/P WM3

GPIO10/E SB_RUN#

GPIO11/B aseAddOpt

TP_CLK

TP_DATA

RE62

0_0402_5%~D

DEPOP#

1 2

1

D

2

G

10K_0402_5%~D

@

RE65

1 2

Board ID

+3VALW_EC

Ra

1 2

Rb

1 2

BOARD ID Table

Board
ID

0
1
2
3
4
5
6
7

1 2

13

TEST_EN#

14

15

GPIO09

16

GPIO0A

17

GPIO0B

18

19

20

21

22

23

24

VCC

GND

25

Title

EC ENE-KB9012QF,KC3810

e Document Number Rev

Siz

Custom

LA-9331P

Date: Sheet of

QE21

@

S

SSM3K7002F_SC59-3~D

3

RE67
100K_0402_5%~D

AD_BID0

1

RE70
0_0402_5%

2

PCB
Revision

0.1 (SSI)

0.2 (PT)

0

.3 (ST)

0.4 (QT)

1.0 (MP)

TH_OVERT#_EC

HDMI_IN_OUT_HPD

HDMI_SW

HDMI_OUT_EN

TL_ENVDD

EC_INV_PWM

HDMI_IN_EN

TH_OVERT#_EC

DP_MXM_CARD_SEL

EC_AC_BAT#

EN_CAM

+3VALW_EC

0.1U_0402_16V4Z~D
CE50

60 mil

1

2

Compal Electronics, Inc.

RE354.7K_0402_5%~D

12

RE414.7K_0402_5%~D

12

DEPOP# <45>

CE46

0.1U_0402_16V4Z~D

Rb

0

8.2K +/- 5%

18K +/- 5%

33K +/- 5%

56K +/- 5%

100K +/- 5%

HDMI_IN_OUT_HPD <35>

HDMI_SW <35>

HDMI_OUT_EN <35>

TL_ENVDD <40,42>

EC_INV_PWM <42>

HDMI_IN_EN <37>

DP_MXM_CARD_SEL <30,32>

EC_AC_BAT# <29>

EN_CAM <42>

1

+5VS

0.1

40 61Friday, June 22, 2012

5

+LAN_IO

12

RL7
0_0402_5%~D

D D

4.7K_0402_5%~D

4.7K_0402_5%~D

4.7K_0402_5%~D

The pull-up resisters might not be
necessory due to existence
on PCH side.

RL10

RL11

RL15

12

PCIE_WAKE#

12

CLKREQ_LAN#_R

12

PLT_RST#

4

PCIE_PRX_GLANTX_P1_C

PCIE_PRX_GLANTX_P1<20>

PCIE_PRX_GLANTX_N1<20>

PCIE_PTX_GLANRX_P1<20>

PCIE_PTX_GLANRX_N1<20>

CLK_PCIE_LAN<18>

CLK_PCIE_LAN#<18>

LANCLK_REQ#<18>

PLT_RST#<6,17,43,51,53>

PCIE_WAKE#<17,43,51>

4

12

GND2GND

RL28

0_0402_5%

OSC1OSC

YL1

3

25MHZ_10PF_7V25000014

2

1

15P_0402_50V8J~D

2

CL51

CL52

1

CL1 0. 1U_0402_16V7K~D

CL4 0. 1U_0402_16V7K~D

RL12 0_0402_5%~D

+LAN_IO

LAN_ACTIVITY#<53>
LAN_LINK#_R<53>
LAN_LED2#_R<53>

15P_0402_50V8J~D

12

PCIE_PRX_GLANTX_N1_C

12

PCIE_PTX_GLANRX_P1

PCIE_PTX_GLANRX_N1

CLK_PCIE_LAN

CLK_PCIE_LAN#

CLKREQ_LAN#_R

12

PLT_RST#

PCIE_WAKE#

RL13 30K_0402_5%

RL29

5.1K_0402_1%~D

1 2

3

UL1

30

TX_P

29

TX_N

35

RX_P

36

RX_N

33

REFCLK_P

32

REFCLK_N

4

CLKREQ#

2

PERST#

3

WAKE#

25

SMCLK

26

SMDATA

28

NC

27

TESTMODE

41

XTLI
XTLO

1 2

LAN_ACTIVITY# +RBIAS
LAN_LINK#_R
LAN_LED2#_R

LAN_LINK#_R

GND

8

XTLI

7

XTLO

5

ISOLAT#

38

LED_0

39

LED_1

23

LED_2

E2201-BL3A-R_QFN40_5X5

VDD33

AVDD33

AVDDL
AVDDL
AVDDL
AVDDL

AVDDL_REG

AVDDH

AVDDH_REG

DVDDL_REG

TRXP0
TRXN0
TRXP1
TRXN1
TRXP2
TRXN2
TRXP3
TRXN3

RBIAS

LX

PPS

1
16

13
19
31
34
6

22
9

37

11
12
14
15
17
18
20
21

40

24

10

W=40mils

+AVDDL

+AVDDH

+DVDDL

LAN_MDIP0
LAN_MDIN0
LAN_MDIP1
LAN_MDIN1
LAN_MDIP2
LAN_MDIN2
LAN_MDIP3
LAN_MDIN3

RL14

1 2

2.37K_0402_1%~D

+LAN_IO

2

LAN_MDIP0 <53>
LAN_MDIN0 <53>
LAN_MDIP1 <53>
LAN_MDIN1 <53>
LAN_MDIP2 <53>
LAN_MDIN2 <53>
LAN_MDIP3 <53>
LAN_MDIN3 <53>

1

1U_0402_6.3V6K~D

RL17
470K_0402_5%~D

1 2

13

D

QL2
SSM3K7002FU_SC70-3

S

W=40mils

CL20

EN_WOL

+3VALW

1

2

QL1
FDC655BN_NL_SSOT6~D

D

6

S

45
2
1

G

3

RL19

1 2

1.5M_0402_5%~D

+LAN_IO_R

RL16

1

CL36

0.1U_0402_25V6

2

1 2

0_0805_5%~D

W=40mils

+LAN_IO

CL21

W=20milsW=20mils

1

1

CL54

2

2

1U_0402_6.3V6K~D

close to Lan pin31

1

CL30

2

4.7U_0603_6.3V6K~D

1A

1

1

1

CL28

1

1

CL22

2

1000P_0402_50V7K~D

1

1

2

CL24

CL23

2

0.1U_0402_16V7K~D
1U_0402_6.3V6K~D

close to Pin 1

1

CL25

2

10U_0603_6.3V6M~D

1

CL41

CL50

2

2

0.1U_0402_16V7K~D

10U_0603_6.3V6M~D

close to Pin 16

CL35

1

2

1U_0402_6.3V6K~D

2

2

1U_0402_6.3V6K~D

CL53

CL29

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

close to Lan pin34 close to Lan pin 6

close to Lan pin19

1

CL32

CL31

2

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

close to Lan pin13

+AVDDH+AVDDL +DVDDL

1

2

0.1U_0402_16V7K~D

1

CL33

1

CL26

2

2

1U_0402_6.3V6K~D

close to Lan pin9

CL34

0.1U_0402_16V7K~D

close to Lan pin22

1

2

0.1U_0402_16V7K~D

W=20mils

1

CL27

CL39

2

1U_0402_6.3V6K~D

close to Lan pin37

1

2

0.1U_0402_16V7K~D

C C

B+_BIAS

+3VALW

RL18

10K_0402_5%~D

B B

1 2

EN_WOL#<43>

2

G

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

2

Title

ze Document Number Rev

Si

Date: Sheet of

Compal Electronics, Inc.

GLAN AR8151 AL1A/ RJ45

LA-9331P

1

41 61Friday, June 22, 2012

0.1

A

+3V_DVDD

LA1

CA16

+3V_DVDD

HDMI_IN_AUDIO_CODEC<37>

+3V_DVDD

10U_0805_10V4Z~D

0.1U_0402_10V6K~D

CA3

CA4

1

2

2

1

10U_0805_10V4Z~D

0.1U_0402_10V6K~D

+3V_DVDD

CA9

CA8

12

1

2

2

1

PCH_AZ_CODEC_SDIN0<16>

1U_0402_6.3V6K~D

1

CA10

PCH_AZ_CODEC_SDOUT<16>

PCH_AZ_CODEC_BITCLK<16>

PCH_AZ_CODEC_SYNC<16>

PCH_AZ_CODEC_RST#<16>

MIC2-VREFO-L MIC_B_PLUG#
LINE2-VREFO
MIC2-VREFO-R

2

20K_0402_1%~D

12

RA14

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

CA27

CA28

1

1

2

2

BEEP#< 43>

HDA_SPKR<16>

2

1

CA18

CA17

10U_0805_10V4Z~D

1

2

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

CA30

CA29

1

1

2

2

1 2

CA38 0. 1U_0402_16V4Z~D

1 2

CA39 0. 1U_0402_16V4Z~D

1 2

CA58 0. 1U_0402_16V4Z~D

1

2

0.1U_0402_10V6K~D

10U_0603_6.3V6M~D

CA31

BEEP_C#

PCH_SPKR_C

+3VS

1 2

RA1 0_0805_5%~D

+3V_DVDD

1 1

FBMA-L11-201209-221LMA30T_0805

2 2

3 3

4 4

Close to Pin39

+5VS

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

CA11

2

1

RA6

RA8

CA19

2.2U_0402_6.3V6M~D

2

1

B

2

CA2

1

0.1U_0402_10V6K~D

2

1

1 2

22_0402_5%

1 2

0_0402_5%

CA22

1U_0402_6.3V6K~D

1

2

1 2

100K_0402_5%~D

1 2

100K_0402_5%~D

1 2

100K_0402_5%~D

CA12

1

2

RA59

RA61

RA82

4.7U_0805_25V6-K

12

4.7U_0805_25V6-K

12

1

+

2

10U_0805_10V4Z~D

CA23

HDA_SDIN0_R

CA15

CA1

23
39

11

7

25

22P_0402_50V8J~D

8
4
5

2

9
6

1

1
29
30

24
21
35
40
41
38

CA20
100U_B3_6.3VM_R55M

20
10

28
22
42

49

0_0402_5%~D

1 2

UA1

HVDD
LDO-IN

DVDD
DVDD-IO
DVDD-IO-CP

SDATA-IN
SDATA-OUT
BCLK
SYNC
RESETB

MIC2-VREFO
LINE2-VRE FO
MIC1-VREFO

CBP
CBN
JDREF
LDO-CAP
VREF
VRP

CPVEE
REGREF

CPVREF
AVSS1
AVSS2

Thermal PAD

ALC3661-CG_MQFN48_6X6~D

+3.3V_AVDD

RA60

LINE2-IN-R/S LEEVE

LINE2-IN-L/ RING2

GPIO1/DMI C-DATA
GPIO2/Com bo-Jack1
GPIO3/Com bo-Jack2

RA44 0_0402_5%~D

1 2

RA45 0_0402_5%~D

1 2

RA47 0_0402_5%~D

1 2

RA48 0_0402_5%~D

1 2

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

CA59

CA37

1

1

1

2

2

2

PC_BEEP

RA62

@

10K_0402_5%~D

1 2

C

PCBEEP

LINE1-R
LINE1-L

MIC1-R

MIC1-L/MIC-CA P

MIC2-R
MIC2-L

SENSE A
SENSE B

SURR-R
SURR-L

FRONT-R

FRONT-L

SPDIF-OUT

SPDIF-in

GPIO/DMIC-CL K

EAPD

10U_0603_6.3V6M~D

CA35

D

RA2 0_0402_5%

1 2

RA3 0_0402_5%

1 2

RA4 0_0402_5%

1 2

CA5

PC_BEEP

1 2

2

0.1U_0402_10V6K~D

46
45

SLEEVE

32

RING2

31

37
36
48
47

RA9

1 2

34

39.2K_0402_1%

33

27
26
19

CEN

18

LFE

44
43

15
16

12
13
17

GPIO3

3

14

EAPD# <43>

AGNDGND

SPK_MUTE#<46>

HP_MUTE#

1 2

MIC2-R
MIC2-L

HP1_A_R
HP1_A_L
HP2_D_L
HP2_D_R

INT-SPK-R <46>
INT-SPK-L <46>

I2S_DAT/SPDIF_IN <37>

DMIC_CLK <33,42>
DMIC0 <33,42>

CA68 0.1U_0402_16V7K
CA69 0.1U_0402_16V7K
CA70 0.1U_0402_16V7K
CA71 0.1U_0402_16V7K

SPK_MUTE#

+3V_DVDD

RA17
10K_0402_1%

1 2

1

CA13

10U_0805_10V4Z~D

1 2
1 2
1 2
1 2

DA9
BAT54CW_SOT323-3

3

1

2

RA13
10K_0402_1%

1 2

DA10

3

2

BAT54AW_SOT323-3~D

DEPOP#

GPIO3

AGNDGND

EC_MUTE#

EAPD#

RA11

1 2

10K_0402_1%

RA12

1 2

5.1K_0402_1%

DEPOP# <43>

E

+3.3V_AVDD+3V_DVDD

HPOUT2-JD

HPOUT-JD

EC_MUTE# <43>

F

S1 (Out + In) : Front L/R + HP1 + MIC (auto-sense)

LINE2-VREFO

LA2

12

0_0603_5%~D

1 2

1 2

LA3

0_0603_5%~D

UA2

A1

INL

A3

INR

B1

/MUTE

B3

SET

MAX9892ERT+T_UCSP6~D

1

CA61 100P_0402_50V8J~D

2

1

2

CA60 100P_0402_50V8J~D

LINE2-VREFO

+3.3V_AVDD

B2

VDD

GND

A2

RA76 18_0402_5%~D

HP1_A_L HP1_A_L_C

1 2

HP1_A_R

1 2

RA77 18_0402_5%~D

HP1_A_L_L

RA5 100_0402_1%

HP1_A_R_L

RA7 100_0402_1%

HP_MUTE#

Setting the Tur n-Off Time:
Ton (ms) = 0.02 x Cset (pF)

1 2

1 2

CA14

0.1U_0402_16V4Z~D

HP1_A_L_L

HP1_A_R_L

S2 (Out) :Center + HP2

LA4

RA78 18_0402_5%~D

HP2_D_L

1 2

RA79 18_0402_5%~D

HP2_D_R

HP2_D_L_R

RA15 100_0402_1%

HP2_D_R_R

RA16 100_0402_1%

HP_MUTE#

Setting the Tur n-Off Time:
Ton (ms) = 0.02 x Cset (pF)

S3 (Out) : Rear L/R

MIC2-L

1 2

CA21 4.7U_0805_25V6-K

MIC2-R

1 2

CA24 4.7U_0805_25V6-K

LINE_B_L_R

RA54 100_0402_1%

LINE_B_R_R
HP_MUTE#

1 2

RA55 100_0402_1%

1 2
1 2

RA57 0_0402_5%

Setting the Tur n-Off Time:
Ton (ms) = 0.02 x Cset (pF)

1 2

1 2

1 2

0.1U_0402_16V4Z~D

LINE_B_L_R

LINE_B_R_R

DEPOP#_R

CA40

0.1U_0402_16V4Z~D

CA25

12

HP2_D_L_R

12

0_0603_5%~D

1 2

HP2_D_R_R

MIC2-VREFO-L

1 2

UA3 MAX9892ERT+T_UCSP6~D

A1

INL

A3

INR

B1

/MUTE

B3

SET

RA362

2.2K_0402_5%~D

RA80

75_0402_1%~D

LINE_B_L_RR

1 2

LINE_B_R_RR

1 2

RA81

75_0402_1%~D

RA363

MIC2-VREFO-R

2.2K_0402_5%~D

UA7 MAX9892ERT+T_UCSP6~D

A1

INL

A3

INR

B1

/MUTE

B3

SET

CA63

LA5

0_0603_5%~D

CA62

VDD

GND

A2

@

12

@

12

+3.3V_AVDD

VDD

GND

A2

B2

RA360

2.2K_0402_5%~D

HP1_A_R_C

RA361

2.2K_0402_5%~D

HP2_D_L1_JK

1

2

100P_0402_50V8J~D

HP2_D_R1_JK

1

2

100P_0402_50V8J~D

+3.3V_AVDD

B2

LA6

0_0603_5%~D

1 2

1 2

LA7

0_0603_5%~D

G

12

12

100P_0402_50V8J~D

CA64

CA65

SLEEVE
RING2

HPOUT-JD

DA6

1

AZ5125-02S.R7G_SOT23-3

Place close to Jack

DA8

1

AZ5125-02S.R7G_SOT23-3

Place close to Jack

DA11

1

AZ5125-02S.R7G_SOT23-3

Place close to Jack

HPOUT2-JD

DA7

1

AZ5125-02S.R7G_SOT23-3

Place close to Jack

DA12

1

AZ5125-02S.R7G_SOT23-3

LINEIN_B_L_C

1

MIC_B_PLUG#

2

LINEIN_B_R_C

1

2

100P_0402_50V8J~D

DA3

1

AZ5125-02S.R7G_SOT23-3

Place close to Jack

JHP1

6
1
2

3
4

5

C-H_13-18200610CP

CONN@

2

3

2

3

2

3

JHP2

6
1
2

3
4

5

C-H_13-18200610CP

CONN@

2

3

2

3

2

3

RING2

HP1_A_L_C

HP1_A_R_C

SLEEVE

HPOUT-JD

HP2_D_L1_JK

HP2_D_R1_JK

HPOUT2-JD

MIC_B_PLUG#

JHP3

6
1
2

3
4

5

C-H_13-18200610CP

CONN@

LINEIN_B_L_C

LINEIN_B_R_C

H

G

7
8

G

G

7
8

G

G

7
8

G

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

D

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

E

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

F

Compal Electronics, Inc.

Title

HD Audio ALC3661

Size Document Number Rev

Custom

LA-9331P

Date: Sheet of

G

42 61Friday, June 22, 2012

H

0.1

5

LA8
FBMA-L11-160808-121LMA30T_0805

INT-SPK-L<45>

INT-SPK-R< 45>

1

1

2

2

1 2

CA42

0.1U_0402_25V6K~D

1 2

12

CA43

1U_0603_25V6K

Close to UA2
Pin7,15,16,27,28

CA67

SPK_CD_L

1 2

470P_0402_50V7K~D

CA66

SPK_CD_R

470P_0402_50V7K~D

12

CA44

1U_0603_25V6K

B+

CA41

10U_1206_25V6M

D D

+PVDD

12

CA45

1U_0603_25V6K

RA63

1 2

240K_0402_1%

RA65

1 2

240K_0402_1%

40mil

12

CA46

1U_0603_25V6K

12

TPA3113 for Speaker

+5VS

@

RA72
100K_0402_1%

1 2

C C

RA74
100K_0402_1%

1 2

@

RA73
100K_0402_1%

1 2

GIN1GIN0

RA75
100K_0402_1%

1 2

GAIN1 GAIN0

0

0

1 0

1 1

AV(inv)

0

20dB

1

26dB

32dB

36dB

CA47

1U_0603_25V6K

12

RA64
10K_0402_5%

@

12

RA66
10K_0402_5%

@

+3VALW

SPK_MUTE#<45>

INPUT
IMPEDANCE

60Kohm

30Kohm

15Kohm

9Kohm

4

CA50

1 2

CA53

1 2

1 2

1 2

0.027U_0402_16V6K

0.027U_0402_16V6K

RA68
100K_0402_5%

@

RA69
0_0402_5%

RA71

100K_0402_5%

+AVCC

+PVDD

AMP_LEFT_C

1 2

0.027U_0402_16V6K

CA51

AMP_RIGHT_C

1 2

0.027U_0402_16V6K

CA54

12

1 2

0_0402_5%

B+

UA8

7

AVCC

15

PVCCR

16

PVCCR

27

PVCCL

28

PVCCL

3

LINP

4

LINN

12

RINP

11

RINN

GIN0

GIN1

EAPD_R

RA83

5

GAIN0

6

GAIN1

1

SD#

2

FAULT#

13

NC

29

GND

TPA3113D2PWPR_H TSSOP28

RA364 10_0402_5%~D

1 2

BSPL

OUTPL

OUTNL

BSNL

BSPR

OUTPR

OUTNR

BSNR

PBTL

PLIMIT

GVDD

PGND
PGND
AGND

1

2

3

+AVCC

10U_0603_6.3V6M~D

CA72

2

OUTPL

26

25

23

BSNL

22

BSPR

17

18

20

BSNR

21

14

PLIMIT

10

+GVDD

9

24
19
8

CA49

1 2

0.22U_0603_25V7K

CA52

0.22U_0603_25V7K

1 2

1 2

CA55

0.22U_0603_25V7K

+GVDD

1U_0603_25V6K

CA57

12

OUTPL

OUTNL

OUTPR

OUTNR

+GVDD

12

RA67

28.7K_0402_1%

1U_0603_25V6K

12

CA56

12

RA70
10K_0402_1%

CA48

0.22U_0603_25V7K

BSPL

1 2

OUTNL

OUTPR

OUTNR

SPK_L1-_CONN
SPK_L2+_CONN
SPK_R1-_CONN
SPK_R2+_CONN

1

CA36

2

CA34

1000P_0402_50V7K

1

CA33

2

1000P_0402_50V7K

LA9
HCB2012KF-121T50_0805

1 2

5A/120ohm/100MHz

LA10
HCB2012KF-121T50_0805

1 2

5A/120ohm/100MHz

LA11
HCB2012KF-121T50_0805

1 2

5A/120ohm/100MHz

LA12
HCB2012KF-121T50_0805

1 2

5A/120ohm/100MHz

1

1

DA4

CA32

2

2

1000P_0402_50V7K

1000P_0402_50V7K

SPK_L2+_CONN

SPK_L1-_CONN

SPK_R2+_CONN

SPK_R1-_CONN

Speaker amp impedance of JBL is 4 ohm.

15 mils trace

2

1

AZ5125-02S.R7G_SOT23-3

2

3

DA5

1

AZ5125-02S.R7G_SOT23-3

1

Speaker Connector

3

JSPK1

1

1

2

2

3

3

4

4

5

GND

6

GND

ACES_50279-0040N-001

CONN@

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

Title

Speaker AMP/CardReaser B

ze Document Number Rev

Si

Custom

LA-9331P

2

Date: Sheet of

1

43 61Friday, June 22, 2012

0.1

5

4

3

2

1

1

2

CONN@

+3.3V_F347

0.1U_0402_16V4Z~D

1

2

W=40mils

C7

JP1

GND1
GND2

+3.3V_F347

1K_0402_1%~D

1

1

2

2

3

3

4

4

5

5

6

6

7
8

1

2

1 2

R1 0_0603_5%~D

1 2

0.1U_0402_16V4Z~D

1U_0805_10V7

C3

1

C4

2

R8

+3.3V_F347

PM_SLP_S5#<17,43>

+3.3V_F347_R

22P_0402_50V8J~D

0.1U_0402_16V4Z~D

C2

C1

2

1

1

2

U1

6

P0.0

VDD

P0.1

4

P0.2

D+

5

P0.3

D-

P0.4

7

P0.5

REGIN

8

P0.6

VBUS

P0.7

9

RST#/C2CK

P1.0

P3.0/C2D

P1.1
P1.2

P2.0

P1.3

P2.1

P1.4

P2.2

P1.5

P2.3

P1.6

P2.4

P1.7

P2.5
P2.6
P2.711GND

C8051F347-GQ_LQFP32_7X7

3V_F347_ON< 43>BATT_LOW_LED#<43>

+3.3V_F347

@

C13 0.1U_0402_16V4Z~D

1

2

+3.3V_F347

+3.3V_F347

@

@

@

C16 0.1U_0402_16V4Z~D

C14 0.1U_0402_16V4Z~D

C15 0.1U_0402_16V4Z~D

1

1

1

2

2

2

12

R17

100K_0402_1%~D

SLP_S5

1

D

Q2
SSM3K7002F_SC59-3~D

S

3

12

R21

100K_0402_1%~D

BATT_LOW_LED

1

D

Q6
SSM3K7002F_SC59-3~D

S

3

USB20_P6
USB20_N6

10

18
17
16
15
14
13
12

@

@

C17 0.1U_0402_16V4Z~D

C18 0.1U_0402_16V4Z~D

We are Green SA00003IR20

1

1

2

2

USB20_P6<20>
USB20_N6<20>

@

@

C12 0.1U_0402_16V4Z~D

C11 0.1U_0402_16V4Z~D

1

1

2

2

2

G

2

G

SPI_MOCLK

2

SPI_MOSO

1

SPI_MOSI

32

SPI_MOCS#

31

I2C_DAT

30

I2C_CLK

29

C5 0.1U_0402_16V4Z~D@

28
27

SLP_S3

26

BATT_CHG_LED

25

ACIN#

24

LID_SW_IN#_D

23

BATT_LOW_LED

22

SLP_S5

21

C8 0.1U_0402_16V4Z~D@

20

C9 0.1U_0402_16V4Z~D@

19

3

place R1564 as close as U602

1 2

R4 0_0402_5%~D

1 2

SDMK0340L-7-F_SOD323-2~D

1 2
1 2

+3.3V_F347

+3VALW +3.3V_F347

B+_BIAS

+3VALW

12

R22

100K_0402_1%~D

1

D

Q7
SSM3K7002F_SC59-3~D

2

100K_0402_1%~D

G

12

R25

S

3

SPI_MOCLK_R

R7 1K_0402_5%~D

1 2

SPI_MOSI

SPI_MOCLK_R

1 2

R13 10K_0402_5%~D

1 2

R14 10K_0402_5%~D

1 2

R15 10K_0402_5%~D

+3.3V_F347

2

SI3456DDV-T1-GE3_TSOP6~D

6

2
1

R20

100K_0402_1%~D

1 2

2

I2C_DAT

I2C_CLK

I2C_DAT <48,53>
I2C_CLK <48,53>

R910K_0402_5%

12

LID_SW_IN#

12

D70

MAXIM - LED
MAXIM - GPIO 0100 001b
I2C EEPROM

J11

@

112

JUMP_43X118

Q3

D

S

45

G

3

SSM3K7002F_SC59-3~D

1

D

G

S

3

+3.3V_F347

SPI_MOCS#

1

2

1

2

Q5

0.1U_0402_16V4Z~D

0.1U_0402_25V6K~D

C21

+3.3V_F347

LID_SW_IN# <19,43,48,53>

R1015_0402_5%

12

5

R1215_0402_5%

12

6

1

7

3

8

22P_0402_50V8J~D

C19

1

C20

2

SMBUS ADDRESSDEVICE
0100 000b

1010 000b

100K_0402_1%~D

12

R19

0.1U_0402_25V6K~D

300K_0402_5%~D

R23

1

2

1 2

U2

DI

CLK

CS

HOLD

WP

VCC

EN25Q80A-100HIP_SO8

C23

+3.3V_F347

R24.7K_0402_5%~D

12

R34.7K_0402_5%~D

12

R11 15_0402_5%

2

1 2

SO

4

VSS

4.7U_0603_6.3V6M~D

C22

1

2

+3.3V_F347 behavior

S0 S3 S4 S5

AC IN

BAT only

ON ON ON ON

ON ON OFF OFF

AC mode battery full in S5:turn off ELC controller

SPI_MOSO

STATE

D D

R5 0_0603_5%~D

1 2

+5VALW

R6 0_0603_5%~D@

1 2

+5VS

1U_0805_10V7

C6

+3.3V_F347

0.1U_0402_16V4Z

C10

1

C C

PM_SLP_S3#<17,43>

B B

ACIN<17,29,43,57,63>

BATT_CHG_LED#<43>

A A

2

Cloase to JP1

+3.3V_F347

D

2

G

S

+3.3V_F347

D

2

G

S

+3.3V_F347

D

2

G

S

12

R16

100K_0402_1%~D

SLP_S3

1

Q1
SSM3K7002F_SC59-3~D

3

12

R18

100K_0402_1%~D

ACIN#

1

Q4
SSM3K7002F_SC59-3~D

3

12

R24

100K_0402_1%~D

BATT_CHG_LED

1

Q8
SSM3K7002F_SC59-3~D

3

AMPHE_G846A06201EU

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

ELC (1)

e Document Number Rev

Siz

Custom

LA-9331P

Date: Sheet of

1

44 61Friday, June 22, 2012

0.1

5

4

3

2

1

7313_INT#<53>

D D

R30

C C

B B

PCH_SATALED#<16>

+3.3V_F347

4.7K_0402_1%~D

12

+3.3V_F347

R26

1 2

4.7K_0402_1%~D

4.7K_0402_1%~D

12

R27

4.7K_0402_1%~D

4.7K_0402_1%~D

12

12

R29

R28

4.7K_0402_1%~D

R31

2

G

12

R32

+5VS

12

1

D

S

3

4.7K_0402_1%~D

12

100K_0402_5%~D

R34

SATA_LED_ACT

SSM3K7002F_SC59-3~D

Q12

TP_LED_R_DRV#<53>
TP_LED_G_DRV#<53>
TP_LED_B_DRV#<53>

7313_INT#

12

Reference AD2 AD1 AD0 MAX7313

U605

U608

0 1 0

0 1 1

U? 1 0 0

A A

L/R Tron, Logo, Alien Head, TP

U3

22

INT#/O16

I2C_CLK
I2C_DAT

AD0_0
AD0_1
AD0_2

TP_LED_R_DRV#
TP_LED_G_DRV#
TP_LED_B_DRV#

MAX7313DATG+T_TQFN-EP24_4X4~D

Indicator, Power

I2C_CLK
I2C_DAT

AD2_0
AD2_1
AD2_2

HDD_R_7313#
HDD_G_7313#
HDD_B_7313#

MAX7313DATG+T_TQFN-EP24_4X4~D

1

D

2

G

S

3

1

D

2

G

S

3

1

D

2

G

S

3

19

SCL

20

SDA

18

AD0

23

AD1

24

AD2

14

P12

15

P13

16

P14

17

OSC

GND9GND

U4

22

INT#/O16

19

SCL

20

SDA

18

AD0

23

AD1

24

AD2

14

P12

15

P13

16

P14

17

OSC

GND9GND

HDD_B

Q9
SSM3K7002F_SC59-3~D

HDD_B_7313#

HDD_R

Q10
SSM3K7002F_SC59-3~D

HDD_R_7313#

HDD_G

HDD_G <53>

Q14
SSM3K7002F_SC59-3~D

HDD_G_7313#

I2C_CLK<47,53>

I2C_DAT<47,53>

4.7K_0402_1%~D
R33

Tron Lights,TP
A-panel,B-Panel Logo

Power Button,
Media and Status LED Color

Button,
Indicator Brightness

21

V+

LTRON_LED_R_DRV#

1

P0

LTRON_LED_G_DRV#

2

P1

LTRON_LED_B_DRV#

3

P2

RTRON_LED_R_DRV#

4

P3

RTRON_LED_G_DRV#

5

P4

RTRON_LED_B_DRV#

6

P5

ALIEN_LED_R_DRV#_1

7

P6

ALIEN_LED_G_DRV#_1

8

P7

ALIEN_LED_B_DRV#_1

10

P8

LOGO_LED_R_DRV#

11

P9

LOGO_LED_G_DRV#

12

P10

LOGO_LED_B_DRV#

13

P11

25

21

V+

1

P0

2

P1

3

P2

4

P3

5

P4

6

P5

7

P6

8

P7

10

P8

11

P9

12

P10

13

P11

25

HDD_B <53>

HDD_R <53>

+3.3V_F347

LED_R_7313#_1
LED_G_7313#_1
LED_B_7313#_1

PWR_R_7313#
PWR_G_7313#
PWR_B_7313#

LID_SW_IN#<19,43,47, 53>

+3.3V_F347

0.1U_0402_16V4Z

1

2

LID_SW

0.1U_0402_16V4Z~D

C24

1

2

RTRON_LED_R_DRV# <53>
RTRON_LED_G_DRV# <53>
RTRON_LED_B_DRV# <53>

C25

LED_R_7313#_1 <53>
LED_G_7313#_1 <53>
LED_B_7313#_1 <53>

PWR_R_7313# <53>
PWR_G_7313# <53>
PWR_B_7313# <53>

+5VALW

100K_0402_5%~D

12

1

D

2

G

S

3

SATA_LED_ACT

1

D

2

G

S

3

R35

LID_SW

LID_SW <53>

Q13
SSM3K7002F_SC59-3~D

Q16
SSM3K7002F_SC59-3~D

+5VS

0.1U_0402_16V4Z

C26

1

20mil

2

LID_SW
LOGO_LED_R_DRV#
LOGO_LED_G_DRV#
LOGO_LED_B_DRV#

ALIEN_LED_R_DRV#_1
ALIEN_LED_G_DRV#_1
ALIEN_LED_B_DRV#_1

LOGO Board CONN

B+_BIAS +5VS +5VS_TP_LED

300K_0402_5%~D

R36

1 2

13

D

EN_TPLED#<43>

2

G

Q15

S

Touchpad LED circuit

JLOGO1

1
2
3
4
5
6
7
8

9
10
11
12
13
14

ACES_50224-0120N-001

CONN@

EN_TPLED

SSM3K7002FU_SC70-3~D

+5VS

0.1U_0402_16V4Z

C27

1
2
3
4
5
6
7
8
9
10
11
12
G1
G2

1

2

RTRON_LED_R_DRV#
RTRON_LED_G_DRV#
RTRON_LED_B_DRV#
LTRON_LED_R_DRV#
LTRON_LED_G_DRV#
LTRON_LED_B_DRV#

JTRONF

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND1

12

GND2

ACES_50224-01001-001

CONN@

TRON LED Board (F) CONN

SI3456DDV-T1-GE3_TSOP6~D

6

0.1U_0402_16V4Z

2
1

C29

1

2

1.5M_0402_5%~D

12

Q11

D

S

45

G

3

R37

1

2

1U_0603_10V4Z~D

C32

1

2

0.1U_0402_25V6K~D

C33

+5VS

0.1U_0402_16V4Z

C30

1

2

LTRON_LED_R_DRV#
LTRON_LED_G_DRV#
LTRON_LED_B_DRV#

JTRONL

1

1

2

2

3

3

4

4

5

5

6

6

7

GND

8

GND

E-T_4260-F06N-10L

CONN@

TRON LED Board (L) CONN

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

ELC (2)

e Document Number Rev

Siz

Custom

LA-9331P

Date: Sheet of

1

45 61Friday, June 22, 2012

0.1

A

1 1

+3VS

10U_0805_10V4Z~D

0.1U_0402_16V4Z~D

C35

C34

1

1

2

2

PCH_SMBDATA
PCH_SMBCLK

SATA_PTX_DRX_P1_R
SATA_PTX_DRX_N1_R

SATA_PRX_DTX_P1_RC
SATA_PRX_DTX_N1_RC

HDD_B_PRE1
HDD_A_PRE1

FFS_INT1
FFS_INT2

7

1
2

5
4

17
19

18

3
13
21

FFS_INT1<17>
FFS_INT2<21,50>

PCH_SMBDATA<6,12,13,14,15,19,50,51,53>

PCH_SMBCLK<6,12,13,14,15,19,50,51,53>

FFS_INT1 connect to PCH GPIO & EC
discuss with BIOS to use which pin

2 2

+3VS

RN1 0_0402_5%

CN15 0.01U_0402_16V7K~D

SATA_PTX_DRX_P1<16>

3 3

SATA_PTX_DRX_N1<16>

SATA_PRX_DTX_P1< 16>
SATA_PRX_DTX_N1<16>

1 2

CN16 0.01U_0402_16V7K~D

1 2

CN18 0.01U_0402_16V7K~D

1 2

CN17 0.01U_0402_16V7K~D

1 2

+3VS

1 2

RN2 0_0402_5%@

1 2

RN3 0_0402_5%@

1 2

RN4 0_0402_5%@

1 2

Pin 20:
PARADE PS8250B:
Reserve RN46, Mount RN12

PERICOM PI3EQX6741ST:
Mount RN46, Reserve RN12

ASMEDIA ASM1466:
Mount RN46, Reserve RN12

B

Free Fall Sensor

UN4

LNG3DM

1

VDD_IO

14

VDD

11

INT 1

9

INT 2

7

SDO/SA0

6

SDA / SDI / SDO

4

SCL/SPC

8

CS

LNG3DMTR_LGA16_3X3~D

UN1

EN

A_INp
A_INn

B_OUTp
B_OUTn

B_PRE1
A_PRE1

TEST
GND
GND
EPAD

PS8520BTQFN20GTR2_TQFN20_4X4

6

VDD

16

VDD

10

NC

20

REXT

9

A_PRE0

8

B_PRE0

15

A_OUTp

14

A_OUTn

11

B_INp

12

B_INn

Pin 9:
PARADE PS8250B:
Reserve RN11.

PERICOM PI3EQX6741ST:
Reserve RN11

ASMEDIA ASM1466:
Mount RN11 to pull down

C

10

RES

13

RES

15

RES

16

RES

5

GND

12

GND

2

NC

3

NC

+3VS

0.01U_0402_16V7K

0.1U_0402_25V6K

1

1

CN23

2

2

HDD_REXT_SATA

HDD_A_PRE0
HDD_B_PRE0

SATA_PTX_DRX_P1_RC
SATA_PTX_DRX_N1_RC SATA_PTX_DRX_N1_C

SATA_PRX_DTX_P1_R
SATA_PRX_DTX_N1_R

0_0402_5%

0_0402_5%

CN24

12

RN5

CN19 0.01U_0402_16V7K~D

1 2

CN20 0.01U_0402_16V7K~D

1 2

CN21 0.01U_0402_16V7K~D

1 2

CN22 0.01U_0402_16V7K~D

1 2

HDD_B_PRE0

HDD_B_PRE1

HDD_A_PRE1

HDD_A_PRE0

HDD_REXT_SATA

0_0402_5%

0_0402_5%

12

12

12

@

RN46

@

RN6

RN8 0_0402_5%@

1 2

RN9 0_0402_5%@

1 2

RN10 0_0402_5%@

1 2

RN11

1 2

RN12

1 2

@

RN7

SATA_PTX_DRX_P1_C

SATA_PRX_DTX_P1_C
SATA_PRX_DTX_N1_C

2K_0402_5%

5.1K_0402_1%

D

+3VS

+5VS

Close to JHDD1

0.1U_0402_16V4Z~D

1

1

CN1

2

2

SATA_PTX_DRX_P0<16>
SATA_PTX_DRX_N0<16>

SATA_PRX_DTX_N0<16>
SATA_PRX_DTX_P0<16>

+3VS

+5VS

0.1U_0402_16V4Z~D

1

1

CN10

2

2

1U_0402_6.3V4Z~D

10U_0805_10V4Z~D

0.1U_0402_16V4Z~D

1000P_0402_50V7K~D

CN2

CN4

1

1

1

CN3

2

2

2

CN6 0.01U_0402_16V7K~D

1 2

CN7 0.01U_0402_16V7K~D

1 2

CN8 0.01U_0402_16V7K~D

1 2

CN9 0.01U_0402_16V7K~D

1 2

HDD_DET#<21>

FFS_INT2_CONN<50>

Close to JHDD2

1000P_0402_50V7K~D

1U_0402_6.3V4Z~D

0.1U_0402_16V4Z~D

10U_0805_10V4Z~D

CN13

CN12

1

1

CN11

1

2

2

2

47P_0402_50V8J~D

2

CN5

1

47P_0402_50V8J~D

CN14

2

1

CN59

SATA_PTX_DRX_P0_C
SATA_PTX_DRX_N0_C

SATA_PRX_DTX_N0_C
SATA_PRX_DTX_P0_C

+3VS

+5VS

FFS_INT2_CONN

CN60

SATA_PTX_DRX_P1_C
SATA_PTX_DRX_N1_C

SATA_PRX_DTX_N1_C
SATA_PRX_DTX_P1_C

+3VS

+5VS

FFS_INT2_CONN

JHDD1

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

VCC3.3

9

VCC3.3

10

VCC3.3

11

GND

12

GND

13

GND

14

VCC5

15

VCC5

16

VCC5

17

GND

18

DAS/DSS

19

GND

20

VCC12

21

VCC12

22

VCC12

FOX_LD2822F-SAQL6

CONN@

JHDD2

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

VCC3.3

9

VCC3.3

10

VCC3.3

11

GND

12

GND

13

GND

14

VCC5

15

VCC5

16

VCC5

17

GND

18

DAS/DSS

19

GND

20

VCC12

21

VCC12

22

VCC12

FOX_LD2822F-SAQL6

CONN@

23

G1

24

G2

23

G1

24

G2

E

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

SATA HDD1 & HDD2/FFS

Size Document Number Rev

Custom

LA-9331P

Date: Sheet of

E

46 61Friday, June 22, 2012

0.1

A

ODD power

1 1

2 2

ODD_EN#<21>

SATA_ODD_PTX_DRX_P2<16>
SATA_ODD_PTX_DRX_N2<16>

SATA_ODD_PRX_DTX_P2<16>
SATA_ODD_PRX_DTX_N2<16>

RN26

300K_0402_5%~D

2

+5VS

B+_BIAS

1 2

ODD_EN

13

D

QN1

G

SSM3K7002FU_SC70-3~D

S

CN27 0.01U_0402_16V7K~D

1 2

CN28 0.01U_0402_16V7K~D

1 2

CN25 0.01U_0402_16V7K~D

1 2

CN26 0.01U_0402_16V7K~D

1 2

+3VS

SI3456DDV-T1-GE3_TSOP6~D

6

1U_0402_6.3V6K~D

2

CN39

1

1

2

+3VS

RN13 0_0402_5%

RN14 0_0402_5%@
RN15 0_0402_5%@

RN16 0_0402_5%@

QN2

D

G

1 2

1 2
1 2

1 2

S

45

3

1.5M_0402_5%~D

RN27

1 2

1

2

SATA_PTX_DRX_P2_R
SATA_PTX_DRX_N2_R

SATA_PRX_DTX_P2_R
SATA_PRX_DTX_N2_R

B

+5VS_ODD

0.1U_0402_25V6K~D
CN40

ODD Redriver

7

1
2

5
4

ODD_B_PRE1

17

ODD_A_PRE1

19

18

3
13
21

+5VS_ODD

UN2

EN

A_INp
A_INn

B_OUTp
B_OUTn

B_PRE1
A_PRE1

TEST
GND
GND
EPAD

PS8520BTQFN20GTR2_TQFN20_4X4

REXT

A_PRE0
B_PRE0

A_OUTp
A_OUTn

B_INp
B_INn

6

VDD

16

VDD

10

NC

20

9
8

15
14

11
12

C

0.1U_0402_16V4Z~D

10U_0805_10V4Z~D

1U_0402_6.3V4Z~D

1000P_0402_50V7K~D

CN36

CN38

CN37

CN35

1

1

1

1

2

2

2

2

ODD_EJECT#< 43>

1, Host generate Low pulse 40 ms to eject ODD
2, After this pulse, signal remain high a nd no
pulse is allowed withi n 7s

Placea caps. near ODD CONN.

+3VS

G

2

FFS_INT2 FFS_INT2_CONN

FFS_INT2<21,49>

+3VS

0.01U_0402_16V7K

0.1U_0402_25V6K

1

1

CN33

2

2

ODD_REXT_SATA

ODD_A_PRE0
ODD_B_PRE0

SATA_PTX_DRX_P2_RC
SATA_PTX_DRX_N2_RC SATA_PTX_DRX_N2_C

SATA_PRX_DTX_P2_RC
SATA_PRX_DTX_N2_RC

SSM3K7002FU_SC70-3~D

0_0402_5%

0_0402_5%

CN34

12

RN17

CN29 0.01U_0402_16V7K~D

1 2

CN30 0.01U_0402_16V7K~D

1 2

CN31 0.01U_0402_16V7K~D

1 2

CN32 0.01U_0402_16V7K~D

1 2

13

D

S

DN1 SDM10U45-7_SOD523-2~D

QN3

0_0402_5%

0_0402_5%

12

@

RN19

12

@

RN20

SATA_PTX_DRX_P2_C

SATA_PRX_DTX_P2_C
SATA_PRX_DTX_N2_C

12

@

RN18

2

G

21

ODD_DA#_R

13

D

QN4
2N7002E-T1-E3_SOT23-3

S

+5VS

12

RN28

@

100K_0402_5%~D

ODD_B_PRE0

ODD_B_PRE1

ODD_A_PRE1

ODD_A_PRE0

ODD_REXT_SATA

RN21 0_0402_5%@

1 2

RN22 0_0402_5%@

1 2

RN23 0_0402_5%@

1 2

RN24

1 2

RN25

1 2

ODD_DA#<17>

FFS_INT2_CONN <49>

2K_0402_5%

5.1K_0402_1%

D

ODD_DETECT#<21>

1 2

FFS_INT2_CONN<49>

+5VS_ODD

SATA_PRX_DTX_P2_C
SATA_PRX_DTX_N2_C

SATA_PTX_DRX_N2_C
SATA_PTX_DRX_P2_C

+5VS

Pin 20:
PARADE PS8250B:
Reserve RN18, Mount RN25

PERICOM PI3EQX6741ST:
Mount RN18, Reserve RN25

ASMEDIA ASM1466:
Mount RN18, Reserve RN25

RN45 0_0402_5%~D

+3VS

ODD_DA#_R

FFS_INT2_CONN

E

SATA ODD Conn.

JODD1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17
18
19
20

21

17

GND1

22

18

GND2

23

19

GND3

24

20

GND4

E-T_0870K-F20C-22L

CONN@

Pin 9:
PARADE PS8250B:
Reserve RN24.

PERICOM PI3EQX6741ST:
Reserve RN24

ASMEDIA ASM1466:
Mount RN24 to pull down

+3VS

+3VS

0.1U_0402_25V6K

m-SATA Re-Driver

3 3

+3VS

RN30 0_0402_5%

1 2

RN31 0_0402_5%@

1 2

RN32 0_0402_5%@

1 2

RN33 0_0402_5%@

1 2

SATA_PTX_DRX_P3_R
SATA_PTX_DRX_N3_R

SATA_PRX_DTX_P3_R
SATA_PRX_DTX_N3_R

Pin 9:
PARADE PS8250B:
Reserve RN41.

PERICOM PI3EQX6741ST:
Reserve RN41

ASMEDIA ASM1466:
Mount RN41 to pull down

CN41 0.01U_0402_16V7K~D

MSATA_PTX_DRX_P3<16>
MSATA_PTX_DRX_N3<16>

MSATA_PRX_DTX_P3<16>
MSATA_PRX_DTX_N3<16>

4 4

1 2

CN42 0.01U_0402_16V7K~D

1 2

CN43 0.01U_0402_16V7K~D

1 2

CN44 0.01U_0402_16V7K~D

1 2

+3VS

Pin 20:
PARADE PS8250B:
Reserve RN35, Mount RN42

PERICOM PI3EQX6741ST:
Mount RN35, Reserve RN42

ASMEDIA ASM1466:
Mount RN35, Reserve RN42

A

mSATA_B_PRE1
mSATA_A_PRE1

UN3

7

EN

1

A_INp

2

A_INn

REXT

5

B_OUTp

4

A_PRE0

B_OUTn

B_PRE0

17

B_PRE1

19

A_PRE1

A_OUTp
A_OUTn

18

TEST

3

B_INp

GND

13

GND

21

B_INn

EPAD

PS8520BTQFN20GTR2_TQFN20_4X4

6

VDD

16

VDD

10

NC

20

9
8

15
14

11
12

B

0.01U_0402_16V7K

1

1

2

mSATA_REXT_SATA

mSATA_A_PRE0
mSATA_B_PRE0

SATA_PTX_DRX_P3_RC
SATA_PTX_DRX_N3_RC

SATA_PRX_DTX_P3_RC SATA_PRX_DTX_P3_C
SATA_PRX_DTX_N3_RC

0_0402_5%

CN50

CN49

2

CN45 0.01U_0402_16V7K~D
CN46 0.01U_0402_16V7K~D

CN47 0.01U_0402_16V7K~D
CN48 0.01U_0402_16V7K~D

mSATA_B_PRE0

RN38 0_0402_5%@

mSATA_B_PRE1

RN39 0_0402_5%@

mSATA_A_PRE1

RN40 0_0402_5%@

mSATA_A_PRE0

RN41

mSATA_REXT_SATA

12

1 2
1 2

1 2
1 2

RN42

RN34

1 2

1 2

1 2

1 2

1 2

0_0402_5%

12

@

RN35

2K_0402_5%

5.1K_0402_1%

0_0402_5%

0_0402_5%

12

@

RN36

12

@

RN37

SATA_PTX_DRX_P3_C
SATA_PTX_DRX_N3_C

SATA_PRX_DTX_N3_C

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

C

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

0.1U_0402_16V4Z~D

1000P_0402_50V7K~D

CN51

1

1

2

2

10U_0805_10V4Z~D

1U_0402_6.3V4Z~D

CN52

CN53

1

1

2

2

Placea caps. near JP2 CONN.

+1.5VS

1U_0402_6.3V4Z~D

0.1U_0402_16V4Z~D

1000P_0402_50V7K~D

CN55

1

1

2

2

10U_0805_10V4Z~D

CN57

CN56

1

1

2

2

Placea caps. near JP2 CONN.

E51TXD_P80DATA<43>

E51RXD_P80CLK<43>

2012/06/22 2013/06/21

CN54

CN58

RN43 0_0402_5%~D

1 2

RN44 0_0402_5%~D

1 2

Compal Secret Data

T62PAD~D @
T63PAD~D @

T61PAD~D @
T59PAD~D @

SATA_PRX_DTX_P3_C
SATA_PRX_DTX_N3_C

SATA_PTX_DRX_N3_C
SATA_PTX_DRX_P3_C

T65PAD~D @
T64PAD~D @

Deciphered Date

D

EC_TX_DAT
EC_RX_CLK

RN47

100K_0402_5%~D

1 2

+3VS

JP2

1

WAKE#

3

NC

5

NC

7

CLKREQ#

9

GND

11

REFCLK-

13

REFCLK+

15

GND

17

NC

19

NC

21

GND

PERST#

23

PERn0

+3.3Vaux

25

PERp0

27

GND

29

GND

SMB_CLK

31

PETn0

SMB_DATA

33

PETp0

35

GND

USB_D-

37

NC

USB_D+

39

NC

41

NC

LED_WW AN#

43

NC

LED_WL AN#

45

NC

LED_WP AN#

47

NC

49

NC

51

NC

53

GND

BELLW_80003-4041

CONN@

+3VS +1.5VS

2

3.3V

4

GND

6

1.5V

8

NC

10

NC

12

NC

14

NC

16

NC

18

GND

20

NC

22
24
26

GND

28

+1.5V

30
32
34

GND

36
38
40

GND

42
44
46
48

+1.5V

50

GND

52

+3.3V

54

GND

Title

Siz

Custom

Date: Sheet of

PCH_SMBCLK
PCH_SMBDATA

PCH_SMBCLK <6,12,13, 14,15,19,49,51,53>

PCH_SMBDATA <6,12,13,14,15,19, 49,51,53>

Compal Electronics, Inc.

SATA ODD/mSATA

e Document Number Rev

LA-9331P

E

47 61Friday, June 22, 2012

0.1

A

B

C

D

E

47P_0402_50V8J~D

C63

SMB_DATA

LED_WW AN#

LED_WL AN#
LED_WP AN#

PERST#

+3.3Vaux

+1.5V

SMB_CLK

USB_D-

USB_D+

+1.5V

+3.3V

3.3V

GND

1.5V
NC
NC
NC
NC
NC

GND

NC

GND

GND

GND

GND

GND

+3VS

4.7U_0805_10V4Z~D

C39

1

2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

WiGi_RADIO_DIS#_R

32
34
36
38
40
42
44
46
48
50
52

54

0.1U_0402_16V4Z~D

C40

1

1

2

2

0.1U_0402_16V4Z~D
47P_0402_50V8J~D

C41

C64

2

1

+3VS

+1.5VS

RE31 0_0402_5%~D

1 2

RE26 0_0402_5%~D

1 2

RE27 0_0402_5%~D

1 2

RE28 0_0402_5%~D

1 2

RE29 0_0402_5%~D

1 2

WL_OFF#
PLT_RST#

RE22 0_0402_5%~D

1 2

USB20_N4
USB20_P4

WiGi_RADIO_DIS#_R WiGi_RADI O_DIS#

2 1

SDMK0340L-7-F

LPC_FRAME# <19,43>

LPC_AD3 <19,43>
LPC_AD2 <19,43>
LPC_AD1 <19,43>
LPC_AD0 <19,43>

WL_OFF# <17>
PLT_RST# <6,17,43,44,53>

WiGi_RADIO_DIS# <21>

USB20_N4 < 20>
USB20_P4 <20>

@

D3

+1.5VS

0.1U_0402_16V4Z~D

4.7U_0805_10V4Z~D

0.1U_0402_16V4Z~D

C37

C36

C38

1

1 1

WLAN

CLK_PCIE_MINI1#< 18>
CLK_PCIE_MINI1<18>

PCIE_PRX_WLANTX_N1<16>
PCIE_PRX_WLANTX_P1<16>

BT_ON#

PCIE_WAKE#
COEX2
COEX1

MINI1CLK_REQ#<18>

PLT_RST#<6,17,43,44,53>

CLK_DEBUG<18>

C59 0.1U_0402_10V7K~D

1 2
1 2

C60 0.1U_0402_10V7K~D

PCIE_WAKE#<17,43,44>

PCIE_PTX_WLANRX_N1<16>
PCIE_PTX_WLANRX_P1<16>

BT_ON#<17>

2 2

1

2

RE12 0_0402_5%~D@

1 2

R38 0_0402_5%~D

1 2

R39 0_0402_5%~D

1 2

MINI1CLK_REQ#

CLK_PCIE_MINI1#
CLK_PCIE_MINI1

RE32 0_0402_5%~D

1 2

PCIE_PRX_WLANTX_N1
PCIE_PRX_WLANTX_P1

PCIE_PTX_WLANRX_N1_C
PCIE_PTX_WLANRX_P1_C

+3VS

BT_ON#_R

1 2

RE1191K_0402_1%~D

2

1

2

1

2

JMINI1

1

WAKE#

3

NC

5

NC

7

CLKREQ#

9

GND

11

REFCLK-

13

REFCLK+

15

GND

17

NC

19

NC

21

GND

23

PERn0

25

PERp0

27

GND

29

GND

31

PETn0

33

PETp0

35

GND

37

NC

39

NC

41

NC

43

NC

45

NC

47

NC

49

NC

51

NC

53

GND

BELLW_80003-4041

CONN@

Display Mini Card (DMC)

4.7U_0805_10V4Z~D

1

2

0.1U_0402_16V4Z~D

C45

C46

1

2

+1.5VS

BLM18AG601SN1D_0603~D

+3VS

PCIE_WAKE#
COEX2
COEX1

MINI2CLK_REQ#<18>

CLK_PCIE_MINI2#< 18>
CLK_PCIE_MINI2<18>

3 3

PCIE_PTX_WANRX_N2<16>
PCIE_PTX_WANRX_P2<16>

PCIE_PRX_WANTX_N2<16>
PCIE_PRX_WANTX_P2<16>

DMC_PCH_DET#<18>
CPU_MXM_DMC_AUXN<39>
CPU_MXM_DMC_AUXP<39>

CPU_MXM_DMC_N2<39>

CPU_MXM_DMC_P2<39>

CPU_MXM_DMC_N0<39>

CPU_MXM_DMC_P0<39>

RE30 0_0402_5%~D@
R40 0_0402_5%~D
R41 0_0402_5%~D

MINI2CLK_REQ#

CLK_PCIE_MINI2#
CLK_PCIE_MINI2

PCIE_PRX_WANTX_N2

PCIE_PTX_WANRX_N2_C

1 2

PCIE_PTX_WANRX_P2_C

1 2

PCIE_PRX_WANTX_P2

+3VS_DMC

DMC_PCH_DET#
CPU_MXM_DMC_AUXN
CPU_MXM_DMC_AUXP

CPU_MXM_DMC_N2
CPU_MXM_DMC_P2

CPU_MXM_DMC_N0
CPU_MXM_DMC_P0

C61 0.1U_0402_10V7K~D

C62 0.1U_0402_10V7K~D

1 2
1 2
1 2

JDMC1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

61

63

63

65

65

67

67

69

69

71

71

73

73

75

75

77

GND1

79

GND3

TYCO_2041286-1

CONN@

GND2

10
12
14
16

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54
56
58
60
62
64
66
68
70
72
74
76

+3VS_DMC

2

2

4

4

6

6

8

8

10
12
14
16

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54
56
58
60
62
64
66
68
70
72
74
76

78

+1.5VS_DMC +3VS_DMC

DMC_RADIO_OFF#
PLT_RST#

MINI2_SMBCLK
MINI2_SMBDATA

USB20_N5
USB20_P5

DP_DMC_HPD

CPU_MXM_DMC_N3
CPU_MXM_DMC_P3

CPU_MXM_DMC_N1
CPU_MXM_DMC_P1

CPU_MXM_DMC_AUXN
CPU_MXM_DMC_AUXP

RE33 0_0402_5%~D@
RE34 0_0402_5%~D@

R42 100K_0402_5%~D
R43 100K_0402_5%~D

DMC_RADIO_OFF# <21>

1 2
1 2

USB20_N5 <20>

USB20_P5 <20>

R44

1M_0402_5%~D

1 2

CPU_MXM_DMC_N3 <39>
CPU_MXM_DMC_P3 <39>

CPU_MXM_DMC_N1 <39>
CPU_MXM_DMC_P1 <39>

1 2
1 2

PCH_SMBCLK
PCH_SMBDATA

DP_DMC_HPD <39>

BLM18PG330SN1D_2P~D

PCH_SMBCLK <6,12,13,14,15, 19,49,50,53>
PCH_SMBDATA <6,12,13,14,15,19,49,50, 53>

+3VS_DMC

L2

12

+1.5VS_DMC

L1

12

4.7U_0805_10V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

C42

1

2

C44

C43

1

1

2

2

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Mini Card -WLAN/DMC/BT

Size Document Number Rev

Custom

LA-9331P

Date: Sheet of

E

48 61Friday, June 22, 2012

0.1

5

RI1 0_0402_5%~D@

1 2

SW_USB20_P0

SW_USB20_N0

D D

USB3RN1_R_C USB3RN1_R

USB3RP1_R_C

LI3

4

3

4

1

1

DLW21SN900SQ2L_0805_4P~D

RI2 0_0402_5%~D@

RI3 0_0402_5%~D@

RI4 0_0402_5%~D@

2

1 2

1 2

LI1

2

1

2

3

3

4

DLW21SN900HQ2L_0805_4P~D

1 2

USB20_P0_CONN

3

USB20_N0_CONN

2

1

USB3RP1_R

4

4

Power share

PWRSHARE_OE#<43>

USB20_N0<20>

USB20_P0<20>

PWRSHARE_OE#
USB20_N0
USB20_P0

+5VALW

PWRSHARE_SEL#

PWRSHARE_OE#
PWRSHARE_SEL#
PWRSHARE_EN

8
7
6
5

0.1U_0402_16V4Z~D
CI1

2

1

RI9 10K_0402_5%~D

RI8 10K_0402_5%~D@
RI10 10K_0402_5%~D@
RI7 10K_0402_5%~D@

UI1

CB
TDM
TDP
VDD

SLG55584AVTR_TDFN8_2X2

1 2

1 2
1 2
1 2

SELCDP

Thermal Pad

3

PWRSHARE_EN

1

CEN

SW_USB20_N0

2

DM

SW_USB20_P0

3

DP

PWRSHARE_SEL#

4
9

PWRSHARE_EN

+5VALW

RI86 0_0402_5%~D

PWRSHARE_EN_EC#<43>

RI82

10K_0402_5%

1 2

DI7

1 2

SDMK0340L-7-F_SOD323-2~D

+3VALW

12

+5VALW

4.7U_0805_10V4Z
100K_0402_5%

1 2

13

D

2

G

S

2

+5VALW

1

CI18

2

RI81

PWRSHARE_EN_R#

SSM3K7002FU_SC70-3~D

QI1

1

CI16

0.1U_0402_16V7K

2

1

CI13

0.1U_0402_16V7K

2

UI2

1

GND

2

VIN
VIN3VOUT

4

EN

2.0A

8

VOUT

7

VOUT

6
5

FLG

EPAD

9

AP2301MPG-13_MSOP8

+USB3_VCCA

80mil

RI80

0_0402_1%

1 2

@

1

1

CI15

0.1U_0402_16V7K

2

USB_OC0# <20>

RI5 0_0402_5%~D@

1 2

USB3TN1_R_C USB3TN1_R

USB3TP1_R_C

+3VS

RI55 3.3K_0402_5%@
RI54 3.3K_0402_5%@

RI53 3.3K_0402_5%@

C C

B B

A A

RI52 3.3K_0402_5%@

RI42 4.7K_0402_5%~D@
RI43 4.7K_0402_5%~D@
RI44 4.7K_0402_5%~D@
RI41 4.7K_0402_5%~D@

RI19 4.7K_0402_5%~D@
RI20 4.7K_0402_5%~D@
RI21 4.7K_0402_5%~D@
RI22 4.7K_0402_5%~D@
RI26 4.7K_0402_5%~D@
RI23 4.7K_0402_5%~D@
RI24 4.7K_0402_5%~D@
RI25 4.7K_0402_5%~D@
RI30 4.7K_0402_5%~D@
RI27 4.7K_0402_5%~D@
RI28 4.7K_0402_5%~D@
RI29 4.7K_0402_5%~D@

RI87 4.7K_0402_5%~D@
RI31 4.7K_0402_5%~D@
RI36 4.7K_0402_5%~D@
RI40 4.7K_0402_5%~D@
RI35 4.7K_0402_5%~D@
RI32 4.7K_0402_5%~D@
RI33 4.7K_0402_5%~D@
RI34 4.7K_0402_5%~D@
RI39 4.7K_0402_5%~D@
RI37 4.7K_0402_5%~D@
RI38 4.7K_0402_5%~D@
RI84 4.7K_0402_5%~D@

RI46 4.7K_0402_5%~D@
RI47 4.7K_0402_5%~D@
RI48 4.7K_0402_5%~D@
RI45 4.7K_0402_5%~D@

RI49 0_0402_5%~D@
RI50 0_0402_5%~D@

RI85 0_0402_5%~D@
RI51 0_0402_5%~D@

USB20_N1<20>

USB20_P1<20>

LI2

2

2

3

3

DLW21SN900HQ2L_0805_4P~D

RI6 0_0402_5%~D@

1 2
1 2

1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2

1 2
1 2

USB20_N1

USB3TN2_R_C USB3TN2_R

USB3TP2_R_C

USB3RN2_R_C USB3RN2_R

USB3RP2_R_C

5

1

1

4

4

1 2

USB3_P1_PIN6
USB3_P1_PIN18

USB3_P0_PIN6
USB3_P0_PIN18

USB3_CM_P0
USB3_CM_P1
USB3_ERD_P0
USB3_ERD_P1

USB3_OS2_P0
USB3_DE2_P0
USB3_EQ2_P0
USB3_OS1_P0
USB3_DE1_P0
USB3_EQ1_P0
USB3_OS2_P1
USB3_DE2_P1
USB3_EQ2_P1
USB3_OS1_P1
USB3_DE1_P1
USB3_EQ1_P1

USB3_OS2_P0
USB3_DE2_P0
USB3_EQ2_P0
USB3_OS1_P0
USB3_DE1_P0
USB3_EQ1_P0
USB3_OS2_P1
USB3_DE2_P1
USB3_EQ2_P1
USB3_OS1_P1
USB3_DE1_P1
USB3_EQ1_P1

USB3_CM_P0
USB3_CM_P1
USB3_ERD_P0
USB3_ERD_P1

USB3_P0_PIN6
USB3_P0_PIN18

USB3_P1_PIN6
USB3_P1_PIN18

RI13 0_0402_5%~D@

1 2

LI6

4

4

1

1

DLW21SN900SQ2L_0805_4P~D

RI14 0_0402_5%~D@

1 2

RI17 0_0402_5%~D@

1 2

LI5

2

2

3

3

DLW21SN900HQ2L_0805_4P~D

RI18 0_0402_5%~D@

1 2

RI15 0_0402_5%~D@

1 2

LI4

2

2

3

3

DLW21SN900HQ2L_0805_4P~D

RI16 0_0402_5%~D@

1 2

USB3TP1_R

Vendor
p

in

pin15

pin16

pin17

pin4

pin3

pin2

pin5

pin14

pin18

pin6

[Parade suggest]
PS8710 AEQ0,BEQ0 adjust 7db,
REXT use 3.3 K well get btter test result.

USB20_N1_CONN

3

3

USB20_P1_CONNUSB20_P1

2

2

1

1

USB3TP2_R

4

4

1

1

USB3RP2_R

4

4

PS8710B
(default)
AEQ1

ADE0

AEQ0

BEQ1

BDE0

BEQ0

PD

TEST

ADE1

BDE1

USB3RN1

USB3RN1<20>
USB3RP1<20>

USB3TN1<20>
USB3TP1<20>

TI

OS2

DE2

EQ2

OS1

DE1

EQ1

EN_RXD

CM

CI9 0.1U_0402_10V6K~D

USB3RP1

CI8 0.1U_0402_10V6K~D

USB3TN1

CI4 0.1U_0402_10V6K~D

USB3TP1

CI5 0.1U_0402_10V6K~D

SN65LVPE502
EN==
1:normal operation(default)
0:sleep mode
CM==
0:normal operation(default)
1:Compliance test mode

PS8710
[A(B)_DE1, A(B)_DE0] ==
LL: 3.5dB de-emphasis
LH: No de-emphasis
HL: 7dB de-emphasis
HH: 5dB with boost output swing
[A(B)_EQ1, A(B)_EQ0] ==
LL: reserved
LH: program EQ for channel loss up to 7dB
HL: program EQ for channel loss up to 14.5dB
HH: program EQ for channel loss up to 11.5dB
TEST ==
L: Normal operation (default)
H: Test mode enable

USB3RN2

USB3RN2<20>

USB3RP2

USB3RP2<20>

USB3TN2

USB3TN2<20>

USB3TP2

USB3TP2<20>

4.7U_0805_10V4Z

USB_PWR_EN#<43,53>

4

0.01U_0402_16V7K~D

1 2
1 2

1 2
1 2

0.01U_0402_16V7K~D

CI27 0.1U_0402_10V6K~D

1 2

CI28 0.1U_0402_10V6K~D

1 2

CI23 0.1U_0402_10V6K~D

1 2

CI24 0.1U_0402_10V6K~D

1 2

+5VALW

1

CI35

2

USB_PWR_EN#

CI7

1 2
1 2

CI6

.1U_0402_16V7K~D

USB3_OS2_P0
USB3_DE2_P0
USB3_EQ2_P0

USB3TN1_L
USB3TP1_L

USB3_OS1_P0
USB3_DE1_P0
USB3_EQ1_P0

CI26

1 2
1 2

CI25

.1U_0402_16V7K~D

1

CI36

0.1U_0402_16V7K

2

1

CI37

0.1U_0402_16V7K

2

+3VS

UI3

1

VCC

13

USB3RN1_L
USB3RP1_L

VCC

11

TX2-

12

TX2+

15

OS2

16

EN_RXD

DE2

17

EQ2

8

RX1-

9

RX1+

4

OS1

3

DE1

2

EQ1

25

PGND

PS8713BTQFN24GTR2-A0_TQFN24_4X4

PCB footprint and CIS symbol use TI
(SN65LVPE502CPRGER)
Compal P/N and value use Parade
(PS8710B)

For OPTION reserve

USB3RN1 USB3RN1_RL
USB3RP1

USB3TN1

USB3RN2
USB3RP2

USB3TN2

+3VS

1

USB3RN2_L
USB3RP2_L

USB3_OS2_P1
USB3_DE2_P1
USB3_EQ2_P1

USB3TN2_L

USB3_OS1_P1
USB3_DE1_P1
USB3_EQ1_P1

13

11
12

15
16
17

8
9

4
3
2

25

PS8713BTQFN24GTR2-A0_TQFN24_4X4

PCB footprint and CIS symbol use TI
(SN65LVPE502CPRGER)
Compal P/N and value use Parade
(PS8710B)

2.0A

UI5

1

GND

2

VIN
VIN3VOUT

4

EN

9

7

NC

24

NC

20

RX2-

19

RX2+

5
14

CM

23

TX1-

22

TX1+

6

GND

10

GND

18

GND

21

GND

RI64 0_0402_5%~D@

1 2

RI65 0_0402_5%~D@

1 2

RI66 0_0402_5%~D@

1 2

RI67 0_0402_5%~D@

1 2

RI60 0_0402_5%~D@

1 2

RI61 0_0402_5%~D@

1 2

RI63 0_0402_5%~D@

1 2

RI62 0_0402_5%~D@

1 2

UI4

VCC

NC

VCC

NC

TX2-

RX2-

TX2+

RX2+

OS2

EN_RXD

DE2

CM

EQ2

RX1-

TX1-

TX1+

RX1+

OS1
DE1

GND

EQ1

GND
GND
GND

PGND

8

VOUT

7

VOUT

6
5

FLG

EPAD

AP2301MPG-13_MSOP8

3

+USB3_VCCA

USB3TP1_R

USB3RN1_R_C
USB3RP1_R_C

USB3TN1_R_C
USB3TP1_R_C

USB3RN2_R_C
USB3RP2_R_C

USB3TN2_R_C
USB3TP2_R_C

Deciphered Date

2

USB3TN1_R
USB20_P0_CONN

USB20_N0_CONN
USB3RP1_R

USB3RN1_R

USB20_P0_CONN

USB20_N0_CONN

USB3TP2_R

USB3TN2_R
USB20_P1_CONN

USB20_N1_CONN
USB3RP2_R

USB3RN2_R

USB20_P1_CONN

USB20_N1_CONN

+USB3_VCCB

RI56 4.99K_0402_1%

1 2

RI57 0_0402_5%~D@

1 2

USB3RN1_R_C
USB3RP1_R_C

USB3_ERD_P0
USB3_CM_P0

USB3TN1_RC

CI11 0.1U_0402_10V6K~D

USB3TP1_RC

USB3_P0_PIN6

USB3_P0_PIN18

+USB3_VCCB

1 2

CI10 0.1U_0402_10V6K~D

1 2

USB3RP1_RL

USB3TN1_RL
USB3TP1_RLUSB3TP1

USB3RN2_RL
USB3RP2_RL

USB3TN2_RL
USB3TP2_RLUSB3TP2

RI77 4. 99K_0402_1%

7

1 2

RI76 0_0402_5%~D@

24

1 2

USB3RN2_R_C

20

USB3RP2_R_C

19

USB3_ERD_P1

5

USB3_CM_P1

14

USB3TN2_RC

23
22

6
10
18
21

CI29 0.1U_0402_10V6K~D

USB3TP2_RC

USB3_P1_PIN6

USB3_P1_PIN18

80mil

RI83

1 2

CI30 0.1U_0402_10V6K~D

1 2

0_0402_1%

1 2

@

1

CI38

0.1U_0402_16V7K

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

USB3TN1_R_C
USB3TP1_R_C

RI72 0_0402_5%~D@
RI73 0_0402_5%~D@

RI74 0_0402_5%~D@
RI75 0_0402_5%~D@

RI68 0_0402_5%~D@
RI69 0_0402_5%~D@

RI71 0_0402_5%~D@
RI70 0_0402_5%~D@

USB_OC1# <20>

2012/06/22 2013/06/21

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

USB3TN2_R_C
USB3TP2_R_CUSB3TP2_L

USBCHG_DET#<43>

Compal Secret Data

USB CONN

JUSB1

9

SSTX+

1

VBUS

8

SSTX-

3

D+

7

GND

2

GND

D-

6

GND

SSRX+

4

GND

GND

5

SSRX-

GND

10

Plug_DET

TAIWI_USB006-107CRL-TWD

CONN@

2

3

PESD5V0U2BT_SOT23-3~D

DI9

1

JUSB2

9

SSTX+

1

VBUS

8

SSTX-

3

D+

7

GND

2

GND

D-

6

GND

SSRX+

4

GND

GND

5

SSRX-

GND

TAITW_PUBAU5-09FLBS1NN4H0

CONN@

2

3

PESD5V0U2BT_SOT23-3~D

DI10

1

+USB3_VCCA

10U_0603_6.3V6M~D

1

CI22

1

+

CI20

11
12
13
14

USB3RN1_R USB3RN1_R

USB3RP1_R USB3RP1_R

USB3TN1_R USB3TN1_R

USB3TP1_R USB3TP1_R

10
11
12
13

USB3RN2_R USB3RN2_R

USB3RP2_R USB3RP2_R

USB3TN2_R USB3TN2_R

USB3TP2_R USB3TP2_R

Title

USB 3.0/2.0 x2 (left side)

e Document Number Rev

Siz

Custom

LA-9331P

Date: Sheet of

220U_6.3V_M

DI2

1

2

4

5

3

8

IP4292CZ10-TBR_XSON10_2.5X1~D

CI32

220U_6.3V_M

DI8

1

2

4

5

3

8

IP4292CZ10-TBR_XSON10_2.5X1~D

Compal Electronics, Inc.

1

2

+USB3_VCCB

1

+

2

10

9

7

6

2

10

9

7

6

10U_0603_6.3V6M~D

CI34

1

2

49 61Friday, June 22, 2012

0.1

5

4

3

2

1

+5VALW

10U_0805_10V6K

1

1

D D

C C

C47

2

2

USB20_N2<20 >
USB20_P2<20>

USB3TP5<20>
USB3TN5<20>

USB3RP5<20>
USB3RN5<20>

USB20_N3<20 >
USB20_P3<20>

USB3TP6<20>
USB3TN6<20>

USB3RP6<20>
USB3RN6<20>

USB_OC2#<20>
USB_OC3#<20>

BTB CONNECTOR TO USB3.0 Board

0.1U_0402_16V4Z~D

C48

+5VALW +5VALW

+5VS

JIO1

+3VS

USB20_N2
USB20_P2

USB3TP5
USB3TN5

USB3RP5
USB3RN5

USB20_N3
USB20_P3

USB3TP6
USB3TN6

USB3RP6

USB3RN6

USB_OC2#
USB_OC3#

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

GND151GND2

E&T_1001-F50E-03R

CONN@

2

2

4

4

6

6

8

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

MXM1_FAN_PWM

10

MXM1_FAN_FB

12

RTRON_LED_G_DRV#

14

RTRON_LED_R_DRV#

16

RTRON_LED_B_DRV#

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

52

USB_PWR_EN#
LAN_ACTIVITY#
LAN_LINK#_R
LAN_LED2#_R

LAN_MDIN0
LAN_MDIP0

LAN_MDIN1
LAN_MDIP1

LAN_MDIN2
LAN_MDIP2

LAN_MDIN3
LAN_MDIP3

+3VS

MXM1_FAN_PWM
MXM1_FAN_FB MXM1_FAN_FB_D

1 2

MXM1_FAN_PWM <43>

MXM1_FAN_FB <43>

RTRON_LED_G_DRV# <48>
RTRON_LED_R_DRV# <48>
RTRON_LED_B_DRV# <48>

USB_PWR_EN# <43,52>
LAN_ACTIVITY# <44>
LAN_LINK#_R <44>
LAN_LED2#_R <44>

+LAN_IO

LAN_MDIN0 <44>
LAN_MDIP0 <44>

LAN_MDIN1 <44>
LAN_MDIP1 <44>

LAN_MDIN2 <44>
LAN_MDIP2 <44>

LAN_MDIN3 <44>
LAN_MDIP3 <44>

10K_0402_5%~D

10K_0402_5%~D

R56

R57

1 2

12

D66

SDMK0340L-7-F_SOD323-2~D

+5VS

+5VS_TP_LED

TP_CLK

TP_DATA

2

3

PESD5V0U2BT_SOT23-3~D
D71

1

Place close to JP3

22U_0805_6.3VAM~D

C56

1

10K_0402_5%~D

R55

2

1 2

Reserve for Key Pad
(Viking only)

KSI[0..7]<43>

KSO[0..17]<43>

KSI[0..7]

KSO[0..17]

PCH_SMBDATA<6,12,13,14,15,19,49,50,51>
PCH_SMBCLK<6,12,13,14,15,19,49,50,51>
TP_LED_R_DRV#<48>
TP_LED_G_DRV#<48>
TP_LED_B_DRV#<48>

EC_SMB_DA2<19,40,43,54>

+3.3V_F347

TP_CLK<43>

TP_DATA<43>

EC_SMB_CK2<19,40,43,54>

USB20_P13<20>
USB20_N13<20>

I2C_DAT<47,48>
7313_INT#<48>

TP_CLK
TP_DATA

TP_LED_R_DRV#
TP_LED_G_DRV#
TP_LED_B_DRV#

VPK_DET#

VPK_DET#<43>

VPK_EN

VPK_EN<43 >

KP_DET#

+5VS

+3VS

I2C_CLK<47,48>

KB_DET#<43>

I2C_CLK
I2C_DAT

KB_DET#
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

JP3

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

35

35

36

36

37

37

38

38

39

39

40

40

41

41

42

42

43

43

44

44

45

45

46

46

47

47

48

48

49

49

50

50

51

51

52

52

53

53

54

54

55

55

56

56

57

57

58

58

59
60

62

59

G2

61

60

G1

CVILU_CF25602D0R0-05-NH

CONN@

60 pin FFC connector To MB

B B

30pin Connector to CardReader

JIO2

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

G1

32

G2

ACES_88196-3041

CONN@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

Custom

2

Date: Sheet of

Title

IO BTB CONN

ze Document Number Rev

Si

LA-9331P

1

50 61Friday, June 22, 2012

0.1

PLT_RST#<6,17,43,44,51>

+3VALW

+3VS

+5VS

+5VALW

HDD_R<48>
HDD_G<48>
HDD_B<48>

LID_SW<48>

PCIE_PTX_CARDRX_P4
PCIE_PTX_CARDRX_N4

PCIE_PRX_CARDTX_P4
PCIE_PRX_CARDTX_N4

CLK_PCIE_CD
CLK_PCIE_CD#

PLT_RST#
CDCLK_REQ#

LID_SW
LID_SW_IN#

4

PCIE_PTX_CARDRX_P4<20>
PCIE_PTX_CARDRX_N4<20>

PCIE_PRX_CARDTX_P4<20>
PCIE_PRX_CARDTX_N4<20>

CLK_PCIE_CD<18>
CLK_PCIE_CD#<18>

CDCLK_REQ#<18>

ON/OFFBTN#

2

3

A A

D72
PESD24VS2UT_SOT23-3~D

1

Place close to JIO2

5

LED_R_7313#_1<48>
LED_B_7313#_1<48>
LED_G_7313#_1<48>

CAPS_LED#<43>

WLES ON/OFF LED#<43>

ON/OFFBTN#<55>

LID_SW_IN#<19,43,47,48>
PWR_G_7313#<48>
PWR_R_7313#<48>
PWR_B_7313#<48>

A

B

C

D

E

1 1

System FAN Controller

100P_0402_50V8J~D

@

C51

Diode circuit s used for skin temp sensor
(placed between CPU and MXM).
Place C51 close to Q17 as possible.

2 2

C

1

2

2

B

E

Q17

3 1

MMBT3904WT1G_SC70-3~D

SENSOR_DIODE_N1

R46 0_0402_5%~D

1 2

R47 0_0402_5%~D

1 2

R48 4.7K_0402_5%~D

+3VS

SYSTEM_FAN_PWM<43>

SYSTEM_FAN_FB<43>

MXM1 FAN Controller

100P_0402_50V8J~D

3 3

C55

@

C

1

2

2

B

E

Q19

3 1

MMBT3904WT1G_SC70-3~D

SENSOR_DIODE_P2

SENSOR_DIODE_N2

R52 0_0402_5%~D

1 2

R53 0_0402_5%~D

1 2

R54 6.8K_0402_5%~D

+3VS

1

470P_0402_50V7K~D

2

1 2

REMOTE_P2

C54

REMOTE_N2

REMOTE_P1SENSOR_DIODE_P1

1

C50

470P_0402_50V7K~D

2

REMOTE_N1

1 2

SYSTEM_FAN_PWM

SYSTEM_FAN_FB

+3VS

1

2

+3VS

0.1U_0402_10V7K~D
C49

1

2

U5

1

VDD

2

D+

SDATA

3

ALERT#

D-

THERM#4GND

ADM1032ARMZ-REEL_MS OP8

ddress:100_1100

A

+3VS

10K_0402_5%~D

10K_0402_5%~D

R50

R49

1 2

1 2

12

D65

SDMK0340L-7-F_SOD323-2~D

0.1U_0402_10V7K~D
C53

U6

1

VDD

2

3

SCLK

D+

SDATA

ALERT#

D-

THERM#4GND

ADM1032ARMZ-2REEL_MS OP8

Address:100_1101

8

7

6

5

EC_SMB_CK2

EC_SMB_DA2

SCLK

+5VS

EC_SMB_CK2

8

EC_SMB_DA2

7

6

5

1

10K_0402_5%~D

R51

2

1 2

EC_SMB_CK2 <19,40,43,53>

22U_0805_6.3VAM~D

C52

JFAN1

1

1

2

2

3

3

4

4

5

G5

6

G6

ACES_50273-0040N-001

CONN@

EC_SMB_DA2 <19,40,43,53>

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/06/22 2013/06/21

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Thermal Sensor & FAN

ze Document Number Rev

Si

Custom

LA-9331P

D

Date: Sheet of

E

51 61Friday, June 22, 2012

0.1

A

B

C

D

E

ON/OFF switch

1 1

2 2

A

IR SENSOR connector

0.1U_0402_16V4Z~D

C57

1

2

USB20_N7

USB20_P7

H1

@

H_3P5

H2

@

H_3P5

H3

@

H_3P5

H4

@

H_3P5

USB20_N7<20>
USB20_P7<20>

+5VS

JIR1

1

1

2

2

3

3

4

4

5

5

6

6

7

GND

8

GND

E-T_4260-F06N-10 L

CONN@

TOP Side

SMT1-05-A_4P

1

2

6

Bottom Side

SMT1-05-A_4P

1

2

6

Pop only for
SSI debug

SW1

5

SW2

5

+3VLP

3

4

3

4

ON/OFFBTN#

Power Button

R58

100K_0402_5%~D

D26

ON/OFFBTN#

ON/OFFBTN#<53>

0.1U_0402_25V6K~D

C58

1

2

1

DAN202UT106_SC7 0-3

1 2

2

3

ON/OFF <43>

1

1

H7

@

H_3P3

H11

@

H_3P0

H21

@

H_3P8

H25

@

H_3P0

1

1

1

1

H8

@

H_3P3

H12

@

H_3P0

H22

@

H_3P8

H26

@

H_3P0

1

1

1

1

1

H13

@

H_3P0

H27

@

H_3P0

1

1

H14

@

H_3P0

H30

@

H_3P0

1

1

H15

@

H_3P0

H31

@

H_3P0

1

1

H16

@

H_3P0

H32

@

H_3P0

1

1

H29

@

H_3P0

H33

@

H_3P0

1

H34

@

H_2P0N

1

ZZZ1

PCB-MB

Security Classification

1

B

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/06/22 2013/06/21

C

Compal Secret Data

Deciphered Date

FD1

@

1

FIDUCIAL_C40M80

D

FD2

@

1

FIDUCIAL_C40M80

Fiducial Mark

Title

Si

B

Date: Sheet of

KB & Power Button & IR

ze Docum ent Number Rev

LA-9331P

FD3

@

1

FIDUCIAL_C40M80

FD4

@

1

FIDUCIAL_C40M80

E

0.1

52 61Friday, June 22, 2012

1

H6

@

H5

@

B

3 3

C

D

E

4 4

F

H_3P3

H9

@

H_3P0

H17

@

H_3P3

H19

@

H_3P8

H23

@

H_3P0

1

1

1

1

1

H_3P3

H10

@

H_3P0

H18

@

H_3P3

H20

@

H_3P8

H24

@

H_3P0

A

1

1

1

1

1

A

DC to DC

B

C

D

E

+5VALW to +5VS

1 1

B+_BIAS

10U_0805_10V4Z~D

CZ1

1

1

2

2

1 2

RZ1

102K_0402_1%

SUSP

10U_0805_10V4Z~D

5

+5VALW

CZ2

QZ1

SI4800BDY-T1-E3_SO8~D

8
7

5

+5VS_GATE

34

QZ2B

DMN66D0LDW-7_SOT363-6~D

4

1

2

+5VS

1
2

10U_0805_10V4Z~D

36

0.1U_0603_25V7K~D
0_0402_5%~D

CZ4

RZ2

1 2

1U_0603_10V4Z~D

CZ5

CZ3

1

1

2

2

B+_BIAS

@

+3VALW to +3VS

+3VALW

10U_0805_10V4Z~D

2 2

B+_BIAS

1 2

RZ3

102K_0402_1%

SUSP

10U_0805_10V4Z~D

CZ6

CZ7

1

1

2

2

+3VS_GATE

SSM3K7002F_SC59-3~D

1

D

QZ4

2

G

S

3

QZ3

SI4800BDY-T1-E3_SO8~D

8
7

5

4

0.1U_0603_25V7K~D

1

12

CZ10

2

0_0402_5%~D

+3VS +5VMXM

1
2
36

@

RZ4

1U_0603_10V4Z~D

10U_0805_10V4Z~D

CZ8

1

CZ9

1

2

2

B+_BIAS

+3VALW to +3V_PCH

+3VALW

SI4800BDY-T1-E3_SO8~D

8

1

2

RZ53

7

10U_0805_10V4Z~D

5

CZ12

+3V_PCH_GATE

SSM3K7002F_SC59-3~D

1

D

QZ5

2

G

S

3

+1.05V

+1.05VS_GATE

SSM3K7002F_SC59-3~D

1

D

QZ7

2

G

S

3

1

2

1 2

102K_0402_1%

PCH_PWR_EN#

10U_0805_10V4Z~D

CZ11

RZ5

1 2

330K_0402_5%~D

SUSP

QZ6

4

1

2

+3V_PCH

1
2

10U_0805_10V4Z~D

36

0.1U_0603_25V7K~D
0_0402_5%~D

CZ15

12

1U_0603_10V4Z~D

CZ13

1

1

CZ14

2

2

@

RZ6

+1.05V to +1.05VS

QZ20

SI4164DY-T1-GE3_SO8~D

8
7

5

4

100P_0402_50V8J~D

1M_0402_5%~D

12

1

CZ32

2

+1.05VS

1
2

10U_0805_10V4Z~D

36

RZ54

CZ16

1

1

2

2

B+_BIAS

DMN66D0LDW-7_SOT363-6~D

1U_0603_10V4Z~D

CZ17

DMN66D0LDW-7_SOT363-6~D

+3VALW to +3VMXM Transfer

200K_0402_5%

1 2

DGPU_PWR_EN#

RZ30

+3VALW +3VMXM

10U_0805_10V4Z~D

CZ20

1

2

+3VMXM_GATE

61

QZ8A

2

UZ2

SI4800BDY-T1-E3_SO8~D

8
7

5

4

0.1U_0603_25V7K~D

12

CZ22

1

2

1
2
36

0_0402_5%~D

@

RZ31

+5VALW to +5VMXM

+5VALW

UZ3

SI4800BDY-T1-E3_SO8~D

10U_0805_10V4Z~D

B+_BIAS

DGPU_PWR_EN#

RZ32

200K_0402_5%

1 2

QZ9A

2

CZ24

1

2

61

8
7

5

+5VMXM_GATE

1
2
36

4

0.1U_0603_25V7K~D
0_0402_5%~D

12

@

RZ33

CZ27

1

2

4

10U_0805_10V4Z~D

CZ23

1

2

100mil(2.5A)

10U_0805_10V4Z~D

1

CZ25

2

0mil(1A)

0.1U_0402_16V4Z~D

1

CZ21

2

0.1U_0402_16V4Z~D

1

CZ26

2

Discharge Circuit

+5VALW

12

RZ46

100K_0402_5%~D

SUSP

SSM3K7002F_SC59-3~D

1

D

QZ16

2

G

0.1U_0603_25V7K~D

S

1

2

2

3

@

CZ29

+5VALW

RZ48

100K_0402_5%~D

1 2

SSM3K7002F_SC59-3~D

1

D

QZ18

G

S

3

Compal Electronics, Inc.

Title

DC/DC Interface

Size Document Number Rev

Custom

LA-9331P

Date: Sheet of

E

0.1

53 61Friday, June 22, 2012

470_0603_5%

SUSP

470_0603_5%

SUSP

RZ40

QZ10

RZ41

QZ19

+1.5VS

12

RZ35

+1.5VS_D

13

D

2

G

S

SSM3K7002FU_SC70-3~D

+1.05VS

12

+1.05VS_D

13

D

2

G

S

SSM3K7002FU_SC70-3~D

RUN_ON_CPU1.5VS3#<6,10>

B

470_0603_5%

DGPU_PWR_EN#

QZ13

1 2

+3VMXM_D

34

QZ8B

DMN66D0LDW-7_SOT363-6~D

5

220_0603_5%~D

2

G

DGPU_PWR_EN#

12

RZ38

+1.35V_CPU_VDDQ_CHG

SSM3K7002FU_SC70-3~D

13

D

S

+0.675VS+1.35V_CPU_VDDQ

22_0603_5%~D

2

G

RZ36

470_0603_5%

12

RZ39

+DDR_CHG

13

D

S

5

SSM3K7002FU_SC70-3~D

+5VMXM

QZ14

PCH_PWR_EN#

12

1

RZ52

2

12

RZ49

100K_0402_5%~D

SSM3K7002F_SC59-3~D

1

QZ17

3

+5VALW

12

RZ45

100K_0402_5%~D

SSM3K7002F_SC59-3~D

1

D

QZ15

2

G

0.1U_0603_25V7K~D

S

3

@

CZ28

DGPU_PWR_EN< 29,43>

Compal Secret Data

Deciphered Date

100K_0402_5%~D

12

RZ47

DGPU_PWR_EN#

100K_0402_5%~D

0.1U_0603_25V7K~D

12

1

RZ51

@

CZ31

2

D

+3VALW

RZ44

@

1 2

+5VMXM_D

34

PCH_PWR_EN<35,43> SUSP#<10,43,59,61>

QZ9B

DMN66D0LDW-7_SOT363-6~D

SYSON<43,59,60>

C

10K_0402_5%~D

1 2

100K_0402_5%~D

+5VALW

SYSON#

D

2

100K_0402_5%~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

G

0.1U_0603_25V7K~D

12

RZ50

S

1

@

CZ30

2

2012/06/22 2013/06/21

+1.35V

12

RZ37

470_0603_5%

+3V_D

SYSON#

QZ11A

DMN66D0LDW-7_SOT363-6~D

+1.35V_D

13

D

2

G

QZ12

S

SSM3K7002FU_SC70-3~D

470_0603_5%

SUSP

A

3 3

+3V_PCH

12

RZ42

470_0603_5%

61

PCH_PWR_EN#

4 4

2

+5VS +3VMXM

RZ34

470_0603_5%

1 2

+5VS_D

61

QZ2A

SUSP

RZ43

5

DMN66D0LDW-7_SOT363-6~D

2

+3VS

12

+3VS_D

34

QZ11B

DMN66D0LDW-7_SOT363-6~D

A

PL1

ADPIN

PJPDC1

@

1

1

2

2

3

3

4

4

5

5

6

6

+DCIN_JACK

1 1

7

7

8

8

9

9

10

10

11

11

ACES 50493-0110N-001

12

PC1

PSID

C8B BPH 853025_2P

12

PC2

1000P_0402_50V7K

PL2

BLM18BD102SN1D_0603~D

1 2

100P_0402_50V8J

12

VIN

12

12

PC3

1000P_0402_50V7K

BATT++BATT+

PL3

C8B BPH 853025_2P

BATT+

1 2

12

12

PC7

PC6

2 2

100P_0402_50V8J

0.01U_0402_25V7K

@

PBATT1

1

1

2

2

3

3

4

4

5

5

DAT_SMB

6

6

BATT_PRS

7

7

SYS_PRES

8

8

9

9

10

10

11

11

12

12

13

MOLEX_87437-1342

3 3

13

CLK_SMB

BATT++

12

12

PC9

PC8

2

PR19
0_0402_5%

<BOM Struct ure>

1

PD4

3

PESD24VS2UT_SOT23-3

PR15

100_0402_5%

1 2

PR18

100_0402_5%

1 2

PR20

100_0402_5%

1 2

1

100P_0402_50V8J

1000P_0402_50V7K

PD3
PESD24VS2UT_SOT23-3

2

3

1 2

B

PC4

Erp lot6 Circuit

100P_0402_50V8J

ACIN<17,29,43,47,63>

12

@

PR1

200K_0402_1%

12

PC5

@

0.1U_0402_25V6

2

-

LOTES AAA-BAT- 054-K01

PR16

10K_0402_1%

1 2

+3VALW

EC_SMB_CK1 <63 >

EC_SMB_DA1 <63 >

@

1M_0402_1%

61

2

@

BATT_TEMP <43,63>

PR7

PQ1A

2N7002BKS 2N SOT363-6

+

JRTC1

@

1

VIN

1 2

5

PR10

@

1M_0402_1%

1 2

PD5

2

3

BAS40CW _SOT323-3

C

PR4

D

1 3

@

12

PR5

3

4

1

2

3.3K_1206_5%~D

PQ1B

@

1

2N7002BKS 2N SOT363-6

3

@

PD1
SM24_SOT23

+RTCBATT

PR6

1 2

100K_0402_1%

PSID-1

PR9

15K_0402_1%

1 2

2

B

E

B+

+3VLP

2

G

PR13

100K_0402_1%

1 2

VSB_N_003

13

D

PQ4
2N7002KW_S OT323-3

S

100K_0402_1%

POK<58>

ADP_I<43,63>

+5VALW

PR14

PR17

1 2

0_0402_5%

1 2

VSB_N_002

12

PC12

.1U_0402_16V7K

33_0402_5%

S

PSID-3

1 2

PQ7
FDV301N_NL_SOT23-3~D

G

2

PSID-2

C

PQ2
MMST3904-7-F_SOT3 23~D

3 1

12

12

PC10

PR12

100K_0402_1%

VSB_N_001

TP0610K-T1-E3_SOT23- 3

0.22U_0603_25V7K

2

PQ3

PH1 under CPU botten side :

D

+3VALW

PR3

2.2K_0402_5%

1 2

PR8

10K_0402_1%

13

B+_BIAS

12

PC11

0.1U_0402_25V6

12

PS_ID <43>

+5VALW

CPU thermal protection at 93 +/- 3 degree C

PR23

+3VLP+3VALW

49.9K_0402_1%

1 2

VCIN1_PH<43>

PC13

PR26

499K_0402_1%

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

1 2

2012/06/22 2013/06/21

@

.1U_0402_16V7K

1 2

Compal Secret Data

Deciphered Date

C

VCIN0_PH<43>

100K_0402_1%_TSM0B104F4251RZ

Title

Size D ocument Number Rev

Date: Sheet of

PR24

12.1K_0402_1%

1 2

Compal Electronics, Inc.

PWR-DCIN / BATT CONN / OTP

LA-9331P

D

PH1

ECAGND<43>

PR25

12.1K_0402_1%

1 2

12

@

0.1

54 61Friday, June 22, 2012

A

1 1

B

PR100

13.7K_0402_1%~D

1 2

1 2

100P_0402_50V8J

@

PC121

20K_0402_5%~D

1 2

PR102

+3VLP

PR103

1 2

0_0603_5%~D

C

PC122

@

100P_0402_50V8J

1 2

PR101

30.9K_0402_1%

12

PR104

20K_0402_5%~D

12

PC114

1U_0603_10V5K

12

D

E

B++

B++

PL103

1UH_NRS4018T1R0NDGJ_3.2A_30%

1 2

12

PC105

B+

2 2

+3VALWP

PC101

0.1U_0402_25V6

3.3UH_PCMB063T-3R3MS_6.5A_20%

1

+

2

150U_B2_6.3VM_R35M

12

PC110

PC106

2200P_0402_50V7K

PL101

1 2

12

12

PC107

@

10U_0805_25V6K

10U_0805_25V6K

PQ101

3 5

241

FDMC8884_POWER33-8-5

12

PR109

4.7_1206_5%
PQ103

SNUB_3V

12

PC116

680P_0603_50V7K

3 5

241

FDMC8878_POWER33-8-5

PC112

0.1U_0603_25V7K

1 2

POK<57>

PR108

2.2_0603_5%

1 2

PR105

1 2

120K_0402_1%~D

3V_EN

UG_3V

BST_3V

SW2

LG_3V

B++

PU100

6

7

10

9

8

FB_3V

5

4

CS2

VFB2

EN2

PGOOD

DRVH2

TPS51225_QFN20_3X3

VBST2

SW2

DRVL211VIN12VREG513EN120DRVL1

12

PC117

0.1U_0603_25V7K

3

VREG3

PR106

FB_5V

2

5V_EN

PC118

1U_0603_10V5K

1 2

59K_0402_1%~D

1

21

CS1

PAD

VFB1

12

15

VO1

VCLK

DRVH1

VBST1

SW1

14

19

UG_5V

16

BST_5V

17

SW1

18

LG_5V

PR118

1 2

0_0603_5%~D

PR107

2.2_0603_5%

1 2

PC111

0.1U_0603_25V7K

1 2

3 5

241

3 5

241

VL

12

PC103

0.1U_0402_25V6

PQ102

AON7518 1N DFN

3.3UH +-20% PIMB104T-3R3MS 10A

12

PR110

4.7_1206_5%

PQ104

AON6508 1N DFN

SNUB_5V

12

PC119

680P_0603_50V7K

PC108

2200P_0402_50V7K

PL102

12

12

12

PC109

PC104

@

10U_0805_25V6K

10U_0805_25V6K

+5VALWP

12

1

+

PC102

220U_6.3V_M

2

3 3

3VALWP
TDC 6.08A
Peak Current 8.11A
OCP current 9.73A
TYP MAX
H/S Rds(on) :22mohm , 30mohm
L/S Rds(on) :12.1mohm ,17mohm

4 4

A

EC_ON<43>

USBCHG_DET_D<43>

VCOUT0_PH#<43>

VIN

LL4148_LL34-2

B

3V_EN

5V_EN

PD102

2

1

3

BAS40CW_SOT323-3

PD100 SBR2U30P1-7_POWERDI123-2

12

@

1M_0402_1%

1 2

@

PD101

PR113

2.2K_0402_5%

1 2

1 2

PR115

1 2

PR111 0_0402_5%

1 2

PR112 0_0402_5%

12

12

PR116

PC120

@

402K_0402_1%

PJP100

+3VALWP

4.7U_0603_6.3V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

1 2

PAD-OPEN 4x4m

2012/06/22 2013/06/21

C

+3VALW

+5VALWP

Compal Secret Data

Deciphered Date

PJP101

1 2

PAD-OPEN 4x4m
PJP102

1 2

PAD-OPEN 4x4m

D

+5VALW

5VALWP
TDC 10.64A
Peak Current 14.19A
OCP current 17.03A
TYP MAX
H/S Rds(on) 11.2mohm , 14mohm
L/S Rds(on) :3.7mohm , 5mohm

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PWR-3VALWP/5VALWP

LA-9331P

E

55 61Friday, June 22, 2012

0.1

5

4

3

2

1

20

PU200

VTT

PAD

VTTGND

VTTSNS

GND

VTTREF

VDDQ

FB

6

PJP201

PAD-OPEN 1x1m

21

1

2

3

4

5

1.35V_FB

+1.35VP

12

PC211 220P _0402_50V8J~ D

1 2

PR204

8.06K_04 02_1%

PR207
10K_040 2_1%

1 2

VTTREF_ 1.35V

+1.35VP

12

VLDOIN_1.3 5V

PJP200

B+

D D

+1.35VP

C C

1.35VP
TDC 13.75A
Peak Current 19.64A
OCP current 23.57A

@

2

112

JUMP_43 X118

0.68UH_P CMC063T-R68MN _15.5A_20%

1 2

1

+

PC201
330U_2.5 V_M

2

1.35V_B+

12

PL201

PR200

1 2

2.2_0603 _5%

12

PC203

PC202

4.7U_0805_25V6-K

4.7U_0805_25V6-K

PR202

4.7_1206_5%

PC212

680P_0603_50V7K

12

12

PC205

PC204

0.1U_0402_25V6
2200P_0402_50V7K

12

SNUB_1.35V

12

PR206

0_0402_ 5%

SYSON<43,56,60>

1 2

5

PQ201

SIR472DP-T1-GE3_POWERPAK8-5~D

123

5

PQ203

213

SIR818DP-T1_POWERPAK-SO8-5~D

12

PC206

0.22U_06 03_10V7K

1 2

4

+5VALW

4

@

PC215

1U_0402 _6.3VX5R

+5VALW

SUSP#<10,43,56,61>

PR203

5.1_0603 _5%

1 2

0_0402_ 5%

1 2

PR201

6.04K_04 02_1%

1 2

12

PC210
1U_0603 _10V6K

PC213
1U_0603 _10V6K

1 2

PR208

BOOT_1.3 5V

DH_1.35V

SW_1 .35V

DL_1.35V

VDD_1.35 V

VDDP_1.3 5V

12

CS_1.35V

VDDP_1.3 5V

1.35V_B+

S5_1.35V

S3_1.35V

PC216

0.1U_0402_10V7K

@

15

LGATE

14

PGND

13

CS

RT8207M ZQW_W QFN20_3X3

12

VDDP

11

VDD

PR205

1M_0402 _1%

1 2

17

16

PHASE

PGOOD

9

10

19

18

BOOT

UGATE

VLDOIN

S5

S3

TON

8

7

0.675Volt +/- 5%
TDC 0.7A
Peak Current 1A
OCP Current 1.2A

12

12

PC207

10U_0805_6.3V6M

12

PC214
.1U_0402 _16V7K

@

+1.35VP

PC208

10U_0805_6.3V6M

PC209

0.033U_0 402_16V7~D

+0.675VSP

TYP MAX
H/S Rds(on) :12.2mohm , 15mohm

B B

L/S Rds(on) :2.7mohm , 3.3mohm

+0.675VS

@

PJP202

PAD-OPEN 1x1m

12

+0.675VSP

PJP203

@

+1.35V +1.35VP

1 2

PAD-OPEN 4x4m

PJP204

@

1 2

PAD-OPEN 4x4m

A A

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/06/ 22 2013/06/ 21

3

Compal Secret Data

Deciphered Date

Title

ze Docum ent Number R ev

Si

2

Date: Sheet of

Compal Electronics, Inc.

PWR-1.35VP/0.675VSP

LA-9331P

1

0.1

56 61Friday, June 22, 2012

5

4

3

+1.05VP_ B+

2

PJP300

@

2

112

JUMP_43 X118

1

B+

+3VS

12

12

D D

PR300
100K_04 02_5%

1 2

PC303

PC302

0.1U_0402_25V6

2200P_0402_50V7K

12

12

PC305

PC304

4.7U_0805_25V6-K

4.7U_0805_25V6-K

PU300

PR302

PR307
10K_040 2_1%

1 2

TRIP_+1.05 VP

EN_+1.05 VP

FB_+1.05 VP

RF_+1.05 VP

12

PR305

470K_04 02_1%

1 2

@

PC307

69.8K_04 02_1%

12

PR303

0_0402_ 5%

SYSON<43,56,59>

C C

B B

1 2

0.22U_04 02_16V7K

1

2

3

4

5

PR306

4.99K_04 02_1%

VBST

PGOOD

TRIP

DRVH

EN

SW

V5IN

VFB

DRVL

TST

TPS5121 2DSCR_SON10_ 3X3

12

BST_+1.0 5VP

10

UG_+1.05 VP

9

SW_+ 1.05VP

8

+1.05VP_ 5V

7

LG_+1.05 VP

6

11

TP

+1.05V +1.05VP

PR301

1 2

2.2_0603 _5%

PC308

1 2

1U_0603 _10V6K

PC306

.1U_0603 _25V7K

12

+5VALW

FDMC769 2S_POWER3 3-8-5

PJP301

@

1 2

PAD-OPEN 4x4m

PQ303

PQ301
FDMC888 4_POWER33 -8-5

3 5

241

3 5

241

1UH_PCM C063T-1R0MN_1 1A_20%

12

4.7_1206 _5%

SNB_1.05 VP

12

1000P_0 402_50V7K

PL301

1 2

PR304

PC309

+1.05VP

1

+

PC301
330U_2.5 V_M

2

+1.05VP

TDC 4.56A
Peak Current 6.51A
OCP current 7.81A
TYP MAX
H/S Rds(on) :22mohm , 30mohm
L/S Rds(on) :10.8mohm ,13.6mohm

A A

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/06/ 22 2013/06/ 21

3

Compal Secret Data

Deciphered Date

Title

ze Docum ent Number R ev

Si

2

Date: Sheet of

Compal Electronics, Inc.

PWR-+1.05VP

LA-9331P

0.1

57 61Friday, June 22, 2012

1

A

1 1

B

C

D

PR400

12

10K_0402_5%

+3VS

+1.5VSP
TDC 0.66A
Peak Current 0.88A
OCP current 1.06A

12

12

@

PL401

1 2

PR401

4.7_0603_5%

@

PC407

680P_0402_50V7K

+1.5VS

PR402

30.1K_0402_1%

PR405

20K_0402_1%

12

12

2 1

PAD-OPEN 1x2m~D@

PC402

22P_0402_50V8J

PJP401

+1.5VSP

12

12

12

12

PC405

PC403

PC404

47P_0402_50V8J

22U_0805_6.3VAM

22U_0805_6.3VAM

+1.5VSP

PU400

+3VALW

2 2

SUSP#<10,43,56,59>

3 3

PJP400

2 1

PAD-OPEN 1x2m~D@

12

0_0402_5%

1 2

PR403

PC400
22U_0805_6.3VAM

EN_1.5VSP

1.5VSP_VIN

12

PC401

0.1U_0402_25V6

PR404

@

47K_0402_5%

12

12

PC406

.1U_0402_16V7K

@

4

10

9

8

5

LX

PVIN

PG

LX

PVIN

SVIN

FB

EN

TP

NC

7

11

SYN470DBC_DFN10_3X3

1.5VSP_LX

2

3

1.5VSP_FB

6

NC

1

1UH_NRS4018T1R 0NDGJ_3.2A_30%

SNUB_1.5VSP

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

DELL CONFIDENTIAL/PROPRIETARY

Title

ze Document Num ber Rev

Si

Date: Sheet of

Compal Electronics, Inc.

PWR-1.5VSP

LA-9331P

D

58 61Friday, June 22, 2012

0.1

5

4

3

2

1

+5VS

PC501

0.22U_0603_16V7K

12

+VCCIO_OUT

D D

VIDSOUT<10>

VIDALERT_N<10>

VIDSCLK<10>

IMVP_VR_ON<43>

PR519 1.91K_0402_1%

12

PC510

47P_0402_50V8J~D

@

PC519

1800P_0402_50V8F~D

PR539

1 2

909_0402_1%

1 2

PC526

4700P_0402_50V7K~D

12

12

12

12

PC547

.1U_0402_16V7K

12

1 2

PR524

1 2

0_0402_5%~D

1 2

3.83K_0402_1%

@

PC517

12

39P_0402_50V8J

12

@

22P_0402_50V8J~D

PC525

39P_0402_50V8J

1 2

ISUMN

PR522

0_0402_5%~D

PR525

PR532

130K_0402_1%

+3VS

IMVP_PWRGD<6,17,43>

PC500

1 2

0.01U_0402_50V7K

PR521

100K_0402_1%

C C

VR_HOT#<43>

+1.05VS

B B

ISEN3

ISEN2

ISEN1

A A

12

PR527

@

1 2

0_0402_5%

@

PR542

1 2

154K_0402_1%

PC539

0.22U_0402_6.3V6K

PC540

0.22U_0402_6.3V6K

PC544

0.22U_0402_6.3V6K

PR500 110_0402_1%~D

PR503 75_0402_5%@

PR504 54.9_0402_1%

12

PR505 0_0402_5%

1 2

PR506 0_0402_5%

1 2

PR508 0_0402_5%

1 2

PR511 0_0402_5%

1 2

VCC_PGOOD

VR_HOT#1

12

PH500

470K_0402_5%_ TSM0B474J4702RE

PR528

27.4K_0402_1%

12

@

FBCOMP

12

12

1 2

1 2

VCCSENSE<10>

VSSSENSE<10>

10_0402_1%

PR543
2K_0402_1%

PC527
330P_0402_50V7K~D

PC523

12

12

VR_ON

IMON

NTC

FB2/VSEN

390P_0402_50V7K

PR533

12

PR537

2.94K_0402_1%

PC541

@

1 2

330P_0402_50V7K

PC546

1 2

0.01U_0402_50V7K

SCLK

COMP

12

SDA

ALERT#

FB

PC520

1
2
3
4
5
6
7
8

33

PR529

@

1 2

0_0402_5%

12

@

PR507

49.9K_0402_1%~D

1 2

PR509

34K_0402_1%

1 2

PR512

24.9K_0402_1%

1 2

SCLK
VR_ON
PGOOD
IMON
VR_HOT#
NTC
COMP
FB

PAD

PR531

0_0402_5%

@

PR540

0_0402_5%

12

PC545

0.082U_0402_16V7K

BOOT2
UGATE2

PHASE2

32

27

30

28

29

25

26

31

SDA

BOOT2

PROG2

PROG3

ALERT#

FB2/VSEN9ISEN310ISEN211ISEN112RTN13ISUMN14ISUMP15VDD

1 2

1 2

PHASE2

UGATE2

LGATE2

SLOPE/PROG1

LGATE1
PHASE1
UGATE1

BOOT1

16

ISL95812HRZ-T_QFN32_4x4

12

PC521

4700P_0402_50V7K~D

PR545

1 2

1.5K_0402_1%

0_0402_5%

1 2

10KB_0402_5%_ERTJ0ER103J

1 2

24
23

VDDP

22

PWM3

21
20
19
18
17

VIN

PU500

12

PR535

453_0402_1%

PC528

0.15U_0402_10V6K~D

1 2

PR548

PR549

11K_0402_1%

1 2

PH501

ISUMN

1 2

PWM3

0.1U_0603_25V7K~D

0.033U_0603_25V7M~D

2.61K_0402_1%

PR501

0_0402_5%~D

+5VALW

PC509

1U_0603_10V6K

1 2

LGATE2

PWM3

LGATE1

PHASE1

UGATE1

BOOT1

0_0402_5%~D

1 2

12

PC511

0.22U_0603_25V7K

1_0402_1%~D

1 2

12

PC518

1U_0603_10V6K

PC529

1 2

PC538

1 2

PR551

1 2

PR526

PR530

PC502

1U_0603_10V6K

6

7

3

4
9

1 2

VCORE_VDDP

0_0402_5%~D

CPU_B+

ISUMP

PU501

UGATE

VCC

FCCM

BOOT

PWM

PHASE

LGATE

GND
TP

ISL6208BCRZ-T_QFN8_2X2

PR520
0_0402_5%~D

@

PR523

12

+5VALW

Local sense put on HW site

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1 2

12

PR502

2.2_0603_5%

BOOT1

LGATE1

UGATE2

PHASE2

BOOT2

2.2_0603_5%

LGATE2

2.2_0603_5%

UGATE3

PHASE3

LGATE3

PR534

UGATE1

PHASE1

PR550

12

1 2

PC522

0.22U_0603_16V7K

PQ509

12

1 2

PC542

0.22U_0603_16V7K

4

PQ511

4

1

BOOT3

2

8

5

DELL CONFIDENTIAL/PROPRIETARY

5

PQ501

4

5

PQ503

4

213

VCC_core (Base on PDDG rev 0.8)
TDC 33A
Peak Current 95A
DC Load line -1.5mV/A
Icc_Dyn_VID1 60A
OCP current 114A
DCR 0.82m ohm

5

PQ505

4

SIR472DP-T1-GE3_POWERPAK8-5~D

123

5

PQ507

4

213

SIR818DP-T1-GE3_POWERPAK8-5

5

PQ510

4

123

SIR472DP-T1-GE3_POWERPAK8-5~D

5

213

SIR818DP-T1-GE3_POWERPAK8-5

2

123

PQ512

5

PQ502

4

SIR472DP-T1-GE3_POWERPAK8-5~D

123

SIR472DP-T1-GE3_POWERPAK8-5~D

5

PQ504

4

213

PR513

4.7_1206_5%

SIR818DP-T1-GE3_POWERPAK8-5

PQ506

PQ508

4

5

4

SIR818DP-T1-GE3_POWERPAK8-5

CPU_B+

5

4

123

5

213

PC512

10U_0805_25V6K

SIR472DP-T1-GE3_POWERPAK8-5~D

123

5

12

SNB_CPU_P2

12

PR541

213

4.7_1206_5%

SIR818DP-T1-GE3_POWERPAK8-5

CPU_B+

12

PC534

PC533

10U_0805_25V6K

10U_0805_25V6K

SIR472DP-T1-GE3_POWERPAK8-5~D

12

SNB_CPU_P1

12

PR554

4.7_1206_5%

SIR818DP-T1-GE3_POWERPAK8-5

12

12

PC503

10U_0805_25V6K

12

PC508

SNB_CPU_P3

680P_0603_50V7K

12

12

PC513

10U_0805_25V6K

PC524

680P_0603_50V7K

ISUMP

12

PC535

10U_0805_25V6K

PC543

1 2

680P_0603_50V7K

ISUMP

Title

Size Document Number Rev

Date: Sheet of

12

PC505

PC506

PC504

10U_0805_25V6K

10U_0805_25V6K

0.22UH +-20% PCMB104T-R22MS 35A

4

P3_SW

3

PR510

10K_0603_1%

ISEN3

V1N

PR514

1 2

3.65K_0603_1%

V2N

ISUMP

12

12

3.65K_0603_1%

12

PC514

PC515

10U_0805_25V6K

0.1U_0402_25V6K~D

0.22UH +-20% PCMB104T-R22MS 35A

PR536

3.65K_0603_1%

12

PR552

P2_SW

1 2

1 2

ISEN2

V1N

V3N

12

PC536

PC537

0.1U_0402_25V6K~D
2200P_0402_50V7K~D

0.22UH +-20% PCMB104T-R22MS 35A

P1_SW

10K_0603_1%

1 2

ISEN1

V2N

@

V3N

10K_0402_1%

Compal Electronics, Inc.

+VCC_CORE

CPU_B+

12

12

PC507

0.1U_0402_25V6K~D
2200P_0402_50V7K~D

PL501

1

V3N

2

12

PR516

@

1_0402_5%

1 2

PR518

@

1_0402_5%

1 2

PL504

FBMA-L11-453215-800LMA90T_1812

1 2

12

PC516

2200P_0402_50V7K~D

PL502

1

4

3

2

PR538

10K_0603_1%

PR546

@

1_0402_5%

12

PR547

@

1_0402_5%

12

1

PL503

12

12

PC530

1

+

PC531

2

100U_25V_M

1

+VCC_CORE

2

V1N

12

ISUMN

59 61Friday, June 22, 2012

12

4

3

PR553

PR555

@

1_0402_5%

PR557

LA-9331P

+VCC_CORE

PR515

1 2

10_0402_1%

ISUMN

B+

+VCC_CORE

V2N

12

PR544
10_0402_1%

ISUMN

1

1

+

+

PC532

2

2

100U_25V_M

100U_25V_M

PR556
10_0402_1%

0.1

A

VIN

1 1

PR706

PC701

2.2U_0805_25V6K

2 2

ACOFF

BATT_TEMP

3 3

12

3.3_1210_5%

PR701

12

3.3_1210_5%

1 2

2

ACIN

1 2

10K_0402_5%

BATT_TEMP<43,57>

5

12

61

PR723

PQ702 SI7149DP

PR704

200K_0402_1%

V1

PQ710A

2N7002BKS 2N SOT363-6

PR720

47K_0402_5%

1 2

2

H_PROCHOT#<6,43>

1
2
3

4

Back_G1

PDTA144EU PNP_SOT 323

2

1U_0603_25V6K

PQ707

2

13

ACIN<17,29,43,47,57>

13

2

61

PQ718A

2N7002BKS 2N SOT363-6

12

PC729

@

13

D

2

G

S

1 3

PQ709

DDTC115EUA-7-F_SOT323

5

ACIN

PQ713

DDTC115EUA-7-F_SOT323

100_0402_1%

ADP_I<43,57>

.1U_0402_16V7K

PQ715

@

SSM3K7002FU_SC70-3

P2

12

12

PR707
150K_0402_1%

3

PQ710B

4

2N7002BKS 2N SOT363-6

PR717

PR721

PR729

PC732

PQ703SI7149DP

1
2
3

PR702

200K_0402_1%

+5VALW

12

@

PR735

PR736

@

33K_0402_1%~D

33K_0402_1%~D

4

Back_G2

12

0.1U_0402_10V7K

1000P_0402_50V7K

1 2

EC_SMB_CK1<57>

EC_SMB_DA1<57>

ISL8731_REF

12

12

12

PC734

@

0.01U_0402_25V7K

@

5

PC710

@

PC714

1 2

PC735

12

PC702

0.1U_0603_25V7K

BATT_TEMP<43,57>

VDDP_LDO

12

100K_0402_1%

12

PC717

158K_0402_1%

0.1U_0402_10V7K

12

PR730

4.7K_0402_5%

1 2

12

1 2

PC733

0.01U_0402_25V7K

P3

5

1 2

5600P_0402_25V7K~D

PC703

3

PQ716B

4

PR719

49.9K_0402_1%

12

PR738

0.01U_0402_25V7K

PR739

2N7002BKS 2N SOT363-6

33K_0402_1%~D

33K_0402_1%~D

Iada=0~4.62A(90W)

ADP_I = 19.9*Iadapter*Rsense

VIN

1 2

12

@

ISL8731_ICREF

12

@

For DT Mode

VIN

12

4 4

ACOFF

PR737

3.3K_1206_5%~D

3

5

PQ718B

4

2N7002BKS 2N SOT363-6

A

BATT_TEMP<43,57>

V1

@

61

2

PQ716A

2N7002BKS 2N SOT363-6

0.005 +-1% 2512

1

2

VIN

PR712

10_1206_1%

1 2

PC712

1U_0603_25V6K

PR715

210K_0402_1%

PR722

0_0402_5%

12

PR724

0_0402_5%

12

ISL8731_EAJ

B

PR703

12

ISL8731_REF

PC728

@

0.1U_0402_10V7K

B

4

3

DCIN

ACSETIN

12

C

VIN

PQ705 SI7149DP

5

B+

CSIN

CSIP

10_0402_5%

PC713

1 2

27

UGATE

PHASE

ICOUT

CSSN

BOOT

VDDP

LGATE

PGND
CSOP

CSON

VFB

12

PR709

10_0402_5%

26

BST

25

21

24

23

20

19
18

17

VFB

15

16

NC

12

PR708

1 2

PC708

0.047U_0603_25V7M

0.1U_0402_25V6K~D

ISL8731_ICREF

1

28

PU700

22

DCIN

CSSP

ICREF

2

ACIN

13

ACOK

11

VDDSMB

10

SCL

9

SDA

14

NC

8

VICM

6

FBO

5

EAI

4

EAO

3

VREF

7

CE

12

GND

29

TP

ISL88731CHRTZ-T_QFN28_5X 5~D

B+_MXM

1

1

+

PC736

PC737

2

2

100U 25V M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

4

PL701

1UH_NRS4018T1R0NDGJ _3.2A_30%

1 2

PC711

0.1U_0402_25V6K~D

0_0603_5%

1 2

100U 25V M

VIN-<29>

PC709
1U_0603_10V6K

1 2

PR713

4.7_0603_5%

PR716

1 2

PR734

100_0402_5%

PR740

0.004_2512_1%

1

2

1 2

VDDP_LDO

DH_CHG

LX_CHG

+

2012/06/22 2013/06/21

P2

1
2
3

PC704

12

BST_CHGA

BATT+

4

3

VIN+<29>

Compal Secret Data

12

PC705

4.7U_0805_25V6-K

Deciphered Date

C

1
2
3

4

Back_G2Back_G1

12

12

0.1U_0603_25V7K

PC706

4.7U_0805_25V6-K

PC715

0.1U_0603_25V7K

1 2

PC716

1 2

1U_0603_10V6K

DL_CHG

PL703

SMB3025500YA_2P

1 2

PQ706SI7149DP

P3

5

CHG_B+

12

PC707

2200P_0402_25V7K~D

PQ701

5

4

123

PQ714

3 5

241

PQ704SI7149DP

1
2
3

PR710

47K_0402_1%

PQ711

DDTC115EUA-7-F_SOT323

SIR472DP-T1-GE3_POWERPAK8-5~D

5.6UH_FDVE1040-H- 5R6M-P3_9.2A_20%~D

1 2

12

PR728

@

SNUB_CHG

12

PC719

@

FDMC7692S_POWER33-8-5

4

Dis_G

1 2

13

PL702

4.7_1206_5%

680P_0402_50V7K

200K_0402_1%

2

VDDP_LDO

12

10_0402_5%

PR731

5

1 2

PR705

1 2

PR725

0.01_1206_1%

CHG

1

2

0.22U_0603_25V7K

B+

Title

PWR-Charger

Size D ocument Number Rev

LA-9331P

Date: Sheet of

D

CC = 3.52A (Normal)

CV = 13.3V

VIN

100K_0402_1%

PR711

V1

3

5

61

1 2

PQ717B

4

PQ717A

2N7002BKS 2N SOT363-6

12

PC720

PC721

10U_0805_25V5K~D

@

PR714

1 2

10K_0402_5%

ACOFF<43>

PC726

1 2

2

4

3

12

0_0402_5%

PR732

PC731

0.1U_0402_25V6K~D

Compal Electronics, Inc.

D

2N7002BKS 2N SOT363-6

BATT+

12

12

10U_0805_25V5K~D

60 61Friday, June 22, 2012

12

PC722

PC723

@

10U_0805_25V5K~D

10U_0805_25V5K~D

0.1

5

Based on PDDG rev 0.8 Table 5-1.

4

3

2

1

+VCC_CORE+VCC_CORE

D D

1

PC900
10U_080 5_4VAM

2

1

PC909
10U_080 5_4VAM

2

1

PC901
10U_080 5_4VAM

2

1

PC910
10U_080 5_4VAM

2

1

PC902
10U_080 5_4VAM

2

1

PC911
10U_080 5_4VAM

2

1

PC903
10U_080 5_4VAM

2

1

PC912
10U_080 5_4VAM

2

1

PC904
10U_080 5_4VAM

2

1

PC913
10U_080 5_4VAM

2

1

PC914
10U_080 5_4VAM

2

1

+

PC905

470U_D2 _2VM_R4.5M~D

2

1

+

PC906

470U_D2 _2VM_R4.5M~D

2

1

+

PC907

470U_D2 _2VM_R4.5M~D

2

1

+

PC908

470U_D2 _2VM_R4.5M~D

2

1

+

PC915

470U_D2 _2VM_R4.5M~D

2

+VCC_CORE

1

PC917
22U_080 5_6.3VAM

2

C C

1

PC922
22U_080 5_6.3VAM

2

1

PC935
22U_080 5_6.3VAM

2

1

PC940
22U_080 5_6.3VAM

2

1

PC918
22U_080 5_6.3VAM

2

1

PC923
22U_080 5_6.3VAM

2

1

PC936
22U_080 5_6.3VAM

2

1

PC941
22U_080 5_6.3VAM

2

1

PC919
22U_080 5_6.3VAM

2

1

PC924
22U_080 5_6.3VAM

2

1

PC937
22U_080 5_6.3VAM

2

1

PC942
22U_080 5_6.3VAM

2

1

PC920
22U_080 5_6.3VAM

2

1

PC925
22U_080 5_6.3VAM

2

1

PC938
22U_080 5_6.3VAM

2

1

PC943
22U_080 5_6.3VAM

2

1

PC921
22U_080 5_6.3VAM

2

1

PC926
22U_080 5_6.3VAM

2

1

PC939
22U_080 5_6.3VAM

2

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

Title

Size Documen t Number Rev

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR DECOUPLING

LA-9331P

61 61Friday, June 22, 2012

1

0.1