Compal LA-9303P Schematics
A
1 1
B
C
D
E
Compal Confidential
2 2
VBA20 LA9303P Schematics Document
INTEL SandyBridge C847/C807 CPU with DDRIII + PCH NM70
AIO M/B
3 3
4 4
A
http://sualaptop365.edu.vn
B
UMA only
REV: 0.1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2012/04/27 2013/04/27
2012/04/27 2013/04/27
2012/04/27 2013/04/27
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Cover Page
Cover Page
Cover Page
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
1 49Friday, August 10, 2012
1 49Friday, August 10, 2012
1 49Friday, August 10, 2012
E
0.2
0.2
0.2
A
B
C
D
E
Compal Confidential
Model Name : VBA20
File Name : LA-9303P
1 1
Sandy Bridge ULV
Intel
Processor
BGA1023
31mm x 24mm
17W
page 4~10
Memory BUS(DDR3)
Dule Channel
1.5V DDRIII 1333 MHz
RF IN
204pin DDRIII-SO-DIMM X2
BANK 0, 1
page 11,12
F
FDI x8
CLK=100MHz
2.7GT/s
LVDS Conn.
page 26
HDMI out
2 2
Conn.
page 25
LVDS
Intel
Panther Point
HDMI
PCH
NM70
1M ROM
page 13
4M ROM
page 13
PCIE
Port1
989pin BGA
25mm x 25mm
DMI x4
CLK=100MHz
2.5GB/s x4
page 13~21
USB port 10 USB port 3 USB port 0,1
TV Tuner
WLAN
On Mini Card On Mini Card
page 33 page 33
Port2 Port3
USB
PCIE
SATA 1.5/3.0/6.0 GT/S
USB 3.0/2.0
Conn x 2
(Side)
page 34
SATA 1.5/3.0 GT/S
USB port 8,9
USB 2.0
Conn x 2
(Rear)
page 23
HD Audio
Audio Codec
ALC-259-VB_GR
USB port 2
WebCAM
page 26
D-MIC
page 27
LAN/Card Reader
RTL8411
page 30
LPC BUS
SATA HDD
Conn.
page 21
port 0
SWITCH*4 Brd
page 23
3 3
LED*3+PWR SW
page 23
CardReader
Conn
page 31
RTC CKT.
page 37
Power On/Off CKT.
page 23
Fan Control
page 29
Transformer
page 31
RJ45
Conn
page 31
ENE KB9012-A3
page 35
SATA ODD
page 21
port 2
SPK Conn.
2W x2
page 28
HP Jcck
page 27
MIC IN
page 27
DC/DC INTERFACE
/Discharge.
4 4
page 28
Power Circuit
page 37~46
A
EC DEBUG CONNECTOR
page 35
http://sualaptop365.edu.vn
B
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2012/04/27 2013/04/27
2012/04/27 2013/04/27
2012/04/27 2013/04/27
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Block Diagrams
Block Diagrams
Block Diagrams
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
2 49Friday, August 10, 2012
2 49Friday, August 10, 2012
2 49Friday, August 10, 2012
E
0.2
0.2
0.2
A
Voltage Rails
Power Plane Description
VIN
B+
+VSB VSB always on power rail ON ON*ON
+VCCSUS3_3 +3VALW to +VCCSUS3_3 power rail for PCH
+CPU_CORE
+VGFX_CORE
+0.75VS 0.75VS switched power rail for DDR terminator OFF
+1.05VS_VTT +1.05VS_VTT power rail for CPU OFF
+1.5V
+1.5VS +1.5V to +1.5VS switched power rail
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
1 1
EC SM Bus1 address
Device
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
Core voltage for UMA graphic
1.5V power rail for CPU VDDIO and DDRIII
SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS
HIGH HIGH HIGH HIGH
LOW
LOW
LOW
HIGH
LOWLOWLOW
HIGHHIGHHIGH
HIGH
HIGH
EC SM Bus2 address
Address Address
DeviceHEX
S1 S3 S5
N/A N/A N/A
ON ON ON*+3VALW 3.3V always on power rail
ON ON ON*+5VALW 5V always on power rail
ON
ON OFF
ON OFF
ON OFF
ON OFF
ON OFF
ON OFF OFF
ON OFF+1.8VS 1.8V switched power rail OFF
ON ON+RTCVCC RTC power
ON
ON
ON
ON
ON
N/AN/AN/A
ON ON*
OFF
OFF
ON
OFFON OFF+3VS 3.3V switched power rail
OFFON OFF+5VS 5V switched power rail
ON
ON
ON
ON
OFF
OFFLOW LOW LOW LOW
HEX
PCIE(GPP) Port Table
1
2
3
SATA Port Table
0
6G
1
2
3G
3
4
5
ON
ON
OFF
OFF
OFF
DevicePort
LAN/Card reader
Mini Card(TV Tuner)
Mini Card(WLAN)
DevicePort
HDD
Disabled on NM70
ODD
Disabled on NM70
NC
NC
SKU ID(Project) Table
Project_ID2
(GPIO189)
USB Port Table
EHCI
EHCI OHCI
Project_ID1
(GPIO190)
1
1
PortUSB 2.0 USB 1.1
Device
0
USB (side I/O)
1
OHCI
USB (side I/O)
2
Web Camera
3
Mini Card(WLAN)
4
Disabled on NM70
5
Disabled on NM70
6
Disabled on NM70
7
Disabled on NM70
8
USB20- (Rear I/O)
9
USB20 (Rear I/O)
10
Mini Card(TV Tuner)
11
NC
12
Disabled on NM70
13
Disabled on NM70
SKU
00
10
0
1
SKU1
SKU2
X
X
807@
847@
BOM Structure Table
BTO Item BOM Structure
CPU C807
CPU C847
PCH NM70
PCH HM70
ME components
Unpop
USB30
LA-9303P 6 Layer PCB
SKU IO Select
PANEL Select
NM70@
ID0L@ ID1L@
NM70@
ID1L@ID0L@
807@
847@
NM70@
HM70@
CONN@
@
USB30@
GPIO64_H@
GPIO64_L@
GPIO65_H@
GPIO65_L@
ID0L@
ID0H@
ID1L@
ID1H@
GPIO64_L@ GPIO65_L@
GPIO65_L@GPIO64_H@
SM Bus Controller 0
Device Address
HEX
SM Bus Controller 1
Device Address HEX
Board ID / SKU ID Table for AD channel
Vcc
R2672
Board ID
0
1
2
3 0.819 V
4
5
6 2.200 V
3.3V +/- 5%
0
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC7
minV
AD_BID
0 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V
http://sualaptop365.edu.vn
typV
AD_BID
0 V
0.250 V0.216 V
0.503 V
3.300 V
V
AD_BID
0 V
0.289 V
0.538 V
0.875 V
1.264 V1.185 V
1.759 V1.650 V
2.341 V
3.300 V
BOARD ID Table
Board
ID
0
max
1
*
2
3
4
PCB
Revision
0.1
0.2
0.3
0.4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
2012/04/27 2013/04/27
2012/04/27 2013/04/27
2012/04/27 2013/04/27
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Notes List
Notes List
Notes List
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
3 49Friday, August 10, 2012
3 49Friday, August 10, 2012
3 49Friday, August 10, 2012
0.2
0.2
0.2
A
1 1
2 2
eDP_COMPIO and ICOMPO signals
should be shorted near balls and
routed with typical impedance
<25 mohms
can't be left floating
,even if disable eDP function...
3 3
+1.05VS_VTT
12
R2
R2
24.9_0402_1%
24.9_0402_1%
DMI_CRX_PTX_N0<15>
DMI_CRX_PTX_N1<15>
DMI_CRX_PTX_N2<15>
DMI_CRX_PTX_N3<15>
DMI_CRX_PTX_P0<15>
DMI_CRX_PTX_P1<15>
DMI_CRX_PTX_P2<15>
DMI_CRX_PTX_P3<15>
DMI_CTX_PRX_N0<15>
DMI_CTX_PRX_N1<15>
DMI_CTX_PRX_N2<15>
DMI_CTX_PRX_N3<15>
DMI_CTX_PRX_P0<15>
DMI_CTX_PRX_P1<15>
DMI_CTX_PRX_P2<15>
DMI_CTX_PRX_P3<15>
FDI_CTX_PRX_N0<15>
FDI_CTX_PRX_N1<15>
FDI_CTX_PRX_N2<15>
FDI_CTX_PRX_N3<15>
FDI_CTX_PRX_N4<15>
FDI_CTX_PRX_N5<15>
FDI_CTX_PRX_N6<15>
FDI_CTX_PRX_N7<15>
FDI_CTX_PRX_P0<15>
FDI_CTX_PRX_P1<15>
FDI_CTX_PRX_P2<15>
FDI_CTX_PRX_P3<15>
FDI_CTX_PRX_P4<15>
FDI_CTX_PRX_P5<15>
FDI_CTX_PRX_P6<15>
FDI_CTX_PRX_P7<15>
FDI_FSYNC0<15>
FDI_FSYNC1<15>
FDI_INT<15>
FDI_LSYNC0<15>
FDI_LSYNC1<15>
W=12mil L=500mil S=15mil
EDP_COMP
B
UCPU1A
UCPU1A
M2
DMI_RX#[0]
P6
DMI_RX#[1]
P1
DMI_RX#[2]
P10
DMI_RX#[3]
N3
DMI_RX[0]
P7
DMI_RX[1]
P3
DMI_RX[2]
P11
DMI_RX[3]
K1
DMI_TX#[0]
M8
DMI_TX#[1]
N4
DMI_TX#[2]
R2
DMI_TX#[3]
K3
DMI_TX[0]
M7
DMI_TX[1]
P4
DMI_TX[2]
T3
DMI_TX[3]
U7
FDI0_TX#[0]
W11
FDI0_TX#[1]
W1
FDI0_TX#[2]
AA6
FDI0_TX#[3]
W6
FDI1_TX#[0]
V4
FDI1_TX#[1]
Y2
FDI1_TX#[2]
AC9
FDI1_TX#[3]
U6
FDI0_TX[0]
W10
FDI0_TX[1]
W3
FDI0_TX[2]
AA7
FDI0_TX[3]
W7
FDI1_TX[0]
T4
FDI1_TX[1]
AA3
FDI1_TX[2]
AC8
FDI1_TX[3]
AA11
FDI0_FSYNC
AC12
FDI1_FSYNC
U11
FDI_INT
AA10
FDI0_LSYNC
AG8
FDI1_LSYNC
AF3
eDP_COMPIO
AD2
eDP_ICOMPO
AG11
eDP_HPD#
AG4
eDP_AUX#
AF4
eDP_AUX
AC3
eDP_TX#[0]
AC4
eDP_TX#[1]
AE11
eDP_TX#[2]
AE7
eDP_TX#[3]
AC1
eDP_TX[0]
AA4
eDP_TX[1]
AE10
eDP_TX[2]
AE6
eDP_TX[3]
IVY-BRIDGE_BGA1023
IVY-BRIDGE_BGA1023
C867@
C867@
DMI Intel(R) FDI
DMI Intel(R) FDI
eDP
eDP
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PCI EXPRESS -- GRAPHICS
PCI EXPRESS -- GRAPHICS
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
C
W=12mil L=500mil S=15mil
G3
G1
G4
H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7
K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6
G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4
F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4
PEG_COMP
R1
R1
24.9_0402_1%
24.9_0402_1%
Celeron 867C867@
+1.05VS_VTT
12
D
PEG_ICOMPI and RCOMPO signals should
be shorted and routed
with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with max length = 500 mils
- typical impedance = 14.5 mohms
HR 1.3G
SA00005BH40(S IC AV8062701148901 SR0FK J1 1.3G ABO!)
E
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
2012/11/222011/11/22
2012/11/222011/11/22
2012/11/222011/11/22
D
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(1/7) DMI,FDI,PEG
PROCESSOR(1/7) DMI,FDI,PEG
PROCESSOR(1/7) DMI,FDI,PEG
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
Friday, August 10, 2012
Friday, August 10, 2012
Friday, August 10, 2012
E
0.2Custom
0.2Custom
0.2Custom
494
494
494
http://sualaptop365.edu.vn
A
1 1
PCH->CPU
UNCOREPWRGOOD:非CORE
SM_DRAMPWROK:DRAM power ok
RESET#:都ok後後CPU做reset
外外外
OK
Follow DG 1.5& Tacoma_Fall2 1.0
reserve XBOX
@
@
C65
R6 10K_0402_5%R6 10K_040 2_5%
2 2
0.1U_0402_16V4ZC65
0.1U_0402_16V4Z
12
12
Follow DG 1.5 & Tacoma_Fall2 1.0 Use open drain logic gate:
Buffered reset to CPU
PLT_A_RST#
PLT_A_RST#
H_CPUPWRGD
R14
R14
0_0402_5%
0_0402_5%
@
@
1 2
+3VS
12
5
U1
U1
1
P
NC
Y
2
A
G
SN74LVC1G07DCKR_S C70-5
SN74LVC1G07DCKR_S C70-5
3
+1.05VS_VTT PU pop
75ohm
series resister pop 43ohm
+1.05VS_VTT
C66
C66
0.1U_0402_16V4Z
0.1U_0402_16V4Z
BUFO_CPU_RST# BUF_CPU_RST#
4
12
RESET#:都ok後後CPU做reset
Follow DG 1.5 & Tacoma_Fall2 1.0
3 3
C67
C67
0.1U_0402_16V4Z
0.1U_0402_16V4Z
SYS_PWROK<15>
PM_DRAM_PW RGD<15>
+3VALW
12
5
U2
U2
1
B
Y
VCC
2
A
G
MC74VHC1G09DFT2G_ SC70-5
MC74VHC1G09DFT2G_ SC70-5
3
PM_SYS_PWRGD_BUF
4
+1.5V_CPU_VDDQ
Use open drain logic gate:
+1.5V_CPU_VDDQ PU pop 200ohm
series resister pop 130ohm
12
R16
R16
200_0402_5%
200_0402_5%
1 2
R18 130_04 02_5%R18 130_04 02_5%
H_PROCHOT#<3 5>
R12
R12
75_0402_5%
75_0402_5%
R15
R15
43_0402_1%
43_0402_1%
1 2
PM_DRAM_PW RGD_R
B
PROC_SELECT#
PH VCPLL and
connect to PCH
DF_TVS
follow Checklist 1.5
+1.05VS_VTT
偵偵
CPU
有有有有
三三三三
R7 62_040 2_5%R7 62_040 2_5%
12
H_PROCHOT# H_PROCHOT#_R
H_CPUPWRGD<18>
UNCOREPWRGOOD:非CORE
SM_DRAMPWROK:DRAM power ok
H_SNB_IVB#<17>
T1 @PADT1 @PAD
H_PECI<18,35>
R8
R8
56_0402_5%
56_0402_5%
1 2
H_THRMTRIP#<18>
H_PM_SYNC<15>
@
@
1 2
R13 0 _0402_5%
R13 0 _0402_5%
PM_DRAM_PW RGD_R
BUF_CPU_RST#
0.1_10
C476
C476
@
@
H_CPUPWRGD _R
12
180P_0402_50V8 J
180P_0402_50V8 J
12/22 Add(ESD request)
C
H_CATERR#
H_PECI
H_CPUPWRGD _R
外外外
OK
C105
C105
180P_0402_50V8 J
180P_0402_50V8 J
F49
C57
C49
A48
C45
D45
C48
B46
BE45
D44
12
UCPU1B
UCPU1B
PROC_SELECT#
PROC_DETECT#
CATERR#
PECI
PROCHOT#
THERMTRIP#
PM_SYNC
UNCOREPWRGOOD
SM_DRAMPWROK
RESET#
IVY-BRIDGE_BGA1023
IVY-BRIDGE_BGA1023
C867@
C867@
D
CLK_CPU_DPLL#
CLK_CPU_DPLL
Checklist1.5 P.67 Graphis Disable Guide
eDP disable:
DPLL_REF_SSCLK PD 1K_5% to GND
DPLL_REF_SSCLK# PU 1K_5% to
+1.05VS_VTT
J3
BCLK
MISC THERMAL PWR MANAGEMENT
MISC THERMAL PWR MANAGEMENT
DPLL_REF_CLK
DPLL_REF_CLK#
CLOCKS
CLOCKS
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
DDR3
MISC
DDR3
MISC
JTAG & BPM
JTAG & BPM
BCLK#
PRDY#
PREQ#
TCK
TMS
TRST#
TDO
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
H2
CLK_CPU_DPLL
AG3
CLK_CPU_DPLL#
AG1
SM_RCOMP0,SM_RCOMP1
W=20mil L=500mil S=13mil
SM_RCOMP2
W=15mil
L=500mil
SM_DRAMRST#
AT30
S=13mil
SM_RCOMP0
BF44
SM_RCOMP1
BE43
SM_RCOMP2
BG43
DDR3 Compensation Signals
N53
N55
XDP_TCK
L56
XDP_TMS
L55
XDP_TRST#
J58
XDP_TDI
M60
TDI
L59
K58
G58
E55
E59
G55
G59
H60
J59
J61
XDP_TDO
XDP_DBRESET#
XDP_DBRESET#
Tacoma_Fall2 1.0 PU 1K +3VS
Check list 1.5 PU 1K +3VS
Debug port DG1.1-1.3 50~5K
ohm
R4 1K_0402_5%R4 1K_040 2_5%
R5 1K_0402_5%R5 1K_040 2_5%
CLK_CPU_DMI <14>
CLK_CPU_DMI# <14>
SM_DRAMRST# <6>
R9 140_0402_1%R9 140_0402_1%
R10 25.5_0402_1%R10 25.5_0402_1%
R11 200_0402_1%R11 200_0402_1%
T2@ PAD T2@ PAD
T3@ PAD T3@ PAD
T4@ PAD T4@ PAD
T5@ PAD T5@ PAD
T6@ PAD T6@ PAD
R17 1K_0402_5%R17 1K_0402_5%
E
12
12
12
12
12
XDP_DBRESET# <15>
12
+1.05VS_VTT
+3VS
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
http://sualaptop365.edu.vn
B
2011/11/ 22 2012/11/ 22
2011/11/ 22 2012/11/ 22
2011/11/ 22 2012/11/ 22
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(3/7) DDRIII
PROCESSOR(3/7) DDRIII
PROCESSOR(3/7) DDRIII
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
Friday, August 10, 20 12
Friday, August 10, 20 12
Friday, August 10, 20 12
E
5 4 9
5 4 9
5 4 9
0.2
0.2
0.2
A
UCPU1C
DDR_A_D[0..63]<11>
1 1
2 2
3 3
DDR_A_BS0<11>
DDR_A_BS1<11>
DDR_A_BS2<11>
DDR_A_CAS#<11>
DDR_A_RAS#<11>
DDR_A_WE#<11>
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
AG6
AP11
AJ10
AR11
AT13
AU13
BA13
BB11
AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43
AW48
BC48
BC45
AR45
AT48
AY48
BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56
BD37
BF36
BA28
BE39
BD39
AT41
UCPU1C
SA_DQ[0]
AJ6
SA_DQ[1]
SA_DQ[2]
AL6
SA_DQ[3]
SA_DQ[4]
AJ8
SA_DQ[5]
AL8
SA_DQ[6]
AL7
SA_DQ[7]
SA_DQ[8]
AP6
SA_DQ[9]
AU6
SA_DQ[10]
AV9
SA_DQ[11]
AR6
SA_DQ[12]
AP8
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
BC7
SA_DQ[16]
BB7
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
BA7
SA_DQ[20]
BA9
SA_DQ[21]
BB9
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
B
AU36
SA_CK[0]
AV36
SA_CK#[0]
AY26
SA_CKE[0]
AT40
SA_CK[1]
AU40
SA_CK#[1]
BB26
SA_CKE[1]
BB40
SA_CS#[0]
BC41
SA_CS#[1]
AY40
SA_ODT[0]
BA41
SA_ODT[1]
DDR_A_DQS#0
AL11
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AR8
AV11
AT17
AV45
AY51
AT55
AK55
AJ11
AR10
AY11
AU17
AW45
AV51
AT56
AK54
BG35
BB34
BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
AY28
AU26
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
SA_CLK_DDR0 <11>
SA_CLK_DDR#0 <11>
DDRA_CKE0_DIMMA <11>
SA_CLK_DDR1 <11>
SA_CLK_DDR#1 <11>
DDRA_CKE1_DIMMA <11>
DDRA_CS0_DIMMA# <11>
DDRA_CS1_DIMMA# <11>
SA_ODT0 <11>
SA_ODT1 <11>
DDR_A_DQS#[0..7] <11>
DDR_A_DQS[0..7] <11>
DDR_A_MA[0..15] <11>
C
UCPU1D
BD13
BF12
BD10
BD14
BE13
BF16
BE17
BE18
BE21
BE14
BG14
BG18
BF19
BD50
BF48
BD53
BF52
BD49
BE49
BD54
BE53
BF56
BE57
BC59
AY60
BE54
BG54
BA58
AW59
AW58
AU58
AN61
AN59
AU59
AU61
AN58
AR58
AK58
AL58
AG58
AG59
AM60
AL59
AF61
AH60
BG39
BD42
AT22
AV43
BF40
BD45
UCPU1D
AL4
SB_DQ[0]
AL1
SB_DQ[1]
AN3
SB_DQ[2]
AR4
SB_DQ[3]
AK4
SB_DQ[4]
AK3
SB_DQ[5]
AN4
SB_DQ[6]
AR1
SB_DQ[7]
AU4
SB_DQ[8]
AT2
SB_DQ[9]
AV4
SB_DQ[10]
BA4
SB_DQ[11]
AU3
SB_DQ[12]
AR3
SB_DQ[13]
AY2
SB_DQ[14]
BA3
SB_DQ[15]
BE9
SB_DQ[16]
BD9
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
BF8
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
DDR_B_D[0..63]<12>
DDR_B_BS0<12>
DDR_B_BS1<12>
DDR_B_BS2<12>
DDR_B_CAS#<12>
DDR_B_RAS#<12>
DDR_B_WE#<12>
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
D
BA34
SB_CK[0]
AY34
SB_CK#[0]
AR22
SB_CKE[0]
BA36
SB_CK[1]
BB36
SB_CK#[1]
BF27
SB_CKE[1]
BE41
SB_CS#[0]
BE47
SB_CS#[1]
AT43
SB_ODT[0]
BG47
SB_ODT[1]
DDR_B_DQS#0
AL3
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
AV3
BG11
BD17
BG51
BA59
AT60
AK59
AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61
BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
E
SB_CLK_DDR0 <12>
SB_CLK_DDR#0 <12>
DDRB_CKE0_DIMMB <12>
SB_CLK_DDR1 <12>
SB_CLK_DDR#1 <12>
DDRB_CKE1_DIMMB <12>
DDRB_CS0_DIMMB# <12>
DDRB_CS1_DIMMB# <12>
SB_ODT0 <12>
SB_ODT1 <12>
DDR_B_DQS#[0..7] <12>
DDR_B_DQS[0..7] <12>
DDR_B_MA[0..15] <12>
IVY-BRIDGE_BGA1023
IVY-BRIDGE_BGA1023
C867@
C867@
R20
R20
1K_0402_5%
1K_0402_5%
+1.5V
12
1 2
R21 1K_0402_5%R21 1K_0402_5%
S0
DRAMRST_CNTRL_PCH hgih ,MOS ON
SM_DRAMRST# HIGH,DDR3 DRAMRST# HIGH
Dimm not reset
S3
DRAMRST_CNTRL_PCH Low ,MOS OFF
SM_DRAMRST# lo,DDR3 DRAMRST# HIGH
Dimm not reset
S4,5
DRAMRST_CNTRL_PCH Low ,MOS OFF
SM_DRAMRST# lo,DDR3 DRAMRST# low
Dimm reset
B
DIMM_DRAMRST# <11,12>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2011/11/22 2012/11/22
2011/11/22 2012/11/22
2011/11/22 2012/11/22
Follow CRB1.0
R19
R19
0_0402_5%
0_0402_5%
1 2
@
1 2
@
D
S
D
S
123
G
G
RST_GATE_R
12
C68
C68
0.047U_0402_16V7K
0.047U_0402_16V7K
DIMM_DRAMRST#_R
Q3
Q3
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
CPU通通DIMM做reset
SM_DRAMRST#<5>
4 4
RST_GATE<14> RST_GATE_R <11,12>
SM_DRAMRST#
4.99K_0402_1%
4.99K_0402_1%
R23
R23
0_0402_5%
0_0402_5%
@
@
1 2
A
R22
R22
IVY-BRIDGE_BGA1023
IVY-BRIDGE_BGA1023
C867@
C867@
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(3/7) DDRIII
PROCESSOR(3/7) DDRIII
PROCESSOR(3/7) DDRIII
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
Friday, August 10, 2012
Friday, August 10, 2012
Friday, August 10, 2012
E
6 49
6 49
6 49
0.2
0.2
0.2
http://sualaptop365.edu.vn
A
B
C
D
E
CFG Straps for Processor
CFG6
CFG5
1K_0402_1%
1K_0402_1%
CFG2
*
*
R31
R31
@
@
12
R25
R25
1K_0402_1%
1K_0402_1%
@
@
1: Normal Operation; Lane # definition matches
socket pin map definition
0:Lane Reversed
CFG4
12
R28@
R28@
1K_0402_1%
1K_0402_1%
UMA,Optimus eDP
DISO eDP
1:Disable
0:Enable
12
12
R32
R32
1K_0402_1%
1K_0402_1%
@
@
11: (Default) 1x16 PCI Express
10: 2x8 PCI Express
*
01: Reserved
00: 1x8,2x4 PCI Express
CFG7
12
R33
R33
@ 1K_0402_1%
@ 1K_0402_1%
關關
啟啟
UCPU1E
UCPU1E
T7 @PADT7 @PAD
1 1
T37 @PADT37 @PAD
T38 @PADT38 @PAD
T39 @PADT39 @PAD
T40 @PADT40 @PAD
2 2
CFG0
CFG2
CFG4
CFG5
CFG6
CFG7
VCC_VAL_SENSE
VSS_VAL_SENSE
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
T8 @PADT8 @PAD
B50
CFG[0]
C51
CFG[1]
B54
CFG[2]
D53
CFG[3]
A51
CFG[4]
C53
CFG[5]
C55
CFG[6]
H49
CFG[7]
A55
CFG[8]
H51
CFG[9]
K49
CFG[10]
K53
CFG[11]
F53
CFG[12]
G53
CFG[13]
L51
CFG[14]
F51
CFG[15]
D52
CFG[16]
L53
CFG[17]
H43
VCC_VAL_SENSE
K43
VSS_VAL_SENSE
H45
VAXG_VAL_SENSE
K45
VSSAXG_VAL_SENSE
F48
VCC_DIE_SENSE
H48
RSVD6
K48
RSVD7
BA19
RSVD8
AV19
RSVD9
AT21
RSVD10
BB21
RSVD11
BB19
RSVD12
AY21
RSVD13
BA22
RSVD14
AY22
RSVD15
AU19
RSVD16
AU21
RSVD17
BD21
RSVD18
BD22
RSVD19
BD25
RSVD20
BD26
RSVD21
BG22
RSVD22
BE22
RSVD23
BG26
RSVD24
BE26
RSVD25
BF23
RSVD26
BE24
RSVD27
RESERVED
RESERVED
BCLK_ITP
BCLK_ITP#
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
DC_TEST_A4
DC_TEST_C4
DC_TEST_D3
DC_TEST_D1
DC_TEST_A58
DC_TEST_A59
DC_TEST_C59
DC_TEST_A61
DC_TEST_C61
DC_TEST_D61
DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58
DC_TEST_BG4
DC_TEST_BG3
DC_TEST_BE3
DC_TEST_BG1
DC_TEST_BE1
DC_TEST_BD1
N59
N58
N42
L42
L45
L47
M13
M14
U14
W14
P13
AT49
K24
AH2
AG13
AM14
AM15
N50
A4
C4
D3
D1
A58
A59
C59
A61
C61
D61
BD61
BE61
BE59
BG61
BG59
BG58
BG4
BG3
BE3
BG1
BE1
BD1
DC_TEST_C4_D3
DC_TEST_A59_C59
DC_TEST_A61_C61
DC_TEST_BE59_BE6 1
DC_TEST_BG59_BG61
DC_TEST_BE3_BG3
DC_TEST_BE1_BG1
These pins are for solder
joint
reliability and non-critical to
function. For BGA only.
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
eDP enable
CFG4
PCIE Port Bifurcation Straps
CFG[6:5]
IVY-BRIDGE_BGA1023
IVY-BRIDGE_BGA1023
C867@
3 3
C867@
PEG DEFER TRAINING
1: (Default) PEG Train immediately following
CFG7
xxRESETB de assertion
Tacoma_Fall2 1.0 P.12
0: PEG Wait for BIOS for training
4 4
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
http://sualaptop365.edu.vn
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Issued Date
Issued Date
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
2012/11/ 222011/11/ 22
2012/11/ 222011/11/ 22
2012/11/ 222011/11/ 22
D
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(4/7) RSVD,CFG
PROCESSOR(4/7) RSVD,CFG
PROCESSOR(4/7) RSVD,CFG
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
Friday, August 10, 20 12
Friday, August 10, 20 12
Friday, August 10, 20 12
E
0.2Custom
0.2Custom
0.2Custom
497
497
497
A
B
C
D
E
1 1
+CPU_CORE
INTEL Recommend VCC
4*470UF,12*22uF(0805) and 35*2.2uF(0402)
PD0.8
CAP at P.51
2 2
3 3
4 4
ULV type
DC 33A
A26
A29
A31
A34
A35
A38
A39
A42
C26
C27
C32
C34
C37
C39
C42
D27
D32
D34
D37
D39
D42
E26
E28
E32
E34
E37
E38
F25
F26
F28
F32
F34
F37
F38
F42
G42
H25
H26
H28
H29
H32
H34
H35
H37
H38
H40
J25
J26
J28
J29
J32
J34
J35
J37
J38
J40
J42
K26
K27
K29
K32
K34
K35
K37
K39
K42
L25
L28
L33
L36
L40
N26
N30
N34
N38
UCPU1F
UCPU1F
VCC[1]
VCC[2]
VCC[3]
VCC[4]
VCC[5]
VCC[6]
VCC[7]
VCC[8]
VCC[9]
VCC[10]
VCC[11]
VCC[12]
VCC[13]
VCC[14]
VCC[15]
VCC[16]
VCC[17]
VCC[18]
VCC[19]
VCC[20]
VCC[21]
VCC[22]
VCC[23]
VCC[24]
VCC[25]
VCC[26]
VCC[27]
VCC[28]
VCC[29]
VCC[30]
VCC[31]
VCC[32]
VCC[33]
VCC[34]
VCC[35]
VCC[36]
VCC[37]
VCC[38]
VCC[39]
VCC[40]
VCC[41]
VCC[42]
VCC[43]
VCC[44]
VCC[45]
VCC[46]
VCC[47]
VCC[48]
VCC[49]
VCC[50]
VCC[51]
VCC[52]
VCC[53]
VCC[54]
VCC[55]
VCC[56]
VCC[57]
VCC[58]
VCC[59]
VCC[60]
VCC[61]
VCC[62]
VCC[63]
VCC[64]
VCC[66]
VCC[67]
VCC[68]
VCC[69]
VCC[70]
VCC[71]
VCC[72]
VCC[73]
VCC[74]
VCC[75]
VCC[76]
IVY-BRIDGE_BGA1023
IVY-BRIDGE_BGA1023
C867@
C867@
POWER
POWER
CORE SUPPLY
CORE SUPPLY
VCCIO[1]
VCCIO[3]
VCCIO[4]
VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]
VCCIO[9]
VCCIO[10]
VCCIO[11]
VCCIO[12]
VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[24]
VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]
VCCIO[30]
VCCIO[31]
VCCIO[32]
PEG IO AND DDR IO
PEG IO AND DDR IO
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]
VCCIO50
VCCIO51
VCCIO_SE L
VCCPQE[1 ]
VCCPQE[2 ]
RAILS
RAILS
VIDALERT#
VIDSCLK
VIDSOUT
VCC_SENS E
VSS_SEN SE
VCCIO_SE NSE
VSS_SEN SE_VCCIO
SENSE LINES SVID QUIET
SENSE LINES SVID QUIET
8.5A
AF46
AG48
AG50
AG51
AJ17
AJ21
AJ25
AJ43
AJ47
AK50
AK51
AL14
AL15
AL16
AL20
AL22
AL26
AL45
AL48
AM16
AM17
AM21
AM43
AM47
AN20
AN42
AN45
AN48
AA14
AA15
AB17
AB20
AC13
AD16
AD18
AD21
AE14
AE15
AF16
AF18
AF20
AG15
AG16
AG17
AG20
AG21
AJ14
AJ15
+1.05VS_VTT
W16
W17
VCCIO_SEL
BC22
+1.05VS_VTT
AM25
AN22
C69
C69
1U_0402_6.3V6K
1U_0402_6.3V6K
H_CPU_SVIDALRT#
A44
H_CPU_SVIDCLK
B43
H_CPU_SVIDDAT
C44
VCCSENSE_R
F43
VSSSENSE_R
G43
R44 10_0402_5%R44 10_0402_5%
AN16
VSSIO_SENSE
AN17
+1.05VS_VTT
For DDR
INTEL Recommend VCCIO
2*330UF,10*10uF(0603) and 26*1uF(0402)
PD0.8
High-Frequency Decoupling
27x1µF
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
CC238
CC238
CC240
CC240
12
12
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
CC252
CC252
CC251
CC251
12
12
12
VCCIO_SEL after Ivy bridge ES2 Voltage support
12
BC22
R36
R36
130_0402_5%
130_0402_5%
R38 43_0402_1%R38 43_0402_1%
1 2
R39 0_0402_ 5%@R39 0_0402_ 5%@
1 2
R40 0_0402_ 5%@R40 0_0402_ 5%@
1 2
+CPU_CORE
12
12
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
CC236
CC236
CC237
CC237
CC231
CC231
12
12
12
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
CC250
CC250
CC249
CC249
CC248
CC248
12
12
12
1/NC : (Default) +1.05VS_VTT
*
0: +1.0VS_VTT
+1.05VS_VTT+1.05VS_VTT
R41
R41
100_0402_1%
100_0402_1%
VCCSENSE <44>
VSSSENS E <44>
R45
R45
100_0402_1%
100_0402_1%
Should change to connect form
power cirucit & layout differential
with VCCIO_SENSE.
For PEG
1 2
R42 0_0402_ 5%@R42 0_0402_ 5%@
R43 0_0402_ 5%@R43 0_0402_ 5%@
1 2
+1.05VS_VTT
10K_0402_5%
10K_0402_5%
VCCIO_SEL
10K_0402_5%
10K_0402_5%
Place the PU
resistors
close to VR
1 2
1 2
VCCIO_SENSE <40>
12
R46
R46
10_0402_5%
10_0402_5%
Check list 1.5
CC254
CC254
12
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
R34
R34
@
@
R35
R35
@
@
+1.05VS_VTT
CC239
CC239
CC253
CC253
+3VS
12
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
CC230
CC230
12
CC246
CC246
12
12
R37
R37
75_0402_5%
75_0402_5%
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
CC235
CC235
12
1U_0402_6.3V6K
1U_0402_6.3V6K
CC247
CC247
12
Place the PU
resistors
close to CPU
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
CC228
CC228
CC229
CC229
12
12
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
CC243
CC243
CC245
CC245
12
12
VR_SVID_ ALRT# <44>
VR_SVID_ CLK <44>
VR_SVID_ DAT <44>
+1.05VS_VTT
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
CC225
CC225
CC227
CC227
CC226
CC226
12
12
12
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
CC242
CC242
CC244
CC244
CC241
CC241
12
12
12
12
CC224
CC224
10U_0603_6.3V6M
10U_0603_6.3V6M
12
+
+
Low-Frequency
CC203
CC203
Decoupling
330U_D2_2V_Y
330U_D2_2V_Y
1x330 µF 9m
12
12
CC217
CC217
CC218
CC218
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
Mid-Frequency Decoupling
10x10µF
12
CC216
CC216
10U_0603_6.3V6M
10U_0603_6.3V6M
12
12
CC214
CC214
CC215
CC215
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
12
12
CC213
CC213
CC212
CC212
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
12
12
CC210
CC210
CC211
CC211
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
A
B
http://sualaptop365.edu.vn
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
2012/11/222011/11/22
2012/11/222011/11/22
2012/11/222011/11/22
Title
PROCESSOR(5/7) PWR,BYPASS
PROCESSOR(5/7) PWR,BYPASS
PROCESSOR(5/7) PWR,BYPASS
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
Date: Sheet of
Friday, August 10, 2012
Date: Sheet of
Friday, August 10, 2012
Date: Sheet of
Friday, August 10, 2012
E
498
498
498
0.2Custom
0.2Custom
0.2Custom
A
B
C
D
E
1 1
POWER
UCPU1G
UCPU1G
+VGFX_CORE
INTEL Recommend VAXG
2*470uF,6*22uF(0805) and 6*10uF(0603)
11*1U(0402)
PD0.8
2 2
CR CheckList Rev1.5
+VGFX_CORE
INTEL Recommend VCCPLL
1*330uF,2*1uF(0402)
3 3
PD0.8
+1.8VS
SGA00001700 S POLY C 220U
220U 2.5V M B2 ESR35 TPE
H1.9
+VCCSA
SGA20331E10 S POLY C 330U
2V Y D2 LESR9M EEFSX H1.9
4 4
INTEL Recommend VCCSA
1*330uF,5*10uF(0603)
VCC_AXG_SENSE<44>
VSS_AXG_SENSE<44>
Place BOT OUT Conn
12
+
+
C91
C91
@
@
220U_B2_2.5VM_R35
220U_B2_2.5VM_R35
12
+
+
C94
C94
330U_D2_2V_Y
330U_D2_2V_Y
Place TOP IN BGA
+VCCSA
C96
C96
C97
C95
C95
1U_0402_6.3V6K
1U_0402_6.3V6K
12
C97
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
Place BOT OUT BGA
C100
C100
10U_0603_6.3V6M
10U_0603_6.3V6M
12
C102
C102
C101
C101
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
12
12
12
R51
R51
100_0402_5%
100_0402_5%
12
R52
R52
100_0402_5%
100_0402_5%
C92
1U_0402_6.3V6K
C92
1U_0402_6.3V6K
12
C98
C98
1U_0402_6.3V6K
1U_0402_6.3V6K
12
C103
C103
10U_0603_6.3V6M
10U_0603_6.3V6M
12
DC 16A
C93
1U_0402_6.3V6K
C93
1U_0402_6.3V6K
12
C99
C99
1U_0402_6.3V6K
1U_0402_6.3V6K
12
C104
C104
10U_0603_6.3V6M
10U_0603_6.3V6M
12
1.2A
6A
AA46
VAXG[1]
AB47
VAXG[2]
AB50
VAXG[3]
AB51
VAXG[4]
AB52
VAXG[5]
AB53
VAXG[6]
AB55
VAXG[7]
AB56
VAXG[8]
AB58
VAXG[9]
AB59
VAXG[10]
AC61
VAXG[11]
AD47
VAXG[12]
AD48
VAXG[13]
AD50
VAXG[14]
AD51
VAXG[15]
AD52
VAXG[16]
AD53
VAXG[17]
AD55
VAXG[18]
AD56
VAXG[19]
AD58
VAXG[20]
AD59
VAXG[21]
AE46
VAXG[22]
N45
VAXG[23]
P47
VAXG[24]
P48
VAXG[25]
P50
VAXG[26]
P51
VAXG[27]
P52
VAXG[28]
P53
VAXG[29]
P55
VAXG[30]
P56
VAXG[31]
P61
VAXG[32]
T48
VAXG[33]
T58
VAXG[34]
T59
VAXG[35]
T61
VAXG[36]
U46
VAXG[37]
V47
VAXG[38]
V48
VAXG[39]
V50
VAXG[40]
V51
VAXG[41]
V52
VAXG[42]
V53
VAXG[43]
V55
VAXG[44]
V56
VAXG[45]
V58
VAXG[46]
V59
VAXG[47]
W50
VAXG[48]
W51
VAXG[49]
W52
VAXG[50]
W53
VAXG[51]
W55
VAXG[52]
W56
VAXG[53]
W61
VAXG[54]
Y48
VAXG[55]
Y61
VAXG[56]
F45
VAXG_SENSE
G45
VSSAXG_SENSE
BB3
VCCPLL[1]
BC1
VCCPLL[2]
BC4
VCCPLL[3]
L17
VCCSA[1]
L21
VCCSA[2]
N16
VCCSA[3]
N20
VCCSA[4]
N22
VCCSA[5]
P17
VCCSA[6]
P20
VCCSA[7]
R16
VCCSA[8]
R18
VCCSA[9]
R21
VCCSA[10]
U15
VCCSA[11]
V16
VCCSA[12]
V17
VCCSA[13]
V18
VCCSA[14]
V21
VCCSA[15]
W20
VCCSA[16]
IVY-BRIDGE_BGA1023
IVY-BRIDGE_BGA1023
C867@
C867@
POWER
VREF
VREF
DDR3 - 1.5V RA ILS
DDR3 - 1.5V RA ILS
GRAPHICS
GRAPHICS
SENSE
LINES
SENSE
LINES
1.8V RAIL
1.8V RAIL
SA RAIL
SA RAIL
VCCSA VID
VCCSA VID
SM_VREF
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
VDDQ[10]
VDDQ[11]
VDDQ[12]
VDDQ[13]
VDDQ[14]
VDDQ[15]
VDDQ[16]
VDDQ[17]
VDDQ[18]
VDDQ[19]
VDDQ[20]
VDDQ[21]
VDDQ[22]
VDDQ[23]
VDDQ[24]
VDDQ[25]
VDDQ[26]
VCCDQ[1]
VCCDQ[2]
QUIET RAILS
QUIET RAILS
VDDQ_SENSE
VSS_SENSE_VDDQ
SENSE LINES
SENSE LINES
VCCSA_SENSE
VCCSA_VID[0]
VCCSA_VID[1]
lines
lines
VDDQ[1]
VDDQ[2]
VDDQ[3]
VDDQ[4]
VDDQ[5]
VDDQ[6]
VDDQ[7]
VDDQ[8]
VDDQ[9]
+V_SM_VREF
AY43
SA_DIMM_VREFDQ
BE7
SB_DIMM_VREFDQ
BG7
5A
AJ28
AJ33
AJ36
AJ40
AL30
AL34
AL38
AL42
AM33
AM36
AM40
AN30
AN34
AN38
AR26
AR28
AR30
AR32
AR34
AR36
AR40
AV41
AW26
BA40
BB28
BG33
+1.5V_CPU_VDDQ
AM28
AN26
BC43
BA43
U10
CPU EDS1.3 P.93
VCCSA_VID0
Must PD
D48
D49
1K_0402_1%
1K_0402_1%
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
C90
C90
1U_0402_6.3V6K
1U_0402_6.3V6K
VCCSA_VID0
VCCSA_VID1
SA_DIMM_VREFDQ <11>
R50
R50
1K_0402_1%
1K_0402_1%
@
@
SB_DIMM_VREFDQ <12>
12
12
R49
R49
@
@
Place TOP IN BGA
C72
C72
C71
C71
1U_0402_6.3V6K
1U_0402_6.3V6K
12
C74
C74
C75
C73
C73
1U_0402_6.3V6K
1U_0402_6.3V6K
12
C75
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
Place BOT OUT BGA
C82
C82
C83
C83
C84
10U_0603_6.3V6M
10U_0603_6.3V6M
12
C84
10U_0603_6.3V6M
10U_0603_6.3V6M
12
VCCSA_SENSE <39>
VCCSA_VID0 <39>
VCCSA_VID1 <39>
@
@
12
R53
R53
0_0402_5%
0_0402_5%
10U_0603_6.3V6M
10U_0603_6.3V6M
12
+V_SM_VREF should
have 20 mil trace
width
0.1U_0402_16V4Z
0.1U_0402_16V4Z
INTEL Recommend VDDQ
1*330uF,8*10uF(0603)
,10*1uF(0402)
PD0.8
C76
C76
C77
C77
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
C86
C86
C85
C85
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
12
12
C79
C79
C78
C78
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
C87
C87
C88
C88
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
12
12
VID0
0
0
1 1
VID1
1U_0402_6.3V6K
1U_0402_6.3V6K
12
10U_0603_6.3V6M
10U_0603_6.3V6M
12
0
1
0 X1
+1.5V_CPU_VDDQ
12
12
12
C70
C70
+1.5V_CPU_VDDQ
C80
C80
12
+
+
C81
C81
330U_D2_2V_Y
330U_D2_2V_Y
C89
C89
SGA20331E10 S POLY C 330U
2V Y D2 LESR9M EEFSX H1.9
VCCSA
HR CR
Vout
0.9V
0.85V
0.775V
0.75V
R47
R47
1K_0402_5%
1K_0402_5%
R48
R48
1K_0402_5%
1K_0402_5%
V V
V
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
Check list1.5 P18
M1 default M3 no
stuff
J1
J1
1 2
JUMP_43X118
JUMP_43X118
@
@
V
V
VX
+1.5VS
,5*1uF(0402)
PD0.8
Security Classification
Security Classification
http://sualaptop365.edu.vn
A
B
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
2012/11/222011/11/22
2012/11/222011/11/22
2012/11/222011/11/22
Title
PROCESSOR(6/7) PWR
PROCESSOR(6/7) PWR
PROCESSOR(6/7) PWR
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
Date: Sheet of
Friday, August 10, 2012
Date: Sheet of
Friday, August 10, 2012
Date: Sheet of
Friday, August 10, 2012
E
499
499
499
0.2C
0.2C
0.2C
A
UCPU1H
UCPU1H
A13
VSS[1]
A17
VSS[2]
A21
VSS[3]
A25
VSS[4]
A28
VSS[5]
A33
VSS[6]
1 1
2 2
3 3
4 4
A37
VSS[7]
A40
VSS[8]
A45
VSS[9]
A49
VSS[10]
A53
VSS[11]
A9
VSS[12]
AA1
VSS[13]
AA13
VSS[14]
AA50
VSS[15]
AA51
VSS[16]
AA52
VSS[17]
AA53
VSS[18]
AA55
VSS[19]
AA56
VSS[20]
AA8
VSS[21]
AB16
VSS[22]
AB18
VSS[23]
AB21
VSS[24]
AB48
VSS[25]
AB61
VSS[26]
AC10
VSS[27]
AC14
VSS[28]
AC46
VSS[29]
AC6
VSS[30]
AD17
VSS[31]
AD20
VSS[32]
AD4
VSS[33]
AD61
VSS[34]
AE13
VSS[35]
AE8
VSS[36]
AF1
VSS[37]
AF17
VSS[38]
AF21
VSS[39]
AF47
VSS[40]
AF48
VSS[41]
AF50
VSS[42]
AF51
VSS[43]
AF52
VSS[44]
AF53
VSS[45]
AF55
VSS[46]
AF56
VSS[47]
AF58
VSS[48]
AF59
VSS[49]
AG10
VSS[50]
AG14
VSS[51]
AG18
VSS[52]
AG47
VSS[53]
AG52
VSS[54]
AG61
VSS[55]
AG7
VSS[56]
AH4
VSS[57]
AH58
VSS[58]
AJ13
VSS[59]
AJ16
VSS[60]
AJ20
VSS[61]
AJ22
VSS[62]
AJ26
VSS[63]
AJ30
VSS[64]
AJ34
VSS[65]
AJ38
VSS[66]
AJ42
VSS[67]
AJ45
VSS[68]
AJ48
VSS[69]
AJ7
VSS[70]
AK1
VSS[71]
AK52
VSS[72]
AL10
VSS[73]
AL13
VSS[74]
AL17
VSS[75]
AL21
VSS[76]
AL25
VSS[77]
AL28
VSS[78]
AL33
VSS[79]
AL36
VSS[80]
AL40
VSS[81]
AL43
VSS[82]
AL47
VSS[83]
AL61
VSS[84]
AM13
VSS[85]
AM20
VSS[86]
AM22
VSS[87]
AM26
VSS[88]
AM30
VSS[89]
AM34
VSS[90]
IVY-BRIDGE_BGA1023
IVY-BRIDGE_BGA1023
C867@
C867@
VSS
VSS
A
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
AM38
AM4
AM42
AM45
AM48
AM58
AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP10
AP51
AP55
AP7
AR13
AR17
AR21
AR41
AR48
AR61
AR7
AT14
AT19
AT36
AT4
AT45
AT52
AT58
AU1
AU11
AU28
AU32
AU51
AU7
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW13
AW43
AW61
AW7
AY14
AY19
AY30
AY36
AY4
AY41
AY45
AY49
AY55
AY58
AY9
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC13
BC5
BC57
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52
BD56
BD8
BE5
BG13
B
UCPU1I
UCPU1I
BG17
VSS[181]
BG21
VSS[182]
BG24
VSS[183]
BG28
VSS[184]
BG37
VSS[185]
BG41
VSS[186]
BG45
VSS[187]
BG49
VSS[188]
BG53
VSS[189]
BG9
VSS[190]
C29
VSS[191]
C35
VSS[192]
C40
VSS[193]
D10
VSS[194]
D14
VSS[195]
D18
VSS[196]
D22
VSS[197]
D26
VSS[198]
D29
VSS[199]
D35
VSS[200]
D4
VSS[201]
D40
VSS[202]
D43
VSS[203]
D46
VSS[204]
D50
VSS[205]
D54
VSS[206]
D58
VSS[207]
D6
VSS[208]
E25
VSS[209]
E29
VSS[210]
E3
VSS[211]
E35
VSS[212]
E40
VSS[213]
F13
VSS[214]
F15
VSS[215]
F19
VSS[216]
F29
VSS[217]
F35
VSS[218]
F40
VSS[219]
F55
VSS[220]
G51
VSS[221]
G6
VSS[222]
G61
VSS[223]
H10
VSS[224]
H14
VSS[225]
H17
VSS[226]
H21
VSS[227]
H4
VSS[228]
H53
VSS[229]
H58
VSS[230]
J1
VSS[231]
J49
VSS[232]
J55
VSS[233]
K11
VSS[234]
K21
VSS[235]
K51
VSS[236]
K8
VSS[237]
L16
VSS[238]
L20
VSS[239]
L22
VSS[240]
L26
VSS[241]
L30
VSS[242]
L34
VSS[243]
L38
VSS[244]
L43
VSS[245]
L48
VSS[246]
L61
VSS[247]
M11
VSS[248]
M15
VSS[249]
IVY-BRIDGE_BGA1023
IVY-BRIDGE_BGA1023
C867@
C867@
B
VSS
VSS
NCTF
NCTF
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
M4
VSS[250]
M58
VSS[251]
M6
VSS[252]
N1
VSS[253]
N17
VSS[254]
N21
VSS[255]
N25
VSS[256]
N28
VSS[257]
N33
VSS[258]
N36
VSS[259]
N40
VSS[260]
N43
VSS[261]
N47
VSS[262]
N48
VSS[263]
N51
VSS[264]
N52
VSS[265]
N56
VSS[266]
N61
VSS[267]
P14
VSS[268]
P16
VSS[269]
P18
VSS[270]
P21
VSS[271]
P58
VSS[272]
P59
VSS[273]
P9
VSS[274]
R17
VSS[275]
R20
VSS[276]
R4
VSS[277]
R46
VSS[278]
T1
VSS[279]
T47
VSS[280]
T50
VSS[281]
T51
VSS[282]
T52
VSS[283]
T53
VSS[284]
T55
VSS[285]
T56
VSS[286]
U13
VSS[287]
U8
VSS[288]
V20
VSS[289]
V61
VSS[290]
W13
VSS[291]
W15
VSS[292]
W18
VSS[293]
W21
VSS[294]
W46
VSS[295]
W8
VSS[296]
Y4
VSS[297]
Y47
VSS[298]
Y58
VSS[299]
Y59
VSS[300]
G48
VSS[301]
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
A5
A57
BC61
BD3
BD59
BE4
BE58
BG5
BG57
C3
C58
D59
E1
E61
Compal Secret Data
Compal Secret Data
2011/11/22 2012/11/22
2011/11/22 2012/11/22
2011/11/22 2012/11/22
C
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(7/7) VSS
PROCESSOR(7/7) VSS
PROCESSOR(7/7) VSS
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
Friday, August 1 0, 2012
Friday, August 1 0, 2012
Friday, August 1 0, 2012
E
E
10 49
10 49
10 49
0.2
0.2
0.2
http://sualaptop365.edu.vn
5
4
3
2
1
Channel A
All VREF traces should
have 15 mil trace width
+V_DDR_REFA
1
C2517
D D
C2517
0.1U_0402_16V4Z
0.1U_0402_16V4Z
M3 support(unpop)
SA_DIMM_VREFDQ<9>
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
RST_GATE_R<6,12>
C C
B B
+3VS
C2537
C2537
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
1
C2518
C2518
1000P_0402_50V7K
1000P_0402_50V7K
2
2
+V_DDR_REFA
R55
R55
0_0402_5%
0_0402_5%
1 2
@
@
D
S
D
S
123
Q4@
Q4@
G
G
DDR_A_BS2<6>
SA_CLK_DDR0<6>
SA_CLK_DDR#0<6>
DDR_A_BS0<6>
DDR_A_WE#<6>
DDR_A_CAS#<6>
DDRA_CS1_DIMMA#<6>
1
1
C2538
C2538
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
+0.75VS
DDR_A_D0
DDR_A_D1
DDR_A_DM0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_MA13
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
1 2
R2523 10K_0402_5%R2523 10K_0402_5%
12
R2524
R2524
10K_0402_5%
10K_0402_5%
+1.5V
JDIMM1
JDIMM1
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
VSS49DQS#0
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
VSS925VSS10
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
DQS247VSS17
VSS1849DQ22
51
DQ18
DQ1953VSS19
VSS2055DQ28
57
DQ24
DQ2559VSS21
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
A12/BC#83A11
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
VDD999VDD10
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
TYCO_2-2013289-1
TYCO_2-2013289-1
CONN@
CONN@
VSS3
DQS0
VSS6
VSS8
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ23
DQ29
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
VTT2
+1.5V
2
DDR_A_D4
4
DQ4
DQ5
DQ6
DQ7
DM1
DM2
A15
A14
A7
A6
A4
A2
A0
CK1
BA1
S0#
NC2
DM4
DM6
SDA
SCL
G2
DDR_A_D5
6
8
DDR_A_DQS#0
10
DDR_A_DQS0
12
14
DDR_A_D6
16
DDR_A_D7
18
20
DDR_A_D12
22
DDR_A_D13
24
26
DDR_A_DM1
28
30
32
DDR_A_D14
34
DDR_A_D15
36
38
DDR_A_D20
40
DDR_A_D21
42
44
DDR_A_DM2
46
48
DDR_A_D22
50
DDR_A_D23
52
54
DDR_A_D28
56
DDR_A_D29
58
60
DDR_A_DQS#3
62
DDR_A_DQS3
64
66
DDR_A_D30
68
DDR_A_D31
70
72
74
76
DDR_A_MA15
78
DDR_A_MA14
80
82
DDR_A_MA11
84
DDR_A_MA7
86
88
DDR_A_MA6
90
DDR_A_MA4
92
94
DDR_A_MA2
96
DDR_A_MA0
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
DDR_A_D36
130
DDR_A_D37
132
134
DDR_A_DM4
136
138
DDR_A_D38
140
DDR_A_D39
142
144
DDR_A_D44
146
DDR_A_D45
148
150
DDR_A_DQS#5
152
DDR_A_DQS5
154
156
DDR_A_D46
158
DDR_A_D47
160
162
DDR_A_D52
164
DDR_A_D53
166
168
DDR_A_DM6
170
172
DDR_A_D54
174
DDR_A_D55
176
178
DDR_A_D60
180
DDR_A_D61
182
184
DDR_A_DQS#7
186
DDR_A_DQS7
188
190
DDR_A_D62
192
DDR_A_D63
194
196
198
200
202
204
206
+0.75VS
DIMM_DRAMRST# <6,12>
DDRA_CKE1_DIMMA <6>DDRA_CKE0_DIMMA<6>
SA_CLK_DDR1 <6>
SA_CLK_DDR#1 <6>
DDR_A_BS1 <6>
DDR_A_RAS# <6>
DDRA_CS0_DIMMA# <6>
SA_ODT0 <6>
SA_ODT1 <6>
C2531
C2531
1000P_0402_50V7K
1000P_0402_50V7K
D_CK_SDATA <12,14>
D_CK_SCLK <12,14>
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
All VREF traces should
have 15 mil trace width
1
1
C2532
C2532
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
+VREF_CA
DDR_A_D[0..63]
DDR_A_MA[0..15]
DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]
+1.5V
2
C2519
C2519
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C2520
C2520
1
DDR_A_D[0..63] <6>
DDR_A_MA[0..15] <6>
DDR_A_DQS#[0..7] <6>
DDR_A_DQS[0..7] <6>
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C2521
C2521
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Place near JDIMM1
2
C2522
C2522
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C2523
C2523
C2524
C2524
1
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
CRB 0.1u X1 4. 7u X1
+0.75VS
2
C2534
C2534
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
1
C2535
C2535
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C2533
C2533
@
@
+1.5V
R2519
R2519
1K_0402_1%
2
C2526
C2526
1
1K_0402_1%
1 2
R2521
R2521
1K_0402_1%
1K_0402_1%
1 2
2
C2527
C2527
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
15mil 15mil
+V_DDR_REFA
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C2525
C2525
1
CRB 100U X2
+1.5V
1
2
1
C2536
C2536
+
+
390U_2.5V_M_R10
390U_2.5V_M_R10
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C2528
C2528
1
+1.5V
+VREF_CA
2
C2529
C2529
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C2588
@+C2588
@
+
390U_2.5V_M_R10
390U_2.5V_M_R10
2
0511 update
+1.5V
R2520
R2520
1K_0402_1%
1K_0402_1%
1 2
R2522
R2522
1K_0402_1%
1K_0402_1%
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C2530
C2530
1
A A
Security Classification
Security Classification
http://sualaptop365.edu.vn
5
4
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
3
2012/04/27 2013/04/27
2012/04/27 2013/04/27
2012/04/27 2013/04/27
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
DDR3 SODIMM-I Socket
DDR3 SODIMM-I Socket
DDR3 SODIMM-I Socket
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
1
11 49Friday, August 10, 2012
11 49Friday, August 10, 2012
11 49Friday, August 10, 2012
0.2
0.2
0.2
5
4
3
2
1
All VREF traces should
have 15 mil trace width
+V_DDR_REFB
1
C2539
D D
C2539
M3 support(unpop)
SB_DIMM_VREFDQ<9>
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
RST_GATE_R<6,11>
C C
B B
A A
+3VS
C2558
C2558
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
DDRB_CKE0_DIMMB<6>
DDRB_CS1_DIMMB#<6>
R2526 10K_0402_5%R2526 10K_0402_5%
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
SB_CLK_DDR0<6>
SB_CLK_DDR#0<6>
DDR_B_BS0<6>
DDR_B_WE#<6>
DDR_B_CAS#<6>
1
2
C2540
C2540
1000P_0402_50V7K
1000P_0402_50V7K
+V_DDR_REFB
R62
R62
0_0402_5%
0_0402_5%
1 2
@
@
D
S
D
S
123
Q5@
Q5@
G
G
DDR_B_BS2<6>
1 2
1
C2559
C2559
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
5
http://sualaptop365.edu.vn
DDR_B_D0
DDR_B_D1
1
DDR_B_DM0
2
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_MA13
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
1 2
R2527
R2527
10K_0402_5%
10K_0402_5%
Channel B
+1.5V
JDIMM2
JDIMM2
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
31
VSS11
33
DQ10
35
DQ11
37
VSS13
39
DQ16
41
DQ17
43
VSS15
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
65
VSS23
67
DQ26
69
DQ27
71
VSS25
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
TYCO_2-2013290-1
TYCO_2-2013290-1
CONN@
CONN@
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
VSS24
DQ30
DQ31
VSS26
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
+1.5V
2
DDR_B_D4
4
DDR_B_D5
6
8
DDR_B_DQS#0
10
DDR_B_DQS0
12
14
DDR_B_D6
16
DDR_B_D7
18
20
DDR_B_D12
22
DDR_B_D13
24
26
DDR_B_DM1
28
30
32
DDR_B_D14
34
DDR_B_D15
36
38
DDR_B_D20
40
DDR_B_D21
42
44
DDR_B_DM2
46
48
DDR_B_D22
50
DDR_B_D23
52
54
DDR_B_D28
56
DDR_B_D29
58
60
DDR_B_DQS#3
62
DDR_B_DQS3
64
66
DDR_B_D30
68
DDR_B_D31
70
72
74
76
DDR_B_MA15
78
A15
A14
A11
A7
A6
A4
A2
A0
S0#
G2
4
DDR_B_MA14
80
82
DDR_B_MA11
84
DDR_B_MA7
86
88
DDR_B_MA6
90
DDR_B_MA4
92
94
DDR_B_MA2
96
DDR_B_MA0
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
DDR_B_D36
130
DDR_B_D37
132
134
DDR_B_DM4
136
138
DDR_B_D38
140
DDR_B_D39
142
144
DDR_B_D44
146
DDR_B_D45
148
150
DDR_B_DQS#5
152
DDR_B_DQS5
154
156
DDR_B_D46
158
DDR_B_D47
160
162
DDR_B_D52
164
DDR_B_D53
166
168
DDR_B_DM6
170
172
DDR_B_D54
174
DDR_B_D55
176
178
DDR_B_D60
180
DDR_B_D61
182
184
DDR_B_DQS#7
186
DDR_B_DQS7
188
190
DDR_B_D62
192
DDR_B_D63
194
196
198
200
202
204
206
+0.75VS
DIMM_DRAMRST# <6,11>
DDRB_CKE1_DIMMB <6>
SB_CLK_DDR1 <6>
SB_CLK_DDR#1 <6>
DDR_B_BS1 <6>
DDR_B_RAS# <6>
DDRB_CS0_DIMMB# <6>
SB_ODT0 <6>
SB_ODT1 <6>
D_CK_SDATA <11,14>
D_CK_SCLK <11,14>
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_D[0..63]
DDR_B_MA[0..15]
DDR_B_DQS#[0..7]
DDR_B_DQS[0..7]
+1.5V
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+VREF_CB
1
C2556
C2556
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Issued Date
Issued Date
1
C2557
C2557
2
1000P_0402_50V7K
1000P_0402_50V7K
2012/04/27 2013/04/27
2012/04/27 2013/04/27
2012/04/27 2013/04/27
3
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C2541
C2541
1
DDR_B_D[0..63] <6>
DDR_B_MA[0..15] <6>
DDR_B_DQS#[0..7] <6>
DDR_B_DQS[0..7] <6>
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C2543
C2543
C2542
C2542
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
C2544
C2544
1
2
C2545
C2545
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.5V
R2531
R2531
1K_0402_1%
15mil 15mil
+V_DDR_REFB
2
2
C2546
C2546
1
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1K_0402_1%
1 2
R2529
R2529
1K_0402_1%
1K_0402_1%
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C2548
C2548
C2547
C2547
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
+1.5V
R2532
R2532
1K_0402_1%
1K_0402_1%
2
C2549
C2549
1
+VREF_CB
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C2550
C2550
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
1 2
R2530
R2530
1K_0402_1%
1K_0402_1%
1 2
C2551
C2551
CRB 0.1u X1 4,7uX1
+0.75VS
2
2
C2554
C2554
C2555
1
C2555
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C2553
C2553
@
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
Place near JDIMM2
Compal Electronics, Inc.
DDR3 SODIMM-II Socket
DDR3 SODIMM-II Socket
DDR3 SODIMM-II Socket
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
12 49Friday, August 10, 2012
12 49Friday, August 10, 2012
12 49Friday, August 10, 2012
1
2
C2552
C2552
1
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.2
0.2
0.2
A
B
C
D
E
RTCRST close RAM door J1
12
+RTCVCC
1U_0603_10V6K
1U_0603_10V6K
1 2
R2864 20K_0402_5%R2864 20K_0402_5%
1 2
R2865 20K_0402_5%R2865 20K_0402_5%
1 1
1U_0603_10V6K
1U_0603_10V6K
+RTCVCC
R2867 1M_0402_5%R2867 1M_0402_5%
1 2
R2868 330K_0402_5%R2868 330K_0402_5%
1 2
INTVRMEN
H：Integrated VRM enable
*
L：Integrated VRM disable
(INTVRMEN should always be pull high.)
+3VS
R2871 @ 1K_0402_5%R2871 @ 1K_0402_5%
1 2
HIGH= Enable ( No Reboot)Disable TCO timer system reboot feature
LOW= Disable (Default internal PD)
*
+VCCSUS3_3
2 2
ME_FLASH<35>
ME_FLASH
ME debug mode,this signal has a weak internal PD
Low = Disabled (Default)
*
High = Enabled [Flash Descriptor Security Overide]
+VCCSUS3_3
R2878 1K_0402_5%R2878 1K_0402_5%
This signal has a weak internal pull-down
On Die PLL VR Select is supplied by
1.5V when sampled high
*
1.8V when sampled low
Needs to be pulled High
for Huron River platfrom
AZ_BITCLK_HD<27>
AZ_SYNC_HD<27>
AZ_RST_HD#<27>
3 3
AZ_SDOUT_HD<27>
R2898 10M_0402_5%R2898 10M_0402_5%
32.768KHZ_12.5PF_1TJF125DP1A000D
32.768KHZ_12.5PF_1TJF125DP1A000D
18P_0402_50V8J
18P_0402_50V8J
12
C2862
C2862
4 4
C2855
C2855
12
C2856
C2856
1K_0402_5%
1K_0402_5%
R2874 0_0402_5%
R2874 0_0402_5%
12
1 2
Y14
Y14
1 2
12
JCOMS1
JCOMS1
CONN@
CONN@
PCH_RTCRST#
PCH_SRTCRST#
12
JCOMS2
JCOMS2
CONN@
CONN@
SM_INTRUDER#
PCH_INTVRMEN
PCH_SPKR
11/30 Add (EMI request)
12
C2858
C2858
22P_0402_50V8J
22P_0402_50V8J
@
@
AZ_BITCLK_HD
PCH_SPKR<27>
AZ_SDIN0_HD<27>
@
@
@
@
R2873
R2873
12
12
HDA_SYNC_PCH
HDA_SDOUT_PCH
Prevent back drive issue.
+5VS
G
G
Q177
Q177
BSS138_NL_SOT23-3
R2879
R2879
33_0402_5%
33_0402_5%
AZ_BITCLK_HD_R
1 2
R2880
R2880
33_0402_5%
33_0402_5%
AZ_SYNC_HD_R
1 2
R2883
R2883
33_0402_5%
33_0402_5%
AZ_RST_HD#_R
1 2
R2886
R2886
33_0402_5%
33_0402_5%
HDA_SDOUT_PCH
1 2
PCH_RTCX1
PCH_RTCX2
12
C2863
C2863
18P_0402_50V8J
18P_0402_50V8J
R2899 1K_0402_5%R2899 1K_0402_5%
1 2
http://sualaptop365.edu.vn
A
BSS138_NL_SOT23-3
HDA_SYNC_PCH
123
D
S
D
S
R2881
R2881
1 2
@ 0_0402_5%
@ 0_0402_5%
12
R2884
R2884
1M_0402_5%
1M_0402_5%
PCH_SPI_CLK_1
PCH_SPI_CLK_2
PCH_SPI_MOSI_1
PCH_SPI_MISO_1
PCH_SPI_CS0#_1
SPI_WP#
PCH_SPI_CS1#_2
PCH_SPI_MISO_2
SPI_WP#
R2889 33_0402_5%R2889 33_0402_5%
12
R2888 33_0402_5%R2888 33_0402_5%
12
R2891
R2891
0_0402_5%
0_0402_5%
12
@
@
R2893
R2893
0_0402_5%
0_0402_5%
12
@
@
R2895 33_0402_5%R2895 33_0402_5%
12
R2894 33_0402_5%R2894 33_0402_5%
12
R2897 33_0402_5%R2897 33_0402_5%
12
R2896 33_0402_5%R2896 33_0402_5%
12
4M Byte
U6
U6
1
CS#
2
DO
3
WP#
4
GND
W25Q32BVSSIG_SO8
W25Q32BVSSIG_SO8
SA00003K800
SA00003K800
HOLD#
8
VCC
7
6
CLK
5
DI
1M Byte(FOR WIN8)
U7
U7
1
CS#
2
SO
3
WP#
4
GND
8M W25Q80BVSSIG SOIC 8P
8M W25Q80BVSSIG SOIC 8P
SA00003EW00
SA00003EW00
HOLD#
SCLK
8
VCC
7
6
5
SI
B
R2882
R2882
51_0402_5%
51_0402_5%
12
T210@PAD T210@PAD
T211@PAD T211@PAD
T212@PAD T212@PAD
+3VS
C1632 0.1U_0402_16V4ZC1632 0.1U_0402_16V4Z
SPI_HOLD#PCH_SPI_MISO_1
PCH_SPI_CLK_1
PCH_SPI_MOSI_1
+3VS
C1633 0.1U_0402_16V4ZC1633 0.1U_0402_16V4Z
SPI_HOLD#
PCH_SPI_CLK_2
PCH_SPI_MOSI_2
PCH_SPI_CLK
PCH_SPI_CS0#PCH_SPI_CS0#_1
PCH_SPI_CS1#PCH_SPI_CS1#_2
PCH_SPI_MOSIPCH_SPI_MOSI_2
PCH_SPI_MISOPCH_SPI_MISO_2
PCH_RTCX1
PCH_RTCX2
PCH_RTCRST#
PCH_SRTCRST#
SM_INTRUDER#
PCH_INTVRMEN
AZ_BITCLK_HD_R
HDA_SYNC_PCH
PCH_SPKR
AZ_RST_HD#_R
AZ_SDIN0_HD
HDA_SDOUT_PCH
PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
1 2
R2901 1K_0402_5%R2901 1K_0402_5%
1 2
+RTCVCC
12
1
C137
C137
1U_0402_6.3V6K
1U_0402_6.3V6K
2
A20
C20
D20
G22
K22
C17
N34
L34
T10
K34
E34
G34
C34
A34
A36
C36
N32
J3
H7
K5
H1
T3
Y14
T1
V4
U3
W=20mils
U103A
U103A
RTCX1
RTCX2
RTCRST#
SRTCRST#
INTRUDER#
INTVRMEN
HDA_BCLK
HDA_SYNC
SPKR
HDA_RST#
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
HDA_SDO
HDA_DOCK_EN# / GPIO33
HDA_DOCK_RST# / GPIO13
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
SPI_CLK
SPI_CS0#
SPI_CS1#
SPI_MOSI
SPI_MISO
COUGARPOINT_FCBGA989
COUGARPOINT_FCBGA989
HM77@
HM77@
+3VS+3VS
+3VALW
D1
D1
2
1
DAN202UT106_SC70
DAN202UT106_SC70
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
RTCIHDA
RTCIHDA
JTAG
JTAG
SPI
SPI
3
C
+RTCBATT_R
W=20mils
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
FWH4 / LFRAME#
LDRQ0#
LDRQ1# / GPIO23
SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA 6G
SATA 6G
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA LPC
SATA LPC
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATAICOMPO
SATAICOMPI
SATA3RCOMPO
SATA3COMPI
SATA3RBIAS
SATALED#
SATA0GP / GPIO21
SATA1GP / GPIO19
+RTCBATT
R106
R106
1 2
1K_0402_5%
1K_0402_5%
LPC_AD0
C38
LPC_AD1
A38
LPC_AD2
B37
LPC_AD3
C37
LPC_FRAME#
D36
E36
PCH_GPIO23
K36
SERIRQ
V5
AM3
AM1
AP7
AP5
AM10
AM8
AP11
AP10
AD7
AD5
AH5
AH4
AB8
AB10
AF3
HM70 not support
AF1
SATA for
Y7
port1/port3
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
L=500mil S=15mil
SATA_COMP
Y10
AB12
L=500mil S=15mil
SATA3_COMP
AB13
RBIAS_SATA3
AH1
PCH_SATALED#
P3
PCH_GPIO21
V14
PCH_GPIO19
P1
Reserve for EMI
2011/11/22 2012/11/22
2011/11/22 2012/11/22
2011/11/22 2012/11/22
LPC_AD0 <35>
LPC_AD1 <35>
LPC_AD2 <35>
LPC_AD3 <35>
LPC_FRAME# <35>
SERIRQ <35>
SATA_PRX_C_DTX_N0 <29>
SATA_PRX_C_DTX_P0 <29>
SATA_PTX_DRX_N0 <29>
SATA_PTX_DRX_P0 <29>
SATA_PRX_C_DTX_N1 <29>
SATA_PRX_C_DTX_P1 <29>
SATA_PTX_DRX_N1 <29>
SATA_PTX_DRX_P1 <29>
1 2
R2885 37.4_0402_1%R2885 37.4_0402_1%
1 2
R2887 49.9_0402_1%R2887 49.9_0402_1%
1 2
R2890 750_0402_1%R2890 750_0402_1%
PCH_SPI_CLK
PCH_SPI_CLK_1
PCH_SPI_CLK_2
Compal Secret Data
Compal Secret Data
Compal Secret Data
1 2
1 2
1 2
Deciphered Date
Deciphered Date
Deciphered Date
+1.05VS_VTT
+1.05VS_VTT
PCH_SATALED# <23>
No use PU 10K +3VS
GPIO19 has internal Pull up
C2859
C2859
10P_0402_50V8J
10P_0402_50V8J
1 2
R2900@33_0402_5% R2900@33_0402_5%
@
@
22P_0402_50V8J
22P_0402_50V8J
1 2
R2902@33_0402_5% R2902@33_0402_5%
@
@
22P_0402_50V8J
22P_0402_50V8J
1 2
R2903@33_0402_5% R2903@33_0402_5%
@
@
D
HDD
ODD
C2860
C2860
C2861
C2861
11/30 Add
SERIRQ
PCH_SATALED#
10K_0402_5%
10K_0402_5%
R2869 10K_0402_5%R2869 10K_0402_5%
R2870 10K_0402_5%R2870 10K_0402_5%
+3VS
12
R2875
R2875
PCH_GPIO23
12
R2876
R2876
1K_0402_5%
1K_0402_5%
@
@
PCH_GPIO19
10K_0402_5%
10K_0402_5%
PCH_GPIO21
R2892
R2892
4.7K_0402_5%
4.7K_0402_5%
12
12
R2877
R2877
R2872
R2872
+3VS
+3VS
12
@10K_0402_5%
@10K_0402_5%
1 2
12
Debug Port DG 1.2 PU 4.7K +3VS
Boot BIOS Strap
Boot BIOS
GPIO51
LPC
Reserved
-
SPI
*
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (1/9) SATA,HDA,SPI, LPC, XDP
PCH (1/9) SATA,HDA,SPI, LPC, XDP
PCH (1/9) SATA,HDA,SPI, LPC, XDP
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
Friday, August 10, 2012
Friday, August 10, 2012
Friday, August 10, 2012
GPIO19
0 0
0
1
1 1
E
1
0
+3VS
13 49
13 49
13 49
0.2
0.2
0.2
A
LAN
WLAN
TV
PCIE_PRX_C_LANTX_N6<30>
PCIE_PRX_C_LANTX_P6<30>
PCIE_PTX_C_LANRX_N6<30>
PCIE_PTX_C_LANRX_P6<30>
PCIE_PRX_TVTX_N4< 33>
PCIE_PRX_TVTX_P4<33>
PCIE_PTX_C_TVRX_N4<33>
PCIE_PTX_C_TVRX_P4<33>
PCIE_PRX_WLANTX_ N3<33>
PCIE_PRX_WLANTX_ P3<33>
PCIE_PTX_C_WLANR X_N3<33>
PCIE_PTX_C_WLANR X_P3<33>
12
12
12
12
12
12
12
12
12
CLKREQ_WLAN#
TV_CLKREQ#
PCH_GPIO45
CLKREQ_LAN#
PCH_GPIO26
PCH_GPIO44
PCH_GPIO25
PCH_GPIO46
PCH_GPIO56
CLK_LAN#<30>
CLK_LAN<30>
CLKREQ_LAN#<30>
CLK_WLAN#< 33>
CLK_WLAN<33>
CLKREQ_WLAN#<33>
CLK_TV#<33>
CLK_TV<33>
TV_CLKREQ#<33>
C2937 0.1U_0402_16V7KC2937 0.1U_0402_16V7K
1 2
C2936 0.1U_0402_16V7KC2936 0.1U_0402_16V7K
1 2
C2864 0.1U_0402_16V7KC2864 0.1U_0402_16V7K
1 2
C2865 0.1U_0402_16V7KC2865 0.1U_0402_16V7K
1 2
C2866 0.1U_0402_16V7KC2866 0.1U_0402_16V7K
1 2
C2867 0.1U_0402_16V7KC2867 0.1U_0402_16V7K
1 2
HM70 not support
PCIE port 5-8
LAN
TV
WLAN
1 1
+3VS
R2915 10K_0402_5%R2915 10K_0402_5%
R2906 10K_0402_5%R2906 10K_0402_5%
+VCCSUS3_3
R2917 10K_0402_5%R2917 10K_0402_5%
R2918 10K_0402_5%R2918 10K_0402_5%
R2919 10K_0402_5%R2919 10K_0402_5%
R2920 10K_0402_5%R2920 10K_0402_5%
R2922 10K_0402_5%R2922 10K_0402_5%
R2923 10K_0402_5%R2923 10K_0402_5%
R2924 10K_0402_5%R2924 10K_0402_5%
2 2
No use PU 10K +3VALW
No use PU 10K +3VS
No use PU 10K +3VS
No use PU 10K +3VALW
No use PU 10K +3VALW
3 3
No use PU 10K +3VALW
No use PU 10K +3VALW
No use PU 10K +3VALW
No use PU 10K +3VALW
B
PCIE_PTX_LANRX_N6
PCIE_PTX_LANRX_P6
PCIE_PTX_TVRX_N4
PCIE_PTX_TVRX_P4
PCIE_PTX_WLANRX_ N3
PCIE_PTX_WLANRX_ P3
CLKREQ_LAN#
CLKREQ_WLAN#
TV_CLKREQ#
PCH_GPIO25
PCH_GPIO26
PCH_GPIO44
PCH_GPIO56
PCH_GPIO45
PCH_GPIO46
U103B
U103B
BG34
PERN1
BJ34
PERP1
AV32
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
PETN2
AY32
PETP2
BG36
PERN3
BJ36
PERP3
AV34
PETN3
AU34
PETP3
BF36
PERN4
BE36
PERP4
AY34
PETN4
BB34
PETP4
BG37
PERN5
BH37
PERP5
AY36
PETN5
BB36
PETP5
BJ38
PERN6
BG38
PERP6
AU36
PETN6
AV36
PETP6
BG40
PERN7
BJ40
PERP7
AY40
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW38
PETN8
AY38
PETP8
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
J2
PCIECLKRQ0# / GPIO73
AB49
CLKOUT_PCIE1N
AB47
CLKOUT_PCIE1P
M1
PCIECLKRQ1# / GPIO18
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P
V10
PCIECLKRQ2# / GPIO20
Y37
CLKOUT_PCIE3N
Y36
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
L12
PCIECLKRQ4# / GPIO26
V45
CLKOUT_PCIE5N
V46
CLKOUT_PCIE5P
L14
PCIECLKRQ5# / GPIO44
AB42
CLKOUT_PEG_B_N
AB40
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ# / GPIO56
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
T13
PCIECLKRQ6# / GPIO45
V38
CLKOUT_PCIE7N
V37
CLKOUT_PCIE7P
K12
PCIECLKRQ7# / GPIO46
AK14
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
AK13
CLKOUT_BCLK0_P / CLKOUT_PCIE8P
COUGARPOINT_FCBGA989
COUGARPOINT_FCBGA989
HM77@
HM77@
SMBUSController
SMBUSController
SML1ALERT# / PCHHOT# / GPIO74
PCI-E*
PCI-E*
CLOCKS
CLOCKS
CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P
C
SMBALERT# / GPIO11
SMBCLK
SMBDATA
SML0ALERT# / GPIO60
SML0CLK
SML0DATA
SML1CLK / GPIO58
SML1DATA / GPIO75
CL_CLK1
CL_DATA1
Link
Link
CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P
FLEX CLOCKS
FLEX CLOCKS
CL_RST1#
PEG_A_CLKRQ# / GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_DMI2_N
CLKIN_DMI2_P
CLKIN_DOT_96N
CLKIN_DOT_96P
REFCLK14IN
CLKIN_PCILOOPBACK
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67
SMB_ALERT#
E12
PCH_SMBCLK
H14
PCH_SMBDATA
C9
RST_GATE
A12
C8
G12
PCH_GPIO74
C13
PCH_SML1CLK
E14
PCH_SML1DATA
M16
M7
T11
P10
PCH_GPIO47
M10
AB37
AB38
CLK_CPU_DMI#
AV22
CLK_CPU_DMI
AU22
AM12
AM13
CLK_BUF_CPU_DMI#
BF18
CLK_BUF_CPU_DMI
BE18
CLKIN_GND1#
BJ30
CLKIN_GND1
BG30
CLK_BUF_DREF_96M#
G24
CLK_BUF_DREF_96M
E24
CLK_BUF_PCIE_SATA#
AK7
CLK_BUF_PCIE_SATA
AK5
CLK_BUF_ICH_14M
K45
CLK_PCI_LPBACK
H45
XTAL25_IN
V47
XTAL25_OUT
V49
W=12mil S=15mil
XCLK_RCOMP
Y47
PCH_GPIO64
K43
PCH_GPIO65
F47
H47
K49
MEMORY
RST_GATE <6>
T9@PAD T9@ PAD
S3 reduse
T10@ PAD T10@ PAD
S3 reduse
EC
CLK_CPU_DMI# <5>
CLK_CPU_DMI <5>
120MHz for eDP.
R2925 10K_0402_5%R2925 10K_0402_5%
1 2
R2926 10K_0402_5%R2926 10K_0402_5%
1 2
R2927 10K_0402_5%R2927 10K_0402_5%
1 2
R2928 10K_0402_5%R2928 10K_0402_5%
1 2
R2929 10K_0402_5%R2929 10K_0402_5%
1 2
R2930 10K_0402_5%R2930 10K_0402_5%
1 2
R2931 10K_0402_5%R2931 10K_0402_5%
1 2
R2932 10K_0402_5%R2932 10K_0402_5%
1 2
R2933 10K_0402_5%R2933 10K_0402_5%
1 2
R2934 @
R2934 @
Reserve for EMI please close to PCH
R2935
R2935
90.9_0402_1%
90.9_0402_1%
1 2
0.1_09
No use PU 10K +3VALW
DDR,WLAN,SMBUS
PU 2.2K +3VALW
No use PU 10K +3VALW
No use PU 10K +3VALW
EC-PCH SMBUS
PU 2.2K +3VALW
No use PU 10K +3VALW
12
R3053
R3053
GPIO65_H@
GPIO65_H@
R3054
R3054
10K_0402_5%
10K_0402_5%
GPIO65_L@
GPIO65_L@
C2868 @ 22P_0402_50V8JC2868 @ 22P_0402_50V8J
+1.05VS_VTT
12
1 2
33_0402_5%
33_0402_5%
10K_0402_5%
10K_0402_5%
D
1 2
PCH_GPIO64PCH_GPIO65
10K_0402_5%
10K_0402_5%
Pull down 10K ohm
for using internal
Clock
+3VS+3VS
12
R3019
R3019
GPIO64_H@10K_0402_5%
GPIO64_H@10K_0402_5%
R3052
R3052
GPIO64_L@
GPIO64_L@
1 2
SMB_ALERT#
PCH_SMBCLK
PCH_SMBDATA
RST_GATE
PCH_GPIO74
PCH_SML1CLK
PCH_SML1DATA
PCH_GPIO47
PCH_SMBDATA
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
PCH_SMBCLK
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
PCH_SML1DATA
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
PCH_SML1CLK
CLK_PCI_LPBACK <17>
R2907 10K_0402_5%R2907 10K_0402_5%
R2908 2.2K_0402_5%R2908 2.2K_0402_5%
R2909 2.2K_0402_5%R2909 2.2K_0402_5%
R2910 1K_0402_5%R2910 1K_0402_5%
R2911 10K_0402_5%R2911 10K_0402_5%
R2912 2.2K_0402_5%R2912 2.2K_0402_5%
R2913 2.2K_0402_5%R2913 2.2K_0402_5%
R2914 10K_0402_5%R2914 10K_0402_5%
+3VS
2
1
6
Q178A
Q178A
5
4
3
Q178B
Q178B
+3VS
2
1
6
Q179A
Q179A
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
XTAL25_IN
XTAL25_OUT
PCH_GPIO65
0
3
Q179B
Q179B
C2869
C2869
12P_0402_50V8J
12P_0402_50V8J
PCH_GPIO64
0
5
0 1
0
1
E
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
MEMORY
R2916
R2916
4.7K_0402_5%
4.7K_0402_5%
1 2
D_CK_SDATA
R2921
R2921
4.7K_0402_5%
4.7K_0402_5%
1 2
D_CK_SCLK
+3VS
+3VS
Pull up at EC side.
EC_SMB_DA2
EC_SMB_CK2
4
1 2
R2936 1M_0402_5%R2936 1M_0402_5%
25MHZ_10PF_7V25000014
25MHZ_10PF_7V25000014
3
3
GND
12
4
SKU 1
SKU 2
+VCCSUS3_3
D_CK_SDATA <11,12>
D_CK_SCLK <11,12>
EC_SMB_DA2 <35,37>
EC_SMB_CK2 <35,37>
1
GND
2
Y15
Y15
SKU
1
12
C2870
C2870
12P_0402_50V8J
12P_0402_50V8J
1 1
4 4
A
B
http://sualaptop365.edu.vn
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2012/11/222011/11/22
2012/11/222011/11/22
2012/11/222011/11/22
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (2/9) PCIE, SMBUS, CLK
PCH (2/9) PCIE, SMBUS, CLK
PCH (2/9) PCIE, SMBUS, CLK
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
Friday, August 10, 2012
Friday, August 10, 2012
Friday, August 10, 2012
E
4914
4914
4914
0.2Custom
0.2Custom
0.2Custom
A
+3VALW
R2938 10K_0402_5%@R2938 10K_0402_5%@
+VCCSUS3_3
1 1
2 2
R2940 10K_0402_5%R2940 10K_0402_5%
R2941 10K_0402_5%R2941 10K_0402_5%
R2942 10K_0402_5%R2942 10K_0402_5%
R2944 200_0402_5%R2944 200_0402_5%
R2946 10K_0402_5%R2946 10K_0402_5%
not support Deep S4,S5
can be left unconnected.
Check list1.5 P.81
not support AMT APWROK can mux
with PWROK (check list1.5 P.47)
12
12
12
12
12
Follow Tacoma 1.0
12
PCH_GPIO31
SUSWARN#_R
PCH_GPIO72
RI#
PM_DRAM_PWRGD
PCH_RSMRST#
T11 @PADT11 @PAD
T13 @PADT13 @PAD
+1.05VS_VTT
SUS_PWR_DN_ACK
T12 @PADT12 @PAD
XDP_DBRESET#<5>
PM_DRAM_PWRGD<5>
PCH_RSMRST#<35>
SUS_PWR_DN_ACK
SUSWARN# SUSWARN#_R
PBTN_OUT#<35>
No use PU 10K +3VALW
3 3
Ring Indicator CRB1.0 PU 10K +3VALW
B
DMI_CTX_PRX_N0<4>
DMI_CTX_PRX_N1<4>
DMI_CTX_PRX_N2<4>
DMI_CTX_PRX_N3<4>
DMI_CTX_PRX_P0<4>
DMI_CTX_PRX_P1<4>
DMI_CTX_PRX_P2<4>
DMI_CTX_PRX_P3<4>
DMI_CRX_PTX_N0<4>
DMI_CRX_PTX_N1<4>
DMI_CRX_PTX_N2<4>
DMI_CRX_PTX_N3<4>
DMI_CRX_PTX_P0<4>
DMI_CRX_PTX_P1<4>
DMI_CRX_PTX_P2<4>
DMI_CRX_PTX_P3<4>
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
L=500mil S=15mil
@
@
@
@
@
@
DMI_IRCOMP
0_0402_5%R2952
0_0402_5%
XDP_DBRESET#_R
SYS_PWROK
PCH_PWROK
PM_DRAM_PWRGD
PCH_RSMRST#
PBTN_OUT#
PCH_GPIO31
1 2
R2947 49.9_0402_1%R2947 49.9_0402_1%
1 2
R2948 750_0402_1%R2948 750_0402_1%
4mil width and place
within 500mil of the
PCH
R2950 @ 0_0402_5%R2950 @ 0_0402_5%
1 2
SUSACK# SUSACK#_RSUSACK#_R
1 2
R2952
1 2
R2954 0_0402_5%
R2954 0_0402_5%
EC_PWROK
R2957 @ 0_0402_5%R2957 @ 0_0402_5%
R2958 0_0402_5%
R2958 0_0402_5%
1 2
R2956 0_0402_5%
R2956 0_0402_5%
1 2
@
@
1 2
T14 @PADT14 @PAD
PCH_GPIO72
RI#
U103C
U103C
BC24
DMI0RXN
BE20
DMI1RXN
BG18
DMI2RXN
BG20
DMI3RXN
BE24
DMI0RXP
BC20
DMI1RXP
BJ18
DMI2RXP
BJ20
DMI3RXP
AW24
DMI0TXN
AW20
DMI1TXN
BB18
DMI2TXN
AV18
DMI3TXN
AY24
DMI0TXP
AY20
DMI1TXP
AY18
DMI2TXP
AU18
DMI3TXP
BJ24
DMI_ZCOMP
BG25
DMI_IRCOMP
BH21
DMI2RBIAS
C12
SUSACK#
K3
SYS_RESET#
P12
SYS_PWROK
L22
PWROK
L10
APWROK
B13
DRAMPWROK
C21
RSMRST#
K16
SUSWARN# / SUS_PWR_DN_ACK / GPIO30
E20
PWRBTN#
H20
ACPRESENT / GPIO31
E10
BATLOW# / GPIO72
A10
RI#
COUGARPOINT_FCBGA989
COUGARPOINT_FCBGA989
HM77@
HM77@
C
DMI
DMI
System Power Management
System Power Management
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI
FDI
FDI_RXP7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWVRMEN
DPWROK
WAKE#
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
PMSYNCH
SLP_LAN# / GPIO29
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
AW16
AV12
BC10
AV14
BB10
A18
E22
B9
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWODVREN
PCH_DPWROK
PCH_PCIE_WAKE#
CLKRUN#
SUS_STAT#
SUSCLK
PM_SLP_S5#
PM_SLP_S4#
PM_SLP_S3#
SLP_A#
SLP_SUS#
H_PM_SYNC
PCH_GPIO29
R2951 0_0402_5%
R2951 0_0402_5%
@
@
1 2
R2953 0_0402_5%
R2953 0_0402_5%
@
@
1 2
T217@PADT217@PAD
T218@ PADT218@ PAD
T219@ PADT219@ PAD
T220@ PADT220@ PAD
T221@ PADT221@ PAD
T237@ PADT237@ PAD
D
FDI_CTX_PRX_N0 <4>
FDI_CTX_PRX_N1 <4>
FDI_CTX_PRX_N2 <4>
FDI_CTX_PRX_N3 <4>
FDI_CTX_PRX_N4 <4>
FDI_CTX_PRX_N5 <4>
FDI_CTX_PRX_N6 <4>
FDI_CTX_PRX_N7 <4>
FDI_CTX_PRX_P0 <4>
FDI_CTX_PRX_P1 <4>
FDI_CTX_PRX_P2 <4>
FDI_CTX_PRX_P3 <4>
FDI_CTX_PRX_P4 <4>
FDI_CTX_PRX_P5 <4>
FDI_CTX_PRX_P6 <4>
FDI_CTX_PRX_P7 <4>
FDI_INT <4>
FDI_FSYNC0 <4>
FDI_FSYNC1 <4>
FDI_LSYNC0 <4>
FDI_LSYNC1 <4>
PCH_RSMRST#
SUSCLK <35>
PM_SLP_S5# <35>
PM_SLP_S4# <35>
PM_SLP_S3# <35>
H_PM_SYNC <5>
No use PU 10K +3VALW
DSWODVREN
DSWODVREN - On Die DSW VR Enable
H：Enable internal DSW +1.05VS
*
L：Disable
Must always PU at +RTCVCC
PCH_PCIE_WAKE#
PCH_GPIO29
CLKRUN#DMI2RBIAS
not support Deep S4,S5 DPWROK mux with
RSMRST#
PCIE_WAKE# <30,33>
check list1.5 P.50
No use PU 10K +3VS
Can be left NC
when IAMT is not
support on the
platfrom
not support
Deep S4,S5 can NC
PCH EDS1.5 P.75
E
R2937 330K_0402_5%R2937 330K_0402_5%
R2939 @ 330K_0402_5%R2939 @ 330K_0402_5%
R2943 10K_0402_5%R2943 10K_0402_5%
R2945 10K_0402_5%R2945 10K_0402_5%
R2949 8.2K_0402_5%R2949 8.2K_0402_5%
PCH_DPWROK
12
12
1 2
1 2
1 2
12
R2955
R2955
100K_0402_5%
100K_0402_5%
@
@
+RTCVCC
+VCCSUS3_3
+3VS
tell PCH all power ok
but cpu core
EC_PWROK<35>
4 4
EC_PWROK
R2960
R2960
10K_0402_5%
10K_0402_5%
VGATE<35,44>
12
A
+3VS
5
U106
U106
2
P
B
1
A
G
MC74VHC1G08DFT2G_SC70-5
MC74VHC1G08DFT2G_SC70-5
3
Y
4
ALL power OK
SYS_PWROK
B
12
R2961
R2961
10K_0402_5%
10K_0402_5%
SYS_PWROK <5>
12
C2871
C2871
@
@
0.047U_0402_16V7K
0.047U_0402_16V7K
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN TIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN TIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN TIAL
AND TRADE SECRET INFORMATION. THIS SHEET MA Y NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MA Y NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MA Y NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2012/11/222011/11/22
2012/11/222011/11/22
2012/11/222011/11/22
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (3/9) DMI,FDI,PM
PCH (3/9) DMI,FDI,PM
PCH (3/9) DMI,FDI,PM
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
VBA20 LA-9303P M/B
Friday, August 10, 2012
Friday, August 10, 2012
Friday, August 10, 2012
E
4915
4915
4915
0.2Custom
0.2Custom
0.2Custom
http://sualaptop365.edu.vn
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