Compal LA-9262P VAZA0, XPS 12 Schematic

MODEL NAME :

PCB NO :

LA-9262P ( DAB0000I010 )

VAZA0

BOM P/N :

1 1

Dell/Compal Confidential

2 2

ZZZ M

B_PCB

Schematic Document

Murcielgo MLK (Haswell ULT)

3 3

2013-04-19

Rev: 1.0

Highlight the short pad for 0 ohm

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/02 2013/10/28

Compal Secre t Data

Deciphered Date

pal Electronics, Inc.

Com

Title

Size Document Number Rev

Date: Sheet of

Com

P01-Cover Page

LA-9262P

1 45Friday, Ap ril 19, 2013

1.0

1 1

eDP Panel Conn x 2.

miniDP Conn.

P.17

P.19

eDP 1.3

DP 1.2

Memory Bus (DDR3L-RS)

Dual Channel

1.35V DDR3L-RS 1600 MHz

Channel A DDR3L-RS 4Gb or 8Gb (x16) * 4

P.12, 14

Channel B DDR3L-RS 4Gb or 8Gb (x16) * 4

P.13, 14

Intel

Haswell ULT

BGA 1168 Balls

USB 3.0 Conn.

2 2

( USB Charger Port )

Digital Camera

P.23

P.17

USB3.0/USB2.0

USB2.0

Touch Screnn

P.17

e-Compass +

I2C

Accelerometer

DE303DLHCTR

3 3

Gyro Sensor

TX3GD20TR

P.20

Pressure Sensor

APS331APTR

P.20

Sensor HUB

STM32F103RC

NFC Module Conn

Touch Pad

P.20

P.22

P.27

I2C

USB2.0

I2C

SMLink

I2C

15W TDP

Page 5, 6, 7, 8, 9, 10, 11

SATA3.0

SPI

SDIO

UART

USB2.0

PCIE *2

HDA

Audio DSP ALC5505

PCM

HDA

P.18

Mini Card (Full)

# mSATA

SPI ROM 8M

NFGG Slot A-SD

WLAN BT WiGig

Daughter Board

Audio Codec ALC3661

P.22

P.07

P.21

Headphone Jack

( iPhone & Nokia compatible)

ALS+CLS

TCS3472

Intel used Capella

FAN conn.

4 4

RTC conn.

DC/DC Interface CKT.

Power Circuit DC/DC

P.20

P.27

P.26

P.25

P.29 ~ 39

TPM AT97SC3204

P.20

SMBus

ENE KB9012BF

Intel used Renesas

Int.KBD

P.26

LPC Bus

Digital MIC

P.17

IOL BTB Conn

P.18

P.28

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

2011/02/23 2013/10/28

Compal Secre t Data

Deciphered Date

Audio AMP APA2605

Title

Size Document Number Rev

Date: Sheet of

P02-Block Diagram

LA-9262P

Int. Speaker

mpal Electronics, Inc.

2 45Friday, Ap ril 19, 2013

1.0

Compal Confidential

Project Code : VAZA0 File Name : LA-9262P

1 1

LS-9261P

Volume Up/Down, PWR, Rotation Button

2 2

Audio Jack

FPC

36 pin

LS-8822P Win8 Button Hall Sensor

Camera

LA-9262P M/B

Keyboard

Keyboard Back light

3 3

FPC (main frame)

30 pin

FFC

4 pin

FFC

6 pin

Touch Pad

CABLE

9 pin

Battery Pack

FPC

16 pin to 15 pin

NFC Module

eDP Cable x 2

Coaxial and Wire

LCD Panel Touch Panel Control Baor d

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

2011/06/02 2013/10/28

Compal Secre t Data

Deciphered Date

mpal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

P03-DaughterB block diagram

LA-9 262P

3 45Friday, Ap ril 19, 2013

1.0

Board ID Table for AD channel

Ra 100K +/- 1%

SMBUS Control Table

EC_SMB_CK1 EC_SMB_DA1

EC_SMB_CK2 EC_SMB_DA2

PCH_SML0CLK PCH PCH_SML0DATA

1 1

PCH_SML1CLK PCH_SML1DATA

MEM_SMBCLK MEM_SMBDATA

3.3V +/- 5%Vcc

VRbBoard ID

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

0 12K +/- 1% 15K +/- 1% 20K +/- 1% 27K +/- 1% 33K +/- 1% 43K +/- 1% 56K +/- 1% 75K +/- 1% 100K +/- 1% 130K +/- 1% 160K +/- 1% 200K +/- 1% 240K +/- 1% 270K +/- 1% 330K +/- 1% 430K +/- 1% 560K +/- 1% 750K +/- 1%

SOURCE

KB9012

NGFF BATT DDR3 SPD

min

V V

AD_BID typVAD_BID

NFCCharger

XDP

maxAD_BIDV

EC AD3

ALS

PCH

V V

BOARD ID Table

Board ID

Touch Pad

PCB Revision

Link

CS 0.1 CS 0.2 CS 0.3 CS 0.4 CS 0.5 CS 1.0

Non-CS 0.1 Non-CS 0.2 Non-CS 0.3 Non-CS 0.4 Non-CS 1.0

PCH USB Port Mapping

PCH DDI

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Port Mapping

USB PORT#

DESTINATION

External USB3

NGFF CARD WLAN

Touch Panel

Camera

Sensors HUB

DDI PORT# DESTINATION

mini-DP

CLK

CLKOUT_PCIE1

CLKOUT_PCIE2

CLKOUT_PCIE3

CLKOUT_PCIE4

CLKOUT_PCIE5

DESTINATIONDIFFERENTIAL

NGFF CARD WLAN

FLEX CLOCKS DESTINATION

CLKOUT_LPC_0

CLKOUT_LPC_1

EC LPC

TPM

SATA PCI EXPRESS

SATA0

SATA1

SATA2

SATA3

DESTINATION

m-SATA

Lane 1CLKOUT_PCIE0

Lane 2

Lane 3

Lane 4

NGFF CARD WLAN

Lane 5

Lane 6

curity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

2011/06/02 2013/10/28

Compal Secre t Data

Deciphered Date

DESTINATION

Symbol Note :

: means Digital Ground

: means Analog Ground

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P04-Notes List

LA-9262P

4 45Friday, Ap ril 19, 2013

1.0

eDP SIDEBAND

PCIE

THERMAL

DDR3L

MISC

PWR

HSW_ULT_DDR3L

1 OF 19

9 OF 19

2 OF 19

EDPDDI

DISPLAY

JTAG

EDP_TXN0

EDP_TXP0

EDP_TXN1

EDP_TXP1

EDP_TXN2

EDP_TXP2

EDP_TXN3

EDP_TXP3

EDP_AUXN EDP_AUXP

EDP_RCOMP

EDP_DISP_UTIL

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPB_AUXN

DDPC_AUXN

DDPB_AUXP DDPC_AUXP

DDPB_HPD DDPC_HPD

EDP_HPD

PRDY

PREQ PROC_TCK PROC_TMS

PROC_TRST

PROC_TDI

PROC_TDO

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

C45 B46 A47 B47

C47 C46 A49 B49

A45 B45

D20 A43

Width 20 mils, Spacing 25 mils, Length < 100 mil

B9 C9 D9 D11

C5 B6 B5 A6

C8 A8 D6

J62 K62 E60 E61 E59 F63 F62

J60 H60 H61 H62 K59 H63 K60 J61

eDP_TXN_P0 19 eDP_TXP_P0 19 eDP_TXN_P1 19 eDP_TXP_P1 19

eDP_AUXN 19 eDP_AUXP 19

+EDP_COM EDP_DISP

PCH_DP_CLK PCH_DP_DAT

PCH_DP_HPD

CPU_eDP_HPD#

XDP_PRDY# XDP_PREQ# CPU_XDP_TCK CPU_XDP_TMS CPU_XDP_TRST# CPU_XDP_TDI CPU_XDP_TDO

closed MCP 1000 mils

XDP_PRDY# XDP_PREQ#

CPU_XDP_TCK CPU_XDP_TMS CPU_XDP_TRST# CPU_XDP_TDI CPU_XDP_TDO

1 2

RC36 24.9_04 02_1% RC158 0_0402_ 5%@

T226@ T227@ T228@ T229@ T230@ T231@

PCH_DP_CLK 21 PCH_DP_DAT 2 1

PCH_DP_AUXN 21

PCH_DP_AUXP 21

PCH_DP_HPD 21

XDP_PRDY# 18 XDP_PREQ# 18 CPU_XDP_TCK 18 CPU_XDP_TMS 18 CPU_XDP_TRST# 18 CPU_XDP_TDI 18 CPU_XDP_TDO 18

XDP_BPM0# 18 XDP_BPM1# 18

T263@ T264@

T265@ T266@ T267@ T268@ T269@

+VCCIOA_OUT

CPU_eDP_HPD#

PU/PD for JTAG signals

CPU_XDP_TMS

CPU_XDP_TDI

CPU_XDP_TDO

CPU_XDP_TCK

CPU_XDP_TRST#

Stuffed : Dual TCK

unstuffed : Singel TCK

Stuffed : Single & Dual TCK

DII-DMN65D8LW-7

0_0402_ 5%

RC160 100K_040 2_5%

+5VS

QC5

RC148

1 2

RC138 100K_040 2_5%

+1.05VS_VCCST

RC4551_0402 _5% @

RC4651_0402 _5% @

RC4851_0402 _5%

RC5251_0402 _5%

RC5451_0402 _5% @

R1d

R2 R9

eDP_HPD 19

UCPU1A

EDP_BKLCTL ENBKL PCH_ENVDD

MPCIE_RST# TPM_IRQ# PCI_PIRQC# PCI_PIRQD#

TP_INT#

Sensor_RST # AUDIO_IRQ#

DDR_PG_CNTL

AU60 AV60 AU61 AV15 AV61

D61 K61 N62

K63

C61

C54 C55 B58 C58 B55 A55 A57 B57

C51 C50 C53 B54 C49 B50 A53 B53

U6 P4 N4 N2

AD4

U7 L1 L3 R5

UCPU1B

PROC_DETECT CATERR PECI

PROCHOT

PROCPWRGD

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST SM_PG_CNTL1

DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3

DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3

UCPU1I

EDP_BKLCTL EDP_BKLEN EDP_VDDEN

PIRQA/GPIO77 PIRQB/GPIO78 PIRQC/GPIO7 9 PIRQD/GPIO8 0 PME

GPIO55 GPIO52 GPIO54 GPIO51 GPIO53

PCH_DP_N021 PCH_DP_P021 PCH_DP_N121 PCH_DP_P121

D D

RC147 0_0402_ 5%@

PCH_INV_PWM19

RH123 100K_040 2_5%@

1 2

RH158 100K_040 2_5%@

1 2

RH300 1M_0402_ 5%

+3VS

1 2

RH281 2.2K_040 2_5%

1 2

RH282 2.2K_040 2_5%

1 2

RH380 100K_040 2_5%@

C C

B B

1 8

RP2 10K_8P4R_5 %

2 7 3 6 4 5

RH396 10K_0402 _5%@

1 2 1 2

RH397 10K_0402 _5%@

1 2

RH381 100K_040 2_5%@

RH452 10K_0402 _5%

1 2

RC44 10K_0402 _5%

Avoid stub in the PWRGD path while placing resistors RC44 & RC53

H_CPUPWRGD_R

1 2

RC146 0_0402_ 5%

ENBKL

PCH_ENVDD

PCH_DP_HPD

PCH_DP_CLK PCH_DP_DAT

TP_INT#

PCI_PIRQC# PCI_PIRQD#

TPM_IRQ#

AUDIO_IRQ# NGFF_WAKE#

MPCIE_RST#

Sensor_RST #

H_PROCHOT#30,32

SM_PG_CTRL39

EDP_BKLCTL

EDP_DISP

+1.05VS_VCCST

RC43 62_0402 _5%

1 2

Width 15 mils, Spacing 25 mils, Length < 500 mil

DDR3 Compensation Signals

+3VS +1.35V_DDR

RC159 220K_040 2_5%

RC161 2M_0402_ 5%

CC240 0 .1U_0402_10V7 K@

PCH_DP_N221 PCH_DP_P221 PCH_DP_N321 PCH_DP_P321

ENBKL19 PCH_ENVDD19,35

MPCIE_RST#23

TP_INT#29

TS_RST#19 NGFF_WAKE#23 Sensor_RST #22

T2@

H_PECI30

1 2

RC41 56_0402 _5%

RC55200_040 2_1% RC58121_040 2_1%

12 12

RC60100_040 2_1%

1 2

UC1

VCC

GND

74AUP1G07GW_ TSSOP5

T123

NGFF_WAKE#

H_CATERR#

H_PROCHOT#_RH_PROCHOT#

H_CPUPWRGD_R

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 H_DRAMRST#

DDR_PG_CNTL

+1.35V_DDR

A A

02-0320

H_DRAMRST#

1 2

RC162 0_0402_ 5%@

RC75 470_040 2_5%

DDR3_DRAMRST# 12, 13,14,15

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

2011/06/02 2013/10/28

Compal Secre t Data

Deciphered Date

mpal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

P05-MCP(1/7) DDI,EDP,PM,XDP

LA-9262P

5 45Friday, Ap ril 19, 2013

1.0

D D

HSW_ULT_DDR3L

DDR CHANNEL A

SA_CLK#0

SA_CLK0

SA_CLK#1

SA_CLK1

SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3

SA_CS#0 SA_CS#1

SA_ODT0

SA_RAS

SA_WE

SA_CAS

SA_BA0 SA_BA1 SA_BA2

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7

SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7

SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1

AU37 AV37 AW36 AY36

AU43 AW43 AY42 AY43

AP33 AR32

AP32

AY34 AW34 AU34

AU35 AV35 AY41

AU36 AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42

AJ61 AN62 AM58 AM55 AV57 AV53 AL43 AL48

AJ62 AN61 AN58 AN55 AW57 AW53 AL42 AL49

AP49 AR51 AP51

10 mil trace width

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

M_CLK_A_DDR#0 12,13 ,16 M_CLK_A_DDR0 12,13, 16

DDR_A_CKE0 12,13,16 DDR_A_CKE1 12,13,16

DDR_A_CS0# 12,13,1 6 DDR_A_CS1# 12,13,1 6

DDR_A_RAS# 12,13,16 DDR_A_WE# 1 2,13,16 DDR_A_CAS# 12,13,16

DDR_A_BS0 12 ,13,16 DDR_A_BS1 12 ,13,16 DDR_A_BS2 12 ,13,16

DDR_A_MA[0..15 ] 12,13,16

DDR_A_DQS#[0 ..7] 12,1 3

DDR_A_DQS[0. .7] 12,13

V_DDR_REF_C A 1 6 V_DDR_REFA_R 16 V_DDR_REFB_R 16

DDR_B_D[0..6 3]14,15

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AY31

AW31

AY29

AW29

AV31 AU31 AV29 AU29 AY27

AW27

AY25

AW25

AV27 AU27 AV25 AU25

AM29

AK29 AL28 AK28 AR29 AN29 AR28 AP28 AN26 AR26 AR25 AP25 AK26

AM26

AK25 AL25 AY23

AW23

AY21

AW21

AV23 AU23 AV21 AU21 AY19

AW19

AY17

AW17

AV19 AU19 AV17 AU17 AR21 AR22 AL21

AM22

AN22 AP21 AK21 AK22 AN20 AR20 AK18 AL18 AK20

AM20

AR18 AP18

UCPU1D

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

DDR_A_D[0..6 3]12,13

C C

B B

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

AH63 AH62 AK63 AK62 AH61 AH60 AK61

AK60 AM63 AM62

AP63

AP62 AM61 AM60

AP61

AP60

AP58

AR58 AM57

AK57

AL58

AK58

AR57

AN57

AP55

AR55 AM54

AK54

AL55

AK55

AR54

AN54

AY58 AW58

AY56 AW56

AV58

AU58

AV56

AU56

AY54 AW54

AY52 AW52

AV54

AU54

AV52

AU52

AK40

AK42 AM43 AM45

AK45

AK43 AM40 AM42 AM46

AK46 AM49

AK49 AM48

AK48 AM51

AK51

UCPU1C

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

HSW_ULT_DDR3L

DDR CHANNEL B

SB_CK#0

SB_CK0

SB_CK#1

SB_CK1

SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3

SB_CS#0 SB_CS#1

SB_ODT0

SB_RAS

SB_WE

SB_CAS

SB_BA0 SB_BA1 SB_BA2

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7

SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7

AM38 AN38 AK38 AL38

AY49 AU50 AW49 AV50

AM32 AK32

AL32

AM35 AK35 AM33

AL35 AM36 AU49

AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46

AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18

AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

M_CLK_B_DDR#0 14,15 ,16 M_CLK_B_DDR0 14,15,16

DDR_B_CKE0 14,15,16 DDR_B_CKE1 14,15,16

DDR_B_CS0# 14,15,16 DDR_B_CS1# 14,15,16

DDR_B_RAS# 14,15,16 DDR_B_WE# 14,15,16 DDR_B_CAS# 14,15,16

DDR_B_BS0 14 ,15,16 DDR_B_BS1 14 ,15,16 DDR_B_BS2 14 ,15,16

DDR_B_MA[0..15 ] 14,15,16

DDR_B_DQS#[0 ..7] 14,1 5

DDR_B_DQS[0. .7] 14,15

A A

3 OF 19

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

2011/06/02 2013/10/28

Compal Secre t Data

Deciphered Date

4 OF 19

mpal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

P06-MCP(2/7) DDRIII

LA-9262P

1.0

6 45Friday, Ap ril 19, 2013

1.0

CH2 15P_0402 _50V8J

32.768KHZ_12. 5PF_9H032000 31

CH3

D D

+RTCVCC

1U_0402_6. 3V6K

1 2

RH23 20K_0402 _5%

1U_0402_6. 3V6K

+RTCVCC

C C

PCH JTAG

+1.05VA

Stuffed : Single & Dual TCK

R3d

R5 R8

B B

A A

YH1

15P_0402 _50V8J

far away hot spot

CH4

CH5

1 2

RH31 330K_040 2_5%

1 2

RH34 330K_040 2_5%@

INTVRMEN

H：Integrated VRM enable

L：Integrated VRM disable

1 2

RH40 51_0402 _5%

1 2

RH445 51 _0402_5%

1 2

RH39 51_0402 _5%

RH375 1K_ 0402_5%@

1 2

RH53 51_0402 _5%@

+3VS

SPI_SO_ROM SPI_IO2_ROM

I_SI_ROM

PCH_SPI_CS# SPI_SO_ROM

PCH_RTCX1

RH2 10M_0402 _5%

PCH_RTCX2

CMOS

CLRP1 SHORT PADS

PCH_RTCRST#

PCH_SRTCRST#

CLRP2 SHORT PADS

ME CMOS

CLP1 & CLP2 place near DIMM

PCH_INTVRMEN

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAG_TMS

PCH_JTAG_JTAGX

PCH_JTAG_TCK

1 2

RH54 1K_0402_ 5%

RH56 1K_0402_ 5%

1 2

Closed to UCPU1

RH255 15_0402 _5%

1 2

RP4

1 8 2 7 3 6 4 5

15_0804 _8P4R_5%

SPI ROM FOR ME ( 8MByte ) ROM is Quad SPI

U48

/CS

DO(IO1)

/HOLD(IO 3)

/WP(IO2)

GND

W25Q64F VSSIQ_SO8

DI(IO0)

HDA_BITCLK_AUDIO20 HDA_RST_AUDIO#20 HDA_SYNC_AUDIO20 HDA_SDOUT_AUDIO20

From EC, for enable ME code programing

+1.5VS_3.3VS_ AUDIO

CLK_REQ2#23

SPI_IO2_ROM

SPI_IO3_ROM

PCH_SPI_CLKSPI_CLK_ROM

PCH_SPI_SO PCH_SPI_IO2

H_SPI_SI

PC PCH_SPI_IO3SPI_IO3_ROM

VCC

SPI_IO3_ROM

SPI_CLK_ROMSPI_IO2_ROM

CLK

I_SI_ROM

HDA_SDO30

WLAN

+3VS

+RTCVCC

RP3

1 8 2 7 3 6 4 5

33_8P4R_ 5%

Q351

DII-DMN65D8LW-7

RH410

1 2

0_0402_ 5%

DII-DMN65D8LW-7

Q346

CH .1U_0402_1 6V7K

1 3

R1197 100K_040 2_5%

1 2

RH11 1M_0402_ 5%

PCH_RTCRST#18

HDA_BIT_CLK HDA_RST# HDA_SYNC HDA_SDOUT

HDA_SDIN020

PCH_JTAG_JTAGX

T273@

PCH_JTAG_TDO

T275@

PCH_JTAG_TMS

T276@RH25 20K_0402 _5%

PCH_JTAG_TCK

T277@ T278@

PCH_JTAG_TDI

closed MCP 1000 mils

PCH_JTAG_TRST#18 PCH_JTAG_TCK18 PCH_JTAG_TDI18 PCH_JTAG_TDO18 PCH_JTAG_TMS18

PCH_JTAG_JTAGX18

+5VA

R1341 1M_0402_ 5%

1 2

RH24 1K_0402_ 5%

1 2

RH91 10K_0402 _5%@

+3VS

RH95 10K_0402 _5%@

CLK_PCIE2#23 CLK_PCIE223

+3VS

+3VS_NGFF

1 2

RH100 10K_0402 _5%

1 2

RH103 10K_0402 _5%@

1 2

RH107 10K_0402 _5%@

1 2

RH110 10K_0402 _5%@

PCH_GPIO20

PCH_RTCX1 PCH_RTCX2 SM_INTRUDER# PCH_INTVRMEN PCH_SRTCRST# PCH_RTCRST#

HDA_BIT_CLK HDA_SYNC HDA_RST#

HDA_SDOUT

PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_JTAG_JTAGX

LPC_AD01 8,22,30 LPC_AD11 8,22,30 LPC_AD21 8,22,30 LPC_AD31 8,22,30 LPC_FRAME#18,22,30

1 2

12P_0402 _50V8J

SML1CLK

SML1DATA

AW5

AY5 AU6 AV7 AV6 AU7

AW8

AV11

AU8 AY10 AU12 AU11

AW10

AV10

AY8

AU62 AE62 AD61 AE61 AD62 AL11

AC4 AE63

AV2

HDA_SDOUT

PCH_GPIO18

PCH_GPIO19

PCH_GPIO20

PCH_GPIO21

PCH_GPIO22

PCH_GPIO23

PCH_SPI_CLK PCH_SPI_CS#

PCH_SPI_SI PCH_SPI_SO PCH_SPI_IO2 PCH_SPI_IO3

MC118

PCH_SPI_CLK

6 1

DMN66D0LDW-7_SO T363-6

1 2

453 0_040 2_5%@

MC94

22P_0402 _50V8J

Reserve for EMI please close to U48

UCPU1E

RTCX1 RTCX2 INTRUDER INTVRMEN SRTCRST RTCRST

HDA_BCLK/I2S0_ SCLK HDA_SYNC/I2S0_ SFRM HDA_RST/I2S_MCLK HDA_SDI0/I2S0 _RXD HDA_SDI1/I2S1 _RXD HDA_SDO/I2S0 _TXD HDA_DOCK_EN/I2 S1_TXD HDA_DOCK_RST/I2 S1_SFRM I2S1_SCLK

PCH_TRST PCH_TCK PCH_TDI PCH_TDO PCH_TMS RSVD RSVD JTAGX RSVD

UCPU1F

C43

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

PCIECLKRQ0/GPI O18

B41

CLKOUT_PCIE_N1

A41

CLKOUT_PCIE_P1

PCIECLKRQ1/GPI O19

C41

CLKOUT_PCIE_N2

B42

CLKOUT_PCIE_P2

AD1

PCIECLKRQ2/GPI O20

B38

CLKOUT_PCIE_N3

C37

CLKOUT_PCIE_P3

PCIECLKRQ3/GPI O21

A39

CLKOUT_PCIE_N4

B39

CLKOUT_PCIE_P4

PCIECLKRQ4/GPI O22

B37

CLKOUT_PCIE_N5

A37

CLKOUT_PCIE_P5

PCIECLKRQ5/GPI O23

UCPU1G

AU14

LAD0

AW12

LAD1

AY12

LAD2

AW11

LAD3

AV12

LFRAME

AA3

SPI_CLK

SPI_CS0

SPI_CS1

AC2

SPI_CS2

AA2

SPI_MOSI

AA4

SPI_MISO

SPI_IO2

AF1

SPI_IO3

+3VS

QH4A

DMN66D0LDW-7_SO T363-6

1 2

33_0402 _5%

RH454 0_0402 _5%@

MR256

1 2

QH4B

I_CLK_ROM

HSW_ULT_DDR3L

RTC

AUDIO SATA

JTAG

5 OF 19

HSW_ULT_DDR3L

6 OF 19

HSW_ULT_DDR3L

LPC

7 OF 19

PCH_SMLCLK 19, 26,30

Connect EC, ALS

PCH_SMLDATA 19,26 ,30

Security Classification

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

CLOCK

SIGNALS

SMBUS

C-LINKSPI

Issued Date

SATA_RN0/PERN6_L 3 SATA_RP0/PERP6_L3

SATA_TN0/PETN6_L3 SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L 2 SATA_RP1/PERP6_L2

SATA_TN1/PETN6_L2 SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L 1 SATA_RP2/PERP6_L1

SATA_TN2/PETN6_L1 SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L 0

SATA_RP3/PERP6_L0 SATA_TN3/PETN6_L0

SATA_TP3/PETP6_L0

SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37

SATA_RCOMP

XTAL24_IN

XTAL24_OUT

RSVD RSVD

DIFFCLK_BIASREF

TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8

CLKOUT_LPC_0 CLKOUT_LPC_1

CLKOUT_ITPXDP

CLKOUT_ITPXDP_P

SMBALERT/GPIO11

SMBCLK

SMBDATA

SML0ALERT/GPIO60

SML0CLK

SML0DATA

SML1ALERT/PCHHOT/GPIO 73

SML1CLK/GPIO7 5

SML1DATA/GPIO74

CL_CLK

CL_DATA

CL_RST

SMBCLK

SMBDATA

J5 H5 B15 A15

J8 H8 A17 B17

J6 H6 B14 C15

F5 E5 C17 D17

V1 U1 V6 AC1

A12

SATA_IREF

L11

RSVD

K10

RSVD

C12 U3

SATALED

A25

XTAL24_IN

B25

XTAL24_OUT

K21 M21 C26

XCLK_BIASREF

C35

TESTLOW1

C34

TESTLOW2

AK8

TESTLOW3

AL8

TESTLOW4

AN15

CLKOUT_LPC0

AP15

CLKOUT_LPC1

B35 A35

LPC CLOC K CAN FE ED ONLY 1 LOAD AT A TIME

AN2

SMBALERT#

AP2

SMBCLK

AH1

SMBDATA

AL2

SML0ALERT#

AN1

SML0CLK

AK1

SML0DATA

AU4 AU3

SML1CLK

AH3

SML1DATA

AF2 AD2 AF4

QH3A

6 1

DMN66D0LDW-7_SO T363-6

1 2

RH105 0_0402 _5%@

DMN66D0LDW-7_SO T363-6

2011/06/02 2013/10/28

SATA_PRX_DTX_N0 24 SATA_PRX_DTX_P0 24 SATA_PTX_DRX_N0 24 SATA_PTX_DRX_P0 24

closed MCP 2000 mils

EC_SMI# PCH_GPIO35 PCH_GPIO36 mSATA_DET#

SATA_RCOMP PCH_SATALED#

Width = 15 mil, Spacing = 12 mil Close PCH within 500 mil

XCLK_BIA SREF <10 0 MILS

TESTLOW1 TESTLOW2 TESTLOW3 TESTLOW4

1 2

RH111 0_0402 _5%@

Compal Secre t Data

EC_SMI# 30

mSATA_DET# 24

1 2

RH43 3K_0402_ 1%

RH35 10K_0402 _5%

1 2

RH113 3K_0402_ 1%

RH428 22_0402 _5%

1 2 1 2

RH360 22_0402 _5%

1 2

RH386 30_0402 _5%

RH76 10K_0402 _5%

1 2 1 2

RH77 10K_0402 _5%

1 2

RH78 10K_0402 _5%

1 2

RH79 10K_0402 _5%

SMBALERT# 22

SML0CLK 24 SML0DATA 24

SML1ALERT# 22

CL_CK 23 CL_DAT 23 CL_RST# 23

+3VS

RH98

10K_0402 _5%

QH3B

Deciphered Date

mSATA

T270@ T271@ T272@ T274@

+V1.05S_ASATA3 PLL

+3VS

Connect NFC

PU to +3VNS_PWR on Sensor HUB side

RH99 10K_0402 _5%

PCH_SMBCLK 1 2,14,18,19

Connect DDR SPD, XDP

PCH_SMBDATA 1 2,14,18,19

+V1.05S_AXCK_LCPLL

CLK_PCI_TPM 22 CLK_PCI_LPC 30 CLK_LPC_DEBUG 18

MC103 10P_0402 _50V8J@

HDA_SDOUT

Reserve for RF please close to UH1

+3VS

PCH_GPIO35 PCH_GPIO36 mSATA_DET#

HDA_SDO

ME debug mode , this signal has a weak internal PD

L=>security measures defined in the Flash Descriptor will be in effect (default)

1 2

RH390 10K_0402 _5%@

1 2

RH391 200K_040 2_5%@

1 2

RH392 100K_040 2_5%

H=>Flash Descriptor Security will be overridden

+1.5VS_3.3VS_ AUDIO

1 2

RH42 1K_0402_ 5%@

Low = Disabled

High = Enabled

XTAL24_IN

XTAL24_OUT

Title

Size Document Number Rev

Date: Sheet of

1 2

RH117 1M_0402_ 5%

YH2

24MHZ_12PF_7V24 000020

123

CH24 15P_0402 _50V8J

SMBCLK SMBDATA SML1CLK SML1DATA

SML0CLK

SML0DATA

SM SML0ALERT# EC_SMI#

P07-MCP(3/7) SATA,HD A,CLK,SPI

LA-9262P

RH70 499_040 2_1%

RH72 499_040 2_1%

BALERT#

mpal Electronics, Inc.

RP7

1 8 2 7 3 6 4 5

2.2K_080 4_8P4R_5%

1 2

RP19

1 8 2 7 3 6 4 5

10K_8P4R_5 %

HDA_SDOUT

CH23 15P_0402 _50V8J

7 45Friday, Ap ril 19, 2013

+3V_PCH

+3VS

1.0

+3VS

Deep S3 support, connect to EC

1 2

RP20

1 8 2 7 3 6 4 5

10K_8P4R_5 %

1 2

LOW=Default

HIGH=No Reboot

NON-Deep S3 Support

+3V_PCH_DSW

+3VS

PCH_GPIO15

BT_RADIO_DIS#

NFC_IRQ

UART_WAKE#

USB0_PWR_EN

SENSOR_INT#

EC_RUNTIME_SCI#

PCH_GPIO17

NFC_DET#

UART1_RXD

UART1_TXD

UART1_RTS#

UART1_CTS#

TS_INT#

HDA_SPKR

TPM_DET

SUSACK#30 PM_SYS_RESET#18 SYS_PWROK18,29 PCH_PWROK29

PCH_RSMRST#3 0 PCH_SUSWARN#30 PBTN_OUT#30 AC_PRESENT30

PM_SLP_S0#18,30,36 ,38

Deep S3 support, PCH_GPIO27 connect from EC PCH_WAKE#

PM_CLKRUN#

D D

SLP_WLAN#

RH248 8.2K_040 2_5%

RH402 10K_0402 _5%@

Deep S3 support, connect to DSW power rail

SYS_RESET#

PCH_GPIO27 PCH_GPIO72

AC_PRESENT

PCH_GPIO27

PCH_RSMRST#

SYS_PWROK

PCH_PWROK

C C

PCH_GPIO15

TLS Confidentiality

+3V_PCH

B B

+3VS

+3V_PCH

A A

RH12 1M_0402_ 5%

RH186 1K_0402_ 5%@

RH159 100K_040 2_5%

RH272 10K_0402 _5%@

RH394 100K_040 2_5%

Low - Intel ME Crypto Transport Layer Security (TLS)

cipher suite with no confidentiality High - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality

RH270 1K_0402_ 5%@

RH188 100K_040 2_5%@

RH294 10K_0402 _5%@

RH383 100K_040 2_5%

RH400 100K_040 2_5%@

RH295 10K_0402 _5%@

1 2

RH398 10K_0402 _5%

1 2

RH395 10K_0402 _5%@

RH465 1M_0402_ 5%

RH457 49.9K_04 02_1%

RH458 49.9K_04 02_1%

RH459 49.9K_04 02_1%

RH460 49.9K_04 02_1%

RH384 100K_040 2_5%@

+3VS

RH37 1K_0402_5%@

1 2

TPM@

1 2

RH274 10K_0402 _5%

RH337 100K_040 2_5%

NTPM@

TPM BOM Optional

PBTN_OUT#_R

02-0320

SUS_PWR_DN

PCH_RSMRST# PCH_RSMRST#_R

1.05VS_PG18,29 ,30

PBTN_SW#18,20,29,3 0

PLT_RST#18 ,22,23,30

RH171 100K_040 2_5%

closed MCP 2000 mils

T279@ T280@ T281@ T282@ T283@ T284@ T285@ T286@ T287@ T288@

I2C0_SDA

RH461 2.2K_040 2_5%@

I2C0_SCK

RH462 2.2K_040 2_5%@

Audio DSP

TPM_DET

TPM

1 = W/TP M

0 = W/O TPM

Sensor HUB

1 2

R1312 3K_ 0402_5%@

Non Deep S3 (Pop RH429)

Deep S3 (Pop RH430)

RH429 0_0402_ 5%@ RH430 0_0402_ 5%@ RH450 0_0402_ 5%@

RH131 0_0402_ 5%@

RH133 0_0402_ 5%@ RH297 0_0402_ 5%@ RH293 0_0402_ 5%@ RH137 0_0402_ 5%@

RH463 0_0402_ 5%@

RH438 0_0402_ 5%@

RH439 0_0402_ 5%@

SENSOR_HUB_I2C_WAKE22

12 12 12

12 12 12 12

1 2

RH168 0_0402_5%@

+3VS

IN1

IN2

UH5 SN74AHC1G08DCKR_SC70 -5

AUDIO_PWREN SENSOR_HUB_I2C_WAKE PCH_GPIO17 KB_DET# EC_RUNTIME_SCI# KB_BL_DET SENSOR_INT# MEM_CONFIG0 MEM_CONFIG1 UART_WAKE#

AUDIO_PWREN20,27,35

KB_BL_DET2 8

KB_DET#28

NFC_RST#24

NFC_IRQ24

TPM_RST#22 BT_CS_NOTICE23

SLATE_MODE22

SENSOR_DFU_EN#22

TS_INT#19 MPHY_PWREN2 7 USB0_PWR_EN25 SENSOR_INT#22

EN_CAM27

SENSOR_EN22,27

UART_WAKE#2 3

EC_RUNTIME_SCI#30

DEVSLP024

SENSOR_STANDBY#22

WL_OFF #23 NFC_DET#24 HDA_SPKR20

1 2

I2C0_SDA_DSP20

I2C0_SCK_DSP20

I2C0_SDA_SNR22

I2C0_SCK_SNR22

+3V_PCH

SUSACK#_R SYS_RESET# SYS_PWROK PCH_PWROK APWROK_R PCH_PLTRST#

SUS_PWR_DN PBTN_OUT#_R AC_PRESENT_RAC_PRESENT PCH_GPIO72 SLP_S0# SLP_WLAN#

APWROK_R

PBTN_OUT#_R

RH183 10K_0402 _5%

1 2

AUDIO_PWREN KB_BL_DET

PCH_GPIO15

KB_DET# PCH_GPIO17

PCH_GPIO27

NFC_IRQ

MEM_CONFIG0

MEM_CONFIG2 MEM_CONFIG1

SENSOR_HUB_I2C_WAKE

TS_INT# MPHY_PWREN USB0_PWR_EN SENSOR_INT#

TPM_DET

UART_WAKE# EC_RUNTIME_SCI#

NFC_DET# HDA_SPKR

I2C0_SDA

I2C0_SCK

RA7 0_0402_5%@

RA8 0_0402_5%@

R1225 0_ 0402_5%@

R1224 0_ 0402_5%@

PCH_PLTRST#

SSD_PWREN#

1 2

AK2 AC3 AG2 AY7 AB5 AG7

AW6 AV4

AL7 AJ8

AN4

AF3

AM5

PBTN_OUT#_R 18

SSD_PWREN#

P1 AU2 AM7 AD6

T3 AD5 AN5 AD7 AN3

AG6 AP1

AL4

AT5 AK4 AB6

U4 Y3 P3 Y2

AT3 AH4 AM4 AG5 AG3

AM3 AM2

P2 C4 L2 N5 V2

RH424 2.2K_040 2_5%@

RH425 2.2K_040 2_5%@

UCPU1H

SUSACK SYS_RESET SYS_PWROK PCH_PWROK APWROK PLTRST

RSMRST SUSWARN/SUSPWRDNACK/GPIO 30 PWRBTN ACPRESENT/GPIO31 BATLOW/GPIO72 SLP_S0 SLP_WLAN/GPIO 29

SYSTEM POWER MANAGEMENT

PCH Stra p PIN

DSWODVREN

DSWODVREN - On Die DSW VR Enable

H：Enable

L：Disable

U682

IN A

GND

SN74AUP1G04DCKR_SOT 23-5

RH431 0_0402_ 5%@

RH423 100K_040 2_5%

1 2

UCPU1J

BMBUSY/GPIO76 GPIO8 LAN_PHY_PWR_CTRL /GPIO12 GPIO15 GPIO16 GPIO17 GPIO24 GPIO27 GPIO28 GPIO26

GPIO56 GPIO57 GPIO58 GPIO59 GPIO44 GPIO47 GPIO48 GPIO49 GPIO50 HSIOPC/GPIO7 1 GPIO13 GPIO14 GPIO25 GPIO45 GPIO46

GPIO9 GPIO10 DEVSLP0/GPIO33 SDIO_POWER_EN/ GPIO70 DEVSLP1/GPIO38 DEVSLP2/GPIO39 SPKR/GPIO81

1 2

HSW_ULT_DDR3L

GPIO

I2C0_SDA

I2C0_SCK

HSW_ULT_DDR3L

CLKRUN/GPIO3 2

SUS_STAT/GPIO61

8 OF 19

RH147 330K_040 2_5%

RH151 330K_040 2_5%@

+3VS

VCC

OUT Y

CPU/

PCH_OPI_RCO MP

MISC

GSPI0_CS/GPIO 83

GSPI0_CLK/G PIO84 GSPI0_MISO/GPIO 85 GSPI0_MOSI/GPIO 86

GSPI1_CS/GPIO 87

GSPI1_CLK/G PIO88 GSPI1_MISO/GPIO 89

GSPI_MOSI/GPIO9 0

UART0_RXD/GPIO9 1 UART0_TXD/GPIO92

UART0_RTS/GPIO93

SERIAL IO

UART0_CTS/GPIO94

UART1_RXD/GPIO0

UART1_TXD/GPIO1 UART1_RST/GPIO2 UART1_CTS/GPIO3

SDIO_CLK/GPI O64

SDIO_CMD/GPIO6 5

10 OF 1 9

+3VS+3VNS_PWR

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

DSWVRMEN

DPWROK

WAKE

SUSCLK/GPIO62

SLP_S5/GPIO6 3

SLP_S4 SLP_S3

SLP_A SLP_SUS SLP_LAN

+RTCVCC

SSD_PWREN 35

THRMTRIP

RCIN/GPIO82

SERIRQ

RSVD RSVD

I2C0_SDA/GPI O4 I2C0_SCL/G PIO5 I2C1_SDA/GPI O6 I2C1_SCL/G PIO7

SDIO_D0/GPI O66 SDIO_D1/GPI O67 SDIO_D2/GPI O68 SDIO_D3/GPI O69

1 2

RH146 1K_0402_ 5%

PM_CLKRUN# 22,30 SUS_STAT# 22 SUSCLK_R 23, 30 PM_SLP_S5# 18,30

PM_SLP_S4# 18,30,39 PM_SLP_S3# 18,27,30,3 7,38 PM_SLP_A# 18 PM_SLP_SUS# 27,29, 30,34,38

02-0320

AW7

DSWODVREN

AV5

PCH_DPWROK

AJ5

WAKE#

PM_CLKRUN#

AG4

SUS_STAT#

AE6

SUSCLK

AP5

AJ6 AT4 AL5 AP4 AJ7

RH132 0_0402_ 5%@

RH313 0_0402_ 5%@

Deep S3 Support

Non Deep S3 (De-pop RH313)

PM_SLP_S4# PM_SLP_S3#

SUSCLK

WAKE#

WAKE# 23

MC102 1 0P_0402_50 V8J@

Reserve for RF please close to UH1

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

1 2

RH426 1K_0402_ 5%@

1 2

RH415 1K_0402_ 5%@

RH416 1K_0402_ 5%@

1 2

For Power on only, after solder MCP need remove.

MPHY_PWREN

NGFF_PWREN

D60

H_THERMTRIP#_R H_THERMTRIP#

KB_RST#

SERIRQ

AW15

PCH_OPIRCOMP

AF20

Width = 15 mil, Spacing = 12 mil

AB21

Close PCH within 500 mil

NGFF_PWREN

L6 N6 L8

PCH_GPIO86

BT_RADIO_DIS#

L5 N7 K2

SSD_PWREN#

DDR_CHA_EN

DDR_CHB_EN

J2 G1 K4

UART1_RXD

UART1_TXD

UART1_RTS#

UART1_CTS#

I2C0_SDA

I2C0_SCK

G4 F1 E3 F4 D3

SDIO_D0

E4 C3 E2

2011/06/02 2013/10/28

1 2

R1185 10 0K_0402_5 %

R1163 10 0K_0402_5 %

1 2

RC49 0_0 402_5%@

NGFF_PWREN 23 ,27 TPM_PWREN 27

BT_RADIO_DIS# 23

PCH_GPIO88 30 TOUCH_EN 27

LCD_DBC 19

UART1_RXD 23 UART1_TXD 23 UART1_RTS# 23

UART1_CTS# 23

I2C0_SDA 30

I2C0_SCK 30

I2C1_SDA 19

I2C1_SCK 19 SDIO_CLK 23

SDIO_CMD 23

SDIO_D0 23

SDIO_D1 23

SDIO_D2 23

SDIO_D3 23

Compal Secre t Data

Deciphered Date

DDR Memory Configuratino Type Strap pin

+3V_PCH

+3VS

GPIO Pin

PCH_GPIO59

PCH_GPIO48

PCH_GPIO47

+3V_PCH

+3VS

KB_RST# 30 SERIRQ 22,30

RH271 10K_0402 _5%@

RH303 10K_0402 _5%@

RH180 10K_0402 _5%@

Pin Name

MEM_CONFIG0

MEM_CONFIG1

MEM_CONFIG2

+3V_PCH_DSW

SUS_PWR_DN

PCH_DPWROK

PCH DPWROK Option for Deep S3

RH309

02-0320

PCH_GPIO27

WAKE#

PCH_GPIO27

H_THERMTRIP#

0_0402_ 5%

1 2

RH126

0_0402_ 5%

RH310 0_0402_ 5%@

RH128 0_0402_ 5%@

RH427 0_0402_ 5%@

RC149 1K_0402_ 5%

KB_DET#

SERIRQ

KB_RST#

DDR_CHA_EN

DDR_CHB_EN

DDR_CHA_EN

DDR_CHB_EN

PCH_OPIRCOMP

PCH_GPIO86

GPIO86 h ave inte rnal pul l down

Boot BIOS Strap

SDIO_D0

GPIO66 h ave inte rnal pul l down

Top-Bloc k Swap O verride mode

Micron 4G SA00005TH0L

0 1

MEM_CONFIG2

MEM_CONFIG0

MEM_CONFIG1

Hynix 4G

Micron 8G

SA00006JF0L

SA00006FB0L

0 0

Title

P08-MCP(4/7) PM ,GPIO,LPIO,M ISC

Size Document Number Rev

LA-9262P

Date: Sheet of

1 2

RH154 1M_0402_ 5%

1 2

RH401 100K_040 2_5%@

08-0328

5VA_EN 30,34

PCH_RSMRST#_RPCH_DPWROK

+1.05VS_VCCST

1 2

RH302 100K_040 2_5%

RH29 10K_0402 _5%

1 2

RH196 10K_0402 _5%

RH440 100K_040 2_5%

1 2

RH441 100K_040 2_5%

RH442 SHORT PADS@

1 2

RH443 SHORT PADS@

1 2

RC156 49.9_04 02_1%

1 2

RH32 1K_0402_ 5%@

Boot BIOS LocationPCH_GPIO86

SPI

1 2

0 = Enab le

1 = Disa ble

RH314 10K_0402 _5%@

RH316 10K_0402 _5%@

RH315 10K_0402 _5%@

Hynix 8G TBD

Samsung 4G SA00006J30L

RH434 1K_0402_ 5%@

RH435 1K_0402_ 5%@

mpal Electronics, Inc.

+3V_PCH

Deep S3 Support

Non Deep S3

WAKE_PCH# 30

EC_WAKE_SCI# 30

+3VS

+VS_LPSS_SDIO

Samsung 8G SA00006J80L

1 1

8 45Friday, Ap ril 19, 2013

1.0

UCPU1K

F10

PERN5_L0

E10

PERP5_L0

C23

PETN5_L0

PCIE_RCOMP

C22

PETP5_L0

PERN5_L1

PERP5_L1

B23

PETN5_L1

A23

PETP5_L1

H10

PERN5_L2

G10

PERP5_L2

B21

PETN5_L2

C21

PETP5_L2

PERN5_L3

PERP5_L3

B22

PETN5_L3

A21

PETP5_L3

G11

PERN3

F11

PERP3

C29

PETN3

B30

PETP3

F13

PERN4

G13

PERP4

B29

PETN4

A29

PETP4

G17

PERN1/USB3RN3

F17

PERP1/USB3RP3

C30

PETN1/USB3TN3

C31

PETP1/USB3TP3

F15

PERN2/USB3RN4

G15

PERP2/USB3RP4

B31

PETN2/USB3TN4

A31

PETP2/USB3TP4

E15

RSVD

E13

RSVD

A27

PCIE_RCOMP

B27

PCIE_IREF

UCPU1Q

AY2

DAISY_CHAIN_NCTF_AY2

AY3

DAISY_CHAIN_NCTF_AY3

AY60

DAISY_CHAIN_NCTF_AY60

AY61

DAISY_CHAIN_NCTF_AY61

AY62

DAISY_CHAIN_NCTF_AY62

DAISY_CHAIN_NCTF_B2

DAISY_CHAIN_NCTF_B3

B61

DAISY_CHAIN_NCTF_B61

B62

DAISY_CHAIN_NCTF_B62

B63

DAISY_CHAIN_NCTF_B63

DAISY_CHAIN_NCTF_C1

DAISY_CHAIN_NCTF_C2

D D

PCIE_PRX_WLANTX_N323 PCIE_PRX_WLANTX_P323

PCIE_PTX_WLANRX_N323 PCIE_PTX_WLANRX_P323

NGFF

C C

B B

PCIE_PRX_DTX_N423 PCIE_PRX_DTX_P423

PCIE_PTX_DRX_N423 PCIE_PTX_DRX_P423

1 2

CH11 0.1U_0402 _10V7K CH16 0.1U_0402 _10V7K

1 2

CH1237 0.1U_040 2_10V7K

1 2 1 2

CH1238 0.1U_040 2_10V7K

+V1.05S_AUSB3PLL

1 2

RH338 3K_0402_ 1%

Width = 15 mil, Spacing = 15 mil Close PCH within 500 mil

PCIE_PTX_WLANRX_N3_C PCIE_PTX_WLANRX_P3_C

PCIE_PTX_DRX_N4_C PCIE_PTX_DRX_P4_C

DC_TEST_AY2 _AW2 DC_TEST_AY3 _AW3

DC_TEST_AY6 1_AW61 DC_TEST_AY6 2_AW62

DC_TEST_A3 _B3 DC_TEST_A6 1_B61 DC_TEST_B6 2_B63

DC_TEST_C1 _C2

HSW_ULT_DDR3L

PCIE USB

11 OF 1 9

HSW_ULT_DDR3L

17 OF 1 9

USB2N0 USB2P0

USB2N1 USB2P1

USB2N2 USB2P2

USB2N3 USB2P3

USB2N4 USB2P4

USB2N5 USB2P5

USB2N6 USB2P6

USB2N7 USB2P7

USB3RN1 USB3RP1

USB3TN1 USB3TP1

USB3RN2 USB3RP2

USB3TN2 USB3TP2

USBRBIAS

OC0/GPIO4 0 OC1/GPIO4 1 OC2/GPIO4 2 OC3/GPIO4 3

DAISY_CHAIN_NCTF_A3 DAISY_CHAIN_NCTF_A4

DAISY_CHAIN_NCTF_A60 DAISY_CHAIN_NCTF_A61 DAISY_CHAIN_NCTF_A62

DAISY_CHAIN_NCTF_AV1 DAISY_CHAIN_NCTF_AW1 DAISY_CHAIN_NCTF_AW2 DAISY_CHAIN_NCTF_AW3

DAISY_CHAIN_NCTF_AW6 1 DAISY_CHAIN_NCTF_AW6 2 DAISY_CHAIN_NCTF_AW6 3

RSVD RSVD

AN8 AM8

AR7 AT7

AR8 AP8

AR10 AT10

AM15 AL15

AM13 AN13

AP11 AN11

AR13 AP13

G20 H20

C33 B34

E18 F18

B33 A33

AJ10 AJ11 AN10 AM10

AL3 AT1 AH2 AV3

DC_TEST_A3 _B3

A60 A61

DC_TEST_A6 1_B61

A62 AV1 AW1 AW2

DC_TEST_AY2 _AW2

AW3

DC_TEST_AY3 _AW3

AW61

DC_TEST_AY6 1_AW61

AW62

DC_TEST_AY6 2_AW62

AW63

USB20_N0 25 USB20_P0 25

USB20_N1 25 USB20_P1 25

USB20_N2 23 USB20_P2 23

USB20_N3 19 USB20_P3 19

USB20_N4 19 USB20_P4 19

USB20_N5 22 USB20_P5 22

USB3RN0 25 USB3RP0 25

USB3TN0 25

USB3TP0 25

USB3RN1 25 USB3RP1 25

USB3TN1 25

USB3TP1 25

Within 450 mils

1 2

USBRBIAS

RH163

22.6_04 02_1%

USB_OC0# USB_OC1# USB_OC2# USB1_PWR_EN

closed MCP 2000 mils

USB_OC0# USB_OC1# USB_OC2# USB1_PWR_EN

USB3.0 (Power Share)

USB3.0 (Power Share) Debug Port

NGFF (WLAN)

Touch Panel

Camera

Sensors HUB

Net USB_BIAS route impedacnes should be 50-ohm and length less than 4 50-mil spacing is 15-mil.

USB_OC0# 25 USB_OC1# 25

USB1_PWR_EN 25

T289@ T290@ T291@ T292@

USB_OC2# USB_OC0# USB_OC1# USB1_PWR_EN

RP11

1 8 2 7 3 6 4 5

10K_8P4R_5 %

+3V_PCH

UCPU1R

AT2

RSVD

AU44

RSVD

AV44

RSVD

D15

RSVD

F22

RSVD

H22

RSVD

J21

RSVD

A A

HSW_ULT_DDR3L

18 OF 1 9

N23

RSVD

R23

RSVD

T23

RSVD

U10

RSVD

AL1

RSVD

AM11

RSVD

AP7

RSVD

AU10

RSVD

AU15

RSVD

AW14

RSVD

AY14

RSVD

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

2011/06/02 2013/10/28

Compal Secre t Data

Deciphered Date

mpal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

P09-MCP(5/7) PCIE,USB

LA-9262P

9 45Friday, Ap ril 19, 2013

1.0

+1.35V_DDR

10U_060 3_6.3V6M

D D

2.2U_040 2_6.3V6M

+1.05VS_VCCST

RC93 75_0402 _5%

RC95 130_040 2_1%

VIDSOUT: Requires a pull-up to VCCIO through a pull-up res istor of 110 ±5% clos e to the processo r, and a pull-up to VCCIO through a pull-up resis tor of 110 ±5% close to Intel MVP 7. VIDSCLK: Required pul l-up to VCCIO through 55 ±5% close to Intel IMVP 7.

C C

+1.05VDX_MODPHY

B B

+1.05VS

+1.05VDX_MODPHY

Deep S3 Support

+3V_PCH

A A

Non Deep S3

1 2

R1240 0_1206_ 5%

LH10

1 2

2.2UH_LQM21PN2R2MC0D_2 0%

22U_0805_6 .3V6M

LH12

1 2

2.2UH_LQM2MPN2R2NG0L_30% CH1212

100U_A_6.3V_ R70M

LH11

1 2

2.2UH_LQM21PN2R2MC0D_2 0%

22U_0805_6 .3V6M

RH348

1 2

+3VALW

0_0402_ 5%

RH351

1 2

0_0603_ 5%

1U_0402_6. 3V6K

+1.05VS +1.05VS

RH355

1 2

+V1.05S_AXCK_DCB_L +V1.05S_AXCK_LCPLL _L

0_0402_ 5%

10U_060 3_6.3V6M

160

161

2.2U_040 2_6.3V6M

238

233

close to CPU

1 2

CH1208

22U_0805_6 .3V6M

+V1.05S_APLLO PI

1U_0402_6. 3V6K

CH1210

22U_0805_6 .3V6M

02-0320

1224

2.2UH_LQM2MPN2R2NG0L_30%

CC163

CC 162

2.2U_040 2_6.3V6M

CC234

239

+V1.05VS_VCCHSIO

40 CH

1U_0402 _6.3V6K

+V1.05S_AUSB3PLL+1.05VDX_MODPHY

CH1209

CH1213

+V1.05S_ASATA3 PLL

CH1211

+3V_PCH_DSW

L61

1 2

1228

100U_A_6.3V_ R70M

10U_060 3_6.3V6M

CC 164

H_CPU_SVIDALRT#

H_CPU_SVIDDAT

+V1.05S_AXCK_DCB

CC165

41 CH

1U_0402 _6.3V6K

+1.5VS_3.3VS_ AUDIO

+1.05VA

22U_0603_6 .3V6M

1U_0402_6. 3V6K

+1.05VS

+1.5VS_3.3VS_ AUDIO

CH85 1U_0402_6. 3V6K

CH1239 10U_0603_6 .3V6M

+3V_PCH

CH1220

+1.05VS

CH1234

1229

SIP

RH340

1 2

0_0805_ 5%

02-0320

CH1214 1U_0402_6. 3V6K

22U_0603_6 .3V6M

+V1.05S_AXCK_LCPLL

1U_0402_6. 3V6K

RH356

1 2

0_0402_ 5%

1U_0402_6. 3V6K

+3VS

+1.05VS

IMVP_VR_PG29,40

+VCCIO_OUT

CH1204 22U_0603_6 .3V6M

CH39

RH405

1 2

0_0603_ 5%

CH1225

CH1235

2.2UH_LQM2MPN2R2NG0L_30%

+1.05VS

CH1241

0.1U_0402_ 10V7K

VR_SVID_ALRT#40

1.05VS_VCCST _PG18,29

+1.05VS_VCCST

+V1.05VS_VCCHSIO

+V1.05S_AUSB3PLL

+V1.05S_ASATA3 PLL

+V1.05S_APLLO PI

+V1.05A_DCPSUS

+1.5VS_3.3VS_ AUDIO

+3V_PCH_DSW

+V1.05S_AXCK_DCB

+V1.05S_AXCK_LCPLL

L62

1 2

100U_1206_ 6.3V6M

+1.05VS_VCCST

VR_SVID_CLK40 VR_SVID_DAT40

VR_ON30,40

+1.05VS_VCCST

CH1205 1U_0402_6. 3V6K

1230

VR_ON

R1211 1M_0402_ 5%

IMVP_VR_PG

VCCSENSE40

AA21

AH14

AH13

AH10

AE20 AE21

+V1.05S_AXCK_LCPLL

R1241

1K_0402_ 5%

+VCC_CORE

RC97 & R C98 clos e to PCH

1 2

RC97 100_040 2_1% RC98 0_0402_ 5%@

1 2

+VCCIO_OUT +VCCIOA_OUT

1 2

RC94 43_0402 _5%

1 2

RC92 0_0402_ 5%@ RC96 0_0402_ 5%@

1 2 1 2

RC150 0_ 0402_5%@

1 2

RC151 0_ 0402_5%@

R1179

1 2

150_040 2_5%

1231

RC152 0_ 0402_5%@

1 2

FIVE_EN

GPIO/LPC

LPT LP POWER

HSIO

OPI

USB3

HDA

VRM

FIVE_EN18

HSW_ULT_DDR3L

+1.05VS_VCCST

+VCC_CORE

OF 19

IMVP_VR_PG

UCPU1M

VCCHSIO

L10

VCCHSIO

VCC1_05

B18

VCCUSB3PLL

B11

VCCSATA3PLL

Y20

RSVD VCCAPLL

W21

VCCAPLL

J13

DCPSUS3

VCCHDA

DCPSUS2

AC9

VCCSUS3_3

AA9

VCCSUS3_3 VCCDSW3_3

VCC3_3

J18

VCCCLK

K19

VCCCLK

A20

VCCACLKPLL

J17

VCCCLK

R21

VCCCLK

T21

VCCCLK

K18

RSVD

M20

RSVD

V21

RSVD VCCSUS3_3 VCCSUS3_3

DCPSUS c an be NC , if INT VRMEN pul l up to enabl e Integr ated VRM

1U_0402_6. 3V6K

+1.35V_DDR

4.2A

+VCC_CORE

VCCSENSE_R

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT VCCSTPG_MCP VR_ON_MCPVR_ON VRPG_MCP

FIVE_EN

RTC

SPI

CORE

THERMAL SENSOR

SERIAL IO

SUS OSCILLATOR

USB2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

AH26

AJ31 AJ33

AJ37 AN33 AP43 AR48 AY35 AY40 AY44 AY50

AC58

AB23

AD23 AA23 AE59

AD60 AD59 AA59 AE60 AC59

AG58

AC22 AE22 AE23

AB57 AD57

AG57

VCCSUS3_3

VCCRTC DCPRTC

VCCSPI

VCCASW VCCASW

VCC1_05 VCC1_05 VCC1_05 VCC1_05

VCC1_05 DCPSUSBYP DCPSUSBYP

VCCASW

DCPSUS1 DCPSUS1

VCCTS1_5

VCC3_3 VCC3_3

VCCSDIO

DCPSUS4

RSVD VCC1_05 VCC1_05

UCPU1L

L59

RSVD

J58

RSVD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

F59

VCC

N58

RSVD RSVD

E63

VCC_SENSE RSVD

A59

VCCIO_OUT

E20

VCCIOA_OUT RSVD RSVD RSVD

L62

VIDALERT

N63

VIDSCLK

L63

VIDSOUT

B59

VCCST_PWRGD

F60

VR_EN

C59

VR_READY

D63

VSS

H59

PWR_DEBUG

P62

VSS

P60

RSVD_TP

P61

RSVD_TP

N59

RSVD_TP

N61

RSVD_TP

T59

RSVD RSVD RSVD RSVD RSVD RSVD RSVD

U59

RSVD

V59

RSVD

VCCST VCCST VCCST

VCC VCC VCC

C24

VCC

C28

VCC

C32

VCC

AH11 AG10 AE7

CH1206 0.1U_040 2_10V7K

AG14 AG13

J11 H11 H15 AE8 AF22 AG19 AG20 AE9 AF9 AG8 AD10 AD8

J15 K14 K16

U8 T9

AB8

AC20 AG16 AG17

HSW_ULT_DDR3L

HSW ULT POWER

12 OF 1 9

+1.05VS

+1.5VS

CH1233 1U_0402_6. 3V6K

+RTCVCC

RH346

1 2

0_0402_ 5%

+1.05VS

Compal Secre t Data

+RTC_VCCSUS

1 2

review f eedback change t o 0 ohm

+PCH_VCCDSW

+V1.05A_DCPSUS

+VS_LPSS_SDIO

+V1.05A_AOSCSUS

2011/06/02 2013/10/28

+3VS

CH47

0.1U_0402_ 10V7K

1 2

1U_0402_6. 3V6K

+3VS

CH1226

0.1U_0402_ 10V7K

+RTC_VCCSUS

Deciphered Date

CH1218

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

CH1215

1U_0402_6. 3V6K

CH1222 1U_0402_6. 3V6K

+VCC_CORE

C36 C40 C44 C48 C52 C56 E23 E25 E27 E29 E31 E33 E35 E37 E39 E41 E43 E45 E47 E49 E51 E53 E55 E57 F24 F28 F32 F36 F40 F44 F48 F52 F56 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 H23 J23 K23 K57 L22 M23 M57 P57 U57 W57

0_0402_ 5%

CH1207 1U_0402_6. 3V6K

closed t o VCC1P0 5

CH1216

1U_0402_6. 3V6K

+1.05VS

CH1223 22U_0603_6 .3V6M

SIP

+3V_PCH

RH341

1.05A_AOSCSUS

CH1232

1U_0402_6. 3V6K

+1.05VS

CH1217

10U_0603_6 .3V6M

closed t o VCCRTC

CH84

1U_0402_6. 3V6K

0.1U_0402_ 10V7K

02-0320

+VS_LPSS_SDIO

L63

1 2

2.2UH_LQM2MPN2R2NG0L_30%

CH1240

100U_A_6.3V_ R70M

Title

P10-MCP(6/7) PW R,VCC

Size Document Number Rev

LA-9262P

Date: Sheet of

mpal Electronics, Inc.

CH83

RH350

1 2

0_0603_ 5%

RH354

1 2

0_0603_ 5%

CH1227 1U_0402_6. 3V6K

1.05A_AOSCSUS_L

0.1U_0402_ 10V7K

1 2

0_0603_ 5%

10 45Frida y, April 19, 20 13

CH82

+1.8VS

+3VS

RH406

+RTCVCC

+1.05VA

1.0

closed MCP 1000 mils

D D

CFG4

RC811K_0402_ 5%

eDP Strap

1 : Disa bled; No Physica l Display Port attached to Embe dded Dis play Port

CFG4

0 : Enab led; An external Display

Port dev ice is c onnected to the Embedded Display Port

RC15349.9_04 02_1%

CFG_RCOMP

PROC_OPI_COMP

RC15449.9_04 02_1%

TD_IREF TD_IREF

RC1558.2K_0 402_1%

Width = 15 mil, Spacing = 15 mil Close PCH within 500 mil

C C

HSW_ULT_DDR3L

UCPU1N

A11

VSS

A14

VSS

A18

VSS

A24

VSS

A28

VSS

A32

VSS

A36

VSS

A40

VSS

A44

VSS

A48

VSS

A52

VSS

A56

VSS

AA1

VSS

AA58

VSS

AB10

VSS

AB20

VSS

AB22

VSS

AB7

VSS

AC61

VSS

AD21

VSS

B B

A A

AD3

VSS

AD63

VSS

AE10

VSS

AE5

VSS

AE58

VSS

AF11

VSS

AF12

VSS

AF14

VSS

AF15

VSS

AF17

VSS

AF18

VSS

AG1

VSS

AG11

VSS

AG21

VSS

AG23

VSS

AG60

VSS

AG61

VSS

AG62

VSS

AG63

VSS

AH17

VSS

AH19

VSS

AH20

VSS

AH22

VSS

AH24

VSS

AH28

VSS

AH30

VSS

AH32

VSS

AH34

VSS

AH36

VSS

AH38

VSS

AH40

VSS

AH42

VSS

AH44

VSS

AH49

VSS

AH51

VSS

AH53

VSS

AH55

VSS

AH57

VSS

AJ13

VSS

AJ14

VSS

AJ23

VSS

AJ25

VSS

AJ27

VSS

AJ29

VSS

14 OF 1 9

AJ35

VSS

AJ39

VSS

AJ41

VSS

AJ43

VSS

AJ45

VSS

AJ47

VSS

AJ50

VSS

AJ52

VSS

AJ54

VSS

AJ56

VSS

AJ58

VSS

AJ60

VSS

AJ63

VSS

AK23

VSS

AK3

VSS

AK52

VSS

AL10

VSS

AL13

VSS

AL17

VSS

AL20

VSS

AL22

VSS

AL23

VSS

AL26

VSS

AL29

VSS

AL31

VSS

AL33

VSS

AL36

VSS

AL39

VSS

AL40

VSS

AL45

VSS

AL46

VSS

AL51

VSS

AL52

VSS

AL54

VSS

AL57

VSS

AL60

VSS

AL61

VSS

AM1

VSS

AM17

VSS

AM23

VSS

AM31

VSS

AM52

VSS

AN17

VSS

AN23

VSS

AN31

VSS

AN32

VSS

AN35

VSS

AN36

VSS

AN39

VSS

AN40

VSS

AN42

VSS

AN43

VSS

AN45

VSS

AN46

VSS

AN48

VSS

AN49

VSS

AN51

VSS

AN52

VSS

AN60

VSS

AN63

VSS

AN7

VSS

AP10

VSS

AP17

VSS

AP20

VSS

CFG3

T293@

CFG018 CFG118 CFG218

CFG3

CFG318

CFG4

CFG418 CFG518 CFG618 CFG718 CFG818 CFG918 CFG1018 CFG1118 CFG1218 CFG1318 CFG1418 CFG1518

CFG1618 CFG1818 CFG1718 CFG1918

CFG_RCOMP

UCPU1O

AP22

VSS

AP23

VSS

AP26

VSS

AP29

VSS

AP3

VSS

AP31

VSS

AP38

VSS

AP39

VSS

AP48

VSS

AP52

VSS

AP54

VSS

AP57

VSS

AR11

VSS

AR15

VSS

AR17

VSS

AR23

VSS

AR31

VSS

AR33

VSS

AR39

VSS

AR43

VSS

AR49

VSS

AR5

VSS

AR52

VSS

AT13

VSS

AT35

VSS

AT37

VSS

AT40

VSS

AT42

VSS

AT43

VSS

AT46

VSS

AT49

VSS

AT61

VSS

AT62

VSS

AT63

VSS

AU1

VSS

AU16

VSS

AU18

VSS

AU20

VSS

AU22

VSS

AU24

VSS

AU26

VSS

AU28

VSS

AU30

VSS

AU33

VSS

AU51

VSS

AU53

VSS

AU55

VSS

AU57

VSS

AU59

VSS

AV14

VSS

AV16

VSS

AV20

VSS

AV24

VSS

AV28

VSS

AV33

VSS

AV34

VSS

AV36

VSS

AV39

VSS

AV41

VSS

AV43

VSS

AV46

VSS

AV49

VSS

AV51

VSS

AV55

VSS

AC60 AC62 AC63 AA63 AA60

Y62 Y61 Y60 V62 V61 V60 U60 T63 T62 T61 T60

AA62

U63

AA61

U62

V63

D1 J20 H18 B12

HSW_ULT_DDR3L

15 OF 1 9

UCPU1S

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG18 CFG17 CFG19

CFG_RCOMP

RSVD

RSVD RSVD RSVD RSVD TD_IREF

HSW_ULT_DDR3L

AV63

RSVD_TP

AU63

RSVD_TP

C63

RSVD_TP

C62

RSVD_TP

B43

RSVD

A51

RSVD_TP

B51

RSVD_TP

L60

RESERVED

19 OF 1 9

AV59

VSS

AV8

VSS

AW16

VSS

AW24

VSS

AW33

VSS

AW35

VSS

AW37

VSS

AW4

VSS

AW40

VSS

AW42

VSS

AW44

VSS

AW47

VSS

AW50

VSS

AW51

VSS

AW59

VSS

AW60

VSS

AY11

VSS

AY16

VSS

AY18

VSS

AY22

VSS

AY24

VSS

AY26

VSS

AY30

VSS

AY33

VSS

AY4

VSS

AY51

VSS

AY53

VSS

AY57

VSS

AY59

VSS

AY6

VSS

B20

VSS

B24

VSS

B26

VSS

B28

VSS

B32

VSS

B36

VSS

B40

VSS

B44

VSS

B48

VSS

B52

VSS

B56

VSS

B60

VSS

C11

VSS

C14

VSS

C18

VSS

C20

VSS

C25

VSS

C27

VSS

C38

VSS

C39

VSS

C57

VSS

D12

VSS

D14

VSS

D18

VSS

D21

VSS

D23

VSS

D25

VSS

D26

VSS

D27

VSS

D29

VSS

D30

VSS

D31

VSS

RSVD_TP

N60

RSVD

W23

RSVD

Y22

RSVD

AY15

PROC_OPI_RC OMP

RSVD RSVD

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

PROC_OPI_COMP

AV62 D58

P22

VSS

N21

VSS

P20 R20

HSW_ULT_DDR3L

UCPU1P

D33

VSS

D34

VSS

D35

VSS

D37

VSS

D38

VSS

D39

VSS

D41

VSS

D42

VSS

D43

VSS

D45

VSS

D46

VSS

D47

VSS

D49

VSS

D50

VSS

D51

VSS

D53

VSS

D54

VSS

D55

VSS

D57

VSS

D59

VSS

D62

VSS

E11

VSS

E17

VSS

F20

VSS

F26

VSS

F30

VSS

F34

VSS

F38

VSS

F42

VSS

F46

VSS

F50

VSS

F54

VSS

F58

VSS

F61

VSS

G18

VSS

G22

VSS

H13

VSS

16 OF 1 9

2011/06/02 2013/10/28

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS

VSS_SENSE

VSS

Compal Secre t Data

H17 H57 J10 J22 J59 J63 K1 K12 L13 L15 L17 L18 L20 L58 L61 L7 M22 N10 N3 P59 P63 R10 R22 R8 T1 T58 U20 U22 U61 U9 V10 V3 V7 W20 W22 Y10 Y59 Y63

V58 AH46 V23 E62 AH16

Deciphered Date

VSSSENSE_R

RC99 & R C100 clo se to PC H

1 2

RC99 0_0402_ 5%@ RC100 100_040 2_1%

1 2

VSSSENSE 40

mpal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

P11-MCP(7/7) PW R,VSS,CFG

LA-9262P

11 45Frida y, April 19, 20 13

1.0

follow INTEL PDG

CD1 .047U_0402 _16V7K

CD2 .047U_0402 _16V7K

1 2

CD3 .047U_0402 _16V7K

CD4 .047U_0402 _16V7K

D D

DDR_A_DQS#[0 ..7]6 ,13

DDR_A_DQS[0. .7]6,1 3

DDR_A_D[0..6 3]6,13

DDR_A_MA[0..15 ]6,13,16

All VREF traces should have 10 mil trace width

C C

B B

1 2

PLACE TH ESE CAPS NEAR TO RESPECTI VE DIMM PINS

+VREFCA

+VREFDQ_A

DDR3_DRAMRST#5 ,13,14,15

CAD NOTE : PLACE TH E CAP NE AR TO SDRAM RE SET PIN

CD5

0.1U_0402_ 25V6

+VREFCA +VREFDQ_A

DDR_A_BS06,13 ,16 DDR_A_BS16,13 ,16 DDR_A_BS26,13 ,16

M_CLK_A_DDR06 ,13,16 M_CLK_A_DDR#06,13 ,16

DDR_A_CKE06,13,16 DDR_A_CKE16,13,16 M_ODT013,16

DDR_A_CS0#6,13,16 DDR_A_CS1#6,13,16

DDR_A_RAS#6,13,16 DDR_A_CAS#6,13,16 DDR_A_WE#6,13,1 6

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

M_CLK_A_DDR0 M_CLK_A_DDR#0

DDR_A_CKE0 DDR_A_CKE1 M_ODT0

DDR_A_CS0# DDR_A_CS1#

DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

DDR_A_DQS0 DDR_A_DQS1

DDR_A_DQS#0 DDR_A_DQS#1

DDR3_DRAMRST#

RD1 240_0402_ 1%

RD79 240_040 2_1%

UD1

VREFCA

VREFDQ

A10/AP

A11

A12/BC#

A13

A14

A15/NC

BA0

BA1

BA2

CK#

CKE0

CKE1/NC

ODT0

ODT1/NC

CS0#

CS1#/NC

RAS#

CAS#

WE#

DQSL

DQSU

DQSL#

DQSU#

DML

DMU

RESET#

ZQ0

ZQ1/NC

MT41K256M16 HA-125M:E_FBGA96

96-BALL SDRAM DDR3L

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

UD2

DDR_A_D6

DDR_A_D0

DDR_A_D2

DDR_A_D5

DDR_A_D3

DDR_A_D4

DDR_A_D7

DDR_A_D1

DDR_A_D13

DDR_A_D15

DDR_A_D12

DDR_A_D14

DDR_A_D8

DDR_A_D11

DDR_A_D9

DDR_A_D10

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

+1.35V_DDR +1.35V_DDR

+VREFCA +VREFDQ_A

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

M_CLK_A_DDR0 M_CLK_A_DDR#0

DDR_A_CKE0 DDR_A_CKE1 M_ODT0

DDR_A_CS0# DDR_A_CS1#

DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

DDR_A_DQS2 DDR_A_DQS3

DDR_A_DQS#2 DDR_A_DQS#3

DDR3_DRAMRST#

RD2 240_0402_1%

RD80 2 40_0402_1 %

VREFCA

VREFDQ

A10/AP

A11

A12/BC#

A13

A14

A15/NC

BA0

BA1

BA2

CK#

CKE0

CKE1/NC

ODT0

ODT1/NC

CS0#

CS1#/NC

RAS#

CAS#

WE#

DQSL

DQSU

DQSL#

DQSU#

DML

DMU

RESET#

ZQ0

ZQ1/NC

96-BALL SDRAM DDR3L

MT41K256M16 HA-125M:E_FBGA96

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

DDR_A_D18

DDR_A_D16

DDR_A_D22

DDR_A_D21

DDR_A_D19

DDR_A_D20

DDR_A_D23

DDR_A_D17

DDR_A_D29

DDR_A_D27

DDR_A_D28

DDR_A_D26

DDR_A_D24

DDR_A_D31

DDR_A_D25

DDR_A_D30

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

+1.35V_DDR

1U_0402 _6.3V6K

A A

1U_0402 _6.3V6K

CD15

1U_0402 _6.3V6K

CD18

10U_060 3_6.3V6M

1U_0402 _6.3V6K

CD 20

10U_060 3_6.3V6M

1U_0402 _6.3V6K

CD111

10U_060 3_6.3V6M

113

Issued Date

114

CD22 330U_B2_2VM_R1 5M

2011/06/02 2013/10/28

CD 112

Security Classification

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

Memory Channel A SPD EEPROM

+3VS

PCH_SMBCLK7,14 ,18,19 PCH_SMBDATA7,14,18, 19

Compal Secre t Data

Deciphered Date

8 7 6 5

AT24C02C -XHM-T_ TSSOP8

VCC

SCL

GND4SDA

RD3 1K_0402_ 5%@

12 12

RD4 1K_0402_ 5%@

mpal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

P12-DD RIII Channel_A Lower

LA-9262P

+3VS

CD23

0.1U_0402_ 10V7K

12 45Frida y, April 19, 20 13

1.0

follow INTEL PDG

CD24 .047U_04 02_16V7K

CD25 .047U_04 02_16V7K

CD26 .047U_04 02_16V7K

D D

DDR_A_DQS#[0 ..7]6 ,12

DDR_A_DQS[0. .7]6,1 2

DDR_A_D[0..6 3]6,12

DDR_A_MA[0..15 ]6,12,16

All VREF traces should have 10 mil trace width

C C

B B

1 2

CD27 .047U_04 02_16V7K

ACE THES E CAPS

NEAR TO RESPECTI VE DIMM PINS

+VREFCA

+VREFDQ_A

DDR3_DRAMRST#5 ,12,14,15

CAD NOTE : PLACE TH E CAP NE AR TO SDRAM RE SET PIN

UD4

+VREFCA +VREFCA

CD28

0.1U_0402_ 25V6

+VREFDQ_A

DDR_A_BS06,12 ,16 DDR_A_BS16,12 ,16 DDR_A_BS26,12 ,16

M_CLK_A_DDR06 ,12,16 M_CLK_A_DDR#06,12 ,16

DDR_A_CKE06,12,16 DDR_A_CKE16,12,16 M_ODT012,16

DDR_A_CS0#6,12,16 DDR_A_CS1#6,12,16

DDR_A_RAS#6,12,16 DDR_A_CAS#6,12,16 DDR_A_WE#6,12,1 6

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 DDR_A_MA15

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

M_CLK_A_DDR0 M_CLK_A_DDR#0

DDR_A_CKE0 DDR_A_CKE1 M_ODT0

DDR_A_CS0# DDR_A_CS1#

DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

DDR_A_DQS4 DDR_A_DQS5

DDR_A_DQS#4 DDR_A_DQS#5

DDR3_DRAMRST#

RD5 240_0402_ 1%

RD81 240_040 2_1%

VREFCA

VREFDQ

A10/AP

A11

A12/BC#

A13

A14

A15/NC

BA0

BA1

BA2

CK#

CKE0

CKE1/NC

ODT0

ODT1/NC

CS0#

CS1#/NC

RAS#

CAS#

WE#

DQSL

DQSU

DQSL#

DQSU#

DML

DMU

RESET#

ZQ0

ZQ1/NC

96-BALL SDRAM DDR3L

MT41K256M16 HA-125M:E_FBGA96

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

DDR_A_D39 DDR_A_D37 DDR_A_D34 DDR_A_D32 DDR_A_D35 DDR_A_D33 DDR_A_D38 DDR_A_D36

DDR_A_D44 DDR_A_D47 DDR_A_D45 DDR_A_D46 DDR_A_D41 DDR_A_D42 DDR_A_D40 DDR_A_D43

+1.35V_DDR +1.35V_DDR

+VREFDQ_A

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

M_CLK_A_DDR0 M_CLK_A_DDR#0

DDR_A_CKE0 DDR_A_CKE1 M_ODT0

DDR_A_CS0# DDR_A_CS1#

DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

DDR_A_DQS6 DDR_A_DQS7

DDR_A_DQS#6 DDR_A_DQS#7

DDR3_DRAMRST#

RD6 240_0402_ 1%

RD82 240_040 2_1%

UD5

VREFCA

VREFDQ

A7 A8 A9 A10/AP A11 A12/BC# A13 A14 A15/NC

BA0 BA1 BA2

CK CK#

CKE0 CKE1/NC ODT0 ODT1/NC CS0# CS1#/NC

RAS# CAS# WE#

DQSL DQSU

DQSL# DQSU#

DML DMU

RESET#

ZQ0

ZQ1/NC

96-BALL SDRAM DDR3L

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

T8 R3 L7 R7 N7 T3 T7

J1 L2 L1

J3 K3 L3

F3 C7

E7 D3

MT41K256M16 HA-125M:E_FBGA96

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DDR_A_D55

DDR_A_D53

DDR_A_D54

DDR_A_D51

DDR_A_D49

DDR_A_D52

DDR_A_D48

DDR_A_D50

DDR_A_D62

DDR_A_D57

DDR_A_D63

DDR_A_D56

DDR_A_D59

DDR_A_D61

DDR_A_D58

DDR_A_D60

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

+1.35V_DDR

1U_0402 _6.3V6K

A A

1U_0402 _6.3V6K

CD39

1U_0402 _6.3V6K

CD41

10U_060 3_6.3V6M

1U_0402 _6.3V6K

CD43

10U_060 3_6.3V6M

1U_0402 _6.3V6K

115

10U_060 3_6.3V6M

CD116

117

118

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

2011/06/02 2013/10/28

Compal Secre t Data

Deciphered Date

mpal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

P13-DD RIII Channel_A U pper

LA-9262P

13 45Frida y, April 19, 20 13

1.0

follow INTEL PDG

CD45 .047U_04 02_16V7K

CD46 .047U_04 02_16V7K

CD47 .047U_04 02_16V7K

D D

DDR_B_DQS#[0 ..7]6,15

DDR_B_DQS[0. .7]6,15

DDR_B_D[0..6 3]6 ,15

DDR_B_MA[0..15 ]6,15,16

All VREF traces should have 10 mil trace width

C C

B B

1 2

CD48 .047U_04 02_16V7K

PLACE TH ESE CAPS NEAR TO RESPECTI VE DIMM PINS

+VREFCA

+VREFDQ_B

DDR3_DRAMRST#5,12,13, 15

CAD NOTE : PLACE TH E CAP NE AR TO SDRAM RE SET PIN

CD49

0.1U_0402_ 25V6

+VREFCA +VREFDQ_B

DDR_B_BS06,15,1 6 DDR_B_BS16,15,1 6 DDR_B_BS26,15,1 6

M_CLK_B_DDR06,1 5,16 M_CLK_B_DDR#06,15,16

DDR_B_CKE06,1 5,16 DDR_B_CKE16,1 5,16 M_ODT21 5,16

DDR_B_CS0#6,15,16 DDR_B_CS1#6,15,16

DDR_B_RAS#6,1 5,16 DDR_B_CAS#6,1 5,16 DDR_B_WE#6,15,16

UD6

VREFCA

VREFDQ

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 DDR_B_MA15

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

M_CLK_B_DDR0 M_CLK_B_DDR#0

DDR_B_CKE0 DDR_B_CKE1 M_ODT2

DDR_B_CS0# DDR_B_CS1#

DDR_B_RAS# DDR_B_CAS# DDR_B_WE#

DDR_B_DQS2 DDR_B_DQS3

DDR_B_DQS#2 DDR_B_DQS#3

RD7 240_0402_ 1%

RD83 240_040 2_1%

A10/AP

A11

A12/BC#

A13

A14

A15/NC

BA0

BA1

BA2

CK#

CKE0

CKE1/NC

ODT0

ODT1/NC

CS0#

CS1#/NC

RAS#

CAS#

WE#

DQSL

DQSU

DQSL#

DQSU#

DML

DMU

RESET#

ZQ0

ZQ1/NC

96-BALL SDRAM DDR3L

MT41K256M16 HA-125M:E_FBGA96

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

DDR_B_D22 DDR_B_D21 DDR_B_D18 DDR_B_D17 DDR_B_D23 DDR_B_D16 DDR_B_D19 DDR_B_D20

DDR_B_D30 DDR_B_D26 DDR_B_D29 DDR_B_D27 DDR_B_D25 DDR_B_D28 DDR_B_D24 DDR_B_D31

+1.35V_DDR +1.35V_DDR

+VREFCA +VREFDQ_B

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

M_CLK_B_DDR0 M_CLK_B_DDR#0

DDR_B_CKE0 DDR_B_CKE1 M_ODT2

DDR_B_CS0# DDR_B_CS1#

DDR_B_RAS# DDR_B_CAS# DDR_B_WE#

DDR_B_DQS0 DDR_B_DQS1

DDR_B_DQS#0 DDR_B_DQS#1

DDR3_DRAMRST#DDR3_DRAMRST#

RD8 240_0402_ 1%

RD84 240_040 2_1%

UD7

VREFCA

VREFDQ

A7 A8 A9 A10/AP A11 A12/BC# A13 A14 A15/NC

BA0 BA1 BA2

CK CK#

CKE0 CKE1/NC ODT0 ODT1/NC CS0# CS1#/NC

RAS# CAS# WE#

DQSL DQSU

DQSL# DQSU#

DML DMU

RESET#

ZQ0

ZQ1/NC

96-BALL SDRAM DDR3L

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

3 L7 R7 N7 T3 T7

7 K7

J1 L2 L1

J3 K3 L3

F3 C7

E7 D3

MT41K256M16 HA-125M:E_FBGA96

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

DDR_B_D7

DDR_B_D1

DDR_B_D3

DDR_B_D5

DDR_B_D6

DDR_B_D4

DDR_B_D2

DDR_B_D0

DDR_B_D8

DDR_B_D12

DDR_B_D15

DDR_B_D14

DDR_B_D13

DDR_B_D10

DDR_B_D9

DDR_B_D11

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

+1.35V_DDR

1U_0402 _6.3V6K

A A

1U_0402 _6.3V6K

CD59

1U_0402 _6.3V6K

CD62

10U_060 3_6.3V6M

1U_0402 _6.3V6K

10U_060 3_6.3V6M

1U_0402 _6.3V6K

10U_060 3_6.3V6M

CD119

120

121

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CO NTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE C USTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

CD66

122

330U_B2_2VM_R1 5M

2011/06/02 2013/10/28

Memory Channel B SPD EEPROM

PCH_SMBCLK7,12 ,18,19 PCH_SMBDATA7,12,18, 19

Compal Secre t Data

Deciphered Date

+3VS

VCC

SCL

GND4SDA

AT24C02C -XHM-T_ TSSOP8

+3VS

RD9 1K_040 2_5%@

2 3

12 12

RD10 1K_0402_5%@

mpal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

P14-DD RIII Channel_B Lower

LA-9262P

+3VS

CD67

0.1U_0402_ 10V7K

1.0

14 45Frida y, April 19, 20 13

1.0

+ 32 hidden pages

Compal LA-9262P VAZA0, XPS 12 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual