Compal LA-9241P Viper MXM, ZBook 15 Schematic

A

1 1

B

C

D

E

Compal Confidential

2 2

Intel Haswell rPGA Processor with Lynx Point-H

Viper MXM

Date : 2012/12/20

Version 0.5

3 3

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2011/06/29 2011/06/29

2011/06/29 2011/06/29

2011/06/29 2011/06/29

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

Cover Page

Cover Page

LA-9241P

LA-9241P

LA-9241P

E

0.5

0.5

1 56Thursday, December 20, 2012

1 56Thursday, December 20, 2012

1 56Thursday, December 20, 2012

0.5

A

B

C

D

E

Compal Confidential

Model Name :

File Name :

1 1

LVDS Panel Conn.

eDP to LVDS
RTD 2136

Page 39

Dock Conn DPD

Page 33

eDP Panel Conn.

DP MUX
PS8338

Page 36

Page 22

DPC

DPE

eDP DeMUX

Page 36

PS8321

eDPFDP Conn

MXM3.0 Conn
AMD:
nVidia:

Page 35

CRT

CRT

CRT

VGA Switch
2 to 2
MAX14885EETL

Page 33

PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)

Port 1

ODD
Conn.

Page 23 Page 23Page 23

TPM1.2

Infineon SLB9656/9635

Page 28

SMBus (PCH)

Page 36Page 36

mSATA
Conn.

Touch Pad

Port 6

Dock Conn

VGA Conn

Port 7

WLAN
(MINI card)

Page 25Page 39

Port 13

Page 32

2 2

3 3

Mini DP Conn.

Port 8

Card Reader

Controller

Page 39

SD/MMC Slot

Accelerometer
ST HP3DC2

CPU FAN1 conn.

Page 28

Page 24

GLAN
Intel
Clarkville

RJ45 Conn.

Page 29

Page 29

ThunderBolt
Cactus Ridge

Page 39

X4

Expresscard

SMSC LPC47N217

Port 5Port 6

Super I/O

Touch pad daughter board

4 4

RTC CKT.

Page 13

PEGx16

SATAx4

Port 2

(GEN1 1.5Gb/S
GEN2 3Gb/S
GEN3 6Gb/S)

USB 2.0 Bus

KBC
SMSC KBC1126

PS2

eDP

100MHz

2.7GT/s

CRT

100MHz

Port 0

Page 13,14,15,16,17,18,19,20,21

SATA HDD
Conn.

Page 30

Int.KBD

Intel

Haswell

rPGA Processor

rPGA947

37.5mm*37.5mm

Page 4,5,6,7,8,9,10

Intel

Lynx Point

PCH

695pin BGA

20mm*20mm

LPC BUS

33MHz

SPI(PCH)

Page 38Page 38

DMI x4FDI x2

100MHz

5GT/s

SPI

BIOS SPI ROM x1,
16 MB

EC ROM
2MB

DDR3L 1333MHz 1.35V

USB 3.0 x4

USB 2.0 x 11

HD Audio

Page 30

HDA Codec
IDT 92HD91

Page 30

Page 26

Power On/Off CKT.

DC/DC interface CKT.

Page 34

A

B

C

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

DDR3-SO-DIMM2, 4

BANK 0, 1, 2, 3

Ch B

Ch A

Digital MIC

Combo Jack

DDR3-SO-DIMM1, 3

BANK 0, 1, 2, 3

Page 22

Page 39

SPK conn

Page 27

Page 12

Page 11

Docking connector:
RJ45
USB30*1
USB20*1
DP*2
Parallel port
Serial port
PS2
Line in/Line out
SATAx2
VGA

Compal Secret Data

Compal Secret Data

D

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2012/03/23 2011/06/29

2012/03/23 2011/06/29

2012/03/23 2011/06/29

X4

USB3.0 x3

X4

X1

X1

X1

X1

X1

X1

X1

Page 33

Dock x1

Smart card Controller
AU9540A51

WWAN SIM Card

Page 25 Page 25

FPR Validity VFM471

Webcam

Page 22

USB2.0

Page 39

WLAN

Page 25

Dock

Page 33

Page 37

Page 28

Compal Electronics, Inc.

Compal Electronics, Inc.

Custom

Custom

Custom

Compal Electronics, Inc.

Block Diagrams

Block Diagrams

Block Diagrams

LA-9241P

LA-9241P

LA-9241P

E

2 56Thursday, December 20, 2012

2 56Thursday, December 20, 2012

2 56Thursday, December 20, 2012

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

0.5

0.5

0.5

5

D D

C C

4

3

2

1

B B

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/03/23 2011/06/29

2012/03/23 2011/06/29

2012/03/23 2011/06/29

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

SMBus block diagram_DSC

SMBus block diagram_DSC

SMBus block diagram_DSC

LA-9241P

LA-9241P

LA-9241P

3 56Thursday, December 20, 2012

3 56Thursday, December 20, 2012

3 56Thursday, December 20, 2012

1

0.5

0.5

0.5

5

D D

DMI_CRX_PTX_N0[14]
DMI_CRX_PTX_N1[14]
DMI_CRX_PTX_N2[14]
DMI_CRX_PTX_N3[14]

DMI_CRX_PTX_P0[14]
DMI_CRX_PTX_P1[14]
DMI_CRX_PTX_P2[14]
DMI_CRX_PTX_P3[14]

DMI_CTX_PRX_N0[14]
DMI_CTX_PRX_N1[14]
DMI_CTX_PRX_N2[14]
DMI_CTX_PRX_N3[14]

DMI_CTX_PRX_P0[14]
DMI_CTX_PRX_P1[14]

C C

B B

DMI_CTX_PRX_P2[14]
DMI_CTX_PRX_P3[14]

FDI_CSYNC[14]
FDI_INT[14]

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

FDI_CSYNC
FDI_INT

4

Haswell rPGA EDS

Haswell rPGA EDS

JCPU1A

JCPU1A

D21

DMI_RXN_0

C21

DMI_RXN_1

B21

DMI_RXN_2

A21

DMI_RXN_3

D20

DMI_RXP_0

C20

DMI_RXP_1

B20

DMI_RXP_2

A20

DMI_RXP_3

D18

DMI_TXN_0

C17

DMI_TXN_1

B17

DMI_TXN_2

A17

DMI_TXN_3

D17

DMI_TXP_0

C18

DMI_TXP_1

B18

DMI_TXP_2

A18

DMI_TXP_3

H29

FDI_CSYNC

J29

DISP_INT

INTEL_HASWELL_HAS WELL

INTEL_HASWELL_HAS WELL

3

+VCCIOA_OUT

PEG_COMP

CAD Note:
Trace width=12 mils ,Spacing=15mil
Max length= 400 mils.

E23

PEG_RCOMP

PEG_RXN_0
PEG_RXN_1
PEG_RXN_2
PEG_RXN_3
PEG_RXN_4
PEG_RXN_5
PEG_RXN_6

PEG

PEG

PEG_RXN_7

DMI FDI

DMI FDI

PEG_RXN_8

PEG_RXN_9
PEG_RXN_10
PEG_RXN_11
PEG_RXN_12
PEG_RXN_13
PEG_RXN_14
PEG_RXN_15

PEG_RXP_0
PEG_RXP_1
PEG_RXP_2
PEG_RXP_3
PEG_RXP_4
PEG_RXP_5
PEG_RXP_6
PEG_RXP_7
PEG_RXP_8

PEG_RXP_9
PEG_RXP_10
PEG_RXP_11
PEG_RXP_12
PEG_RXP_13
PEG_RXP_14
PEG_RXP_15

PEG_TXN_0

PEG_TXN_1

PEG_TXN_2

PEG_TXN_3

PEG_TXN_4

PEG_TXN_5

PEG_TXN_6

PEG_TXN_7

PEG_TXN_8

PEG_TXN_9
PEG_TXN_10
PEG_TXN_11
PEG_TXN_12
PEG_TXN_13
PEG_TXN_14
PEG_TXN_15

PEG_TXP_0

PEG_TXP_1

PEG_TXP_2

PEG_TXP_3

PEG_TXP_4

PEG_TXP_5

PEG_TXP_6

PEG_TXP_7

PEG_TXP_8

PEG_TXP_9
PEG_TXP_10
PEG_TXP_11
PEG_TXP_12
PEG_TXP_13
PEG_TXP_14
PEG_TXP_15

1 OF 9

1 OF 9

PEG_COMP

M29

PEG_CRX_GTX_N0

K28

PEG_CRX_GTX_N1

M31

PEG_CRX_GTX_N2

L30

PEG_CRX_GTX_N3

M33

PEG_CRX_GTX_N4

L32

PEG_CRX_GTX_N5

M35

PEG_CRX_GTX_N6

L34

PEG_CRX_GTX_N7

E29

PEG_CRX_GTX_N8

D28

PEG_CRX_GTX_N9

E31

PEG_CRX_GTX_N10

D30

PEG_CRX_GTX_N11

E35

PEG_CRX_GTX_N12

D34

PEG_CRX_GTX_N13

E33

PEG_CRX_GTX_N14

E32

PEG_CRX_GTX_N15

L29

PEG_CRX_GTX_P0

L28

PEG_CRX_GTX_P1

L31

PEG_CRX_GTX_P2

K30

PEG_CRX_GTX_P3

L33

PEG_CRX_GTX_P4

K32

PEG_CRX_GTX_P5

L35

PEG_CRX_GTX_P6

K34

PEG_CRX_GTX_P7

F29

PEG_CRX_GTX_P8

E28

PEG_CRX_GTX_P9

F31

PEG_CRX_GTX_P10

E30

PEG_CRX_GTX_P11

F35

PEG_CRX_GTX_P12

E34

PEG_CRX_GTX_P13

F33

PEG_CRX_GTX_P14

D32

PEG_CRX_GTX_P15

H35

PEG_CTX_GRX_C_N0

H34

PEG_CTX_GRX_C_N1

J33

PEG_CTX_GRX_C_N2

H32

PEG_CTX_GRX_C_N3

J31

PEG_CTX_GRX_C_N4

G30

PEG_CTX_GRX_C_N5

C33

PEG_CTX_GRX_C_N6

B32

PEG_CTX_GRX_C_N7

B31

PEG_CTX_GRX_C_N8

A30

PEG_CTX_GRX_C_N9

B29

PEG_CTX_GRX_C_N10

A28

PEG_CTX_GRX_C_N11

B27

PEG_CTX_GRX_C_N12

A26

PEG_CTX_GRX_C_N13

B25

PEG_CTX_GRX_C_N14

A24

PEG_CTX_GRX_C_N15

J35

PEG_CTX_GRX_C_P0

G34

PEG_CTX_GRX_C_P1

H33

PEG_CTX_GRX_C_P2

G32

PEG_CTX_GRX_C_P3

H31

PEG_CTX_GRX_C_P4

H30

PEG_CTX_GRX_C_P5

B33

PEG_CTX_GRX_C_P6

A32

PEG_CTX_GRX_C_P7

C31

PEG_CTX_GRX_C_P8

B30

PEG_CTX_GRX_C_P9

C29

PEG_CTX_GRX_C_P10

B28

PEG_CTX_GRX_C_P11

C27

PEG_CTX_GRX_C_P12

B26

PEG_CTX_GRX_C_P13

C25

PEG_CTX_GRX_C_P14

B24

PEG_CTX_GRX_C_P15

12

RC124.9_0402_1% RC124.9_0402_1%

PEG_CRX_GTX_N[0..15] [35]

PEG_CRX_GTX_P[0..15] [35]

2

PEG_CTX_GRX_P[0..15]

PEG_CTX_GRX_N[0..15]

PEG_CTX_GRX_C_P0
PEG_CTX_GRX_C_N0 PEG_CTX_GRX_N0

PEG_CTX_GRX_C_P1
PEG_CTX_GRX_C_N1

PEG_CTX_GRX_C_P2
PEG_CTX_GRX_C_N2

PEG_CTX_GRX_C_P3
PEG_CTX_GRX_C_N3

PEG_CTX_GRX_C_P4
PEG_CTX_GRX_C_N4

PEG_CTX_GRX_C_P5
PEG_CTX_GRX_C_N5

PEG_CTX_GRX_C_P6
PEG_CTX_GRX_C_N6

PEG_CTX_GRX_C_P7
PEG_CTX_GRX_C_N7

PEG_CTX_GRX_C_P8
PEG_CTX_GRX_C_N8

PEG_CTX_GRX_C_P9
PEG_CTX_GRX_C_N9

PEG_CTX_GRX_C_P10
PEG_CTX_GRX_C_N10

PEG_CTX_GRX_C_P11
PEG_CTX_GRX_C_N11

PEG_CTX_GRX_C_P12
PEG_CTX_GRX_C_N12

PEG_CTX_GRX_C_P13
PEG_CTX_GRX_C_N13

PEG_CTX_GRX_C_P14
PEG_CTX_GRX_C_N14

PEG_CTX_GRX_C_P15
PEG_CTX_GRX_C_N15

12

CC1 0.22U_0402_6.3V6KCC1 0.22U_0402_6.3V6K

12

CC2 0.22U_0402_6.3V6KCC2 0.22U_0402_6.3V6K

12

CC3 0.22U_0402_6.3V6KCC3 0.22U_0402_6.3V6K

12

CC4 0.22U_0402_6.3V6KCC4 0.22U_0402_6.3V6K

12

CC5 0.22U_0402_6.3V6KCC5 0.22U_0402_6.3V6K

12

CC6 0.22U_0402_6.3V6KCC6 0.22U_0402_6.3V6K

12

CC7 0.22U_0402_6.3V6KCC7 0.22U_0402_6.3V6K

12

CC8 0.22U_0402_6.3V6KCC8 0.22U_0402_6.3V6K

12

CC9 0.22U_0402_6.3V6KCC9 0.22U_0402_6.3V6K

12

CC10 0.22U_0402_6.3V6KCC10 0.22U_0402_6.3V6K

12

CC11 0.22U_0402_6.3V6KCC11 0.22U_0402_6.3V6K

12

CC12 0.22U_0402_6.3V6KCC12 0.22U_0402_6.3V6K

12

CC13 0.22U_0402_6.3V6KCC13 0.22U_0402_6.3V6K

12

CC14 0.22U_0402_6.3V6KCC14 0.22U_0402_6.3V6K

12

CC15 0.22U_0402_6.3V6KCC15 0.22U_0402_6.3V6K

12

CC16 0.22U_0402_6.3V6KCC16 0.22U_0402_6.3V6K

1 2

CC17 0.22U_0402_6.3V6KCC17 0.22U_0402_6.3V6K

1 2

CC18 0.22U_0402_6.3V6KCC18 0.22U_0402_6.3V6K

1 2

CC19 0.22U_0402_6.3V6KCC19 0.22U_0402_6.3V6K

1 2

CC20 0.22U_0402_6.3V6KCC20 0.22U_0402_6.3V6K

1 2

CC21 0.22U_0402_6.3V6KCC21 0.22U_0402_6.3V6K

1 2

CC22 0.22U_0402_6.3V6KCC22 0.22U_0402_6.3V6K

1 2

CC23 0.22U_0402_6.3V6KCC23 0.22U_0402_6.3V6K

1 2

CC24 0.22U_0402_6.3V6KCC24 0.22U_0402_6.3V6K

1 2

CC25 0.22U_0402_6.3V6KCC25 0.22U_0402_6.3V6K

1 2

CC26 0.22U_0402_6.3V6KCC26 0.22U_0402_6.3V6K

1 2

CC27 0.22U_0402_6.3V6KCC27 0.22U_0402_6.3V6K

1 2

CC28 0.22U_0402_6.3V6KCC28 0.22U_0402_6.3V6K

1 2

CC29 0.22U_0402_6.3V6KCC29 0.22U_0402_6.3V6K

1 2

CC30 0.22U_0402_6.3V6KCC30 0.22U_0402_6.3V6K

1 2

CC31 0.22U_0402_6.3V6KCC31 0.22U_0402_6.3V6K

1 2

CC32 0.22U_0402_6.3V6KCC32 0.22U_0402_6.3V6K

PEG_CTX_GRX_P[0..15] [35]

PEG_CTX_GRX_N[0..15] [35]

PEG_CTX_GRX_P0

PEG_CTX_GRX_P1
PEG_CTX_GRX_N1

PEG_CTX_GRX_P2
PEG_CTX_GRX_N2

PEG_CTX_GRX_P3
PEG_CTX_GRX_N3

PEG_CTX_GRX_P4
PEG_CTX_GRX_N4

PEG_CTX_GRX_P5
PEG_CTX_GRX_N5

PEG_CTX_GRX_P6
PEG_CTX_GRX_N6

PEG_CTX_GRX_P7
PEG_CTX_GRX_N7

PEG_CTX_GRX_P8
PEG_CTX_GRX_N8

PEG_CTX_GRX_P9
PEG_CTX_GRX_N9

PEG_CTX_GRX_P10

PEG_CTX_GRX_N10

PEG_CTX_GRX_P11

PEG_CTX_GRX_N11

PEG_CTX_GRX_P12

PEG_CTX_GRX_N12

PEG_CTX_GRX_P13

PEG_CTX_GRX_N13

PEG_CTX_GRX_P14

PEG_CTX_GRX_N14

PEG_CTX_GRX_P15

PEG_CTX_GRX_N15

1

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2012/03/23 2011/06/29

2012/03/23 2011/06/29

2012/03/23 2011/06/29

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

DMI,PEG

DMI,PEG

DMI,PEG

LA-9241P

LA-9241P

LA-9241P

1

4 56Thursday, December 20, 2012

4 56Thursday, December 20, 2012

4 56Thursday, December 20, 2012

0.5

0.5

0.5

5

SM_DRAMPWROK with DDR Power Gating Topology

+5VDS

CC35

CC35

08/10 Add RC106 and change UC1.1 connection to VR_ON
9/11 Delete RC106
09/23 Change netname to PWR_GD

D D

C C

KBC_PROC_HOT#

PWR_GD[30,31,47]

PM_DRAM_PWRGD[14]

+3VS

+VCCIO_OUT

RC23 62_0402_5%RC23 62_0402_5%

Q592N7002KW_SOT323-3

Q592N7002KW_SOT323-3

13

D

D

2

G

G

S

S

1 2

RC9 100K_0402_1%RC9 100K_0402_1%

KBC_PROC_HOT_R[24,47]

1 2

#4/9 change by HP requirement

PCH_THERMTRIP#_R[18,24,35]

CLK_CPU_SSC_DPLL#[15]
CLK_CPU_SSC_DPLL[15]

KBC_PROC_HOT

H_PM_SYNC[14]

H_CPUPWRGD[18]

CLK_CPU_DPLL#[15]
CLK_CPU_DPLL[15]

CLK_CPU_DMI#[15]
CLK_CPU_DMI[15]

#4/9 change by
HP requirement

09/11 Delete RC27 and connect CPU.AM35 pin to PCH_THERMTRIP#_R

1 2

0.1U_0402_10V6K

0.1U_0402_10V6K

UC1

UC1

5

1

P

B

4

O

2

A

G

74AHC1G09GW_TSSOP5

74AHC1G09GW_TSSOP5

3

Part Number = SA00003Y000

Part Number = SA00003Y000

KBC_PROC_HOT_R

T120PAD @T120PAD @

T118PAD @T118PAD @

H_PECI[30]

1 2

RC26 56_0402_5%RC26 56_0402_5%

CPU_PLTRST#[18]

09/11 Connect CPU.AT26 pin to CPU_PLTRST#

4

+1.35VS

12

RC5

RC5

1.8K_0402_1%

1.8K_0402_1%

PM_DRAM_PWRGD_CPU

12

RC10

RC10

3.3K_0402_1%

3.3K_0402_1%

07/30 Non Install QC1
10/18 Delete QC1 and RC12

CPU_DETECT#

H_CATERR#
H_PECI

T1PAD @T1PAD @

KBC_PROC_HOT_R
PCH_THERMTRIP#_R

H_PM_SYNC
H_CPUPWRGD
PM_DRAM_PWRGD_CPU
CPU_PLTRST#

Haswell rPGA EDS

Haswell rPGA EDS

JCPU1B

JCPU1B

AP32

SKTOCC

AN32

CATERR

AR27

PECI

AK31

FC_AK31

AM30

PROCHOT

AM35

THERMTRIP

AT28

PM_SYNC

AL34

PWRGOO D

AC10

SM_DRAMPW ROK

AT26

PLTRSTIN

G28

DPLL_REF _CLKN

H28

DPLL_REF _CLKP

F27

SSC_DPLL _REF_CLKN

E27

SSC_DPLL _REF_CLKP

D26

BCLKN

E26

BCLKP

INTEL_HASWELL_HASWELL

INTEL_HASWELL_HASWELL

3

+VCCIO_OUT

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

CC33

CC33

CC34

CC34

2

2

Place near JXDP1

RC5 need to close to JCPU1

H_CPUPWRGD H_CPUPWRGD_XDP

ON/OFFBTN#[14,30]

CPU_PWR_DEBUG[9]
PM_PWROK[14,30]

DDR_XDP_WAN_SMBDAT[11,12,13,16,28,38]
DDR_XDP_WAN_SMBCLK[11,12,13,16,28,38]

MISC

MISC

THERMAL

THERMAL

DDR3

DDR3

PWR

PWR

CLOCK

CLOCK

SM_RCOMP_ 0
SM_RCOMP_ 1
SM_RCOMP_ 2
SM_DRAMRST

JTAG

JTAG

BPM_N_0
BPM_N_1
BPM_N_2
BPM_N_3
BPM_N_4
BPM_N_5
BPM_N_6
BPM_N_7

PRDY
PREQ

TRST

2 OF 9

2 OF 9

TCK
TMS

TDO
DBR

TDI

AP3

SM_RCOMP0

AR3

SM_RCOMP1

AP2

SM_RCOMP2

AN3

DDR3_DRAMRST#_CPU

AR29

XDP_PRDY#

AT29

XDP_PREQ#

AM34

XDP_TCLK

AN33

XDP_TMS

AM33

XDP_TRST#

AM31

XDP_TDI

AL33

XDP_TDO

AP33

XDP_DBRESET#

AR30

XDP_OBS0

AN31

XDP_OBS1

AN29

XDP_OBS2_R

AP31

XDP_OBS3_R

AP30

XDP_OBS4_R

AN28

XDP_OBS5_R

AP29

XDP_OBS6_R

AP28

XDP_OBS7_R

For ESD concern, please put near CPU

09/11 Noninstall RC36, RC38, RC40, RC43, RC45, RC47
11/07 Delete RC36, RC38, RC40, RC43, RC45, RC47 by
ESD request. Add T144, T145, T146, T147, T148, T149

1 2

RC13 1K_0402_1%RC13 1K_0402_1%

1 2

@

T144 PAD@T144 PAD

@

T145 PAD@T145 PAD

@

T146 PAD@T146 PAD

@

T147 PAD@T147 PAD

@

T148 PAD@T148 PAD

@

T149 PAD@T149 PAD

RC107 0_0402_5%RC107 0_0402_5%

09/23 Change netname to VGATE
09/26 Change netname to PM_PWROK. Add RC107

XDP_DBRESET# [14]

CFG0[8]
CFG1[8]

CFG2[8]
CFG3[8]

CFG4[8]
CFG5[8]

CFG6[8]
CFG7[8]

XDP_TCLK

DDR3_DRAMRST#_CPU

XDP_PREQ#
XDP_PRDY#

CFG0
CFG1

CFG2
CFG3

XDP_OBS0
XDP_OBS1

CFG4
CFG5

CFG6
CFG7

2

+VCCIO_OUT +VCCIO_OUT

JXDP1

JXDP1

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A 0

11

OBSDATA_A 1

13

GND4

15

OBSDATA_A 2

17

OBSDATA_A 3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B 0

29

OBSDATA_B 1

31

GND10

33

OBSDATA_B 2

35

OBSDATA_B 3

37

GND12

39

PWRGOO D/HOOK0

41

HOOK1

43

VCC_OBS_ AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01-L-D-A

SAMTE_BSH-030-01-L-D-A

07/25 Delete RC24

KBC_DS3_EN[30,45]

ITPCLK#/HOO K5

RESET#/HOO K6

RC22 0_0402_5%

RC22 0_0402_5%

BSS138W-7-F_SOT323-3

BSS138W-7-F_SOT323-3

2

GND1

4

OBSFN_C0

6

OBSFN_C1

8

GND3

10

OBSDATA_C0

12

OBSDATA_C1

14

GND5

16

OBSDATA_C2

18

OBSDATA_C3

20

GND7

22

OBSFN_D0

24

OBSFN_D1

26

GND9

28

OBSDATA_D0

30

OBSDATA_D1

32

GND11

34

OBSDATA_D2

36

OBSDATA_D3

38

GND13

40

ITPCLK/HOOK 4

42
44

VCC_OBS_ CD

46
48

DBR#/HOOK 7

50

GND15

52

TD0

54

TRST#

56

TDI

58

TMS

60

GND17

CONN@

CONN@

1 2

@

@

QC2

QC2

D

S

D

S

13

4.99K_0402_1%

4.99K_0402_1%

G

G

2

12

RC28

RC28

1 2

RC25 3.3K_0402_5%RC25 3.3K_0402_5%

13

D

D

@

@

2

QC3

QC3

G

G

2N7002_SOT23

2N7002_SOT23

S

S

10/18 Uninstall QC3 10/18 Change RC108 to 10k ohms, and install RC108

CFG17
CFG16

CFG8
CFG9

CFG10
CFG11

CFG19
CFG18

CFG12
CFG13

CFG14
CFG15

XDP_RST#_R
XDP_DBRESET#

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS

RC105 1K_0402_1%RC105 1K_0402_1%

12

10/12 Reserve RC108

1

CFG17 [8]
CFG16 [8]

CFG8 [8]
CFG9 [8]

CFG10 [8]
CFG11 [8]

CFG19 [8]
CFG18 [8]

CFG12 [8]
CFG13 [8]

CFG14 [8]
CFG15 [8]

12

RC16 1K_0402_1%RC16 1K_0402_1%

12

CFG3

CPU_DRAM_RST# [11]

DDR_RST_EN [16]

RC108

RC108
10K_0402_1%

10K_0402_1%

PLT_RST#

PLT_RST# [13,14,25,28,29,30,35,37,39]

PU/PD for JTAG signals

XDP_DBRESET#

09/11 Change RC55.1 connection to H_CPUPWRGD

H_CPUPWRGD

B B

12

RC55

RC55
10K_0402_1%

10K_0402_1%

DDR3 COMPENSATION SIGNALS

09/11 Delete RC66

A A

5

4

CAD Note:
Avoid stub in the PWRGD path
while placing resistors RC25 & RC130

3

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil

1 2

RC59 100_0402_1%RC59 100_0402_1%

1 2

RC61 75_0402_1%RC61 75_0402_1%

1 2

RC65 100_0402_1%RC65 100_0402_1%

Compal Secret Data

Compal Secret Data

2012/03/23 2011/06/29

2012/03/23 2011/06/29

2012/03/23 2011/06/29

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

RC52 1K_0402_1%RC52 1K_0402_1%

XDP_TDO

RC57 51_0402_1%RC57 51_0402_1%

XDP_TCLK

RC60 51_0402_1%RC60 51_0402_1%

XDP_TRST#

RC62 51_0402_1%RC62 51_0402_1%

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PM,XDP,CLK

PM,XDP,CLK

PM,XDP,CLK

12

12

12

12

LA-9241P

LA-9241P

LA-9241P

1

+3VS

+1.05VS

0.5

0.5

5 56Thursday, December 20, 2012

5 56Thursday, December 20, 2012

5 56Thursday, December 20, 2012

0.5

5

D D

JCPU1C

AM14

AM15

CC86

CC86

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

JCPU1C

AR15

SA_DQ_0

AT14

SA_DQ_1
SA_DQ_2

AN14

SA_DQ_3

AT15

SA_DQ_4

AR14

SA_DQ_5

AN15

SA_DQ_6
SA_DQ_7

AM9

SA_DQ_8

AN9

SA_DQ_9

AM8

SA_DQ_10

AN8

SA_DQ_11

AR9

SA_DQ_12

AT9

SA_DQ_13

AR8

SA_DQ_14

AT8

SA_DQ_15

AJ9

SA_DQ_16

AK9

SA_DQ_17

AJ6

SA_DQ_18

AK6

SA_DQ_19

AJ10

SA_DQ_20

AK10

SA_DQ_21

AJ7

SA_DQ_22

AK7

SA_DQ_23

AF4

SA_DQ_24

AF5

SA_DQ_25

AF1

SA_DQ_26

AF2

SA_DQ_27

AG4

SA_DQ_28

AG5

SA_DQ_29

AG1

SA_DQ_30

AG2

SA_DQ_31

J1

SA_DQ_32

J2

SA_DQ_33

J5

SA_DQ_34

H5

SA_DQ_35

H2

SA_DQ_36

H1

SA_DQ_37

J4

SA_DQ_38

H4

SA_DQ_39

F2

SA_DQ_40

F1

SA_DQ_41

D2

SA_DQ_42

D3

SA_DQ_43

D1

SA_DQ_44

F3

SA_DQ_45

C3

SA_DQ_46

B3

SA_DQ_47

B5

SA_DQ_48

E6

SA_DQ_49

A5

SA_DQ_50

D6

SA_DQ_51

D5

SA_DQ_52

E5

SA_DQ_53

B6

SA_DQ_54

A6

SA_DQ_55

E12

SA_DQ_56

D12

SA_DQ_57

B11

SA_DQ_58

A11

SA_DQ_59

E11

SA_DQ_60

D11

SA_DQ_61

B12

SA_DQ_62

A12

SA_DQ_63

AM3

SM_VREF

F16

SA_DIMM_VREFDQ

F13

SB_DIMM_VREFDQ

INTEL_HASWELL_HASWE LL

INTEL_HASWELL_HASWE LL

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_A_D[0..63][11]

C C

B B

+SM_VREF_CA
+DIMM01_VREF_DQ
+DIMM23_VREF_DQ

07/10 Change by HP request

1

2

CC84

CC84

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

CC85

CC85

1

2

4

Haswell rPGA EDS

Haswell rPGA EDS

SA_CK_N_0

SA_CK_P_0

SA_CKE_0
SA_CK_N_1
SA_CK_P_1

SA_CKE_1
SA_CK_N_2
SA_CK_P_2

SA_CKE_2
SA_CK_N_3
SA_CK_P_3

SA_CKE_3

SA_CS_N_0
SA_CS_N_1
SA_CS_N_2
SA_CS_N_3

SA_ODT_0

SA_ODT_1

SA_ODT_2

SA_ODT_3

SA_BS_0
SA_BS_1
SA_BS_2

SA_RAS

SA_WE

SA_CAS

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_MA_15

SA_DQS_N_0
SA_DQS_N_1
SA_DQS_N_2
SA_DQS_N_3
SA_DQS_N_4
SA_DQS_N_5
SA_DQS_N_6
SA_DQS_N_7
SA_DQS_P_0
SA_DQS_P_1
SA_DQS_P_2
SA_DQS_P_3
SA_DQS_P_4
SA_DQS_P_5
SA_DQS_P_6
SA_DQS_P_7

RSVD

VSS

3 OF 9

3 OF 9

AC7
U4

M_CLK_A_DDR#0

V4

M_CLK_A_DDR0

AD9

DDR_CKE0_DIMMA

U3

M_CLK_A_DDR#1

V3

M_CLK_A_DDR1

AC9

DDR_CKE1_DIMMA

U2

M_CLK_A_DDR#2

V2

M_CLK_A_DDR2

AD8

DDR_CKE2_DIMMA

U1

M_CLK_A_DDR#3

V1

M_CLK_A_DDR3

AC8

DDR_CKE3_DIMMA

M7

DDR_CS0_DIMMA#

L9

DDR_CS1_DIMMA#

M9

DDR_CS2_DIMMA#

M10

DDR_CS3_DIMMA#

M8

M_A_ODT0

L7

M_A_ODT1

L8

M_A_ODT2

L10

M_A_ODT3

V5

DDR_A_BS0

U5

DDR_A_BS1

AD1

DDR_A_BS2

V10
U6

DDR_A_RAS#

U7

DDR_A_WE#

U8

DDR_A_CAS#

V8

DDR_A_MA0

AC6

DDR_A_MA1

V9

DDR_A_MA2

U9

DDR_A_MA3

AC5

DDR_A_MA4

AC4

DDR_A_MA5

AD6

DDR_A_MA6

AC3

DDR_A_MA7

AD5

DDR_A_MA8

AC2

DDR_A_MA9

V6

DDR_A_MA10

AC1

DDR_A_MA11

AD4

DDR_A_MA12

V7

DDR_A_MA13

AD3

DDR_A_MA14

AD2

DDR_A_MA15

AP15

DDR_A_DQS#0

AP8

DDR_A_DQS#1

AJ8

DDR_A_DQS#2

AF3

DDR_A_DQS#3

J3

DDR_A_DQS#4

E2

DDR_A_DQS#5

C5

DDR_A_DQS#6

C11

DDR_A_DQS#7

AP14

DDR_A_DQS0

AP9

DDR_A_DQS1

AK8

DDR_A_DQS2

AG3

DDR_A_DQS3

H3

DDR_A_DQS4

E3

DDR_A_DQS5

C6

DDR_A_DQS6

C12

DDR_A_DQS7

M_CLK_A_DDR#0 [11]
M_CLK_A_DDR0 [11]
DDR_CKE0_DIMMA [11]
M_CLK_A_DDR#1 [11]
M_CLK_A_DDR1 [11]
DDR_CKE1_DIMMA [11]
M_CLK_A_DDR#2 [11]
M_CLK_A_DDR2 [11]
DDR_CKE2_DIMMA [11]
M_CLK_A_DDR#3 [11]
M_CLK_A_DDR3 [11]
DDR_CKE3_DIMMA [11]

DDR_CS0_DIMMA# [11]
DDR_CS1_DIMMA# [11]
DDR_CS2_DIMMA# [11]
DDR_CS3_DIMMA# [11]

M_A_ODT0 [11]
M_A_ODT1 [11]
M_A_ODT2 [11]

M_A_ODT3 [11]
DDR_A_BS0 [11]
DDR_A_BS1 [11]
DDR_A_BS2 [11]

DDR_A_RAS# [11]
DDR_A_WE# [11]
DDR_A_CAS# [11]

DDR_A_MA[0..15] [11]

DDR_A_DQS#[0..7] [11]

DDR_A_DQS[0..7] [11]

3

JCPU1D

DDR_B_D[0..63][12]

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

JCPU1D

AR18

SB_DQ_0

AT18

SB_DQ_1

AM17

SB_DQ_2

AM18

SB_DQ_3

AR17

SB_DQ_4

AT17

SB_DQ_5

AN17

SB_DQ_6

AN18

SB_DQ_7

AT12

SB_DQ_8

AR12

SB_DQ_9

AN12

SB_DQ_10

AM11

SB_DQ_11

AT11

SB_DQ_12

AR11

SB_DQ_13

AM12

SB_DQ_14

AN11

SB_DQ_15

AR5

SB_DQ_16

AR6

SB_DQ_17

AM5

SB_DQ_18

AM6

SB_DQ_19

AT5

SB_DQ_20

AT6

SB_DQ_21

AN5

SB_DQ_22

AN6

SB_DQ_23

AJ4

SB_DQ_24

AK4

SB_DQ_25

AJ1

SB_DQ_26

AJ2

SB_DQ_27

AM1

SB_DQ_28

AN1

SB_DQ_29

AK2

SB_DQ_30

AK1

SB_DQ_31

L2

SB_DQ_32

M2

SB_DQ_33

L4

SB_DQ_34

M4

SB_DQ_35

L1

SB_DQ_36

M1

SB_DQ_37

L5

SB_DQ_38

M5

SB_DQ_39

G7

SB_DQ_40

J8

SB_DQ_41

G8

SB_DQ_42

G9

SB_DQ_43

J7

SB_DQ_44

J9

SB_DQ_45

G10

SB_DQ_46

J10

SB_DQ_47

A8

SB_DQ_48

B8

SB_DQ_49

A9

SB_DQ_50

B9

SB_DQ_51

D8

SB_DQ_52

E8

SB_DQ_53

D9

SB_DQ_54

E9

SB_DQ_55

E15

SB_DQ_56

D15

SB_DQ_57

A15

SB_DQ_58

B15

SB_DQ_59

E14

SB_DQ_60

D14

SB_DQ_61

A14

SB_DQ_62

B14

SB_DQ_63

INTEL_HASWELL_HASWE LL

INTEL_HASWELL_HASWE LL

2

Haswell rPGA EDS

Haswell rPGA EDS

RSVD

SB_CKN0

SB_CK0

SB_CKE_0

SB_CKN1

SB_CK1

SB_CKE_1

SB_CKN2

SB_CK2

SB_CKE_2

SB_CKN3

SB_CK3

SB_CKE_3

SB_CS_N_0
SB_CS_N_1
SB_CS_N_2
SB_CS_N_3

SB_ODT_0
SB_ODT_1
SB_ODT_2
SB_ODT_3

SB_BS_0
SB_BS_1
SB_BS_2

SB_RAS

SB_WE

SB_CAS

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_MA_15

SB_DQS_N_0
SB_DQS_N_1
SB_DQS_N_2
SB_DQS_N_3
SB_DQS_N_4
SB_DQS_N_5
SB_DQS_N_6
SB_DQS_N_7
SB_DQS_P_0
SB_DQS_P_1
SB_DQS_P_2
SB_DQS_P_3
SB_DQS_P_4
SB_DQS_P_5
SB_DQS_P_6
SB_DQS_P_7

4 OF 9

4 OF 9

VSS

AG8
Y4

M_CLK_B_DDR#0

AA4

M_CLK_B_DDR0

AF10

DDR_CKE0_DIMMB

Y3

M_CLK_B_DDR#1

AA3

M_CLK_B_DDR1

AG10

DDR_CKE1_DIMMB

Y2

M_CLK_B_DDR#2

AA2

M_CLK_B_DDR2

AG9

DDR_CKE2_DIMMB

Y1

M_CLK_B_DDR#3

AA1

M_CLK_B_DDR3

AF9

DDR_CKE3_DIMMB

P4

DDR_CS0_DIMMB#

R2

DDR_CS1_DIMMB#

P3

DDR_CS2_DIMMB#

P1

DDR_CS3_DIMMB#

R4

M_B_ODT0

R3

M_B_ODT1

R1

M_B_ODT2

P2

M_B_ODT3

R7

DDR_B_BS0

P8

DDR_B_BS1

AA9

DDR_B_BS2

R10
R6

DDR_B_RAS#

P6

DDR_B_WE#

P7

DDR_B_CAS#

R8

DDR_B_MA0

Y5

DDR_B_MA1

Y10

DDR_B_MA2

AA5

DDR_B_MA3

Y7

DDR_B_MA4

AA6

DDR_B_MA5

Y6

DDR_B_MA6

AA7

DDR_B_MA7

Y8

DDR_B_MA8

AA10

DDR_B_MA9

R9

DDR_B_MA10

Y9

DDR_B_MA11

AF7

DDR_B_MA12

P9

DDR_B_MA13

AA8

DDR_B_MA14

AG7

DDR_B_MA15

AP18

DDR_B_DQS#0

AP11

DDR_B_DQS#1

AP5

DDR_B_DQS#2

AJ3

DDR_B_DQS#3

L3

DDR_B_DQS#4

H9

DDR_B_DQS#5

C8

DDR_B_DQS#6

C14

DDR_B_DQS#7

AP17

DDR_B_DQS0

AP12

DDR_B_DQS1

AP6

DDR_B_DQS2

AK3

DDR_B_DQS3

M3

DDR_B_DQS4

H8

DDR_B_DQS5

C9

DDR_B_DQS6

C15

DDR_B_DQS7

T3 PAD~D@T3 PA D~D@

M_CLK_B_DDR#0 [12]
M_CLK_B_DDR0 [12]
DDR_CKE0_DIMMB [12]
M_CLK_B_DDR#1 [12]
M_CLK_B_DDR1 [12]
DDR_CKE1_DIMMB [12]
M_CLK_B_DDR#2 [12]
M_CLK_B_DDR2 [12]
DDR_CKE2_DIMMB [12]
M_CLK_B_DDR#3 [12]
M_CLK_B_DDR3 [12]
DDR_CKE3_DIMMB [12]

DDR_CS0_DIMMB# [12]
DDR_CS1_DIMMB# [12]
DDR_CS2_DIMMB# [12]
DDR_CS3_DIMMB# [12]

M_B_ODT0 [12]
M_B_ODT1 [12]
M_B_ODT2 [12]

M_B_ODT3 [12]
DDR_B_BS0 [12]
DDR_B_BS1 [12]
DDR_B_BS2 [12]

DDR_B_RAS# [12]
DDR_B_WE# [12]
DDR_B_CAS# [12]

1

DDR_B_MA[0..15] [12]

DDR_B_DQS#[0..7] [12]

DDR_B_DQS[0..7] [12]

07/10 Delete by HP request

08/03 Add CC84, CC85, CC86

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/03/23 2011/06/29

2012/03/23 2011/06/29

2012/03/23 2011/06/29

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

DDRIII

DDRIII

DDRIII

LA-9241P

LA-9241P

LA-9241P

6 56Thursday, December 20, 2012

6 56Thursday, December 20, 2012

6 56Thursday, December 20, 2012

1

0.5

0.5

0.5

5

D D

4

3

2

1

COMPENSATION PU FOR eDP

+VCCIOA_OUT

EDP_COMP

CAD Note:Trace width=20 mils ,Spacing=25mil,

Haswell rPGA EDS

Haswell rPGA EDS

JCPU1H

JCPU1H

T28

DDIB_TXBN_0

U28

DDIB_TXBP_0

T30

C C

DDIB_TXBN_1

U30

DDIB_TXBP_1

U29

DDIB_TXBN_2

V29

DDIB_TXBP_2

U31

DDIB_TXBN_3

V31

DDIB_TXBP_3

T34

DDIC_TXCN_0

U34

DDIC_TXCP_0

U35

DDIC_TXCN_1

V35

DDIC_TXCP_1

U32

DDIC_TXCN_2

T32

DDIC_TXCP_2

U33

DDIC_TXCN_3

V33

DDIC_TXCP_3

P29

DDID_TXDN_0

R29

DDID_TXDP_0

N28

DDID_TXDN_1

P28

DDID_TXDP_1

P31

DDID_TXDN_2

R31

DDID_TXDP_2

N30

DDID_TXDN_3

P30

DDID_TXDP_3

INTEL_HASWELL_HAS WELL

INTEL_HASWELL_HAS WELL

eDP

eDP

EDP_RCOMP

EDP_DISP_UT IL

EDP_AUXN
EDP_AUXP

EDP_HPD

EDP_TXN_0
EDP_TXP_0
EDP_TXN_1
EDP_TXP_1

FDI_TXN_0

FDI_TXP_0

FDI_TXN_1

FDI_TXP_1

DDI

DDI

8 OF 9

8 OF 9

M27

EDP_CPU_C_AUX#

N27

EDP_CPU_C_AUX

P27

EDP_HPD

E24

EDP_COMP

R27

P35

EDP_CPU_C_LANE_N0

R35

EDP_CPU_C_LANE_P0

N34

EDP_CPU_C_LANE_N1

P34

EDP_CPU_C_LANE_P1

P33
R33
N32
P32

T119 PAD@T119 PAD@

1 2

C126 0.1U_0402_25V6C126 0.1U_0402_25V6

1 2

C127 0.1U_0402_25V6C127 0.1U_0402_25V6

1 2

C128 0.1U_0402_25V6C128 0.1U_0402_25V6

1 2

C129 0.1U_0402_25V6C129 0.1U_0402_25V6

1 2

C130 0.1U_0402_25V6C130 0.1U_0402_25V6

1 2

C131 0.1U_0402_25V6C131 0.1U_0402_25V6

Max length=100 mils.

FDI_CTX_PRX_N0
FDI_CTX_PRX_P0
FDI_CTX_PRX_N1
FDI_CTX_PRX_P1

+VCCIO_OUT

HPD INVERSION FOR EDP

B B

CPU_EDP_HPD#[36]

2

G

G

100K_0402_5%

100K_0402_5%

12

RC79

RC79

12

RC7724.9_0402_1% RC7724.9_0402_1%

EDP_CPU_AUX# [36]
EDP_CPU_AUX [36]

EDP_CPU_LANE_N0 [36]
EDP_CPU_LANE_P0 [36]
EDP_CPU_LANE_N1 [36]
EDP_CPU_LANE_P1 [36]
FDI_CTX_PRX_N0 [14]
FDI_CTX_PRX_P0 [14]
FDI_CTX_PRX_N1 [14]
FDI_CTX_PRX_P1 [14]

12

10K_0402_5%

10K_0402_5%
RC78

RC78

08/07 Change RC78 to 10K

EDP_HPD

13

D

D

QH1

QH1
BSS138W-7-F_SOT323-3

BSS138W-7-F_SOT323-3

S

S

SB000002X00

SB000002X00

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2012/03/23 2011/06/29

2012/03/23 2011/06/29

2012/03/23 2011/06/29

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

CPU-FDI,eDP,DDI

CPU-FDI,eDP,DDI

CPU-FDI,eDP,DDI

LA-9241P

LA-9241P

LA-9241P

1

7 56Thursday, December 20, 2012

7 56Thursday, December 20, 2012

7 56Thursday, December 20, 2012

0.5

0.5

0.5

5

4

3

2

1

CFG STRAPS for CPU

CFG2

D D

PEG Static Lane Reversal - CFG2 is for the 16x

1:(Default) Normal Operation; Lane #

CFG2

definition matches socket pin map definition
0:Lane Reversed

Haswell rPGA EDS

Haswell rPGA EDS

JCPU1I

JCPU1I

AT1

RSVD_TP

AT2

RSVD_TP

AD10

RSVD

A34

RSVD_TP

A35

RSVD_TP

T15 PAD~D@T15 PAD~D@
T12 PAD~D@T12 PAD~D@

T16 PAD~D@T16 PAD~D@

C C

12

B B

RC84 49.9_0402_1%RC84 49.9_0402_1%

RC85 49.9_0402_1%RC85 49.9_0402_1%

RC86 49.9_0402_1%RC86 49.9_0402_1%

H_CPU_TESTLO

12

CFG_RCOMP

12

H_CPU_RSVD

T17 PAD~D@T17 PAD~D@

T26 PAD~D@T26 PAD~D@
T28 PAD~D@T28 PAD~D@

CFG0[5]
CFG1[5]
CFG2[5]
CFG3[5]
CFG4[5]
CFG5[5]
CFG6[5]
CFG7[5]
CFG8[5]
CFG9[5]
CFG10[5]
CFG11[5]
CFG12[5]
CFG13[5]
CFG14[5]
CFG15[5]

+VCC_CORE

H_CPU_RSVD

H_CPU_TESTLO

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

W29

RSVD_TP

W28

RSVD_TP

G26

TESTLO_G26

W33

VSS

AL30

RSVD

AL29

RSVD

F25

VCC

C35

RSVD_TP

B35

RSVD_TP

AL25

RSVD_TP

W30

RSVD_TP

W31

RSVD_TP

W34

TESTLO

AT20

CFG_0

AR20

CFG_1

AP20

CFG_2

AP22

CFG_3

AT22

CFG_4

AN22

CFG_5

AT25

CFG_6

AN23

CFG_7

AR24

CFG_8

AT23

CFG_9

AN20

CFG_10

AP24

CFG_11

AP26

CFG_12

AN25

CFG_13

AN26

CFG_14

AP25

CFG_15

INTEL_HASWELL_HAS WELL

INTEL_HASWELL_HAS WELL

CFG_RCOMP

9 OF 9

9 OF 9

RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP

CFG_16
CFG_18
CFG_17
CFG_19

RSVD

FC_G6

RSVD
RSVD
RSVD
RSVD
RSVD

RSVD

RSVD
RSVD

RSVD

RSVD_TP

RSVD_TP
RSVD_TP

VSS
VSS

VSS
VSS

C23
B23
D24
D23

AT31

CFG_RCOMP

AR21

CFG16

AR23

CFG18

AP21

CFG17

AP23

CFG19

AR33
G6
AM27
AM26
F5
AM2
K6

E18

U10
P10

B1

NC

A2
AR1

E21
E20

AP27
AR26

AL31
AL32

07/10 Delete RC106 and RC107

CFG16 [5]
CFG18 [5]
CFG17 [5]
CFG19 [5]

1 : Disabled; No Physical Display Port

CFG4

attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2

CFG[6:5]

disabled
01: Reserved - (Device 1 function 1 disabled ; function

2 enabled)

CFG4

Display Port Presence Strap

CFG6

CFG5

PCIE Port Bifurcation Straps

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CFG9

1K_0402_1%

1K_0402_1%

12

@RC106

@

RC106

CFG7

1K_0402_1%

1K_0402_1%

12

@RC80

@

RC80

1K_0402_1%

1K_0402_1%

12

RC81

RC81

1K_0402_1%

1K_0402_1%

1K_0402_1%

1K_0402_1%

12

12

@RC83

@RC82

@

RC82

@

RC83

1K_0402_1%

1K_0402_1%

12

@RC87

@

RC87

09/21 Reserve CFG9 PD RC106

PEG DEFER TRAINING

1: (Default) PEG Train immediately

CFG7

following xxRESETB de assertion
0: PEG Wait for BIOS for training

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2012/03/23 2011/06/29

2012/03/23 2011/06/29

2012/03/23 2011/06/29

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

CPU-RSVD,CFG

CPU-RSVD,CFG

CPU-RSVD,CFG

LA-9241P

LA-9241P

LA-9241P

1

8 56Thursday, December 20, 2012

8 56Thursday, December 20, 2012

8 56Thursday, December 20, 2012

0.5

0.5

0.5

5

4

3

2

1

+1.35VS Source

D D

SLP_S3[34,49]

11/06 Change QC5A.2 and QC5B.5 connection to SLP_S3

09/11 Delete RC93 and connect SLP_S3# to QC5.5

10/16 Add Q80

C C

+VCC_CORE

100_0402_1%

B B

VCC_SENSE

100_0402_1%

12

RC101

RC101

2

+1.35V

B+ +1.35VS

12

RC88

RC88
100K_0402_5%

100K_0402_5%

RUN_ON_CPU1.5VS3

61

@

@

2N7002DWH_SOT363-6

2N7002DWH_SOT363-6
QC5A

QC5A

330K_0402_5%

330K_0402_5%

10/18 Delete Q80, R461, Q2, RC90. Modify +1.35VS power circuit
12/12 Uninstall QC4,RC92,CC39,RC89,QC5 and RC88. Add J4.
12/13 Install RC88

CAD Note: RC101 SHOULD BE PLACED CLOSE TO CPU

VCCSENSE[47]

VCCSENSE

CAD Note: RC104 SHOULD BE PLACED CLOSE TO CPU

VSSSENSE[10,47]

A A

VSSSENSE

09/11 Delete RC102 and RC103

100_0402_1%

100_0402_1%

12

RC104

RC104

J4

J4

112

JUMP_43X79

JUMP_43X79

SI7326DN-T1-E3_PAK1212-8

SI7326DN-T1-E3_PAK1212-8

QC4

@QC4

@

12

@

@

@

@

RC92

RC92

RUN_ON_CPU1.5VS3 [11,12]

2

4

1

CC39

CC39

2

0.1U_0402_25V6

0.1U_0402_25V6

1
2
35

R6

R6

20K_0402_5%

20K_0402_5%

12

@

@

07/25 Delete RC96

+1.35VS

RC89

RC89
470_0603_5%

470_0603_5%

@

@

1 2

34

QC5B

QC5B
2N7002DWH_SOT363-6

2N7002DWH_SOT363-6

@

@

10U_0603_6.3V6M

10U_0603_6.3V6M

1

CC42

CC42

2

22U_0805_6.3V6M

22U_0805_6.3V6M

CH1

CH1

1

2

5

SLP_S3

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CC43

CC43

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

CH2

CH2

1

1

2

2

VDDQ DECOUPLING

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CC46

CC44

CC44

CH3

CH3

CC46

CC45

CC45

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

CH4

CH4

CH5

CH5

1

1

2

2

+1.05VS

1

2

1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CC47

CC47

22U_0805_6.3V6M

22U_0805_6.3V6M

CH6

CH6

150_0402_1%

150_0402_1%

12

RC98

RC98

CPU_PWR_DEBUG

10U_0603_6.3V6M

10U_0603_6.3V6M

1

CC48

CC48

2

22U_0805_6.3V6M

22U_0805_6.3V6M

CH7

CH7

1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CC50

CC50

CC49

CC49

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

CH8

CH8

CH9

CH9

1

1

2

2

CC38 0.1U_0402_10V6KCC38 0.1U_0402_10V6K

12

CC40 0.1U_0402_10V6KCC40 0.1U_0402_10V6K

12

+VCC_CORE

09/11 Change netname to VCCSENSE

+VCCIO_OUT

T54

@ T54

@

PAD~D

PAD~D

+VCCIOA_OUT

VR_SVID_ALRT#[47]
VR_SVID_CLK[ 47]
VR_SVID_DAT[47]

CPU_PWR_DEBUG[5]

T50 PAD~D@T50 PAD~D@
T51 PAD~D@T51 PAD~D@
T52 PAD~D@T52 PAD~D@
T53 PAD~D@T53 PAD~D@

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

2

1

1

CC87

CC87

CC41

CC41

+

+

+

+

@

@

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y

CC51

CC51

2

2

08/06 Reserve CC87

22U_0805_6.3V6M

22U_0805_6.3V6M

CH10

CH10

CH11

CH11

1

2

+1.35VS

VCCSENSE

VR_SVID_ALRT#
VR_SVID_CLK
VR_SVID_DAT

+VCC_CORE

Haswell rPGA EDS

Haswell rPGA EDS

JCPU1E

JCPU1E

K27

RSVD

L27

RSVD

T27

RSVD

V27

RSVD

AB11

VDDQ

AB2

VDDQ

AB5

VDDQ

AB8

VDDQ

AE11

VDDQ

AE2

VDDQ

AE5

VDDQ

AE8

VDDQ

AH11

VDDQ

K11

VDDQ

N11

VDDQ

N8

VDDQ

T11

VDDQ

T2

VDDQ

T5

VDDQ

T8

VDDQ

W11

VDDQ

W2

VDDQ

W5

VDDQ

W8

VDDQ

N26

RSVD

K26

VCC

AL27

RSVD

AK27

RSVD

AL35

VCC_SENSE

E17

RSVD

AN35

VCCIO_OUT

A23

FC_A23

F22

VCOMP_OUT

W32

RSVD

AL16

RSVD

J27

RSVD

AL13

RSVD

AM28

VIDALERT

AM29

VIDSCLK

AL28

VIDSOUT

AP35

VSS

H27

PWR_DEBUG

AP34

VSS

AT35

RSVD_TP

AR35

RSVD_TP

AR32

RSVD_TP

AL26

RSVD_TP

AT34

VSS

AL22

VSS

AT33

VSS

AM21

VSS

AM25

# 04/02 change Pin name

VSS

AM22

by Intel update

VSS

AM20

VSS

AM24

VSS

AL19

VSS

AM23

VSS

AT32

VSS

Y25

VCC

Y26

VCC

Y27

VCC

Y28

VCC

Y29

VCC

Y30

VCC

Y31

VCC

Y32

VCC

Y33

VCC

Y34

VCC

Y35

VCC

INTEL_HASWELL_HASWE LL

INTEL_HASWELL_HASWE LL

# 04/02 change Pin name
by Intel update

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCC
VCC
VCC
VCC

VCC
VCC

5 OF 9

5 OF 9

AA26
AA28
AA34
AA30
AA32
AB26
AB29
AB25
AB27
AB28
AB30
AB31
AB33
AB34
AB32
AC26
AB35
AC28
AD25
AC30
AD28
AC32
AD31
AC34
AD34
AD26
AD27
AD29
AD30
AD32
AD33
AD35
AE26
AE32
AE28
AE30
AG28
AG34
AE34
AF25
AF26
AF27
AF28
AF29
AF30
AF31
AF32
AF33
AF34
AF35
AG26
AH26
AH29
AG30
AG32
AH32
AH35
AH25
AH27
AH28
AH30
AH31
AH33
AH34
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
G25
H25
J25
K25
L25
M25
N25
P25
R25
T25

U25
U26
V25
V26

W26
W27

+VCC_CORE

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/03/23 2011/06/29

2012/03/23 2011/06/29

2012/03/23 2011/06/29

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

CPU- PWR

CPU- PWR

CPU- PWR

LA-9241P

LA-9241P

LA-9241P

1

9 56Thursday, December 20, 2012

9 56Thursday, December 20, 2012

9 56Thursday, December 20, 2012

0.5

0.5

0.5

5

Haswell rPGA EDS

Haswell rPGA EDS

JCPU1F

D D

C C

B B

JCPU1F

A10

VSS

A13

VSS

A16

VSS

A19

VSS

A22

VSS

A25

VSS

A27

VSS

A29

VSS

A3

VSS

A31

VSS

A33

VSS

A4

VSS

A7

VSS

AA11

VSS

AA25

VSS

AA27

VSS

AA31

VSS

AA29

VSS

AB1

VSS

AB10

VSS

AA33

VSS

AA35

VSS

AB3

VSS

AC25

VSS

AC27

VSS

AB4

VSS

AB6

VSS

AB7

VSS

AB9

VSS

AC11

VSS

AD11

VSS

AC29

VSS

AC31

VSS

AC33

VSS

AC35

VSS

AD7

VSS

AE1

VSS

AE10

VSS

AE25

VSS

AE29

VSS

AE3

VSS

AE27

VSS

AE35

VSS

AE4

VSS

AE6

VSS

AE7

VSS

AE9

VSS

AF11

VSS

AF6

VSS

AF8

VSS

AG11

VSS

AG25

VSS

AE31

VSS

AG31

VSS

AE33

VSS

AG6

VSS

AH1

VSS

AH10

VSS

AH2

VSS

AG27

VSS

AG29

VSS

AH3

VSS

AG33

VSS

AG35

VSS

AH4

VSS

AH5

VSS

AH6

VSS

AH7

VSS

AH8

VSS

AH9

VSS

AJ11

VSS

AJ5

VSS

AK11

VSS

AK25

VSS

AK26

VSS

AK28

VSS

AK29

VSS

AK30

VSS

AK32

VSS

E19

VSS

INTEL_HASWELL_HAS WELL

INTEL_HASWELL_HAS WELL

4

AK34

VSS

AK5

VSS

AL1

VSS

AL10

VSS

AL11

VSS

AL12

VSS

AL14

VSS

AL15

VSS

AL17

VSS

AL18

VSS

AL2

VSS

AL20

VSS

AL21

VSS

AL23

VSS

E22

VSS

AL3

VSS

AL4

VSS

AL5

VSS

AL6

VSS

AL7

VSS

AL8

VSS

AL9

VSS

AM10

VSS

AM13

VSS

AM16

VSS

AM19

VSS

E25

VSS

AM32

VSS

AM4

VSS

AM7

VSS

AN10

VSS

AN13

VSS

AN16

VSS

AN19

VSS

AN2

VSS

AN21

VSS

AN24

VSS

AN27

VSS

AN30

VSS

AN34

VSS

AN4

VSS

AN7

VSS

AP1

VSS

AP10

VSS

AP13

VSS

AP16

VSS

AP19

VSS

AP4

VSS

AP7

VSS

W25

VSS

AR10

VSS

AR13

VSS

AR16

VSS

AR19

VSS

AR2

VSS

AR22

VSS

AR25

VSS

AR28

VSS

AR31

VSS

AR34

VSS

AR4

VSS

AR7

VSS

AT10

VSS

AT13

VSS

AT16

VSS

AT19

VSS

AT21

VSS

AT24

VSS

AT27

VSS

AT3

VSS

AT30

VSS

AT4

VSS

AT7

VSS

B10

VSS

B13

VSS

B16

VSS

B19

VSS

B2

VSS

B22

VSS

6 OF 9

6 OF 9

3

Haswell rPGA EDS

Haswell rPGA EDS

JCPU1G

JCPU1G

B34

VSS

B4

VSS

B7

VSS

C1

VSS

C10

VSS

C13

VSS

C16

VSS

C19

VSS

C2

VSS

C22

VSS

C24

VSS

C26

VSS

C28

VSS

C30

VSS

C32

VSS

C34

VSS

C4

VSS

C7

VSS

D10

VSS

D13

VSS

D16

VSS

D19

VSS

D22

VSS

D25

VSS

D27

VSS

D29

VSS

D31

VSS

D33

VSS

D35

VSS

D4

VSS

D7

VSS

E1

VSS

E10

VSS

E13

VSS

E16

VSS

E4

VSS

E7

VSS

F10

VSS

F11

VSS

F12

VSS

F14

VSS

F15

VSS

F17

VSS

F18

VSS

F20

VSS

F21

VSS

F23

VSS

F24

VSS

F26

VSS

F28

VSS

F30

VSS

F32

VSS

F34

VSS

F4

VSS

F6

VSS

F7

VSS

F8

VSS

F9

VSS

G1

VSS

G11

VSS

G2

VSS

G27

VSS

G29

VSS

G3

VSS

G31

VSS

G33

VSS

G35

VSS

G4

VSS

G5

VSS

H10

VSS

H26

VSS

H6

VSS

H7

VSS

J11

VSS

J26

VSS

J28

VSS

J30

VSS

J32

VSS

J34

VSS

J6

VSS

K1

VSS

INTEL_HASWELL_HAS WELL

INTEL_HASWELL_HAS WELL

VSS_SENSE

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

RSVD

7 OF 9

7 OF 9

K10
K2
K29
K3
K31
K33
K35
K4
K5
K7
K8
K9
L11
L26
L6
M11
M26
M28
M30
M32
M34
M6
N1
N10
N2
N29
N3
N31
N33
N35
N4
N5
N6
N7
N9
P11
P26
P5
R11
R26
R28
R30
R32
R34
R5
T1
T10
T29
T3
T31
T33
T35
T4
T6
T7
T9
U11
U27
V11
V28
V30
V32
V34
W1
W10
W3
W35
W4
W6
W7
W9
Y11
H11
AL24
F19
T26
AK35
AK33

2

09/11 Change netname to VSSSENSE

1

VSSSENSE [47,9]

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2012/03/23 2011/06/29

2012/03/23 2011/06/29

2012/03/23 2011/06/29

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

CPU-VSS

CPU-VSS

CPU-VSS

LA-9241P

LA-9241P

LA-9241P

1

10 56Thursday, December 20, 2012

10 56Thursday, December 20, 2012

10 56Thursday, December 20, 2012

0.5

0.5

0.5

5

Populate RD1, De-Populate RD7 for Intel DDR3
VREFDQ multiple methods M1
Populate RD7, De-Populate RD1 for Intel DDR3

10U_0603_6.3V6M

10U_0603_6.3V6M

CD14

CD14

1U_0402_6.3V6K

1U_0402_6.3V6K

CD24

CD24

G

G

S

S

10U_0603_6.3V6M

10U_0603_6.3V6M

1
@

@

2

2

QD1

QD1
2N7002K W_SOT 323-3

2N7002K W_SOT 323-3

13

D

D

+1.35V

1

CD15

CD15

+

+

2

SGA000 04400

SGA000 04400

VREFDQ multiple methods M3

1 2

RD24 1K_0402_1%RD24 1K_0402_1%

All VREF traces should
have 10 mil trace width

CD16

CD16
330U_B2 _2.5VM_R 15M

330U_B2 _2.5VM_R 15M

07/10 Change by HP request

+DIMM_A_D Q

1K_0402_1%

1K_0402_1%

12

RD23

RD23

DDR_CK E0_DIMMA[6]

M_CLK_A _DDR0[6]
M_CLK_A _DDR#0[6]

DDR_A_ BS0[6]

DDR_A_ WE#[6]
DDR_A_ CAS#[6]

DDR_CS 1_DIMMA#[6]

+3VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

CD27

CD27

2

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

CD3

CD3

CD4

CD4

2

2

DDR_A_ BS2[6]

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1

CD28

CD28

2

RUN_ON_CPU1 .5VS3[12,9]

+DIMM01_V REF_D Q

DDR_A_ D[0..63][6]

DDR_A_ DQS[0..7][6 ]

DDR_A_ DQS#[0..7 ][6]

DDR_A_ MA[0..15][6]

+1.35V

+1.35V

07/10 Change by HP request

Layout Note:
Place near JDIMM1

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD6

CD6

CD5

CD5

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD10

CD10

CD9

CD9

1

1

1

2

2

2

Layout Note:
Place near JDIMM1.203,204

+0.675VS

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CD21

CD21

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD7

CD7

CD8

CD8

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD11

CD11

CD12

CD12

CD13

CD13

1

1

1

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

1

CD23

CD23

CD22

CD22

2

2

2

D D

C C

B B

A A

4

JDIMM1 H=4mm TOP

07/17 Rename JP3 to JDIMM1

+1.35V +1.35V

JDIMM1

JDIMM1

2

VREF_DQ1VSS1

4

VREF_CA

EVENT#

DDR_A_ D4

6

DDR_A_ D5

8
10

DDR_A_ DQS#0

12

DDR_A_ DQS0

14
16

DDR_A_ D6

18

DDR_A_ D7

20
22

DDR_A_ D12

24
26
28
30

DDR3_D RAMRST# _R

32
34

DDR_A_ D14

36

DDR_A_ D15

38
40

DDR_A_ D20DD R_A_D 16

42

DDR_A_ D21

44
46
48
50

DDR_A_ D22

52

DDR_A_ D23

54
56

DDR_A_ D28

58

DDR_A_ D29

60
62

DDR_A_ DQS#3

64

DDR_A_ DQS3

66
68

DDR_A_ D30

70

DDR_A_ D31

72

74
76
78

DDR_A_ MA15

80

DDR_A_ MA14

82
84

DDR_A_ MA11DDR_A_ MA12

86

DDR_A_ MA7DDR_A_ MA9

A7

88
90

DDR_A_ MA6DDR_A_ MA8

A6

92

DDR_A_ MA4DDR_A_ MA5

A4

94
96

DDR_A_ MA2

A2

98

DDR_A_ MA0DDR_A_ MA1

A0

100
102

M_CLK_A _DDR1

CK1

104

M_CLK_A _DDR#1

CK1#

106

VDD12

108

DDR_A_ BS1

BA1

110

DDR_A_ RAS#

RAS#

112

VDD14

114

DDR_CS 0_DIMMA#

S0#

116

M_A_ODT 0

ODT0

118

VDD16

120

M_A_ODT 1

ODT1

122

NC2

124

VDD18

126
128

VSS28

130

DDR_A_ D36

DQ36

132

DDR_A_ D37

DQ37

134

VSS30

136

DM4

138

VSS31

140

DDR_A_ D38

DQ38

142

DDR_A_ D39

DQ39

144

VSS33

146

DDR_A_ D44

DQ44

148

DDR_A_ D45

DQ45

150

VSS35

152

DDR_A_ DQS#5

DQS#5

154

DDR_A_ DQS5

DQS5

156

VSS38

158

DDR_A_ D46

DQ46

160

DDR_A_ D47

DQ47

162

VSS40

164

DDR_A_ D52

DQ52

166

DDR_A_ D53

DQ53

168

VSS42

170

DM6

172

VSS43

174

DDR_A_ D54

DQ54

176

DDR_A_ D55

DQ55

178

VSS45

180

DDR_A_ D60

DQ60

182

DDR_A_ D61

DQ61

184

VSS47

186

DDR_A_ DQS#7

DQS#7

188

DDR_A_ DQS7

DQS7

190

VSS50

192

DDR_A_ D62

DQ62

194

DDR_A_ D63

DQ63

196

VSS52

198
200

SDA

202

SCL

204

VTT2

G2

+0.675VS+0.675VS

206

DDR_A_ D0
DDR_A_ D1

DDR_A_ D2
DDR_A_ D3

DDR_A_ D8
DDR_A_ D9 DDR _A_D13

DDR_A_ DQS#1
DDR_A_ DQS1

DDR_A_ D10
DDR_A_ D11

DDR_A_ D17

DDR_A_ DQS#2
DDR_A_ DQS2

DDR_A_ D18
DDR_A_ D19

DDR_A_ D24
DDR_A_ D25

DDR_A_ D26
DDR_A_ D27

DDR_CK E0_DIMMA DDR_ CKE1_D IMMA

DDR_A_ BS2

DDR_A_ MA3

M_CLK_A _DDR0
M_CLK_A _DDR#0

DDR_A_ MA10
DDR_A_ BS0

DDR_A_ WE#
DDR_A_ CAS#

DDR_A_ MA13
DDR_CS 1_DIMMA#

DDR_A_ D32
DDR_A_ D33

DDR_A_ DQS#4
DDR_A_ DQS4

DDR_A_ D34
DDR_A_ D35

DDR_A_ D40
DDR_A_ D41

DDR_A_ D42
DDR_A_ D43

DDR_A_ D48
DDR_A_ D49

DDR_A_ DQS#6
DDR_A_ DQS6

DDR_A_ D50
DDR_A_ D51

DDR_A_ D56
DDR_A_ D57

DDR_A_ D58
DDR_A_ D59

VSS23DQ4
DQ05DQ5
DQ17VSS3
VSS49DQS#0
DM011DQS0
VSS513VSS6
DQ215DQ6
DQ317DQ7
VSS719VSS8
DQ821DQ12
DQ923DQ13
VSS925VSS10
DQS#127DM1
DQS129RESET#
VSS1131VSS12
DQ1033DQ14
DQ1135DQ15
VSS1337VSS14
DQ1639DQ20
DQ1741DQ21
VSS1543VSS16
DQS#245DM2
DQS247VSS17
VSS1849DQ22
DQ1851DQ23
DQ1953VSS19
VSS2055DQ28
DQ2457DQ29
DQ2559VSS21
VSS2261DQS#3
DM363DQS3
VSS2365VSS24
DQ2667DQ30
DQ2769DQ31
VSS2571VSS26

CKE073CKE1
VDD175VDD2
NC177A15
BA279A14
VDD381VDD4
A12/BC#83A11

85

A9
VDD587VDD6

89

A8

91

A5
VDD793VDD8

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS 0A626-U4 RN-7F

FOX_AS 0A626-U4 RN-7F

CONN@

CONN@

08/07 Change JDIMM1 footprint

Reverse

DDR3_D RAMRST# _R[12]

DDR_CK E1_DIMMA [6]

M_CLK_A _DDR1 [6]
M_CLK_A _DDR#1 [6]

DDR_A_ BS1 [6]
DDR_A_ RAS# [6]

DDR_CS 0_DIMMA# [6]
M_A_ODT 0 [6]

+DIMM_VRE F_CA

M_A_ODT 1 [6]

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1K_0402_1%

1K_0402_1%

12

CD19

CD19

1

1

RD25

RD25

2

2

DDR_XD P_WAN_ SMBDAT [12 ,13,16,2 8,38,5]
DDR_XD P_WAN_ SMBCLK [12,13,16,28,3 8,5]

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CD20

CD20

RD6 33_0402_ 5%RD6 33_0 402_5%

08/03 Change RD6 to 33 ohms

1 2

RD26 1K_0402_1%RD26 1K_0402_1%

D

S

D

S

1 3

QD2

QD2

G

G

2N7002K W_SOT 323-3

2N7002K W_SOT 323-3

2

3

1 2

+1.35V

+SM_VREF _CA

RUN_ON_CPU1 .5VS3

2

1

JDIMM1 H=5.2mm BOT

+1.35V

1K_0402_5%

1K_0402_5%

12

RD2

RD2

All VREF traces should

CPU_DRA M_RST# [5]

have 10 mil trace width

07/10 Change by HP request

+DIMM_A_D Q

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1

1

CD1

CD1

2

2

DDR_CK E2_DIMMA[6]

M_CLK_A _DDR2[6]
M_CLK_A _DDR#2[6]

DDR_CS 3_DIMMA#[6]

+3VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1

CD26

CD26

1

CD25

CD25

2

2

+1.35V +1.35V

JDIMM3

DDR_A_ D0
DDR_A_ D1

CD2

CD2

DDR_A_ D2
DDR_A_ D3

DDR_A_ D8
DDR_A_ D9 DDR _A_D13

DDR_A_ DQS#1
DDR_A_ DQS1

DDR_A_ D10
DDR_A_ D11

DDR_A_ D17

DDR_A_ DQS#2
DDR_A_ DQS2

DDR_A_ D18
DDR_A_ D19

DDR_A_ D24
DDR_A_ D25

DDR_A_ D26
DDR_A_ D27

DDR_CK E2_DIMMA

DDR_A_ BS2

DDR_A_ MA12
DDR_A_ MA9

DDR_A_ MA8
DDR_A_ MA5

DDR_A_ MA3
DDR_A_ MA1

M_CLK_A _DDR2
M_CLK_A _DDR#2

DDR_A_ MA10
DDR_A_ BS0

DDR_A_ CAS#

DDR_A_ MA13
DDR_CS 3_DIMMA#

DDR_A_ D32
DDR_A_ D33

DDR_A_ DQS#4
DDR_A_ DQS4

DDR_A_ D34
DDR_A_ D35

DDR_A_ D40
DDR_A_ D41

DDR_A_ D42
DDR_A_ D43

DDR_A_ D48
DDR_A_ D49

DDR_A_ DQS#6
DDR_A_ DQS6

DDR_A_ D50
DDR_A_ D51

DDR_A_ D56
DDR_A_ D57

DDR_A_ D58
DDR_A_ D59

+0.675VS

JDIMM3

85

89
91

95
97

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

205

LCN_DAN0 6-K4406 -0102

LCN_DAN0 6-K4406 -0102
CONN@

CONN@

VREF_DQ1VSS1
VSS23DQ4
DQ05DQ5
DQ17VSS3
VSS49DQS#0
DM011DQS0
VSS513VSS6
DQ215DQ6
DQ317DQ7
VSS719VSS8
DQ821DQ12
DQ923DQ13
VSS925VSS10
DQS#127DM1
DQS129RESET#
VSS1131VSS12
DQ1033DQ14
DQ1135DQ15
VSS1337VSS14
DQ1639DQ20
DQ1741DQ21
VSS1543VSS16
DQS#245DM2
DQS247VSS17
VSS1849DQ22
DQ1851DQ23
DQ1953VSS19
VSS2055DQ28
DQ2457DQ29
DQ2559VSS21
VSS2261DQS#3
DM363DQS3
VSS2365VSS24
DQ2667DQ30
DQ2769DQ31
VSS2571VSS26

CKE073CKE1
VDD175VDD2
NC177A15
BA279A14
VDD381VDD4
A12/BC#83A11
A9
VDD587VDD6
A8
A5
VDD793VDD8
A3
A1
VDD999VDD10
CK0
CK0#
VDD11

VDD12
A10/AP
BA0
VDD13

VDD14
WE#
CAS#
VDD15

VDD16
A13
S1#
VDD17

VDD18
NCTEST

VREF_CA

VSS27

VSS28
DQ32
DQ33
VSS29

VSS30
DQS#4
DQS4

VSS31
VSS32
DQ34
DQ35

VSS33
VSS34
DQ40
DQ41

VSS35
VSS36

DQS#5
DM5
VSS37

VSS38
DQ42
DQ43
VSS39

VSS40
DQ48
DQ49
VSS41

VSS42
DQS#6
DQS6

VSS43
VSS44
DQ50
DQ51

VSS45
VSS46
DQ56
DQ57

VSS47
VSS48

DQS#7
DM7
VSS49

VSS50
DQ58
DQ59
VSS51

VSS52
SA0

EVENT#
VDDSPD
SA1
VTT1

G1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86

A7

88
90

A6

92

A4

94
96

A2

98

A0

100
102

CK1

104

CK1#

106
108

BA1

110

RAS#

112
114

S0#

116

ODT0

118
120

ODT1

122

NC2

124
126
128
130

DQ36

132

DQ37

134
136

DM4

138
140

DQ38

142

DQ39

144
146

DQ44

148

DQ45

150
152
154

DQS5

156
158

DQ46

160

DQ47

162
164

DQ52

166

DQ53

168
170

DM6

172
174

DQ54

176

DQ55

178
180

DQ60

182

DQ61

184
186
188

DQS7

190
192

DQ62

194

DQ63

196
198
200

SDA

202

SCL

204

VTT2

206

G2

DDR_A_ D4
DDR_A_ D5

DDR_A_ DQS#0
DDR_A_ DQS0

DDR_A_ D6
DDR_A_ D7

DDR_A_ D12

DDR3_D RAMRST# _R

DDR_A_ D14
DDR_A_ D15

DDR_A_ D20DD R_A_D 16
DDR_A_ D21

DDR_A_ D22
DDR_A_ D23

DDR_A_ D28
DDR_A_ D29

DDR_A_ DQS#3
DDR_A_ DQS3

DDR_A_ D30
DDR_A_ D31

DDR_CK E3_DIMMA

DDR_A_ MA15
DDR_A_ MA14

DDR_A_ MA11
DDR_A_ MA7

DDR_A_ MA6
DDR_A_ MA4

DDR_A_ MA2
DDR_A_ MA0

M_CLK_A _DDR3
M_CLK_A _DDR#3

DDR_A_ BS1
DDR_A_ RAS#

DDR_CS 2_DIMMA#DDR_A_ WE#
M_A_ODT 2

M_A_ODT 3

DDR_A_ D36
DDR_A_ D37

DDR_A_ D38
DDR_A_ D39

DDR_A_ D44
DDR_A_ D45

DDR_A_ DQS#5
DDR_A_ DQS5

DDR_A_ D46
DDR_A_ D47

DDR_A_ D52
DDR_A_ D53

DDR_A_ D54
DDR_A_ D55

DDR_A_ D60
DDR_A_ D61

DDR_A_ DQS#7
DDR_A_ DQS7

DDR_A_ D62
DDR_A_ D63

DDR_XD P_WAN_ SMBDAT
DDR_XD P_WAN_ SMBCLK

+0.675VS

DDR_CK E3_DIMMA [6]

M_CLK_A _DDR3 [6]
M_CLK_A _DDR#3 [6 ]

DDR_CS 2_DIMMA# [6]
M_A_ODT 2 [6]

M_A_ODT 3 [6]

1

2

+DIMM_VRE F_CA

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

CD17

CD17

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CD18

CD18

1

2

Standard

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

2012/03/23 2011/06/29

2012/03/23 2011/06/29

2012/03/23 2011/06/29

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

DDRIII DIMM1&2

DDRIII DIMM1&2

DDRIII DIMM1&2

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-9241P

LA-9241P

Date: Sheet

Date: Sheet

Date: Sheet

LA-9241P

1

of

11 56Thursday, Dece mber 20 , 2012

of

11 56Thursday, Dece mber 20 , 2012

of

11 56Thursday, Dece mber 20 , 2012

0.5

0.5

0.5

5

Populate RD4, De-Populate RD8 for Intel DDR3
VREFDQ multiple methods M1
Populate RD8, De-Populate RD4 for Intel DDR3
VREFDQ multiple methods M3

D D

All VREF traces should

100P_0402_50V8J

100P_0402_50V8J

1

C511

C511

2

11/06 Add C511 by rf request

10U_0603_6.3V6M

10U_0603_6.3V6M

1

CD43

CD43

1

+

+

@

@

CD44

CD44
330U_B2 _2.5VM_R 15M

330U_B2 _2.5VM_R 15M

2

2

have 10 mil trace width

DDR_B_ D[0..63][6]

DDR_B_ DQS[0..7][6 ]

DDR_B_ DQS#[0..7 ][6]

DDR_B_ MA[0..15][6]

Layout Note:
Place near JDIMM2

C C

B B

A A

+1.35V

+1.35V

10U_0603_6.3V6M

10U_0603_6.3V6M

CD37

CD37

1

2

+0.675VS

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD33

CD33

CD34

CD34

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD38

CD38

CD39

CD39

1

1

1

2

2

2

Layout Note:
Place near JDIMM2.203,204

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD49

CD49

CD50

CD50

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD35

CD35

CD36

CD36

@

@

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD40

CD40

CD42

CD42

CD41

CD41

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD51

CD51

CD52

CD52

2

2

07/10 Change by HP request

+DIMM_B_D Q

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1

2

DDR_CK E0_DIMMB[6]

DDR_B_ BS2[6 ]

M_CLK_B _DDR0[6]
M_CLK_B _DDR#0[6]

DDR_B_ BS0[6]

DDR_B_ WE#[6]
DDR_B_ CAS#[6]

DDR_CS 1_DIMMB#[6]

+3VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CD31

CD31

1

CD32

CD32

2

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

CD56

CD56

1

CD55

CD55

2

4

JDIMM2 H=9.2mm TOP

+1.35V +1.35V

DDR_B_ D0
DDR_B_ D1

DDR_B_ D2
DDR_B_ D3

DDR_B_ D8
DDR_B_ D9

DDR_B_ DQS#1
DDR_B_ DQS1

DDR_B_ D10
DDR_B_ D11

DDR_B_ D16
DDR_B_ D17

DDR_B_ DQS#2
DDR_B_ DQS2

DDR_B_ D18
DDR_B_ D19

DDR_B_ D24
DDR_B_ D25

DDR_B_ D26
DDR_B_ D27

DDR_CK E0_DIMMB

DDR_B_ BS2

DDR_B_ MA12
DDR_B_ MA9

DDR_B_ MA8
DDR_B_ MA5

DDR_B_ MA3
DDR_B_ MA1

M_CLK_B _DDR0
M_CLK_B _DDR#0

DDR_B_ MA10
DDR_B_ BS0

DDR_B_ WE#
DDR_B_ CAS#

DDR_B_ MA13
DDR_CS 1_DIMMB#

DDR_B_ D32
DDR_B_ D33

DDR_B_ DQS#4
DDR_B_ DQS4

DDR_B_ D34
DDR_B_ D35

DDR_B_ D40
DDR_B_ D41

DDR_B_ D42
DDR_B_ D43

DDR_B_ D48
DDR_B_ D49

DDR_B_ DQS#6
DDR_B_ DQS6

DDR_B_ D50
DDR_B_ D51

DDR_B_ D56
DDR_B_ D57

DDR_B_ D58
DDR_B_ D59

+0.675VS

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

205

08/07 Change JDIMM2 footprint

JDIMM2

JDIMM2

VREF_DQ1VSS1
VSS23DQ4
DQ05DQ5
DQ17VSS3
VSS49DQS#0
DM011DQS0
VSS513VSS6
DQ215DQ6
DQ317DQ7
VSS719VSS8
DQ821DQ12
DQ923DQ13
VSS925VSS10
DQS#127DM1
DQS129RESET#
VSS1131VSS12
DQ1033DQ14
DQ1135DQ15
VSS1337VSS14
DQ1639DQ20
DQ1741DQ21
VSS1543VSS16
DQS#245DM2
DQS247VSS17
VSS1849DQ22
DQ1851DQ23
DQ1953VSS19
VSS2055DQ28
DQ2457DQ29
DQ2559VSS21
VSS2261DQS#3
DM363DQS3
VSS2365VSS24
DQ2667DQ30
DQ2769DQ31
VSS2571VSS26

CKE073CKE1
VDD175VDD2
NC177A15
BA279A14
VDD381VDD4
A12/BC#83A11
A985A7
VDD587VDD6
A889A6
A591A4
VDD793VDD8
A395A2
A197A0
VDD999VDD10
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST

VREF_CA
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

G1

TYCO_2-2 013311 -4

TYCO_2-2 013311 -4

CONN@

CONN@

Reverse

EVENT#

3

RUN_ON_CPU1 .5VS3[11,9]

+DIMM23_V REF_D Q

2
4

DDR_B_ D4

6

DDR_B_ D5

8
10

DDR_B_ DQS#0

12

DDR_B_ DQS0

14
16

DDR_B_ D6

18

DDR_B_ D7

20
22

DDR_B_ D12

24

DDR_B_ D13

26
28
30

DDR3_D RAMRST# _R

32
34

DDR_B_ D14

36

DDR_B_ D15

38
40

DDR_B_ D20

42

DDR_B_ D21

44
46
48
50

DDR_B_ D22

52

DDR_B_ D23

54
56

DDR_B_ D28

58

DDR_B_ D29

60
62

DDR_B_ DQS#3

64

DDR_B_ DQS3

66
68

DDR_B_ D30

70

DDR_B_ D31

72

74

DDR_CK E1_DIMMB

76
78

DDR_B_ MA15

80

DDR_B_ MA14

82
84

DDR_B_ MA11

86

DDR_B_ MA7

88
90

DDR_B_ MA6

92

DDR_B_ MA4

94
96

DDR_B_ MA2

98

DDR_B_ MA0

100
102

M_CLK_B _DDR1

CK1

104

M_CLK_B _DDR#1

CK1#

106

VDD12

108

DDR_B_ BS1

BA1

110

DDR_B_ RAS#

RAS#

112

VDD14

114

DDR_CS 0_DIMMB#

S0#

116

M_B_ODT 0

ODT0

118

VDD16

120

M_B_ODT 1

ODT1

122

NC2

124

VDD18

126
128

VSS28

130

DDR_B_ D36

DQ36

132

DDR_B_ D37

DQ37

134

VSS30

136

DM4

138

VSS31

140

DDR_B_ D38

DQ38

142

DDR_B_ D39

DQ39

144

VSS33

146

DDR_B_ D44

DQ44

148

DDR_B_ D45

DQ45

150

VSS35

152

DDR_B_ DQS#5

DQS#5

154

DDR_B_ DQS5

DQS5

156

VSS38

158

DDR_B_ D46

DQ46

160

DDR_B_ D47

DQ47

162

VSS40

164

DDR_B_ D52

DQ52

166

DDR_B_ D53

DQ53

168

VSS42

170

DM6

172

VSS43

174

DDR_B_ D54

DQ54

176

DDR_B_ D55

DQ55

178

VSS45

180

DDR_B_ D60

DQ60

182

DDR_B_ D61

DQ61

184

VSS47

186

DDR_B_ DQS#7

DQS#7

188

DDR_B_ DQS7

DQS7

190

VSS50

192

DDR_B_ D62

DQ62

194

DDR_B_ D63

DQ63

196

VSS52

198
200

SDA

202

SCL

204

VTT2

+0.675VS

206

G2

DDR3_D RAMRST# _R [11 ]

DDR_CK E1_DIMMB [6]

M_CLK_B _DDR1 [6]
M_CLK_B _DDR#1 [6 ]

DDR_B_ BS1 [6]
DDR_B_ RAS# [6]

DDR_CS 0_DIMMB# [6]
M_B_ODT 0 [6]

+DIMM_VRE F_CA

M_B_ODT 1 [6]

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

CD48

CD48

CD47

CD47

1

1

2

2

DDR_XD P_WAN_ SMBDAT [11 ,13,16,2 8,38,5]
DDR_XD P_WAN_ SMBCLK [11,13,16,28,3 8,5]

07/10 Change by HP request

G

G

2

QD3

QD3
2N7002K W_SOT 323-3

2N7002K W_SOT 323-3

13

D

S

D

S

+1.35V

All VREF traces should
have 10 mil trace width

1 2

RD27 1K_0402_1 %RD27 1K_0402 _1%

+DIMM_B_D Q

0.1U_0402_16V4Z

0.1U_0402_16V4Z

RD28

RD28

12

1K_0402_1%

1K_0402_1%

1

CD30

CD30

2

DDR_CK E2_DIMMB[6]

M_CLK_B _DDR2[6]
M_CLK_B _DDR#2[6]

DDR_CS 3_DIMMB#[6]

+3VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

CD54

CD54

1

1

CD53

CD53

2

2

JDIMM4 H=5.2mm BOT

4/16 change by HP requirement

+1.35V +1.35V

DDR_B_ D0
DDR_B_ D1

DDR_B_ D2
DDR_B_ D3

DDR_B_ D8
DDR_B_ D9

DDR_B_ DQS#1
DDR_B_ DQS1

DDR_B_ D10
DDR_B_ D11

DDR_B_ D16
DDR_B_ D17

DDR_B_ DQS#2
DDR_B_ DQS2

DDR_B_ D18
DDR_B_ D19

DDR_B_ D24
DDR_B_ D25

DDR_B_ D26
DDR_B_ D27

DDR_CK E2_DIMMB

DDR_B_ BS2

DDR_B_ MA12
DDR_B_ MA9

DDR_B_ MA8
DDR_B_ MA5

DDR_B_ MA3
DDR_B_ MA1

M_CLK_B _DDR2
M_CLK_B _DDR#2

DDR_B_ MA10
DDR_B_ BS0

DDR_B_ WE#
DDR_B_ CAS#

DDR_B_ MA13
DDR_CS 3_DIMMB#

DDR_B_ D32
DDR_B_ D33

DDR_B_ DQS#4
DDR_B_ DQS4

DDR_B_ D34
DDR_B_ D35

DDR_B_ D40
DDR_B_ D41

DDR_B_ D42
DDR_B_ D43

DDR_B_ D48
DDR_B_ D49

DDR_B_ DQS#6
DDR_B_ DQS6

DDR_B_ D50
DDR_B_ D51

DDR_B_ D56
DDR_B_ D57

DDR_B_ D58
DDR_B_ D59

+0.675VS

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

205
207

JDIMM4

JDIMM4

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS

CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT

GND1
BOSS1

LCN_DAN0 6-K4406 -0103

LCN_DAN0 6-K4406 -0103

CONN@

CONN@

DQS0#

RESET#

DQS3#

VREF_CA

DQS5#

DQS7#

EVENT#

BOSS2

2

2

VSS

4

DDR_B_ D4

DQ4

6

DDR_B_ D5

DQ5

8

VSS

10

DDR_B_ DQS#0

12

DDR_B_ DQS0

DQS0

14

VSS

16

DDR_B_ D6

DQ6

18

DDR_B_ D7

DQ7

20

VSS

22

DDR_B_ D12

DQ12

24

DDR_B_ D13

DQ13

26

VSS

28

DM1

30

DDR3_D RAMRST# _R

32

VSS

34

DDR_B_ D14

DQ14

36

DDR_B_ D15

DQ15

38

VSS

40

DDR_B_ D20

DQ20

42

DDR_B_ D21

DQ21

44

VSS

46

DM2

48

VSS

50

DDR_B_ D22

DQ22

52

DDR_B_ D23

DQ23

54

VSS

56

DDR_B_ D28

DQ28

58

DDR_B_ D29

DQ29

60

VSS

62

DDR_B_ DQS#3

64

DDR_B_ DQS3

DQS3

66

VSS

68

DDR_B_ D30

DQ30

70

DDR_B_ D31

DQ31

72

VSS

74

DDR_CK E3_DIMMB

CKE1

76

VDD

78

DDR_B_ MA15

A15

80

DDR_B_ MA14

A14

82

VDD

84

DDR_B_ MA11

A11

86

DDR_B_ MA7

A7

88

VDD

90

DDR_B_ MA6

A6

92

DDR_B_ MA4

A4

94

VDD

96

DDR_B_ MA2

A2

98

DDR_B_ MA0

A0

100

VDD

102

M_CLK_B _DDR3

CK1

104

M_CLK_B _DDR#3

CK1#

106

VDD

108

DDR_B_ BS1

BA1

110

DDR_B_ RAS#

RAS#

112

VDD

114

DDR_CS 2_DIMMB#

S0#

116

M_B_ODT 2

ODT0

118

VDD

120

M_B_ODT 3

ODT1

122

NC

124

VDD

126
128

VSS

130

DDR_B_ D36

DQ36

132

DDR_B_ D37

DQ37

134

VSS

136

DM4

138

VSS

140

DDR_B_ D38

DQ38

142

DDR_B_ D39

DQ39

144

VSS

146

DDR_B_ D44

DQ44

148

DDR_B_ D45

DQ45

150

VSS

152

DDR_B_ DQS#5

154

DDR_B_ DQS5

DQS5

156

VSS

158

DDR_B_ D46

DQ46

160

DDR_B_ D47

DQ47

162

VSS

164

DDR_B_ D52

DQ52

166

DDR_B_ D53

DQ53

168

VSS

170

DM6

172

VSS

174

DDR_B_ D54

DQ54

176

DDR_B_ D55

DQ55

178

VSS

180

DDR_B_ D60

DQ60

182

DDR_B_ D61

DQ61

184

VSS

186

DDR_B_ DQS#7

188

DDR_B_ DQS7

DQS7

190

VSS

192

DDR_B_ D62

DQ62

194

DDR_B_ D63

DQ63

196

VSS

198
200

DDR_XD P_WAN_ SMBDAT

SDA

202

DDR_XD P_WAN_ SMBCLK

SCL

204

VTT

GND2

+0.675VS

206
208

DDR_CK E3_DIMMB [6]

M_CLK_B _DDR3 [6]
M_CLK_B _DDR#3 [6 ]

DDR_CS 2_DIMMB# [6]
M_B_ODT 2 [6]

+DIMM_VRE F_CA

M_B_ODT 3 [6]

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

CD45

CD45

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CD46

CD46

1

2

1

Reverse

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

2012/03/23 2011/06/29

2012/03/23 2011/06/29

2012/03/23 2011/06/29

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

DDRIII DIMM3&4

DDRIII DIMM3&4

DDRIII DIMM3&4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-9241P

LA-9241P

Date: Sheet

Date: Sheet

Date: Sheet

LA-9241P

1

of

12 56Thursday, Dece mber 20 , 2012

of

12 56Thursday, Dece mber 20 , 2012

of

12 56Thursday, Dece mber 20 , 2012

0.5

0.5

0.5

+RTCVCC

5

330K_0402_5%

330K_0402_5%

12

RH6

RH6

4

07/09 Delete by HP request.

3

2

07/09 Delete by HP request.

1

D D

INTVRMEN - INTEGRATED SUS 1.05V VRM
ENABLE
High - Enable Internal VRs
Low - Enable External VRs

+3VS

1 2

RH29 10K_0402_5%

RH29 10K_0402_5%

NO REBOOT STRAP

DISABLED WHEN LOW (DEFAULT)
ENABLED WHEN HIGH

C C

B B

1 2

RH33 100K_0402_5%

RH33 100K_0402_5%

08/03 RH33.1 connection to GND

HDA_SYNC Isolation Circuit

A A

W=20mils

CH102

CH102

1

1U_0603_10V4Z

1U_0603_10V4Z

2

Place near PCH

PCH_INTVRMEN

HDA_SPKR

@

@

HDD_HALTLED

@

@

CMOS_CLR1

Shunt Clear CMOS

Open

ME_CLR1

Shunt Clear ME RTC Registers

Open

SB000002X00

SB000002X00

BSS138W-7-F_SOT323-3

BSS138W-7-F_SOT323-3

RH43

RH43
1M_0402_5%

1M_0402_5%

1 2

D40

D40

1

DAN202U_SC70

DAN202U_SC70

5

07/09 Change by HP request.

BAT_GRNLED#[30,39]

+3V_PCH

RH30 2.2K_0402_5%RH30 2.2K_0402_5%

09/03 Instal RH31
09/19 Change QH11 to P MOS, change RH30 to 2.2K ohms

10/26 Swap QH11A.2 and QH11B.5 connection

12

MESS84DW-G_SC88-6

MESS84DW-G_SC88-6

FLASH DESCRIPTOR SECURITY OVERRIDE

LOW = DESABLED (DEFAULT)
HIGH = ENABLED

CMOS setting

Keep CMOS

TPM setting

Keep ME RTC Registers

+5VS

G

G

2

QH2

QH2

13

HDA_SYNCHDA_SYNC_R

D

S

D

S

+BATT1.1+RTCVCC +3VDS

2

3

+BATT_D

W=20mils

RH233

RH233

1 2

1K_0402_5%

1K_0402_5%

W=20mils

2

G

G

QH11A

QH11A

1 6

D

S

D

S

MESS84DW-G_SC88-6

MESS84DW-G_SC88-6

+RTCVCC

1

1

2

@

@

ME1 SHORT PADS

ME1 SHORT PADS

1 2

CH15 1U_0402_6.3V6KCH15 1U_0402_6.3V6K

W=20mils

08/07 Change JBATT1 footprint

PLT_RST#

5

G

G

QH11B

QH11B

4 3

HDA_SDOUT

D

S

D

S

RH34 20K_0402_5%RH34 20K_0402_5%

RH35 1M_0402_5%RH35 1M_0402_5%

RH36 20K_0402_5%RH36 20K_0402_5%

2

+3V_PCH

JBATT1

JBATT1

1

1

2

2

3

G1

4

G2

ACES_50271-00201-001

ACES_50271-00201-001

CONN@

CONN@

1 2

1 2

1 2

4

18P_0402_50V8J

18P_0402_50V8J

32.768KHZ_12.5PF_Q13FC1350000500

32.768KHZ_12.5PF_Q13FC1350000500

1

CH13

CH13

2

11/01 Change YH1 to small package

WWAN_DET#[25]

1

1

@

@

CMOS1 SHORT PADS

CMOS1 SHORT PADS

CH16

CH16

CMOS place near DIMM

2

2

1 2

1U_0402_6.3V6K

1U_0402_6.3V6K

RH39 51_0402_1%@RH39 51_0402_1%@

1 2

RH40

@RH40

@

1 2

RH41

@RH41

@

1 2

RH44

@RH44

@

09/21 Non-install RH39, RH40,
RH41, RH44, RH48, RH47, RH46

HDA_BITCLK_AUDIO[26]

1 2

RH28 10M_0402_5%RH28 10M_0402_5%

YH1

YH1

1 2

12

200_0402_5%

200_0402_5%

200_0402_5%

200_0402_5%

200_0402_5%

200_0402_5%

HDA_SYNC_AUDIO[26]

HDA_SDOUT_AUDIO[26]
HDA_RST_AUDIO#[26]

PCH_RTCX1

PCH_RTCX2

1

CH14

CH14
18P_0402_50V8J

18P_0402_50V8J

2

1 2

RH230 0_0402_5%RH230 0_0402_5%

PCH_RTCRST#[14]

HDA_SPKR[26]

HDA_SDI0[26]

07/06 Follow HP's GPIO table

HDD_HALTLED[39]

ISO_PREP#[33,36]

100_0402_1%

100_0402_1%

100_0402_1%

100_0402_1%

100_0402_1%

100_0402_1%

12

12

12

RH46

RH46

RH48

RH48

RH47

RH47

@

@

@

@

@

@

27P_0402_50V8J

27P_0402_50V8J

@CH17

@

CH17

1

2

DDR_XDP_WAN_SMBDAT[11,12,16,28,38,5]
DDR_XDP_WAN_SMBCLK[11,12,16,28,38,5]

PCH_RTCX1

PCH_RTCX2

SRTCRST#

INTRUDER#

PCH_INTVRMEN

PCH_RTCRST#

HDA_BIT_CLK

HDA_SYNC

HDA_SPKR

HDA_RST#

HDA_SDI0

HDA_SDOUT

HDD_HALTLED

ISO_PREP#

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

1 2

RH45 0_0402_5%RH45 0_0402_5%

1 2

RH51 33_0402_5%RH51 33_0402_5%

RP6

RP6

4 5
3 6
2 7
1 8

33_8P4R_5%

33_8P4R_5%

10/25 Delete RH50, RH52, RH53. Add RP6

3

PCH_TP25

HDA_SYNC_R

HDA_SDOUT
HDA_RST#
HDA_BIT_CLK

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

AL10

Issued Date

Issued Date

Issued Date

RH37

RH37

10K_0402_5%

10K_0402_5%

UH1A

UH1A

B5

RTCX1

B4

RTCX2

B9

SRTCRST#

A8

INTRUDER#

G10

INTVRMEN

D9

RTCRST#

B25

HDA_BCLK

A22

HDA_SYNC

SPKR

C24

HDA_RST#

L22

HDA_SDI0

K22

HDA_SDI1

G22

HDA_SDI2

F22

HDA_SDI3

A24

HDA_SDO

B17

DOCKEN#/GPIO33

C22

HDA_DOCK_RST #/GPIO13

AB3

JTAG_TCK

AD1

JTAG_TMS

AE2

JTAG_TDI

AD3

JTAG_TDO

F8

TP25

C26

TP22

AB6

TP20

RH38

RH38
10K_0402_5%

10K_0402_5%

1 2

1 2

+3VS

LPT_PCH_M_EDS

LPT_PCH_M_EDS

REV = 5

REV = 5

SATA_RXN_0
SATA_RXP_0

SATA_TXN_0
SATA_TXP_0

SATA_RXN_1
SATA_RXP_1

SATA_TXN_1
SATA_TXP_1

SATA

SATA

JTAGRTC AZALIA

JTAGRTC AZALIA

LYNXPOINT_BGA695

LYNXPOINT_BGA695

1 OF 11

1 OF 11

Compal Secret Data

Compal Secret Data

2012/03/23 2011/06/29

2012/03/23 2011/06/29

2012/03/23 2011/06/29

Compal Secret Data

SATA_RXN_2
SATA_RXP_2

SATA_TXN_2
SATA_TXP_2

SATA_RXN_3
SATA_RXP_3

SATA_TXN_3
SATA_TXP_3

SATA_RXN4/PERN1
SATA_RXP4/PERP1

SATA_TXN4/PETN1
SATA_TXP4/PETP1

SATA_RXN5/PERN2
SATA_RXP5/PERP2

SATA_TXN5/PETN2
SATA_TXP5/PETP2

SATA_RCOMP

SATA0GP/GPIO21

SATA1GP/GPIO19

SATA_IREF

Deciphered Date

Deciphered Date

Deciphered Date

2

SATALED#

SATA Impedance Compensation

BC8

SATA_PRX_DTX_N0

BE8

SATA_PRX_DTX_P0

AW8

SATA_PTX_DRX_N0

AY8

SATA_PTX_DRX_P0

BC10

SATA_PRX_DTX_N1

BE10

SATA_PRX_DTX_P1

AV10

SATA_PTX_DRX_N1

AW10

SATA_PTX_DRX_P1

BB9

SATA_PRX_DTX_N2

BD9

SATA_PRX_DTX_P2

AY13

SATA_PTX_DRX_N2

AW13

SATA_PTX_DRX_P2

BC12

SATA_PRX_DTX_N3

BE12

SATA_PRX_DTX_P3

AR13

SATA_PTX_DRX_N3

AT13

SATA_PTX_DRX_P3

BD13
BB13

AV15
AW15

BC14

SATA_PRX_DTX_N5

BE14

SATA_PRX_DTX_P5

AP15

SATA_PTX_DRX_N5

AR15

SATA_PTX_DRX_P5

AY5

SATA_COMP

AP3

SATA_ACT#

AT1

SG_IN

AU2

FN9

BD4

SATA_IREF

BA2

TP9

BB2

TP8

CAD note:
Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.

RH42 0_0402_5%RH42 0_0402_5%

SATA_COMP

1 2

R463 10K_0402_5%R463 10K_0402_5%

SATA_ACT# [33,39]

1 2

1 2

T72PAD~D @T72PAD~D @

RH497.5K_0402_1% RH497.5K_0402_1%

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

SATA_PRX_DTX_N0 [23]
SATA_PRX_DTX_P0 [23]

SATA_PTX_DRX_N0 [23]
SATA_PTX_DRX_P0 [23]

SATA_PRX_DTX_N1 [23]
SATA_PRX_DTX_P1 [23]

SATA_PTX_DRX_N1 [23]
SATA_PTX_DRX_P1 [23]

SATA_PRX_DTX_N2 [33]
SATA_PRX_DTX_P2 [33]

SATA_PTX_DRX_N2 [33]
SATA_PTX_DRX_P2 [33]

SATA_PRX_DTX_N3 [33]
SATA_PRX_DTX_P3 [33]

SATA_PTX_DRX_N3 [33]
SATA_PTX_DRX_P3 [33]

SATA_PRX_DTX_N5 [23]
SATA_PRX_DTX_P5 [23]

SATA_PTX_DRX_N5 [23]
SATA_PTX_DRX_P5 [23]

SG_IN [22]

+1.5VS

+3VS

PLT_RST#[14,25,28,29,30,35,37,39,5]

+1.5VS

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PCH-RTC,HDA,SATA,XDP

PCH-RTC,HDA,SATA,XDP

PCH-RTC,HDA,SATA,XDP

+3VS

RH237

RH237

1 2

10K_0402_5%

10K_0402_5%

LA-9241P

LA-9241P

LA-9241P

1

2

G

G

mSATA

HDD

ODD

DOCK_SATA5

DOCK_SATA3

+3VS

12

12

UMA@

UMA@

13

D

D

Q70

Q70
2N7002KW_SOT323-3

2N7002KW_SOT323-3

S

S

13 56Thursday, December 20, 2012

13 56Thursday, December 20, 2012

13 56Thursday, December 20, 2012

10K_0402_5%

10K_0402_5%
R7

R7

10K_0402_5%

10K_0402_5%
R8

R8

0.5

0.5

0.5

5

4

3

2

1

+3VDS

JME1

JME1

1

+3V_PCH

1 2

RH63 10K_ 0402_5%RH63 10K_040 2_5%

1 2

RH64 10K_ 0402_5%RH64 10K_040 2_5%

1 2

D D

C C

B B

11/06 Change PCH.D2 pin connection to DDR3_SET

RH72 10K_ 0402_5%RH72 10K_040 2_5%

1 2

RH75 10K_ 0402_5%RH75 10K_040 2_5%

+3VS

1 2

RH78 8.2K _0402_5%RH78 8.2K _0402_5%

1 2

RH70 200 K_0402_5%RH70 200 K_0402_5%

10/25 Change RH70 to 200K

DMI_CTX_PRX _N0[4]
DMI_CTX_PRX _N1[4]

DMI_CTX_PRX _N2[4]
DMI_CTX_PRX _N3[4]

DMI_CTX_PRX _P0[4]
DMI_CTX_PRX _P1[4]

DMI_CTX_PRX _P2[4]
DMI_CTX_PRX _P3[4]

DMI_CRX_P TX_N0[4]
DMI_CRX_P TX_N1[4]

DMI_CRX_P TX_N2[4]
DMI_CRX_P TX_N3[4]

DMI_CRX_P TX_P0[4] FDI_CSYNC [4]
DMI_CRX_P TX_P1[4]

DMI_CRX_P TX_P2[4]
DMI_CRX_P TX_P3[4]

+1.5VS

+1.5VS

09/11 Delete RH92, RH93, RH221, RH94, RH95

PM_PWR OK[30,5 ]

PCH_PW ROK_R[31]

PM_APW ROK[30,31]

PM_DRAM_P WRGD[5]

PM_RSMRST#[30]

SUS_PW R_ACK[30 ]

ON/OFFBTN#[30,5]

AC_PRES_ OUT[30,35]

BATLOW#[30 ]

DDR3_SET[4 5]

SUS_PW R_ACK

PCH_PCIE_ WAKE#

10/26 change RH75.2 connection to BATLOW#

BATLOW#

PM_CLKRUN#

SLP_LAN #

DMI_CTX_PRX _N0
DMI_CTX_PRX _N1

DMI_CTX_PRX _N2
DMI_CTX_PRX _N3

DMI_CTX_PRX _P0
DMI_CTX_PRX _P1

DMI_CTX_PRX _P2
DMI_CTX_PRX _P3

DMI_CRX_P TX_N0
DMI_CRX_P TX_N1

DMI_CRX_P TX_N2
DMI_CRX_P TX_N3

DMI_CRX_P TX_P0
DMI_CRX_P TX_P1

DMI_CRX_P TX_P2
DMI_CRX_P TX_P3

1 2

1 2

1 2

T90 PAD~D@ T90 PA D~D@

DMI_IREF

ME_SUS_P WR_ACK_R

RH88 0_04 02_5%RH8 8 0_0402_5 %

RH90 7.5K _0402_1%RH90 7.5K _0402_1%

10/16 Delete R230

SYS_RESE T#

PCH_PW ROK_R

RH97 0_040 2_5%RH97 0_0402 _5%

ON/OFFBTN#

AC_PRES_ OUT

BATLOW#

10/26 change PCH.K7 connection to BATLOW#

PCH_RI#

DDR3_SET

XDP_DBRE SET#[5]

08/10 Add RH245
10/12 Delete RH245. Add UH6, CH116
10/12 Delete VCC1_PWRGD connection to UH6.1 and 2. Then add R613
between +3VDS and UH6 pin 1,2. change UH6.5 pin connection to +3VDS
10/18 install R613, CH116 and UH6. Uninstall RH67
10/18 Uninstall R613, CH116 and UH6. Install RH68
12/12 Delete UH6, R613 and CH116

LPT_PCH_M_EDS

UH1B

UH1B

AW22

DMI_RXN_0

AR20

DMI_RXN_1

AP17

DMI_RXN_2

AV20

DMI_RXN_3

AY22

DMI_RXP_0

AP20

DMI_RXP_1

AR17

DMI_RXP_2

AW20

DMI_RXP_3

BD21

DMI_TXN_0

BE20

DMI_TXN_1

BD17

DMI_TXN_2

BE18

DMI_TXN_3

BB21

DMI_TXP_0

BC20

DMI_TXP_1

BB17

DMI_TXP_2

BC18

DMI_TXP_3

BE16

DMI_IREF

AW17

TP12

AV17

TP7

DMI_RCOMP

AY17

DMI_RCOMP

R6

SUSACK#

10/17 Change R614.1 connection to +3V_PCH
10/18 Change R614 to 10K ohms, and connection R614.1 to PM_RSMRST#
10/23 Uninstall Q79, R614
12/12 Delete Q79, R615

SUSACK#

AM1

SYS_RESET#

AD7

SYS_PWROK

F10

PWROK

AB7

APWROK

H3

DRAMPWROK

J2

RSMRST#

J4

SUSWARN#/SUSPWRNACK/GPIO30

K1

PWRBTN#

E6

ACPRESENT/GPIO31

K7

BATLOW#/GPIO72

N4

RI#

AB10

TP21

D2

SLP_WLAN#/GPIO29

LYNXPOINT_B GA695

LYNXPOINT_B GA695

08/10 Change UH7.5 connection to +3V_PCH power rail

LPT_PCH_M_EDS

DMI

DMI

System Power

System Power

1 2

RH54 0_04 02_5%RH5 4 0_0402_5 %

PCH_DPW ROK

REV = 5

REV = 5

FDI

FDI

Management

Management

4 OF 11

4 OF 11

RH67 0_04 02_5%RH67 0_040 2_5%

FDI_RXN_0

FDI_RXN_1

FDI_RXP_0

FDI_RXP_1

FDI_CSYNC

FDI_INT

FDI_IREF

FDI_RCOMP

DSWVRMEN

DPWROK

WAKE#

CLKRUN#

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN#

1 2

TP16

TP5

TP15

TP10

TP17

TP13

PCH_GPIO51

SYS_RESE T#

PM_RSMRST#PCH_RI#

AJ35

FDI_CTX_PRX _N0

AL35

FDI_CTX_PRX _N1

AJ36

FDI_CTX_PRX _P0

AL36

FDI_CTX_PRX _P1

AV43

AY45

AV45

AW44

AL39

FDI_CSYNC

AL40

FDI_INT

AT45

AU42

AU44

AR44

C8

L13

K3

AN7

U7

Y6

Y7

C6

H1

F3

F1

AY3

G5

SLP_LAN #_R

1 2

FDI_IREF

RH86 0_04 02_5%RH8 6 0_0402_5 %

FDI_RCOMP

DSWODV REN

PCH_DPW ROK

PCH_PCIE_ WAKE#

PM_CLKRUN#

BT_OFF DGPU_HOL D_RST#

SUSCLK_K BC

SLP_S5#

SLP_S4#

SLP_S3#

SIO_SLP _A#

SIO_SLP _SUS#

H_PM_SYNC

RH247 10K_0 402_5%RH247 10K_ 0402_5%

12

RH897. 5K_0402_1 % RH897 .5K_0402_ 1%

10/26 change PCH.U7 connection to BT_OFF

1 2

SLP_LAN #

10/25 Add R247

PCH_RTCRST#[1 3]

07/20 Add ME debug circuit

FDI_CTX_PRX _N0 [7]

FDI_CTX_PRX _N1 [7]

FDI_CTX_PRX _P0 [7]

FDI_CTX_PRX _P1 [7]

FDI_INT [4]

+1.5VS

+1.5VS

PCH_PCIE_ WAKE# [25]

PM_CLKRUN# [28, 30,32]

BT_OFF [25]

SUSCLK_K BC [30]

T85 PAD~D @T85 PA D~D@

@

@

T86 PAD ~D

T86 PAD ~D

SLP_S4# [45]

SLP_S3# [30,31 ,34,45]

SIO_SLP _A# [3 0,31,46]

T88 PAD ~D

T88 PAD ~D

@

@

SIO_SLP _SUS#

T89 PAD~D

T89 PAD~D

@

@

H_PM_SYNC [5]

SLP_LAN # [29 ,30]

Boot BIOS Strap

SATA1GP/
GPIO19

Boot BIOS Location

SLP_S3#

SLP_S5#
SLP_S4#
SIO_SLP _A#

PCH_RTCRST#

ON/OFFBTN#

SYS_RESE T#

PCH_CRT_BLU[36]

PCH_CRT_GRN[ 36]

PCH_CRT_RED[36]

PCH_CRT_DDC_ CLK[36]

PCH_CRT_DDC_ DAT[36]

PCH_CRT_HSYNC[36]

PCH_CRT_VSYN C[36 ]

DGPU_HOL D_RST#[35]

DGPU_SEL ECT#[35,36]

DGPU_PW R_EN[15 ,35]

+3VS

09/20 Change to +3VS

TBT_RR_GPIO#[3 9]

07/18 Delete PCH_GPIO55 PD RH186.
07/23 Add CR_SX_WARN# off page symbol
10/23 Change net name to TBT_RR_GPIO#

07/18 Add QH12 to invertion PCH_GPIO55 signal
07/23 Move QH12 to S/B.

00 LPC

A A

08/10 Change RH235 to 0ohms

0 1 Reserved (NAND)

1 0

PCI

1

2

2

3

3

4

4

5

5

6

6

7

16

7

G2

8

15

8

G1

9

9

10

10

11

11

12

12

13

13

14

14

FCI_1005 1922-1410E LF

FCI_1005 1922-1410E LF

CONN@

CONN@

DSWODVREN - ON DIE DSW VR ENABLE

HIGH = ENABLED (DEFAULT)
LOW = DISABLED

PCH_CRT_BLU

PCH_CRT_GRN

PCH_CRT_RED

PCH_CRT_DDC_ CLK

PCH_CRT_DDC_ DAT

1 2

RH84 20_ 0402_1%RH84 20_0402 _1%

1 2

RH85 20_ 0402_1%RH85 20_0402 _1%

1 2

RH87 649 _0402_1%RH87 649 _0402_1%

BKL_PW M_PCH[35 ]

PANEL_B KEN_PCH[35 ]

ENVDD_PCH[35]

DGPU_SELECT#

DGPU_PW R_EN

1 2

RH147 1 00K_0402 _5%RH147 100K_ 0402_5%

Camera_ON[22]

T45

U44

V45

M43

M45

HSYNC

VSYNC

CRT_IREF

N42

N44

U40

U39

N36

BKL_PW M_PCH

K36

G36

ENVDD_PCH

H20

PCI_PIRQA #

L20

PCI_PIRQB #

K17

PCI_PIRQC #

M20

PCI_PIRQD #

A12

B13

C12

C10

PCH_GPIO 51

A10

Camera_ON

AL6

TBT_RR_GPIO#

10/25 Delete RH98, RH99, RH100. Add RP9

RH101 1 00K_0402 _5%RH101 100K_ 0402_5%

VGA_BLUE

VGA_GREEN

VGA_RED

VGA_DDC_CLK

VGA_DDC_DATA

VGA_HSYNC

VGA_VSYNC

DAC_IREF

VGA_IRTN

EDP_BKLTCTL

EDP_BKLTEN

EDP_VDDEN

PIRQA#

PIRQB#

PIRQC#

PIRQD#

GPIO50

GPIO52

GPIO54

GPIO51

GPIO53

GPIO55

LYNXPOINT_B GA695

LYNXPOINT_B GA695

RP9

RP9

18
27
36
45

150_120 6_8P4R_1%

150_120 6_8P4R_1%

1 2

STP_A16OVR

LPT_PCH_M_EV

LPT_PCH_M_EV

LVDSCRT

LVDSCRT

PCH_CRT_BLU
PCH_CRT_GRN
PCH_CRT_RED

ENVDD_PCH

PCI

PCI

5 OF 11

5 OF 11

A16 SWAP OVERRIDE STRAP

LOW = A16 SWAP OVERRIDE
HIGH = DEFAULT

REV = 5UH1E

REV = 5UH1E

DDPB_CTRLDATA

DDPC_CTRLDATA

DDPD_CTRLDATA

DISPLAY

DISPLAY

MC74VHC1G 08DFT2G_SC70 -5

MC74VHC1G 08DFT2G_SC70 -5

DDPB_CTRLCLK

DDPC_CTRLCLK

DDPD_CTRLCLK

DDPB_AUXN

DDPC_AUXN

DDPD_AUXN

DDPB_AUXP

DDPC_AUXP

DDPD_AUXP

DDPB_HPD

DDPC_HPD

DDPD_HPD

PIRQE#/GPIO2

PIRQF#/GPIO3

PIRQG#/GPIO4

PIRQH#/GPIO5

PME#

PLTRST#

PLTRST#

07/23 Connection RH55.2 to +RTCVCC

+RTCVCC

330K_0402_5%

330K_0402_5%

1 2

07/31 Correct netname

DSWODV REN

10/25 Delete RH66, RH69, RH71. Add RP8

09/20 Change RH74 to 100k

R40

R39

R35

R36

N40

N38

H45

K43

J42

H43

K45

J44

K40

K38

H39

07/06 Correct netname to follow GPIO table

G17

PWRSV_ SEL#

F17

ODD_DA#

L15

NMI_SMI_DB G#

M15

ACCEL_INT_R #

AD10

T87 PAD~D@ T87 PA D~D@

Y11

PLTRST#

08/10 Change UH3.5 connection to +3V_PCH power rail

+3V_PCH

CH20

CH20

1 2

0.1U_040 2_16V4Z

0.1U_040 2_16V4Z

5

UH3

UH3

1

IN1

VCC

OUT

2

IN2

GND

3

10/25 Delete RH56, RH57, RH59, RH60. Add RP7

PCI_PIRQC #
PCI_PIRQA #
PCI_PIRQB #

4

PLT_RST#

1

@

@

22P_040 2_50V8J

22P_040 2_50V8J

2

PCI_PIRQD #

PWRSV_ SEL#

DGPU_PW R_EN
DGPU_HOL D_RST#
ODD_DA#

NMI_SMI_DB G#

PCH_CRT_DDC_ CLK

PCH_CRT_DDC_ DAT

DGPU_SEL ECT#

Camera_ON

ACCEL_INT_R #

TBT_RR_GPIO#

07/23 Add CR_SX_WARN# PU RH244
10/23 Change netname to TBT_RR_GPIO#

PWRSV_ SEL# [37]

ODD_DA# [23]

NMI_SMI_DB G# [30]

12

RH960_0 402_5% RH960_ 0402_5%

CH107

CH107

07/16 Add for ESD's request

RH55

RH55

RP7

RP7

18
27
36
45

8.2K_8P 4R_5%

8.2K_8P 4R_5%

12

RH6210K_0 402_5% RH621 0K_0402_ 5%

RP8

RP8

1 8
2 7
3 6
4 5

10K_8P4 R_5%

10K_8P4 R_5%

1 2

RH74100K_0402 _5% RH74100K_0402 _5%

12

RH762.2K _0402_5% RH762.2K _0402_5%

12

RH772.2K _0402_5% RH772.2K _0402_5%

12

RH8010K_0 402_5% RH801 0K_0402_ 5%

12

RH8210K_0 402_5% RH821 0K_0402_ 5%

12

RH838.2K _0402_5% RH838.2K_040 2_5%

12

RH24410K_0402_ 5% RH24410K_0402_ 5%

ACCEL_INT# [28]

PLT_RST# [13,25 ,28,29,30, 35,37,39,5 ]

+3VS

11 SPI

Security Classification

Security Classification

9/13 Delete UH7, RH235. Move RH236, CH106 to page 31

5

4

3

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

2012/03/23 2011/06/29

2012/03/23 2011/06/29

2012/03/23 2011/06/29

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Numb er Rev

Size Document Numb er Rev

Size Document Numb er Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH -DMI,FDI,PM,DP,CRT

PCH -DMI,FDI,PM,DP,CRT

PCH -DMI,FDI,PM,DP,CRT

LA-9241P

LA-9241P

LA-9241P

1

14 56Thursday, December 20, 2012

14 56Thursday, December 20, 2012

14 56Thursday, December 20, 2012

of

0.5

0.5

0.5

5

D D

4

3

2

+3V_PCH

10K_0402_5%

10K_0402_5%

RH106

RH106

1

1 2

GFX_CLK_REQ#

07/23 Delete FN14 and FN15 off page symbol

09/11 Delete RH107, RH103, RH203, RH114, RH116,
RH205, RH122, RH124, RH126, RH127, RH128, RH130

+3V_PCH

CLK_PCIE_CR#[39]
CLK_PCIE_CR[39]

+3VS

CR_CLK_REQ#[39]

CLK_TB_REFCLK#[39]

CLK_TB_REFCLK[39]

+3VS

C C

B B

TB_CLKREQ#[39]

+3V_PCH

CLK_PCIE_EXP#[39]
CLK_PCIE_EXP[39]

CLKREQ_EXP#[39]

+3V_PCH
CLK_PCIE_LAN#[29]
CLK_PCIE_LAN[29]

CLK_PCIE_LAN_REQ1#[29]

CLK_PCI_DEBUG_KBC[30]
CLK_PCI_DEBUG[25]

+3V_PCH
CLK_PCIE_MINI1#[25]

CLK_PCIE_MINI1[25]

+3V_PCH

MINI1_CLKREQ#[25]

CLK_PCI_KBC[30]
CLK_PCI_SIO[32]

CLK_PCI_TPM[28]

RH104 10K_0402_5%RH104 10K_0402_5%

RH105 10K_0402_5%RH105 10K_0402_5%

RH113 10K_0402_5%RH113 10K_0402_5%

RH118 10K_0402_5%RH118 10K_0402_5%

+3V_PCH

RH121 10K_0402_5%RH121 10K_0402_5%

RH125 10K_0402_5%RH125 10K_0402_5%

RH128 10K_0402_5%RH128 10K_0402_5%

RH131 10K_0402_5%RH131 10K_0402_5%

RH135 10_0402_5%RH135 10_0402_5%
RH137 10_0402_5%RH137 10_0402_5%

RH138 22_0402_5%RH138 22_0402_5%

10/25 Delete RH141, RH234, RH139. Add RP10.

12

12

12

12

12

12

12

12

12
12

12

RP10

RP10

18
27
36
45

22_1206_8P4R_5%

22_1206_8P4R_5%

CLKREQ_EXP#

CLK_PCIE_LAN_REQ1#

MINI1_CLKREQ#

CLK_PCI0

PCI_LOOPBACKOUTCLK_PCI_LOOPBACK

CLK_PCI2

CLK_PCI4

UH1C

UH1C

Y43

CLKOUT_PCIE_N_0

Y45

CLKOUT_PCIE_P_0

AB1

PCIECLKRQ0#/GPIO73

AA44

CLKOUT_PCIE_N_1

AA42

CLKOUT_PCIE_P_1

AF1

PCIECLKRQ1#/GPIO18

AB43

CLKOUT_PCIE_N_2

AB45

CLKOUT_PCIE_P_2

AF3

PCIECLKRQ2#/GPIO20/SMI#

AD43

CLKOUT_PCIE_N_3

AD45

CLKOUT_PCIE_P_3

T3

PCIECLKRQ3#/GPIO25

AF43

CLKOUT_PCIE_N_4

AF45

CLKOUT_PCIE_P_4

V3

PCIECLKRQ4#/GPIO26

AE44

CLKOUT_PCIE_N5

AE42

CLKOUT_PCIE_P_5

AA2

PCIECLKRQ5#/GPIO44

AB40

CLKOUT_PCIE_N_6

AB39

CLKOUT_PCIE_P_6

AE4

PCIECLKRQ6#/GPIO45

AJ44

CLKOUT_PCIE_N_7

AJ42

CLKOUT_PCIE_P_7

Y3

PCIECLKRQ7#/GPIO46

AH43

CLKOUT_ITPXDP

AH45

CLKOUT_ITPXDP_P

D44

CLKOUT_33MHZ0

E44

CLKOUT_33MHZ1

B42

CLKOUT_33MHZ2

F41

CLKOUT_33MHZ3

A40

CLKOUT_33MHZ4

CLOCK SIGNAL

CLOCK SIGNAL

PCIECLK REQ Pull UP Power Rail:
SUS Rail : 0 3 4 5 6 7
Core Rail: 1 2

A A

LPT_PCH_M_EDS

LPT_PCH_M_EDS

LYNXPOINT_BGA695

LYNXPOINT_BGA695

2 OF 11

2 OF 11

REV = 5

REV = 5

CLKOUT_PEG_A

CLKOUT_PEG_A_P

PEGA_CLKRQ#/GPIO47

CLKOUT_PEG_B

CLKOUT_PEG_B_P

PEGB_CLKRQ#/GPIO56

CLKOUT_DMI

CLKOUT_DMI_P

CLKOUT_DP

CLKOUT_DP_P

CLKOUT_DPNS

CLKOUT_DPNS_P

CLKIN_DMI

CLKIN_DMI_P

CLKIN_GND

CLKIN_GND_P

CLKIN_DOT96N

CLKIN_DOT96P

CLKIN_SATA

CLKIN_SATA_P

REFCLK14IN

CLKIN_33MHZLOOPBACK

XTAL25_IN

XTAL25_OUT

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

ICLK_IREF

DIFFCLK_BIASREF

TP19
TP18

AB35

CLK_PCIE_VGA#

AB36

CLK_PCIE_VGA

AF6

GFX_CLK_REQ#

Y39

Y38

U4

WLAN_TRAMSIT_OFF#

AF39

CLK_CPU_DMI#

AF40

CLK_CPU_DMI

AJ40

CLK_CPU_SSC_DPLL#

AJ39

CLK_CPU_SSC_DPLL

AF35

CLK_CPU_DPLL#

AF36

CLK_CPU_DPLL

AY24

CLK_BUF_DMI#

AW24

CLK_BUF_DMI

AR24

CLK_BUF_BCLK#

AT24

CLK_BUF_BCLK

H33

CLK_BUF_DOT96#

G33

CLK_BUF_DOT96

BE6

CLK_BUF_CKSSCD#

BC6

CLK_BUF_CKSSCD

F45

CLK_PCH_14M

D17

CLK_PCI_LOOPBACK

08/06 Change ball name

AM43
AL44

C40

F38

SIO_14M

F36

F39

AM45

ICLK_IREF

AD39
AD38

AN44

PCH_CLK_BIASREF

CLK_PCIE_VGA# [35]

CLK_PCIE_VGA [35]

RH109

RH109

12

10K_0402_5%

10K_0402_5%

WLAN_TRAMSIT_OFF# [25]

CLK_CPU_DMI# [5]

CLK_CPU_DMI [5]

CLK_CPU_SSC_DPLL# [5]

CLK_CPU_SSC_DPLL [5]

CLK_CPU_DPLL# [5]

CLK_CPU_DPLL [5]

T91PAD~D @T91PAD~D @

T92PAD~D @T92PAD~D @

1 2

1 2

12

RH1400_0402_5% RH1400_0402_5%

RH1427.5K_0402_1% RH1427.5K_0402_1%

RH136 22_0402_5%RH136 22_0402_5%

+3V_PCH

+1.5VS

+1.5VS

XTAL25_IN
XTAL25_OUT

2

G

G

2N7002KW_SOT323-3

2N7002KW_SOT323-3

1 3

D

S

D

S

Q55

Q55

07/06 Follow HP's GPIO table

CLK_SIO_14M [32]

10/25 Delete RH108, RH110, RH111, RH112. Add RP11

CLK_BUF_DMI
CLK_BUF_DMI#
CLK_BUF_BCLK
CLK_BUF_BCLK#

CLK_BUF_DOT96#
CLK_BUF_DOT96

CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD

CLK_PCH_14M

DGPU_PWR_EN [14,35]

PEG_CLK_REQ# [35]

11/01 Change YH2 to
small package

18P_0402_50V8J

18P_0402_50V8J

RP11

RP11

1 8
2 7
3 6
4 5

10K_8P4R_5%

10K_8P4R_5%

1 2

RH115 10K_0402_5%R H115 10K_0402_5%

1 2

RH117 10K_0402_5%R H117 10K_0402_5%

1 2

RH119 10K_0402_5%R H119 10K_0402_5%

1 2

RH120 10K_0402_5%R H120 10K_0402_5%

1 2

RH123 10K_0402_5%R H123 10K_0402_5%

1 2

RH132 1M _0402_5%RH 132 1M_0402_5%

YH2

YH2

3

4

25MHZ_20PF_5YEA2500020BIF50Q3

25MHZ_20PF_5YEA2500020BIF50Q3

1

CH21

CH21

2

OUT

NC

1

IN

2

NC

18P_0402_50V8J

18P_0402_50V8J

1

CH22

CH22

2

CLOCK TERMINATION for FCIM and need close to PCH

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2012/03/23 2011/06/29

2012/03/23 2011/06/29

2012/03/23 2011/06/29

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

PCH- CLK

PCH- CLK

PCH- CLK

LA-9241P

LA-9241P

LA-9241P

1

15 56Thursday, December 20, 2012

15 56Thursday, December 20, 2012

15 56Thursday, December 20, 2012

0.5

0.5

0.5

of

5

D D

+3VS

1 2

RH145 10K_0402 _5%RH 145 10K_0402_5%

C C

PCH_SPI_CLK[30]

PCH_SPI_CS0#[30]

PCH_SPI_SI[30]

PCH_SPI_SO[30]

PCH_SPI_WP#[30]

PCH_SPI_HOLD#[30]

B B

SIRQ

1 2

1 2

1 2

1 2

1

CH113
22P_0402_50V8J

22P_0402_50V8J

2

LPC_LAD0

LPC_LAD1

LPC_LAD2

LPC_LAD3

LPC_LFRAME#

SIRQ

PCH_SPI_CLK_R

PCH_SPI_CS0#_R

12

PCH_SPI_SI_R

12

PCH_SPI_SO_R

PCH_SPI_WP#_RPCH_SPI_WP#

07/09 Delete by HP request.

LPC_LAD0[25,28,30,32]

LPC_LAD1[25,28,30,32]

LPC_LAD2[25,28,30,32]

LPC_LAD3[25,28,30,32]

LPC_LFRAME#[25,28,30,32]

LPC_LDRQ0#[32]

SIRQ[28,30,32]

PCH_SPI_CLK

PCH_SPI_CS0#

PCH_SPI_SI

PCH_SPI_SO

PCH_SPI_HOLD# PCH_SPI_HOLD#_R

07/30 Add CH113 by RF request.

RH154 5_0402_1%RH154 5_0402_1%

RH155 5_0402_1%RH155 5_0402_1%

RH156 5_0402_1%RH156 5_0402_1%

RH157 5_0402_1%RH157 5_0402_1%

RH242 15_0402_5%RH242 15_0402_5%

RH243 15_0402_5%RH243 15_0402_5%

07/19 Add RH242 and RH243
07/26 Install RH242 and RH244

PCH_SPI_CLK

@ CH113

@

4

UH1D

UH1D

A20

LAD_0

C20

LAD_1

A18

LAD_2

C18

LAD_3

B21

LFRAME#

D21

LDRQ0#

G20

LDRQ1#/GPIO23

AL11

SERIRQ

AJ11

SPI_CLK

AJ7

SPI_CS0#

AL7

SPI_CS1#

AJ10

SPI_CS2#

AH1

SPI_MOSI

AH3

SPI_MISO

AJ4

SPI_IO2

AJ2

SPI_IO3

LYNXPOINT_BGA695

LYNXPOINT_BGA695

MEM_SMBCLK

MEM_SMBDATA

SPILPC

SPILPC

LPT_PCH_M_EDS

LPT_PCH_M_EDS

SMBus

SMBus

C-Link

C-Link

Thermal

Thermal

3 OF 11

3 OF 11

2N7002DWH_SOT363-6

2N7002DWH_SOT363-6

3 4

2N7002DWH_SOT363-6

2N7002DWH_SOT363-6

QH3B

QH3B

REV = 5

REV = 5

SML1ALERT#/PCHHOT#/GPIO74

+3VS

2

6 1

QH3A

QH3A

5

SMBALERT#/GPIO11

SMBDATA

SML0ALERT#/GPIO60

SML0CLK

SML0DATA

SML1CLK/GPIO58

SML1DATA/GPIO75

CL_DATA

CL_RST#

SMBCLK

CL_CLK

TD_IREF

3

DDR_XDP_WAN_ SMBCLK [11,12,13,28,38,5]

DDR_XDP_WAN_ SMBDAT [11,12,13,28,38,5]

N7

FPR_OFF

R10

MEM_SMBCLK

U11

MEM_SMBDATA

N8

DDR_RST_EN

U8

LAN_SMBCLK

R7

LAN_SMBDATA

H6

NFC_RST#

K6

SML1_SMBCLK

N11

SML1_SMBDATA

AF11

CL_CLK1

AF10

CL_DATA1

AF7

CL_RST1#

BA45

TP1

BC45

TP2

BE43

TP4

BE44

TP3

AY43

1 2

PCH_TD_IREF

RH158 8.2K_0402_1%RH158 8.2K_0402_1%

H1

H1

H_3P0

H_3P0

HOLEA

HOLEA

@

@

1

H27

H27

H_3P3

H_3P3

HOLEA

HOLEA

@

@

1

FPR_OFF [28]

DDR_RST_EN [5]

LAN_SMBCLK [29]

LAN_SMBDATA [29]

NFC_RST# [39]

07/06 Add for NFC function

CL_CLK1 [25]

CL_DATA1 [25]

CL_RST1# [25]

H2

H2

H6

H6

H_3P3

H_3P3

H_3P8

H_3P8

HOLEA

HOLEA

HOLEA

HOLEA

@

@

1

1

H28

H28

H29

H29

H_3P3

H_3P3

H_3P3

H_3P3

HOLEA

HOLEA

HOLEA

HOLEA

@

@

1

1

H7

H7

H_3P8

H_3P8

HOLEA

HOLEA

@

@

@

@

1

H30

H30

H_3P0

H_3P0

HOLEA

HOLEA

@

@

@

@

1

H8

H8

H_3P0

H_3P0

HOLEA

HOLEA

1

H31

H31

H_3P8

H_3P8

HOLEA

HOLEA

1

2

07/06 Add for NFC function

SML1_SMBCLK

SML1_SMBDATA

H9

H9

H_3P8

H_3P8

HOLEA

HOLEA

@

@

@

@

1

H33

H33

H_3P1N

H_3P1N

HOLEA

HOLEA

@

@

@

@

1

08/07 Install RH148 and
change value to 2.2K
10/18 Uninstall RH148
07/06 Add for NFC function

10/09 Change to RH152, RH153 to 499ohms
11/09 Change RH152, RH153 to 2.2K ohms

+3VS +3VS +3V S

2N7002DWH_SOT363-6

H10

H10

H_3P8

H_3P8

HOLEA

HOLEA

H35

H35

H_3P8

H_3P8

HOLEA

HOLEA

@

@

1

@

@

1

2N7002DWH_SOT363-6

3 4

@

@

2N7002DWH_SOT363-6

2N7002DWH_SOT363-6

QH10B

QH10B

2N7002DWH_SOT363-6

2N7002DWH_SOT363-6

H20

H20

H19

H19

H_4P3

H_4P3

H_4P8X3P8

H_4P8X3P8

HOLEA

HOLEA

HOLEA

HOLEA

@

@

1

1

H37

H37

H38

H38

H_3P0

H_3P0

H_3P8

H_3P8

HOLEA

HOLEA

HOLEA

HOLEA

@

@

1

1

LAN_SMBCLK

LAN_SMBDATA

FPR_OFF

MEM_SMBCLK

MEM_SMBDATA

DDR_RST_EN

NFC_RST#

SML1_SMBCLK

SML1_SMBDATA

LAN_SMBCLK

LAN_SMBDATA

6 1

@

@

QH10A

QH10A

5

QH9B

QH9B

5

H21

H21

H_3P8

H_3P8

HOLEA

HOLEA

@

@

H40

H40

H_3P0

H_3P0

HOLEA

HOLEA

@

@

1

1

RH238

RH238

12

2.2K_0402_5%

2.2K_0402_5%

@

@

2

2N7002DWH_SOT363-6

2N7002DWH_SOT363-6

QH9A

QH9A

61

2

34

H22

H22

H_4P8X3P8

H_4P8X3P8

HOLEA

HOLEA

@

@

@

@

1

H42

H42

H_2P8

H_2P8

HOLEA

HOLEA

@

@

@

@

1

1 2

1 2

RH239

RH239

12

2.2K_0402_5%

2.2K_0402_5%

@

@

H24

H24

H_3P3

H_3P3

HOLEA

HOLEA

@

@

1

H43

H43

H_2P8

H_2P8

HOLEA

HOLEA

@

@

1

1

12

12

12

12

@

@

12

12

12

H25

H25

H_2P8

H_2P8

HOLEA

HOLEA

1

H44

H44

H_2P4X3P9N

H_2P4X3P9N

HOLEA

HOLEA

1

+3V_PCH

RH14310K_0402_5% RH14310K_0402_5%

RH1442.2K_0402_5% RH1442.2K_0402_5%

RH1462.2K_0402_5% RH1462.2K_0402_5%

RH1482.2K_0402_5%

RH1482.2K_0402_5%

RH14910K_0402_5% RH14910K_0402_5%

RH1502.2K_0402_5% RH1502.2K_0402_5%

RH1512.2K_0402_5% RH1512.2K_0402_5%

+3VM_LAN

RH1522.2K_0402_5% RH1522.2K_0402_5%

RH1532.2K_0402_5% RH1532.2K_0402_5%

NFC_3S_SMBCLK [39]

NFC_3S_SMBDAT [39]

PCH_KBC_I2CLK [30,35]

PCH_KBC_I2CDAT [30,35]

H26

H26

H_3P3

H_3P3

HOLEA

HOLEA

@

@

@

@

1

H45

H45

H_3P8X4P8N

H_3P8X4P8N

HOLEA

HOLEA

@

@

@

@

1

+3V_PCH

+3V_PCH

ZZZ1

ZZZ1

PCB

PCB

MB

MB

H47

H47

H46

H46

H_3P0N

H_3P0N

H_3P8

H_3P8

HOLEA

HOLEA

HOLEA

HOLEA

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2012/03/23 2011/06/29

2012/03/23 2011/06/29

2012/03/23 2011/06/29

@

@

@

@

1

1

H49

H49

H48

H48

H_3P3

H_3P3

H_3P0N

H_3P0N

HOLEA

HOLEA

HOLEA

HOLEA

@

@

@

@

1

1

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

H50

H50

H_3P0

H_3P0

HOLEA

HOLEA

1

FD4

@

@

FD4
FIDUCIAL_C40M80

FIDUCIAL_C40M80

@

@

1

1

0.5

0.5

16 56Thursday, December 20, 2012

16 56Thursday, December 20, 2012

16 56Thursday, December 20, 2012

0.5

FD2

FD1

FD1
FIDUCIAL_C40M80

FIDUCIAL_C40M80

@

@

2

1

07/20 Modify screw hole
07/23 Modify screw hole
08/06 Delete H23
09/12 Delete H4, H32, H34, H41. Add H42, H43, H44, H45, H46
09/21 Add H47, H48

FD2
FIDUCIAL_C40M80

FIDUCIAL_C40M80

@

@

1

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

FD3

FD3
FIDUCIAL_C40M80

FIDUCIAL_C40M80

@

@

1

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PCH - SPI, SMBUS,LPC

PCH - SPI, SMBUS,LPC

PCH - SPI, SMBUS,LPC

LA-9241P

LA-9241P

LA-9241P

5

D D

07/17 Add by HP request.

PCIE_PRX_DTX_N1[39]
PCIE_PRX_DTX_P1[39]

PCIE_PTX_C_DRX_N1[39]
PCIE_PTX_C_DRX_P1[39]

PCIE_PRX_DTX_N2[39]
PCIE_PRX_DTX_P2[39]

PCIE_PTX_C_DRX_N2[39]

PCIE_PTX_C_DRX_P2[39]

PCIE_PRX_DTX_N3[39]
PCIE_PRX_DTX_P3[39]

PCIE_PTX_C_DRX_N3[39]
PCIE_PTX_C_DRX_P3[39]

PCIE_PRX_DTX_N4[39]

C C

Express card slot

GIGA LAN

WLAN

Card Reader

B B

PCIE_PRX_DTX_P4[39]

PCIE_PTX_C_DRX_N4[39]

PCIE_PTX_C_DRX_P4[39]

PCIE_PRX_EXPTX_N5[39]
PCIE_PRX_EXPTX_P5[39]

PCIE_PTX_EXPRX_N5[39]
PCIE_PTX_EXPRX_P5[39]

PCIE_PRX_DTX_N6[29]
PCIE_PRX_DTX_P6[29]

PCIE_PTX_C_DRX_N6[29]

PCIE_PTX_C_DRX_P6[29]

PCIE_PRX_DTX_N7[25]
PCIE_PRX_DTX_P7[25]

PCIE_PTX_C_DRX_N7[25]
PCIE_PTX_C_DRX_P7[25]

PCIE_PRX_DTX_N8[39]
PCIE_PRX_DTX_P8[39]

PCIE_PTX_C_DRX_N8[39]

PCIE_PTX_C_DRX_P8[39]

1 2

CH108 0.1U_0402_10V7KCH108 0.1U_0402_10V7K

1 2

CH109 0.1U_0402_10V7KCH109 0.1U_0402_10V7K

1 2

CH110 0.1U_0402_10V7KCH110 0.1U_0402_10V7K

1 2

CH111 0.1U_0402_10V7KCH111 0.1U_0402_10V7K

1 2

CH27 0.1U_0402_10V7KCH 27 0.1U _0402_10V7K

1 2

CH28 0.1U_0402_10V7KCH 28 0.1U _0402_10V7K

1 2

CH29 0.1U_0402_10V7KCH29 0.1U_0402_10V7K

1 2

CH30 0.1U_0402_10V7KCH30 0.1U_0402_10V7K

1 2

CH100 0.1U_0402_ 10V7KCH100 0.1U_0402_10V7K

1 2

CH99 0.1U_0402_10V7KCH99 0.1U_0402_10V7K

1 2

CH31 0.1U_0402_10V7KCH31 0.1U_0402_10V7K

1 2

CH32 0.1U_0402_10V7KCH32 0.1U_0402_10V7K

1 2

CH33 0.1U_0402_10V7KCH 33 0.1U _0402_10V7K

1 2

CH34 0.1U_0402_10V7KCH 34 0.1U _0402_10V7K

1 2

CH35 0.1U_0402_10V7KCH35 0.1U_0402_10V7K

1 2

CH36 0.1U_0402_10V7KCH36 0.1U_0402_10V7K

+1.5VS

+1.5VS

4

PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1

PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1

PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2

PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2

PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3

PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3

PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4

PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4

PCIE_PRX_EXPTX_N5
PCIE_PRX_EXPTX_P5

PCIE_PTX_EXPRX_N5_C
PCIE_PTX_EXPRX_P5_C

PCIE_PRX_DTX_N6
PCIE_PRX_DTX_P6

PCIE_PTX_DRX_N6
PCIE_PTX_DRX_P6

PCIE_PRX_DTX_N7
PCIE_PRX_DTX_P7

PCIE_PTX_DRX_N7
PCIE_PTX_DRX_P7

PCIE_PRX_DTX_N8
PCIE_PRX_DTX_P8

PCIE_PTX_DRX_N8
PCIE_PTX_DRX_P8

1 2

RH160 0_0402_5%RH160 0_0402_5%

1 2

RH164 7.5K_0402_1%RH164 7.5K_04 02_1%

PCH_PCIE_IREF

PCH_PCIE_RCOMP

AW31

PERN1/USB3RN3

AY31

PERP1/USB3RP3

BE32

PETN1/USB3TN3

BC32

PETP1/USB3TP3

AT31

PERN2/USB3RN4

AR31

PERP2/USB3RP4

BD33

PETN2/USB3TN4

BB33

PETP2/USB3TP4

AW33

PERN_3

AY33

PERP_3

BE34

PETN_3

BC34

PETP_3

AT33

PERN_4

AR33

PERP_4

BE36

PETN_4

BC36

PETP_4

AW36

PERN_5

AV36

PERP_5

BD37

PETN_5

BB37

PETP_5

AY38

PERN_6

AW38

PERP_6

BC38

PETN_6

BE38

PETP_6

AT40

PERN_7

AT39

PERP_7

BE40

PETN_7

BC40

PETP_7

AN38

PERN_8

AN39

PERP_8

BD42

PETN_8

BD41

PETP_8

BE30

PCIE_IREF

BC30

TP11

BB29

TP6

BD29

PCIE_RCOMP

LYNXPOINT_BGA695

LYNXPOINT_BGA695

UH1I

UH1I

LPT_PCH_M_EDS

LPT_PCH_M_EDS

PCIe

PCIe

9 OF 11

9 OF 11

USB

USB

3

REV = 5

REV = 5

USB2N0
USB2P0
USB2N1
USB2P1
USB2N2
USB2P2
USB2N3
USB2P3
USB2N4
USB2P4
USB2N5
USB2P5
USB2N6
USB2P6
USB2N7
USB2P7
USB2N8
USB2P8
USB2N9

USB2P9
USB2N10
USB2P10
USB2N11
USB2P11
USB2N12
USB2P12
USB2N13
USB2P13

USB3RN1
USB3RP1

USB3TN1
USB3TP1

USB3RN2
USB3RP2

USB3TN2
USB3TP2

USB3RN5
USB3RP5

USB3TN5
USB3TP5

USB3RN6
USB3RP6

USB3TN6
USB3TP6

USBRBIAS#

USBRBIAS

TP24
TP23

OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43

OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14

B37

USBP0-

D37

USBP0+

A38

USBP1-

C38

USBP1+

A36
C36
A34
C34
B33

USBP4-

D33

USBP4+

F31

USBP5-

G31

USBP5+

K31

USBP6-

L31

USBP6+

G29

USBP7-

H29

USBP7+

A32

USBP8-

C32

USBP8+

A30

USBP9-

C30

USBP9+

B29

USBP10-

D29

USBP10+

A28

USBP11-

C28

USBP11+

G26

USBP12-

F26

USBP12+

F24

USBP13-

G24

USBP13+

AR26

USB3RN1

AP26

USB3RP1

BE24

USB3TN1

BD23

USB3TP1

AW26

USB3RN2

AV26

USB3RP2

BD25

USB3TN2

BC24

USB3TP2

AW29

USB3RN5

AV29

USB3RP5

BE26

USB3TN5

BC26

USB3TP5

AR29

USB3RN6

AP29

USB3RP6

BD27

USB3TN6

BE28

USB3TP6

K24

USBRBIAS

K26

M33
L33

P3

WWAN_DE T#_PCH

V1

USB_OC1#_R

U2

USB_OC2#

P1

USB_OC3#

M3

USB_OC4#_R

T1

dGPU_HPD_INTR

N2
M1

2

USBP0- [33]

USBP0+ [33]

USBP1- [40]

USBP1+ [40]

USBP4- [39]

USBP4+ [39]

USBP5- [39]

USBP5+ [39]

USBP6- [39]

USBP6+ [39]

USBP7- [37]

USBP7+ [37]

USBP8- [28]

USBP8+ [28]

USBP9- [39]

USBP9+ [39]

USBP10- [22]

USBP10+ [22]

USBP11- [33]

USBP11+ [33]

USBP12- [25]

USBP12+ [25]

USBP13- [25]

USBP13+ [25]

USB3RN1 [33]

USB3RP1 [33]

USB3TN1 [33]

USB3TP1 [33]

USB3RN2 [40]

USB3RP2 [40]

USB3TN2 [40]

USB3TP2 [40]

USB3RN5 [39]

USB3RP5 [39]

USB3TN5 [39]

USB3TP5 [39]

USB3RN6 [39]

USB3RP6 [39]

USB3TN6 [39]

USB3TP6 [39]

10/26 Change PCH.P3 and RPH2.4 connection to WWAN_DET#_PCH

07/18 Change net name to TB_HOT_PLUG# follow HP request.
09/11 Delete RH165

----->Docking USB 3.0

----->USB 3.0 Walkup port 2

----->NA

----->NA

----->USB 3.0 Walkup port 3

----->USB 3.0 Walkup port 4

----->Express card slot

----->Smart card reader

----->Finger Print Reader

----->Walkup USB 2.0 port

----->USB Camera

----->Docking USB 2.0 port

----->WWAN

----->BT/WLAN Combo

----->Docking USB 3.0

----->USB 3.0 Walkup port 2

----->USB 3.0 Walkup port 3

----->USB 3.0 Walkup port 4

WWAN_DE T#_PCH [25]

07/23 Delete off page symbol

dGPU_HPD_INTR [35]
LED_LINK_LAN#_R [29]
TB_HOT_PLUG# [39]

1

USBRBIAS

CAD NOTE:
Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15 mils.

09/11 Change RPH1.3
connection to TB_HOT_PLUG#

TB_HOT_PLUG#
LED_LINK_LAN#_R

WWAN_DE T#_PCH

07/23 Modify pin define for layout smooth

12

USB_OC4#_R

USB_OC3#

10K_1206_8P4R_5%

10K_1206_8P4R_5%

dGPU_HPD_INTR
USB_OC2#
USB_OC1#_R

10K_1206_8P4R_5%

10K_1206_8P4R_5%

22.6_0402_1%

22.6_0402_1%

RH159

RH159

4 5
3 6
2 7
1 8

4 5
3 6
2 7
1 8

RPH1

RPH1

RPH2

RPH2

+3V_PCH

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2012/03/23 2011/06/29

2012/03/23 2011/06/29

2012/03/23 2011/06/29

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PCH-PCIE,USB

PCH-PCIE,USB

PCH-PCIE,USB

LA-9241P

LA-9241P

LA-9241P

1

17 56Thursday, December 20, 2012

17 56Thursday, December 20, 2012

17 56Thursday, December 20, 2012

0.5

0.5

0.5

5

13

+3VS

RH167 10K_0402_5%RH167 10K_0402_5%

RH169 100K_0402_5%RH169 100K_0402_5%

RH171 10K_0402_5%RH171 10K_0402_5%

RH175 8.2K_0402_5%RH175 8.2K_0402_5%

D D

C C

RH177 10K_0402_5%RH177 10K_0402_5%

RH172 10K_0402_5%RH172 10K_0402_5%

RH173 10K_0402_5%RH173 10K_0402_5%

RH178 10K_0402_5%RH178 10K_0402_5%

RH240 10K_0402_5%RH240 10K_0402_5%

RH241 10K_0402_5%RH241 10K_0402_5%

+3V_PCH

RH182 10K_0402_5%RH182 10K_0402_5%

RH183 10K_0402_5%RH183 10K_0402_5%

RH184 10K_0402_5%

RH184 10K_0402_5%

RH185 10K_0402_5%RH185 10K_0402_5%

RH176 10K_0402_5%RH176 10K_0402_5%

+3VDS

RH248 100K_0402_5%RH248 100K_0402_5%

10/25 Add LANWAKE# PU RH248 to +3VDS

+3V_PCH

4.7K_0402_5%

4.7K_0402_5%

RH193

RH193

1 2

PCH_GPIO28

1K_0402_1%

1K_0402_1%

12

@RH194

@

RH194

12

PCH_GPIO0

12

OCP_OC#

12

07/06 Add PU resistor

12

12

12

@

@

12

07/06 Change for NFC
07/23 Follow VBK10.
10/24 Install RH185

12

12

ODD_EN

DGPU_PWROK

DOCK_ID0

DOCK_ID1

KBC_SIO_RST#

EC_SCI#

THERM_SCI#

WWA N_TRANSMIT_OFF#

PCH_GPIO24

PCH_GPIO8

LAN_DIS#

NFC_INT

FPR_LOCK#

1 2

1 2

1 2

1 2

1 2

1 2

1 2

10/24 Change RH176.2 connection to GND. Install RH176

LANWAKE#

OCP_PWM_OUT[30]

07/23 Correct Net name

07/06 Follow HP's GPIO table

+3VS

2

G

G

WWA N_TRANSMIT_OFF#[25]

07/23 Delete PCH_GPIO24 off page symbol
07/23 Delete FN_CLK2 off page symbol
08/01 Change net name to mSATA_DET#
10/26 Change net name to PCH_GPIO_35

10/26 Change net name to PCH_GPIO_36
08/01 Change net name to Sec_HDD_DET
07/23 Delete PCH_GPIO37 off page symbol

07/06 Change for NFC

1 2

RH181 1K_0402_1%RH181 1K_0402_1%

1 2

RH180 100K_0402_5%RH180 100K_0402_5%

1 2

RH170 100K_0402_5%RH170 100K_0402_5%

Q582N7002KW_SOT323-3

Q582N7002KW_SOT323-3

D

D

S

S

EC_SCI#[30]

DGPU_PWROK[35]

LANWAKE#[29]

FPR_LOCK#[28]

DGPU_PRSNT#[35]

D3E_WAKE#

KBC_SIO_RST#[30,32]

GPS_XMIT_OFF#[25]

PCH_GPIO15

PCH_GPIO_35

PCH_GPIO34

4

PCH_GPIO0

OCP_OC#

EC_SCI#

THERM_SCI#

PCH_GPIO8

LAN_DIS#[29]

KBL_DET#[38]

NFC_INT[39]

ODD_EN[23]

08/01 Change net name to mSATA_DET#
10/26 Change RH180.2 connection to PCH_GPIO_35.
Change RH180.1 connection to +3VS

PCH_GPIO8

LAN_DIS#

PCH_GPIO15

KBL_DET#

DGPU_PWROK

WWA N_TRANSMIT_OFF#

PCH_GPIO24

LANWAKE#

PCH_GPIO28

PCH_GPIO34

PCH_GPIO_35

PCH_GPIO_36

PCH_GPIO37

DOCK_ID0

DOCK_ID1

FPR_LOCK#

DGPU_PRSNT#

NFC_INT

ODD_EN

D3E_WAKE#

KBC_SIO_RST#

GPS_XMIT_OFF#

UH1F

UH1F

AT8

BMBUSY#/GPIO0

F13

TACH1/GPIO1

A14

TACH2/GPIO6

G15

TACH3/GPIO7

Y1

GPIO8

K13

LAN_PHY_PWR_CTRL/GPIO12

AB11

GPIO15

AN2

SATA4GP/GPIO16

C14

TACH0/GPIO17

BB4

SCLOCK/GPIO22

Y10

GPIO24

R11

GPIO27

AD11

GPIO28

AN6

GPIO34

AP1

GPIO35/NMI#

AT3

SATA2GP/GPIO36

AK1

SATA3GP/GPIO37

AT7

SLOAD/GPIO38

AM3

SDATAOUT0/GPIO39

AN4

SDATAOUT1/GPIO48

AK3

SATA5GP/GPIO49

U12

GPIO57

C16

TACH4/GPIO68

D13

TACH5/GPIO69

G13

TACH6/GPIO70

H15

TACH7/GPIO71

BE41

VSS

BE5

VSS

C45

VSS

A5

VSS

LYNXPOINT_BGA695

LYNXPOINT_BGA695

LPT_PCH_M_EDS

LPT_PCH_M_EDS

3

GPIO

GPIO

6 OF 11

6 OF 11

2

+3VS

REV = 5

REV = 5

CPU/Misc

CPU/Misc

AN10

TP14

AY1

PECI

AT6

RCIN#

THRMTRIP#

AV3

AV1

AU4

N10

VSS

A2

VSS

A41

VSS

A43

VSS

A44

VSS

B1

VSS

B2

VSS

B44

VSS

B45

VSS

BA1

VSS

BC1

VSS

BD1

VSS

BD2

VSS

BD44

VSS

BD45

VSS

BE2

VSS

BE3

VSS

D1

VSS

E1

VSS

E45

VSS

A4

VSS

PROCPWRGD

PLTRST_PROC#

NCTF

NCTF

10/26 Delete A20GATE off page symbol

A20GATE

RCIN#

H_CPUPWRGD

PCH_THERMTRIP#_R

CPU_PLTRST#

T104PAD~D @T104PAD~D @

RCIN#

H_CPUPWRGD [5]

CPU_PLTRST# [5]

A20GATE

RCIN#

10/29 Change RH179 to 100ohms

RH179 100_0402_5%RH179 100_0402_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

CH37

CH37

2

12

RH16610K_0402_5% RH16610K_0402_5%

12

RH16810K_0402_5% RH16810K_0402_5%

12

PCH_THERMTRIP#_R

+1.05VS

PCH_THERMTRIP#_R [24,35,5]

1

08/01 Change net name to Sec_HDD_DET

PLL ON DIE VR ENABLE

ENABLED - HIGH(DEFAULT)

B B

DISABLED - LOW

Config

USB X4,PCIEX8,SATAX6

GPIO16,49

11

+3VS

1 2

RH197 10K_0402_5%RH197 10K_0402_5%

RH199 10K_0402_5%RH199 10K_0402_5%

08/03 Delete RH201, RH202

12

KBL_DET#

DGPU_PRSNT#

SATA2GP/GPIO36 , SATA3GP/GPIO37 SAMPLED AT RISING EDGE OF PWROK.
WEAK INTERNAL PULL-DOWN.(WEAK INTERNAL PULL-DOWN IS DISABLED AFTER
PLRST_N DE-ASSERTS).
NOTE: THIS SIGNAL SHOLD NOT BE PULLED HIGH WHEN STRAP IS SAMPLED.

RH198 10K_0402_5%RH198 10K_0402_5%

RH200 10K_0402_5%RH200 10K_0402_5%

10/26 Change netname to PCH_GPIO_36

12

PCH_GPIO_36

12

PCH_GPIO37

01USB X6,PCIEX8,SATAX4

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/03/23 2011/06/29

2012/03/23 2011/06/29

2012/03/23 2011/06/29

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PCH -GPIO,MISC,NTFC

PCH -GPIO,MISC,NTFC

PCH -GPIO,MISC,NTFC

LA-9241P

LA-9241P

LA-9241P

1

18 56Thursday, December 20, 2012

18 56Thursday, December 20, 2012

18 56Thursday, December 20, 2012

0.5

0.5

0.5

5

D D

+1.05VS

10U_0603_6.3V6M

10U_0603_6.3V6M

1

CH38

C C

B B

CH38

2

+1.05VM

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CH39

CH39

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

CH49

CH49

2

1U_0402_6.3V6K

1

1

CH43

CH43

CH44

CH44

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CH51

CH51

CH50

CH50

2

2

+PCH_VCCDSW

4

AA24
AA26
AD20
AD22
AD24
AD26
AD28
AE18
AE20
AE22
AE24
AE26
AG18
AG20
AG22
AG24

Y26

U14

AA18

U18
U20
U22
U24
V18
V20
V22
V24
Y18
Y20
Y22

LYNXPOINT_BGA695

LYNXPOINT_BGA695

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

DCPSUSBYP
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW

LPT_PCH_M_EDS

LPT_PCH_M_EDS

Core

Core

PCIe/DMI

PCIe/DMI

VCCMPHY

VCCMPHY

7 OF 11

7 OF 11

CRT DAC

CRT DAC

FDI

FDI

HVCMOS

HVCMOS

USB3

USB3

SATA

SATA

3

+VCCADAC

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.01U_0402_16V7K

0.01U_0402_16V7K

1

CH40

CH40

2

REV = 5UH1G

REV = 5UH1G

VCCADAC1_5

VCCADACBG3_3

VCC3_3_R30
VCC3_3_R32

VSS

VCCVRM

VCCIO

VCCIO

DCPSUS1

VCCSUS3_3
VCCSUS3_3

DCPSUS3
DCPSUS3

VCCIO
VCCVRM
VCCVRM

VCCVRM

VCCIO

VCCVRM

VCCIO

VCCIO

VCCIO

VCCIO

VCCIO

VCCIO

VCCIO

P45

P43

M31

BB44

AN34

AN35

R30
R32

Y12

+PCH_USB_DCPSUS1

AJ30
AJ32

AJ26

+PCH_USB_DCPSUS3

AJ28
AK20
AK26
AK28

BE22

AK18

AN11

AK22

AM18
AM20
AM22
AP22
AR22
AT22

+3VS

+1.05VS

+1.05VS

1

2

T141 PAD

T141 PAD

T142 PAD

T142 PAD

1U_0402_6.3V6K

1U_0402_6.3V6K

CH55

CH55

1

1

2

@

@

@

@

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

CH42

CH42

CH41

CH41

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CH56

CH56

CH57

CH57

2

2

2

LH1

LH1

BLM18PG181SN1D_2P

BLM18PG181SN1D_2P

+1.05VS

1U_0402_6.3V6K

1U_0402_6.3V6K

12

+3V_PCH

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

+1.5VS

10U_0603_6.3V6M

10U_0603_6.3V6M

1

CH58

CH58

CH59

CH59

2

1

+1.5VS

+1.5VS

+1.05VS

+3VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

CH47

CH47

2

CH48

CH48

+1.5VS

+1.5VS

10U_0603_6.3V6M

10U_0603_6.3V6M

1

@

@

CH53

CH53

10U_0603_6.3V6M

10U_0603_6.3V6M

2

1

@

@

CH54

CH54

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1

@

@

CH45

1

2

CH45

CH46

CH46

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

@

@

CH52

CH52

2

1 2

RH204 5.11_0402_1%~DRH204 5.11_0402_1%~D

+PCH_VCCDSW_R

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CH61

CH61

2

A A

5

+PCH_VCCDSW

07/20 Delete CH60, CH62, CH63

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2012/03/23 2011/06/29

2012/03/23 2011/06/29

2012/03/23 2011/06/29

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PCH- Power

PCH- Power

PCH- Power

LA-9241P

LA-9241P

LA-9241P

1

19 56Thursday, December 20, 2012

19 56Thursday, December 20, 2012

19 56Thursday, December 20, 2012

0.5

0.5

0.5

5

D D

+3V_PCH

0.1U_0402_10V6K

0.1U_0402_10V6K

+1.05VS

1

CH65

CH65

0.1U_0402_10V6K

0.1U_0402_10V6K

2

C C

+1.05VS_VCC+1.05VS

LH2

LH2

1 2

4.7UH_LQM18FN4R7M00D_20%

4.7UH_LQM18FN4R7M00D_20%

+3VS

1

CH67

CH67

0.1U_0402_10V6K

0.1U_0402_10V6K

2

+1.05VS

CH68

CH68

1

0.1U_0402_10V6K

2

0.1U_0402_10V6K

+1.5VS

1

CH70

CH70

07/19 Non Install CH101

10U_0603_6.3V6M

10U_0603_6.3V6M

07/20 Delete CH102

1

2

CH72

CH72

2

+1.05VS_VCC

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CH81

CH81

CH80

CH80

2

2

4

@

T143PAD@T143PAD

+1.05VS

+3VS

09/24 Change netname

+1.05VS

+1.05VS_VCC

R24
R26
R28
U26

M24

U35

U30

S2

AF34

AP45

M29

M26

U32

AD34

AA30
AA32

AD35

AG30
AG32

AD36

AE30
AE32

UH1H

UH1H

VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3

VSS

VCCUSBPLL

L24

VCC3_3

VCCIO

V28

VCCIO

V30

VCCIO

Y30

VCCIO

Y35

DCPSUS2

VCCVRM

VCC

Y32

VCCCLK

VCCCLK3_3

L29

VCCCLK3_3

L26

VCCCLK3_3
VCCCLK3_3

VCCCLK3_3

V32

VCCCLK3_3

VCCCLK

VCCCLK
VCCCLK

VCCCLK

VCCCLK
VCCCLK

VCCCLK

VCCCLK
VCCCLK

LYNXPOINT_BGA695

LYNXPOINT_BGA695

LPT_PCH_M_EDS

LPT_PCH_M_EDS

8 OF 11

8 OF 11

3

REV = 5

REV = 5

VCCSUS3_3

GPIO/LPC

GPIO/LPC

VCCSUS3_3

VCCDSW3_3

USB

USB

DCPSST

VCC3_3
VCC3_3
VCC3_3

VCCIO

Azalia

Azalia

VCCSUSHDA

VCCSUS3_3

RTC

RTC

CPU

CPU

ICC

ICC

SPI

SPI

Fuse

Fuse

VCCRTC

DCPRTC
DCPRTC

V_PROC_IO
V_PROC_IO

VCCSPI

VCC
VCC

VCCASW

VCCASW

VCCVRM

Thermal

Thermal

VCC3_3

VCC3_3

+3V_PCH

CH104

R20
R22

A16

AA14

AE14
AF12
AG14

U36

CH104

1 2

0.1U_0402_10V6K

0.1U_0402_10V6K

+PCH_VCCDSW3_3

+PCH_VCCSST

CH66 0.1U_0402_10V6KCH66 0.1U_0402_10V6K

+1.05VS

A26

K8

A6

P14

+PCH_DCPRTC

P16

+1.05VS

AJ12
AJ14

07/25 Change power rail

AD12

P18
P20

L17

R18

AW40

AK30

CH74 0.1U_0402_10V7K~DCH74 0.1U_0402_10V7K~D

CH105 0.1U_0402_10V6KCH105 0.1U_0402_10V6K
CH83 0.1U_0402_10V6KCH83 0.1U_0402_10V6K
CH84 1U_0402_6.3V6KCH84 1U_0402_6.3V6K

+1.05VM

+1.5VS

AK32

1 2

1 2

1 2
1 2
1 2

1

2

+3VS

1U_0402_6.3V6K

1U_0402_6.3V6K

CH92

CH92

+3VS

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CH79

CH79

2

0.1U_0402_10V6K

0.1U_0402_10V6K

1

CH85

CH85

2

0.1U_0402_10V6K

0.1U_0402_10V6K

10/18 Install RH209. Uninstall RH208

CH64

CH64

10/23 Install RH208. Uninstall RH209

09/11 Delete RH226

1

+3V_PCH

RH2080_0402_5% RH2080_0402_5%

12

12

RH2090_0402_5% @ RH2090_0402_5% @

+3VDS

+3VS

0.01U_0402_16V7K_X7R

0.01U_0402_16V7K_X7R

CH69

CH69

1

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

CH71

CH71

2

+3V_PCH

+3V_PCH

+3V_PCH

1U_0402_6.3V6K

+RTCVCC

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

1

1

CH76

CH76

CH75

CH75

2

2

1U_0402_6.3V6K

1

CH73

CH73

1U_0402_6.3V6K

1U_0402_6.3V6K

2

1

CH77

CH77

2

2

B B

+1.05VS

09/24 Delete RH213, RH216, and change netname.

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

CH87

CH87

1

1

@

@

CH86

CH86

2

2

1U_0402_6.3V6K

CH88

CH88

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CH89

CH89

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CH90

CH90

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CH91

CH91

1

2

Place near pin AP45 Place near pin Y32,AA30,AA32 Place near pin AD34 Place near pin AD35,AD36 Place near pin AG30,AG32,AE30,AE32

+3VS

1U_0402_6.3V6K

1U_0402_6.3V6K

CH93

CH93

1

2

A A

5

Place near pin M29 Place near pin L29 Place near pin L26,M26 Place near pin U32,V32

1U_0402_6.3V6K

1U_0402_6.3V6K

CH94

CH94

1

2

4

1U_0402_6.3V6K

1U_0402_6.3V6K

CH95

CH95

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CH96

CH96

1

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/03/23 2011/06/29

2012/03/23 2011/06/29

2012/03/23 2011/06/29

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH - Power

PCH - Power

PCH - Power

LA-9241P

LA-9241P

LA-9241P

20 56Thursday, December 20, 2012

20 56Thursday, December 20, 2012

20 56Thursday, December 20, 2012

1

0.5

0.5

0.5

5

D D

AL34

VSS

AL38

VSS

AL8

VSS

AM14

VSS

AM24

VSS

AM26

VSS

AM28

VSS

AM30

VSS

AM32

VSS

AM16

VSS

AN36

VSS

AN40

VSS

AN42

VSS

AN8

VSS

AP13

VSS

AP24

VSS

AP31

VSS

AP43

C C

B B

VSS

AR2

VSS

AK16

VSS

AT10

VSS

AT15

VSS

AT17

VSS

AT20

VSS

AT26

VSS

AT29

VSS

AT36

VSS

AT38

VSS

D42

VSS

AV13

VSS

AV22

VSS

AV24

VSS

AV31

VSS

AV33

VSS

BB25

VSS

AV40

VSS

AV6

VSS

AW2

VSS

F43

VSS

AY10

VSS

AY15

VSS

AY20

VSS

AY26

VSS

AY29

VSS

AY7

VSS

B11

VSS

B15

VSS

LYNXPOINT_BGA695

LYNXPOINT_BGA695

UH1J

UH1J

LPT_PCH_M_EDS

LPT_PCH_M_EDS

4

REV = 5

REV = 5

K39

VSS

L2

VSS

L44

VSS

M17

VSS

M22

VSS

N12

VSS

N35

VSS

N39

VSS

N6

VSS

P22

VSS

P24

VSS

P26

VSS

P28

VSS

P30

VSS

P32

VSS

R12

VSS

R14

VSS

R16

VSS

R2

VSS

R34

VSS

R38

VSS

R44

VSS

R8

VSS

T43

VSS

U10

VSS

U16

VSS

U28

VSS

U34

VSS

U38

VSS

U42

VSS

U6

VSS

V14

VSS

V16

VSS

V26

VSS

V43

VSS

W2

VSS

W44

VSS

Y14

VSS

Y16

VSS

Y24

VSS

Y28

VSS

Y34

VSS

Y36

VSS

Y40

VSS

Y8

VSS

10 OF 11

10 OF 11

3

LPT_PCH_M_EDS

LPT_PCH_M_EDS

UH1K

UH1K

AA16

VSS

AA20

VSS

AA22

VSS

AA28

VSS

AA4

VSS

AB12

VSS

AB34

VSS

AB38

VSS

AB8

VSS

AC2

VSS

AC44

VSS

AD14

VSS

AD16

VSS

AD18

VSS

AD30

VSS

AD32

VSS

AD40

VSS

AD6

VSS

AD8

VSS

AE16

VSS

AE28

VSS

AF38

VSS

AF8

VSS

AG16

VSS

AG2

VSS

AG26

VSS

AG28

VSS

AG44

VSS

AJ16

VSS

AJ18

VSS

AJ20

VSS

AJ22

VSS

AJ24

VSS

AJ34

VSS

AJ38

VSS

AJ6

VSS

AJ8

VSS

AK14

VSS

AK24

VSS

AK43

VSS

AK45

VSS

AL12

VSS

AL2

VSS

BC22

VSS

BB42

VSS

LYNXPOINT_BGA695

LYNXPOINT_BGA695

11 OF 11

11 OF 11

REV = 5

REV = 5

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

B19
B23
B27
B31
B35
B39
B7
BA40
BD11
BD15
BD19
AY36
AT43
BD31
BD35
BD39
BD7
D25
AV7
F15
F20
F29
F33
BC16
D4
G2
G38
G44
G8
H10
H13
H17
H22
H24
H26
H31
H36
H40
H7
K10
K15
K20
K29
K33
BC28

2

1

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2012/03/23 2011/06/29

2012/03/23 2011/06/29

2012/03/23 2011/06/29

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PCH - GND

PCH - GND

PCH - GND

LA-9241P

LA-9241P

LA-9241P

1

21 56Thursday, December 20, 2012

21 56Thursday, December 20, 2012

21 56Thursday, December 20, 2012

0.5

0.5

0.5

5

LCD POWER CIRCUIT

12

U47

1

C498

C498
4700P_0402_16V7K

4700P_0402_16V7K

2

USB20_N10_R

USB20_P10_R

U47

3

ON

1

VIN

2

VIN

4

VBIAS

6

CT

TPS22965DSGR_SON8_2X2

TPS22965DSGR_SON8_2X2

ENABLT_R

R490 100K_0402_5%R490 100K_0402_5%

ENAVDD[35]

D D

C C

07/23 Add C392 and C394 by RF request

ENABLT[35]

LID_SW#[30,38,39]

USBP10-[17]

USBP10+[17]

ENAVDD

09/26 Change C497 to 4.7u. Install R490

+3VDS +LCDVDD

C393

C393

C497

C497

1

1

18P_0402_50V8J

18P_0402_50V8J

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

@

@

2

2

+5VDS

09/25 Change LCDVDD power rail solution.
Delete R9, R10, R11, Q12, Q20, C1, C7, C8
Add U47, C497, C498, C499
Uninstall R494
11/06 Change C498 to 4700pF

1 2

ENABLT

R12

R12

2K_0402_5%

2K_0402_5%

12

R13

R13
100K_0402_5%

100K_0402_5%

D3

D3

1 2

RB751V-40_SOD323-2

RB751V-40_SOD323-2

9/20 Change to commond part.

1 2

R15 0_0402_5%@R15 0_0402_5%@

L3

L3

1

2

1

2

3

443

WCM-2012-900T_4P

WCM-2012-900T_4P

1 2

@

@

R16 0_0402_5%

R16 0_0402_5%

08/03 Swap pin define for layout smooth

VOUT

VOUT

GND
GND

4

7

8

5
9

C22 680P_0402_50V7KC22 680P_0402_50V7K

W=60mils

C394

C394

C499

C499

18P_0402_50V8J

18P_0402_50V8J

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

@

@

2

2

07/23 Add C392 and C394 by RF request

07/31 Delete Q21,Q22,R454,R14.

12

INV_PWM

3

Place closed to JLVDS1

+LCDVDD

1

C2

C2

10U_0603_6.3V6M

10U_0603_6.3V6M

2

07/06 Change for eDP MUX

EDP_SW_D3N[36]

EDP_SW_D3P[36]

EDP_SW_D2N[36]

EDP_SW_D2P[36]

EDP_SW_D1N[36]

EDP_SW_D1P[36]

EDP_SW_D0N[36]

EDP_SW_D0P[36]

EDC_SW_AUX[36]

EDC_SW_AUX#[36]

R179

R179

100K_0402_5%

100K_0402_5%

+3VS

INV_PWM[35]

INV_PWM

12

R491

R491

0.1U_0402_16V4Z

0.1U_0402_16V4Z

100K_0402_5%

100K_0402_5%

07/31 Delete +5VS_R_LOGO_KBL signal

D_MIC_CLK
D_MIC_DATA

C500

C500

1

@

@

2

09/25 Reserve C500, C501 for ESD request

10P_0402_25V8K

10P_0402_25V8K

1 2

C83

C83

@

@

1

2

R178

R178
100K_0402_5%

100K_0402_5%

1

2

C3

C3

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 2

+3VS

1

2

C501

C501

10P_0402_25V8K

10P_0402_25V8K

Camera_ON[14]

2

W=60mils

C449

C449

82P 50V J NPO 0402

82P 50V J NPO 0402

12

@

@

08/08 Reserve C449 by RF request

W=60mils

+LCDVDD

SG_IN[13]

INVPWR_B+

+5VS

EDP_SW_HPD
ENABLT_R

D_MIC_CLK

D_MIC_DATA

EDP_SW_HPD[36]

D_MIC_CLK[26]

D_MIC_DATA[26]

INVPWR_B+ B+

C4

680P_0402_50V7KC4680P_0402_50V7K

1

2

USB20_P10_R
USB20_N10_R

L1

L1

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

L2

L2

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

C5

1

SM010014520 3000ma

68P_0402_50V8JC568P_0402_50V8J

220ohm@100mhz

2

DCR 0.04

eDP PANEL Conn.

W=60mils

JEDP1

JEDP1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

35

35

36

36

G1

37

37

G2

38

38

G3

39

39

G4

40

40

G5

ACES_50398-04071-001

ACES_50398-04071-001

CONN@

CONN@

09/12 Modify JEDP1 symbol and footprint.
09/13 Modify JEDP1 symbol and footprint.
09/20 Correct circuit short issue, Modify pin define.

09/12 Modify JEDP1 symbol and footprint.

1

12

12

+5VS

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

C84

C84

C81

C81

1

1

2

2

41
42
43
44
45

11/01 Delete C23, C80, C82, C111

B B

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR D ISCLOSED TO ANY THIRD PA RTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

MAY BE USED BY OR D ISCLOSED TO ANY THIRD PA RTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

5

4

MAY BE USED BY OR D ISCLOSED TO ANY THIRD PA RTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

2011/06/29 2011/06/29

2011/06/29 2011/06/29

2011/06/29 2011/06/29

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

eDP/LVDS CONN & Camera

eDP/LVDS CONN & Camera

eDP/LVDS CONN & Camera

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

LA-9241P

LA-9241P

LA-9241P

Date: Sheet

Date: Sheet

Date: Sheet

of

of

of

22 56Thursday, December 20, 2012

22 56Thursday, December 20, 2012

22 56Thursday, December 20, 2012

1

0.5

0.5

0.5

5

4

3

2

1

SATA HDD CONN.

JHDD1

CONN@JHDD1

CONN@

1

GND

2

SATA_PTX_C_DRX_P0

A+

3

SATA_PTX_C_DRX_N0

A-

4

GND

5

SATA_PRX_C_DTX_N0

B-

6

SATA_PRX_C_DTX_P0

B+

7

GND

8

V33

9

V33

D D

23
24

+5V_ODD+5VS

1 2

@

@

R55 0_0 805_5%

R55 0_0 805_5%

S

S

D

D

13

CC52

1U_0402_6.3V6K

CC52

C C

R57

R57
100K_0402 _5%

100K_0402 _5%

Q25

Q25

2

ODD_EN

ODD_EN[18 ]

07/06 Correct Net name to follow HP GPIO table

G

G

1U_0402_6.3V6K

+5VS

1

12

2

R539

R539

1 2

ODD_EN#

100K_0402 _5%

100K_0402 _5%

13

D

D

07/12 Delete C54 and add R539 by HP request

S

S

2N7002_SOT23-3

2N7002_SOT23-3

Q24

Q24

G

G

SI2305CDS-T1-GE 3_SOT23-3

SI2305CDS-T1-GE 3_SOT23-3

2

SATA ODD CONN.

14
15
16
17

SANTA_203801-1

SANTA_203801-1

CONN@

CONN@

07/30 Modify JODD1 footprint.
08/03 Modify JODD1 footprint.
08/03 Change JODD1 pin 16 and 17 to NC.
10/31 Modify JODD1 footprint.

10

V33

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

Reserved

19

GND

GND

20

V12

GND

21

V12

22

V12

SANTA_199201-1

SANTA_199201-1

07/30 Modify JHHD1 footprint.

JODD1

JODD1

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

DP

9

+5V

10

+5V

GND

11

MD

GND

12

GND

GND

13

GND

GND

+5VS

SATA_PTX_C_DRX_P1
SATA_PTX_C_DRX_N1

SATA_PRX_C_DTX_N1
SATA_PRX_C_DTX_P1

1 2

R56 0_0402_5%@R56 0_0402_5%@

+5V_ODD

+5V_ODD

10U_0805_10V4K

10U_0805_10V4K

C55

C55

1

2

Placea caps. near
ODD CONN.

1

2

0.1U_0402_10V6K

0.1U_0402_10V6K

C56

C56

1

2

Place caps.
near HDD
CONN.

1 2
1 2

1 2
1 2

Place caps.
near ODD
CONN.

1 2

C490.01U_0402_ 16V7K_X7R C490.01U_0 402_16V7K_X7 R

1 2

C500.01U_0402_ 16V7K_X7R C500.01U_0 402_16V7K_X7 R

1 2

C510.01U_0402_ 16V7K_X7R C510.01U_0 402_16V7K_X7 R

1 2

C520.01U_0402_ 16V7K_X7R C520.01U_0 402_16V7K_X7 R

C53

C53

0.1U_0402_1 0V6K@

0.1U_0402_1 0V6K@

ODD_DA# [14]

0.1U_0402_10V6K

0.1U_0402_10V6K

68P_0402_50V8J

68P_0402_50V8J

C57

C57

1

1

2

2

11/07 Change C58 to 68pF

C410.01U_0402_ 16V7K_X7R C410.01U_0 402_16V7K_X7 R
C420.01U_0402_ 16V7K_X7R C420.01U_0 402_16V7K_X7 R

C430.01U_0402_ 16V7K_X7R C430.01U_0 402_16V7K_X7 R
C440.01U_0402_ 16V7K_X7R C440.01U_0 402_16V7K_X7 R

+5VS

100mils

10U_0805_10V4Z

10U_0805_10V4Z

C45

C45

1

2

Placea caps. near
HDD CONN.

C58

C58

1U_0402_6.3V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C46

C46

C47

C47

1

1

2

2

SATA_PTX_DRX_P1 [13 ]
SATA_PTX_DRX_N1 [13]

SATA_PRX_DTX_N1 [13]
SATA_PRX_DTX_P1 [13 ]

SATA_PTX_DRX_P0 [13 ]
SATA_PTX_DRX_N0 [13]

SATA_PRX_DTX_N0 [13]
SATA_PRX_DTX_P0 [13 ]

68P_0402_50V8J

68P_0402_50V8J

C48

C48

1

2

11/07 Change C48 to 68pF

B B

08/01 Modify SATA bus from port 2 to port 5

SATA_PRX_DTX_P5[ 13]
SATA_PRX_DTX_N5[13 ]

SATA_PTX_DRX_N5[13 ]
SATA_PTX_DRX_P5[ 13]

mSATA_DET#[ 32]

A A

5

1 2

C61 0.01U_0402_16V7KC61 0.01 U_0402_16V7K

1 2

C62 0.01U_0402_16V7KC62 0.01 U_0402_16V7K

1 2

C63 0.01U_0402_16V7KC63 0.01 U_0402_16V7K

1 2

C64 0.01U_0402_16V7KC64 0.01 U_0402_16V7K

mSATA_DET#

08/01 Delete Q48 and add R565
10/26 Delete R565

+3VS

4

SATA_PRX_C_DTX_P5
SATA_PRX_C_DTX_N5

SATA_PTX_C_DRX_N5
SATA_PTX_C_DRX_P5

+3VS

1 2

R1316 10K_0402_ 5%R1316 10K_0 402_5%

07/06 Change value to 10K

mSATA Conn.

JMINI1

JMINI1

2

112

4

334

6

556

8

778

10

9910

12

111112

14

131314

16

151516

18

171718

20

191920

22

212122

24

232324

26

252526

28

272728

30

292930

32

313132

34

333334

36

353536

38

373738

40

393940

42

414142

44

434344

46

454546

48

474748

50

494950

52

515152

54

GND153GND2

BELLW_80 003-1023

BELLW_80 003-1023

CONN@

CONN@

+3VS

+3VS

1

1

C59

C59

C60

C60

4.7U_0603_6 .3V6K

4.7U_0603_6 .3V6K

0.1U_0402_1 6V4Z

0.1U_0402_1 6V4Z

2

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR D ISCLOSED TO ANY THIRD PA RTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

MAY BE USED BY OR D ISCLOSED TO ANY THIRD PA RTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

3

MAY BE USED BY OR D ISCLOSED TO ANY THIRD PA RTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

2012/03/23 2010/03/31

2012/03/23 2010/03/31

2012/03/23 2010/03/31

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

IBEX-M(1/6)-HDA/JTAG/SATA

IBEX-M(1/6)-HDA/JTAG/SATA

IBEX-M(1/6)-HDA/JTAG/SATA

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-9241P

LA-9241P

LA-9241P

Date: Sheet

Date: Sheet

Date: Sheet

1

23 56Thursday, December 2 0, 2012

23 56Thursday, December 2 0, 2012

23 56Thursday, December 2 0, 2012

of

of

of

0.5

0.5

0.5

5

4

3

2

1

PWM Fan Control circuit

#4/11 change by HP requirement

FAN_PWM[30]

KBC_PROC_HOT#[30,5]

D D

#5/7 change by
HP requirement

C C

+VCCIO_OUT

KBC_PROC_HOT_R[47,5]

R17

R17

D4

D4

RB751V-40_SOD323-2

RB751V-40_SOD323-2

4.7K_0402_5%

4.7K_0402_5%

1 2

2K_0402_5%

2K_0402_5%

+3VS

R61

R61

1 2

150_0402_1%

150_0402_1%

R133

R133

2

B

B

12

12

13

C

C

E

E

1

2

Q65

Q65
MMBT3904_SOT23-3

MMBT3904_SOT23-3

2

C660.1U_0402_16V4Z C660.1U_0402_16V4Z

1

+5VS

07/12 Change U3 to TC7SET00 by HP request

5

U3

U3

P

INB

O

INA

G

TC7SET00FU _SSOP5

TC7SET00FU _SSOP5

3

R166

R166

1 2

47K_0402_5%

47K_0402_5%

4

+5VS

22_0402_5%

22_0402_5%

1 2

Notes:

Place Q65 close CPU side

U38

U38

1

SET

5

VCC

2

GND

4

HYST

3

R492 0_0402_5%R492 0_0402_5%

OT#

GMT G708T1U

GMT G708T1U

10/18 Install R492 and change R492.2 connection to PCH_THERMTRIP#_R

TACH_FAN_IN[30]

R60

R60

1 2

C65

C65

0.1U_0402_10V6K

0.1U_0402_10V6K

@

@

28K_0402_1%

28K_0402_1%

R1315

R1315

1 2

+5VS

JFAN1

JFAN1

1

1

2

2

3

3

4

4

12

07/12 Swap JFAN1 pin1 and pin 2

08/01 Change netname to KBC_PWR_ON
08/01 Change netname to KBC_PWR_ON

5

G5

6

G6

ACES_50273-0040N-001

ACES_50273-0040N-001

CONN@

CONN@

PCH_THERMTRIP#_R [18,35,5]

B B

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/03/23 2011/12/31

2012/03/23 2011/12/31

2012/03/23 2011/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Thermal/FAN

Thermal/FAN

Thermal/FAN

LA-9241P

LA-9241P

LA-9241P

1

24 56Thursday, December 20, 2012

24 56Thursday, December 20, 2012

24 56Thursday, December 20, 2012

0.5

0.5

0.5

A

WWAN

JMINI3

CONN@JMINI3

CONN@

WWAN_DET#_PCH
WLAN_WAKE#
WWAN_RSVD2

JSIM1

JSIM1

5

GND

6

VPP

7

I/O

4

NC

HB_5680629-SICR11

HB_5680629-SICR11

UIM_PWR

Q29

Q29

2

2

Q31

Q31

A

1

GND

3

GND
GND5FULL_CARD_PWR_OFF#
USB_D+7W_DISABLE1#

9

USB_D-

11

GND

GND_WWAN13AUDIO1

15

RESERVED

17

RESERVED

19

GND
USB3_TX-21UIM_RESET

23

USB3_TX+

25

GND

27

USB3RX-

29

USB3RX+

31

GND

33

NC

35

NC

37

GND

39

NC

41

NC

43

GND

45

NC

47

NC

49

GND

51

ANTCTL0

53

ANTCTL1

55

ANTCTL2

57

ANTCTL3

59

RESET#

61

PEDET

63

GND

65

GND

67

OC_USB3

LOTES_APCI0018-P002A

LOTES_APCI0018-P002A

U5

1

6

CH1

CH4

2

5

Vn

Vp

4

CH23CH3

S DIO(BR) NUP4301MR6T1 TSOP-6@U5S DIO(BR) NUP4301MR6T1 TSOP-6@

CONN@

CONN@

09/12 Modify JSIM1 symbol and footprint.

+3VS

07/31 modify Q4A circuit.
08/03 Q4.2 connection to BT_ON

47K

47K

10K

10K

1 3

13

10K

10K

47K

47K

+3VS

WWAN_DET#[13]

USBP12+[17]

08/07 Add R567 and connection
R567.1 to WLAN_WKAE#
10/16 Install R567

1 1

10/24 Delete R567

11/06 Change JMINI3.13
connection to signal
WWAN_DET#_PCH

2 2

07/25 JSIM1.7 connection to SUM_DET

3 3

4 4

USBP12-[17]

WWAN_DET#_PCH[17]

09/10 Delet T126

PLT_RST#
NGFF_WWAN_PEDET

@

T134PAD@T134PAD

11/06 Change JMINI3.65 connection to GND.

UIM_VPP[39]

@

T135PAD@T135PAD

NGFF_WWAN_USB3_OC

UIM_VPP
UIM_DATA
SIM_DET

R83

R83

47K_0402_5%

47K_0402_5%

@

@

07/31 Install Q29 and Q31

DTA114YKAGZT146_SOT23-3

DTA114YKAGZT146_SOT23-3

WL_LED#

WW_LED#

DTA114YKAGZT146_SOT23-3

DTA114YKAGZT146_SOT23-3

12

2

3P3VAUX

4

3P3VAUX

6
8
10

LED1#

12

AUDIO0

14
16

AUDIO2

18

AUDIO3

20

IUM_RFU

22
24

UIM_CLK

26

UIM_DATA

28

UIM_PWR

30

NC

32

GNSS0

34

GNSS1

36

GNSS2

38

GNSS3

40

GNSS4

42

NC

44

NC

46

NC

48

NC

50

NC

52

COEX3

54

COEX2

56

COEX1

58

SIM_DET

60

SUSCLK

62

3P3VAUX

64

3P3VAUX

66

3P3VAUX

68

GND1

69

GND2

1

UIM_PWR

VCC

2

UIM_RST

RST

3

UIM_CLK

CLK

18P_0402_50V8J

18P_0402_50V8J

1

C76

C76

C77

C77

2

9

GND

8

GND

@

@

10/25 Delete R89

2

BT_ON

WL_LED

WL_LED

07/06 Change to NFCC connector
07/24 Modify JMINI3 pin define.

+3V_WWAN

07/25 Modify JMINI3 pin define.
08/03 Modify JMINI3 footprint

WWAN_FULL_PWR
M_WXMIT_OFF#
WW_LED#

R6510K_0402_5% R6510K_0402_5%

12

UIM_RST
UIM_CLK
UIM_DATA
UIM_PWR

SIM_DET

+3V_WWAN

+3V_WWAN

D9

@D9

@

3

1

2

DAN217T146_SC59-3

DAN217T146_SC59-3

4.7U_0805_10V4Z

4.7U_0805_10V4Z

0.1U_0402_10V6K

0.1U_0402_10V6K

C78

C78

1

1

2

2

WWAN_DISABLE[30]

WL/BT_LED#

61

Q4A

Q4A
2N7002DW T/R7_SOT-363-6

2N7002DW T/R7_SOT-363-6

3

Q4B

Q4B

5

2N7002DW T/R7_SOT-363-6

2N7002DW T/R7_SOT-363-6

4

1 2

R94 100K_0402_5%R94 100K_0402_5%

GPS_XMIT_OFF# [18]

@

T128 PAD@T128 PAD

09/10 Delet T128

+3VS

09/10 Add R599 and R600

WWAN_FULL_PWR

WWAN_RSVD2

WWAN_TRANSMIT_OFF#[18]

R81

R81

10K_0402_5%

10K_0402_5%

10/24 Add PD R618
10/25 Delete R618

B

C70

C70

C69

39P_0402_50V8J@

C69

39P_0402_50V8J@

1

2

0.01U_0402_16V7K

0.01U_0402_16V7K

C72

C72

C73

C73

1

2

1 2

R599 10K_0402_5%R599 10K_0402_5%

R600 10K_0402_5%R600 10K_0402_5%

1 2

1 2

R84

R84

1 2

220K_0402_1%

220K_0402_1%

07/19 Delete C79

WL/BT_LED# [39]

B

+3V_WWAN

39P_0402_50V8J@

39P_0402_50V8J@

1

2

+3V_WWAN

0.1U_0402_10V6K

0.1U_0402_10V6K

1

2

2

C71

39P_0402_50V8J@

C71

39P_0402_50V8J@

1

2

C74

C74

1

2

1 2

+3VDS

G

G

4.7U_0805_10V4Z

4.7U_0805_10V4Z

D8

D8

S

S

D

D

1 3

WLAN

WLAN&BT Combo module circuits

BT_CRTL

BT_ON#

+3V_WWAN

M_WXMIT_OFF#

RB751V-40_SOD323-2

RB751V-40_SOD323-2

Q27

Q27
SI2305CDS-T1-GE3_SOT23-3

SI2305CDS-T1-GE3_SOT23-3

+3V_WWAN

7W

BT

BT

on module

on module

Enable

Disable

LOHI

HILO

MINI1_CLKREQ#[15]

For Wireless LAN

C

08/07 Add JMINI2.1 net name. Add R568
and connection R586.1 to KBC_DS3_EN

+3VS +3V_AOAC

2

G

G

1 3

D

S

D

S

Q69

Q69

2N7002KW_SOT323-3

2N7002KW_SOT323-3

CLK_PCI_DEBUG[15]

CL_CLK1[16]
CL_DATA1[16]
CL_RST1#[16]

C

10/16 Change R568.1 connection to KBC_WAKE#. Delete R64

R568 0_0402_5%@R568 0_0402_5%@

KBC_WAKE#[29,30]

PCH_PCIE_WAKE#[14]

PCIE_PTX_C_DRX_N7[17]
PCIE_PTX_C_DRX_P7[17]

2N7002_SOT23-3

2N7002_SOT23-3

BT_OFF[14]

1 2

1 2

0_0402_5%

0_0402_5%

CLK_PCIE_MINI1#[15]

CLK_PCIE_MINI1[15]

PLT_RST#

CLK_PCI_DEBUG

PCIE_PRX_DTX_N7[17]

PCIE_PRX_DTX_P7[17]

+3V_AOAC

10/24 Add R619, R620, R621

R619 0_0402_5%R619 0_0402_5%

1 2
1 2

R620 0_0402_5%R620 0_0402_5%
R621 0_0402_5%R621 0_0402_5%

1 2

+3V_AOAC

12

R85

R85
10K_0402_5%

10K_0402_5%

Q28

Q28

13

D

D

2

G

G

S

S

R67

R67

@

@

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

BT_ON

Issued Date

Issued Date

Issued Date

WLAN_WAKE#

D

WLAN

JMINI2

JMINI2

2

112

4

334

6

556

8

778

10

9910

12

111112

14

131314

16

151516

18

171718

20

191920

22

212122

24

232324

26

252526

28

272728

30

292930

32

313132

34

333334

36

353536

38

373738

40

393940

42

414142

44

434344

46

454546

48

474748

50

494950

52

515152

54

GND153GND2

BELLW_80003-1023

BELLW_80003-1023

CONN@

CONN@

07/19 Change power rail to +3VDS

2012/03/23 2010/03/31

2012/03/23 2010/03/31

2012/03/23 2010/03/31

D

#4/13 change by HP requirement

LPC_LFRAME#
LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0

D10 RB751V-40_SOD323-2D10 RB751V-40_SOD323-2

WL_LED#

Primary Power (mA)

Peak Normal

1000

330

500

R457 200K_0402_5%R457 200K_0402_5%

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C86

C86

2

Mini Card Power Rating

123

DGS

DGS

Power

+3VS

+3V

+1.5VS

+3VDS

+3V_AOAC

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

12

750

250

375

R458 0_0402_5%R458 0_0402_5%

1 2

11/06 Change R458 to 0ohm

12

R90

R90
1K_0402_5%

1K_0402_5%

07/19 Delete C85

Q30

Q30
AO3413L_SOT23-3

AO3413L_SOT23-3

LPC_LFRAME# [16,28,30,32]
LPC_LAD3 [16,28,30,32]
LPC_LAD2 [16,28,30,32]
LPC_LAD1 [16,28,30,32]
LPC_LAD0 [16,28,30,32]

WLAN_TRAMSIT_OFF# [15]
PLT_RST# [13,14,28,29,30,35,37,39,5]

USBP13- [17]

USBP13+ [17]

Auxiliary Power (mA)

Normal

250 (wake enable)

5 (Not wake enable)

WLAN_DISABLE [30]

08/01 Q68 and R459 uninstall
11/06 Delete Q68, R459

+3VDS

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

LA-9241P

LA-9241P

LA-9241P

Date: Sheet of

Date: Sheet of

Date: Sheet of

E

WLAN_TRAMSIT_OFF#

1

@

@

C375

C375

22P_0402_50V8J

22P_0402_50V8J

2

07/16 Add for ESD's request

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

WWAN/NAND mini

WWAN/NAND mini

WWAN/NAND mini

25 56Thursday, December 20, 2012

25 56Thursday, December 20, 2012

E

25 56Thursday, December 20, 2012

0.5

0.5

0.5

5

4

3

2

1

Notes:

Keep PVDD supply and speaker traces routed on the DGND plane.
Keep away from AGND and other analog signals

If Sense_A total length is greater than
6 inches, chagne C12 to 0.1uF

+AVDD_CODEC

+AVDD_CODEC

If Sense_B is un-used, then pull high
Sense_B to AVDD by 10Kohm resistor

07/06 Delete MIC_SENSE# circuit

AVDD1
AVDD2

PVDD1
PVDD2

SENSE_A
SENSE_B

PORTC_L
PORTC_R

PORTE_L
PORTE_R

PORTF_L

PORTF_R

PCBEEP

VREFFILT

CAP2

AVSS1
AVSS2
AVSS3

V-

+AVDD_CODEC

27
38

45
39

13
14

28
29
23

31
32

19
20
24

15
16

17
18

40
41

44
43

25

12

21
22
34
37

26
30
33

1

1

CA6

CA6

2

2

0.1U_0402_25V6

0.1U_0402_25V6

HP_OUT_L
HP_OUT_R

DOCK_LI_L_CODE C
DOCK_LI_R_COD EC

SPKL+
SPKL-

SPKR+
SPKR-

CA14 0.1U_0402_25V6CA14 0.1U_040 2_25V6

CA16

CA16

+5VS

CA8,CA10 near UA5 PIN45

CA7

CA7

1U_0402_6.3V6K

1U_0402_6.3V6K

SENSE_A
SENSE_B

12

1

1

CA21

CA21

2

2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

CA9,CA21 near UA5 PIN39

1

1

1

CA9

CA9

CA10

CA10

CA11

CA11

2

2

2

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

DOCK_HP_L_ CODEC [27]
DOCK_HP_R_ CODEC [27]

EXT_MIC_L [27]
EXT_MIC_JACK [27]
VREFOUT_MIC_JACK [27]

MONO_INMONO_INR

1

CA18

CA18

2

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

CA19

CA19

10U_0603_6.3V6M

10U_0603_6.3V6M

Place C209,C210,CA87,CA89 close to Codec

1

CA12

CA12

2

10U_0603_6.3V6M

10U_0603_6.3V6M

SENSE_A [27]
SENSE_B [27]

External MIC

HP_OUT_L [39]
HP_OUT_R [39]

DOCK_LI_L_CODE C [27]
DOCK_LI_R_COD EC [27]

SPKL+ [27]
SPKL- [27]

SPKR+ [27]
SPKR- [27 ]

Combo Jack

Headphone

Internal SPKR(front stereo speaker)

PLACE CLOSE TO U1 PIN 13

RA3 2.49K_0402_ 1%RA3 2.49K_0 402_1%

SENSE_A

SENSE_B

CA1 1000P_ 0402_50V7KCA1 10 00P_0402_50V7K

RA4 2.49K_0402_ 1%RA4 2.49K_0 402_1%

CA13 100 0P_0402_50V7K

CA13 100 0P_0402_50V7K

PLACE CLOSE TO U1 PIN 14

07/06 Delete MUTE LED circuit

1 2

1 2

1 2

1 2

@

@

07/23 Delete RA7

+3VS

D D

0.1U_0402_ 25V6

0.1U_0402_ 25V6

HDA_BITCLK_AUDIO

HDA_BITCLK_AUDIO[13 ]

HDA_SDOUT_AUD IO[13]

HDA_SYNC_AUDIO[13]

C C

B B

HDA_RST_AUDIO#[13]

D_MIC_CLK[22]

D_MIC_DATA[22]

09/20 Delete RA13, CA20

EC_MUTE#[30]

1 2

RA9

RA9

HDA_SDI0[13 ]

D_MIC_CLK

MUTE_LED_ CNTR[39]

2

1

33_0402_5 %@

33_0402_5 %@

10/11 Change RA14 to 0 ohm.

1

CA2

CA2

CA3

CA3

2

CA8

CA8

22P_0402_5 0V8J

22P_0402_5 0V8J

1 2

@

@

HDA_BITCLK_AUDIO

HDA_SDOUT_AUD IO

HDA_SYNC_AUDIO

HDA_SDI0 SDIN_CODEC

HDA_RST_AUDIO#

1 2

DH1 RB751V-40_SOD323-2DH1 RB751V-40_SOD323-2

9/20 Change to commond part.

RA27 10K_ 0402_5%RA27 10K_040 2_5%

+3VS

RA12 100 _0402_5%RA12 10 0_0402_5%
RA14 0_0 402_5%RA14 0 _0402_5%

+3VS

1

CA4

CA4

2

0.1U_0402_25V6

0.1U_0402_25V6

1U_0402_6.3V6K

1U_0402_6.3V6K

EAPD_L

1 2

12
12

REC_MUTE_ LED_CTRL
MUTE_LED_ CNTR

10K_0402_5 %

10K_0402_5 %
RA16

RA16

4.7U_0603_ 6.3V6K

4.7U_0603_ 6.3V6K

1 2

Place close to Codec

Place AVDD ,PVDD,and DVDD capacitor close to Codec

1

CA5

CA5
10U_0603_ 6.3V

RA113 3_0402_5% RA113 3_0402_5%

10U_0603_ 6.3V

2

12

D_MIC_CLK_L_ C
D_MIC_DATA_CD_MIC_DATA

CA15

CA15

1

2

UA1

UA1

1

DVDD_CORE

3

DVDD_IO

9

DVDD

6

HDA_BITCLK

5

HDA_SDO

10

HDA_SYNC

8

HDA_SDI

11

HDA_RST#

47

EAPD

2

DMIC_CLK/GPIO1

4

DMIC0/GPIO2

48

SPDIFOUT0/GPIO3

46

DMIC1/GPIO0/SPDIFOUT1

36

CAP+

35

CAP-

7

DVSS

42

PVSS

49

PAD

92HD91B2X5N LGXWCX8_QFN48_7X7

92HD91B2X5N LGXWCX8_QFN48_7X7

09/03 Change UA1 P/N

HP0_PORTA_L
HP0_PORTA_R

VREFOUT_A

HP1_PORTB_L
HP1_PORTB_R

VREFOUT_C/GPIO4

SPK_PORTD_+L
SPK_PORTD_-L

SPK_PORTD_+R

SPK_PORTD_-R

MONO_OUT

VREG(+2.5V)

+AVDD_CODEC

12

RA17

2

QA1A

QA1A

RA17
10K_0402_5 %

10K_0402_5 %

CA22

CA22

1 2

0.1U_0402_ 25V6

0.1U_0402_ 25V6

61

RA18

RA18

1 2

100K_0402_ 5%

100K_0402_ 5%

10K_0402_5 %

10K_0402_5 %

RA19

RA19

12

MONO_IN

1

CA26

CA26

0.01U_0402 _16V7K

0.01U_0402 _16V7K

2

680P_0603_ 50V7K

680P_0603_ 50V7K

1

2

+AVDD_CODEC

CA28

CA28

0.1U_0402_25V6

0.1U_0402_25V6

2

CA29

CA29
10U_0805_ 10V6K

10U_0805_ 10V6K

1

12

C87

C87

680P_0603_50V7K

680P_0603_50V7K

+5VS

W=40Mil

1 2

RA20

RA20

10K_0402_5 %

10K_0402_5 %

1

12

C88

C88

CA31

CA31

0.1U_0402_ 25V6

0.1U_0402_ 25V6

2

UA2

UA2

VOUT

1

VIN

BYPASS

3

EN

GND

HPA01085DBVR SOT 23 5P

HPA01085DBVR SOT 23 5P

5

4

2

REC_MUTE_ CTRL_KB [38]

2N7002KW _SOT323-3

2N7002KW _SOT323-3

13

D

D

1 2

2

G

G

S

S

Q75

Q75

07/20 HP's request.

HDA_SPKR[13]

SB Beep

HDA_SPKR

DMN66D0LD W-7_SOT363-6

DMN66D0LD W-7_SOT363-6

1 2

CA23 0.1U_0402_25V6@C A23 0.1U _0402_25V6@

1 2

CA24 0.1U_0402_25V6@C A24 0.1U _0402_25V6@

1 2

CA25 0.1U_0402_25V6@C A25 0.1U _0402_25V6@

1 2

CA27 0.1U_0402_25V6@C A27 0.1U _0402_25V6@

1 2

CA30 0.1U_0402_25V6@C A30 0.1U _0402_25V6@

1 2

RA21 0_080 5_5%RA21 0_0 805_5%

A A

REC_MUTE_ LED_CTRL

RA28

RA28

10K_0402_5 %

10K_0402_5 %

GNDAGND

RA53 need under or near UA5

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/03/23 2011/06/29

2012/03/23 2011/06/29

2012/03/23 2011/06/29

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Audio IDT 92HD91

Audio IDT 92HD91

Audio IDT 92HD91

LA-XXXXP

1

26 56Thursday, December 20, 20 12

26 56Thursday, December 20, 20 12

26 56Thursday, December 20, 20 12

0.5

0.5

0.5

5

Speaker Connector

SPKR+

SPKR+[26]

SPKR-

SPKR-[26]

SPKL+

SPKL+[26]

SPKL-

SPKL-[26]

D D

2200P_0402_50V7K

2200P_0402_50V7K

3.3_0402_5%

3.3_0402_5%

2200P_0402_50V7K

2200P_0402_50V7K

2200P_0402_50V7K

2200P_0402_50V7K

1

CA32

CA32

2

12

3.3_0402_5%

3.3_0402_5%

RA25

RA25

2200P_0402_50V7K

2200P_0402_50V7K

1

1

2

12

1

CA34

CA34

CA33

CA33

RA23

RA23

CA35

CA35

2

2

12

12

3.3_0402_5%

3.3_0402_5%

3.3_0402_5%

3.3_0402_5%

RA26

RA26

@

@

RA24

RA24

YSDA0502C C/A SOT-23

YSDA0502C C/A SOT-23

DA3

DA3

4

JSPKR1

JSPKR1

6

G6

5

G5

4

4

3

3

2

2

1

1

ACES_50273-0040N-001

ACES_50273-0040N-001

CONN@

CONN@

3

3

223

223

DA2

@DA2

@

YSDA0502C C/A SOT-23

YSDA0502C C/A SOT-23

1

1

1

1

07/16 Change P/N for ESD's request
07/20 Change P/N for ESD's request

3

VREFOUT_MIC_JACK[26]

EXT_MIC_JACK[26]

07/16 Delete DA1 for ESD's request

2

RA22

RA22

2.2K_0402_5%

2.2K_0402_5%

1

C89

C89

2

1U_0402_6.3V6K

1U_0402_6.3V6K

7/13 Move to small board

BK1608HS601-T_2P

BK1608HS601-T_2P

220P_0402_50V7K

220P_0402_50V7K

1

LA3

LA3

12

CA36

CA36

EXT_MIC_L2

1

2

EXT_MIC_L2 [39]

Need place near Audio Codec (UA5)

DOCK Audio

3

2

LA8

LA8

BK1608HS601-T_2P

BK1608HS601-T_2P

+AVDD_CODEC

8

U6A

U6A

+

OUT

-

4

R96

R96

1 2

C93

C93

100K_0402_5%

100K_0402_5%

1 2

15P_0402_50V8J

15P_0402_50V8J

12

P

1

G

TLV2462CDR_SO8

TLV2462CDR_SO8

R99 10K_0402_5%R99 10K_0402_5%

1

C96

C96
68P_0402_50V8J

68P_0402_50V8J

2

MIC_OUT

1 2

C90

C90

1U_0603_16V7

1U_0603_16V7

IN-

12

100K_0402_5%

100K_0402_5%

100K_0402_5%

100K_0402_5%

EXT_MIC_L [26]

+AVDD_CODEC

12

R103

R103

12

R105

R105

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

CC55

CC55

+AVDD_CODEC

8

U6B

U6B

5

P

+

7

OUT

6

-

1

2

0.1U_0402_16V7K

0.1U_0402_16V7K
C97

C97

2

1

G

TLV2462CDR_SO8

TLV2462CDR_SO8

4

+VREF_EQ

C C

07/06 Change C91 and C94 to 2.2uF as spec
10/11 Change C91 and C94 to 150u

C91

C91

1 2

20K_0402_1%

20K_0402_1%

R110

R110

1 2

150U_B2_6.3VM_R45M

150U_B2_6.3VM_R45M

C94

C94

1 2

150U_B2_6.3VM_R45M

150U_B2_6.3VM_R45M

20K_0402_1%

20K_0402_1%

R167

R167

2

12

DOCK_HP_L_CODEC[26]

DOCK_HP_R_CODEC[26]

DOCK_LI_L_CODEC[26]

B B

07/23 Combine with QA1B
11/05 Delete R174, QA1B. HP_SENSE# connection to R167.1

A A

DOCK_LI_R_CODEC[26]

HP_SENSE#[39]

DOCK_HPS#[33]

10/11 Change to AGND

100K_0402_5%

100K_0402_5%

+

+

+

+

12

R100

R100

CC53

CC53

1 2

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

CC54

CC54

1 2

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2K_0402_5%

2K_0402_5%

12

R108

R108

39.2K_0402_1%

39.2K_0402_1%

61

Q6A

Q6A

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

10/11 Change R97 and R98 to 1%

1 2

R97

R97

30_0402_1%

30_0402_1%

1 2

R98

R98

30_0402_1%

30_0402_1%

12

20K_0402_1%

20K_0402_1%
R101

R101

10/11 Change R102 and R104 to 1%

6.2K_0402_1%

6.2K_0402_1%

6.2K_0402_1%

6.2K_0402_1%

12

12

R107

@R107

@

R106

@R106

@

2K_0402_5%

2K_0402_5%

10/11 Non install R106 and R107

SENSE_A [26]

1 2

R102

R102

1 2

R104

R104

LINE_IN_SENSE[33]

BK1608HS601-T_2P

BK1608HS601-T_2P

BK1608HS601-T_2P

BK1608HS601-T_2P

220P_0402_50V7K

220P_0402_50V7K

DOCK_LINE_IN_L

DOCK_LINE_IN_R

100K_0402_5%

100K_0402_5%

LA6

LA6

LA7

LA7

12

12

CA39

CA39

20K_0402_1%

20K_0402_1%

R111

R111

1

2

R109

R109

5

12

DLINE_OUT_L [33]

DLINE_OUT_R [ 33]

1

CA40

CA40

220P_0402_50V7K

220P_0402_50V7K

2

DOCK_LINE_IN_L [33]

DOCK_LINE_IN_R [33]

SENSE_B [26]

12

3

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6
Q6B

Q6B

4

+VREF_EQ

10/11 Change C95 to 0.47U X5R

EXT_MIC_JACK

2

C92

C92

0.01U_0402_16V7K

0.01U_0402_16V7K

1

C95

C95

1 2

0.47U_0603_16V7X

0.47U_0603_16V7X

IN-

10/11 Change to AGND

5

4

10/11 Change to AGND

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2012/10/212012/03/23

2012/10/212012/03/23

2012/10/212012/03/23

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Audio SPK Conn/Jack/MIC

Audio SPK Conn/Jack/MIC

Audio SPK Conn/Jack/MIC

LA-9241P

LA-9241P

LA-9241P

1

27 56Thursday , December 20, 2012

27 56Thursday , December 20, 2012

27 56Thursday , December 20, 2012

of

of

of

0.5

0.5

0.5

5

+3VS

TPM1.2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C98

C98

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

D D

LPC_LAD0[16,25,30,32]
LPC_LAD1[16,25,30,32]
LPC_LAD2[16,25,30,32]
LPC_LAD3[16,25,30,32]

CLK_PCI_TPM[15]

LPC_LFRAME#[16,25,30,32]
PLT_RST#[13,14,25,29,30,35,37,39,5]
SIRQ[16,30,32]

+3VS

R119

R119

12

R122

R122

9635@

9635@

0_0402_5%

0_0402_5%

C C

LPC_PD#_TPM

PM_CLKRUN#[14,30,32]

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

PLT_RST#

PM_CLKRUN#_TPM

1 2

@

@

4.7K_0402_5%

4.7K_0402_5%

+3VS

12

R126

9635@R126

9635@

4.7K_0402_5%

4.7K_0402_5%

R129 0_0402_5%

R129 0_0402_5%

#4/15 Correct Net name.

B B

1

C99

C99

2

12

9656@

9656@

R177

R177

1 2

0_0402_5%

0_0402_5%

9635@

9635@

1

C100

C100

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

26
23
20
17

21
22
16
27
15

7

R123

R123

0_0402_5%

0_0402_5%

12

PM_CLKRUN#_TPM

U11

U11

LAD0
LAD1
LAD2
LAD3

SLB9656TT1.2

SLB9656TT1.2

SLB9656TT1.2

SLB9656TT1.2

SLB9656TT1.2SLB9656TT1.2

SLB9656TT1.2SLB9656TT1.2

LCLK
LFRAME#
LRESET#
SERIRQ
TEST
PP

BADDPLT_RST#

19

24

VDD

4

4

+3VS +3VDS

12

9656@

9656@

R112

R112

0_0402_5%

0_0402_5%

5

10

VDD

VDD

VDD

TESTB1/LRESET#

GND

GND

GND

GND

SLB9656TT1.2_TSSOP28

SLB9656TT1.2_TSSOP28

11

18

25

12

R113

R113

0_0402_5%

0_0402_5%

9656@

9656@

28

LPC_PD#_TPM

NC

9

BADD

8

TEST1

14

TPM_XTALO

NC

13

TPM_XTALI

NC

2

NC

6

GPIO

1

NC

3

NC

12

NC

07/26 Change U11 symbol and P/N to SLB9656.

12

R114

R114
0_0402_5%

0_0402_5%

9635@

9635@

1

C101

C101

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

T108 PAD @T108 PAD@
T109 PAD @T109 PAD@

TPM_XTALI

TPM_XTALO

Base I/O Address

0 = 02Eh

* 1 = 04Eh

12

R117

R117

9635@

9635@

4.7K_0402_5%

4.7K_0402_5%

CLK_PCI_TPM

C105

C105

12

R127

R127

@

@

Y1

32.768KHZ_12.5PF_FC-135

32.768KHZ_12.5PF_FC-135

1 2

C106

10M_0402_5%

10M_0402_5%

1 2

R120

R120

18P_0402_50V8J9635@

18P_0402_50V8J9635@

1 2

9635@Y1

9635@

1 2

18P_0402_50V8J

18P_0402_50V8J

+3VS

12

R115

R115

9635@

9635@

12

R116

R116

4.7K_0402_5%

4.7K_0402_5%

@

@

33_0402_5%@

33_0402_5%@

9635@C106

9635@

3

4.7K_0402_5%

4.7K_0402_5%

22P_0402_50V8J

22P_0402_50V8J

1 2

C102

C102

@

@

DDR_XDP_WAN_ SMBCLK[11,12,13,16,38,5]
DDR_XDP_WAN_ SMBDAT[11,12,13,16,38,5]

FPR_OFF[16]

R118 10K_0402_5%R118 10K_0402_5%

+3VS

12/12 Add Q85

2

ACCELEROMETER

+3VS

U9

1

Vdd_IO

4

SCL/SPC

6

SDA/SDI/SDO

7

SDO/SA0

12

12

R121

R121
0_0402_5%

0_0402_5%

12

R124

R124

@

@

0_0402_5%

0_0402_5%

+5VS

2

G

G

1 3

D

S

D

S

Q85

Q85

2N7002KW_SOT323-3

2N7002KW_SOT323-3

8

CS

2

NC

3

NC

USBP8-[17]
USBP8+[17]

FPR_LOCK#[18]

07/16 Change P/N for ESD's request

RH219

RH219

10K_0402_5%

10K_0402_5%

9

INT2

11

INT1

14

VDD

5

GND

12

GND

10

RES

13

RES

15

RES

16

RES

HP3DC2U9HP3DC2

07/06 Delete LED1

Finger printer

C107

C107

0.1U_0402_16V4Z

0.1U_0402_16V4Z

R131 0_0402_5%R131 0_0402_5%
R130 0_0402_5%R130 0_0402_5%

12/13 Change netname to FPR_OFF_C

12
12

FPR_LOCK#
FPR_OFF_C

D11

D11

SCA00000U10

SCA00000U10

YSLC05CH_SOT23-3

YSLC05CH_SOT23-3

1

+3VS

12

ACCEL_INT#

10/24 change ACCEL_INT#
connection to U9.11

0.1U_0402_16V7K

0.1U_0402_16V7K

+3VS

1

2

USB20_N8_R
USB20_P8_R

2

3

7/24 Modify pin define.
9/12 Modify JFP1 footprint
9/18 Modify JFP1 pin define

9/26 Modify JFP1 pin define to follow ME request.

1

+3VS

1

C103

C103

2

JFP1

JFP1

1
3
5
7
9

11

ACES_85203-0602N-10

ACES_85203-0602N-10

CONN@

CONN@

ACCEL_INT# [14]

1

C104

C104
10U_0603_6.3V6M

10U_0603_6.3V6M

2

221
443
665

887
10109
121211

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

2012/03/23 2006/09/25

2012/03/23 2006/09/25

2012/03/23 2006/09/25

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

TPM/Gsensor

TPM/Gsensor

TPM/Gsensor

LA-9241P

LA-9241P

LA-9241P

1

0.5

0.5

28 56Thursday, December 20, 2012

28 56Thursday, December 20, 2012

28 56Thursday, December 20, 2012

0.5

1

2

3

4

5

W=60mils

+3VM_LAN

22U_0603_6.3V6K

22U_0603_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C110

C110

C109

C109

1

1U_0402_6.3V6K

A A

07/23 Change R128 to 4.7K ohms

2

1

C108

C108

1U_0402_6.3V6K

1

2

2

07/20 Change C110 to 22UF

SLP_LAN[34]

SLP_LAN#[14,30]

SLP_LAN

+3VDS

10/26 Change R376 to 10k. Change R376.1
connection to +3VDS

12

R376

R376
10K_0402_5%

10K_0402_5%

61

AMT@

AMT@

Q7A

Q7A

2

2N7002DWH_SOT363-6

2N7002DWH_SOT363-6

07/20 Change location to Q7A

+3VM_LAN

R136

10K_0402_5%

R136

10K_0402_5%

U10

CLK_PCIE_LAN_REQ1#[15]

PLT_RST#[13,14,25,28,30,35,37,39,5]

CLK_PCIE_LAN[15]

B B

07/11 Delete R151, R152 by HP request
08/07 Add R569 and connection R569.1 to KBC_DS3_EN
10/16 Change R569.1 connection to KBC_WAKE#
10/25 Add Q63

C C

D D

CLK_PCIE_LAN#[15]

PCIE_PRX_DTX_P6[17]
PCIE_PRX_DTX_N6[17]

PCIE_PTX_C_DRX_P6[17]
PCIE_PTX_C_DRX_N6[17]

LAN_SMBCLK[16]

LAN_SMBDATA[16]

LANWAKE#[18]
KBC_WAKE#[25,30]
LAN_DIS#[18]

LAN_ACT#[33]

+3VM_LAN

1

07/11 Delete R135 by HP request
07/11 Delete R139 by HP request

+3VM_LAN

R569 0_0402_5%@R569 0_0402_5%@

10/26 Delete R153

C124

C124
33P_0402_50V8J

33P_0402_50V8J

1 2

C115 0.1U_0402_10V7KC115 0.1U_0402_10V7K

1 2

C116 0.1U_0402_10V7KC116 0.1U_0402_10V7K

1 2

R128 4.7K_0402_5%R128 4.7K_0402_5%

1 2

1 2

R154 10K_0402_5%@R154 10K_0402_5%@

1 2

R155 10K_0402_5%@R155 10K_0402_5%@

R158 1K_0402_5%R158 1K_0402_5%

R159 3.01K_0402_1%R159 3.01K_0402_1%

Y2

1

3

25MHZ 18PF +-20PPM CRG3202518Y225MHZ 18PF +-20PPM CRG3202518

1

IN

2

OUT

NC

NC

2

4

9/27 Change Y2 to 3225 package.

2

MMBT3904_SOT23-3

MMBT3904_SOT23-3

1 3

Q63

Q63

1 2

1 2

XTAL1

XTAL2

1

C125

C125
33P_0402_50V8J

33P_0402_50V8J

2

PCIE_PRX_DTX_P6_C
PCIE_PRX_DTX_N6_C

LAN_SMBCLK
LAN_SMBDATA

LANWAKE#_R

EBC

EBC

LED_LINK_LAN#
LAN_ACT#

T110T110
T111T111

LAN_JTAG_TMS
LAN_JTAG_TCK

XTAL2
XTAL1

U10

48

CLK_REQ_N

36

PE_RST_N

44

PE_CLKP

45

PE_CLKN

38

PETp

39

PETn

41

PERp

42

PERn

28

SMB_CLK

31

SMB_DATA

2

LANWAKE_N

3

LAN_DISABLE_N

26

LED0

27

LED1

25

LED2

32

JTAG_TDI

34

JTAG_TDO

33

JTAG_TMS

35

JTAG_TCK

9

XTAL_OUT

10

XTAL_IN

30

TEST_EN

12

RBIAS

2

MDO0+

MDO0-

MDO1+

MDO1-

MDO2+

MDO2-

MDO3+

MDO3-

LEDJTAG

LEDJTAG

PCIE

PCIE

SMBUS

SMBUS

CLARKVILLE

CLARKVILLE

MDO0+ [33]

MDO0- [33]

MDO1+ [33]

MDO1- [33]

MDO2+ [33]

MDO2- [33]

MDO3+ [33]

MDO3- [33]

MDI_PLUS0

MDI_MINUS0

MDI_PLUS1

MDI_MINUS1

MDI_PLUS2

MDI

MDI

MDI_MINUS2

MDI_PLUS3

MDI_MINUS3

SVR_EN_N

RSVD1_VCC3P3

VDD3P3_IN

VDD3P3_4
VDD3P3_15
VDD3P3_19
VDD3P3_29

VDD0P9_8
VDD0P9_11
VDD0P9_16

VDD0P9_22

VDD0P9_37

VDD0P9_40
VDD0P9_43
VDD0P9_46
VDD0P9_47

CTRL_0P9

CTRL_0P9

13

LAN_MDIP0

14

LAN_MDIN0

17

LAN_MDIP1

18

LAN_MDIN1

20

LAN_MDIP2

21

LAN_MDIN2

23

LAN_MDIP3

24

LAN_MDIN3

6

1

5

4
15
19
29

8
11
16

22

37

40
43
46
47

7

49

07/23 Add C389, C390, C391, C392.

1 2

47K_0402_5%

47K_0402_5%

R145

R145

1 2

C117 1000P_0402_50V7KC117 1000P_0402_50V7K

1 2

C505 10U_0603_6.3V6MC505 10U_0603_6.3V6M

11/02 Add C505

SHI00004C00

SHI00004C00

1 2

4.7UH +-5% 1008HC-472EJFS-A

4.7UH +-5% 1008HC-472EJFS-A

DELTA_1008HC-472EJFS-A_2P

DELTA_1008HC-472EJFS-A_2P

1 2

C120 0.01U_0402_16V7KC120 0.01U_0402_16V7K

1 2

C389 0.1U_0402_16V4ZC389 0.1U_0402_16V4Z

1 2

C390 0.1U_0402_16V4ZC390 0.1U_0402_16V4Z

1 2

C391 0.1U_0402_16V4ZC391 0.1U_0402_16V4Z

1 2

C392 1U_0402_6.3V4ZC392 1U_0402_6.3V4Z

LAN_ACT#

07/11 Delete R140, R142 by HP request

+3VM_LAN

+1.05VM_LAN

L15

L15

C373

C373

C504

C504

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0603_6.3V6M

10U_0603_6.3V6M

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

@

@

+V_DAC

+V_DAC

+V_DAC

+V_DAC

1

2

LAN_MDIP0

LAN_MDIN0

LAN_MDIP1

LAN_MDIN1

LAN_MDIP2

LAN_MDIN2

LAN_MDIP3

LAN_MDIN3

1

2

LED_LINK_LAN#_R[17]

07/06 Add by HP request

C350

C350

47U_0805_4V6M

47U_0805_4V6M

1

2

11/02 Reserve C504.
Change C350 to 47u.

TS1

TS1

1

TD1+

2

3

4

5

6

7

8

9

10

11

TX1+

TD1-

TX1-

TDCT1

TXCT1

TDCT2

TXCT2

TD2+

TX2+

TD2-

TX2-

TD3+

TX3+

TD3-

TX3-

TDCT3

TXCT3

TDCT4

TXCT4

TD4+

TX4+

TD4-12TX4-

350UH_NA0069RLF

350UH_NA0069RLF

SP050006Y00

SP050006Y00

2012/03/23 2009/12/31

2012/03/23 2009/12/31

2012/03/23 2009/12/31

+3VM_LAN

24

MDO0+

23

MDO0-

22

21

20

MDO1+

19

MDO1-

18

MDO2+

17

MDO2-

16

15

14

MDO3+

13

MDO3-

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

1 2

R144 10K_0402_5%R144 10K_0402_5%

LED_LINK_LAN#

LED_LINK_LAN#_R LED_LINK_LAN#

10/26 Connect Q34.3 to LED_LINK_LAN_DOCK# with R625, and delete LED_LINK_LAN_DOCK#
connection to Q34.1. Delete R157 and connect Q34.1 and signal LED_LINK_LAN#_R.

10/25 Delete R160, R161, R162, R163. Add RP12

4

12

1 2

C114680P_0402_50V7K@ C114680P_0402_50V7K@

1 2

C118680P_0402_50V7K@ C118680P_0402_50V7K@

RP12

RP12

75_1206_8P4R_5%

75_1206_8P4R_5%

D13

D13

SCA00000U10

SCA00000U10

YSLC05CH_SOT23-3

YSLC05CH_SOT23-3

07/16 Change P/N for ESD's request

RJ-45 CONN.

1 2

R138 300_0603_5%R138 300_0603_5%

1 2

R150 300_0603_5%R150 300_0603_5%

1 3

D

S

D

S

Q34

Q34
2N7002_SOT23-3

2N7002_SOT23-3

G

G

2

LAN_DIS#

45
36
27
18

2

1

2

3

@

@

1

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

+3VM_LAN

MDO3­MDO3+
MDO2+
MDO2­MDO1+
MDO1­MDO0+
MDO0-

2

3

@

@

D12

D12

SCA00000U10

SCA00000U10

YSLC05CH_SOT23-3

YSLC05CH_SOT23-3

1

07/16 Change P/N for ESD's request

1 2

R625 0_0402_5%R625 0_0402_5%

07/23 Change C121 to 1000pF

C121

C121

SE120102K90

SE120102K90

1000P_1808_3KV

1000P_1808_3KV

1

C122

C122

12

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

L16

L16

100UH_SSC0301101MCF_0.18A_20%

100UH_SSC0301101MCF_0.18A_20%

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Intel 82566 Nineveh

Intel 82566 Nineveh

Intel 82566 Nineveh

LA-9241P

LA-9241P

LA-9241P

JP4

JP4

1

1

2

2

3

3

4

4

5

5

6

6

7

7

G2

8

8

G1

9

9

10

10

11

11

12

12

13

13

14

14

ACES_87212-14G0

ACES_87212-14G0

CONN@

CONN@

1

C123

C123

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

2

5

16
15

LED_LINK_LAN_DOCK# [33]

29 56Thursday, December 20, 2012

29 56Thursday, December 20, 2012

29 56Thursday, December 20, 2012

0.5

0.5

0.5

1

+3VDS

07/20 Rearrange pin define
for layout smooth.

RP1

RP1

18

KSI0

27

KSI1

36

KSI2

45

KSI3

100K_0804_8P4R_5%

100K_0804_8P4R_5%

RP2

RP2

1 8

KSI7

2 7

KSI6

3 6

KSI5

4 5

KSI4

100K_0804_8P4R_5%

100K_0804_8P4R_5%

09/12 Change RP1 and RP2 to 100K ohms.

A A

7/13 Delete R224 and R460, beacuse no QW LED and CALC LED
7/13 Delete R220, R223 and short to make layout easier

7/13 Delete R496,R497,R498,R499

T121PAD @T121PAD @
T122PAD @T122PAD @

+3VS

4.7K_0804_8P4R_5%

4.7K_0804_8P4R_5%

1 8
2 7
3 6
4 5

RP3

RP3

4.7K_0804_8P4R_5%

4.7K_0804_8P4R_5%

1 8
2 7
3 6
4 5

RP4

RP4

+RTCVCC

7/13 Delete R244

B B

1

C188

C188
1U_0402_6.3V6K

1U_0402_6.3V6K

2

PVT_SCLK

C C

SPI ROM (16MByte )

+3VDS

7/13 Change power rail from +3V_SPI to +3VDS
12/12 Change RH222, RH223, RH224 to 100K

1 2

PCH_SPI_CS0# PCH_SPI_HOLD#

RH222

@RH222

@

100K_0402_5%

100K_0402_5%

1 2

PCH_SPI_WP#

RH223

RH223

100K_0402_5%

100K_0402_5%

1 2

PCH_SPI_HOLD#

RH224

RH224

100K_0402_5%

20mils

1

CH97

CH97

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

100K_0402_5%

+3VDS

+3VDS

D D

7/13 Change by HP request

Layout note: Close to PIN68

PVT_MOSI

10/16 Delete R218

07/18 Non install R219 and install R218
09/10 Delete R219

PVT_CS#

PVT_MISO

KSO4
KSO5

+3VS

D44

07/20 Add D44 and D45

PCH_SPI_CLK[16]

7/13 Delete RH220

CH98

CH98
22P_0402_50V8J

22P_0402_50V8J

D44

1

BAT54CW_SOT323-3

BAT54CW_SOT323-3

D45

D45

1

BAT54CW_SOT323-3

BAT54CW_SOT323-3

+3VDS

CH114

CH114

22P_0402_50V8J

22P_0402_50V8J

1

@

@

2

08/03 Add CH114

CURRENT_ADC[43]

OCP_A_IN[50]

TP_CLK
TP_DATA
SP_CLK
SP_DATA

PS2_CLK
PS2_DATA
KBD_DATA
KBD_CLK

07/18 Non install R266
09/10 Delete R266, netname MAIN_BAT_DET#

7/13 Delete R269

1

@

@

2

+RTCVCC

1

1

1

C179

C179

C180

C180

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Layout note: Close to PIN14

3

PS2_CLK

2

PS2_DATA

3

KBD_DATA

2

KBD_CLK

09/10 Delete R262, R264. Change pin 71 netname to KBC_XTAL1

A_GND
VOLTAGE_ADC[43]
LATCHED_ALARM[51]

08/03 Change R437 to 33 ohms

PCH_SPI_CLK

R437 33_0402_5%R437 33_0402_5%

WLAN_DISABLE[25]

CHRG_ADP_DET[43]

TP_DATA[38]
WWAN_DISABLE[25]

SLP_LAN#[14,29]

PCH_SPI_CLK_EC

07/24 Add C419 for EMI request

1

C181

C181

C182

C182

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Layout note: Close to PIN37

Layout note: Close to PIN58

PCH_SPI_SI

PCH_SPI_SI[16]

PCH_SPI_CS0#

PCH_SPI_CS0#[16]

PCH_SPI_SO

PCH_SPI_SO[16]

KSO[0..13][38]

KSI[0..7][38]

TP_CLK

TP_CLK[38]

SP_CLK

SP_CLK[38]

SP_DATA

SP_DATA[38]

PS2_CLK

PS2_CLK[33]

PS2_DATA

PS2_DATA[33]

PM_CLKRUN#[14,28,32]
SIRQ[16,28,32]
CLK_PCI_KBC[15]
EC_SCI#[18]

LPC_LAD3[16,25,28,32]
LPC_LAD2[16,25,28,32]
LPC_LAD1[16,25,28,32]
LPC_LAD0[16,25,28,32]

LPC_LFRAME#[16,25,28,32]
KBC_SIO_RST#[18,32]

12/12 Delete R605 12/12 Install R624
07/18 Non install R264 and install R262
09/25 Reserve R605

1 2

R272 300_0402_5%R272 300_0402_5%
R273 300_0402_5%R273 300_0402_5%

07/09 Delete 16 pin SPI ROM socket

PM_CLKRUN#
SIRQ
CLK_PCI_KBC
EC_SCI#

LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0

LPC_LFRAME#
KBC_SIO_RST#

KBC_XTAL1

1 2

C189 2200P_0402_50V7KC189 2200P_0402_50V7K

1 2

N27271393

R267 300_0402_5%R267 300_0402_5%

07/24 Change net name

PCH_SPI_CLK_EC

WLAN_DISABLE

TP_DATA
WWAN_DISABLE
SLP_LAN#

1 2

N27271121

1 2

N27271128

1

C419

C419
33P_0402_50V8J

33P_0402_50V8J

@

@

2

1

1

C183

C183

2

Layout note: Close to PIN84

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

1

C184

C184

C185

C185

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

7/13 Change by HP request

Layout note: Close to PIN119

Power Mgmt/SIRQ

Power Mgmt/SIRQ

LPC

LPC
Bus

Bus

PWR_GD

1 2

C190 2200P_0402_50V7KC190 2200P_0402_50V7K

1 2

C192 2200P_0402_50V7KC192 2200P_0402_50V7K

7/13 Change power rail
from +3V_SPI to +3VDS

PCH_SPI_WP#[16]

PCH_SPI_HOLD#[16]

+RTCVCC

Layout note: Close to PIN106

U17

U17

128

FLDATAOUT

127

*PVT_MOSI/GPIO54

97

FLCS0#

96

*PVT_CS0#/GPIO146

95

FLDATAIN

94

*PVT_MISO/GPIO164

21

KSO0

20

KSO1

19

KSO2

18

KSO3

17

KSO4

16

KSO5

13

KSO6

12

KSO7

10

KSO8

9

KSO9

8

KSO10

7

KSO11

6

*KSO12/GPIO5

5

*KSO13/GPIO6

29

KSI0

28

KSI1

27

KSI2

26

KSI3

25

KSI4

24

KSI5

23

KSI6

22

KSI7

35

*IMCLK/GPIO51

61

*GPIO50/KCLK

62

*GPIO65/KDAT

66

*GPIO46/EMCLK

67

*GPIO47/EMDAT

55

CLKRUN#

57

SER_IRQ

54

PCI_CLK

76

EC_SCI#

51

LAD[3]

50

LAD[2]

48

LAD[1]

46

LAD[0]

52

LFRAME#

53

LRESET#

70

*VSS_VBAT

71

*XTAL1

39

*ADC3/GPIO61

1

*GPIO36

2

*PVT_SCLK/GPIO153

3

*SHD_SCLK/GPIO122

30

*GPIO31

31

*GPIO127

32

*IMDAT/GPIO52

33

GPIO147

34

GPIO151

43

*ADC1/GPIO57

44

*ADC0/ADC_TO_PWM_IN/GPI O56

MEC1322-NU VTQFP 128P

MEC1322-NU VTQFP 128P

PWR_GD[31,47,5]

07/18 Install R277
08/10 Change R277.1 connection to VR_ON
09/12 Delete R278
09/23 Change netname to PWR_GD

Layout note: ADC nets are spaced at least 20mils from any high speed switching signals to prevent cross talk that could add noise

07/19 Add off page symbol
PCH_SPI_WP# and PCH_SPI_HOLD#

+3VDS

68

VCC158VCC184VCC1

*VBAT

100mA 2mA

Keyboard/Mouse Interface

Keyboard/Mouse Interface

Access Bus Interface

Access Bus Interface

*PWRGD

VSS

VSS47VSS56VSS

72

11

+3VDS

PCH_SPI_WP#

PCH_SPI_CS0#

PCH_SPI_CLK

PCH_SPI_SI

12

R555

R555
0_0402_5%

0_0402_5%

1

CH112

@ CH112

@

22P_0402_50V8J

22P_0402_50V8J

2

07/23 Add CH112 for RF request
07/24 Add R555 for EMI request

2

10/16 Change R215.2 to GND
07/18 R215 install by HP request.

JTAG_RST#

R215 100K_0402_5%R215 100K_0402_5%

09/10 Delete R216
07/18 R216 non install by HP request.

10/16 Delete C186

14

37

106

119

49

VCC1

VCC1

VCC1

*JTAG_RST#

General Purpose I/O Interface

General Purpose I/O Interface

SMSC_1322-NU_TQFP-128P

SMSC_1322-NU_TQFP-128P

*ADC_TO_PWM_OUT/GPIO41

Miscellaneous

Miscellaneous

VSS

AVSS

VSS82VSS

36

45

104

117

A_GND

1 2

R281 0_0402_5%R281 0_0402_5%

UH5

UH5

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

128M W25Q128FVSIG SOIC8P

128M W25Q128FVSIG SOIC8P

CONN@

CONN@

08/09 Correct UH5 and &UH1 SPI ROM size
08/09 Change UH5 footprint

1 2

7/13 Add R543
9/12 Delete R543

CAP

*GPIO145
*GPIO157/BC_CL K
*GPIO160/BC_DAT

*GPIO161/BC_INT#
*GPIO24/I2C3_C LK0
*GPIO25/I2C3_D AT0

*GPIO66

*GPIO44

*GPIO135/KBRST

*GPIO34/TACH2PWM_OUT

*GPIO133/PW M0
*GPIO136/PW M2

*GPIO30

VREF_PCEI

*GPIO131/PECI_ DATA

*GPIO7/KSO14

*GPIO10/KSO15

OUT1/RSMRST#

*GPIO162/RXD

*GPIO165/TXD/HSD_CS1 #

*GPIO23/I2C1_D AT0
*GPIO22/I2C1_C LK0
*GPIO21/I2C2_D AT0
*GPIO20/I2C2_C LK0

*GPIO105/FAN_TACH1
*GPIO140/TACH2PWM_ IN
*GPIO45/A20M/PVT_CS#1

*GPIO53/PS2CLK

*GPIO152/PS2DAT

*GPIO11/KSO16

*GPIO130

*I2C0_DATA0

*I2C0_CLK0

*I2C0_DATA1

*I2C0_CLK1

*GPIO110

*GPIO12/KSO17

*GPIO13

*nRESET_OUT#/GPIO121

*GPIO141/PW M3

VCC1_RST#

*ADC4/GPIO62

*XTAL2

*GPIO163

*nBAT_LED#/GPIO154

*nPWR_LED#/GP IO156

*GPIO155

10/16 Change EC pin 41 and R436.1 joint
point connection to iSCT_LED#

*GPIO206

*ADC2/GPIO60

GPIO33

*GPIO27

GPIO35

AVCC

1 2

C191 2200P_0402_50V7KC191 2200P_0402_50V7K

4

VSS

2

Q

R283 5_0402_1%R283 5_0402_1%

08/07 Change net name

07/09 Add by HP request.
07/10 Change R537 to 10K
08/03 Change R540 to 4.7K
10/16 Delete R540, Q74
12/12 Add Q84

+3VS

2

G

G

Q84

Q84

2N7002KW_SOT323-3

2N7002KW_SOT323-3

1 3

Layout note: 2vias to GND

15

1 2

C187 4.7U_0805_10V4ZC187 4.7U_0805_10V4Z

93
98
99
100
126
125

10/23 Add R617

124

123
122
121
120
118

107
79
80
81
83

85
86
87

88
89
90
91
92
101
102

103
105
4
74

111
112

109
110

73

108
59
75
60
78
77
38

69

116
113
115
114

41
42
65
64
63
40

TX_STBY_LED#

1 2

N27271225

R222 0_0402_5%R222 0_0402_5%

10/16 Change U7.125 connection to CHRG_RST,
U7.126 connection to KBC_WAKE#

12/12 Delete R617, R227
10/17 Change R227 to 10K
09/20 Change R227 to 3K

10/16 Connect D21.2 to PM_APWROK. Install D21.

1 2

KBRST#KBRST#

D21 RB751V-40_SOD323-2D21 RB751V-40_SOD323-2

FAN_PWM

7/13 Delete R236

H_PECI_R

R238 43_0402_1%R238 43_0402_1%

8051_RECOVER#/_NUM_LOCK_LED#

10/12 Add R610. Change U17.85 connection netname to RSMRST#_EC

RSMRST#_EC

10/16 Delete R239, R240

KBC_PROC_HOT#

07/18 Install R242

TACH_FAN_IN

1 2

R615 100K_0402_5%R615 100K_0402_5%

10/18 Change R615 to 470K ohms

KBD_CLK

12/12 Change R615 to 100K ohms

KBD_DATA
ON/OFFBTN#

I2C_MAIN_DAT
I2C_MAIN_CLK

I2C_BAY_DAT
I2C_BAY_CLK

ON/OFFBTN_KBC#

09/12 Delete R249, R251

09/10 Delete R253 and R549

07/18 Non install R253 and install R254.

09/12 Delete R256
07/18 Non install R258 and install R500

1 2

KBC_XTAL2

R624 0_0402_5%R624 0_0402_5%

10/15 Reserve R624 and connection to SUSCLK_KBC
09/10 Delete R258, R500 and change pin69 netname to KBC_XTAL2

07/18 R436 change to 1K

iSCT_LED#

R436 100K_0402_5%R436 100K_0402_5%

1 2

N27271143

R270 300_0402_5%R270 300_0402_5%

09/10 Delete R271

&UH1

45@&UH1

45@

128M W 25Q128FVSIG SOIC8P

128M W 25Q128FVSIG SOIC8P

12

PCH_SPI_SOPCH_SPI_SO_R_1

+3VDS

12

R559

R559
100K_0402_5%

100K_0402_5%

3

Q77B

Q77B
2N7002KDW_SOT363-6

2N7002KDW_SOT363-6

5

4

NMI_SMI_DBG# [14]

D

S

D

S

BATLOW# [14]

SIO_SLP_A#

KBC_PWR_ON

09/24 Non-install D21 09/25 Install R237, R235, R234, R233, R231

KBD_PWM_LED

1 2

1 2

R610 470_0402_5%R610 470_0402_5%

1 2

R541 0_0402_5%R541 0_0402_5%

1 2

R542 0_0402_5%R542 0_0402_5%

1 2

R252 10K_0402_5%R252 10K_0402_5%

PCH_KBC_I2CDAT
PCH_KBC_I2CLK

10/16 Add a 680K PD for U7.102. Change U7.102 connection to PLT_DET.

OCP_PWM_OUT

KBC_DS3_EN

ADP_ID_CHK

VCC1_PWRGD_SUS#

SUSCLK_KBC

TX_STBY_LED#

09/21 R436 change to 100K PD

1 2

TRAVEL_BAT_DET#
LID_SW#

07/23 Change C322 to 100pF
10/16 Delete C322

+3VDS

12

61

Q77A

Q77A
2N7002KDW_SOT363-6

2N7002KDW_SOT363-6

2

07/25 Add Q77 and R559

3

10/16 Remove current VCC1_PWRGD connection to
JP6.16. Then add a 4.7 K resistor between JP6.16

SIO_SLP_A# [14,31,46]
SUS_PWR_ACK [14]
AC_PRES_OUT [14,35]
KBC_PWR_ON [ 34,44]
KBC_WAKE# [25,29]
CHRG_RST [43]

FET_A [51]
PM_APWROK [14,31]
FAN_PWM [24]
BAT_GRNLED# [13,39]
KBD_PWM_LED [38]

CPPWR_EN [ 39]

+1.05VS

H_PECI [5]
SLP_S3# [14,31,34,45]
8051_RECOVER#/_NUM_LOCK_LED# [38]

10/18 Change R610 to 470 ohms

PCH_KBC_I2CDAT [16,35]
PCH_KBC_I2CLK [16,35]

KBD_CLK [33]
KBD_DATA [33]

ON/OFFBTN# [14,5]
ADP_PRES [50]

I2C_MAIN_DAT [42,43]
I2C_MAIN_CLK [42,43]

I2C_BAY_DAT [42]
I2C_BAY_CLK [42]

ON/OFFBTN_KBC# [33,38]
KSO17 [39]
OCP_PWM_OUT [18]
KBC_DS3_EN [45,5]
PM_PWROK [14,5]

10/16 Change U17 pin 77 connection to VCC1_PWRGD_SUS#

ADP_ID_CHK [50]

07/19 Delete R254, Add R549

EN_P1V5 [33,39,40,44,45]

SUSCLK_KBC [14]

FET_B [51]
AMBER_BATLED# [39]

8051RX_CAPLED# [38]

iSCT_LED# [39]

10/16 change R436.2 connection to +3VDS

+3VDS

ADP_A_ID [50]
TRAVEL_BAT_DET# [42]
LID_SW# [22,38,39]
ADP_EN [43]

+3VDS

KBC_XTAL1

@

@

KBC_XTAL2

09/10 Add C487, C488, and Y4
11/01 Uninstall Y4, C487, C488

and new signal VCC1_PWRGD_SUS#.

7/13 Reserve R541 and R542 for NFC function

PM_RSMRST# [14]

7/19 Install R541, R542

NFC_RX [39]

7/26 Add R561, R562. Non install R541, R542

NFC_TX [39]

9/03 Non install R561, R562. install R541, R543
9/12 Delete R561, R562.

KBC_PROC_HOT# [ 24,5]
EC_MUTE# [26]

09/10 Delete R241 and connect EC_MUTE# to KBC.91 directly.

MAIN_BAT_DET# [42]

Delete R242 and connect MAIN_BAT_DET# to KBC.92 directly.

TACH_FAN_IN [24]
PLT_DET

08/10 Add VCC1_PWRGD off page symbol
10/26 Delete VCC1_PWRGD off page symbol

08/10 Change R253.2 connection to VR_ON

07/25 Change net name
08/07 Change net name
09/07 Delete TX_STBY_LED# offpage symbol

1 2

C487 10P_0402_25V8K@C487 10P_0402_25V8K@

Y4

Y4

32.768KHZ_12.5PF_FC-135

32.768KHZ_12.5PF_FC-135

1 2

1 2

C488 10P_0402_25V8K@C488 10P_0402_25V8K@

09/03 Change R282 to 10K

+3VDS

1 2

R282 10K_0402_5%R282 10K_0402_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C193

C193

1

2

PVT_SCLK

10/16 Add R616

07/18 Install U18
07/25 Change U18 to scoket and add &UH2
08/09 Correct U18 and &UH2 SPI ROM size

R560

R560
100K_0402_5%

100K_0402_5%

8051TX_STBYLED# [33,38,39]

CLK_PCI_DEBUG_KBC[15]

PLT_RST#[13,14,25,28,29,35,37,39,5]

07/18 change net name
07/25 change net name
08/07 Change net name

VCC1_PWRGD_SUS#

12/12 Remove R611. Connect JP6.16 to VCC1_PWRGD_SUS#

KSO0
KSO1
KSO3
KSO2
JTAG_RST#

1 2

R237 15_0402_5%R237 15_0402_5%

1 2

R235 15_0402_5%R235 15_0402_5%

1 2

R234 15_0402_5%R234 15_0402_5%

1 2

R233 15_0402_5%R233 15_0402_5%

1 2

R231 15_0402_5%R231 15_0402_5%

+3VDS

10/16 Change R245.1 connection to KBC_WAKE#

KBC_WAKE#
ADP_EN

10/16 Delete R247

VCC1_PWRGD_SUS#

07/25 Change net name
08/07 Change net name

TX_STBY_LED#
8051RX_CAPLED#
KBD_PWM_LED
KBC_PWR_ON

ON/OFFBTN_KBC#
CHRG_ADP_DET
PCH_KBC_I2CDAT
PCH_KBC_I2CLK
LID_SW#
MAIN_BAT_DET#
TRAVEL_BAT_DET#
TACH_FAN_IN

ON/OFFBTN#

8051_RECOVER#/_NUM_LOCK_LED#

PVT_CS#

07/18 Add R546 by HP request.

10/12 Change R276.1 connection netname to RSMRST#_EC

10/16 Change R243 to 100K. Change R243.1 connection
to CHRG_RST. Change R243.2 connection to GND

PVT ROM (IN)

U18

CONN@U18

CONN@

20mils

8

4

VCC

VSS

3

W

7

1 2

R438

R438

HOLD

10K_0402_5%

10K_0402_5%

1

PVT_CS#

S

6

1 2

R616

R616

C

15_0402_5%

15_0402_5%

PVT_MOSI PVT_MISO

5

Q

D

16M W25Q16CVSSIG SOIC 8P

16M W25Q16CVSSIG SOIC 8P

2

LPC Debug Port

B+

LPC_LFRAME#

SIRQ

NMI_SMI_DBG#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

TX_STBY_LED#
8051RX_CAPLED#
8051_RECOVER#/_NUM_LOCK_LED#

1 2

R245 100K_0402_5%R245 100K_0402_5%

1 2

R246 10K_0402_5%R246 10K_0402_5%

12/12 Change R248 to 100k ohms

1 2

R248 100K_0402_5%R248 100K_0402_5%

10/16 Change R248 to 200k ohms. Change
R248.1 connection to VCC1_PWRGD_SUS#

1 2

R255 100K_0402_5%R255 100K_0402_5%

1 2

R257 100K_0402_5%R257 100K_0402_5%

1 2

R259 10K_0402_5%R259 10K_0402_5%

1 2

R263 100K_0402_5%R263 100K_0402_5%

1 2

R268 10K_0402_5%R268 10K_0402_5%

1 2

R439 10K_0402_5%R439 10K_0402_5%

1 2

R440 10K_0402_5%R440 10K_0402_5%

1 2

R441 10K_0402_5%R441 10K_0402_5%

1 2

R442 10K_0402_5%R442 10K_0402_5%

1 2

R443 10K_0402_5%R443 10K_0402_5%

1 2

R444 10K_0402_5%R444 10K_0402_5%

1 2

R445 10K_0402_5%R445 10K_0402_5%

1 2

R295 100K_0402_5%R295 100K_0402_5%

1 2

R493 100K_0402_5%R493 100K_0402_5%

1 2

R546 100K_0402_5%R546 100K_0402_5%

4.7K_0804_8P4R_5%

4.7K_0804_8P4R_5%

1 8

I2C_MAIN_CLK

2 7

I2C_MAIN_DAT

3 6

I2C_BAY_CLK

4 5

I2C_BAY_DAT

RP5

RP5

1 2

CPPWR_EN

R274 10K_0402_5%R274 10K_0402_5%

1 2

PM_PWROK

R275 10K_0402_5%R275 10K_0402_5%

1 2

RSMRST#_EC

R276 10K_0402_5%R276 10K_0402_5%

1 2

ADP_ID_CHK

R278 10K_0402_5%R278 10K_0402_5%

1 2

FET_A

R279 100K_0402_5%R279 100K_0402_5%

1 2

FET_B

R280 100K_0402_5%R280 100K_0402_5%

1 2

KBC_PROC_HOT#

R446 100K_0402_5%R446 100K_0402_5%

1 2

OCP_PWM_OUT

R447 10K_0402_5%R447 10K_0402_5%

1 2

KBC_DS3_EN

R265 100K_0402_5%R265 100K_0402_5%

1 2

CHRG_RST

R243 100K_0402_5%R243 100K_0402_5%

2MB

&UH2

16M W2 5Q16CVSSIG SOIC 8 P

16M W2 5Q16CVSSIG SOIC 8 P

JP6

JP6

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

G1

26

G2

ACES_50238-02471-002

ACES_50238-02471-002

CONN@

CONN@

08/07 Change JP6 footprint

+3VDS

+3VDS

45@&UH2

45@

4

5

Security Cla ssification

Security Cla ssification

Security Cla ssification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS
MAY BE USED BY OR DI SCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRONICS, INC.

MAY BE USED BY OR DI SCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRONICS, INC.

1

2

3

MAY BE USED BY OR DI SCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRONICS, INC.

4

Compal Secret Data

Compal Secret Data

Compal Secret Data

2012/03/23 2011/1 2/31

2012/03/23 2011/1 2/31

2012/03/23 2011/1 2/31

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

KBC1322

KBC1322

KBC1322

LA-9241P

LA-9241P

LA-9241P

5

of

30 56Thursday, December 20, 2012

of

30 56Thursday, December 20, 2012

of

30 56Thursday, December 20, 2012

0.5

0.5

0.5

R309

R309

1 2

1M_0402_5%

1M_0402_5%

+5VDS

8

U20B

U20B

P

+

-

G

LM393DR2G_SO8

LM393DR2G_SO8

4

+3VS

07/23 Change R286 to 10K

1 2

7

O

R286

R286
10K_0402_5%

10K_0402_5%

PWR_GD

09/23 Change netname to PWR_GD

+3VDS

R175

R175

3.3K_0402_5%

3.3K_0402_5%

1 2

12

R307

R307
1K_0402_5%

1K_0402_5%

PWR_GD [30,47,5]

PM_APWROK [14,30]

09/23 Change netname to VGATE

VGATE[47]

CH115

CH115

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

12/12 Change CH115 to 0.22uF

09/11 Delete R287. Connect joint point of R286.1 and U18.1 to VR_ON

+3V_PCH

12

RH246

RH246

4.7K_0402_5%

4.7K_0402_5%

1 2

R312 1M_0402_5%R312 1M_0402_5%

+5VDS

8

U20A

U20A

3

P

+

2

-

G

LM393DR2G_SO8

LM393DR2G_SO8

1

4

2

1

O

9/13 Modify power ok circuit

PCH_PWROK_R [14]

09/03 Non install R284

1

R284

@

@

2

1 2

R290 10K_0402_5%R290 10K_0402_5%

12

1

C196

C196

2

19.1K_0402_1%

19.1K_0402_1%

1

R284

40.2K_0402_1%

40.2K_0402_1%

1 2

1 2

R291 105K_0402_1%R291 105K_0402_1%

31.6K_0402_1%

31.6K_0402_1%

R296 10K_0402_5%R296 10K_0402_5%

R299

R299

73.2K_0402_1%

73.2K_0402_1%

C197

C197

R313

R313

R292

R292

1 2

1

2

1000P_0402_50V7K

1000P_0402_50V7K

12

1.75VREF

12

12

35.7K_0402_1%

35.7K_0402_1%
R306

R306

1

C199

C199

3300P_0402_25V7K

3300P_0402_25V7K

2

1.75VREF

R311

R311

1 2

10K_0402_5%

10K_0402_5%

C194

C194

3300P_0402_25V7K

+5VS

+0.675VS

1.5VS_PG[49]

SLP_S3#[14,30,34,45]

PM_APWROK

+3VS

+1.35VS

+1.05VS

11/01 Change R304.1 connection to +5VL. Change R304 to 88.7k +-1%

1.05VM_PG[46]

SIO_SLP_A#[14,30,46]

1 2

R288 76.8K_0402_1%R288 76.8K_0402_1%

09/03 Change R289 to 11.5K

1 2

R289

R289

1 2

R550 3.3K_0402_5%R550 3.3K_0402_5%

R551

R551

1 2

3.3K_0402_5%

3.3K_0402_5%

R552

R552

1 2

3.3K_0402_5%

3.3K_0402_5%

1 2

R297 76.8K_0402_1%R297 76.8K_0402_1%

1 2

R293 30.9K_0402_1%R293 30.9K_0402_1%

1 2

R553

R553

+3VM_LAN

3300P_0402_25V7K

11.5K_0402_1%

11.5K_0402_1%

10/31 Change R291.1 connection to

D41

D41

2

3

DAP202UGT106_SC70-3

DAP202UGT106_SC70-3

24.3K_0402_1%

24.3K_0402_1%

+5VL

1 2

R310 20.5K_0402_1%R310 20.5K_0402_1%

1 2

R547

R547

R548

R548

1 2

3.3K_0402_5%

3.3K_0402_5%

+5VL. Change R291 to 105K_1%

1

3300P_0402_25V7K

3300P_0402_25V7K

1 2

R304 88.7K_0402_1%R304 88.7K_0402_1%

3.3K_0402_5%

3.3K_0402_5%

D43

D43

2

3

DAP202UGT106_SC70-3

DAP202UGT106_SC70-3

+5VL

R285

R285

1 2

1M_0402_5%

1M_0402_5%

+5VDS

8

U19A

U19A

3

P

+

1

O

2

-

G

LM393DR2G_SO8

LM393DR2G_SO8

4

1

C195

C195
1000P_0402_50V7K

1000P_0402_50V7K

2

R294

R294

1 2

1M_0402_5%

1M_0402_5%

+5VDS

8

U19B

U19B

5

P

+

7

O

6

-

G

LM393DR2G_SO8

LM393DR2G_SO8

4

07/20 Follow VBK10 PWR_GD circuit

1 2

1M_0402_5%

1M_0402_5%

0.068U_0402_10V6K

0.068U_0402_10V6K

07/18 HP request

5

6

R301

R301

C198

C198

1 2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/03/23 2010/03/31

2012/03/23 2010/03/31

2012/03/23 2010/03/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

POK CKT

POK CKT

POK CKT

LA-9241P

LA-9241P

LA-9241P

31 56Thursday, December 20, 2012

31 56Thursday, December 20, 2012

31 56Thursday, December 20, 2012

0.5

0.5

0.5

1

2

3

4

5

D27

D27

RP13

RP13

RP14

RP14

RP15

RP15

RP16

RP16

1 2

CLK_SIO_14MCLK_PCI_SIO

12

R333
10_0402_5%

10_0402_5%

1

C206
10P_0402_25V8K

10P_0402_25V8K

2

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

SIO_GPIO46

SIO_GPIO23
SIO_GPIO41
SIO_GPIO42
SIO_GPIO44

SIO_IRQ
SIO_GPIO12
SIO_GPIO10

SIO_GPIO44
SIO_GPIO43

SIO_GPIO42

SYSOPT

@R333

@

@C206

@

+5VS

10/25 Delete R318, R319,
R321, R322. Add RP17

RP17

DSR#1
CTS#1

1 2

RI#1
DCD#1

RXD1

RP17

4.7K_0804_8P4R_5%

4.7K_0804_8P4R_5%

1 2

R323 1K_0402_5%R323 1K_0402_5%

+3VS

18
27
36
45

U22

U22

54

RXD1[33]
TXD1[33]
DSR#1[33]
RTS#1[33]
CTS#1[33]
DTR#1[33]
RI#1[33]
DCD#1[33]

LPTINIT#[33]
LPTSLCTIN#[33]
LPD0[33]
LPD1[33]
LPD2[33]
LPD3[33]
LPD4[33]
LPD5[33]
LPD6[33]
LPD7[33]
LPTSLCT[33]
LPTPE[33]
LPTBUSY[33]
LPTACK#[33]
LPTERR#[33]
LPTAFD#[33]
LPTSTB#[33]

+3VS

C201 0.1U_0402_16V4ZC201 0.1U_0402_16V4Z

1

2

RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

LPTINIT#
LPTSLCTIN#
LPD0
LPD1
LPD2LPD2
LPD3
LPD4LPD4
LPD5
LPD6LPD6
LPD7
LPTSLCT
LPTPE
LPTBUSY
LPTACK#
LPTERR#
LPTAFD#
LPTSTB#

+3VS

C202 0.1U_0402_16V4ZC202 0.1U_0402_16V4Z

C203 0.1U_0402_16V4ZC203 0.1U_0402_16V4Z

C204 4.7U_0805_10V4ZC204 4.7U_0805_10V4Z

1

1

1

2

2

2

RXD1

55

TXD1

56

DSR1#

1

RTS1#

2

CTS1#

3

DTR1#

4

RI1#

5

DCD1#

35

INIT#

36

SLCTIN#

37

PD0

39

PD1

40

PD2

41

PD3

42

PD4

43

PD5

44

PD6

45

PD7

47

SLCT

48

PE

49

BUSY

50

ACK#

51

ERROR#

52

ALF#

53

STROBE#

7

VTR

10

VCC

23
38
46

POWER

POWER

VCC
VCC
VCC

LPC47N217N-ABZJ_QFN56_8X8

LPC47N217N-ABZJ_QFN56_8X8

SERIAL I/FPARALLEL I/F

SERIAL I/FPARALLEL I/F

LPC I/F

LPC I/F

CLOCK

CLOCK

GPIO11/SYSOPT

GPIO12/IO_SMI#

GPIO13/IRQIN1
GPIO14/IRQIN2

LAD0
LAD1
LAD2
LAD3

LFRAME#

LDRQ#

PCI_RESET#

LPCPD#

CLKRUN#

PCI_CLK
SER_IRQ
IO_PME#

CLK14

GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46

GPIO

GPIO

GPIO47
GPIO10

GPIO23

EPAD

9
11
12
13

14
15

16
17

18
19
20
6

8

21
22
24
25
26
27
28
29
30
31
32
33
34

57

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

LPC_LFRAME#
LPC_LDRQ0#

KBC_SIO_RST#
LPCPD#_SIO

PM_CLKRUN#
CLK_PCI_SIO
SIRQ
SIO_PME#

CLK_SIO_14M

SIO_GPIO41
SIO_GPIO42
SIO_GPIO43
SIO_GPIO44
mSATA_DET#
SIO_GPIO46
SER_SHD_GPIO47
SIO_GPIO10
SYSOPT
SIO_GPIO12
SIO_IRQ

SIO_GPIO23

LPC_LAD0 [16,25,28,30]
LPC_LAD1 [16,25,28,30]
LPC_LAD2 [16,25,28,30]
LPC_LAD3 [16,25,28,30]

LPC_LFRAME# [16,25,28,30]
LPC_LDRQ0# [16]

KBC_SIO_RST# [18,30]

PM_CLKRUN# [14,28,30]
CLK_PCI_SIO [15]

1 2

R324 10K_0402_5%R324 10K_0402_5%

10/26 Connect U22.26 pin to signal mSATA_DET#

12

R327

R327
10K_0402_5%

10K_0402_5%

SIRQ [16,28,30]

+3VS

CLK_SIO_14M [15]

mSATA_DET# [23]

LPCPD#_SIO

R325 4.7K_0402_5%R325 4.7K_0402_5%

+3VS

1 2

Parallel Port

TO LPC47N217N

RB751V-40_SOD323-2

10/25 Delete R320, R477,
R478, R464. Add RP13

A A

B B

C C

+5VS_PRN

10/25 Delete R465, R466,
R467, R472. Add RP14

10/25 Delete R473, R474,
R475, R468. Add RP15

10/25 Delete R469, R470,
R471, R479. Add RP16

07/19 Change R483.1 and R482.1 connection to +3VS.
Change R330.1, R329.1, and R328.1 connection to GND
07/20 Reserve SIO_GPIO44 PD R554, and modify R328,
R329, R330 value to 4.7K. Modify R482, R483 value
to 10K

+3VS

09/11 Add R601 4.7K PU to +3VS on signal SIO_GPIO42. Noninstall R601

RB751V-40_SOD323-2

LPTACK#
LPTERR#
LPTAFD#
LPTSTB#

4.7K_0804_8P4R_5%

4.7K_0804_8P4R_5%

LPD7
LPTSLCT
LPTPE
LPTBUSY

4.7K_0804_8P4R_5%

4.7K_0804_8P4R_5%

LPD3
LPD4
LPD5
LPD6

4.7K_0804_8P4R_5%

4.7K_0804_8P4R_5%

LPTSLCTIN#
LPD0
LPD1
LPD2

4.7K_0804_8P4R_5%

4.7K_0804_8P4R_5%

LPTINIT#

R476 4.7K_0402_5%R476 4.7K_0402_5%

1 2

R480 4.7K_0402_5%R480 4.7K_0402_5%

10/26 Delete R481

1 2

R328 4.7K_0402_5%R328 4.7K_0402_5%

1 2

R329 4.7K_0402_5%R329 4.7K_0402_5%

1 2

R330 4.7K_0402_5%R330 4.7K_0402_5%

1 2

R554 4.7K_0402_5%@R554 4.7K_0402_5%@

4.7K_0804_8P4R_5%

4.7K_0804_8P4R_5%

R482 10K_0402_5%R482 10K_0402_5%
R483 10K_0402_5%R483 10K_0402_5%

R601 4.7K_0402_5%@R601 4.7K_0402_5%@

R331 10K_0402_5%R331 10K_0402_5%

12

R332

R332
33_0402_5%

33_0402_5%

1

C205

C205
82P 50V J NPO 0402

82P 50V J NPO 0402

2

10/25 Delete R484, R485,

RP18

RP18

R486. Add RP18

18
27
36
45

1 2
1 2

1 2

1 2

Base I/O Address

0 = 02Eh
1 = 04Eh

11/07 Change R332 to 33 ohms, C205 to 82pF and install R332 and C205

D D

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/03/23 2009/09/09

2012/03/23 2009/09/09

2012/03/23 2009/09/09

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

4

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

SUPER I/O LPC47N217N-ABZJ

SUPER I/O LPC47N217N-ABZJ

SUPER I/O LPC47N217N-ABZJ

LA-9241P

LA-9241P

LA-9241P

5

32 56Thursday, December 20, 2012

32 56Thursday, December 20, 2012

32 56Thursday, December 20, 2012

0.5

0.5

0.5

1

VA

C207 0.1U_0603_50V4ZC207 0.1U_0603_50V4Z

(1) PCI Express x1 channels
(2) PS/2 Interfaces
(2) USB 2.channels
(2) SATA Channels
(2) Display Port Channels
(1) Serial Port
(1) Parallel Port
(1) Line In
(1) Line Out
(1) RJ45 (10/100/1000)
(1) VGA

A A

(1) 2 LAN indicator LED's
(1) Power Button
(1) I2C interface

B B

Quick SW

MDO3+[29]
MDO3-[29]

MDO2+[29]
MDO2-[29]

DPB_TXP0[36]
DPB_TXN0[36]

DPB_TXP1[36]
DPB_TXN1[36]

DPB_TXP2[36]
DPB_TXN2[36]

DPB_TXP3[36]
DPB_TXN3[36]

DPB_AUX[36]
DPB_AUX#[36]

C209 0.1U_0603_50V4ZC209 0.1U_0603_50V4Z

1

1

2

2

L30ESD24VC3-2_SOT23-3

L30ESD24VC3-2_SOT23-3

VA

DETECT

+5VS

1

D42

D42

@

@

2

3

DPB_AUX
DPB_AUX#

DOCK CONN. 184PIN

VIN VA

HCB2012KF-121T50_0805

HCB2012KF-121T50_0805

1 2

5A

HCB2012KF-121T50_0805

HCB2012KF-121T50_0805

1 2

10/11 Non-install D42
07/16 Add by ESD's request

12A

JDOCK1A

JDOCK1A

190

P1

188

188

187

187

186

186

185

185

184

184

183

183

182

182

181

181

180

180

179

179

178

178

177

177

176

176

175

175

174

174

173

173

172

172

171

171

170

170

169

169

168

168

167

167

166

166

165

165

164

164

163

163

162

162

161

161

160

160

159

159

158

158

157

157

156

156

155

155

154

154

153

153

152

152

151

151

150

150

149

149

148

148

147

147

146

146

145

145

144

144

FOX_QL0094L-D26601-8H

FOX_QL0094L-D26601-8H

CONN@

CONN@

2

DOCKING CONNECT

+5VS

L27

L27

L28

L28

189

G1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45

USB3TN1
USB3TP1

USB3RN1
USB3RP1

MXM_DCK_AUX
MXM_DCK_AUX#

13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45

+5VS

C210

C210

C211

C211

10U_0805_10V4Z

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

MDO1+ [29]
MDO1- [29]

MDO0+ [29]
MDO0- [29]

LED_LINK_LAN_DOCK# [29]
LAN_ACT# [29]

USB3TN1 [17]

USB3TP1 [17]

USB3RN1 [17]

USB3RP1 [17]

USBP0- [17]

USBP0+ [17]

MXM_DCK_LANE_P0 [35]
MXM_DCK_LANE_N0 [35]

MXM_DCK_LANE_P1 [35]
MXM_DCK_LANE_N1 [35]

MXM_DCK_LANE_P2 [35]
MXM_DCK_LANE_N2 [35]

MXM_DCK_LANE_P3 [35]
MXM_DCK_LANE_N3 [35]

MXM_DCK_AUX [35]
MXM_DCK_AUX# [35]

C212

C212

1

2

3

DOCK_ID
ISO_PREP#

C213

C213

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

09/11 Delete R351 and connect
EN_P1V5 to JDOCK1.140

DPB_HPD[36]
EN_P1V5[30,39,40,44,45]

ADP_SIGNAL

DPB_AUX
DPB_AUX# MXM_DCK_AUX#

LPTSTB#[32]
LPTAFD#[32]
LPTERR#[32]
LPTACK#[32]
LPTBUSY[32]
LPTPE[32]
LPTSLCT[32]
LPD7[32]
LPD6[32]
LPD5[32]
LPD4[32]
LPD3[32]
LPD2[32]
LPD1[32]
LPD0[32]
LPTSLCTIN#[32]
LPTINIT#[32]

SATA_ACT#[13,39]
DOCK_ID[36]
ISO_PREP#[13,36]

SATA_PTX_DRX_P3[13]
SATA_PTX_DRX_N3[13]

SATA_PRX_DTX_P3[13]
SATA_PRX_DTX_N3[13]

USBP11-[17]
USBP11+[17]

SATA_PTX_DRX_P2[13]
SATA_PTX_DRX_N2[13]

GPU

SATA_PRX_DTX_P2[13]
SATA_PRX_DTX_N2[13]

08/01 Modify SATA bus from port 5 to port 2

09/11 Change C299 to 0.01uF. Delete R336 and
connect C299.1 to ON/OFFBTN_KBC#. Connect
ON/OFFBTN_KBC# to JDOCK1.49

R168 100K_0402_5%R168 100K_0402_5%

DPB_HPD

ADP_SIGNAL

09/27 Delete R339, R341 09/27 Delete R340, R342

LPTSTB#
LPTAFD#
LPTERR#
LPTACK#
LPTBUSY
LPTPE
LPTSLCT
LPD7
LPD6
LPD5
LPD4
LPD3
LPD2
LPD1
LPD0
LPTSLCTIN#
LPTINIT#
STB_LED#_R
SATA_ACT#
DOCK_ID
ISO_PREP#

USBP11­USBP11+

4

1 2

R334 10K_0402_5%R334 10K_0402_5%

1 2

R337 10K_0402_5%R337 10K_0402_5%

2

C299

C299

0.01U_0402_16V7K_X7R

0.01U_0402_16V7K_X7R

1

1 2

+5VS

+3V_PCH

JDOCK1B

JDOCK1B

143

143

142

142

141

141

140

140

139

139

138

138

137

137

136

136

135

135

134

134

133

133

132

132

131

131

130

130

129

129

128

128

127

127

126

126

125

125

124

124

123

123

122

122

121

121

120

120

119

119

118

118

117

117

116

116

115

115

114

114

113

113

112

112

111

111

110

110

109

109

108

108

107

107

106

106

105

105

104

104

103

103

102

102

101

101

100

100

99

99

98

98

97

97

96

96

95

95

192

G2

194

G4

196

G6

198

G8

200

G10

FOX_QL0094L-D26601-8H

FOX_QL0094L-D26601-8H

CONN@

CONN@

ON/OFFBTN_KBC#

46

46

47

47

48

48

49

49

50

50

51

51

52

52

53

53

54

54

55

55

56

56

57

57

58

58

59

59

60

60

61

61

62

62

63

63

64

64

65

65

66

66

67

67

68

68

69

69

70

70

71

71

72

72

73

73

74

74

75

75

76

76

77

77

78

78

79

79

80

80

81

81

82

82

83

83

84

84

85

85

86

86

87

87

88

88

89

89

90

90

91

91

92

92

93

93

94

94

191

G1

193

G3

195

G5

197

G7

199

G9

DCK1_HPD
ON/OFFBTN_KBC#
VA_ON#

D_DDCDATA
D_DDCCLK

R_DOCK_RED

R_DOCK_GRN
R_DOCK_BLU

DCD#1
RI#1
DTR#1
CTS#1
RTS#1
DSR#1
TXD1
RXD1

KBD_DATA
KBD_CLK
PS2_DATA
PS2_CLK

DOCK_HPS#

DLINE_OUT_L
DLINE_OUT_R

DETECT

5

VA_ON#

R335

R335

1K_0402_5%

1K_0402_5%

ON/OFFBTN_KBC# [30,38]

DCK1_HPD [35]

D_DDCDATA [36]
D_DDCCLK [36]
D_VSYNC [36]
D_HSYNC [36]

R_DOCK_GRN [36]

R_DOCK_BLU [36]

DCD#1 [32]
RI#1 [32]
DTR#1 [32]
CTS#1 [32]
RTS#1 [32]
DSR#1 [32]
TXD1 [32]
RXD1 [32]

KBD_DATA [30]
KBD_CLK [30]
PS2_DATA [30]
PS2_CLK [30]
LINE_IN_SENSE [27]
DOCK_HPS# [27]

DOCK_LINE_IN_L [27]
DOCK_LINE_IN_R [27]

DLINE_OUT_L [27]
DLINE_OUT_R [27]

12

MXM_DCK_AUX

R_DOCK_RED [36]

1

C208

C208

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

C C

+5VDS

12

R346

R346
10K_0402_5%

10K_0402_5%

07/18 change by HP request

8051TX_STBYLED#[30,38,39]

D D

IN

NC<-->COM

L

H

1

2

ON

OFF

NO<-->COM

OFF

ON

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/03/23 2009/12/31

2012/03/23 2009/12/31

2012/03/23 2009/12/31

8051TX_STBYLED#

Compal Secret Data

Compal Secret Data

Compal Secret Data

2

Deciphered Date

Deciphered Date

Deciphered Date

4

STB_LED#_R

13

D

D

Q35

Q35

G

G

2N7002_SOT23-3

2N7002_SOT23-3

S

S

R_DOCK_RED
R_DOCK_GRN
R_DOCK_BLU

R_DOCK_RED
R_DOCK_GRN
R_DOCK_BLU

Title

Title

Title

DOCK CONN

DOCK CONN

DOCK CONN

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-9241P

LA-9241P

LA-9241P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1 2

R343 150_0402_1%R343 150_0402_1%

1 2

R344 150_0402_1%R344 150_0402_1%

1 2

R345 150_0402_1%R345 150_0402_1%

1 2

C214 0.1U_0402_16V4Z@C214 0.1U_0402_16V4Z@

1 2

C215 0.1U_0402_16V4Z@C215 0.1U_0402_16V4Z@

1 2

C216 0.1U_0402_16V4Z@C216 0.1U_0402_16V4Z@

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

33 56Thursday, December 20, 2012

33 56Thursday, December 20, 2012

5

33 56Thursday, December 20, 2012

0.5

0.5

0.5

A

+3VALW TO +3VALW(PCH AUX Power)

07/06 Swap Drain and Source
to aviod leakage issue

10U_0603_6.3V6M

1 1

10U_0603_6.3V6M

KBC_PWR_ON#[46]

KBC_PWR_ON[30,44]

Short J1 for PCH VCCSUS3.3

+3VDS

C224

C224

1

2

KBC_PWR_ON#

J1

JUMP_43X79

JUMP_43X79

Q40 AO3 413L_SOT23-3

Q40 AO3 413L_SOT23-3

R489

R489

1K_0402_5%

1K_0402_5%

2

112

12

61

+3V_PCH

@J1

@

2

40mil

123

DGS

DGS

R455 200K_040 2_5%R455 2 00K_0402_5%

R622 100K_040 2_5%R622 1 00K_0402_5%

10/25 Change R455 to 200k. Add PD R622.
10/26 Change R455.2 connection to B+

DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6
Q18A

Q18A

C225

10U_0603_6.3V6M

C225

10U_0603_6.3V6M

1

1

@

2

2

B+ +3VDS

1 2

1 2

C220

1U_0603_25V6@C220

1U_0603_25V6

1 2
34

R355

R355

470_0603_5%

470_0603_5%

5

KBC_PWR_ON#

Q18B

Q18B

DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

@

@

C508

C508

C509

C509

100P_0402_50V8J

100P_0402_50V8J

1

1

@

@

2

2

08/10 Reserve C455 for RF

B

C490 0.01 U_0402_16V7K@C490 0.01U_0402_16 V7K@

1 2

R603 0_0402_ 5%R6 03 0_0402_5%

1 2

SLP_S3# SLP_S3#

C489

C489

C455

C455

10U_0603_6.3V6M

10U_0603_6.3V6M

68P_0402_50V8J

68P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

1

1

@

@

2

+5VDS

C491 47 00P_0402_16V7KC491 4700P_0402 _16V7K

1 2

2

9/25 Change +5VS power rail soultion. Delete U24, C226, C221, C222. Add U45, R603, C489, C490, C491, C492
9/26 Change C489, C492 to 10u. Change C490 to 0.01u
11/06 Add C506, C507, C508, C509 by RF reqeust
11/06 Change C491 to 4700pF

U45

U45

3

ON

1

VIN

VOUT

2

VIN

VOUT

4

VBIAS

GND

6

CT

GND

TPS22965DSGR_SON8_2X2

TPS22965DSGR_SON8_2X2

7

8

5
9

C

+5VS+5VDS

4.5A 6.5A

C506

C453

C453

C492

C492

68P_0402_50V8J

68P_0402_50V8J

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

@

@

2

2

C506

C507

C454

C454

68P_0402_50V8J

68P_0402_50V8J

1

@

@

2

C507

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

1

1

@

@

@

@

2

2

D

+3VDS to +3VS Transfer+5VDS to +5VS Transfer

U46

C493 0.01 U_0402_16V7K@C493 0.01U_0402_16 V7K@

+3VDS +3VS

C494

C494

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

09/25 Change +3VS power rail solution.
Delete U25, C218, C223, C219, C227, R354, R356, R357, Q9.
Add U46, R604, C493, C494, C495, C496
09/26 Change C494, C496 to 10u. Change C493 to 0.01u
11/06 Change C495 to 4700pF

1 2

R604 0_0402_ 5%R6 04 0_0402_5%

1 2

+5VDS

C495 47 00P_0402_16V7KC495 4700P_0402 _16V7K

1 2

U46

3

ON

1

VIN

VOUT

2

VIN

VOUT

4

VBIAS

GND

6

CT

GND

TPS22965DSGR_SON8_2X2

TPS22965DSGR_SON8_2X2

7

8

5
9

08/10 Reserve C452, C456, C457, C458 for RF08/10 Reserve C453 and C454 for RF
11/06 Reserve C510 by RF request

1

@

@

2

E

C452

C452

C496

C496

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

C456

C456

68P_0402_50V8J

68P_0402_50V8J

@

@

C510

C510

68P_0402_50V8J

68P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

1

1

@

@

@

@

2

2

C457

C457

C458

C458

68P_0402_50V8J

68P_0402_50V8J

68P_0402_50V8J

68P_0402_50V8J

1

1

@

@

2

2

10/12 Change R455 to 47K. Add Q18A, C504, R609. Modify circuit
10/16 Delete C504, R609, R456, Q67B. Add R612. Modify circuit.
10/18 Change R612 to 4.7k ohms. Delete Q67A
10/23 Delete R612

2 2

+3VALW to +3VM_LAN Transfer

AMT@

AMT@

+3VDS +3VM_LAN

C229

1U_0402_6.3V4Z

C229

1U_0402_6.3V4Z

1

2

SLP_LAN[29]

+1.05VM to +1.05VS Transfer

Q41

Q41
AO4430L_SO8

AO4430L_SO8

8

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 2

7
6
5

4

3

5

SLP_S3

4

09/26 Change netname to SLP_S3#
09/26 Change +1.05VS power circuit.

Q42B

Q42B
2N7002DW T/R7_SOT-363-6

2N7002DW T/R7_SOT-363-6

C233

10U_0805_10V4Z

C233

10U_0805_10V4Z

C234

C234

1

2

3 3

R375 220K_040 2_5%R375 2 20K_0402_5%

B+

1
2
3

C503

C503

3300P_0402_25V7K

3300P_0402_25V7K

1

2

10/26 Change Q36 to AO3413

1K_0402_5%

1K_0402_5%

SLP_LAN

+1.05VS+1.05VM

C235

C235

09/28 Add C503

AMT@

AMT@

Q36

Q36

AO3413L_SOT23-3

AO3413L_SOT23-3

123

DGS

DGS

12

R488

R488

6A

10U_0805_10V4Z

10U_0805_10V4Z

C232

C232

1

1

+

+

2

2

1.5A

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C230

C230

1

AMT@

AMT@

2

07/20 Delete C231

Discharge circuit-1

330U_B2_2VM_R15M

330U_B2_2VM_R15M

@

@

+1.05VS

12

R369

R369
470_0402_5%

470_0402_5%

61

Q42A

Q42A
2N7002DW T/R7_SOT-363-6

2N7002DW T/R7_SOT-363-6

2

SLP_S3

09/26 Change Q42 to Dual channel

07/23 Remove Q37, R366, R361

+3VS

12

@

@

13

2

SLP_S3

G

G

R370

R370
220_0402_5%

220_0402_5%

D

D

Q43

Q43
2N7002_SOT23-3

2N7002_SOT23-3

@

@

S

S

9/25 Uninstall R370, R373, Q43, Q44

07/10 Change R363 to 4.7K

SLP_S3[49,9]

SLP_S3#[14,30,31,45]

+5VS

@

@

2

SLP_S3

G

G

100K_0402_5%

100K_0402_5%

12

R373

R373
470_0402_5%

470_0402_5%

13

D

D

S

S

R368

R368

Q44

Q44
2N7002_SOT23-3

2N7002_SOT23-3

@

@

SLP_S3

12

+3VDS

2

G

G

12

R363

R363

4.7K_0402_5%

4.7K_0402_5%

13

D

D

S

S

Q39

Q39
2N7002KW_SOT323-3

2N7002KW_SOT323-3

Discharge circuit-2 for V-M

SLP_LAN

+3VM_LAN

5

12

R360

R360
470_0402_5%

470_0402_5%

34

Q7B

Q7B
2N7002DWH_SOT363-6

2N7002DWH_SOT363-6

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/03/23 2009/12/31

2012/03/23 2009/12/31

2012/03/23 2009/12/31

D

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

LA-9241P

LA-9241P

LA-9241P

DC/DC Circuits

DC/DC Circuits

DC/DC Circuits

E

of

34 56Thursday, December 20, 2012

of

34 56Thursday, December 20, 2012

of

34 56Thursday, December 20, 2012

0.5

0.5

0.5

5

PEG_CTX_GRX_P[0..15][4]

PEG_CTX_GRX_N[0..15][4]

PEG_CRX_GTX_P[0..15][4]

PEG_CRX_GTX_N[0..15][4]

D D

C C

PEG_CRX_GTX_N15
PEG_CRX_GTX_P15

PEG_CRX_GTX_N14
PEG_CRX_GTX_P14

PEG_CRX_GTX_N13
PEG_CRX_GTX_P13

PEG_CRX_GTX_N12
PEG_CRX_GTX_P12

PEG_CRX_GTX_N11
PEG_CRX_GTX_P11

PEG_CRX_GTX_N10
PEG_CRX_GTX_P10

PEG_CRX_GTX_N9
PEG_CRX_GTX_P9

PEG_CRX_GTX_N8
PEG_CRX_GTX_P8

PEG_CRX_GTX_N7
PEG_CRX_GTX_P7

PEG_CRX_GTX_N6
PEG_CRX_GTX_P6

PEG_CRX_GTX_N5
PEG_CRX_GTX_P5

B B

PEG_CRX_GTX_N4
PEG_CRX_GTX_P4

6/2 change to fix MXM no function issue.

A A

PEG_CTX_GRX_P[0..15]

PEG_CTX_GRX_N[0..15]

PEG_CRX_GTX_P[0..15]

PEG_CRX_GTX_N[0..15]

+5VS

1 2

DGPU_PWR_EN

R487 4.7K_0402_5%@R487 4.7K_0402_5%@

+3VS

ENAVDD_G

DGPU_SELECT#[14,36]

BL_EN_G

DGPU_SELECT#

BKL_PWM_PCH[14]

BL_PWM_G

DGPU_SELECT#

12/12 Change U34, U35, U36 to small package for material shortage issue.

R63 100K_0402_5%R63 100K_0402_5%

1 2

PEG_CRX_GTX_C_N15

CV90.22U_0402_6.3V6K CV90.22U_0402_6.3V6K

1 2

PEG_CRX_GTX_C_P15

CV100.22U_0402_6.3V6K CV100.22U_0402_6.3V6K

1 2

PEG_CRX_GTX_C_N14

CV110.22U_0402_6.3V6K CV110.22U_0402_6.3V6K

1 2

PEG_CRX_GTX_C_P14

CV120.22U_0402_6.3V6K CV120.22U_0402_6.3V6K

1 2

PEG_CRX_GTX_C_N13

CV130.22U_0402_6.3V6K CV130.22U_0402_6.3V6K

1 2

PEG_CRX_GTX_C_P13

CV140.22U_0402_6.3V6K CV140.22U_0402_6.3V6K

1 2

PEG_CRX_GTX_C_N12

CV150.22U_0402_6.3V6K CV150.22U_0402_6.3V6K

1 2

PEG_CRX_GTX_C_P12

CV160.22U_0402_6.3V6K CV160.22U_0402_6.3V6K

1 2

PEG_CRX_GTX_C_N11

CV170.22U_0402_6.3V6K CV170.22U_0402_6.3V6K

1 2

PEG_CRX_GTX_C_P11

CV180.22U_0402_6.3V6K CV180.22U_0402_6.3V6K

1 2

PEG_CRX_GTX_C_N10

CV190.22U_0402_6.3V6K CV190.22U_0402_6.3V6K

1 2

PEG_CRX_GTX_C_P10

CV200.22U_0402_6.3V6K CV200.22U_0402_6.3V6K

1 2

PEG_CRX_GTX_C_N9

CV210.22U_0402_6.3V6K CV210.22U_0402_6.3V6K

1 2

PEG_CRX_GTX_C_P9

CV220.22U_0402_6.3V6K CV220.22U_0402_6.3V6K

1 2

PEG_CRX_GTX_C_N8

CV230.22U_0402_6.3V6K CV230.22U_0402_6.3V6K

1 2

PEG_CRX_GTX_C_P8

CV240.22U_0402_6.3V6K CV240.22U_0402_6.3V6K

1 2

PEG_CRX_GTX_C_N7

CV250.22U_0402_6.3V6K CV250.22U_0402_6.3V6K

1 2

PEG_CRX_GTX_C_P7

CV260.22U_0402_6.3V6K CV260.22U_0402_6.3V6K

1 2

PEG_CRX_GTX_C_N6

CV270.22U_0402_6.3V6K CV270.22U_0402_6.3V6K

1 2

PEG_CRX_GTX_C_P6

CV280.22U_0402_6.3V6K CV280.22U_0402_6.3V6K

1 2

PEG_CRX_GTX_C_N5

CV290.22U_0402_6.3V6K CV290.22U_0402_6.3V6K

1 2

PEG_CRX_GTX_C_P5

CV300.22U_0402_6.3V6K CV300.22U_0402_6.3V6K

1 2

PEG_CRX_GTX_C_N4

CV310.22U_0402_6.3V6K CV310.22U_0402_6.3V6K

1 2

PEG_CRX_GTX_C_P4

CV320.22U_0402_6.3V6K CV320.22U_0402_6.3V6K

3
1
6

74LVC1G3157GW_SC-88-6

74LVC1G3157GW_SC-88-6

3
1
6

74LVC1G3157GW_SC-88-6

74LVC1G3157GW_SC-88-6

3
1
6

74LVC1G3157GW_SC-88-6

74LVC1G3157GW_SC-88-6

5

U34

U34

Y0
Y1
S

U35

U35

Y0
Y1
S

U36

U36

Y0
Y1
S

ENAVDD_G
BL_EN_G
BL_PWM_G

12

VCC

GND

VCC

GND

VCC

GND

Z

Z

Z

B+ B+

JMXM1A

JMXM1A

1

PWR_SRC

3

PWR_SRC

5

PWR_SRC

7

PWR_SRC

9

PWR_SRC

11

PWR_SRC

13

PWR_SRC

15

PWR_SRC

17

PWR_SRC

19

PWR_SRC

21

GND

23

GND

25

GND

27

GND

29

GND

31

GND

33

GND

35

GND

37

GND

39

GND

41

5V

43

5V

45

5V

47

5V

49

5V

51

GND

53

GND

55

GND

57

GND

59

PEX_STD_SW#

61

VGA_DISABLE#

63

PNL_PWR_EN

65

PNL_BL_EN

67

PNL_BL_PWM

69

HDMI_CEC

71

DVI_HPD

73

LVDS_DDC_DAT

75

LVDS_DDC_CLK

77

GND

79

OEM

81

OEM

83

OEM

85

OEM

87

GND

89

PEX_RX15#

91

PEX_RX15

93

GND

95

PEX_RX14#

97

PEX_RX14

99

GND

101

PEX_RX13#

103

PEX_RX13

105

GND

107

PEX_RX12#

109

PEX_RX12

111

GND

113

PEX_RX11#

115

PEX_RX11

117

GND

119

PEX_RX10#

121

PEX_RX10

123

GND

125

PEX_RX9#

127

PEX_RX9

129

GND

131

PEX_RX8#

133

PEX_RX8

135

GND

137

PEX_RX7#

139

PEX_RX7

141

GND

143

PEX_RX6#

145

PEX_RX6

147

GND

149

PEX_RX5#

151

PEX_RX5

153

GND

155

PEX_RX4#

157

PEX_RX4

FOX_AS0B826-S43B1-7H

FOX_AS0B826-S43B1-7H

08/09 Modify JMXM1 footprint

+3VS

5
4
2

+3VS

5
4
2

ENAVDD [22]ENVDD_PCH[14]

ENABLT [22]PANEL_BKEN_PCH[14]

PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC

PRSNT_R#

WAKE#

PWR_GOOD

PWR_EN

PWR_LEVEL

TH_OVERT#
TH_ALERT#

TH_PWM

SMB_DAT
SMB_CLK

PEX_TX15#

PEX_TX15

PEX_TX14#

PEX_TX14

PEX_TX13#

PEX_TX13

PEX_TX12#

PEX_TX12

PEX_TX11#

PEX_TX11

PEX_TX10#

PEX_TX10

PEX_TX9#

PEX_TX9

PEX_TX8#

PEX_TX8

PEX_TX7#

PEX_TX7

PEX_TX6#

PEX_TX6

PEX_TX5#

PEX_TX5

PEX_TX4#

PEX_TX4

CONN@

CONN@

2
4
6
8
10
12
14
16
18
20
22

GND

24

GND

26

GND

28

GND

30

GND

32

GND

34

GND

36

GND

38

GND

40

GND

42
44
46
48
50

RSVD

52

RSVD

54

RSVD

56

RSVD

58
60
62
64
66

GPIO0

68

GPIO1

70

GPIO2

72
74
76

GND

78

OEM

80

OEM

82

OEM

84

OEM

86

GND

88
90
92

GND

94
96
98

GND

100
102
104

GND

106
108
110

GND

112
114
116

GND

118
120
122

GND

124
126
128

GND

130
132
134

GND

136
138
140

GND

142
144
146

GND

148
150
152

GND

154
156

S Z

+3VS

5
4
2

INV_PWM [ 22]

LOHIY0

4

DGPU_PRSNT#

DGPU_PWROK
DGPU_PWR_EN

1 2

R606 4.7K_0402_5%R606 4.7K_0402_5%

MXM_PCH_KBC_I2CDAT
MXM_PCH_KBC_I2CLK

PEG_CTX_GRX_N15
PEG_CTX_GRX_P15

PEG_CTX_GRX_N14
PEG_CTX_GRX_P14

PEG_CTX_GRX_N13
PEG_CTX_GRX_P13

PEG_CTX_GRX_N12
PEG_CTX_GRX_P12

PEG_CTX_GRX_N11
PEG_CTX_GRX_P11

PEG_CTX_GRX_N10
PEG_CTX_GRX_P10

PEG_CTX_GRX_N9
PEG_CTX_GRX_P9

PEG_CTX_GRX_N8
PEG_CTX_GRX_P8

PEG_CTX_GRX_N7
PEG_CTX_GRX_P7

PEG_CTX_GRX_N6
PEG_CTX_GRX_P6

PEG_CTX_GRX_N5
PEG_CTX_GRX_P5

PEG_CTX_GRX_N4
PEG_CTX_GRX_P4

07/06 Swap PEG TX and RX

Y1

4

DGPU_PRSNT# [18]

DGPU_PWROK [18]
DGPU_PWR_EN [14,15]

+3VS

2

Q60A

Q60A

2N7002DW T/R7_SOT-363-6

2N7002DW T/R7_SOT-363-6

Q82A

Q82A

2

2N7002KDW_SOT363-6

2N7002KDW_SOT363-6

61

AC_PRES_OUT

MXM_THERMTRIP#

MMBT3904_SOT23-3

MMBT3904_SOT23-3

10/25 Change Q61 and Q62 to dual channel 7002
11/08 Delete D52. Add Q83, R627

1 2

R607 10K_0402_5%R607 10K_0402_5%

1 2

R608 300_0402_5%R608 300_0402_5%

10/25 Change R607 and R608 to 10K
10/29 Change R608 to 300 ohms.

09/27 Add R606, R607, R608
10/18 Change R606,R607 and R608 to 4.7K

DGPU_PWROK

61

Q60B

Q60B

354

2N7002DW T/R7_SOT-363-6

2N7002DW T/R7_SOT-363-6

dGPU_HPD_INTR[17]

dGPU_HPD_INTR

#4/6 change by HP
requirement

PCH_THERMTRIP#_R

AC_PRES_OUT

PEX_RST

5/28 change by HP requirement

R627

R627

4.7K_0402_5%

4.7K_0402_5%

10/18 change R137 to 4.7K
10/29 Delete R137, Q82.B. Add D52

2

13

PCH_THERMTRIP#_R

EBC

EBC

Q83

Q83

+3VS

PCH_KBC_I2CDAT [ 16,30]

PCH_KBC_I2CLK [16,30]

Thunder Bolt

2N7002KW_SOT323-3

2N7002KW_SOT323-3

13

D

D

2

G

G

12

S

S

Q51

Q51

R451

R451
100K_0402_5%

100K_0402_5%

PCH_THERMTRIP#_R [18,24,5]

AC_PRES_OUT [14,30]

EDP

2

TB_HPD DCK1_HPDDCK1_SYS_HPD

G

G

12

R452

R452
100K_0402_5%

100K_0402_5%

3

07/06 Swap PEG TX and RX

PEG_CRX_GTX_N2
PEG_CRX_GTX_P2

PEG_CRX_GTX_N1
PEG_CRX_GTX_P1

PEG_CRX_GTX_N0
PEG_CRX_GTX_P0

MXM_eDP_LANE_N0[36]
MXM_eDP_LANE_P0[36]

MXM_eDP_LANE_N1[36]
MXM_eDP_LANE_P1[36]

MXM_eDP_LANE_N2[36]
MXM_eDP_LANE_P2[36]

MXM_eDP_LANE_N3[36]
MXM_eDP_LANE_P3[36]

GPU_AUX#[36]
GPU_AUX[36]

MXM_TB_LANE_N0[39]
MXM_TB_LANE_P0[39]

MXM_TB_LANE_N1[39]
MXM_TB_LANE_P1[39]

MXM_TB_LANE_N2[39]
MXM_TB_LANE_P2[39]

MXM_TB_LANE_N3[39] MXM_DCK_AUX [33]
MXM_TB_LANE_P3[39]

MXM_TB_AUX#[39]
MXM_TB_AUX[39]

12

CV3 0.22U_0402_6.3V6KCV3 0.22U_0402_6.3V6K

12

CV4 0.22U_0402_6.3V6KCV4 0.22U_0402_6.3V6K

12

CV5 0.22U_0402_6.3V6KCV5 0.22U_0402_6.3V6K

12

CV6 0.22U_0402_6.3V6KCV6 0.22U_0402_6.3V6K

12

CV7 0.22U_0402_6.3V6KCV7 0.22U_0402_6.3V6K

12

CV8 0.22U_0402_6.3V6KCV8 0.22U_0402_6.3V6K

CLK_PCIE_VGA#[15]
CLK_PCIE_VGA[15]

07/09 Change by easy layout
10/11 Change DP port C to eDP

07/09 Change by easy layout
10/11 Change DP port A to Thunder bolt

12

C240.1U_0402_10V7K C240.1U_0402_10V7K

12

C250.1U_0402_10V7K C250.1U_0402_10V7K

12

C260.1U_0402_10V7K C260.1U_0402_10V7K

12

C270.1U_0402_10V7K C270.1U_0402_10V7K

12

C280.1U_0402_10V7K C280.1U_0402_10V7K

12

C290.1U_0402_10V7K C290.1U_0402_10V7K

12

C300.1U_0402_10V7K C300.1U_0402_10V7K

12

C310.1U_0402_10V7K C310.1U_0402_10V7K

12

C320.1U_0402_10V7K C320.1U_0402_10V7K

12

C330.1U_0402_10V7K C330.1U_0402_10V7K

12

C340.1U_0402_10V7K C340.1U_0402_10V7K

12

C350.1U_0402_10V7K C350.1U_0402_10V7K

12

C360.1U_0402_10V7K C360.1U_0402_10V7K

12

C370.1U_0402_10V7K C370.1U_0402_10V7K

12

C380.1U_0402_10V7K C380.1U_0402_10V7K

12

C390.1U_0402_10V7K C390.1U_0402_10V7K

12

C400.1U_0402_10V7K C400.1U_0402_10V7K

12

C670.1U_0402_10V7K C670.1U_0402_10V7K

PEG_CTX_GRX_N3
PEG_CTX_GRX_P3

PEG_CRX_GTX_C_N2
PEG_CRX_GTX_C_P2

PEG_CRX_GTX_C_N1
PEG_CRX_GTX_C_P1

PEG_CRX_GTX_C_N0
PEG_CRX_GTX_C_P0

MXM_eDP_C_LANE_N0
MXM_eDP_C_LANE_P0

MXM_eDP_C_LANE_N1
MXM_eDP_C_LANE_P1

MXM_eDP_C_LANE_N2
MXM_eDP_C_LANE_P2

MXM_eDP_C_LANE_N3
MXM_eDP_C_LANE_P3

GPU_C_AUX#
GPU_C_AUX

MXM_TB_C_LANE_N0
MXM_TB_C_LANE_P0

MXM_TB_C_LANE_N1
MXM_TB_C_LANE_P1

MXM_TB_C_LANE_N2
MXM_TB_C_LANE_P2

MXM_TB_C_LANE_N3
MXM_TB_C_LANE_P3

MXM_TB_AUX#
MXM_TB_AUX

12

2N7002KW_SOT323-3

2N7002KW_SOT323-3

13

D

D

S

S

Q52

Q52

12

3

2

G

G

R453

R453
100K_0402_5%

100K_0402_5%

2N7002KW_SOT323-3

2N7002KW_SOT323-3

13

D

D

S

S

Q53

Q53

100K_0402_5%

100K_0402_5%

R169

R169

158

GND

160

PEX_TX3#

162

PEX_TX3

164

GND

166

GND

168

PEX_RX2#

170

PEX_RX2

172

GND

174

PEX_RX1#

176

PEX_RX1

178

GND

180

PEX_RX0#

182

PEX_RX0

184

GND

186

PEX_REFCLK#

188

PEX_REFCLK

190

GND

192

RSVD

194

RSVD

196

RSVD

198

RSVD

200

RSVD

202

LVDS_UCLK#

204

LVDS_UCLK

206

GND

208

LVDS_UTX3#

210

LVDS_UTX3

212

GND

214

LVDS_UTX2#

216

LVDS_UTX2

218

GND

220

LVDS_UTX1#

222

LVDS_UTX1

224

GND

226

LVDS_UTX0#

228

LVDS_UTX0

230

GND

232

DP_C_L0#

234

DP_C_L0

236

GND

238

DP_C_L1#

240

DP_C_L1

242

GND

244

DP_C_L2#

246

DP_C_L2

248

GND

250

DP_C_L3#

252

DP_C_L3

254

GND

256

DP_C_AUX#

258

DP_C_AUX

260

RSVD

262

RSVD

264

RSVD

266

RSVD

268

RSVD

270

RSVD

272

RSVD

274

RSVD

276

RSVD

278

RSVD

280

RSVD

282

RSVD

284

GND

286

DP_A_L0#

288

DP_A_L0

290

GND

292

DP_A_L1#

294

DP_A_L1

296

GND

298

DP_A_L2#

300

DP_A_L2

302

GND

304

DP_A_L3#

306

DP_A_L3

308

GND

310

DP_A_AUX#

312

DP_A_AUX

314

PRSNT_L#

316

GND

318

GND

CONN@

CONN@

08/09 Modify JMXM1 footprint

FOX_AS0B826-S43B1-7H

FOX_AS0B826-S43B1-7H

2

JMXM1B

JMXM1B

159

GND

161

PEX_RX3#

PEX_TX2#

PEX_TX1#

PEX_TX0#

PEX_CLK_REQ#

PEX_RST#
VGA_DDC_DAT
VGA_DDC_CLK

VGA_VSYNC
VGA_HSYNC

VGA_GREEN

VGA_BLUE

LVDS_LCLK#

LVDS_LCLK

LVDS_LTX3#

LVDS_LTX3

LVDS_LTX2#

LVDS_LTX2

LVDS_LTX1#

LVDS_LTX1

LVDS_LTX0#
LVDS_LTX0#

DP_D_L0#

DP_D_L1#

DP_D_L2#

DP_D_L3#

DP_D_AUX#

DP_D_AUX

DP_C_HPD

DP_D_HPD

DP_B_L0#

DP_B_L1#

DP_B_L2#

DP_B_L3#

DP_B_AUX#

DP_B_AUX

DP_B_HPD

DP_A_HPD

PEG_CRX_GTX_C_N3

163

PEG_CRX_GTX_C_P3 PEG_CRX_GTX_P3

PEX_RX3

165

GND

167

GND

169

PEG_CTX_GRX_N2

171

PEG_CTX_GRX_P2

PEX_TX2

173

GND

175

PEG_CTX_GRX_N1

177

PEG_CTX_GRX_P1

PEX_TX1

179

GND

181

PEG_CTX_GRX_N0

183

PEG_CTX_GRX_P0

PEX_TX0

185

GND

187
189

PEX_RST

191
193
195
197
199

GND

201

VGA_RED

203
205
207

GND

209
211
213

R92

R92

R91

R91

R93

R93

GND

215

150_0402_1%

150_0402_1%

150_0402_1%

150_0402_1%

217

@

@

@

@

219

1 2

1 2

GND

221
223
225

GND

227

12/20 Uninstall R91, R92, R93.

229
231

GND

233
235
237

GND

DP_D_L0

GND

DP_D_L1

GND

DP_D_L2

GND

DP_D_L3

GND

RSVD
RSVD
RSVD
RSVD

DP_B_L0

GND

DP_B_L1

GND

DP_B_L2

GND

DP_B_L3

GND

3V3
3V3

GND
GND

Security Cla ssification

Security Cla ssification

Security Cla ssification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NO R THE INFORMATION IT CONTAINS
MAY BE USED BY OR DI SCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRONICS, INC.

MAY BE USED BY OR DI SCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRONICS, INC.

MAY BE USED BY OR DI SCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRONICS, INC.

10/11 Change DP port D to SWITCH

239
241
243
245
247
249
251
253
255
257
259
261
263
265
267

1 2

269

R450 10K_0402_5%R450 10K_0402_5%

271
273
275
277

10/11 Change DP port B to DOCK

279
281
283
285
287
289
291
293
295
297
299
301
303
305

1 2

307

R448 10K_0402_5%R448 10K_0402_5%

1 2

309

R449 10K_0402_5%R449 10K_0402_5%

311
313

C347

C347

C348

C348

315

10U_0603_6.3V6M

10U_0603_6.3V6M

317

1

1

2

2

5/17 change by HP agree

08/08 Reserve C450, C451 by RF request

2012/03/23 2009/0 9/09

2012/03/23 2009/0 9/09

2012/03/23 2009/0 9/09

2

CV1 0.22U_0402_6.3V6KCV1 0.22U_0402_6.3V6K
CV2 0.22U_0402_6.3V6KCV2 0.22U_0402_6.3V6K

PEG_CLK_REQ# [15]

GPU_VGA_DDC_DAT [36]
GPU_VGA_DDC_CLK [36]
GPU_VGA_VSYNC [ 36]
GPU_VGA_HSYNC [36]

150_0402_1%

150_0402_1%

@

@

1 2

C349

C349

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

12

@

@

2

12
12

RED_R [36]
GREEN_R [36]
BLUE_R [36]

DCK1_SYS_HPD

DCK1_HPD
TB_HPD

+3VS

C451

C451

C450

C450

82P 50V J NPO 0402

82P 50V J NPO 0402

82P 50V J NPO 0402

82P 50V J NPO 0402

12

@

@

Compal Secret Data

Compal Secret Data

Compal Secret Data

CRT

4

OUT

Deciphered Date

Deciphered Date

Deciphered Date

PEG_CRX_GTX_N3

+3VS

5

U37

U37

1

VCC

IN1

2

IN2

GND

MC74VHC1G08DFT2G_SC70-5

MC74VHC1G08DFT2G_SC70-5

3

MXM_SYS_LANE_N0 [36]
MXM_SYS_LANE_P0 [36]

MXM_SYS_LANE_N1 [36]
MXM_SYS_LANE_P1 [36]

MXM_SYS_LANE_N2 [36]
MXM_SYS_LANE_P2 [36]

MXM_SYS_LANE_N3 [36]
MXM_SYS_LANE_P3 [36]

MXM_SYS_AUX# [36]

MXM_SYS_AUX [36]
GPU_HPD [36]
DCK1_SYS_HPD [ 36]

MXM_DCK_LANE_N0 [33]
MXM_DCK_LANE_P0 [33]

MXM_DCK_LANE_N1 [33]
MXM_DCK_LANE_P1 [33]

MXM_DCK_LANE_N2 [33]
MXM_DCK_LANE_P2 [33]

MXM_DCK_LANE_N3 [33]
MXM_DCK_LANE_P3 [33]

MXM_DCK_AUX# [33]

DCK1_HPD [33]
TB_HPD [39]

07/09 Change by easy layout

DGPU_HOLD_RST# [ 14]

PLT_RST# [13,14,25,28,29,30,37,39,5]

07/09 Change by easy layout

Dock

Date: Sheet

Date: Sheet

Date: Sheet

1

SWITCH

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

MXM

MXM

MXM

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

LA-9241P

LA-9241P

LA-9241P

1

of

35 56Thursday, December 20, 2012

of

35 56Thursday, December 20, 2012

of

35 56Thursday, December 20, 2012

0.5

0.5

0.5

1

2

3

4

5

07/17 Modify eDP MUX solution to PI3VDP12413

A A

From CPU

From GPU

B B

C C

1 2

R348 10K_0402_5%R348 10K_0402_5%

+5VS

DGPU_SELECT#

D D

EDP_CPU_LANE_N0[ 7]
EDP_CPU_LANE_P0[7]
EDP_CPU_LANE_N1[ 7]
EDP_CPU_LANE_P1[7]

EDP_CPU_AUX#[7]
EDP_CPU_AUX[7]
CPU_EDP_HPD#[7]

MXM_eDP_LANE_N0[35]
MXM_eDP_LANE_P0[35]
MXM_eDP_LANE_N1[35]

MXM_eDP_LANE_P1[35]
MXM_eDP_LANE_N2[35]
MXM_eDP_LANE_P2[35]
MXM_eDP_LANE_N3[35]
MXM_eDP_LANE_P3[35]

GPU_AUX#[35]
GPU_AUX[35]

GPU_HPD[35]

+5VS

61

Q78A

Q78A
2N7002KDW_SOT363-6

2N7002KDW_SOT363-6

2

DOCK_ID[33]

07/25 Combine Q56 and Q57 to Q79

07/27 Add R563, R564

EDP_CPU_LANE_N0
EDP_CPU_LANE_P0
EDP_CPU_LANE_N1
EDP_CPU_LANE_P1

1 2

R564 200K_0402_5%R564 200K_0402_5%

EDP_CPU_AUX#
EDP_CPU_AUX
CPU_EDP_HPD#

MXM_eDP_LANE_N0
MXM_eDP_LANE_P0
MXM_eDP_LANE_N1
MXM_eDP_LANE_P1
MXM_eDP_LANE_N2
MXM_eDP_LANE_P2
MXM_eDP_LANE_N3
MXM_eDP_LANE_P3
GPU_AUX#
GPU_AUX
GPU_HPD

12

100K_0402_5%

100K_0402_5%

R504

R504

PCH_CRT_RED[14]

RED_R[35]

PCH_CRT_GRN[14]

GREEN_R[35]

PCH_CRT_BLU[14]

BLUE_R[35]

PCH_CRT_DDC_CLK[14]
GPU_VGA_DDC_CLK[35]

PCH_CRT_DDC_DAT[14]
GPU_VGA_DDC_DAT[35]

1 2

R350 10K_0402_5%R350 10K_0402_5%

+5VS

PCH_CRT_HSYNC[14]

GPU_VGA_HSYNC[35]

PCH_CRT_VSYNC[14]

GPU_VGA_VSYNC[35]

R349 10K_0402_5%R349 10K_0402_5%

1 2

3

Q78B

Q78B
2N7002KDW_SOT363-6

2N7002KDW_SOT363-6

5

4

+3VS

10K_0402_5%

10K_0402_5%

+3VS

12

R563

R563
200K_0402_5%

200K_0402_5%

U42

U42

42
41
40
39
38
37
36
35
24
23
16

33
32
31
30
29
28
27
26
19
20
15

R505

R505

25

12

PI3VDP12412ZHEX_TQFN42_9X3P5

PI3VDP12412ZHEX_TQFN42_9X3P5

7

17

8

18

9

19

5

15

6

16

2

3

13

4

14

1
40
39
38

30
20
10

41

eDP MUX

D0-A
D0+A
D1-A
D1+A
D2-A
D2+A
D3-A
D3+A
AUX-A
AUX+A
HPD_A

D0-B
D0+B
D1-B
D1+B
D2-B
D2+B
D3-B
D3+B
AUX-B
AUX+B
HPD_B

OE

U28

U28

GPU_SEL

AUX_HPD_S EL

DGPU_SELECT#[14,35]

07/23 Change to dual channel MOS Q76

MAX14885E

MAX14885E

REDA
REDB

GRNA
GRNB

BLUA
BLUB

SCLA
SCLB

SDAA
SDAB

EN

SHA
SHB

SVA
SVB

S00
S01
S10
S11

GND
GND
GND

GPAD

MAX14885EETL+T_TQFN40_5X5~D

MAX14885EETL+T_TQFN40_5X5~D

HGND

+3VS

1

1

CC74

CC74

CC83

CC83

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

2

07/23 Delete R516 and CC84

1

2

EDP_SW_D0N [22]
EDP_SW_D0P [22]
EDP_SW_D1N [22]
EDP_SW_D1P [22]
EDP_SW_D2N [22]
EDP_SW_D2P [22]
EDP_SW_D3N [22]
EDP_SW_D3P [22]

EDC_SW_AUX# [22]
EDC_SW_AUX [22]

EDP_SW_HPD [22]

C369

0.1U_0402_16V4Z

C369

0.1U_0402_16V4Z

C368

1U_0402_6.3V4Z

C368

1U_0402_6.3V4Z

1

1

2

2

MXM_SYS_LANE_N0[35]
MXM_SYS_LANE_P0[35]
MXM_SYS_LANE_N1[35]
MXM_SYS_LANE_P1[35]
MXM_SYS_LANE_N2[35]
MXM_SYS_LANE_P2[35]
MXM_SYS_LANE_N3[35]
MXM_SYS_LANE_P3[35]

MXM_SYS_AUX#[ 35]
MXM_SYS_AUX[35]

DCK1_SYS_HPD[35]

1

CC73

CC73

CC72

CC72

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+3VS

1 2

3

R462

R462
10K_0402_5%

10K_0402_5%

Q76B

Q76B

2N7002KDW_SOT363-6

2N7002KDW_SOT363-6

2

+3VS

12

VDD

21

VDD

34

VDD

2

SEL_eDP_MUX

3

D0-

4

D0+

6

D1-

7

D1+

8

D2-

9

D2+

10

D3-

11

D3+

13

AUX-

14

AUX+

5

SEL_eDP_MUX

18

HPD

GND
GND
GND

1
17
22
43

SEL_eDP_MUX

5

07/19 Delete CC70, CC71, CC75, CC76,
CC77, CC78, CC79, CC80, CC81, CC82

+3VS

C367

0.1U_0402_16V4Z

C367

0.1U_0402_16V4Z

C370

0.1U_0402_16V4Z

C370

0.1U_0402_16V4Z

1

1

2

2

07/23 Modify net name07/23 Modify net name

SEL_DP_MUX

SEL_DP_MUX

12
21
34

2
3
4
6
7
8

9
10
11

13
14

5
18

1
17
22
43

4

09/07 Add JVGA2 circuit

1 2

DAC_RE

L29 110NH_CS0805-R11J-S_5%L29 110NH_CS0805-R11J-S_5%

L30 110NH_CS0805-R11J-S_5%L30 110NH_CS0805-R11J-S_5%

1 2

DAC_GR

L31 110NH_CS0805-R11J-S_5%L31 110NH_CS0805-R11J-S_5%

1 2

DAC_BL

C461 18P_0402_50V8JC461 18P_0402_50V8J

C460 18P_0402_50V8JC460 18P_0402_50V8J

1

1

2

2

VGA_R

RED1
RED2

GRN1
GRN2

SDA1
SDA2

1

1

1

CC61

CC61

CC60

CC60

2

+3VS

10U_0603_6.3V6M

29

VCC

21

VCC

11

VL

33
24

32
23

31

BLU1

22

BLU2

35

SCL1

26

SCL2

34
25

37

SH1

28

SH2

36

SV1

27

SV2

12

NC

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

CC66

CC66

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

VGA_RED
R_DOCK_RED

VGA_GRN
R_DOCK_GRN

VGA_BLU
R_DOCK_BLU

VGA_DDCCLK
D_DDCCLK

VGA_DDCDATA
D_DDCDATA

R_CRT_HSYNC CRT_HSYNC

R385 33_0402_1%R385 33_0402_1%
R386 33_0402_1%R386 33_0402_1%

R_D_HSYNC

R387 33_0402_1%R387 33_0402_1%

R_CRT_VSYNC

R388 33_0402_1%R388 33_0402_1%

R_D_VSYNC

R501 10K_0402_5%R501 10K_0402_5%

VGA_DDCCLK
VGA_DDCDATA

1 2

R502 10K_0402_5%R502 10K_0402_5%

1 2

1

CC62

CC62

CC63

CC63

CC64

CC64

2

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

09/07 Delete VGA_RED, VGA_GRN, VGA_BLU,
VGA_DDCCLK, VGA_DDCDATA, CRT_HSYNC, and
CRT_VSYNC off page symbol

R_DOCK_RED [33]

R_DOCK_GRN [33]

R_DOCK_BLU [33]

D_DDCCLK [33]

D_DDCDATA [33]

1 2
1 2

1 2
1 2

1

CC65

CC65

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CRT_VSYNC

+3VS

+5VS

1

2

D_HSYNC [33]

D_VSYNC [33]

VGA_RED

VGA_GRN

VGA_BLU

1 2

L32 39NH_CS0805-39NJ-S_5%L32 39NH_CS0805-39NJ-S_5%

L33 39NH_CS0805-39NJ-S_5%L33 39NH_CS0805-39NJ-S_5%

1 2

L34 39NH_CS0805-39NJ-S_5%L34 39NH_CS0805-39NJ-S_5%

1 2

182736

45

RP19

RP19
150_0804_8P4R_5%

150_0804_8P4R_5%

10/25 Delete R570, R571,
R572. Add RP19
12/20 Change RP19 to 150ohms

C459 18P_0402_50V8JC459 18P_0402_50V8J

1

2

DP MUX

U26

U26

VDD
VDD
VDD

GPU_SEL
D0­D0+
D1­D1+
D2­D2+
D3­D3+

AUX­AUX+
AUX_HPD_S EL
HPD

GND
GND
GND
HGND

PI3VDP12412ZHEX_TQFN42_9X3P5

PI3VDP12412ZHEX_TQFN42_9X3P5

D47

2

3

YSLC05CH_SOT23-3

YSLC05CH_SOT23-3

@D47

@

AUX-A
AUX+A
HPD_A

AUX-B
AUX+B
HPD_B

07/23 Modify net name

9/21 Correct netname.

1

42

D0-A
D0+A
D1-A
D1+A
D2-A
D2+A
D3-A
D3+A

D0-B
D0+B
D1-B
D1+B
D2-B
D2+B
D3-B
D3+B

DPA_TXN0

41

DPA_TXP0

40

DPA_TXN1

39

DPA_TXP1

38

DPA_TXN2

37

DPA_TXP2

36

DPA_TXN3

35

DPA_TXP3

24
23
16

33
32
31
30
29
28
27
26
19
20
15

25

OE

+3VS

12

SEL_DP_MUX

2N7002KDW_SOT363-6

2N7002KDW_SOT363-6

61

Q76A

Q76A

07/23 Change dual channel MOS Q76

DAC_RED

R573

R573

R574

R574

DAC_GRN

R575

R575

DAC_BLU

C463 18P_0402_50V8JC463 18P_0402_50V8J

C462 18P_0402_50V8JC462 18P_0402_50V8J

1

1

1

2

2

2

VGA_B CRT_HSYNC

R535

R535
10K_0402_5%

10K_0402_5%

1 2

1 2

1 2

07/17 Modify DP MUX solution to PI3VDP12412

1 2

C382 0.1U_0402_16V7KC382 0.1U_0402_16V7K
C381 0.1U_0402_16V7KC381 0.1U_0402_16V7K

1 2
1 2

C386 0.1U_0402_16V7KC386 0.1U_0402_16V7K
C383 0.1U_0402_16V7KC383 0.1U_0402_16V7K

1 2

C385 0.1U_0402_16V7KC385 0.1U_0402_16V7K

1 2
1 2

C384 0.1U_0402_16V7KC384 0.1U_0402_16V7K
C388 0.1U_0402_16V7KC388 0.1U_0402_16V7K

1 2
1 2

C387 0.1U_0402_16V7KC387 0.1U_0402_16V7K

R544 10K_0402_5%R544 10K_0402_5%

1 2

2

ISO_PREP# [13,33]

VGA_RE

0_0805_5%

0_0805_5%

VGA_GR

0_0805_5%

0_0805_5%

VGA_BL VGA_B

0_0805_5%

0_0805_5%

C465 10P_0402_50V8J@C465 10P_0402_50V8J

1

@

@

2

CRT_VSYNC

VGA_DDCCLK

VGA_DDCDATA

D48

@D48

@

2

3

YSLC05CH_SOT23-3

YSLC05CH_SOT23-3

C466 10P_0402_50V8J@C466 10P_0402_50V8J

1

2

C464 18P_0402_50V8JC464 18P_0402_50V8J

MB_DPA_TXN0 [39]
MB_DPA_TXP0 [39]
MB_DPA_TXN1 [39]
MB_DPA_TXP1 [39]
MB_DPA_TXN2 [39]
MB_DPA_TXP2 [39]
MB_DPA_TXN3 [39]
MB_DPA_TXP3 [39]
MB_DPA_AUX# [39]
MB_DPA_AUX [39]
MB_DP_HPD [39]

DPB_TXN0 [33]
DPB_TXP0 [33]
DPB_TXN1 [33]
DPB_TXP1 [33]
DPB_TXN2 [33]
DPB_TXP2 [33]
DPB_TXN3 [33]
DPB_TXP3 [33]
DPB_AUX# [33]
DPB_AUX [33]
DPB_HPD [33]

+3VS

07/23 Delete R545 and C371

F1

F1

1.1A_8VDC_FUSE

1.1A_8VDC_FUSE

21

1 2

R576 0_0805_5%R576 0_0805_5%

R577 0_0805_5%R577 0_0805_5%

1 2

R578 0_0805_5%R578 0_0805_5%

1 2

C467 10P_0402_50V8J@C467 10P_0402_50V8J

1

@

2

1 2

R579 0_0402_5%R579 0_0402_5%

1 2

R580 0_0402_5%R580 0_0402_5%

1

2

3

CRT_HSYNC_RCRT_HSYNC

CRT_VSYNC_R

CRT_VSYNCVGA_G

M/B DP

Docking

D46

D46

RB491D_SOT23-3

RB491D_SOT23-3

1

VGA_R

VGA_G

D49

@D49

@

2

3

YSLC05CH_SOT23-3

YSLC05CH_SOT23-3

+CRTVDD+5VS +RCRT_VCC

W=40mils

JVGA2

JVGA2

6

11

1
7

16

G

G

12

17

G

G

2
8

13

3
9

14

4
10
15

5

C-H_13-12201572CP

C-H_13-12201572CP

CONN@

CONN@

09/12 Modify JVGA2 footprint
10/31 Modify JVGA2 footprint

1

C468

C468

0.1U_0402_10V6K

0.1U_0402_10V6K

1

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

1

2

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2012/03/23 2009/12/31

2012/03/23 2009/12/31

2012/03/23 2009/12/31

4

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Switch/MUX/VGA

Switch/MUX/VGA

Switch/MUX/VGA

LA-9241P

LA-9241P

LA-9241P

of

of

of

36 56Thursday, December 20, 2012

36 56Thursday, December 20, 2012

5

36 56Thursday, December 20, 2012

0.5

0.5

0.5

5

+VCC_SM

12

R391

R391

4.7K_0402_5%

CC68

CC68

4.7K_0402_5%

SCardC8
SCardC6
SCardFcb

12

+5VS

1U_0402_6.3V6K

1U_0402_6.3V6K

2

CC69

CC69

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

1

2

2

D D

+5VS

0.1U_0402_16V7K

0.1U_0402_16V7K

SCardRst
SCardclk

R395 0_0402_5%R395 0_0402_5%

1 2

SCardData

+3VS_SM

C253

C253

0.1U_0402_16V7K

0.1U_0402_16V7K

R396 470_0402_5%R396 470_0402_5%

USBP7-[17]
USBP7+[17]

+VCC_SM

1

2

1

C252

C252

2

4

09/03 Change U30 P/N
11/01 Change U30 to AU9560-GBS-GR

U30

U30

1

SCard0C8

2

SCard0C6

3

SCard0Fcb

4

SMIO_5VPWR

5

SCard0Rst

6

SCard0Clk

7

SCard0Data

8

DM

9

DP

10

AV33

11

SCPWR0

12

5VGND

13

5VInput

+3VS_SM

C257

C257

0.1U_0402_16V7K

0.1U_0402_16V7K

07/20 Vendor's suggestion 07/20 Vendor's suggestion

14

V33OUT

AU9560-GBS-GR_SSOP28

AU9560-GBS-GR_SSOP28

C258

C258

C259

C259

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K

1

1

2

2

PWRSV_SEL

LEDCRD

LEDPWR

RESET

EEPDATA

EEPCLK

P1(6)

ICCInsertN

VDDH
VDDP

V18OUT

28

XO

27

XI

26
25
24
23
22
21
20
19
18
17
16

VDD

15

3

XTAL_OUT
XTAL_IN
PWRSV_SEL#

07/06 Correct netname to follow GPIO table

C255

C255

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

SSDA
SSCL
EEPWP
ICCInsertN

T93 PAD~D @T93 PAD~D @
T94 PAD~D @T94 PAD~D @

T95 PAD~D @T95 PAD~D @

+1.8VS_SM

C256

C256

1

0.1U_0402_16V7K

0.1U_0402_16V7K

2

PWRSV_SEL# [14]

+3VS_SM

PLT_RST# [13,14,25,28,29,30,35,39,5]

09/20 Delete R393, CC67, and connector U30.23 to PLT_RST#

C254

C254

0.1U_0402_16V7K

0.1U_0402_16V7K

1

2

2

1

C C

J3

J3

12

GND

11

GND

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

ACES_51524-0100N-001

ACES_51524-0100N-001

CONN@

CONN@

07/10 Modify J3 footprint
09/12 Modify J3 pin define

B B

C264

C264

C265

C265

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

1

1

@

@

@

@

2

2

C263

C263

0.1U_0402_16V7K

0.1U_0402_16V7K

1

@

@

2

SCardRst
SCardclk
SCardFcb

SCardC6
SCardData
SCardC8
ICCInsertN

07/12 Modify J3 pin define
07/16 Modify J3 pin define

1

2

C260

C260

0.1U_0402_16V7K

0.1U_0402_16V7K

+VCC_SM

@

@

C261

C261

0.1U_0402_16V7K

0.1U_0402_16V7K

1

2

07/20 Vendor's suggestion
11/05 Uninstall Y3, CV33, CV34

CV33 18P_0402_50V8J

CV33 18P_0402_50V8J

@

@

12

RH225

@ RH225

@

1M_0402_5%

1M_0402_5%

@

@

CV34 18P_0402_50V8J

CV34 18P_0402_50V8J

XTAL_OUT

34

21

Y3

@Y3

@

12MHZ_12PF_5YEA12000122IFA2Q3

12MHZ_12PF_5YEA12000122IFA2Q3

11/01 Change Y3 to small package

XTAL_IN

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2012/03/23 2011/06/29

2012/03/23 2011/06/29

2012/03/23 2011/06/29

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Smart Card

Smart Card

Smart Card

1

37 56Thursday, December 20, 2012

37 56Thursday, December 20, 2012

37 56Thursday, December 20, 2012

of

of

of

0.5

0.5

0.5

5

4

3

2

1

Power Board Conn

11/01 Add R626

REC_MUTE_CTRL_KB[26]

ON/OFFBTN_KBC#

D D

2

C270

C270

0.1U_0402_16V7K

0.1U_0402_16V7K

1

LID_SW#[22,30,39]

09/12 Modify JPWR1 connector pin define.
09/12 Modify JPWR1 connector footprint and pin define.
10/26 Modify JPWR1 connector footprint and pin define.

LID_SW#

8051TX_STBYLED#[30,33,39]

ON/OFFBTN_KBC#[30,33]

+5VDS+3VDS

+5VDS
+3VDS

8051TX_STBYLED#
ON/OFFBTN_KBC#

TP/B Conn

SP_LEFT
SP_MID
SP_RIGHT

DDR_XDP_WAN_SMBCLK[11,12,13,16,28,5]

C C

DDR_XDP_WAN_SMBDAT[11,12,13,16,28,5]
TP_DATA[30]
TP_CLK[30]

C298

C298

C297

C297

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

1

1

2

2

D32 YSDA0502C C/A SOT-23D32 YS DA0502C C/A SOT-23

Stick Point CONN

JP13

B B

SP_DATA[30]
SP_CLK[30]

SP_LEFT
SP_MID
SP_RIGHT

+5VS

ACES_50554-0080N-001

ACES_50554-0080N-001

8
7
6
5
4
3
2
1

JP13

CONN@

CONN@

DDR_XDP_WAN_SMBCLK
DDR_XDP_WAN_SMBDAT
TP_DATA
TP_CLK

+3VS

3

223

1

1

07/16 Change P/N for ESD's request
07/20 Change P/N for ESD's request
10/11 Install D32

12

G4

11

G3

10

G2

9

G1

8 8
7
6 6
5
4 4
3
2 2
1

JPWR1

JPWR1

1

221

3

443

5

665

7

887

9

10109

11

121211

ACES_85203-0602N-10

ACES_85203-0602N-10

CONN@

CONN@

JTP1

JTP1

2

112

4

334

6

556

8

778

10

9910

12

111112

14

131314

16

151516

18

171718

20

191920

E-T_6900K-Q10N-00R

E-T_6900K-Q10N-00R

CONN@

CONN@

07/09 Change by follow spec
08/10 Modify JTP1 pin define.

+3VS

1

C296

C296

2

0.1U_0402_16V7K

0.1U_0402_16V7K

KSI[0..7][30]

KSO[0..13][30]

1

KSI0

1

KSI1

1

KSI2

KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0

KSO13
KSO12
KSO11
KSO10

KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0

D33

D33

2

KSI_D_0

3

DAP202UGT106_SOT323-3

DAP202UGT106_SOT323-3

D34

D34

DAP202UGT106_SOT323-3

DAP202UGT106_SOT323-3

D35

D35

DAP202UGT106_SOT323-3

DAP202UGT106_SOT323-3

KSI_D_8

2

KSI_D_1

3

KSI_D_9

2

KSI_D_2

3

KSI_D_10

KB backlight Conn

JP9

JP9

8
6
4
2

ACES_50611-0040N-001

ACES_50611-0040N-001

CONN@

CONN@

09/26 Modify JP9 pin define to follow ME request

KSI_D_0 [39]

KSI_D_1 [39]

+5VS_KBL

778
556
334
112

8051_RECOVER#/_NUM_LOCK_LED#[30]

+5VS

3

S

S

D

D

1

AO3413L_SOT23-3

AO3413L_SOT23-3

KBL_DET# [18]

8051RX_CAPLED#[30]

07/12 Modify KB connector pin define.
07/20 Modify KB connector pin define.
08/07 Change JKB1 footprint
09/12 Change JKB1 footprint09/12 Modify JTP1 pin define and footprint
09/13 Change JKB1 pin define,
10/31 Change JKB1 footprint and pin define,
11/05 Modify JKB1 pin define to follow ME request.

KSI3

KSI4

KSI5

Q47

Q47

2

G

G

@

@

+3VDS

D36

D36

1

DAP202UGT106_SOT323-3

DAP202UGT106_SOT323-3

D37

D37

1

DAP202UGT106_SOT323-3

DAP202UGT106_SOT323-3

D38

D38

1

DAP202UGT106_SOT323-3

DAP202UGT106_SOT323-3

1 2

R408 200K_0402_5%R408 200K_0402_5%

09/27 Change R408 to 200k

0.047U_0402_16V7K

0.047U_0402_16V7K

1

C295

C295

2

1 2

R400 360_0402_5%R400 360_0402_5%

1 2

R626 0_0402_5%R626 0_0402_5%

2

KSI_D_3

3

KSI_D_11

2

KSI_D_4

3

KSI_D_12

2

KSI_D_5

3

KSI_D_13

+5VDS

12

61

Q10A

Q10A

2N7002KDW_SOT363-6

2N7002KDW_SOT363-6

KSO13
KSO12
KSO9
KSI_D_9
KSI_D_11
KSI_D_13
KSI7
KSI_D_6
KSI_D_5
KSO1
KSO10
KSO6
KSO7
KSO4
KSO8
KSO3
KSI_D_3
KSI_D_1
KSI_D_2
KSI_D_4
KSI_D_0
KSI_D_10
KSI_D_12
KSI_D_8
KSI_D_14
KSO5
KSO2
KSO0
KSO11

R407

R407
100K_0402_5%

100K_0402_5%

2

JKB1

JKB1

2
4
6
8

10
12
14
16
18
20
22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54
56

56

58

58

60

60

62

62

64

64

66

66

68

68

GND70GND

HB_A823461-SBVR02

HB_A823461-SBVR02

CONN@

CONN@

D39

D39

1

KSI6

DAP202UGT106_SOT323-3

DAP202UGT106_SOT323-3

KBD_PWM_LED [30]

112
334
556
778

9910
111112
131314
151516
171718
191920

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51
535354

55

55

57

57

59

59

61

61

63

63

65

65

67

67

69

2

KSI_D_6

3

KSI_D_14

C420

C420
C421

C421
C422

C422
C423

C423

C424

C424
C425

C425
C426

C426
C427

C427

C428

C428
C429

C429
C430

C430
C431

C431

C432

C432
C433

C433
C434

C434
C435

C435

C436

C436
C437

C437
C438

C438
C439

C439

C440

C440
C441

C441
C442

C442
C443

C443

C444

C444
C445

C445
C446

C446
C447

C447
C448

C448

1 2
1 2

@

@
1 2
1 2

@

@

1 2
1 2

@

@
1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2
1 2

@

@
1 2

1 2
1 2
1 2
1 2

1 2
1 2

@

@
1 2
1 2

1 2
1 2
1 2
1 2
1 2

100P_0402_50V8J@

100P_0402_50V8J@
100P_0402_50V8J

100P_0402_50V8J
100P_0402_50V8J@

100P_0402_50V8J@
100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J@

100P_0402_50V8J@
100P_0402_50V8J

100P_0402_50V8J
100P_0402_50V8J@

100P_0402_50V8J@
100P_0402_50V8J@

100P_0402_50V8J@

100P_0402_50V8J@

100P_0402_50V8J@
100P_0402_50V8J@

100P_0402_50V8J@
100P_0402_50V8J@

100P_0402_50V8J@
100P_0402_50V8J@

100P_0402_50V8J@

100P_0402_50V8J@

100P_0402_50V8J@
100P_0402_50V8J@

100P_0402_50V8J@
100P_0402_50V8J

100P_0402_50V8J
100P_0402_50V8J@

100P_0402_50V8J@

100P_0402_50V8J@

100P_0402_50V8J@
100P_0402_50V8J@

100P_0402_50V8J@
100P_0402_50V8J@

100P_0402_50V8J@
100P_0402_50V8J@

100P_0402_50V8J@

100P_0402_50V8J@

100P_0402_50V8J@
100P_0402_50V8J

100P_0402_50V8J
100P_0402_50V8J@

100P_0402_50V8J@
100P_0402_50V8J@

100P_0402_50V8J@

100P_0402_50V8J@

100P_0402_50V8J@
100P_0402_50V8J@

100P_0402_50V8J@
100P_0402_50V8J@

100P_0402_50V8J@
100P_0402_50V8J@

100P_0402_50V8J@
100P_0402_50V8J@

100P_0402_50V8J@

KSO12
KSI_D_9
KSI_D_13
KSI_D_6

KSO1
KSO6
KSO4
KSO3

KSI_D_1
KSI_D_4
KSI_D_10
KSI_D_8

KSO13
KSO9
KSI_D_11
KSI7

KSI_D_5
KSO10
KSO7
KSO8

KSI_D_3
KSI_D_2
KSI_D_0
KSI_D_12

KSI_D_14
KSO2
KSO11
KSO0

KSO5

07/24 Add for EMI request

07/09 Change by follow spec
09/12 Delete JTP2 connector

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/03/23 2011/11/02

2012/03/23 2011/11/02

2012/03/23 2011/11/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

KB/TP/LED

KB/TP/LED

KB/TP/LED

1

38 56Thursday, December 20, 2012

38 56Thursday, December 20, 2012

38 56Thursday, December 20, 2012

0.5

0.5

0.5

5

4

3

2

1

VGA+Function Board

+5VDS +5VDS

D D

9/07 Remove JVGA1 BTB connector

iSCT_LED#[30]

USB20

+5VDS

C C

EN_P1V5

USBP9-[17]
USBP9+[17]

07/10 Modify JUB1 footprint and pin define.
07/24 Modify JUB1 pin define.

JUB1

JUB1

112
334
556
778
9910
111112
131314
151516
171718
191920

21

21

22

23

23

24

ACES_50611-0120N-001

ACES_50611-0120N-001

CONN@

CONN@

2
4
6
8
10
12
14
16
18
20
22
24

Function Board

+5VS

KSI_D_0[38]
KSI_D_1[38]
KSO17[30]
MUTE_LED_CNTR[26]
WL/BT_LED#[25]
LID_SW#[22,30,38]

9/07 Add JFUN1 connector
9/12 Modify JFUN1 pin define and footprint
09/26 Modify JFUN1 pin define to follow ME request

KSI_D_0
KSI_D_1
KSO17
MUTE_LED_CNTR
WL/BT_LED#
LID_SW#

JFUN1

JFUN1

20

191920

18

171718

16

151516

14

131314

12

111112

10

9910

8

778

6

556

4

334

2

112

E-T_6900K-Q10N-00R

E-T_6900K-Q10N-00R

CONN@

CONN@

SATA_ACT#[13,33]

+1.5VS

10/23 Add Q80 for iSCT_LED# circuit.

1 2

R623 1K_0402_5%R623 1K_0402_5%

10/24 Change Q80 to
single MOS, Add R623, Q81

WL/BT_LED#

BSS138W-7-F_SOT323-3

BSS138W-7-F_SOT323-3

iSCT_LED#

Q80

Q80

G

G

2

2N7002KW_SOT323-3

2N7002KW_SOT323-3

13

D

S

D

S

D

S

D

S

13

Q81

Q81

G

G

2

10/16 Change JTB1.91 net
name to iSCT_LED#
10/23 Change netname
to TBT_RR_GPIO#

0.01U_0402_16V7K_X7R

0.01U_0402_16V7K_X7R

USBP5-[17]
USBP5+[17]

USB3TN6[17]
USB3TP6[17]

USB3RN6[17]
USB3RP6[17]

MB_DPA_TXP3[36]
MB_DPA_TXN3[36]

MB_DPA_TXP2[36]
MB_DPA_TXN2[36]

MB_DPA_TXP1[36]
MB_DPA_TXN1[36]

MB_DPA_TXP0[36]
MB_DPA_TXN0[36]

PCIE_PTX_EXPRX_N5[17]
PCIE_PTX_EXPRX_P5[17]

PCIE_PRX_EXPTX_N5[17]
PCIE_PRX_EXPTX_P5[17]

CLK_PCIE_EXP#[15]
CLK_PCIE_EXP[15]

CLKREQ_EXP#[15]

USBP6-[17]
USBP6+[17]

MB_DPA_AUX#[36]
MB_DPA_AUX[36]

MB_DP_HPD[36]

PLT_RST#[13,14,25,28,29,30,35,37,5]
8051TX_STBYLED#[30,33,38]
AMBER_BATLED#[30]
BAT_GRNLED#[13,30]
TBT_RR_GPIO#[14]

TB_HOT_PLUG#[17]

07/31 Change JTB1.95 to +3VDS

EN_P1V5

1

C339

C339

2

07/10 Modify JTB1 footprint and pin define.

07/17 Modify JTB1 pin define.

09/13 Modify JTB1 footprint

+1.5VS

+3VDS

+3VDS +3VDS

Thunderbolt

JTB1

JTB1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

61

63

63

65

65

67

67

69

69

71

71

73

73

75

75

77

77

79

79

81

81

83

83

85

85

87

87

89

89

91

91

93

93

95

95

97

97

99

99

101

GND1

ACES_50019-10001-001

ACES_50019-10001-001

CONN@

CONN@

GND2

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

54

56

56

58

58

60

60

62

62

64

64

66

66

68

68

70

70

72

72

74

74

76

76

78

78

80

80

82

82

84

84

86

86

88

88

90

90

92

92

94

94

96

96

98

98

100

100

102

CLK_TB_REFCLK# [15]
CLK_TB_REFCLK [15]

MXM_TB_LANE_N3 [35]
MXM_TB_LANE_P3 [35]

MXM_TB_LANE_N2 [35]
MXM_TB_LANE_P2 [35]

MXM_TB_LANE_N1 [35]
MXM_TB_LANE_P1 [35]

MXM_TB_LANE_N0 [35]
MXM_TB_LANE_P0 [35]

PCIE_PRX_DTX_N4 [17]
PCIE_PRX_DTX_P4 [17]

PCIE_PTX_C_DRX_N4 [17]
PCIE_PTX_C_DRX_P4 [17]

PCIE_PRX_DTX_N3 [17]
PCIE_PRX_DTX_P3 [17]

PCIE_PTX_C_DRX_N3 [17]
PCIE_PTX_C_DRX_P3 [17]

PCIE_PRX_DTX_N2 [17]
PCIE_PRX_DTX_P2 [17]

PCIE_PTX_C_DRX_N2 [17]
PCIE_PTX_C_DRX_P2 [17]

PCIE_PRX_DTX_N1 [17]
PCIE_PRX_DTX_P1 [17]

PCIE_PTX_C_DRX_N1 [17]
PCIE_PTX_C_DRX_P1 [17]

MXM_TB_AUX# [35]
MXM_TB_AUX [35]
TB_HPD [35]
EN_P1V5 [30,33,40,44,45]
CPPWR_EN [30]
TB_CLKREQ# [15]

HDD_HALTLED [13]

07/18 Remove B+ and change to HDD_HALTLED07/18 Add PWR_GD signal

B B

Card Reader Board

JCR1

+5VDS +3VS

USBP4-[17]
USBP4+[17]

USB3RN5[17]
USB3RP5[17]

USB3TN5[17] PCIE_PTX_C_DRX_P8 [17]

08/10 Change JCR1.21 connection to +3VS
08/10 Change JCR1.21 connection to +3VDS

A A

08/01 JCR1.35 connection to PCH_PCIE_WAKE#
10/16 Delete R602, connection JCR1.5 to +5VDS

USB3TP5[17]

07/19 Modify pin define
for better return path

+5VDS

HP_SENSE#[27]

09/19 Add R602, and noninstall.

5

+3VS
+3VS

EN_P1V5

JCR1

GND45GND
GND43GND
GND41GND

39

39

40

37

37

38

35

35

36

33

33

34

31

31

32

29

29

30

27

27

28

25

25

26

23

23

24

21

21

22

19

19

20

17

17

18

15

15

16

13

13

14

11

11

12

9

9

10

7

7

8

5

5

6

3

3

4

1

1

2

ACES_50103-04071-001

ACES_50103-04071-001

CONN@

CONN@

46
44
42

40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

PLT_RST#

07/30 Modify JCR1 pin define and footprint.
08/07 Change JCR1 footprint
08/08 Change JCR1 pin define

07/19 Modify pin define
for better return path

CLK_PCIE_CR [15]
CLK_PCIE_CR# [15]

PCIE_PRX_DTX_P8 [17]
PCIE_PRX_DTX_N8 [17]

PCIE_PTX_C_DRX_N8 [17]

CR_CLK_REQ# [15]

EXT_MIC_L2 [27]

HP_OUT_R [26]

HP_OUT_L [26]

7/13 Modify pin net name

4

+3VS

NFC_3S_SMBDAT[16] NFC_3S_SMBCLK [16]
NFC_INT[18]
UIM_VPP[25]
NFC_TX[30]

1 2

R558 0_0402_5%

R558 0_0402_5%

100K_0402_5%

100K_0402_5%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

NFC_SW

@

@

12

R538

R538

NFC CONN

JNFC1

JNFC1

GND
GND

12
10
8
6
4
2

CONN@

CONN@

GND
GND

15
13

11

11

9

9

7

7

5

5

3

3

1

1

Compal Secret Data

Compal Secret Data

Compal Secret Data

16
14

12
10

8
6
4
2

ACES_50559-01201-001

ACES_50559-01201-001

2012/03/23 2010/03/31

2012/03/23 2010/03/31

2012/03/23 2010/03/31

07/06 Add NFC connector
07/09 Modify Pin define
07/30 Modify Pin define.
08/07 Modify JNFC1 footprint and pin define
08/08 Modify JNFC1 pin define
09/21 Delete R557, Non-install R358, C374

NFC_SEL_R

Deciphered Date

Deciphered Date

Deciphered Date

NFC_RST# [16]

NFC_RX [30]

2

+3V_PCH

12

R358

+3VS

1

C374

C374

@

@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

R358

@

@

10K_0402_5%

10K_0402_5%

NFC_SEL_R

12

R556

R556

@

@

10K_0402_5%

10K_0402_5%

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

I/O CONN

I/O CONN

I/O CONN

LA-9241P

LA-9241P

LA-9241P

1

0.5

0.5

39 56Thursday, December 20, 2012

39 56Thursday, December 20, 2012

39 56Thursday, December 20, 2012

0.5

A

USB Power Switch

+5VDS

U43

U43

1

1 1

C481

C481

C476

C476

1

1

680P_0603_50V7K

680P_0603_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

12

2

2

2 2

EN_P1V5[30,33,39,44,45]

C483

C483

0.1U_0402_16V4Z

0.1U_0402_16V4Z

09/24 Delete Q79, Q80, C475, C477, C478, R588, R587.

EN_P1V5

change power switch to high active parts
20120803

Add DC to DC interface
2012/8/3

2

4

GND

VOUT
VOUT

VIN
VIN3VOUT

FLG

EN

G547I1P81U_MSOP8

G547I1P81U_MSOP8

8
7
6
5

B

9/07 Add USB3.0 repeater and connector

+USB_CS

W=100milsW=100mils

C484

C484

C475

C475

C479

C479

150U_B2_6.3VM_R45M

150U_B2_6.3VM_R45M

1

+

+

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1000P_0402_50V7K

1000P_0402_50V7K

1

1

2

12

2

C480

C480

C

09/24 Change power rail to +3VS

A_DE0

A_DE1

A_EQ0

A_EQ1

680P_0603_50V7K

680P_0603_50V7K

+3VS

1

C502

C502

10U_0603_6.3V6M

10U_0603_6.3V6M

2

09/26 Add C502

1 2

R590 4.7K_0402_5%@R590 4.7K_0402_5%@

1 2

R591 4.7K_0402_5%@R591 4.7K_0402_5%@

1 2

R596 4.7K_0402_5%@R596 4.7K_0402_5%@

1 2

R595 4.7K_0402_5%@R595 4.7K_0402_5%@

09/24 Change power rail to +3VS

FORM CPU

USB3TP2[17]
USB3TN2[17]

C473 0.1U_0402_25V6KC473 0.1U_0402_25V6K
C471 0.1U_0402_25V6KC471 0.1U_0402_25V6K

+3VS

+3VS

2

1

C482

C482

1

2

0.01U_0402_50V7K

0.01U_0402_50V7K

09/24 Change power rail to +3VS

1 2
1 2

FORM USB CONNECTOR

09/24 Change power rail to +3VS

1 2

R592 4.7K_0402_5%

R592 4.7K_0402_5%

@

@

Chip test mode enable.

3.3V tolerant. Internally pulled down at
~150K

次

.
TEST ==
L: Normal operation (default)
H: Test mode enable

+3VS

Programmable output pre-emphasis level setting for channel A

3.3V tolerant. Internally pulled down at ~150K
[A_EQ1, A_EQ0] ==
LL: 3.5dB de-emphasis
LH: No de-emphasis
HL: 5dB de-emphasis
HH: Reserved

Equalizer control and program for channel A

3.3V tolerant. Internally pulled down at
~150K

次

[A_EQ1, A_EQ0] ==
LL: adaptive EQ enable
LH: program EQ at 3.5dB
HL: program EQ at 6dB
HH: program EQ at 10dB

C469

C469

0.1U_0402_25V6K

0.1U_0402_25V6K

+3VS

A_EQ1
A_DE0
A_EQ0
A_DE1

USB3_C_TP2
USB3_C_TN2

USB3_RP2_RE USB3_C_RP2
USB3_RN2_RE

12

R598

R598

4.99K_0402_1%

4.99K_0402_1%

Folow ESD team recommeend change ESD diode D5 D6
20120713

USB3.0 Repeater

VDD : 1.5V for PS8713A
VDD : 3.3V for PS8713B

TESTTEST

次

U44

U44

1

VDD

13

VDD

15

A_EQ1/SDA_CTL

16

A_DE0/SCL_CTL

17

A_EQ0/NC

18

A_DE1/NC

19

A_INp

20

A_INn

9

B_INp

8

B_INn

5

PD#

7

REXT

14

TEST

24

I2C_EN

PS8713BTQFN24GTR2_TQFN24_4X4

PS8713BTQFN24GTR2_TQFN24_4X4

B_EQ1/I2C_ADDR1
B_DE0/I2C_ADDR0

B_EQ0/NC
B_DE1/NC

A_OUTp
A_OUTn

B_OUTp
B_OUTn

GND
GND

GPAD

D

4
3
2
6

12
11

22
23

10
21
25

B_EQ0

R594 4.7K_0402_5%@R594 4.7K_0402_5%@

B_EQ1

R589 4.7K_0402_5%@R589 4.7K_0402_5%@

B_DE0

R593 4.7K_0402_5%@R593 4.7K_0402_5%@

B_DE1

R597 4.7K_0402_5%@R597 4.7K_0402_5%@

B_EQ1
B_DE0
B_EQ0
B_DE1

USB3_C_TP2_RE
USB3_C_TN2_RE

USB3_C_RN2

09/24 Change power rail to +3VS

+3VS

1 2

1 2

1 2

1 2

1 2

C470 0.1U_0402_25V6KC470 0.1U_0402_25V6K

1 2

C474 0.1U_0402_25V6KC474 0.1U_0402_25V6K

1 2

C486 0.1U_0402_25V6KC486 0.1U_0402_25V6K

1 2

C472 0.1U_0402_25V6KC472 0.1U_0402_25V6K

E

Equalizer control and program for channel B

3.3V tolerant. Internally pulled down at
~150K

次

[B_EQ1, B_EQ0] ==
LL: adaptive EQ enable
LH: program EQ at 3.5dB
HL: program EQ at 6dB
HH: program EQ at 10dB

Programmable output pre-emphasis level setting for channel B

3.3V tolerant. Internally pulled down at ~150K
[B_EQ1, B_EQ0] ==
LL: 3.5dB de-emphasis
LH: No de-emphasis
HL: 5dB de-emphasis
HH: Reserved

USB3_TP2_RE
USB3_TN2_RE

TO USB CONNECTOR

USB3RP2 [17]
USB3RN2 [17]

次

TO CPU

D50

3 3

9/17 Swap L35, L36, L37 for layout smoothly

R583 0_0402_5%@R583 0_0402_5%@

USB3_TN2_RE

USB3_TP2_RE USB3TXDP2_R

USB3_RN2_RE

4 4

A

USB3_RP2_RE

USBP1-[17]

USBP1+[17]

1 2

L36

L36

4

4

1

1

WCM-2012-900T_4P

WCM-2012-900T_4P

1 2

R586 0_0402_5%@R586 0_0402_5%@
R584 0_0402_5%@R584 0_0402_5%@

1 2

L37

L37

4

4

1

1

WCM-2012-900T_4P

WCM-2012-900T_4P

1 2

R582 0_0402_5%@R582 0_0402_5%@

R585 0_0402_5%@R585 0_0402_5%@

1 2

L35

L35

4

4

1

1

WCM-2012-900T_4P

WCM-2012-900T_4P

1 2

R581 0_0402_5%@R581 0_0402_5%@

USB3TXDN2_R

3

3

2

2

USB3RXDN2_R

3

3

2

2

USB3RXDP2_R

USB20_N1_R

3

3

2

2

USB20_P1_R

B

TO USB connector TX

TO USB connector RX

USB3RXDN2_R USB3RXDN2_R

USB3RXDP2_R

USB3TXDN2_R

USB3TXDP2_R

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D50

1

2

4

5

3

TVWDF1004AD0_DFN9

TVWDF1004AD0_DFN9

USB20_N1_R

USB20_P1_R

2

3

D51

D51
YSLC05CH_SOT23-3

YSLC05CH_SOT23-3

1

9

8

USB3RXDP2_R

7

USB3TXDN2_R

6

USB3TXDP2_R

@

@

Compal Secret Data

Compal Secret Data

2012/05/11 2013/05/11

2012/05/11 2013/05/11

2012/05/11 2013/05/11

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

USB3.0 Connector

+USB_CS

2.5A

JUSB1

JUSB1

1

VBUS

USB20_N1_R
USB20_P1_R

USB3RXDN2_R
USB3RXDP2_R

USB3TXDN2_R
USB3TXDP2_R

9/13 Modify JUSB1 footprint and pin define

2

D-

3

D+

4

GND

5

SSRX-

6

SSRX+

7

GND

8

SSTX-

9

SSTX+

LOTES_AUSB0041-P002A

LOTES_AUSB0041-P002A

CONN@

CONN@

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

USB3.0 CONN/Repeater

USB3.0 CONN/Repeater

USB3.0 CONN/Repeater

10

GND

11

GND

12

GND

13

GND

LA-9241P

E

40 56Thursday, December 20, 2012

40 56Thursday, December 20, 2012

40 56Thursday, December 20, 2012

0.5

0.5

0.5

5

4

3

2

1

ADP_EN

DC IN

D D

Main
BATT

2nd
BATT

C C

ACFET RBFET

Battery
Selector

BATT

Charger

BQ24736

ACDRV

ACDRV

RBFET

B+

B++

EN_P1V5

SLP_S3#

SIO_SLP_A#

RT8243AZQW

EN

RT8207M

EN

TPS51212

EN

TPS51631

+3VDSP

+1.35VP
+1.5VP

+0.675VSP
+0.75VSP

+CPU_CORE

Jumper

Jumper

Jumper

Jumper

Jumper

+3VDS

+5VDS+5VDSP

+1.35V
+1.5V

+0.675VS
+0.75VS

+1.05VM+1.05VMP

+3VS

SY8032

+3VS

EN

7/19

+1.5VSP +1.5VS

B B

VR_ON

EN

A A

5

4

3

2

1

5

ADP_SIGNAL

PJP1

PJP1

D D

1

3

5

7

9

ACES_59 012-0100N-002

ACES_59 012-0100N-002

@

@

2

2

1

4

4

3

6

6

5

8

8

7

10

10

9

ADPIN I2C_MAIN_CLK -1

12

2

3

1

12

PC1

PC1

100P_0402_50V8J

100P_0402_50V8J

PD1

PD1
L30ESD2 4VC3-2_SOT23-3

L30ESD2 4VC3-2_SOT23-3

PC4

PC4

VIN

4

PJP2 Zero force Footprint:
FOX_BP0208C-B24B1-9HQ_8P-T

PL1

PL1

HCB2012 KF-121T50_080 5

HCB2012 KF-121T50_080 5

1 2

PL2

PL2

HCB2012 KF-121T50_080 5

HCB2012 KF-121T50_080 5

1 2

PL3

PL3

HCB2012 KF-121T50_080 5

HCB2012 KF-121T50_080 5

1 2

1000P_0402_50V7K

1000P_0402_50V7K

12

PC5

PC5

PC6

PC6

100P_0402_50V8J

100P_0402_50V8J

3

PD11

PD11
AZC099-0 4S.R7G SOT23 ES D

+3VDS

PJP2

PJP2
FOXCONN BP0208C-B24B1 -9H 8P BATT@

VIN

12

12

1000P_0402_50V7K

1000P_0402_50V7K

PR1

@P R1

@

15K_040 2_5%

15K_040 2_5%

FOXCONN BP0208C-B24B1 -9H 8P BATT@

1

1

2

2

3
4
5
6
7
8

I2C_MAIN_DAT -1

3
4
5
6
7
8

AZC099-0 4S.R7G SOT23 ES D

4

V I/O

5

Ground

V BUS

6

V I/O

7/11

12

PR3

PR3

MAIN_BAT_DET#[30]

V I/O

V I/O

1K_0402_5%

1K_0402_5%

2

PD10

PD10
L30ESD2 4VC3-2_SOT23-3

VMB_A

12

PC10

PC10
100P_04 02_50V8J

100P_04 02_50V8J

100_0402_5%

100_0402_5%

2

3

12

L30ESD2 4VC3-2_SOT23-3

PC3

PC3
1000P_0 402_50V7K

1000P_0 402_50V7K

1

PL4

PL4

HCB2012 KF-121T50_080 5

HCB2012 KF-121T50_080 5

1 2

1 2

PL5

PL5

HCB2012 KF-121T50_080 5

HCB2012 KF-121T50_080 5

3

2

1

12

PC8

PC8

12

PC2

PC2

0.1U_060 3_50V7K

0.1U_060 3_50V7K

12

PR4

PR4

100P_0402_50V8J

100P_0402_50V8J

12

12

100_0402_5%

100_0402_5%

PR5

PR5

PC9

PC9

100P_0402_50V8J

100P_0402_50V8J

1

BATT_A

12

I2C_MAIN_DAT [30,43]

I2C_MAIN_CLK [30,4 3]

PC7

PC7

0.01U_04 02_50V7K

0.01U_04 02_50V7K

PR13

PR13

3.9K_0402_5%

3.9K_0402_5%

5

PQ1A

PQ1A

PQ2B

PQ2B

VIN

ME2N7002DKW-G 2N SOT363-6

ME2N7002DKW-G 2N SOT363-6

12

SD028680380

PR10

PR10

+3VDS

680K_0402_5%

680K_0402_5%

61

2

+3VDS

12

5

3 4

61

ME2N7002DKW-G 2N SOT363-6

ME2N7002DKW-G 2N SOT363-6

12

PR11

PR11

10K_0402_5%

10K_0402_5%

12

PR12

PR12

30K_0402_5%

30K_0402_5%

SD028300080

PR15

PR15

300_0402_5%

300_0402_5%

PQ2A

PQ2A

2

12

PR16

PR16

ME2N7002DKW-G 2N SOT363-6

ME2N7002DKW-G 2N SOT363-6

4

PD12

PD13

PD13
AZC099-0 4S.R7G SOT23 ES D

+3VDS

PJP3

PJP3

1

1

2

2

3
4
5
6
7
8

I2C_BAY_DAT-1
I2C_BAY_CLK-1

3
4
5
6
7
8

FOX_BR0 208C-Z71H1-9H

FOX_BR0 208C-Z71H1-9H

CONN@

CONN@

AZC099-0 4S.R7G SOT23 ES D

4

V I/O

V I/O

5

Ground

V BUS

6

V I/O

V I/O

7/11

12

PR7

PR7

3

2

1

12

PC14

PC14

1K_0402_5%

1K_0402_5%

12

PC11

PC11

0.1U_060 3_50V7K

0.1U_060 3_50V7K

12

PR8

PR8

100P_0402_50V8J

100P_0402_50V8J

12

12

100_0402_5%

100_0402_5%

PR9

PR9

PC15

PC15

100P_0402_50V8J

100P_0402_50V8J

TRAVEL_BAT_DET#[30]

100K_0402_5%

100K_0402_5%

Security Class ification

Security Class ification

Security Class ification

2012/04/03

2012/04/03

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/04/03

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2014/12/31

2014/12/31

2014/12/31

2

Title

Title

Title

Size Doc ument Number Rev

Size Doc ument Number Rev

Size Doc ument Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

PD12
L30ESD2 4VC3-2_SOT23-3

L30ESD2 4VC3-2_SOT23-3

2

3

VMB_B

12

PC12

PC12
1000P_0 402_50V7K

1000P_0 402_50V7K

12

PC16

PC16
100P_04 02_50V8J

100P_04 02_50V8J

100_0402_5%

100_0402_5%

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

DC Conn/BATT Conn

DC Conn/BATT Conn

DC Conn/BATT Conn

15W

15W

15W

Thursday, December 20 , 2012

Thursday, December 20 , 2012

Thursday, December 20 , 2012

1

PL6

PL6

HCB2012 KF-121T50_080 5

HCB2012 KF-121T50_080 5

1 2

1 2

PL7

PL7

HCB2012 KF-121T50_080 5

HCB2012 KF-121T50_080 5

1

BATT_B

12

PC13

PC13

0.01U_04 02_50V7K

0.01U_04 02_50V7K

I2C_BAY_DAT [30]

I2C_BAY_CLK [3 0]

0.3

0.3

0.3

5242

5242

5242

PQ1B

PQ1B

12

34

ME2N7002DKW-G 2N SOT363-6

ME2N7002DKW-G 2N SOT363-6

C C

PR14 300K_0 402_5%P R14 300K_ 0402_5%

1 2

SB00000SA00

B B

SB00000SA00

A A

5

5

4

3

2

1

P2 B+P1VIN

PQ102

PQ101 AO 4423L 1P SO8PQ101 AO4423L 1P SO8

1
2
3 6

D D

12

12

PR101

PR101

220K_0402_5%

220K_0402_5%

61

2

12

PC101

PC101

PR103

PR103

220K_0402_5%

220K_0402_5%

0.1U_0402_25V6

0.1U_0402_25V6

ACFET_CHG

PQ103A

PQ103A
ME2N7002DKW -G 2N SOT363-6

ME2N7002DKW -G 2N SOT363-6

8
7

5

4

21

PD101

PD101

@

@

SB00000SA00

34

PQ103B

PQ103B

ME2N7002DKW-G 2N SOT363-6

ME2N7002DKW-G 2N SOT363-6

PR114

PR114

18.2K_0402_1%

18.2K_0402_1%

PD104

PD104
LL4148_LL34-2

LL4148_LL34-2

PR118

PR118
10K_0402_1%

10K_0402_1%

CHRG_RST [30]

12

12

PR107

PR107

100K_0402_5%

100K_0402_5%

ADP_EN [30]

12

PR115

PR115
127K_0402_1%

127K_0402_1%

12

PR119

PR119
20K_0402_1%

20K_0402_1%

2

G

G

+3VDS

4/11

12

PR113

PR113
22K_0402_1%

22K_0402_1%

12

PR116

PR116
1M_0402_5%

1M_0402_5%

12

PC122

PC122

100P_0402_50V8 J

100P_0402_50V8 J

13

D

D

PQ108

PQ108

S

S

2N7002KW 1N SOT323-3

2N7002KW 1N SOT323-3

I2C_MAIN_DAT[30,42]

I2C_MAIN_CLK[30,42]

SRSET[50]

V_3.9K[50]

+3VDS

5

C C

+5VS VIN

12

12

B B

PQ102
MDU1512RH 1N PO WERDFN56-8

MDU1512RH 1N PO WERDFN56-8

1
2
3

4

12

12

PR104

PR104

4.12K_0603_1%

4.12K_0603_1%

BAT54WS-7-F_SOD323-2~D

BAT54WS-7-F_SOD323-2~D

BQ24736RGRR_QFN20_3P 5X3P5

BQ24736RGRR_QFN20_3P 5X3P5

4/12

CHRG_ADP_DET [30]

4/12

12

PR105

PR105

4.12K_0603_1%

4.12K_0603_1%

PR127

PR127
10_0402_1%

10_0402_1%

1 2

1 2

PR128

PR128
10_0402_1%

10_0402_1%

PR117

PR117
10K_0402_5%

10K_0402_5%

1 2

PR122

PR122
0_0402_5%

0_0402_5%

1 2

PC125

PC125

100P_0402_50V8 J

100P_0402_50V8 J

PL101

BST_CHG-1

12

0.047U_0402_25V7K

0.047U_0402_25V7K

PL101
1UH_PCMB053T-1R0M S_7A_20%

1UH_PCMB053T-1R0M S_7A_20%

1 2

PR108

PR108

1 2

2.2_0402_1%

2.2_0402_1%

PC112

PC112

1 2

4

12

12

PC103

PC103

@

@

10U_0805_25V6K

10U_0805_25V6K

PQ104

PQ104
AON7408L_DFN8-5

AON7408L_DFN8-5

3 5

241

4.7U 20% VMPI0703AR-4R7M-Z01 5.5A

4.7U 20% VMPI0703AR-4R7M-Z01 5.5A

1 2

12

PR111

5

PR111

4.7_1206_5%

4.7_1206_5%

SNB_CHG

12

PQ106

PQ106

AON7406L_DFN8-5

AON7406L_DFN8-5

123

PC121

PC121

680P_0402_50V7 K

680P_0402_50V7 K

12

PC105

PC105

PC104

PC104

10U_0805_25V6K

10U_0805_25V6K

PL102

PL102

12

10U_0805_25V6K

10U_0805_25V6K

12

12

PC106

PC106

PC107

PC107

0.1U_0402_25V6

0.1U_0402_25V6
2200P_0402_50 V7K

2200P_0402_50 V7K

for RF request, 8/6

PR110

PR110

0.02_1206_1%

0.02_1206_1%

1

CHG

2

CSOP1

12

PC113

PC113

0.1U_0402_25V6

0.1U_0402_25V6

12

PC138

PC138

PC108

PC108

@

@

@

@

68P_0402_50V8J

68P_0402_50V8J

82P 50V J NPO 0402

82P 50V J NPO 0402

PQ105

PQ105

P2

AO4409L 1P SO8

AO4409L 1P SO8

1
2
3 6

P1

8
7

5

4

BATT

4

3

CSON1

12

PC114

PC114

0.1U_0402_25V6

0.1U_0402_25V6

12

PD102

PD102

2 1

RB551V-30_SOD323-2

RB551V-30_SOD323-2

12

12

PC11510U_0805_25V6K PC11510 U_0805_25V6K

12

PC11610U_0805 _25V6K PC11610U_0805_25V6K

PC117220 0P_0402_50V7K PC1172200 P_0402_50V7K

12

12

PC1551U_06 03_25V6K@PC1551U_06 03_25V6K

PC154

PC154

PC1180.01U_0402_50V7K PC1180.01U_0402_50V7K

0.1U_0402_25V6

0.1U_0402_25V6

@

@

@

PR102

PR102

0.005_1206_1%

0.005_1206_1%

ACDRV_CHG

4

ACDRV

SRN_CHG

0.1U_0402_25V6

0.1U_0402_25V6

12

PC109

PC109

CMSRC_CHG

3

CMSRC

SRP_CHG

12

@

@

1

2

0.1U_0402_25V6

0.1U_0402_25V6

PC126

PC126

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

5

CHRG_ADP_DET

PU102

PU102

5

6

ACPRES

ACDET

7

ICS

IOUT

8

SDA

9

SCL

10

ILIM

0.01U_0402_50 V7K

0.01U_0402_50 V7K

12

PC123

PC123

DLIM11SRN12SRP13GND14LODRV

0.01U_0402_50 V7K

0.01U_0402_50 V7K

12

PC119

PC119

PC102

PC102

1 2

ACN_CHG

ACP_CHG

2

21

1

ACP

ACN

VCC

PHASE

HIDRV

BTST

REGN

15

DL_CHG

PR120

PR120
0_0402_5%

0_0402_5%

1 2

PR121

PR121
0_0402_5%

0_0402_5%

1 2

CURRENT_ADC [30]

4

3

12

PC110

PC110

0.1U_0402_25V6

0.1U_0402_25V6

B+

12

PR109

PR109
10_1206_1%

10_1206_1%

PC111

PAD

20

VCC_CHG

19

LX_CHG

18

DH_CHG

17

BST_CHG

16

REGN_CHG

12

PC120

PC120
1U_0603_25V6K

1U_0603_25V6K

PC111
1U_0603_25V6K

1U_0603_25V6K

1 2

PR112

PR112

2.2_0402_1%

2.2_0402_1%

1 2

PD103

PD103

RB751V-40_SOD323-2

RB751V-40_SOD323-2

12

PC124

PC124

0.1U_0603_25V7K

0.1U_0603_25V7K

Remove 6 *2200pF MLCC for RF request, 11/6

B+

VIN

PR125

5

12

PR125
576K_0402_1%

576K_0402_1%

1 2

PC127

PC127

100P_0402_50V8 J

100P_0402_50V8 J

PR124

PR124

49.9K_0402_1%

49.9K_0402_1%

1 2

A A

SD034576380

12

PR126

PR126

49.9K_0402_1%

49.9K_0402_1%

12

PC128

PC128

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

VOLTAGE_ADC [30]

4

12

PC130

PC130

@

@

0.1U_0402_25V6

0.1U_0402_25V6

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

12

12

@

@

12

PC139

PC139

PC133

PC131

PC131

6.8P_0402_50V8C

6.8P_0402_50V8C

PC133

@

@

@

@

0.1U_0402_25V6

0.1U_0402_25V6

82P 50V J NPO 0402

82P 50V J NPO 0402

2012/04/03

2012/04/03

2012/04/03

3

12

12

PC134

PC134

@

@

@

@

6.8P_0402_50V8C

6.8P_0402_50V8C

Compal Secret Data

Compal Secret Data

Compal Secret Data

12

PC140

PC140

@

@

82P 50V J NPO 0402

82P 50V J NPO 0402

Deciphered Date

Deciphered Date

Deciphered Date

12

PC136

PC136

@

@

0.1U_0402_25V6

0.1U_0402_25V6

12

12

PC141

PC141

PC143

@

@

82P 50V J NPO 0402

82P 50V J NPO 0402

2014/12/31

2014/12/31

2014/12/31

2

PC143

@

@

0.1U_0402_25V6

0.1U_0402_25V6

PC137

PC137

6.8P_0402_50V8C

6.8P_0402_50V8C

12

12

@

@

12

PC145

PC145

PC144

PC144

@

@

@

@

6.8P_0402_50V8C

6.8P_0402_50V8C
82P 50V J NPO 0402

82P 50V J NPO 0402

12

12

12

PC149

PC147

PC147

0.1U_0402_25V6

0.1U_0402_25V6

PC149

PC148

PC148

@

@

6.8P_0402_50V8C

6.8P_0402_50V8C

PC151

PC151

@

@

@

@

82P 50V J NPO 0402

82P 50V J NPO 0402

for RF request, 8/6

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

CHARGER

CHARGER

CHARGER

Size D ocument Number Rev

Size D ocument Number Rev

Size D ocument Number Rev

15W

15W

15W

Date: Sheet of

Thursday, December 20, 2012

Date: Sheet of

Thursday, December 20, 2012

Date: Sheet of

Thursday, December 20, 2012

1

12

12

PC153

PC153

PC152

PC152

@

@

@

@

0.1U_0402_25V6

0.1U_0402_25V6

6.8P_0402_50V8C

6.8P_0402_50V8C
82P 50V J NPO 0402

82P 50V J NPO 0402

0.3

0.3

0.3

5243

5243

5243

5

+5VLP

+3VDS

D D

34

5

KBC_PWR_ON[30,34]

B+

1 2

PJP301

@PJ P301

@

PAD-OPEN 1x3m

PAD-OPEN 1x3m

C C

For RF request, 11/5

+3VDSP

12

@

@

for RF request, 8/6

B B

12

PC324

PC324

12

12

PC328

PC328

PC327

PC327

PC326

PC326

@

@

@

@

0.1U_0402_25V6

0.1U_0402_25V6
2200P_0402_50 V7K

2200P_0402_50 V7K

B++

12

12

PC322

PC322

@

@

100P_0402_50V8J

100P_0402_50V8J

68P_0402_50V8J

68P_0402_50V8J

for RF request, 8/6 for RF request, 8/6

SH00000PH00

1

12

PC329

PC329

2

6.8P_0402_50V8C

6.8P_0402_50V8C

100P_0402_50V8J

100P_0402_50V8J

12

PC305

PC305

@

@

@

@

2200P_0402_50V7K

2200P_0402_50V7K

PL303

PL303

4.7U 20% VMPI0703AR -4R7M-Z01 5.5A

4.7U 20% VMPI0703AR -4R7M-Z01 5.5A

1 2

+

+

PC314

PC314

220U_6.3V_M

220U_6.3V_M

12

PQ305B

PQ305B

SB00000SA00

ME2N7002DKW-G 2N SOT363-6

ME2N7002DKW-G 2N SOT363-6

12

PC303

PC303

PC304

PC304

0.1U_0402_25V6

0.1U_0402_25V6
10U_0805_25V6K

10U_0805_25V6K

PR314

PR314

4.7_1206_5%

4.7_1206_5%

PC313

PC313

680P_0402_50V7K

680P_0402_50V7K

PR326

PR326

12

12

12

2N7002KW 1N SOT323-3

2N7002KW 1N SOT323-3

100K_0402_1%

100K_0402_1%

2

PQ301

PQ301

5

PC334

PC334

10U_0805_25V6K

10U_0805_25V6K

123

5

123

4

PQ306

PQ306

PQ305A

PQ305A

61

ME2N7002DKW-G 2N SOT363-6

ME2N7002DKW-G 2N SOT363-6

4

0.1U_0603_25V7K

0.1U_0603_25V7K

SIS412DN-T1-GE3_POWERPAK8-5

SIS412DN-T1-GE3_POWERPAK8-5

PQ303

PQ303

4

AON7406L_DFN8-5

AON7406L_DFN8-5

13

D

D

2

EN_P1V5 [30,33,39,40,45]

G

G

S

S

13.7K_0402_1%

PR311

@PR3 11

@

0_0402_5%

0_0402_5%

1 2

PR313

PR313

2.2_0603_5%

2.2_0603_5%

1 2

12

PC319

PC319

0.1U_0603_25V7K

0.1U_0603_25V7K

13.7K_0402_1%

20K_0402_1%

20K_0402_1%

PG_3V_5V

PR321

PR321

499K_0402_1%

499K_0402_1%

1 2

+3VDSP

For HP request, 11/5

3VDS_PG

PC310

PC310

12

BST_3V-1

B++

PC320

PC320
100P_0402_50V8J

100P_0402_50V8J

1 2

PR304

PR304

1 2

PR306

PR306

BST_3V

UG_3V

LX_3V

LG_3V

PR316
0_0402_5%

0_0402_5%

1 2

12

PU301

PU301

6

PGOOD

7

BOOT2

8

UGATE2

9

PHASE2

10

LGATE2

ENLDO_3V_5V

12

PR325

PR325

100K_0402_1%

100K_0402_1%

FB_3V

5

3

@PR316

@

12

12

1 2

PR309 115K_0402_1%PR309 115K_0402_1%

PR310 68K_0603_5%PR310 68K_0603_5%

PR308 124K_0402_1%PR308 124K_0402_1%

ENTRIP2

ENTRIP1

2

4

3

FB2

TON

ENTRIP1

ENTRIP2

RT8243AZQW WQFN 20P

RT8243AZQW WQFN 20P

VIN11ENLDO12ENM13LDO514LDO3

12

12

PC316

PC316

1U_0402_10V6K

1U_0402_10V6K

12

PR32410K_0402_1% PR32410K_0402_1%

PR305

PR305

30K_0402_1%

30K_0402_1%

PR307

PR307

20K_0402_1%

20K_0402_1%

1 2

FB_5V

1

FB1

PAD

BYP1

BOOT1

UGATE1

PHASE1

LGATE1

15

12

PC302

PC302

4.7U_0805_10V6K

4.7U_0805_10V6K

PC317

PC317

4.7U_0805_10V6K

4.7U_0805_10V6K

21

20

19

BST_5V

18

UG_5V

17

LX_5V

16

LG_5V

12

PR312

PR312

2.2_0603_5%

2.2_0603_5%

1 2

+3VLP

Typ: 175mA

+5VLP

Typ: 225mA

+5VDSP

12

PC321

PC321
1U_0402_10V6K

1U_0402_10V6K

BST_5V-1

2

PC311

PC311

0.1U_0603_25V7K

0.1U_0603_25V7K

1 2

1

<1>5V=283KHz 3V=330KHz (Vin=6.5 ~ 12v)
<2>5V=321KHz 3V=375KHz (Vin=12 ~ 25v)
(By Rton= 68K ohm)

For RF request, 11/5

12

PC306

5

PQ302

PQ302

4

SIS412DN-T1-GE3_POW ERPAK8-5

SIS412DN-T1-GE3_POW ERPAK8-5

123

5

PQ304

PQ304

4

123

MDV1526URH_PDFN33-8-5

MDV1526URH_PDFN33-8-5

PC306

10U_0805_25V6K

10U_0805_25V6K

PL302

PL302

2.2UH +-20% ETQ P3W2R2WF N 8.5A

2.2UH +-20% ETQ P3W2R2WF N 8.5A

1 2

12

PR315

PR315

4.7_1206_5%

4.7_1206_5%

12

PC312

PC312

680P_0402_50V7K

680P_0402_50V7K

12

PC307

PC307

PC315

PC315

B++

12

PC308

PC308

@

@

10U_0805_25V6K

10U_0805_25V6K

1

+

+

2

220U_6.3V_M

220U_6.3V_M

12

12

PC309

PC309

@

@

@

@

0.1U_0402_25V6

0.1U_0402_25V6

2200P_0402_50V7K

2200P_0402_50V7K

12

12

PC330

PC330

PC331

PC331

@

@

@

@

0.1U_0402_25V6

0.1U_0402_25V6
2200P_0402_50 V7K

2200P_0402_50 V7K

for RF request, 8/6

12

PC323

PC323

PC325

PC325

68P_0402_50V8J

68P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

+5VDSP

12

12

PC332

PC332

PC333

PC333

@

@

6.8P_0402_50V8C

6.8P_0402_50V8C

100P_0402_50V8J

100P_0402_50V8J

PJP302

PJP302
JUMP_43X118

JUMP_43X118

112

PJP303

PJP303
JUMP_43X118

JUMP_43X118

112

PJP306

PJP306
JUMP_43X39

JUMP_43X39

+5VLP +5VL

A A

5

112

+5VDS+5VDSP

2

+3VDS+3VDSP

2

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

+3VLP

Compal Secret Data

Compal Secret Data

2011/06/13

2011/06/13

2011/06/13

3

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/12/31

2014/12/31

2014/12/31

Title

Title

Title

Size D ocument Number Rev

Size D ocument Number Rev

Size D ocument Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

3VDSP/5VDSP

Thursday, December 20, 2012

Thursday, December 20, 2012

Thursday, December 20, 2012

15W

1

44 52

44 52

44 52

0.3

0.3

0.3

5

PL401

PL401

HCB1608 KF-121T30_060 3

HCB1608 KF-121T30_060 3

B+

D D

1 2

12

12

PC401

PC401

PC419

PC419

@

@

@

@

82P 50V J NPO 0402

82P 50V J NPO 0402

B+_1.35V

12

12

PC403

PC403

@

@

0.1U_0402_25V6

0.1U_0402_25V6

68P_0402_50V8J

68P_0402_50V8J

For RF request, 11/5

12

12

PC404

PC404

@

@

2200P_0402_50V7K

2200P_0402_50V7K

PC406

PC406

PC405

PC405

10U_0805_25V6K

10U_0805_25V6K

for RF request, 8/6

PL402

1

2

330U_2.5V_M+PC409

330U_2.5V_M

PL402

1 2

12

PR404

PR404

4.7_1206 _5%

4.7_1206 _5%

SNB_1.35V

12

PC410

PC410

680P_0603_50V7K

680P_0603_50V7K

2.2UH_VM PI0703AR-2R2M-Z01 _8A_20%

2.2UH_VM PI0703AR-2R2M-Z01 _8A_20%

+1.35VP

+

PC409

C C

4

4.7U_0805_25V6-K

4.7U_0805_25V6-K

5

PQ401

PQ401

4

SIS412DN-T 1-GE3_POWE RPAK8-5

SIS412DN-T 1-GE3_POWE RPAK8-5

123

5

PQ402

PQ402

4

123

MDV1526 URH_PDFN33-8-5

MDV1526 URH_PDFN33-8-5

+5VDS

PR405

PR405

5.1_0603 _5%

5.1_0603 _5%

1 2

12

7/11

PC402

PC402

0.22U_04 02_10V6K

0.22U_04 02_10V6K

1 2

PR403

PR403

15.8K_04 02_1%

15.8K_04 02_1%

1 2

+5VDS

PC411

PC411
1U_0603 _10V6K

1U_0603 _10V6K

+3VS

3

PR418

PR418

2.2_0603 _5%

2.2_0603 _5%

1 2

PR402

PR402
0_0402_ 5%

0_0402_ 5%

1 2

DH_1.35V

+1.35VP

+0.675VSP

LX_1.35V

16

PC412

PC412
1U_0603 _10V6K

1U_0603 _10V6K

PR419

PR419
100K_0402_5%

100K_0402_5%

@

@

1 2

1.35V_PG

PR407

PR407
887K_04 02_1%

887K_04 02_1%

1 2

15

LGATE

14

PGND

13

CS

RT8207M ZQW_W QFN20_3X3

RT8207M ZQW_W QFN20_3X3

12

VDDP

11

VDD

10

DL_1.35V

CS_1.35V

VDD_1.35 V +1.35VP

12

B+_1.35V

BST_1.35V

18

17

PHASE

PGOOD

9

19

20

PU401

PU401

21

VTT

BOOT

UGATE

S5

TON

8

TON_1.35V

PAD

VTTGND

VTTSNS

GND

VTTREF

VDDQ

FB

6

FB_1.35V

1

2

3

4

5

VLDOIN

S3

7

S3_1.35V

2

VTTREF_ 0.675V

+1.35VP

+1.35VP

PR406

PR406

10.2K_04 02_1%

10.2K_04 02_1%

1 2

PR408

PR408

42.2K_04 02_1%

42.2K_04 02_1%

1 2

1

+0.675VSP

12

12

PC407

PC407

PC408

PC408

10U_0805_6.3V6K

10U_0805_6.3V6K

10U_0805_6.3V6K

10U_0805_6.3V6K

12

PC413

PC413

0.033U_0 402_16V7K

0.033U_0 402_16V7K

+1.35VP

12

PC415

PC415
.1U_0402 _16V7K

.1U_0402 _16V7K

PR411

PR411

12

2014/12/31

2014/12/31

2014/12/31

2

PC418

PC418

0.22U_04 02_16V7K

0.22U_04 02_16V7K

12

PR420

PR420

42.2K_04 02_1%

42.2K_04 02_1%

PQ403

PQ403

13

D

D

2N7002K W 1N SOT323 -3

2N7002K W 1N SOT323 -3

2

G

G

S

S

12

Title

Title

Title

Size Doc ument Number Rev

Size Doc ument Number Rev

Size Doc ument Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

12

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

DDR Power

DDR Power

DDR Power

15W

15W

15W

Thursday, December 20 , 2012

Thursday, December 20 , 2012

Thursday, December 20 , 2012

PR415

PR415
10K_040 2_5%

10K_040 2_5%

DDR3_SE T [14]

8/1

1

0.3

0.3

0.3

5245

5245

5245

EN_P1V5[30,33,39,40,44]

10.2K_04 02_1%

PR412

12

B B

A A

5

PR416

PR416

4.7K_040 2_5%

4.7K_040 2_5%

SLP_S4#[14]

12

PR417

PR417

100_0402_5%

100_0402_5%

1

PD401

PD401
BAT54CW _SOT323-3

BAT54CW _SOT323-3

3

2

4

SLP_S3#[14,30,31,34]

KBC_DS3_EN [30,5]

Security Class ification

Security Class ification

Security Class ification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PR412
0_0402_ 5%

0_0402_ 5%

1 2

+1.35VP

+0.675VSP

2012/04/03

2012/04/03

2012/04/03

3

12

PC416

@P C416

@

0.1U_040 2_10V7K

0.1U_040 2_10V7K

PJP401

PJP401
JUMP_43 X118

JUMP_43 X118

1 2

PJP402

PJP402
JUMP_43 X39

JUMP_43 X39

112

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

10.2K_04 02_1%

12

PC417

@P C417

@

0.1U_040 2_10V7K

0.1U_040 2_10V7K

+1.35V

2

+0.675VS

5

D D

+3VS

12

PR511

@

PR511

@

100K_0402_5%

12

PR506

PR506

470K_04 02_1%

470K_04 02_1%

100K_0402_5%

TRIP_1.05V

EN_1.05V

FB_1.05V

RF_1.05V

1.05VM_P G[31]

7/17

PR503

PR503

86.6K_04 02_1%

86.6K_04 02_1%

PR504

PR504
100_040 2_5%

100_040 2_5%

SIO_SLP_A#

C C

1 2

1 2

12

PC508

PC508

@

@

.1U_0402_16V7K

.1U_0402_16V7K

4

PU501

PU501

1

2

3

4

5

VBST

PGOOD

TRIP

DRVH

EN

SW

V5IN

VFB

DRVL

RF

TPS5121 2DSCR_SON10_ 3X3

TPS5121 2DSCR_SON10_ 3X3

TP

10

9

8

7

6

11

BST_1.05 V

DH_1.05V

LX_1.05V

DL_1.05V

PR502

PR502

2.2_0603 _5%

2.2_0603 _5%

1 2

BST_1.05 V-1

+5VDS

12

PC507

PC507
1U_0603 _6.3V6M

1U_0603 _6.3V6M

PC506

PC506

0.22U_06 03_16V7K

0.22U_06 03_16V7K

1 2

4/11

3

B+_1.05V

12

12

PC505

PC505

PC504

PC504

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

5

PQ501

PQ501

4

SIS412DN-T 1-GE3_POWE RPAK8-5

SIS412DN-T 1-GE3_POWE RPAK8-5

123

5

PQ502

PQ502

4

123

4.7U_0805_25V6-K

2.2UH +-20 % ETQP3W2R 2WFN 8.5A

2.2UH +-20 % ETQP3W2R 2WFN 8.5A

12

PR505

PR505

4.7_1206 _5%

4.7_1206 _5%

SNB_1.05V

12

PC511

PC511
680P_06 03_50V7K

680P_06 03_50V7K

AON7406L_DFN8-5

AON7406L_DFN8-5

PL502

PL502

1 2

2

12

12

PC502

PC502

@

@

0.1U_0402_25V6

0.1U_0402_25V6

for RF request, 8/6

1

PL501

PL501

HCB2012 KF-121T50_080 5

HCB2012 KF-121T50_080 5

1 2

12

12

PC512

PC512

PC503

PC503

@

@

2200P_0402_50V7K

2200P_0402_50V7K

PC513

PC513

@

@

68P_0402_50V8J

68P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

B+

+1.05VMP

1

+

+

PC510

PC510
330U_2.5 V_M

330U_2.5 V_M

2

PR508

PR508

5.11K_04 02_1%

5.11K_04 02_1%

12

PQ503

2N7002K W 1N SOT323 -3

2N7002K W 1N SOT323 -3

KBC_PWR_ON #

B B

A A

PQ503

13

D

D

2

G

G

S

S

4/11

5

PR510

PR510
10K_040 2_1%

10K_040 2_1%

1 2

PJP501

PJP501

+1.05VMP

Security Class ification

Security Class ification

Security Class ification

2012/04/03

2012/04/03

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/04/03

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

JUMP_43 X79@

JUMP_43 X79@

2014/12/31

2014/12/31

2014/12/31

2

112

+1.05VM

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

1.05VMP

1.05VMP

1.05VMP

Size Doc ument Number Rev

Size Doc ument Number Rev

Size Doc ument Number Rev

15W

15W

15W

Date: Sheet of

Thursday, December 20 , 2012

Date: Sheet of

Thursday, December 20 , 2012

Date: Sheet of

Thursday, December 20 , 2012

1

0.3

0.3

0.3

5246

5246

5246

A

B

C

D

CPU_VREF

12

12

PR201

@ PR201

@

10K_0402_1%

10K_0402_1%

1 1

PH201

PH201

100K_0402_1%_TSM0B104F4251RZ

100K_0402_1%_TSM0B104F4251RZ

12

12

PR203

GFB

VFB

PC245

PC245

1 2

PR203

10K_0402_1%

10K_0402_1%

SLEWA

PU201

PU201

17

CSP1

18

CSN1

19

CSN2

20

CSP2

21

CSP3

22

CSN3

23

GFB

24

VFB

PR219

PR219

2.94K_0402_1%

2.94K_0402_1%

1 2

CPU_VREF

0.33U_0402_10V6K

0.33U_0402_10V6K

PR226

PR226

10_0603_1%

10_0603_1%

1 2

1U_0603_10V6K

1U_0603_10V6K

PR202

PR202

39K_0402_1%

39K_0402_1%

PR212

PR212

10K_0402_1%

10K_0402_1%

CPU_B+

37W pop, 47W up unpop

+3VS

2 2

VSSSENSE[10,9]

VCCSENSE[9]

3 3

PR242

@PR242

@

0_0402_5%

0_0402_5%

1 2

CSP3

CSN3

PR221

PR221

0_0402_5%

0_0402_5%

1 2

1 2

PR224

PR224

0_0402_5%

0_0402_5%

10K_0402_1%

10K_0402_1%

1 2

12

CSP1

CSN1

CSN2

CSP2

PC246

2.2P_0402_50V8C

2.2P_0402_50V8C

1 2

PR220

PR220

10K_0402_1%

10K_0402_1%

1 2

PR215

PR215

330P_0402_50V7K

330P_0402_50V7K

@PC246

@

+5VDS

12

PC201

PC201

12

PC202

PC202

.1U_0402_16V7K

.1U_0402_16V7K

15

16

13

14

IMON

VBAT

SLEWA

THERM

TPS51631RSMR_QFN32_4X4

TPS51631RSMR_QFN32_4X4

COMP

V5A

DROOP

VREF

26

28

25

27

12

PC203

PC203

12

PC254

PC254

12

PR204

PR204

PR206

88.7K_0402_1%

88.7K_0402_1%

@ PR206

4700P_0402_16V7K

4700P_0402_16V7K

@

12

PR207

PR207

PR205

PR205

39K_0402_1%

39K_0402_1%

F-IMAX

B-RAM

OCP-I

O-USR

10

9

11

12

OCP-I

O-USR

F-IMAX

B-RAMP

VR_ON

SKIP#

PWM1

PWM2

PWM3

PGOOD

VDD

VDIO

VCLK

ALERT#

GND

VR_HOT#

31

29

30

VR_HOT#

SCLK

PAD

32

33

1U_0603_10V6K

1U_0603_10V6K

ALERT#

+VCCIO_OUT

PR232

PR230

PR230

100_0402_5%

100_0402_5%

PC206

@ PC206

@

1 2

PR236

PR236

22_0402_5%

22_0402_5%

1 2

PR237

PR237

22_0402_5%

22_0402_5%

1 2

PR238

PR238

22_0402_5%

22_0402_5%

12

1 2

PR228

PR228

0_0402_5%

0_0402_5%

VR_SVID_DAT[9]

VR_SVID_ALRT#[9]

4 4

VR_SVID_CLK[9]

KBC_PROC_HOT_R[24,5]

47P_0402_50V8J

47P_0402_50V8J

A

PR232

PR231

PR231

100_0402_5%

100_0402_5%

1 2

1 2

VR_HOT#

1 2

100_0402_5%

100_0402_5%

1 2

SDIO

ALERT#

SCLK

12

100K_0402_1%

100K_0402_1%

12

100K_0402_1%

100K_0402_1%

0_0402_5%

0_0402_5%

8

1 2

7

6

5

4

3

2

1

SDIO

PC250

PC250

PC256

PC256
.1U_0402_16V7K

.1U_0402_16V7K

PR208

PR208

PR209

PR209

12

12

PR227

PR227

SKIP

PWM1

PWM2

12

PR210

PR210

255K_0402_1%

255K_0402_1%

36.5K_0402_1%

36.5K_0402_1%

12

12

PR211

PR211

20K_0402_1%

20K_0402_1%

150K_0402_1%

150K_0402_1%

PWR_GD [30,31,5]

PWM3

RF Part (47.3)EMI Part (47.1 )

12

12

PC232

0.1U_0402_25V6

0.1U_0402_25V6

EMI@ PC232

EMI@

PC265

PC238

68P_0402_50V8J

68P_0402_50V8J

2200P_0402_50V7K

2200P_0402_50V7K

EMI@ PC238

EMI@

@RF@ PC265

@RF@

PWM3

12

PC229

PC229

PC268

@RF@ PC268

@RF@

PR218 2.2_0402_5%PR218 2.2_0402_5%

82P 50V J NPO 0402

82P 50V J NPO 0402

1 2

1 2

PC248 .1U_ 0402_16V7KPC248 .1U_0402_16V7K

VGATE [31]

12

1 2

1 2

10_0402_1%

10_0402_1%

47K_0402_1%

47K_0402_1%

12

12

+3VS

12

PC214

PC215

0.1U_0402_25V6

0.1U_0402_25V6
2200P_0402_50V7K

2200P_0402_50V7K

EMI@ PC215

EMI@

EMI@ PC214

EMI@

PWM1

EMI Part (47.1) RF Part (4 7.3)

PR253

PR253

PR252

PR252

RF Part (47.3)EMI Part (47.1 )

12

12

12

PC207

0.1U_0402_25V6

0.1U_0402_25V6

EMI@ PC207

EMI@

B

12

PC266

PC208

2200P_0402_50V7K

2200P_0402_50V7K

EMI@ PC208

EMI@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

PC204

PC204

PC269

68P_0402_50V8J

68P_0402_50V8J

@RF@ PC266

@RF@

@RF@ PC269

@RF@

PR245 2.2_0402_5%PR245 2.2_0402_5%

82P 50V J NPO 0402

82P 50V J NPO 0402

1 2

1 2

PC261 .1U_0402_16V7KP C261 .1U_0402_16V7K

PWM2

phase3
37W pop, 47W up unpop

EMI Part (47.1)

CPU_B+

12

12

PC230

PC230

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

PU204

PU204

CSD97374CQ4M_SON8_3P5X4P5

CSD97374CQ4M_SON8_3P5X4P5

CPU_B+

12

12

PC264

PC211

PC211

PC267

68P_0402_50V8J

68P_0402_50V8J

@RF@ PC267

@RF@

@RF@ PC264

@RF@

PR223 2.2_0402_5%PR223 2.2_0402_5%

82P 50V J NPO 0402

82P 50V J NPO 0402

1 2

1 2

PC253 .1U_ 0402_16V7KPC253 .1U_0402_16V7K

CSD97374CQ4M_SON8_3P5X4P5

CSD97374CQ4M_SON8_3P5X4P5

5

6

7

8

10U_0805_25V6K

10U_0805_25V6K

VIN

BOOT_R

BOOT

PWM

12

PC212

PC212

9

PGND2

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0805_25V6K

10U_0805_25V6K

EMI@ PC26 0

EMI@

VSW

PGND1

VDD

SKIP#

PC210

PC210

5

6

7

8

PU202

PU202

PC260

470P_0402_50V7K

470P_0402_50V7K

1 2

4

3

2

1

12

9

PGND2

VIN

PGND1

BOOT_R

BOOT

PWM

SKIP#

PC216

PC216

1U_0402_6.3V6K

1U_0402_6.3V6K

1 2

0_0402_5%

0_0402_5%

EMI@ PC259

EMI@

VSW

VDD

12

EMI Part (47.1)

CPU_B+

12

12

PC205

PC205

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

CSD97374CQ4M_SON8_3P5X4P5

CSD97374CQ4M_SON8_3P5X4P5

2011/06/24 2014/12/31

2011/06/24 2014/12/31

2011/06/24 2014/12/31

5

6

7

8

PU203

PU203

VIN

BOOT_R

BOOT

PWM

PGND2

9

PC263

EMI@ PC263

EMI@

470P_0402_50V7K

470P_0402_50V7K

1 2

4

VSW

3

PGND1

2

VDD

1

SKIP#

PC262

PC262

1U_0402_6.3V6K

1U_0402_6.3V6K

12

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

C

PR243

PR243

EMI@

EMI@

4.7_1206_5%

4.7_1206_5%

1 2

SKIP

PR217

PR217

EMI Part (47.1)

PC259

EMI@ PR240

1 2

4

3

2

1

EMI@ PR249

EMI@

1 2

PR247

PR247

0_0402_5%

0_0402_5%

EMI@

1 2

PR233

PR233

0_0402_5%

0_0402_5%

PR249

4.7_1206_5%

4.7_1206_5%

1 2

470P_0402_50V7K

470P_0402_50V7K

PR240

4.7_1206_5%

4.7_1206_5%

1 2

SKIP

PR244

PR244

2.1K_0402_1%

2.1K_0402_1%

12

2

1

0.15UH +-20% ETQP4LR15AFM 29A

0.15UH +-20% ETQP4LR15AFM 29A

+5VDS

3

4

PL203

PL203

CPU_B+ B+

1

+

+

2

2.1K_0402_1%

2.1K_0402_1%

0.15UH +-20% ETQP4LR15AFM 29A

0.15UH +-20% ETQP4LR15AFM 29A

SKIP

+5VDS

PR250

PR250

2.1K_0402_1%

2.1K_0402_1%

2

1

0.15UH +-20% ETQP4LR15AFM 29A

0.15UH +-20% ETQP4LR15AFM 29A
PL202

PL202

+5VDS

12

12

PH202

PH202

PR214

PR214

63.4K_0402_1%

63.4K_0402_1%
PR216

PR216

12

12

PC209

PC209

10K_0402_1%_TSM0A103F34D1RZ

10K_0402_1%_TSM0A103F34D1RZ

3.01K_0402_1%

3.01K_0402_1%

CSP3

CSN3

0.15U_0402_10V6K

0.15U_0402_10V6K

+VCC_CORE

EMI Part (47.1)

PJP201

PJP201

1 2

PAD-OPEN 1x3m

PAD-OPEN 1x3m

1 2

PL201

@EMI@ PL201

@EMI@

FBMA-L11-453215-800LMA90T_1812

FBMA-L11-453215-800LMA90T_1812

100U_25V_M

100U_25V_M

12

PR225

PR225

63.4K_0402_1%

63.4K_0402_1%

3

4

PL204

PL204

Acoustic (37.2)

12

12

PH203

PH203

12

PR229

PR229

10K_0402_1%_TSM0A103F34D1RZ

10K_0402_1%_TSM0A103F34D1RZ

3.01K_0402_1%

3.01K_0402_1%

12

PC257@RF@

PC257@RF@

68P_0402_50V8J

68P_0402_50V8J

PR241

PR241

2

1

PC233

PC233

@

@

RF Part (47.3)

12

PR235

PR235

3

4

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

12

12

PH204

PH204

63.4K_0402_1%

63.4K_0402_1%

PR239

PR239

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PWR-CPU_CORE

PWR-CPU_CORE

PWR-CPU_CORE

12

PC217

PC217

12

0.15U_0402_10V6K

0.15U_0402_10V6K

10K_0402_1%_TSM0A103F34D1RZ

10K_0402_1%_TSM0A103F34D1RZ

3.01K_0402_1%

3.01K_0402_1%

D

12

PC213

PC213

12

1

+

+

PC234

PC234

2

CSP1

CSN1

0.15U_0402_10V6K

0.15U_0402_10V6K

+VCC_CORE

PC258@RF@

PC258@RF@

220P_0402_25V8K

220P_0402_25V8K

CSP2

CSN2

+VCC_CORE

47 52

47 52

47 52

1

+

+

PC235

PC235

2

100U_25V_M

100U_25V_M

100U_25V_M

100U_25V_M

0.3

0.3

0.3

5

4

3

2

1

1

+

+

PC2002

PC2002

2

@

@

1

PC2014

PC2014

2

12

PC2025

PC2025

2 X 470u/4m
30 X 22u/0805

12

470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

1

PC2015

PC2015

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

12

12

PC2026

PC2026

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

PC2005

PC2005

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

PC2016

PC2016

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

12

PC2027

PC2027

22U_0805_6.3V6M

22U_0805_6.3V6M

PC2007

PC2007

PC2006

PC2006

2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

12

PC2018

PC2018

PC2017

PC2017

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

12

PC2029

PC2029

PC2028

PC2028

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

PC2009

PC2009

PC2008

PC2008

2

2

12

PC2019

PC2019

12

PC2030

PC2030

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

12

PC2020

PC2020

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

12

PC2031

PC2031

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

12

12

PC2010

PC2010

22U_0805_6.3V6M

22U_0805_6.3V6M

12

PC2021

PC2021

22U_0805_6.3V6M

22U_0805_6.3V6M

12

PC2032

PC2032

22U_0805_6.3V6M

22U_0805_6.3V6M

12

PC2011

PC2011

PC2012

PC2012

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

12

12

PC2022

PC2022

PC2023

PC2023

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

12

12

PC2034

PC2034

PC2033

PC2033

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

+VCC_CORE

+VCC_CO RE

D D

1

+

+

PC2001

PC2001

2

470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

12

PC2013

PC2013

22U_0805_6.3V6M

22U_0805_6.3V6M

C C

12

PC2024

PC2024

22U_0805_6.3V6M

22U_0805_6.3V6M

B B

A A

Security Class ification

Security Class ification

Security Class ification

2012/04/03

2012/04/03

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/04/03

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2014/12/31

2014/12/31

2014/12/31

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PROCESSOR DECOUPLING

PROCESSOR DECOUPLING

PROCESSOR DECOUPLING

Size Doc ument Number Rev

Size Doc ument Number Rev

Size Doc ument Number Rev

LA-9371P

LA-9371P

LA-9371P

Date: Sheet of

Thursday, December 20 , 2012

Date: Sheet of

Thursday, December 20 , 2012

Date: Sheet of

Thursday, December 20 , 2012

1

5248

5248

5248

0.3

0.3

0.3

A

1 1

+3VS

7/17

1

PJP602

PJP602

1

JUMP_43 X39

JUMP_43 X39

@

@

2

2

2 2

12

PC601

PC601

100K_0402_5%

100K_0402_5%

22U_0805_6.3VAM

22U_0805_6.3VAM

12

PR605

@

PR605

@

+3VS

PU601

PU601
SY8032ABC _SOT23-6

SY8032ABC _SOT23-6

4

IN

5

PG

GND

FB6EN

7/17

LX

B

3

LX_1.5V

2

1

EN_1.5V

12

@ PC 603

@

0.1U_040 2_10V7K

0.1U_040 2_10V7K

1.5VS_PG [31]

2N7002K W 1N SOT323 -3

2N7002K W 1N SOT323 -3

SLP_S3[34,9]

PC602

PC602

680P_04 02_50V7K

680P_04 02_50V7K

1 2

SNUB_+1.5V

PR601

PR601

4.7_0402_1%

4.7_0402_1%

1 2

0.47UH +-2 0% PCMC042T-R47 MN 6A

0.47UH +-2 0% PCMC042T-R47 MN 6A

PC603

PQ601

PQ601

2

G

G

4X4

PL602

PL602

1 2

PR602

PR602
10K_040 2_5%

10K_040 2_5%

1 2

13

D

D

S

S

+3VS

12

PR603

PR603

150K_0402_1%

150K_0402_1%

12

PR604

PR604
100K_04 02_1%

100K_04 02_1%

C

+1.5VSP

12

PC604

PC604

22P_0402_50V8J

22P_0402_50V8J

12

12

PC606

PC606

PC605

PC605

22U_0805_6.3VAM

22U_0805_6.3VAM

22U_0805_6.3VAM

22U_0805_6.3VAM

+1.5VSP

+1.5V_PCIEP
TDC=0.46A

2

JUMP_43 X39@

JUMP_43 X39@

PJP601

PJP601

D

112

+1.5VS

Peak Current=0.66A

3 3

4 4

Security Class ification

Security Class ification

Security Class ification

2012/04/03

2012/04/03

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2012/04/03

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

C

2014/12/31

2014/12/31

2014/12/31

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

1.5VSP

1.5VSP

1.5VSP

Size Doc ument Number Rev

Size Doc ument Number Rev

Size Doc ument Number Rev

15W

15W

15W

Date: Sheet of

Thursday, December 20 , 2012

Date: Sheet of

Thursday, December 20 , 2012

Date: Sheet of

Thursday, December 20 , 2012

D

5249

5249

5249

0.3

0.3

0.3

5

D D

4

3

2

1

+3VDS

+3VDS

2

B

B

B

B

2

12

PR1109

PR1109
100K_04 02_5%

100K_04 02_5%

C

C

PQ1103

PQ1103
MMBT390 4WH_SOT32 3-3

MMBT390 4WH_SOT32 3-3

E

E

3 1

E

E

3

PQ1104

PQ1104
MMBT390 6H_SOT23-3

MMBT390 6H_SOT23-3

C

C

1

SRSET [43]

PQ1101

PQ1101
NDS0610 _NL_SOT23-3

PR1108

PR1108
100_040 2_5%

100_040 2_5%

PR1121

PR1121
200K_04 02_1%

200K_04 02_1%

PR1123

PR1123

86.6K_04 02_1%

86.6K_04 02_1%

1 2

2N7002K W 1N SOT323 -3

2N7002K W 1N SOT323 -3

12

PR1126

PR1126
100K_04 02_1%

100K_04 02_1%

PQ504

PQ504

2

G

G

12

PR1125

PR1125
13K_040 2_1%

13K_040 2_1%

13

D

D

S

S

12

PR1124

PR1124
47K_040 2_5%

47K_040 2_5%

12

PR1110

PR1110

8.06K_04 02_1%

8.06K_04 02_1%

12

PR1113

PR1113

8.66K_04 02_1%

8.66K_04 02_1%

12

PR1117

PR1117

45.3K_04 02_1%

45.3K_04 02_1%

PR1120

PR1120
470K_04 02_1%

470K_04 02_1%

1 2

3

+

2

-

12

PC1104

@P C1104

@

0.01U_04 02_16V7K

0.01U_04 02_16V7K

+3VDS

B

B

2

E

E

1

3

C

C

PQ1102

PQ1102
MMBT390 6H_SOT23-3

MMBT390 6H_SOT23-3

+5VL

8

P

1

O

G

PU1102A

PU1102A
LM393DR 2G SO8

LM393DR 2G SO8

4

ADP_SIGNA L

C C

ADP_ID_CHK

B B

P1

12

12

NDS0610 _NL_SOT23-3

D

S

D

S

13

G

G

2

VIN

12

12

+3VDS

12

PR1122

PR1122
47K_040 2_5%

47K_040 2_5%

PR1114

PR1114
220K_04 02_5%

220K_04 02_5%

PR1118

PR1118
130K_04 02_1%

130K_04 02_1%

ADP_PRE S [30]

12

PR1116

PR1116

3.9K_040 2_5%

3.9K_040 2_5%

@

@

1

PC1103

PC1103
3900P_0 402_50V7K

3900P_0 402_50V7K

2

V_3.9K[43 ]

12

PR1115

PR1115
619_040 2_1%

619_040 2_1%

12

PD1102
GLZ4.7B_ LL34-2

GLZ4.7B_ LL34-2

@PD110 2

@

12

PR1119

PR1119

3.24K_04 02_1%

3.24K_04 02_1%

PR1112

PR1112
100K_04 02_5%

100K_04 02_5%

1 2

OCP_A_IN [30]ADP_A_ID [30]

+5VL

A A

Security Class ification

Security Class ification

Security Class ification

2012/04/03

2012/04/03

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/04/03

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2014/12/31

2014/12/31

2014/12/31

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

ADP_OCP

ADP_OCP

ADP_OCP

Size Doc ument Number Rev

Size Doc ument Number Rev

Size Doc ument Number Rev

15W

15W

15W

Date: Sheet of

Thursday, December 20 , 2012

Date: Sheet of

Thursday, December 20 , 2012

Date: Sheet of

Thursday, December 20 , 2012

1

5250

5250

5250

0.3

0.3

0.3

5

MFET_B

D D

PD1202

PD1202

21

MFET_A

SX34H_S MA2

SX34H_S MA2

12

PR1205

PR1205
470K_04 02_5%

470K_04 02_5%

BATT

C C

B B

12

PR1207

PR1207
470K_04 02_5%

470K_04 02_5%

BATT

12

PR1216

PR1216
200K_04 02_1%

200K_04 02_1%

12

PR1218

PR1218
137K_04 02_1%

A A

137K_04 02_1%

5

4

3 6
2
1

PQ1203

PQ1203
AO4409L 1P SO8

AO4409L 1P SO8
PQ1205

PQ1205
AO4409L _SO8

AO4409L _SO8

1
2
3 6

4

PD1203

PD1203

SX34H_S MA2

SX34H_S MA2

+3VDS

4/11

12

PR1214

PR1214

10K_040 2_5%

10K_040 2_5%

12

PR1217

PR1217

64.9K_04 02_1%

64.9K_04 02_1%

13

D

D

2

G

G

PQ1209

PQ1209

S

S

2N7002K W 1N SOT323 -3

2N7002K W 1N SOT323 -3

21

5

5

7

7

8

8

8

8

7

7

5

5

4

PQ1204

PQ1204
AO4409L 1P SO8

AO4409L 1P SO8
PQ1206

PQ1206
AO4409L 1P SO8

AO4409L 1P SO8

4

MFET_B

MFET_A

PR1213

PR1213
1M_0402 _5%

1M_0402 _5%

1 2

+5VL

4/11 4/1 1

8

5

P

+

6

-

G

PU1102B

PU1102B
LM393DR 2G SO8

LM393DR 2G SO8

4

PR1202

PR1202
10K_040 2_5%

10K_040 2_5%

1 2

36
2
1

1
2
36

1 2

10K_040 2_5%

10K_040 2_5%
PR1212

PR1212

12

7

O

4

1

2

3
12

12

12

12

12

12

2

3

1

PC1201

PC1201

0.1U_060 3_25V7M

0.1U_060 3_25V7M

4

PD1201

PD1201
BAV99W T1G_SC70-3

BAV99W T1G_SC70-3

PR1201

PR1201
10K_040 2_5%

10K_040 2_5%

PR1203

PR1203
10K_040 2_5%

10K_040 2_5%

LATCHED _ALARM

PR1206

PR1206
220K_04 02_5%

220K_04 02_5%

BATT_A

BATT_B

PR1208

PR1208
220K_04 02_5%

220K_04 02_5%

PR1209

PR1209
10K_040 2_5%

10K_040 2_5%

PR1210

PR1210
10K_040 2_5%

10K_040 2_5%

LATCHED _ALARM

PD1204

PD1204
BAV99W T1G_SC70-3

BAV99W T1G_SC70-3

+3VDS

3

2

BATT_A

2

12

PR1204

PR1204
470K_04 02_5%

470K_04 02_5%

61

PQ1202A

PQ1202A

ME2N7002DKW-G 2N SOT363-6

ME2N7002DKW-G 2N SOT363-6

SB00000SA00

SB00000SA00

61

2

PQ1201A

PQ1201A

ME2N7002DKW-G 2N SOT363-6

ME2N7002DKW-G 2N SOT363-6

34

5

PQ1201B

PQ1201B

+3VDS

ME2N7002DKW-G 2N SOT363-6

ME2N7002DKW-G 2N SOT363-6

FET_A[30]

BATT_B

5

2012/04/03

2012/04/03

2012/04/03

12

PR1211

PR1211
470K_04 02_5%

470K_04 02_5%

34

SB00000SA00

PQ1202B

PQ1202B

ME2N7002DKW-G 2N SOT363-6

ME2N7002DKW-G 2N SOT363-6

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2014/12/31

2014/12/31

2014/12/31

2

SB00000SA00

34

5

PQ1207B

PQ1207B

12

PR1215

PR1215
100K_04 02_5%

100K_04 02_5%

LATCHED _ALARM

Security Class ification

Security Class ification

Security Class ification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

61

2

PQ1207A

PQ1207A

+3VDS

FET_B[30]

ME2N7002DKW-G 2N SOT363-6

ME2N7002DKW-G 2N SOT363-6

ME2N7002DKW-G 2N SOT363-6

ME2N7002DKW-G 2N SOT363-6

LATCHED_ALARM [30]

3

1

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Battery selector

Battery selector

Battery selector

Size Doc ument Number Rev

Size Doc ument Number Rev

Size Doc ument Number Rev

15W

15W

15W

Date: Sheet of

Thursday, December 20 , 2012

Date: Sheet of

Thursday, December 20 , 2012

Date: Sheet of

Thursday, December 20 , 2012

1

5251

5251

5251

0.3

0.3

0.3

5

Ite m

Ite m Issu e D esc r iptio n

Ite mIte m

P a ge # T itle

P a ge #P ag e#

Title

TitleT itle

4

V ersion C ha ng e L ist ( P . I. R . L ist )

V ersion C ha ng e L ist ( P . I. R . L ist )

V ersion C ha ng e L ist ( P . I. R . L ist )Versio n C hange L ist ( P . I. R . L ist )

R e qu es t

R e qu es t

D at e

D at eD at e

R e qu es tR eq ue st

O w ner

O w ner

O w nerO wn er

Issu e D esc r iptio nD at e

Issu e D esc r iptio nIs su e D es c r iptio n

3

Page 1

Page 1

Page 1P age 1

2

So lu tio n D e sc r ip tion

So lu tio n D e sc r ip tion R ev .

So lu tio n D e sc r ip tionSo lu tio n D e sc r ip tion

1

R e v.P a ge #

R e v.R ev .

D D

1 43

2 Reserve PC324,322,323,325326,327,328,329,330,331,332,33344

7 46

8

10 48 Change PC233,234 from SF000001280 to SF000004M00 2012/08/09 Change the hieght to 6mm

11 47 Change PR234 from 19.1K to 62K 2012/08/10 HP suggestion

12 Change PQ203,204,211 from SB00000K300 to SB00000U3002012/09/11 Design change48

13 Change PQ201,205,209 from SB00000SJ00 to SB00000WX002012/09/13 Design change48

14 44 Change PQ301,302 from SB00000JM00 to SB00000IA00 2012/09/17 Design change

15 44 Change PQ303 from SB00000CT00 to SB00000H700 2012/09/17 Design change

C C

16 44 Change PQ304 from SB00000N800 to SB00000TZ00 2012/09/17 Design change

17 45 Change PQ401 from SB00000H800 to SB00000IA00

18 45 Change PQ402 from SB00000N800 to SB00000TZ00

19 46 Change PQ501 from SB00000H800 to SB00000IA00

20 46 Change PQ502 from SB00000N800 to SB00000H700

21 51 Reserve PR1101,1102,1103,1104,1105,1106,1107,PC1101,1102,PU1101,PD11012012/09/25 HP suggestion

22 45 Change PD401 from SC600000D00 to SCS00006400 2012/10/2 HP suggestion

23 45 Change PR416 from SD034100380 to SD028470180 2012/10/2 HP suggestion

24 43 Change PL101 from SH00000MR00 to SH00000NW00 2012/10/2 Design change

25 23 Change PR240,243,249 from SD001470B80 to SD0000102802012/10/2 Design change

26 23 Reserve PL201 2012/10/2 Design change

27 25 Reserve PL301 2012/10/2 Design change

Reserve PC130,129,131,139,133,132,134,140,136,135,137,141,143,142,144,145,146,147,148,149,151,150,152,153,138

443

Add PC305,304,308,309

454

Reserve PC419,401

455

Add PC403,404,405

466

Reserve PC512,513

Add PC502,503

48 Reserve PC264,267,266,269,265,268 2012/08/06 RF solution

Add PC214,215,207,203,232,236 2012/08/06 RF solution

489

2012/08/06

2012/08/06

2012/08/06 RF solution

2012/08/06 RF solution

2012/08/06

2012/08/06

2012/09/17

2012/09/17

2012/09/17

2012/09/17

RF solution

RF solution2012/08/06

RF solution

RF solution

Design change

Design change

Design change

Design change

RF solution

B B

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2011/10/03 2014/12/31

2011/10/03 2014/12/31

2011/10/03 2014/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PWR - PIR

PWR - PIR

PWR - PIR

LA-9241P

LA-9241P

LA-9241P

52 52Thursday, December 20, 2012

52 52Thursday, December 20, 2012

52 52Thursday, December 20, 2012

1

0.3

0.3

0.3

5

VBL20 from DB0 to DB1 LA-9241P REV:0.1 -> 0.2 Modify <2012.07.04.~2012.08.07. >

Item ImpactDate PageRev. Modify DescriptionChange Cause

0.2 1 7/6 CKT 13 -Follow HP GPIO table

0.2 2 7/6 CKT 14,37 -Follow HP GPIO table -Change UH1.G17 and U30.26 to PWRSV_SEL#.

0.2 3

0.2 4

0.2 5

0.2 6

0.2 7

D D

0.2 8

0.2 9

0.2 10

110.2

0.2 12

0.2 13

0.2 14

0.2 15

0.2 16

0.2 17

0.2 18

0.2 19

0.2 20

0.2 21

0.2 22 7/9 CKT, LAYOUT 13 -HP request -Delete PCH XDP circuit

0.2 7/9 CKT, LAYOUT

0.2 7/9 CKT, LAYOUT

0.2 7/9 CKT, LAYOUT

25 -HP request30 -Delete 16pin SPI ROM socket

C C

27 35 -HP request -Swap MXM port A and port C for layout smoothly

0.2

31

0.2

32

0.2

33

0.2

0.2 CKT, LAYOUT7/1134 36 -Follow vendor request -Add CC75,CC76,CC77,CC78,CC79,CC80,CC81,CC82. Modify U26 circuit

36

0.2 7/12 CKT, LAYOUT

37

0.2 7/12 CKT, LAYOUT

38

0.2 7/12 CKT, LAYOUT

39

0.2 7/12 CKT, LAYOUT41 38 -Follow latest KB connector pin 1 location. -Modify JKB1 pin define.

42

43

B B

44

45

46 7/16 CKT, LAYOUT 14 -ESD request -Reserve CH107

0.2

47 -ESD requestCKT, LAYOUT 257/16 -Reserve C375

0.2

48 CKT, LAYOUT -ESD request7/16 27 -Change DA2 and DA3 P/N.

0.2

49 -ESD request27CKT, LAYOUT7/16 -Delete DA1

0.2

50 7/16 CKT, LAYOUT 28 -ESD request -Change D11 P/N

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

A A

CKT7/6 -Follow HP GPIO table15 -Change UH1.U4 to WLAN_TRAMSIT_OFF#

7/6 CKT, LAYOUT 18,23 -Follow HP GPIO table -Change UH1.C16 to ODD_EN. Change Q25.1 netname to ODD_EN and Q25.2 netname to ODD_EN#

CKT, LAYOUT7/6 19 -Add PU resistor to avoid issue. -Add RH240 and RH241PU resistor of THERM_SCI# and WWAN_TRANSMIT_OFF#

7/6 CKT, LAYOUT 22 -eDP MUX -Modify eDP connector signal source from eDP MUX.

7/6 CKT 23 -Power driving -Change R1316 from 100K to 10K ohms

7/6

CKT, LAYOUT 25 -Change WWAN connector to NFCC -Modify JMINI3 connector type and pin define

7/6

CKT, LAYOUT 26 -Move Mute circuit to S/B -Move QA2 and R95 to S/B

7/6 26CKT, LAYOUT -Audio Combo Jack -Delete MIC_SENSE# circuit.

7/6 CKT, LAYOUT 27 -Follow reference design -Change C91 and C94 to 2.2uF as spec

7/6 CKT, LAYOUT 28 -No ACCELEROMETER LED -Delete LED1

CKT, LAYOUT7/6 29 -NIC yellow ban issue -Add C350 and C373 to +1.05VM_LAN

7/6 CKT, LAYOUT 30 -Follow HP KBC pin define. -Modify U17 pin define.

7/6 CKT, LAYOUT 34 -Avoid leakage issue -Swap Q40 drain and source

7/6 CKT, LAYOUT 36 -To support DP1.2a -Change U26 to PS8338 to support DP1.2a spec.

CKT, LAYOUT7/90.2

CKT, LAYOUT7/90.2

CKT, LAYOUT7/90.2 29 39 -Follow spec pin define -Modify JNFC1 pin define

7/1030

CKT, LAYOUT

7/10 CKT, LAYOUT

7/10 CKT, LAYOUT

7/10 CKT, LAYOUT

7/11 CKT, LAYOUT0.2 35 29 -HP request -Delete R135, R139, R151, R152, R140, R142 for layout.

CKT, LAYOUT7/120.2

7/12 CKT, LAYOUT0.2 40 37 -Follow latest Smart card module pin define. -Modify J3 pin define.

7/13 CKT, LAYOUT0.2

7/13

CKT, LAYOUT0.2

7/13

CKT, LAYOUT0.2

7/13

CKT, LAYOUT0.2

7/16 CKT, LAYOUT 38 -ESD request54 -Change D32 P/N.

CKT7/17 -Change JP3 to JDIMM111 -Correct connector name55

CKT, LAYOUT7/17 -Modify U26 and U42 to PI3VDP12412ZHEX and releate circuit.-Change DP and eDP MUX to passive solution3656

16CKT, LAYOUT7/6 -For NFC function -Change UH1.H6 to NFC_RST#, and add QH10, RH238, RH239 for NFC SMBUS level shift

-Follow HP GPIO table7/6 18CKT, LAYOUT -Change UH1.U12 and RH185.1 to NFC_INT

35CKT, LAYOUT7/6 -MXM no display out issue -Swap JMXM1 PEG TX and RX bus

36CKT, LAYOUT7/6 -Avoid eDP signal quality fail issue -Change U42 to PS8321 which had include repeater function

39CKT, LAYOUT7/6 -Add NFC function -Add JNFC1 circuit.

-HP request1323 -Add QH11

-HP request16 -Delete U39, U40, RH23224

-HP request30CKT, LAYOUT7/90.2

3828 -Follow spec pin define -Modify JTP1 and JTP2 pin define

6,11,12 -Following Intel CRB by HP request -Modify JCPU1 pin AM3,F16,F13 netname. Delete RC73,RC76,C13,C75. Add QD3,RD27,RD28

8 -HP request -Delete RC106, RC107

30 -HP request -Modify R537 to 10K ohms

34 -HP request -Modify R363 to 4.7K ohms

22 -HP request -Delete C6

23 -HP request -Delete C54. Add R539.

24 -HP request -Change U3 to TC7SET00

24 -FAN module pin define wrong. -Modify JFAN1 pin define by follow latest spec.

27,39 -Reduce layout spacing -Move R494,R495,LA5,LA9,CA37,CA38,DA4 to sub board

30 -Correct KBC circuit -Change U17.68, C179.1, C188.1 to +RTCVCC.

39 -Follow ME connector list -Modify JVGA1 footprint and pin define.

-Follow ME connector list39 -Modify JTB1 pin define, add WL/BT_LED# signal.

-ESD request29CKT, LAYOUT7/1651 -Change D12 and D13 P/N

-ESD request33CKT, LAYOUT7/16 -Add D4252

-Follow HP latest generation smart card connector pin define.37CKT, LAYOUT7/16 -Modify J3 pin define.53

-Follow HP request30,32CKT, LAYOUT7/1860

5

4

3

2

1

-Change UH1.B17 to HDD_HALTLED

-Add R537,Q7326

-Delete R224, R460, R220, R223, R496, R497, R498, R499, R244, R269, R236, RH220.

-Change RH222.1, RH223.1, RH224.1, CH97.1, CH98.1, UH5.8 to +3VDS

-Reserve R541, R542 for NFC TX/RX

-Modify JTB1 pin define. Add CH108, CH109, CH110, CH111. Connect PCIE port 1 and port 2 to JTB1.-Follow HP requestCKT, LAYOUT7/17 17,3957

-Delete RH186, and add QH12 to invertion PCH_GPIO56 signal for CR_SX_WARN#-Follow HP requestCKT, LAYOUT 147/1858

-Change RH165.2 net name to TB_HOT_PLUG# for TBT function.-Follow HP request17CKT, LAYOUT7/1859

-Change JP6.13 connection to 8051TX_STBYLED# (instead of 8051TX_STBLED#)

-Change Q35.2 connection to 8051TX_STBYLED# (instead of 8051TX_STBLED#)

-Add a 100K pullup resistor between signal PVT_CS# and +3VDS power rail.

-Make these resistors as non-install (from Install): R219,R266,R258,R253,R216,R264

-Make R215 install

-Change R436 to 1K (from 10 ohm)

-Make these resistors as install (from un-install): R242,R254,R500,R277,R269,R262,R218

-Make U18 as install.

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

2010/12/012011/11/5

2010/12/012011/11/5

2010/12/012011/11/5

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

HW_PIR1

HW_PIR1

HW_PIR1

LA-9241P

LA-9241P

Thursday, December 20, 2012

Thursday, December 20, 2012

Thursday, December 20, 2012

LA-9241P

1

0.5

0.5

53

53

53

0.5

56

56

56

5

VBL20 from DB0 to DB1 LA-9241P REV:0.1 -> 0.2 Modify <2012.07.04.~2012.08.07. >

Item ImpactDate PageRev. Modify DescriptionChange Cause

0.2 61 7/18 31 -Follow HP requestCKT, LAYOUT

67 7/19 CKT,LAYOUT 32 -Change R483.1 and R482.1 connection to +3VS. Change R330.1, R329.1, and R328.1 connection to GND0.2 -Follow HP request

D D

68 7/19 CKT,LAYOUT0.2 36 -Follow HP request -Delete CC70, CC71, CC75, CC76, CC77, CC78, CC79, CC80, CC81, CC82

69 -Modify pin define JVGA1 and JCR1 pin define for better return path-Follow HP request39CKT,LAYOUT7/190.2

71 CKT,LAYOUT 14 -Follow HP request -Add ME debug connector JME10.2 7/20

-Follow HP request40CKT,LAYOUT70 7/190.2 - Connect signal ADP_ID_CHK to pin 78 of KBC via a 0 ohm resistor (install this resistor).

16CKT, LAYOUT72 -Correct screw hole size.-Follow latest ME drawing.7/200.2

19,20CKT,LAYOUT -Delete CH60, CH62, CH63, CH102-Follow HP request.7/20730.2

CKT,LAYOUT 29,34 -Change C110 to 22uF, Delete C231. Change Q170A lcation to Q7A-Follow HP request.0.2 76 7/20

CKT,LAYOUT 30 -Add D44 and D450.2 78 7/20 -Follow HP request.

CKT,LAYOUT -Follow HP request. -Move QH12 to sub board. Add CR_SX_WARN# PU 10K ohms RH244

C C

0.2 86 7/23 CKT,LAYOUT 17 -Correct net name -Change RH171.1 connection to ODD_EN

0.2 89 7/23 26CKT,LAYOUT -MIC_SENSE circuit had been removed. -Delete RA7.

7/23870.2 -Non install RH184 and RH185. Add C389, C390, C391, C392. Change C121 to 1000pF. Change C322 to 100pF. Delete Q37, R366, R361.-Follow VBK1018,29,30,34

88 7/230.2 22,30 -Follow RF request. -Reserve C393, C394, CH112CKT,LAYOUT

CKT,LAYOUT

7/23900.2 -Combine QA2B with QA1A.-Reduce layout spacing27CKT,LAYOUT

7/23910.2 CKT,LAYOUT

7/2392 -Combine Q63 and Q72 to Dual channel Q76. Delete R516, R545, CC84, C371.36CKT,LAYOUT0.2 -Follow HP request.

31CKT, LAYOUT -Modify PWR_GD circuit.-Follow HP request.7/20790.2

147/23830.2

15,17,187/23840.2 CKT,LAYOUT

-No connection to other page. -Delete FN14, FN15, USB_OC0#_R, USB_OC1#_R, USB_OC2#, USB_OC3#, USB_OC4#_R, PCH_GPIO24, FN_CLK2, PCH_GPIO37 off page symbol.

16CKT, LAYOUT7/23850.2 -Modify screw hole size.-Follow latest ME drawing.

-Follow EMI request30,38CKT,LAYOUT7/24970.2

-Follow HP request39CKT,LAYOUT7/24980.2 -Modify JUB1 pin define.

-Follow HP request5,9,20CKT,LAYOUT7/25990.2 -Delete RC24, RC96. Change UH1 pin AJ12 and AJ14 connection to +1.05VS

-Follow HP request30 -Change U18 to socket and add &UH2 for KBC ROMCKT,LAYOUT7/251000.2

-Follow HP request101 7/25 CKT,LAYOUT 30 -Connect JP6.13, U17.115, and R255.1 to TX_STBY_LED. Add R559, R560, and Q770.2

B B

0.2 116 8/01 23,33,39 -Swap SATA bus port 2 and port 5. JCR1.35 connection to PCH_PCIE_WAKE#CKT,LAYOUT -HP request

A A

8/011170.2 -HP requestCKT,LAYOUT -Uninstall Q68, R459. Change PCH.AT3 and RH198.2 netname to Sec_HDD_DET. Change PCH.AP1 and RH180.2 to mSATA_DET#. Delete Q48. Add R565.18,23,25

8/011180.2 -Change R492.2 connection to KBC_PWR_ON-PWR request24CKT,LAYOUT

8/01 -Change KBC symbol to SMC1322-Follow RFQ spec301190.2 CKT

8/031200.2 CKT,LAYOUT -HP request

5

6,11,13,18

-Reduce layout spacingCKT,LAYOUT7/25102 -Combine Q56 and Q57 to dual channel Q79360.2

26 -Delete Q21,Q22,R454,R14. Delete JEDP1.35 signal0.2 114 7/31 -No LOGO KBL functionCKT,LAYOUT

14 -Change RH62.2 netname to PWRSV_SEL#7/310.2 115 -Correct netnameCKT,LAYOUT

4

-Modify PM_APWROK circuit

-Modify JTB1 connector pin define. Add HDD_HALTLED and PWR_GD0.2 397/1862 -Follow HP requestCKT, LAYOUT

-Reserve RH242 and RH243. Add off page symbol of PCH_SPI_WP# and PCH_SPI_HOLD#16,307/190.2 -Follow HP requestCKT, LAYOUT63

-Non-install CH101-Follow Intel reference schematic V1.2207/190.2 CKT64

-Delete C79 and C85. Change R457.1 power rail to +3VDS257/19 CKT,LAYOUT650.2 -Follow HP request

-Delete R25430CKT, LAYOUT7/19660.2 -Follow HP request

- Connect NFC_RX to pin 86 of KBC directly, and then move R541 (install) between ADP_ID_CHK and pin 86 of KBC.

- Connect NFC_TX to pin 87 of KBC directly, and then move R542 (install) between pin 87 of KBC and signal PLT_SEL.

-Add RA28 and Q75 for REC_MUTE_CTRL_KB signal. Modify JKB1 pin define.-Follow HP request.19,21,38CKT,LAYOUT7/20740.2

-Change DA2, DA3, D32 P/N-Follow ESD request.27,38CKT7/20750.2

3

2

1

-Modify RP1 pin define.-Layout smooth30CKT,LAYOUT770.2 7/20

-Change C258 and C255 to 1uF. Non install RH225.-Vendor's suggestion37CKT7/20800.2

-Reserve SIO_GPIO44 PD R554, and modify R328, R329, R330 value to 4.7K. Modify R482, R483 value to 10K-Modify for 2 DIMM and 4 DIMM SKU.38CKT7/20810.2

-Connection RH55.2 to power rail +RTCVCC-Schematic wrong.147/23820.2 CKT,LAYOUT

-Change R286 to 10K31 -Follow HP request.

-Change SEL to SEL_eDP_MUX. Change SEL_DP to SEL_DP_MUX367/2393 -Modify netname to more clear.CKT,LAYOUT0.2

-Modify RPH1 and RPH2 pin define-Layout smooth177/230.2 94 CKT,LAYOUT

-Modify JMINI3 pin define.-Follow latest NGFF pin define.257/24 CKT,LAYOUT950.2

-Modify JFP1 pin define.-Follow latest FP spec.28CKT,LAYOUT7/24960.2

-Add C420, C421, C422, C422, C423, C424, C425, C426, C427, C428, C429, C430, C431, C432, C433, C434, C435, C436, C437, C438, C439, C440, C441, C442, C443, C444, C445, C446,
C447, C448, R555 and C419. Change R437.2 netname to PCH_SPI_CLK_EC.

-Modify JMINI3 and JSIM1 pin define.-Follow latest NGFF specCKT,LAYOUT7/25103 250.2

-Install RH242, RH244. Add R561, R562. Noninstall R541, R5420.2 16,30104 7/26 CKT,LAYOUT -Follow HP request

-Change U11 to SLB96560.2 28CKT,LAYOUT7/26105 -Follow RFQ spec

-Add R563, R56436CKT, LAYOUT7/270.2 -Follow HP request106

-Non install QC15 -F ollow Intel reference schematicCKT,LAYOUT7/301070.2

-PCH_SPI_CLK reserve CH113 to GND-Follow RF request16CKT,LAYOUT7/301080.2

-Change R10.1 to +5VDS and Q20.3 to +3VDS for layout easy. Modify JVGA1 and JCR1 pin define.22,39CKT,LAYOUT7/301090.2 -Follow HP request

-Modify JHDD1, JODD1 and JCR1 footprint.23CKT, LAYOUT7/30110 -Follow latest connector list0.2

-Modify JNFC1 pin define.39 -Correct JNFC1 pin defineCKT,LAYOUT7/301110.2

-Modify Q4A circuit. Change JTB1.95 connection to +3VDS.25,39CKT,LAYOUT7/311120.2 -Follow HP request

-Install Q29 and Q3125CKT7/311130.2 -Wireless LED fail issue.

-Add CC84, CC85, CC86. Change RD6 to 33ohms. RH33.1 connection to GND. Delete RH201, RH202. Q4.2 connection to BT_ON

-Swap L3 pin define for layout smooth8/03121 -Layout smoothCKT,LAYOUT0.2 22

-Modify JODD1, JMINI3 footprint8/03122 -Follow ME connector list23LAYOUT0.2

-Q4.2 connection to BT_ON. Change R437 to 33 ohms. Change R540 to 4.7K. Change JVGA1 pin 39 and 40 connection to +3VDS8/03 25,30,39CKT,LAYOUT -HP request1230.2

-Add CH1148/03 -RF request30CKT,LAYOUT1240.2

-Reserve CC87. Change JCPU1 pin AM43 and pin AL44 ball name-HP request9,15CKT,LAYOUT8/061250.2

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

2010/12/012011/11/5

2010/12/012011/11/5

2010/12/012011/11/5

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

HW_PIR2

HW_PIR2

HW_PIR2

LA-9241P

LA-9241P

Thursday, December 20, 2012

Thursday, December 20, 2012

Thursday, December 20, 2012

LA-9241P

1

0.5

0.5

54

54

54

0.5

56

56

56

5

VBL20 from DB0 to DB1 LA-9241P REV:0.1 -> 0.2 Modify <2012.07.04.~2012.08.14. >

Item ImpactDate PageRev. Modify DescriptionChange Cause

0.2 126 8/07 7,16,25,29 -Follow HP requestCKT, LAYOUT

CKT, LAYOUT8/07128

D D

1320.2 5,14,30 -Add RC106 and change UC1.1 connection to VR_ON. Change UH7.5 and UH3.5 connection to +3V_PCH power rail. Change RH235 to 0ohms. Add RH245 and connection to

8/10 CKT, LAYOUT -Follow HP request

0.2 133 39 -Change JCR1.21 connection to +3VDS8/10 CKT -Add +3VDS power rail for USB repeater

0.2 -Material EOL8/14 -Change Q59, Q70, Q55, Q58, Q68, Q75, Q39, Q61, Q51, Q52, Q53 to SB000009Q80 (S TR 2N7002KW 1N SOT323-3 )CKT136

8/10 -Modify JTP1 pin define.381340.2 -Follow TP module pin defineCKT

CKT -Change D4, D8, D10, D21, D27 to SCS00000Z00 (S SCH DIO RB751V-40 SOD-323)8/14 -Material EOL0.2 137 24,25,30,32

30,38,39

4

-Change RC78 to 10Kohms. Install RH148 and change to 2.2Kohms. Add R567, R568 and R569.

-Change TX_STBY_LED net name to TX_STBY_LED#0.2 30127 8/07 -Correct netnameCKT, LAYOUT

-Modify JDIMM1, JDIMM2, JBATT1, JKB1, JCR1, JNFC1, JP6 connector footprint0.2 -Follow latest ME connector list11,12,13,

-Reserve C449, C450, C4510.2 -RF request22,35CKT, LAYOUT8/08129

-Modify JCR1 and JNFC1 pin define.0.2 39130 8/08 CKT, LAYOUT -Follow latest ME connector list

-Modify JMXM1 footprint390.2 131 -Follow latest ME connector list8/09 CKT

3

2

1

VCC1_PWRGD. Change R277.1 and R253.2 connection to VR_ON

-Reserve C452, C453, C454, C455, C456, C457, C458 8/10 -RF request0.2 135 34CKT, LAYOUT

VBL20 from DB1 to DB2 LA-9241P REV:0.2 -> 0.3 Modify <2012.09.03.~ 2012.09.28 >

0.3 1 -Change UA1 P/N to 92HD91B2X5NLGXWCX8-Chang UA1 to HP P/N9/03 26CKT

0.3 5 -Add WWAN_FULL_PWR and WWAN_RSVD2 PU R599 and R600 to +3V_WWAN. Delete T126 and T128259/10 CKT, LAYOUT

0.3 7 9/11 CKT, LAYOUT 5,9,10,14,

C C

9/03 -Follow HP request -Install R451, R452. Noninstall R561, R562, R284. Change R282 to 10K ohms. Change R289 to 11.5k ohms20.3 CKT 30,31

9/07 CKT0.3 3 -Delete TX_STBY_LED#, VGA_RED, VGA_GRN, VGA_BLU, VGA_DDCCLK, VGA_DDCDATA, CRT_HSYNC, and CRT_VSYNC off page symbol-No used30,36

60.3 CKT, LAYOUT9/10 30

0.3 9/12 CKT, LAYOUT -ME rotate Smart connector 90 degree. -Modify J3 pin define.3710

0.3 9/14 CKT, LAYOUT -Delete UH7, RH235. Move RH236, CH106 to page 31. Modify POWER OK circuit14,3112 -Follow HP request

0.3 -Modify JEDP1, UH5, JTB1, JUSB1 and JKB1 pin define and footprint.CKT, LAYOUT9/14 -Follow ME and DFX request13 22,30,38,39,40

B B

0.3 -Reserve CFG9 PD resistance RC106. Non-install RH39, RH40, RH41, RH44, RH48, RH47, RH46. Change R436 to 100K and connection R436.2 to GND. Delete R557, Non-install R358, C374CKT, LAYOUT9/21 -Follow HP request23 8,13,30,39

0.3 -Delete Q79, Q80, C475, C477, C478, R588, R587. Change +3VDS_P power rail to +3VS.CKT, LAYOUT27 -No need another DC/DC circuit to provide +3VDS_P to U44.9/24 40

0.3 229/25 -Change +3VS, +5VS and +LCDVDD power rail soultion28 CKT, LAYOUT

9/20 CKT, LAYOUT -Change D3 and DH1 to RB751V-40_SOD323-20.3 22,2622 -Change to common part.

9/21 CKT, LAYOUT -Change L29.2 netname to DAC_RED. L30.2 netname to DAC_GRN. L31.2 netname to DAC_BLU0.3 3624 -Netname issue.

9/23 5,30,31,470.3 -Change netname VR_ON to PWR_GD, change netname PWR_GOOD_3 to VGATECKT, LAYOUT25 -Follow HP request

31 5,22,34,409/260.3 -Change JXDP1.47 connection to PM_PWROK via a 0ohm resistor. Add a C502 (10uF cap) for +3VS decoupling. Change C489 and C492 value to 10uF or 4.7uF. Change C494 and C496 to

32 -Change R375.1 connection netname to SLP_S3#0.3 9/26 34 -Correct NetnameCKT, LAYOUT

33 CKT, LAYOUT -Follow ME request38,399/260.3 -Modify JP9 and JFUN1 pin define.

34 -Modify +1.05VS power circuit.0.3 9/26 34 -Follow HP request.CKT, LAYOUT

A A

ImpactItem Change Cause Modify DescriptionRev. PageDate

-Follow HP request

-Follow HP request

15,17,20,
31,32, 33

CKT, LAYOUT9/1280.3 -Follow HP request30

280.3 -Modify JFP1 pin define.CKT, LAYOUT9/18 -Follow ME drawing17

220.3 -Modify JEDP1 connector circuit. Add one more +3VS power pin for power consumptionCKT, LAYOUT9/20 -Correct circuit short issue21

300.3 -Install R237, R235, R234, R233, R231CKT, LAYOUT29 -Follow HP request9/25

CKT, LAYOUT -Follow HP request

CKT, LAYOUT 349/280.3 -Add C50337 -Follow HP request.

ckT38 -Change RH152, RH153 to 499ohms.0.3 10/09 16 -Follow HP request.

3130 CKT, LAYOUT -Reserve R605 and connect R605.1 to SUSCLK_KBC0.3 9/25 -Reserve for EC CLK issue

-Follow HP request

-ME move LID SW from Power board to Function baord.CKT, LAYOUT9/120.3 9 38, -Modify JPWR1 and JFUNC1 connector pin defein.

-Follow latest ME drawingCKT, LAYOUT9/130.3 11 16 -Delete H4, H32, H34, H41, JP2. Add H42, H43, H44, H45, H46. Modify JEDP1, JSIM1, JFP1, JVGA2, J3, JKB1, JTP1. JFUN1 pin define and footprint.

-Follow ME connector list15 380.3 -Change JPWR1 footprint and pin define.CKT, LAYOUT9/17

-Layout smooth19 340.3 -Delete J2CKT, LAYOUT9/19

-Add VGA circuit and connector. Remove JVGA1 BTB connector. Add JFUN1 connector. Add USB3.0 repeater and connector40.3 9/07 36,39,40 -Follow latest ME drawingCKT, LAYOUT

-Delete R219, R258, R500, R262, R264, R266, R216, R241, R242, R253, R549, R271.
Change U17 pin69 to KBC_XTA2, pin 71 to KBC_XTAL1. Add C487, C488, Y4
Connect EC_MUTE# to KBC.91. MAIN_BAT_DET# to KBC.92. pin 70 of KBC to GND. ADP_ID_CHK signal to KBC.78. A\DP_EN signal to KBC.63

-Delete RC102 and RC103. Connect CPU.AL35 pin to VCCSENSE. Connect CPU.AK35 pin to VSSSENSE. Delete RH165 and connect PCH.M1 to TB_HOT_PLUG# directly. Connect
RPH1.3 to TB_HOT_PLUG# directly. Delete RH226 and connect pin AD12 of PCH to +3V_PCH power rail. Delete RC106 and connect UC1.1 to VR_ON. Noninstall
RC36,RC38,RC40,RC43,RC45,RC47. Delete RC66. Connect CPU.AT26 pin to CPU_PLTRST#. Delete RC30. Connect CPU.AL34 pin to H_CPUPWRGD. Change RC55.1 connection to
H_CPUPWRGD. Delete RC27. Connect CPU.AM35 pin to PCH_THERMTRIP#_R. Delete RC93 and connect SLP_S3# to QC5.5. Delete R351. Connect EN_P1V5 to JDOCK1.140. Change
C299 to 0.01uF. Delete R336 and connect C299.1 to ON/OFFBTN_KBC# . Connect ON/OFFBTN_KBC# to JDOCK1.49. Delete R287. Connect joint point of R286.1 and U18.1 to VR_ON.
Add R601 4.7K PU to +3VS on signal SIO_GPIO42. Noninstall R601. Delete RH92, RH93, RH221, RH94, RH95, RH107, RH103, RH203, RH114, RH116, RH205, RH122, RH124, RH126,
RH127, RH128, RH130

-Delete R543, R561, R562. Delete signal ADP_ID_CHK connection to KBC.86 pin. Delete R249 and connect signal OCP_PWM_OUT to KBC.59 pin. Delete R251 and connect signal
PM_PWROK to KBC.60 pin. Delete R256 and connect signal EN_P1V5 to KBC.38 pin. Delete R277 and connect signal VR_ON to KBC.72. Change RP1 and RP2 to 100K.

-Swap L35, L36, L37 for layout smoothly.0.3 4014 -Layout request9/17 CKT, LAYOUT

-Modify JKB1 pin define.0.3 3816 -Follow Keyboard spec9/17 CKT, LAYOUT

-Add a 0ohm resistor between JCR1.5 and signal PCH_PCIE_WAKE#. Then make this resistor open. Change QH11 to P MOS. Change RH30 to 2.2K ohms0.3 13,3918 -Follow HP request9/19 CKT, LAYOUT

-Change RH74 to 100K. Change RH147.1 power rail to +3VS. Delete RA13, CA20. Change R227 to 3K. Delete R393, CC67, and connector U30.23 to PLT_RST#.0.3 14,26,30,3720 -Follow HP request9/20 CKT, LAYOUT

-Non install D21. Delete RH213, RH216, and change netname0.3 20,309/24 -Follow HP request26 CKT, LAYOUT

-Delete R9, R10, R11, Q12, Q20, C1, C7, C8, U24, C226, C221, C222, U25, C218, C223, C219, C227, R354, R356, R357, Q9. Add U47, C497, C498, C499, U45, R603, C489, C490, C491,
C492, U46, R604, C493, C494, C495, C496, Uninstall R370, R373, Q43, Q44, R490

10uF or 4.7uF. Change C499 value to 4.7uF and make R480 as install. Change C493 and C490 to 0.01uF

-Delete R339, R340, R341, R342. Add R606, R607, R608 PU to +3VS. Change R408 to 200K ohms. Uninstall C295.35 CKT, LAYOUT -Follow HP request.33,35,389/270.3

-Change Y2 to smaller (32x25 mm) package.0.3 9/27 29 -Material shortage issueCKT, LAYOUT36

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

2010/12/012011/11/5

2010/12/012011/11/5

2010/12/012011/11/5

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

HW_PIR3

HW_PIR3

HW_PIR3

LA-9241P

LA-9241P

Thursday, December 20, 2012

Thursday, December 20, 2012

Thursday, December 20, 2012

LA-9241P

1

0.5

0.5

55

55

55

0.5

56

56

56

5

VBL20 from DB1R to SI1 LA-9241P REV:0.3 -> 0.4 Modify <2012.10.11.~ 2012.11.09>

Item ImpactDate PageRev. Modify DescriptionChange Cause

0.4 1 10/11 26,27 -Follow IDT requestCKT, LAYOUT

10/11 350.4 -Re-arrange MXM DP port. Port A for Thunder Bolt. Port B for Dock. Port C for EDP. Port D for SWITCH-Follow HP request3 CKT, LAYOUT

CKT, LAYOUT10/1650.4

D D

10/1870.4 -Change R615 to 470K, R610 to 470 ohm, R614 to 10K ohms, R612, R137, R606, R607 and R608 to 4.7K ohms, RC108 to 10K ohms . Delete Q67A, QC1, RC12, Q80, R461, Q2, RC90.

CKT, LAYOUT

10/2380.4 -Delete R612. Reserve R616 between KBC. 124 pin and signal SIO_SLP_SUS#. Uninstall RH209, Q79, R614, R613, CH116 and UH6. Install RH67, RH208. Change PCH.AL6, JTB1.91

CKT, LAYOUT

0.4 9 10/24 18,25,28 -Follow HP requestCKT, LAYOUT -Add R618, R619, R620, R621. Delete R567, and connect JMINI3.15 to WLAN_WAKE# directly. Change ACCEL_INT# connection to U9.11. Change RH176.2 connection to GND and make

0.4 CKT, LAYOUT -Follow HP request14,18,25

0.4 CKT, LAYOUT -Follow Compal HW request13,14,15

0.4 CKT, LAYOUT -For layout smoothly.13,14,15

0.4 CKT, LAYOUT10/26

C C

10/2510 -Add R247, Q63. Change RH70 to 200k ohms. Add LANWAKE# PU RH248 to +3VDS. Delete R618, R89. Change R455 to 200k. Add PD R622. Change Q61 and Q62 to dual channel 7002

10/25 30 -Solve KBC external crystal can not work issue.CKT, LAYOUT0.4 -Reserve R624 and connection to SUSCLK_KBC11

10/2612 -Delete RH56, RH57, RH59, RH60, RH66, RH69, RH71, RH98, RH99, RH100, RH141, RH234, RH139, RH108, RH110, RH111, RH112, R160, R161, R162, R163, R320, R477, R478, R464,

10/2613 -Rearrange RP11, RP8, RP17, RP13, RP14, RP15, RP16, RP12, RP10, RP7 pin assignment for layout smoothly.

15 -Delete R153, R481, R565. Swap QH11A.2 and QH11B.5 connection. Change RH75.2 and PCH.K7 connect to BATLOW#. Change PCH.U7 connect to BT_OFF. Change PCH.P3 and RPH2.4

170.4 -Follow ME request.18,3610/31 -Change JODD1, JVGA2, JKB1 footprintCKT, LAYOUT

11/01 -Change R304.1 connection to +5VL. Change R304 to 88.7k +-1%. Uninstall R306.CKT, LAYOUT190.4 -Follow HP request.31

11/05230.4 27 -Delete R174, QA1B. HP_SENSE# connection to R167.1CKT, LAYOUT -Audio Jack change to normal open type

26 11/06 -Follow HP requestCKT, LAYOUT 9,14,22, 25 -Change QC5A.2 and QC5B.5 connection to SLP_S3. Change PCH.D2 pin connection to DDR3_SET. Delete Q68, R459. Change R458 to 0ohm. Change JMINI3.13 connection to signal

0.4

27 11/06 12CKT, LAYOUT -Add C506, C507, C508, C509, C510, C511-Follow RF request0.4

28 11/07 CKT, LAYOUT 50.4 -Follow ESD request -Delete RC36, RC38, RC40, RC43, RC45, RC47 by ESD request. Add T144, T145, T146, T147, T148, T149

29 -Follow RF request23,32CKT, LAYOUT11/070.4 -Change C48 and C58 to 68pF. Change R332 to 33 ohms, C205 to 82pF and install R332 and C205

5,14,30,3410/124 -Follow HP request -Reserve RC108, UH6, CH116, R610. Change U17.85 and R276.1 connection netname to RSMRST#_EC. Change R455 to 47K. Add Q18A, C504, R609. Modify +3V_PCH power circuit0.4 CKT, LAYOUT

30,34,39

14,3060.4 10/17 -Follow HP request -Change R614.1 connection to +3V_PCH. Correct R227 to 10K.CKT, LAYOUT

20,24,25
30,34,35

34,39

-Follow HP request9,14,25,29,

-Follow HP request5,9,14,16

-Follow HP request14,20,30

29,34,35

29,32,36

29,32,36
38 -Move LID switch to PWR board by ME reqesut.CKT, LAYOUT0.4 -Change JPWR1 to 6 pin, and modify the JPWR1 pin define.14 10/26

18,23,29
30,32,34
38,

-Follow HP request.13,14,17

18,35 -Follow HP request.0.4 16 CKT, LAYOUT -Change RH179 to 100ohms. Delete R137, Q82.B. Add D5210/29

-Follow HP request.0.4 18 CKT, LAYOUT -Change R291.1 connection to +5VL. Change R291 to 105K_1%10/31 18,37

22,30,37,3811/01 -Uninstall Y4, C487, C488. Delete C23, C80, C82, C111. Change U30 to AU9560-GBS-GR. Add R626CKT, LAYOUT210.4 -Follow HW request

290.4 22 11/02 CKT, LAYOUT -Reserve C504. Add C505-Follow HP request.

380.4 24 11/05 -Follow ME requestCKT, LAYOUT -Modify JKB1 pin define to follow ME request.

39CKT, LAYOUT -Smart Card Reader AU9560-GBS-GR no need external crystal11/05250.4 -Uninstall Y3, CV33, CV34

16,34,35 -F ollow HP request -Change RH152 and RH153 value to 2.2K. Change C491 and C495 to 4700pF. Change R627 to 4.7K.0.4 31 11/09 CKT

-Follow HP request -Delete D52. Add Q83, R62723,33CKT, LAYOUT11/08300.4

4

-Change RA14 to 0 ohm. Change C91, C94 to 150u. Change R97, R98, R102, R104 to 1%. Non-install R106, R107. Change C95 to 0.47u X5R. Change QA1.4, R110.2, Q6.1, R111.2, Q6.4 to
AGND.

-Non-install D42. Install D32.0.4 3310/112 -Follow ESD request.CKT,

-Install R567, D21. Add R612, R616, Q80, R614, Q79. Delete R602, C504, R609, R456, Q67B, R218, R239, R240, R540, Q74, R247, C322, C186, R230, R64. Change R568.1, R569.1 and
R245.1 connection to KBC_WAKE#. Remove current VCC1_PWRGD connection to JP6.16. Then add a 4.7 K resistor between JP6.16 and new signal VCC1_PWRGD_SUS#. Change R215.2
to GND. Change R227 to 3.3K. Add a R615 PD for U7.102. Change U7.102 connection to PLT_DET. Change R248 to 200k ohms. Change R248.1, U17.77 connection to
VCC1_PWRGD_SUS#. Change R243.1 and U7.125 connection to CHRG_RST. Change R243 to 100K. Change R243.2 connection to GND. change R436.2 connection to +3VDS. Change
JTB1.91, U17.41 and R436.1 connection to iSCT_LED#. Change D21.2 connection to PM_APWROK. Modify +3V_PCH power circuit. Change JCR1.5 connection to +5VDS.

Install RH209, R492, RC108, R613, CH116 and UH6. Uninstall QC3, RH148, RH67, RH208. Change R492.2 connection to PCH_THERMTRIP#_R Connection R614.1 to PM_RSMRST#. Modify
+1.35VS power circuit

3

2

1

and RH244.2 connection to TBT_RR_GPIO#. Add Q80 for iSCT_LED# circuit

RH176 install. Change RH185 as install

R465, R466, R467, R472, R473, R474, R475, R468, R469, R470, R471, R479, R484, R485, R486, R318, R319, R321, R322, R570, R571,
R572. Add RP7, RP8, RP9, RP10, RP11, RP12, RP13, RP14, RP15, RP16, RP17, RP18, RP19.

connect to WWAN_DET#_PCH. Delete A20GATE and VCC1_PWRGD_SUS# off page symbol. Change RH180.2 and UH1.AP1 connect to PCH_GPIO_35. Change RH198.1 and UH1.AT3
connect to PCH_GPIO_36. Change R376 to 10k. Change R376.1 connect to +3VDS. Connect Q34.3 to LED_LINK_LAN_DOCK# with R625, and delete LED_LINK_LAN_DOCK# connection to
Q34.1. Delete R157 and connect Q34.1 and signal LED_LINK_LAN#_R. Connect U22.26 pin to signal mSATA_DET#. Change R455.2 connection to B+. Change Q36 to AO3413.

-Change Y3, YH1, YH2 to small package11/01 13,15,37 -Material shortage issue0.4 20 CKT, LAYOUT

WWAN_DET#_PCH. Change JMINI3.65 connection to GND. Change C498 to 4700pF

VBL20 from SI1 to SI2 LA-9241P REV:0.4 -> 0.5 Modify <2012.12.12.~ >

B B

Item ImpactDate PageRev. Modify DescriptionChange Cause

0.5 1 12/12 9,14,28,3031-Follow HP request

0.5 3 12/13 CKT -Follow HP request9,28 -Install RC88. Change JFP1.11 netname to FPR_OFF_C

A A

CKT, LAYOUT

CKT, LAYOUT

5

-Solve CRT switch issueCKT12/2040.5 -Uninstall R91,R92,R93. Change RP19 to150 ohms35,36

4

-Uninstall QC4, RC92, CC39, RC89, QC5 and RC88. Add J4, Q84, Q85. Delete Q79, R615, UH6, R613, R617, R227 , CH116, R605. Change RH222, RH223, RH224, R615, R248 to 100K.
Remove R611. Connect JP6.16 to VCC1_PWRGD_SUS#. Install R624. Change CH115 to 0.22uF

-Change U34, U35, U36 to small package0.5 3512/122 -Material shortage issue.

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

2010/12/012011/11/5

2010/12/012011/11/5

2010/12/012011/11/5

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

HW_PIR3

HW_PIR3

HW_PIR3

LA-9241P

LA-9241P

Thursday, December 20, 2012

Thursday, December 20, 2012

Thursday, December 20, 2012

LA-9241P

1

56

56

56

0.5

0.5

0.5

56

56

56