Compal LA-9241P Schematics
CyberForum.ru
A
1 1
B
C
D
E
Compal Confidential
2 2
Intel Haswell rPGA Processor with Lynx Point-H
Viper MXM
Date : 2012/12/20
Version 0.5
3 3
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2011/06/29 2011/06/29
2011/06/29 2011/06/29
2011/06/29 2011/06/29
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Cover Page
Cover Page
Cover Page
LA-9241P
LA-9241P
LA-9241P
E
0.5
0.5
1 56Thursday, December 20, 2012
1 56Thursday, December 20, 2012
1 56Thursday, December 20, 2012
0.5
CyberForum.ru
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mpal Confidential
C
M
el Name :
od
A
B
C
D
E
File Name :
1 1
D
R3-SO-DIMM2, 4
LVDS Panel Conn.
eDP to LVDS
RTD 2136
Page 39
Dock Conn DPD
Page 33
2 2
3 3
Mini DP Conn.
Port 8
Card Reader
Controller
Page 39
SD/MMC Slot
Accelerometer
ST HP3DC2
CPU FAN1 conn.
Page 28
Page 24
GLAN
Intel
Clarkville
RJ45 Conn.
ThunderBolt
Cactus Ridge
X4
Expresscard
Page 29
Page 29
SMSC LPC47N217
Page 39
Port 5Port 6
Port 6
Super I/O
eDP Panel Conn.
DP MUX
PS8338
Page 36
Dock Conn
VGA Conn
Port 7
WLAN
(MINI card)
Page 25Page 39
Port 13
Page 32
Page 22
Page 33
TPM1.2
Infineon SLB9656/9635
Touch pad daughter board
4 4
RTC CKT.
Page 13
eDP DeMUX
Page 36
PS8321
DPC
eDPFDP Conn
MXM3.0 Conn
AMD:
nVidia:
DPE
CRT
VGA Switch
2 to 2
CRT
MAX14885EETL
PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)
ODD
Conn.
Page 23 Page 23Page 23
SMBus (PCH)
Page 35
CRT
Page 36Page 36
Port 1
mSATA
Conn.
Page 28
Touch Pad
PEGx16
SATAx4
Port 2
(GEN1 1.5Gb/S
GEN2 3Gb/S
GEN3 6Gb/S)
USB 2.0 Bus
KBC
SMSC KBC1126
PS2
eDP
100MHz
2.7GT/s
CRT
100MHz
Port 0
Page 13,14,15,16,17,18,19,20,21
SATA HDD
Conn.
Page 30
Int.KBD
Intel
Haswell
rPGA Processor
rPGA947
37.5mm*37.5mm
Page 4,5,6,7,8,9,10
Intel
Lynx Point
PCH
695pin BGA
20mm*20mm
LPC BUS
33MHz
SPI(PCH)
Page 38Page 38
DMI x4FDI x2
100MHz
5GT/s
SPI
BIOS SPI ROM x1,
16 MB
EC ROM
2MB
DDR3L 1333MHz 1.35V
USB 3.0 x4
USB 2.0 x 11
HD Audio
Page 30
HDA Codec
IDT 92HD91
Page 30
Page 26
Ch B
Power On/Off CKT.
DC/DC interface CKT.
Page 34
A
B
C
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NTOF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NTOF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NTOF COMPAL ELECTRONICS, INC.
D
B
NK 0, 1, 2, 3
A
DDR3-SO-DIMM1, 3
BANK 0, 1, 2, 3
Ch A
Digital MIC
Combo Jack
SPK conn
Page 22
Page 39
Page 27
Page 12
Page 11
X4
X4
X1
X1
X1
X1
X1
X1
X1
Docking connector:
RJ45
USB30*1
USB20*1
DP*2
Parallel port
Serial port
PS2
Line in/Line out
SATAx2
VGA
Compal Secret Data
Compal Secret Data
D
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2012/03/23 2011/06/29
2012/03/23 2011/06/29
2012/03/23 2011/06/29
USB3.0 x3
Page 33
Dock x1
Smart card Controller
AU9540A51
WWAN SIM Card
FPR Validity VFM471
Webcam
USB2.0
WLAN
Dock
Page 37
Page 25 Page 25
Page 28
Page 22
Page 39
Page 25
Page 33
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Block Diagrams
Block Diagrams
Block Diagrams
LA-9241P
LA-9241P
LA-9241P
E
2 56Thursday, December 20, 2012
2 56Thursday, December 20, 2012
2 56Thursday, December 20, 2012
0.5
0.5
0.5
CyberForum.ru
5
D D
C C
4
3
2
1
B B
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2012/03/23 2011/06/29
2012/03/23 2011/06/29
2012/03/23 2011/06/29
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
SMBus block diagram_DSC
SMBus block diagram_DSC
SMBus block diagram_DSC
LA-9241P
LA-9241P
LA-9241P
3 56Thursday, December 20, 2012
3 56Thursday, December 20, 2012
3 56Thursday, December 20, 2012
1
0.5
0.5
0.5
CyberForum.ru
5
D D
DMI_CRX_PTX_N0[14]
DMI_CRX_PTX_N1[14]
DMI_CRX_PTX_N2[14]
DMI_CRX_PTX_N3[14]
DMI_CRX_PTX_P0[14]
DMI_CRX_PTX_P1[14]
DMI_CRX_PTX_P2[14]
DMI_CRX_PTX_P3[14]
DMI_CTX_PRX_N0[14]
DMI_CTX_PRX_N1[14]
DMI_CTX_PRX_N2[14]
DMI_CTX_PRX_N3[14]
DMI_CTX_PRX_P0[14]
DMI_CTX_PRX_P1[14]
C C
B B
DMI_CTX_PRX_P2[14]
DMI_CTX_PRX_P3[14]
FDI_CSYNC[14]
FDI_INT[14]
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
FDI_CSYNC
FDI_INT
4
Haswell rPGA EDS
Haswell rPGA EDS
JCPU1A
JCPU1A
D21
DMI_RXN_0
C21
DMI_RXN_1
B21
DMI_RXN_2
A21
DMI_RXN_3
D20
DMI_RXP_0
C20
DMI_RXP_1
B20
DMI_RXP_2
A20
DMI_RXP_3
D18
DMI_TXN_0
C17
DMI_TXN_1
B17
DMI_TXN_2
A17
DMI_TXN_3
D17
DMI_TXP_0
C18
DMI_TXP_1
B18
DMI_TXP_2
A18
DMI_TXP_3
H29
FDI_CSYNC
J29
DISP_INT
INTEL_HASWELL_HAS WELL
INTEL_HASWELL_HAS WELL
3
+
VCCIOA_OUT
P
EG_COMP
CAD Note:
Trace width=12 mils ,Spacing=15mil
Max length= 400 mils.
E23
PEG_RCOMP
PEG_RXN_0
PEG_RXN_1
PEG_RXN_2
PEG_RXN_3
PEG_RXN_4
PEG_RXN_5
PEG_RXN_6
PEG
PEG
PEG_RXN_7
DMI FDI
DMI FDI
PEG_RXN_8
PEG_RXN_9
PEG_RXN_10
PEG_RXN_11
PEG_RXN_12
PEG_RXN_13
PEG_RXN_14
PEG_RXN_15
PEG_RXP_0
PEG_RXP_1
PEG_RXP_2
PEG_RXP_3
PEG_RXP_4
PEG_RXP_5
PEG_RXP_6
PEG_RXP_7
PEG_RXP_8
PEG_RXP_9
PEG_RXP_10
PEG_RXP_11
PEG_RXP_12
PEG_RXP_13
PEG_RXP_14
PEG_RXP_15
PEG_TXN_0
PEG_TXN_1
PEG_TXN_2
PEG_TXN_3
PEG_TXN_4
PEG_TXN_5
PEG_TXN_6
PEG_TXN_7
PEG_TXN_8
PEG_TXN_9
PEG_TXN_10
PEG_TXN_11
PEG_TXN_12
PEG_TXN_13
PEG_TXN_14
PEG_TXN_15
PEG_TXP_0
PEG_TXP_1
PEG_TXP_2
PEG_TXP_3
PEG_TXP_4
PEG_TXP_5
PEG_TXP_6
PEG_TXP_7
PEG_TXP_8
PEG_TXP_9
PEG_TXP_10
PEG_TXP_11
PEG_TXP_12
PEG_TXP_13
PEG_TXP_14
PEG_TXP_15
1 OF 9
1 OF 9
PEG_COMP
M29
PEG_CRX_GTX_N0
K28
PEG_CRX_GTX_N1
M31
PEG_CRX_GTX_N2
L30
PEG_CRX_GTX_N3
M33
PEG_CRX_GTX_N4
L32
PEG_CRX_GTX_N5
M35
PEG_CRX_GTX_N6
L34
PEG_CRX_GTX_N7
E29
PEG_CRX_GTX_N8
D28
PEG_CRX_GTX_N9
E31
PEG_CRX_GTX_N10
D30
PEG_CRX_GTX_N11
E35
PEG_CRX_GTX_N12
D34
PEG_CRX_GTX_N13
E33
PEG_CRX_GTX_N14
E32
PEG_CRX_GTX_N15
L29
PEG_CRX_GTX_P0
L28
PEG_CRX_GTX_P1
L31
PEG_CRX_GTX_P2
K30
PEG_CRX_GTX_P3
L33
PEG_CRX_GTX_P4
K32
PEG_CRX_GTX_P5
L35
PEG_CRX_GTX_P6
K34
PEG_CRX_GTX_P7
F29
PEG_CRX_GTX_P8
E28
PEG_CRX_GTX_P9
F31
PEG_CRX_GTX_P10
E30
PEG_CRX_GTX_P11
F35
PEG_CRX_GTX_P12
E34
PEG_CRX_GTX_P13
F33
PEG_CRX_GTX_P14
D32
PEG_CRX_GTX_P15
H35
PEG_CTX_GRX_C_N0
H34
PEG_CTX_GRX_C_N1
J33
PEG_CTX_GRX_C_N2
H32
PEG_CTX_GRX_C_N3
J31
PEG_CTX_GRX_C_N4
G30
PEG_CTX_GRX_C_N5
C33
PEG_CTX_GRX_C_N6
B32
PEG_CTX_GRX_C_N7
B31
PEG_CTX_GRX_C_N8
A30
PEG_CTX_GRX_C_N9
B29
PEG_CTX_GRX_C_N10
A28
PEG_CTX_GRX_C_N11
B27
PEG_CTX_GRX_C_N12
A26
PEG_CTX_GRX_C_N13
B25
PEG_CTX_GRX_C_N14
A24
PEG_CTX_GRX_C_N15
J35
PEG_CTX_GRX_C_P0
G34
PEG_CTX_GRX_C_P1
H33
PEG_CTX_GRX_C_P2
G32
PEG_CTX_GRX_C_P3
H31
PEG_CTX_GRX_C_P4
H30
PEG_CTX_GRX_C_P5
B33
PEG_CTX_GRX_C_P6
A32
PEG_CTX_GRX_C_P7
C31
PEG_CTX_GRX_C_P8
B30
PEG_CTX_GRX_C_P9
C29
PEG_CTX_GRX_C_P10
B28
PEG_CTX_GRX_C_P11
C27
PEG_CTX_GRX_C_P12
B26
PEG_CTX_GRX_C_P13
C25
PEG_CTX_GRX_C_P14
B24
PEG_CTX_GRX_C_P15
12
R
R
C124.9_0402_1%
C124.9_0402_1%
PEG_CRX_GTX_N[0..15] [35]
PEG_CRX_GTX_P[0..15] [35]
2
PEG_CTX_GRX_P[0..15]
PEG_CTX_GRX_N[0..15]
PEG_CTX_GRX_C_P0
PEG_CTX_GRX_C_N0 PEG_CTX_GRX_N0
PEG_CTX_GRX_C_P1
PEG_CTX_GRX_C_N1
PEG_CTX_GRX_C_P2
PEG_CTX_GRX_C_N2
PEG_CTX_GRX_C_P3
PEG_CTX_GRX_C_N3
PEG_CTX_GRX_C_P4
PEG_CTX_GRX_C_N4
PEG_CTX_GRX_C_P5
PEG_CTX_GRX_C_N5
PEG_CTX_GRX_C_P6
PEG_CTX_GRX_C_N6
PEG_CTX_GRX_C_P7
PEG_CTX_GRX_C_N7
PEG_CTX_GRX_C_P8
PEG_CTX_GRX_C_N8
PEG_CTX_GRX_C_P9
PEG_CTX_GRX_C_N9
PEG_CTX_GRX_C_P10
PEG_CTX_GRX_C_N10
PEG_CTX_GRX_C_P11
PEG_CTX_GRX_C_N11
PEG_CTX_GRX_C_P12
PEG_CTX_GRX_C_N12
PEG_CTX_GRX_C_P13
PEG_CTX_GRX_C_N13
PEG_CTX_GRX_C_P14
PEG_CTX_GRX_C_N14
PEG_CTX_GRX_C_P15
PEG_CTX_GRX_C_N15
12
CC1 0.22U_0402_6.3V6KCC1 0.22U_0402_6.3V6K
12
CC2 0.22U_0402_6.3V6KCC2 0.22U_0402_6.3V6K
12
CC3 0.22U_0402_6.3V6KCC3 0.22U_0402_6.3V6K
12
CC4 0.22U_0402_6.3V6KCC4 0.22U_0402_6.3V6K
12
CC5 0.22U_0402_6.3V6KCC5 0.22U_0402_6.3V6K
12
CC6 0.22U_0402_6.3V6KCC6 0.22U_0402_6.3V6K
12
CC7 0.22U_0402_6.3V6KCC7 0.22U_0402_6.3V6K
12
CC8 0.22U_0402_6.3V6KCC8 0.22U_0402_6.3V6K
12
CC9 0.22U_0402_6.3V6KCC9 0.22U_0402_6.3V6K
12
CC10 0.22U_0402_6.3V6KCC10 0.22U_0402_6.3V6K
12
CC11 0.22U_0402_6.3V6KCC11 0.22U_0402_6.3V6K
12
CC12 0.22U_0402_6.3V6KCC12 0.22U_0402_6.3V6K
12
CC13 0.22U_0402_6.3V6KCC13 0.22U_0402_6.3V6K
12
CC14 0.22U_0402_6.3V6KCC14 0.22U_0402_6.3V6K
12
CC15 0.22U_0402_6.3V6KCC15 0.22U_0402_6.3V6K
12
CC16 0.22U_0402_6.3V6KCC16 0.22U_0402_6.3V6K
1 2
CC17 0.22U_0402_6.3V6KCC17 0.22U_0402_6.3V6K
1 2
CC18 0.22U_0402_6.3V6KCC18 0.22U_0402_6.3V6K
1 2
CC19 0.22U_0402_6.3V6KCC19 0.22U_0402_6.3V6K
1 2
CC20 0.22U_0402_6.3V6KCC20 0.22U_0402_6.3V6K
1 2
CC21 0.22U_0402_6.3V6KCC21 0.22U_0402_6.3V6K
1 2
CC22 0.22U_0402_6.3V6KCC22 0.22U_0402_6.3V6K
1 2
CC23 0.22U_0402_6.3V6KCC23 0.22U_0402_6.3V6K
1 2
CC24 0.22U_0402_6.3V6KCC24 0.22U_0402_6.3V6K
1 2
CC25 0.22U_0402_6.3V6KCC25 0.22U_0402_6.3V6K
1 2
CC26 0.22U_0402_6.3V6KCC26 0.22U_0402_6.3V6K
1 2
CC27 0.22U_0402_6.3V6KCC27 0.22U_0402_6.3V6K
1 2
CC28 0.22U_0402_6.3V6KCC28 0.22U_0402_6.3V6K
1 2
CC29 0.22U_0402_6.3V6KCC29 0.22U_0402_6.3V6K
1 2
CC30 0.22U_0402_6.3V6KCC30 0.22U_0402_6.3V6K
1 2
CC31 0.22U_0402_6.3V6KCC31 0.22U_0402_6.3V6K
1 2
CC32 0.22U_0402_6.3V6KCC32 0.22U_0402_6.3V6K
PEG_CTX_GRX_P[0..15] [35]
PEG_CTX_GRX_N[0..15] [35]
PEG_CTX_GRX_P0
PEG_CTX_GRX_P1
PEG_CTX_GRX_N1
PEG_CTX_GRX_P2
PEG_CTX_GRX_N2
PEG_CTX_GRX_P3
PEG_CTX_GRX_N3
PEG_CTX_GRX_P4
PEG_CTX_GRX_N4
PEG_CTX_GRX_P5
PEG_CTX_GRX_N5
PEG_CTX_GRX_P6
PEG_CTX_GRX_N6
PEG_CTX_GRX_P7
PEG_CTX_GRX_N7
PEG_CTX_GRX_P8
PEG_CTX_GRX_N8
PEG_CTX_GRX_P9
PEG_CTX_GRX_N9
PEG_CTX_GRX_P10
PEG_CTX_GRX_N10
PEG_CTX_GRX_P11
PEG_CTX_GRX_N11
PEG_CTX_GRX_P12
PEG_CTX_GRX_N12
PEG_CTX_GRX_P13
PEG_CTX_GRX_N13
PEG_CTX_GRX_P14
PEG_CTX_GRX_N14
PEG_CTX_GRX_P15
PEG_CTX_GRX_N15
1
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2012/03/23 2011/06/29
2012/03/23 2011/06/29
2012/03/23 2011/06/29
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
DMI,PEG
DMI,PEG
DMI,PEG
LA-9241P
LA-9241P
LA-9241P
1
4 56Thursday, December 20, 2012
4 56Thursday, December 20, 2012
4 56Thursday, December 20, 2012
0.5
0.5
0.5
CyberForum.ru
5
SM_DRAMPWROK with DDR Power Gating Topology
+
5VDS
C
C
C35
C35
08/10 Add RC106 and change UC1.1 connection to VR_ON
9/11 Delete RC106
09/23 Change netname to PWR_GD
P
D D
C C
KBC_PROC_HOT#
WR_GD[30,31,47]
M_DRAM_PWRGD[14]
P
+
3VS
R
R
+VCCIO_OUT
RC23 62_0402_5%RC23 62_0402_5%
Q592N7002KW_SOT323-3
Q592N7002KW_SOT323-3
13
D
D
2
G
G
S
S
1 2
C9 100K_0402_1%
C9 100K_0402_1%
KBC_PROC_HOT_R[24,47]
1 2
#4/9 change by HP requirement
PCH_THERMTRIP#_R[18,24,35]
CLK_CPU_SSC_DPLL#[15]
CLK_CPU_SSC_DPLL[15]
KBC_PROC_HOT
H_PM_SYNC[14]
H_CPUPWRGD[18]
CLK_CPU_DPLL#[15]
CLK_CPU_DPLL[15]
CLK_CPU_DMI#[15]
CLK_CPU_DMI[15]
#4/9 change by
HP requirement
09/11 Delete RC27 and connect CPU.AM35 pin to PCH_THERMTRIP#_R
1 2
0.1U_0402_10V6K
0.1U_0402_10V6K
U
U
C1
C1
5
1
P
B
4
O
2
A
G
74AHC1G09GW_TSSOP5
74AHC1G09GW_TSSOP5
3
Part Number = SA00003Y000
Part Number = SA00003Y000
KBC_PROC_HOT_R
T120PAD @T120PAD @
T118PAD @T118PAD @
H_PECI[30]
1 2
RC26 56_0402_5%RC26 56_0402_5%
CPU_PLTRST#[18]
09/11 Connect CPU.AT26 pin to CPU_PLTRST#
4
+
1.35VS
12
R
R
1.8K_0402_1%
1.8K_0402_1%
M_DRAM_PWRGD_CPU
P
12
R
R
C10
C10
3.3K_0402_1%
3.3K_0402_1%
07/30 Non Install QC1
10/18 Delete QC1 and RC12
CPU_DETECT#
H_CATERR#
H_PECI
T1PAD @T1PAD @
KBC_PROC_HOT_R
PCH_THERMTRIP#_R
H_PM_SYNC
H_CPUPWRGD
PM_DRAM_PWRGD_CPU
CPU_PLTRST#
C5
C5
AP32
AN32
AR27
AK31
AM30
AM35
AT28
AL34
AC10
AT26
G28
H28
F27
E27
D26
E26
Haswell rPGA EDS
Haswell rPGA EDS
JCPU1B
JCPU1B
MISC
MISC
SKTOCC
CATERR
PECI
FC_AK31
PROCHOT
THERMTRIP
PM_SYNC
PWRGOO D
SM_DRAMPW ROK
PLTRSTIN
DPLL_REF _CLKN
DPLL_REF _CLKP
SSC_DPLL _REF_CLKN
SSC_DPLL _REF_CLKP
BCLKN
BCLKP
INTEL_HASWELL_HASWELL
INTEL_HASWELL_HASWELL
3
+
VCCIO_OUT
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
CC33
CC33
CC34
CC34
2
2
Place near JXDP1
RC5 need to close to JCPU1
H_CPUPWRGD H_CPUPWRGD_XDP
ON/OFFBTN#[14,30]
CPU_PWR_DEBUG[9]
PM_PWROK[14,30]
DDR_XDP_WAN_SMBDAT[11,12,13,16,28,38]
DDR_XDP_WAN_SMBCLK[11,12,13,16,28,38]
AP3
PRDY
PREQ
TRST
2 OF 9
2 OF 9
TCK
TMS
TDO
DBR
TDI
SM_RCOMP0
AR3
SM_RCOMP1
AP2
SM_RCOMP2
AN3
DDR3_DRAMRST#_CPU
AR29
XDP_PRDY#
AT29
XDP_PREQ#
AM34
XDP_TCLK
AN33
XDP_TMS
AM33
XDP_TRST#
AM31
XDP_TDI
AL33
XDP_TDO
AP33
XDP_DBRESET#
AR30
XDP_OBS0
AN31
XDP_OBS1
AN29
XDP_OBS2_R
AP31
XDP_OBS3_R
AP30
XDP_OBS4_R
AN28
XDP_OBS5_R
AP29
XDP_OBS6_R
AP28
XDP_OBS7_R
For ESD concern, please put near CPU
09/11 Noninstall RC36, RC38, RC40, RC43, RC45, RC47
11/07 Delete RC36, RC38, RC40, RC43, RC45, RC47 by
ESD request. Add T144, T145, T146, T147, T148, T149
SM_RCOMP_ 0
THERMAL
THERMAL
SM_RCOMP_ 1
SM_RCOMP_ 2
DDR3
DDR3
SM_DRAMRS T
PWR
PWR
JTAG
JTAG
BPM_N_0
BPM_N_1
CLOCK
CLOCK
BPM_N_2
BPM_N_3
BPM_N_4
BPM_N_5
BPM_N_6
BPM_N_7
1 2
RC13 1K_0402_1%RC13 1K_0402_1%
1 2
@
T144 PAD@T144 PAD
@
T145 PAD@T145 PAD
@
T146 PAD@T146 PAD
@
T147 PAD@T147 PAD
@
T148 PAD@T148 PAD
@
T149 PAD@T149 PAD
RC107 0_0402_5%RC107 0_0402_5%
09/23 Change netname to VGATE
09/26 Change netname to PM_PWROK. Add RC107
XDP_DBRESET# [14]
FG0[8]
C
FG1[8]
C
C
FG2[8]
C
FG3[8]
C
FG4[8]
CFG5[8]
CFG6[8]
CFG7[8]
XDP_TCLK
DDR3_DRAMRST#_CPU
X
DP_PREQ#
DP_PRDY#
X
X
DP_OBS0
X
DP_OBS1
C
C
C
C
C
C
CFG6
CFG7
FG0
FG1
FG2
FG3
FG4
FG5
VCCIO_OUT
+
2
J
J
XDP1
XDP1
1
G
ND0
3
BSFN_A0
O
5
O
BSFN_A1
7
ND2
G
9
BSDATA_A0
O
11
O
BSDATA_A1
13
G
ND4
15
O
BSDATA_A2
17
BSDATA_A3
O
19
ND6
G
21
O
BSFN_B0
23
O
BSFN_B1
25
ND8
G
27
BSDATA_B0
O
29
OBSDATA_B 1
31
GND10
33
OBSDATA_B 2
35
OBSDATA_B 3
37
GND12
39
PWRGO OD/HOOK0
41
HOOK1
43
VCC_OBS_ AB
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
SAMTE_BSH-030-01-L-D-A CONN@
SAMTE_BSH-030-01-L-D-A CONN@
07/25 Delete RC24
BSS138W-7-F_SOT323-3
BSS138W-7-F_SOT323-3
KBC_DS3_EN[30,45]
VCCIO_OUT
+
2
G
ND1
4
C
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
QC2
QC2
1 2
@
@
QC3
QC3
2N7002_SOT23
2N7002_SOT23
FG17
FG16
C
C
FG8
C
FG9
FG10
C
FG11
C
C
FG19
C
FG18
FG12
C
FG13
C
CFG14
CFG15
XDP_RST#_R
XDP_DBRESET#
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
BSFN_C0
O
O
BSFN_C1
ND3
G
BSDATA_C0
O
O
BSDATA_C1
G
ND5
O
BSDATA_C2
BSDATA_C3
O
ND7
G
O
BSFN_D0
O
BSFN_D1
ND9
G
BSDATA_D0
O
OBSDATA_D 1
GND11
OBSDATA_D 2
OBSDATA_D 3
GND13
ITPCLK/HOO K4
ITPCLK#/HO OK5
VCC_OBS_ CD
RESET#/HOO K6
DBR#/HOOK 7
GND15
TD0
TRST#
TDI
TMS
GND17
1 2
@
@
RC22 0_0402_5%
RC22 0_0402_5%
D
S
D
S
13
4.99K_0402_1%
4.99K_0402_1%
G
G
2
12
RC28
RC28
RC25 3.3K_0402_5%RC25 3.3K_0402_5%
13
D
D
2
G
G
S
S
10/18 Uninstall QC3 10/18 Change RC108 to 10k ohms, and install RC108
C
FG17 [8]
C
FG16 [8]
FG8 [8]
C
FG9 [8]
C
C
FG10 [8]
C
FG11 [8]
FG19 [8]
C
FG18 [8]
C
C
FG12 [8]
CFG13 [8]
CFG14 [8]
CFG15 [8]
RC16 1K_0402_1%RC16 1K_0402_1%
12
RC105 1K_0402_1%RC105 1K_0402_1%
DDR_RST_EN [16]
12
RC108
RC108
10K_0402_1%
10K_0402_1%
10/12 Reserve RC108
CFG3
1
12
PLT_RST#
CPU_DRAM_RST# [11]
PLT_RST# [13,14,25,28,29,30,35,37,39]
PU/PD for JTAG signals
XDP_DBRESET#
09/11 Change RC55.1 connection to H_CPUPWRGD
H_CPUPWRGD
B B
12
RC55
RC55
10K_0402_1%
10K_0402_1%
DDR3 COMPENSATION SIGNALS
09/11 Delete RC66
A A
5
4
CAD Note:
Avoid stub in the PWRGD path
while placing resistors RC25 & RC130
3
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil
1 2
RC59 100_0402_1%RC59 100_0402_1%
1 2
RC61 75_0402_1%RC61 75_0402_1%
1 2
RC65 100_0402_1%RC65 100_0402_1%
Compal Secret Data
Compal Secret Data
2012/03/23 2011/06/29
2012/03/23 2011/06/29
2012/03/23 2011/06/29
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
RC52 1K_0402_1%RC52 1K_0402_1%
XDP_TDO
RC57 51_0402_1%RC57 51_0402_1%
XDP_TCLK
RC60 51_0402_1%RC60 51_0402_1%
XDP_TRST#
RC62 51_0402_1%RC62 51_0402_1%
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PM,XDP,CLK
PM,XDP,CLK
PM,XDP,CLK
12
12
12
12
LA-9241P
LA-9241P
LA-9241P
1
+3VS
+1.05VS
0.5
0.5
5 56Thursday, December 20, 2012
5 56Thursday, December 20, 2012
5 56Thursday, December 20, 2012
0.5
CyberForum.ru
5
D D
JCPU1C
AM14
AM15
CC86
CC86
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
JCPU1C
AR15
SA_DQ_0
AT14
SA_DQ_1
SA_DQ_2
AN14
SA_DQ_3
AT15
SA_DQ_4
AR14
SA_DQ_5
AN15
SA_DQ_6
SA_DQ_7
AM9
SA_DQ_8
AN9
SA_DQ_9
AM8
SA_DQ_10
AN8
SA_DQ_11
AR9
SA_DQ_12
AT9
SA_DQ_13
AR8
SA_DQ_14
AT8
SA_DQ_15
AJ9
SA_DQ_16
AK9
SA_DQ_17
AJ6
SA_DQ_18
AK6
SA_DQ_19
AJ10
SA_DQ_20
AK10
SA_DQ_21
AJ7
SA_DQ_22
AK7
SA_DQ_23
AF4
SA_DQ_24
AF5
SA_DQ_25
AF1
SA_DQ_26
AF2
SA_DQ_27
AG4
SA_DQ_28
AG5
SA_DQ_29
AG1
SA_DQ_30
AG2
SA_DQ_31
J1
SA_DQ_32
J2
SA_DQ_33
J5
SA_DQ_34
H5
SA_DQ_35
H2
SA_DQ_36
H1
SA_DQ_37
J4
SA_DQ_38
H4
SA_DQ_39
F2
SA_DQ_40
F1
SA_DQ_41
D2
SA_DQ_42
D3
SA_DQ_43
D1
SA_DQ_44
F3
SA_DQ_45
C3
SA_DQ_46
B3
SA_DQ_47
B5
SA_DQ_48
E6
SA_DQ_49
A5
SA_DQ_50
D6
SA_DQ_51
D5
SA_DQ_52
E5
SA_DQ_53
B6
SA_DQ_54
A6
SA_DQ_55
E12
SA_DQ_56
D12
SA_DQ_57
B11
SA_DQ_58
A11
SA_DQ_59
E11
SA_DQ_60
D11
SA_DQ_61
B12
SA_DQ_62
A12
SA_DQ_63
AM3
SM_VREF
F16
SA_DIMM_VREFDQ
F13
SB_DIMM_VREFDQ
INTEL_HASWELL_HASWE LL
INTEL_HASWELL_HASWE LL
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDR_A_D[0..63][11]
C C
B B
+SM_VREF_CA
+DIMM01_VREF_DQ
+DIMM23_VREF_DQ
07/10 Change by HP request
1
2
CC84
CC84
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
CC85
CC85
1
2
4
Haswell rPGA EDS
Haswell rPGA EDS
SA_CK_N_0
SA_CK_P_0
SA_CKE_0
SA_CK_N_1
SA_CK_P_1
SA_CKE_1
SA_CK_N_2
SA_CK_P_2
SA_CKE_2
SA_CK_N_3
SA_CK_P_3
SA_CKE_3
SA_CS_N_0
SA_CS_N_1
SA_CS_N_2
SA_CS_N_3
SA_ODT_0
SA_ODT_1
SA_ODT_2
SA_ODT_3
SA_BS_0
SA_BS_1
SA_BS_2
SA_RAS
SA_WE
SA_CAS
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_MA_15
SA_DQS_N_0
SA_DQS_N_1
SA_DQS_N_2
SA_DQS_N_3
SA_DQS_N_4
SA_DQS_N_5
SA_DQS_N_6
SA_DQS_N_7
SA_DQS_P_0
SA_DQS_P_1
SA_DQS_P_2
SA_DQS_P_3
SA_DQS_P_4
SA_DQS_P_5
SA_DQS_P_6
SA_DQS_P_7
RSVD
VSS
3 OF 9
3 OF 9
AC7
U4
M_CLK_A_DDR#0
V4
M_CLK_A_DDR0
AD9
DDR_CKE0_DIMMA
U3
M_CLK_A_DDR#1
V3
M_CLK_A_DDR1
AC9
DDR_CKE1_DIMMA
U2
M_CLK_A_DDR#2
V2
M_CLK_A_DDR2
AD8
DDR_CKE2_DIMMA
U1
M_CLK_A_DDR#3
V1
M_CLK_A_DDR3
AC8
DDR_CKE3_DIMMA
M7
DDR_CS0_DIMMA#
L9
DDR_CS1_DIMMA#
M9
DDR_CS2_DIMMA#
M10
DDR_CS3_DIMMA#
M8
M_A_ODT0
L7
M_A_ODT1
L8
M_A_ODT2
L10
M_A_ODT3
V5
DDR_A_BS0
U5
DDR_A_BS1
AD1
DDR_A_BS2
V10
U6
DDR_A_RAS#
U7
DDR_A_WE#
U8
DDR_A_CAS#
V8
DDR_A_MA0
AC6
DDR_A_MA1
V9
DDR_A_MA2
U9
DDR_A_MA3
AC5
DDR_A_MA4
AC4
DDR_A_MA5
AD6
DDR_A_MA6
AC3
DDR_A_MA7
AD5
DDR_A_MA8
AC2
DDR_A_MA9
V6
DDR_A_MA10
AC1
DDR_A_MA11
AD4
DDR_A_MA12
V7
DDR_A_MA13
AD3
DDR_A_MA14
AD2
DDR_A_MA15
AP15
DDR_A_DQS#0
AP8
DDR_A_DQS#1
AJ8
DDR_A_DQS#2
AF3
DDR_A_DQS#3
J3
DDR_A_DQS#4
E2
DDR_A_DQS#5
C5
DDR_A_DQS#6
C11
DDR_A_DQS#7
AP14
DDR_A_DQS0
AP9
DDR_A_DQS1
AK8
DDR_A_DQS2
AG3
DDR_A_DQS3
H3
DDR_A_DQS4
E3
DDR_A_DQS5
C6
DDR_A_DQS6
C12
DDR_A_DQS7
M_CLK_A_DDR#0 [11]
M_CLK_A_DDR0 [11]
DDR_CKE0_DIMMA [11]
M_CLK_A_DDR#1 [11]
M_CLK_A_DDR1 [11]
DDR_CKE1_DIMMA [11]
M_CLK_A_DDR#2 [11]
M_CLK_A_DDR2 [11]
DDR_CKE2_DIMMA [11]
M_CLK_A_DDR#3 [11]
M_CLK_A_DDR3 [11]
DDR_CKE3_DIMMA [11]
DDR_CS0_DIMMA# [11]
DDR_CS1_DIMMA# [11]
DDR_CS2_DIMMA# [11]
DDR_CS3_DIMMA# [11]
M_A_ODT0 [11]
M_A_ODT1 [11]
M_A_ODT2 [11]
M_A_ODT3 [11]
DDR_A_BS0 [11]
DDR_A_BS1 [11]
DDR_A_BS2 [11]
DDR_A_RAS# [11]
DDR_A_WE# [11]
DDR_A_CAS# [11]
DDR_A_MA[0..15] [11]
DDR_A_DQS#[0..7] [11]
DDR_A_DQS[0..7] [11]
3
JCPU1D
DDR_B_D[0..63][12]
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
JCPU1D
AR18
SB_DQ_0
AT18
SB_DQ_1
AM17
SB_DQ_2
AM18
SB_DQ_3
AR17
SB_DQ_4
AT17
SB_DQ_5
AN17
SB_DQ_6
AN18
SB_DQ_7
AT12
SB_DQ_8
AR12
SB_DQ_9
AN12
SB_DQ_10
AM11
SB_DQ_11
AT11
SB_DQ_12
AR11
SB_DQ_13
AM12
SB_DQ_14
AN11
SB_DQ_15
AR5
SB_DQ_16
AR6
SB_DQ_17
AM5
SB_DQ_18
AM6
SB_DQ_19
AT5
SB_DQ_20
AT6
SB_DQ_21
AN5
SB_DQ_22
AN6
SB_DQ_23
AJ4
SB_DQ_24
AK4
SB_DQ_25
AJ1
SB_DQ_26
AJ2
SB_DQ_27
AM1
SB_DQ_28
AN1
SB_DQ_29
AK2
SB_DQ_30
AK1
SB_DQ_31
L2
SB_DQ_32
M2
SB_DQ_33
L4
SB_DQ_34
M4
SB_DQ_35
L1
SB_DQ_36
M1
SB_DQ_37
L5
SB_DQ_38
M5
SB_DQ_39
G7
SB_DQ_40
J8
SB_DQ_41
G8
SB_DQ_42
G9
SB_DQ_43
J7
SB_DQ_44
J9
SB_DQ_45
G10
SB_DQ_46
J10
SB_DQ_47
A8
SB_DQ_48
B8
SB_DQ_49
A9
SB_DQ_50
B9
SB_DQ_51
D8
SB_DQ_52
E8
SB_DQ_53
D9
SB_DQ_54
E9
SB_DQ_55
E15
SB_DQ_56
D15
SB_DQ_57
A15
SB_DQ_58
B15
SB_DQ_59
E14
SB_DQ_60
D14
SB_DQ_61
A14
SB_DQ_62
B14
SB_DQ_63
INTEL_HASWELL_HASWE LL
INTEL_HASWELL_HASWE LL
2
Haswell rPGA EDS
Haswell rPGA EDS
RSVD
SB_CKN0
SB_CK0
SB_CKE_0
SB_CKN1
SB_CK1
SB_CKE_1
SB_CKN2
SB_CK2
SB_CKE_2
SB_CKN3
SB_CK3
SB_CKE_3
SB_CS_N_0
SB_CS_N_1
SB_CS_N_2
SB_CS_N_3
SB_ODT_0
SB_ODT_1
SB_ODT_2
SB_ODT_3
SB_BS_0
SB_BS_1
SB_BS_2
SB_RAS
SB_WE
SB_CAS
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_MA_15
SB_DQS_N_0
SB_DQS_N_1
SB_DQS_N_2
SB_DQS_N_3
SB_DQS_N_4
SB_DQS_N_5
SB_DQS_N_6
SB_DQS_N_7
SB_DQS_P_0
SB_DQS_P_1
SB_DQS_P_2
SB_DQS_P_3
SB_DQS_P_4
SB_DQS_P_5
SB_DQS_P_6
SB_DQS_P_7
4 OF 9
4 OF 9
VSS
AG8
Y4
M_CLK_B_DDR#0
AA4
M_CLK_B_DDR0
AF10
DDR_CKE0_DIMMB
Y3
M_CLK_B_DDR#1
AA3
M_CLK_B_DDR1
AG10
DDR_CKE1_DIMMB
Y2
M_CLK_B_DDR#2
AA2
M_CLK_B_DDR2
AG9
DDR_CKE2_DIMMB
Y1
M_CLK_B_DDR#3
AA1
M_CLK_B_DDR3
AF9
DDR_CKE3_DIMMB
P4
DDR_CS0_DIMMB#
R2
DDR_CS1_DIMMB#
P3
DDR_CS2_DIMMB#
P1
DDR_CS3_DIMMB#
R4
M_B_ODT0
R3
M_B_ODT1
R1
M_B_ODT2
P2
M_B_ODT3
R7
DDR_B_BS0
P8
DDR_B_BS1
AA9
DDR_B_BS2
R10
R6
DDR_B_RAS#
P6
DDR_B_WE#
P7
DDR_B_CAS#
R8
DDR_B_MA0
Y5
DDR_B_MA1
Y10
DDR_B_MA2
AA5
DDR_B_MA3
Y7
DDR_B_MA4
AA6
DDR_B_MA5
Y6
DDR_B_MA6
AA7
DDR_B_MA7
Y8
DDR_B_MA8
AA10
DDR_B_MA9
R9
DDR_B_MA10
Y9
DDR_B_MA11
AF7
DDR_B_MA12
P9
DDR_B_MA13
AA8
DDR_B_MA14
AG7
DDR_B_MA15
AP18
DDR_B_DQS#0
AP11
DDR_B_DQS#1
AP5
DDR_B_DQS#2
AJ3
DDR_B_DQS#3
L3
DDR_B_DQS#4
H9
DDR_B_DQS#5
C8
DDR_B_DQS#6
C14
DDR_B_DQS#7
AP17
DDR_B_DQS0
AP12
DDR_B_DQS1
AP6
DDR_B_DQS2
AK3
DDR_B_DQS3
M3
DDR_B_DQS4
H8
DDR_B_DQS5
C9
DDR_B_DQS6
C15
DDR_B_DQS7
T3 PAD~D@T3 PA D~D@
M_CLK_B_DDR#0 [12]
M_CLK_B_DDR0 [12]
DDR_CKE0_DIMMB [12]
M_CLK_B_DDR#1 [12]
M_CLK_B_DDR1 [12]
DDR_CKE1_DIMMB [12]
M_CLK_B_DDR#2 [12]
M_CLK_B_DDR2 [12]
DDR_CKE2_DIMMB [12]
M_CLK_B_DDR#3 [12]
M_CLK_B_DDR3 [12]
DDR_CKE3_DIMMB [12]
DDR_CS0_DIMMB# [12]
DDR_CS1_DIMMB# [12]
DDR_CS2_DIMMB# [12]
DDR_CS3_DIMMB# [12]
M_B_ODT0 [12]
M_B_ODT1 [12]
M_B_ODT2 [12]
M_B_ODT3 [12]
DDR_B_BS0 [12]
DDR_B_BS1 [12]
DDR_B_BS2 [12]
DDR_B_RAS# [12]
DDR_B_WE# [12]
DDR_B_CAS# [12]
1
DDR_B_MA[0..15] [12]
DDR_B_DQS#[0..7] [12]
DDR_B_DQS[0..7] [12]
07/10 Delete by HP request
08/03 Add CC84, CC85, CC86
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2012/03/23 2011/06/29
2012/03/23 2011/06/29
2012/03/23 2011/06/29
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
DDRIII
DDRIII
DDRIII
LA-9241P
LA-9241P
LA-9241P
6 56Thursday, December 20, 2012
6 56Thursday, December 20, 2012
6 56Thursday, December 20, 2012
1
0.5
0.5
0.5
CyberForum.ru
5
D D
4
3
2
1
COMPENSATION PU FOR eDP
+VCCIOA_OUT
EDP_COMP
CAD Note:Trace width=20 mils ,Spacing=25mil,
Haswell rPGA EDS
Haswell rPGA EDS
JCPU1H
JCPU1H
T28
DDIB_TXBN_0
U28
DDIB_TXBP_0
T30
C C
DDIB_TXBN_1
U30
DDIB_TXBP_1
U29
DDIB_TXBN_2
V29
DDIB_TXBP_2
U31
DDIB_TXBN_3
V31
DDIB_TXBP_3
T34
DDIC_TXCN_0
U34
DDIC_TXCP_0
U35
DDIC_TXCN_1
V35
DDIC_TXCP_1
U32
DDIC_TXCN_2
T32
DDIC_TXCP_2
U33
DDIC_TXCN_3
V33
DDIC_TXCP_3
P29
DDID_TXDN_0
R29
DDID_TXDP_0
N28
DDID_TXDN_1
P28
DDID_TXDP_1
P31
DDID_TXDN_2
R31
DDID_TXDP_2
N30
DDID_TXDN_3
P30
DDID_TXDP_3
INTEL_HASWELL_HAS WELL
INTEL_HASWELL_HAS WELL
eDP
eDP
EDP_RCOMP
EDP_DISP_UT IL
EDP_AUXN
EDP_AUXP
EDP_HPD
EDP_TXN_0
EDP_TXP_0
EDP_TXN_1
EDP_TXP_1
FDI_TXN_0
FDI_TXP_0
FDI_TXN_1
FDI_TXP_1
DDI
DDI
8 OF 9
8 OF 9
M27
EDP_CPU_C_AUX#
N27
EDP_CPU_C_AUX
P27
EDP_HPD
E24
EDP_COMP
R27
P35
EDP_CPU_C_LANE_N0
R35
EDP_CPU_C_LANE_P0
N34
EDP_CPU_C_LANE_N1
P34
EDP_CPU_C_LANE_P1
P33
R33
N32
P32
T119 PAD@T119 PAD@
1 2
C126 0.1U_0402_25V6C126 0.1U_0402_25V6
1 2
C127 0.1U_0402_25V6C127 0.1U_0402_25V6
1 2
C128 0.1U_0402_25V6C128 0.1U_0402_25V6
1 2
C129 0.1U_0402_25V6C129 0.1U_0402_25V6
1 2
C130 0.1U_0402_25V6C130 0.1U_0402_25V6
1 2
C131 0.1U_0402_25V6C131 0.1U_0402_25V6
Max length=100 mils.
FDI_CTX_PRX_N0
FDI_CTX_PRX_P0
FDI_CTX_PRX_N1
FDI_CTX_PRX_P1
+VCCIO_OUT
HPD INVERSION FOR EDP
B B
CPU_EDP_HPD#[36]
2
G
G
100K_0402_5%
100K_0402_5%
12
RC79
RC79
12
RC7724.9_0402_1% RC7724.9_0402_1%
EDP_CPU_AUX# [36]
EDP_CPU_AUX [36]
EDP_CPU_LANE_N0 [36]
EDP_CPU_LANE_P0 [36]
EDP_CPU_LANE_N1 [36]
EDP_CPU_LANE_P1 [36]
FDI_CTX_PRX_N0 [14]
FDI_CTX_PRX_P0 [14]
FDI_CTX_PRX_N1 [14]
FDI_CTX_PRX_P1 [14]
12
10K_0402_5%
10K_0402_5%
RC78
RC78
08/07 Change RC78 to 10K
EDP_HPD
13
D
D
QH1
QH1
BSS138W-7-F_SOT323-3
BSS138W-7-F_SOT323-3
S
S
SB000002X00
SB000002X00
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2012/03/23 2011/06/29
2012/03/23 2011/06/29
2012/03/23 2011/06/29
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
CPU-FDI,eDP,DDI
CPU-FDI,eDP,DDI
CPU-FDI,eDP,DDI
LA-9241P
LA-9241P
LA-9241P
1
7 56Thursday, December 20, 2012
7 56Thursday, December 20, 2012
7 56Thursday, December 20, 2012
0.5
0.5
0.5
CyberForum.ru
5
4
3
2
1
CFG STRAPS for CPU
C
FG2
1K_0402_1%
1K_0402_1%
12
@RC80
@
RC80
D D
PEG Static Lane Reversal - CFG2 is for the 16x
1:(Default) Normal Operation; Lane #
CFG2
Haswell rPGA EDS
Haswell rPGA EDS
JCPU1I
JCPU1I
AT1
RSVD_TP
AT2
RSVD_TP
AD10
RSVD
A34
RSVD_TP
A35
RSVD_TP
T15 PAD ~D@T15 PAD~D@
T12 PAD ~D@T12 PAD~D@
T16 PAD ~D@T16 PAD~D@
C C
12
B B
RC84 49.9_0402_1%RC84 49.9_0402_1%
RC85 49.9_0402_1%RC85 49.9_0402_1%
RC86 49.9_0402_1%RC86 49.9_0402_1%
H_CPU_TESTLO
12
CFG_RCOMP
12
H_CPU_RSVD
T17 PAD ~D@T17 PAD~D@
T26 PAD ~D@T26 PAD~D@
T28 PAD ~D@T28 PAD~D@
CFG0[5]
CFG1[5]
CFG2[5]
CFG3[5]
CFG4[5]
CFG5[5]
CFG6[5]
CFG7[5]
CFG8[5]
CFG9[5]
CFG10[5]
CFG11[5]
CFG12[5]
CFG13[5]
CFG14[5]
CFG15[5]
+VCC_CORE
H_CPU_RSVD
H_CPU_TESTLO
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
W29
RSVD_TP
W28
RSVD_TP
G26
TESTLO_G26
W33
VSS
AL30
RSVD
AL29
RSVD
F25
VCC
C35
RSVD_TP
B35
RSVD_TP
AL25
RSVD_TP
W30
RSVD_TP
W31
RSVD_TP
W34
TESTLO
AT20
CFG_0
AR20
CFG_1
AP20
CFG_2
AP22
CFG_3
AT22
CFG_4
AN22
CFG_5
AT25
CFG_6
AN23
CFG_7
AR24
CFG_8
AT23
CFG_9
AN20
CFG_10
AP24
CFG_11
AP26
CFG_12
AN25
CFG_13
AN26
CFG_14
AP25
CFG_15
INTEL_HASWELL_HAS WELL
INTEL_HASWELL_HAS WELL
CFG_RCOMP
9 OF 9
9 OF 9
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
CFG_16
CFG_18
CFG_17
CFG_19
RSVD
FC_G6
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD_TP
RSVD_TP
RSVD_TP
VSS
VSS
VSS
VSS
C23
B23
D24
D23
AT31
CFG_RCOMP
AR21
CFG16
AR23
CFG18
AP21
CFG17
AP23
CFG19
AR33
G6
AM27
AM26
F5
AM2
K6
E18
U10
P10
B1
NC
A2
AR1
E21
E20
AP27
AR26
AL31
AL32
07/10 Delete RC106 and RC107
CFG16 [5]
CFG18 [5]
CFG17 [5]
CFG19 [5]
CFG4
CFG[6:5]
CFG9
1K_0402_1%
1K_0402_1%
12
@RC106
@
RC106
definition matches socket pin map definition
0:Lane Reversed
CFG4
1K_0402_1%
1K_0402_1%
12
RC81
RC81
Display Port Presence Strap
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
CFG6
CFG5
1K_0402_1%
1K_0402_1%
1K_0402_1%
1K_0402_1%
12
12
@RC83
@RC82
@
RC82
@
RC83
PCIE Port Bifurcation Straps
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CFG7
1K_0402_1%
1K_0402_1%
12
@RC87
@
RC87
09/21 Reserve CFG9 PD RC106
PEG DEFER TRAINING
1: (Default) PEG Train immediately
CFG7
following xxRESETB de assertion
0: PEG Wait for BIOS for training
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2012/03/23 2011/06/29
2012/03/23 2011/06/29
2012/03/23 2011/06/29
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
CPU-RSVD,CFG
CPU-RSVD,CFG
CPU-RSVD,CFG
LA-9241P
LA-9241P
LA-9241P
1
8 56Thursday, December 20, 2012
8 56Thursday, December 20, 2012
8 56Thursday, December 20, 2012
0.5
0.5
0.5
CyberForum.ru
5
4
3
2
1
+1.35VS Source
D D
SLP_S3[34,49]
11/06 Change QC5A.2 and QC5B.5 connection to SLP_S3
09/11 Delete RC93 and connect SLP_S3# to QC5.5
10/16 Add Q80
C C
+VCC_CORE
100_0402_1%
B B
VCC_SENSE
100_0402_1%
12
RC101
RC101
2
1.35V
+
B
+
12
C88
C88
R
R
100K_0402_5%
100K_0402_5%
R
UN_ON_CPU1.5VS3
61
@
@
2N7002DWH_SOT363-6
2N7002DWH_SOT363-6
QC5A
QC5A
330K_0402_5%
330K_0402_5%
10/18 Delete Q80, R461, Q2, RC90. Modify +1.35VS power circuit
12/12 Uninstall QC4,RC92,CC39,RC89,QC5 and RC88. Add J4.
12/13 Install RC88
CAD Note: RC101 SHOULD BE PLACED CLOSE TO CPU
VCCSENSE[47]
VCCSENSE
CAD Note: RC104 SHOULD BE PLACED CLOSE TO CPU
VSSSENSE[10,47]
A A
VSSSENSE
09/11 Delete RC102 and RC103
100_0402_1%
100_0402_1%
12
RC104
RC104
4
4
J
J
112
JUMP_43X79
JUMP_43X79
SI7326DN-T1-E3_PAK1212-8
SI7326DN-T1-E3_PAK1212-8
Q
C4
@QC4
@
12
@
@
@
@
RC92
RC92
RUN_ON_CPU1.5VS3 [11,12]
2
4
1
CC39
CC39
2
0.1U_0402_25V6
0.1U_0402_25V6
1
2
35
R
R
20K_0402_5%
20K_0402_5%
12
@
@
07/25 Delete RC96
+1.35VS
+
1.35VS
6
6
1
2
1
2
C89
C89
R
R
470_0603_5%@
470_0603_5%@
1 2
34
C5B
C5B
Q
Q
2N7002DWH_SOT363-6
2N7002DWH_SOT363-6
@
@
5
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CC42
CC42
CC43
CC43
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
CH2
CH2
CH1
CH1
1
2
SLP_S3
VDDQ DECOUPLING
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
CC44
CC44
CC45
CC45
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
CH3
CH3
CH4
CH4
1
1
2
2
VCC_CORE
V
V
V
V
V
V
V
V
V
V
V
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
5 OF 9
5 OF 9
+
AA26
CC
AA28
CC
AA34
CC
AA30
CC
AA32
CC
AB26
CC
AB29
CC
AB25
CC
AB27
CC
AB28
CC
AB30
CC
AB31
AB33
AB34
AB32
AC26
AB35
AC28
AD25
AC30
AD28
AC32
AD31
AC34
AD34
AD26
AD27
AD29
AD30
AD32
AD33
AD35
AE26
AE32
AE28
AE30
AG28
AG34
AE34
AF25
AF26
AF27
AF28
AF29
AF30
AF31
AF32
AF33
AF34
AF35
AG26
AH26
AH29
AG30
AG32
AH32
AH35
AH25
AH27
AH28
AH30
AH31
AH33
AH34
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
G25
H25
J25
K25
L25
M25
N25
P25
R25
T25
U25
U26
V25
V26
W26
W27
H
H
aswell rPGA EDS
aswell rPGA EDS
JCPU1E
JCPU1E
K27
SVD
R
L27
SVD
R
T27
R
SVD
V27
R
+
1.35VS
C38 0.1U_0402_10V6K
C38 0.1U_0402_10V6K
C
C
12
CC40 0.1U_0402_10V6KCC40 0.1U_0402_10V6K
12
+VCC_CORE
09/11 Change netname to VCCSENSE
VCCSENSE
+VCCIO_OUT
T54
@ T54
@
PAD~D
PAD~D
+VCCIOA_OUT
1
CC87
CC87
+
+
@
@
330U_D2_2V_Y
330U_D2_2V_Y
2
08/06 Reserve CC87
VR_SVID_ALRT#
VR_SVID_CLK
VR_SVID_DAT
+VCC_CORE
VR_SVID_ALRT#[47]
VR_SVID_CLK[ 47]
+1.05VS
150_0402_1%
150_0402_1%
12
RC98
RC98
CPU_PWR_DEBUG
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
CC46
CC46
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
CH5
CH5
1
1
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
CC49
CC49
CC48
CC48
CC47
CC47
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
CH8
CH8
CH7
CH7
CH6
CH6
1
1
2
2
VR_SVID_DAT[47]
CPU_PWR_DEBUG[5]
T50 P AD~D@T50 PAD~D@
T51 P AD~D@T51 PAD~D@
T52 P AD~D@T52 PAD~D@
T53 P AD~D@T53 PAD~D@
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CC41
1
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
2
CC41
1
+
+
330U_D2_2V_Y
CC50
CC50
CH9
CH9
330U_D2_2V_Y
CC51
CC51
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
CH10
CH10
CH11
CH11
1
1
2
2
SVD
AB11
V
DDQ
AB2
VDDQ
AB5
VDDQ
AB8
VDDQ
AE11
VDDQ
AE2
VDDQ
AE5
VDDQ
AE8
VDDQ
AH11
VDDQ
K11
VDDQ
N11
VDDQ
N8
VDDQ
T11
VDDQ
T2
VDDQ
T5
VDDQ
T8
VDDQ
W11
VDDQ
W2
VDDQ
W5
VDDQ
W8
VDDQ
N26
RSVD
K26
VCC
AL27
RSVD
AK27
RSVD
AL35
VCC_SENSE
E17
RSVD
AN35
VCCIO_OUT
A23
FC_A23
F22
VCOMP_OUT
W32
RSVD
AL16
RSVD
J27
RSVD
AL13
RSVD
AM28
VIDALERT
AM29
VIDSCLK
AL28
VIDSOUT
AP35
VSS
H27
PWR_DEBUG
AP34
VSS
AT35
RSVD_TP
AR35
RSVD_TP
AR32
RSVD_TP
AL26
RSVD_TP
AT34
VSS
AL22
VSS
AT33
VSS
AM21
VSS
AM25
# 04/02 change Pin name
VSS
AM22
by Intel update
VSS
AM20
VSS
AM24
VSS
AL19
VSS
AM23
VSS
AT32
VSS
Y25
VCC
Y26
VCC
Y27
VCC
Y28
VCC
Y29
VCC
Y30
VCC
Y31
VCC
Y32
VCC
Y33
VCC
Y34
VCC
Y35
VCC
INTEL_HASWELL_HASWE LL
INTEL_HASWELL_HASWE LL
# 04/02 change Pin name
by Intel update
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2012/03/23 2011/06/29
2012/03/23 2011/06/29
2012/03/23 2011/06/29
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
CPU- PWR
CPU- PWR
CPU- PWR
LA-9241P
LA-9241P
LA-9241P
1
9 56Thursday, December 20, 2012
9 56Thursday, December 20, 2012
9 56Thursday, December 20, 2012
0.5
0.5
0.5
CyberForum.ru
5
H
H
aswell rPGA EDS
aswell rPGA EDS
JCPU1F
D D
C C
B B
JCPU1F
A10
SS
V
A13
V
SS
A16
V
SS
A19
VSS
A22
VSS
A25
VSS
A27
VSS
A29
VSS
A3
VSS
A31
VSS
A33
VSS
A4
VSS
A7
VSS
AA11
VSS
AA25
VSS
AA27
VSS
AA31
VSS
AA29
VSS
AB1
VSS
AB10
VSS
AA33
VSS
AA35
VSS
AB3
VSS
AC25
VSS
AC27
VSS
AB4
VSS
AB6
VSS
AB7
VSS
AB9
VSS
AC11
VSS
AD11
VSS
AC29
VSS
AC31
VSS
AC33
VSS
AC35
VSS
AD7
VSS
AE1
VSS
AE10
VSS
AE25
VSS
AE29
VSS
AE3
VSS
AE27
VSS
AE35
VSS
AE4
VSS
AE6
VSS
AE7
VSS
AE9
VSS
AF11
VSS
AF6
VSS
AF8
VSS
AG11
VSS
AG25
VSS
AE31
VSS
AG31
VSS
AE33
VSS
AG6
VSS
AH1
VSS
AH10
VSS
AH2
VSS
AG27
VSS
AG29
VSS
AH3
VSS
AG33
VSS
AG35
VSS
AH4
VSS
AH5
VSS
AH6
VSS
AH7
VSS
AH8
VSS
AH9
VSS
AJ11
VSS
AJ5
VSS
AK11
VSS
AK25
VSS
AK26
VSS
AK28
VSS
AK29
VSS
AK30
VSS
AK32
VSS
E19
VSS
INTEL_HASWELL_HAS WELL
INTEL_HASWELL_HAS WELL
4
AK34
SS
V
AK5
V
SS
AL1
V
SS
AL10
VSS
AL11
VSS
AL12
VSS
AL14
VSS
AL15
VSS
AL17
VSS
AL18
VSS
AL2
VSS
AL20
VSS
AL21
VSS
AL23
VSS
E22
VSS
AL3
VSS
AL4
VSS
AL5
VSS
AL6
VSS
AL7
VSS
AL8
VSS
AL9
VSS
AM10
VSS
AM13
VSS
AM16
VSS
AM19
VSS
E25
VSS
AM32
VSS
AM4
VSS
AM7
VSS
AN10
VSS
AN13
VSS
AN16
VSS
AN19
VSS
AN2
VSS
AN21
VSS
AN24
VSS
AN27
VSS
AN30
VSS
AN34
VSS
AN4
VSS
AN7
VSS
AP1
VSS
AP10
VSS
AP13
VSS
AP16
VSS
AP19
VSS
AP4
VSS
AP7
VSS
W25
VSS
AR10
VSS
AR13
VSS
AR16
VSS
AR19
VSS
AR2
VSS
AR22
VSS
AR25
VSS
AR28
VSS
AR31
VSS
AR34
VSS
AR4
VSS
AR7
VSS
AT10
VSS
AT13
VSS
AT16
VSS
AT19
VSS
AT21
VSS
AT24
VSS
AT27
VSS
AT3
VSS
AT30
VSS
AT4
VSS
AT7
VSS
B10
VSS
B13
VSS
B16
VSS
B19
VSS
B2
VSS
B22
VSS
6 OF 9
6 OF 9
3
H
H
aswell rPGA EDS
aswell rPGA EDS
JCPU1G
JCPU1G
B34
SS
V
B4
V
SS
B7
V
SS
C1
VSS
C10
VSS
C13
VSS
C16
VSS
C19
VSS
C2
VSS
C22
VSS
C24
VSS
C26
VSS
C28
VSS
C30
VSS
C32
VSS
C34
VSS
C4
VSS
C7
VSS
D10
VSS
D13
VSS
D16
VSS
D19
VSS
D22
VSS
D25
VSS
D27
VSS
D29
VSS
D31
VSS
D33
VSS
D35
VSS
D4
VSS
D7
VSS
E1
VSS
E10
VSS
E13
VSS
E16
VSS
E4
VSS
E7
VSS
F10
VSS
F11
VSS
F12
VSS
F14
VSS
F15
VSS
F17
VSS
F18
VSS
F20
VSS
F21
VSS
F23
VSS
F24
VSS
F26
VSS
F28
VSS
F30
VSS
F32
VSS
F34
VSS
F4
VSS
F6
VSS
F7
VSS
F8
VSS
F9
VSS
G1
VSS
G11
VSS
G2
VSS
G27
VSS
G29
VSS
G3
VSS
G31
VSS
G33
VSS
G35
VSS
G4
VSS
G5
VSS
H10
VSS
H26
VSS
H6
VSS
H7
VSS
J11
VSS
J26
VSS
J28
VSS
J30
VSS
J32
VSS
J34
VSS
J6
VSS
K1
VSS
INTEL_HASWELL_HAS WELL
INTEL_HASWELL_HAS WELL
VSS_SENSE
V
V
V
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RSVD
7 OF 9
7 OF 9
2
K10
SS
K2
SS
K29
SS
K3
K31
K33
K35
K4
K5
K7
K8
K9
L11
L26
L6
M11
M26
M28
M30
M32
M34
M6
N1
N10
N2
N29
N3
N31
N33
N35
N4
N5
N6
N7
N9
P11
P26
P5
R11
R26
R28
R30
R32
R34
R5
T1
T10
T29
T3
T31
T33
T35
T4
T6
T7
T9
U11
U27
V11
V28
V30
V32
V34
W1
W10
W3
W35
W4
W6
W7
W9
Y11
H11
AL24
F19
T26
AK35
AK33
09/11 Change netname to VSSSENSE
VSSSENSE [47,9]
1
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2012/03/23 2011/06/29
2012/03/23 2011/06/29
2012/03/23 2011/06/29
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
CPU-VSS
CPU-VSS
CPU-VSS
LA-9241P
LA-9241P
LA-9241P
1
10 56Thursday, December 20, 2012
10 56Thursday, December 20, 2012
10 56Thursday, December 20, 2012
0.5
0.5
0.5
CyberForum.ru
5
Populate RD1, De-Populate RD7 for Intel DDR3
VREFDQ multiple methods M1
Populate RD7, De-Populate RD1 for Intel DDR3
10U_0603_6.3V6M
10U_0603_6.3V6M
CD14
CD14
1U_0402_6.3V6K
1U_0402_6.3V6K
CD24
CD24
G
G
S
S
10U_0603_6.3V6M
10U_0603_6.3V6M
1
@
@
2
2
Q
Q
2N7002K W_SOT 323-3
2N7002K W_SOT 323-3
13
D
D
+
1.35V
1
CD15
CD15
+
+
2
SGA000 04400
SGA000 04400
VREFDQ multiple methods M3
D1
D1
1 2
R
R
D24 1K_0402_1%
D24 1K_0402_1%
All VREF traces should
have 10 mil trace width
CD16
CD16
330U_B2 _2.5VM_R 15M
330U_B2 _2.5VM_R 15M
07/10 Change by HP request
+
DIMM_A_D Q
1K_0402_1%
1K_0402_1%
12
RD23
RD23
DDR_CK E0_DIMMA[6]
DDR_A_ BS2[6]
M_CLK_A _DDR0[6]
M_CLK_A _DDR#0[6]
DDR_A_ BS0[6]
DDR_A_ WE#[6]
DDR_A_ CAS#[6]
DDR_CS 1_DIMMA#[6]
+3VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
CD27
CD27
2
2
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
CD3
CD3
CD4
CD4
2
2
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
CD28
CD28
R
UN_ON_CPU1.5 VS3[12 ,9]
+
DIMM01_V REF_DQ
0
D
DR_A_D [0..63][6]
D
DR_A_D QS[0..7][6]
D
DR_A_D QS#[0..7][6]
DDR_A_ MA[0..15][6]
+1.35V
+1.35V
7/10 Change by HP request
Layout Note:
Place near JDIMM1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
C
C
C
C
D6
D6
D5
D5
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
C
C
C
C
1
1
1
D10
D10
D9
D9
2
2
2
Layout Note:
Place near JDIMM1.203,204
+0.675VS
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C
C
D21
D21
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
C
C
CD8
CD8
D7
D7
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
C
C
C
C
CD13
CD13
1
1
1
D11
D11
D12
D12
2
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
1
CD23
CD23
C
C
D22
D22
2
2
2
D D
C C
B B
A A
4
JDIMM1 H=4mm TOP
07/17 Rename JP3 to JDIMM1
1.35V
+
J
J
DIMM1
DIMM1
1
V
REF_DQ
3
V
SS2
D
DR_A_D 0
D
DR_A_D 1
D
DR_A_D 2
D
DR_A_D 3
D
DR_A_D 8
D
DR_A_D 9
DR_A_D QS#1
D
DR_A_D QS1
D
DR_A_D 10
D
DR_A_D 11
D
DDR_A_ D17
DDR_A_ DQS#2
DDR_A_ DQS2
DDR_A_ D18
DDR_A_ D19
DDR_A_ D24
DDR_A_ D25
DDR_A_ D26
DDR_A_ D27
DDR_CK E0_DIMMA DDR_C KE1_D IMMA
DDR_A_ BS2
DDR_A_ MA3
M_CLK_A _DDR0
M_CLK_A _DDR#0
DDR_A_ MA10
DDR_A_ BS0
DDR_A_ WE#
DDR_A_ CAS#
DDR_A_ MA13
DDR_CS 1_DIMMA#
DDR_A_ D32
DDR_A_ D33
DDR_A_ DQS#4
DDR_A_ DQS4
DDR_A_ D34
DDR_A_ D35
DDR_A_ D40
DDR_A_ D41
DDR_A_ D42
DDR_A_ D43
DDR_A_ D48
DDR_A_ D49
DDR_A_ DQS#6
DDR_A_ DQS6
DDR_A_ D50
DDR_A_ D51
DDR_A_ D56
DDR_A_ D57
DDR_A_ D58
DDR_A_ D59
5
D
Q0
7
Q1
D
9
SS4
V
11
M0
D
13
SS5
V
15
Q2
D
17
D
Q3
19
V
SS7
21
D
Q8
23
D
Q9
25
V
SS9
27
D
QS#1
29
D
QS1
31
SS11
V
33
Q10
D
35
Q11
D
37
V
SS13
DQ1639DQ20
DQ1741DQ21
VSS1543VSS16
DQS#245DM2
DQS247VSS17
VSS1849DQ22
DQ1851DQ23
DQ1953VSS19
VSS2055DQ28
DQ2457DQ29
DQ2559VSS21
VSS2261DQS#3
DM363DQS3
VSS2365VSS24
DQ2667DQ30
DQ2769DQ31
VSS2571VSS26
CKE073CKE1
VDD175VDD2
NC177A15
BA279A14
VDD381VDD4
A12/BC#83A11
85
A9
VDD587VDD6
89
A8
91
A5
VDD793VDD8
95
A3
97
A1
VDD999VDD10
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
FOX_AS 0A626-U4 RN-7F
FOX_AS 0A626-U4 RN-7F
CONN@
CONN@
08/07 Change JDIMM1 footprint
R
VREF_CA
EVENT#
1.35V
+
2
V
SS1
4
D
DR_A_D 4
D
Q4
6
D
DR_A_D 5
D
Q5
8
SS3
V
10
D
DR_A_D QS#0
QS#0
D
12
D
DR_A_D QS0
QS0
D
14
SS6
V
16
D
DR_A_D 6
Q6
D
18
D
DR_A_D 7
D
Q7
20
V
SS8
22
D
DR_A_D 12
D
Q12
24
D
DR_A_D 13
D
Q13
26
V
SS10
28
D
M1
30
DR3_DR AMRST#_ R
D
ESET#
32
SS12
V
34
DR_A_D 14
D
Q14
D
36
DR_A_D 15
D
Q15
D
38
V
SS14
40
DDR_A_ D20DD R_A_D 16
42
DDR_A_ D21
44
46
48
50
DDR_A_ D22
52
DDR_A_ D23
54
56
DDR_A_ D28
58
DDR_A_ D29
60
62
DDR_A_ DQS#3
64
DDR_A_ DQS3
66
68
DDR_A_ D30
70
DDR_A_ D31
72
74
76
78
DDR_A_ MA15
80
DDR_A_ MA14
82
84
DDR_A_ MA11DDR_A_ MA12
86
DDR_A_ MA7DDR_A_ MA9
A7
88
90
DDR_A_ MA6DDR_A_ MA8
A6
92
DDR_A_ MA4DDR_A_ MA5
A4
94
96
DDR_A_ MA2
A2
98
DDR_A_ MA0DDR_A_ MA1
A0
100
102
M_CLK_A _DDR1
CK1
104
M_CLK_A _DDR#1
CK1#
106
VDD12
108
DDR_A_ BS1
BA1
110
DDR_A_ RAS#
RAS#
112
VDD14
114
DDR_CS 0_DIMMA#
S0#
116
M_A_ODT 0
ODT0
118
VDD16
120
M_A_ODT 1
ODT1
122
NC2
124
VDD18
126
128
VSS28
130
DDR_A_ D36
DQ36
132
DDR_A_ D37
DQ37
134
VSS30
136
DM4
138
VSS31
140
DDR_A_ D38
DQ38
142
DDR_A_ D39
DQ39
144
VSS33
146
DDR_A_ D44
DQ44
148
DDR_A_ D45
DQ45
150
VSS35
152
DDR_A_ DQS#5
DQS#5
154
DDR_A_ DQS5
DQS5
156
VSS38
158
DDR_A_ D46
DQ46
160
DDR_A_ D47
DQ47
162
VSS40
164
DDR_A_ D52
DQ52
166
DDR_A_ D53
DQ53
168
VSS42
170
DM6
172
VSS43
174
DDR_A_ D54
DQ54
176
DDR_A_ D55
DQ55
178
VSS45
180
DDR_A_ D60
DQ60
182
DDR_A_ D61
DQ61
184
VSS47
186
DDR_A_ DQS#7
DQS#7
188
DDR_A_ DQS7
DQS7
190
VSS50
192
DDR_A_ D62
DQ62
194
DDR_A_ D63
DQ63
196
VSS52
198
200
SDA
202
SCL
204
VTT2
G2
+0.675VS+0.675VS
206
Reverse
D
DR3_DR AMRST#_ R[12]
DDR_CK E1_DIMMA [6]
M_CLK_A _DDR1 [6]
M_CLK_A _DDR#1 [6]
DDR_A_ BS1 [6]
DDR_A_ RAS# [6]
DDR_CS 0_DIMMA# [6]
M_A_ODT 0 [6]
+DIMM_VRE F_CA
M_A_ODT 1 [6]
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
1K_0402_1%
1K_0402_1%
12
CD19
CD19
1
1
RD25
RD25
2
2
DDR_XD P_WAN_ SMBDAT [12 ,13,16,2 8,38,5]
DDR_XD P_WAN_ SMBCLK [1 2,13,16 ,28,38,5]
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CD20
CD20
R
R
D6 33_0402_5 %
D6 33_0402_5 %
08/03 Change RD6 to 33 ohms
1 2
RD26 1K_0402_1%RD26 1K_0402_1%
1 3
D
S
D
S
QD2
QD2
G
G
2N7002K W_SOT 323-3
2N7002K W_SOT 323-3
2
3
1 2
+1.35V
+SM_VREF _CA
RUN_ON_CPU1 .5VS3
2
1
JDIMM1 H=5.2mm BOT
+3VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
CD25
CD25
2
07/10 Change by HP request
+
DIMM_A_D Q
1
2
DDR_CK E2_DIMMA[6]
M_CLK_A_ DDR2[6]
M_CLK_A_ DDR#2[6]
DDR_CS 3_DIMMA#[6]
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
1
CD26
CD26
2
+
1.35V
DIMM3
DIMM3
J
J
1
V
REF_DQ
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
D
DR_A_D 0
DR_A_D 1
D
1
CD2
CD2
CD1
CD1
2
D
DR_A_D 2
D
DR_A_D 3
D
DR_A_D 8
D
DR_A_D 9
D
DR_A_D QS#1
D
DR_A_D QS1
DR_A_D 10
D
DR_A_D 11
D
DR_A_D 16
D
DR_A_D 17
D
DDR_A_ DQS#2
DDR_A_ DQS2
DDR_A_ D18
DDR_A_ D19
DDR_A_ D24
DDR_A_ D25
DDR_A_ D26
DDR_A_ D27
DDR_CK E2_DIMMA
DDR_A_ BS2
DDR_A_ MA12
DDR_A_ MA9
DDR_A_ MA8
DDR_A_ MA5
DDR_A_ MA3
DDR_A_ MA1
M_CLK_A_ DDR2
M_CLK_A_ DDR#2
DDR_A_ MA10
DDR_A_ BS0
DDR_A_ CAS#
DDR_A_ MA13
DDR_CS 3_DIMMA#
DDR_A_ D32
DDR_A_ D33
DDR_A_ DQS#4
DDR_A_ DQS4
DDR_A_ D34
DDR_A_ D35
DDR_A_ D40
DDR_A_ D41
DDR_A_ D42
DDR_A_ D43
DDR_A_ D48
DDR_A_ D49
DDR_A_ DQS#6
DDR_A_ DQS6
DDR_A_ D50
DDR_A_ D51
DDR_A_ D56
DDR_A_ D57
DDR_A_ D58
DDR_A_ D59
+0.675VS
3
V
SS2
5
D
Q0
7
D
Q1
9
V
SS4
11
D
M0
13
SS5
V
15
Q2
D
17
Q3
D
19
SS7
V
21
Q8
D
23
D
Q9
25
V
SS9
27
D
QS#1
29
D
QS1
31
V
SS11
33
D
Q10
35
D
Q11
37
SS13
V
39
Q16
D
41
Q17
D
43
V
SS15
DQS#245DM2
DQS247VSS17
VSS1849DQ22
DQ1851DQ23
DQ1953VSS19
VSS2055DQ28
DQ2457DQ29
DQ2559VSS21
VSS2261DQS#3
DM363DQS3
VSS2365VSS24
DQ2667DQ30
DQ2769DQ31
VSS2571VSS26
CKE073CKE1
VDD175VDD2
NC177A15
BA279A14
VDD381VDD4
A12/BC#83A11
85
A9
VDD587VDD6
89
A8
91
A5
VDD793VDD8
95
A3
97
A1
VDD999VDD10
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
LCN_DAN0 6-K4406 -0102
LCN_DAN0 6-K4406 -0102
CONN@
CONN@
D
V
R
ESET#
V
V
V
VDD12
VDD14
VDD16
VDD18
VREF_CA
VSS28
VSS30
VSS31
VSS33
VSS35
DQS#5
VSS38
VSS40
VSS42
VSS43
VSS45
VSS47
DQS#7
VSS50
VSS52
EVENT#
+
1.35V
2
V
SS1
4
D
DR_A_D 4
D
Q4
6
D
DR_A_D 5
D
Q5
8
V
SS3
10
D
DR_A_D QS#0
QS#0
12
D
DR_A_D QS0
D
QS0
14
SS6
V
16
D
DR_A_D 6
Q6
D
18
D
DR_A_D 7
Q7
D
20
SS8
V
22
D
DR_A_D 12
Q12
D
24
D
DR_A_D 13
D
Q13
26
SS10
28
D
M1
30
D
DR3_DR AMRST#_ R
32
SS12
34
DR_A_D 14
D
D
Q14
36
DR_A_D 15
D
D
Q15
38
SS14
40
DR_A_D 20
D
Q20
D
42
DR_A_D 21
D
Q21
D
44
SS16
46
48
50
DDR_A_D 22
52
DDR_A_D 23
54
56
DDR_A_D 28
58
DDR_A_D 29
60
62
DDR_A_D QS#3
64
DDR_A_D QS3
66
68
DDR_A_D 30
70
DDR_A_D 31
72
74
DDR_CKE 3_DIMMA
76
78
DDR_A_MA 15
80
DDR_A_MA 14
82
84
DDR_A_MA 11
86
DDR_A_MA 7
A7
88
90
DDR_A_MA 6
A6
92
DDR_A_MA 4
A4
94
96
DDR_A_MA 2
A2
98
DDR_A_MA 0
A0
100
102
M_CLK_A_ DDR3
CK1
104
M_CLK_A_ DDR#3
CK1#
106
108
DDR_A_B S1
BA1
110
DDR_A_R AS#
RAS#
112
114
DDR_CS2 _DIMMA#DDR_A_ WE#
S0#
116
M_A_ODT2
ODT0
118
120
M_A_ODT3
ODT1
122
NC2
124
126
128
130
DDR_A_D 36
DQ36
132
DDR_A_D 37
DQ37
134
136
DM4
138
140
DDR_A_D 38
DQ38
142
DDR_A_D 39
DQ39
144
146
DDR_A_D 44
DQ44
148
DDR_A_D 45
DQ45
150
152
DDR_A_D QS#5
154
DDR_A_D QS5
DQS5
156
158
DDR_A_D 46
DQ46
160
DDR_A_D 47
DQ47
162
164
DDR_A_D 52
DQ52
166
DDR_A_D 53
DQ53
168
170
DM6
172
174
DDR_A_D 54
DQ54
176
DDR_A_D 55
DQ55
178
180
DDR_A_D 60
DQ60
182
DDR_A_D 61
DQ61
184
186
DDR_A_D QS#7
188
DDR_A_D QS7
DQS7
190
192
DDR_A_D 62
DQ62
194
DDR_A_D 63
DQ63
196
198
200
DDR_XDP _WAN_ SMBDAT
SDA
202
DDR_XDP _WAN_ SMBCLK
SCL
204
VTT2
206
G2
+0.675VS
DDR_CKE 3_DIMMA [6]
M_CLK_A_ DDR3 [6]
M_CLK_A_ DDR#3 [6 ]
DDR_CS2 _DIMMA# [6]
M_A_ODT2 [6]
M_A_ODT3 [6]
1
2
+DIMM_VRE F_CA
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
CD17
CD17
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CD18
CD18
1
2
+
1.35V
1K_0402_5%
1K_0402_5%
12
RD2
RD2
All VREF traces should
C
PU_DRAM_ RST# [5 ]
have 10 mil trace width
Standard
5
4
3
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
Compal Secret Dat a
Compal Secret Dat a
Compal Secret Dat a
2012/03/23 2011/06/29
2012/03/23 2011/06/29
2012/03/23 2011/06/29
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
DDRIII DIMM1&2
DDRIII DIMM1&2
DDRIII DIMM1&2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
LA-9241P
LA-9241P
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-9241P
1
11 56Thursday, Dece mber 20 , 2012
11 56Thursday, Dece mber 20 , 2012
11 56Thursday, Dece mber 20 , 2012
0.5
0.5
0.5
CyberForum.ru
5
Populate RD4, De-Populate RD8 for Intel DDR3
VREFDQ multiple methods M1
Populate RD8, De-Populate RD4 for Intel DDR3
VREFDQ multiple methods M3
D D
All VREF traces should
D
DR_B_D [0..63][6]
D
DR_B_D QS[0..7][6]
D
DR_B_D QS#[0..7][6]
D
DR_B_MA [0..15][6]
Layout Note:
Place near JDIMM2
C C
B B
A A
+1.35V
+1.35V
10U_0603_6.3V6M
10U_0603_6.3V6M
C
C
1
D37
D37
2
+0.675VS
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
C
C
C
C
D33
D33
D34
D34
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
C
C
C
C
1
1
1
D38
D38
D39
D39
2
2
2
Layout Note:
Place near JDIMM2.203,204
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
C
C
C
C
D49
D49
D50
D50
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
C
C
CD36
CD36
D35
D35
@
@
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
C
C
CD42
CD42
CD41
CD41
1
1
D40
D40
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
C
C
CD52
CD52
D51
D51
2
2
have 10 mil trace width
100P_0402_50V8J
100P_0402_50V8J
1
C511
C511
2
11/06 Add C511 by rf request
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CD43
CD43
1
+
+
@
@
CD44
CD44
330U_B2 _2.5VM_R 15M
330U_B2 _2.5VM_R 15M
2
2
0
7/10 Change by HP request
+
DIMM_B_D Q
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
CD31
CD31
1
2
DDR_CK E0_DIMMB[6]
DDR_B_ BS2[6 ]
M_CLK_B _DDR0[6]
M_CLK_B _DDR#0[6]
DDR_B_ BS0[6]
DDR_B_ WE#[6]
DDR_B_ CAS#[6]
DDR_CS 1_DIMMB#[6]
+3VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
CD55
CD55
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
CD32
CD32
2
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
CD56
CD56
1
2
4
JDIMM2 H=9.2mm TOP
+
1.35V
1
3
D
DR_B_D 0
D
DR_B_D 1
D
DR_B_D 2
D
DR_B_D 3
D
DR_B_D 8
D
DR_B_D 9
D
DR_B_D QS#1
DR_B_D QS1
D
D
DR_B_D 10
DR_B_D 11
D
D
DR_B_D 16
DDR_B_ D17
DDR_B_ DQS#2
DDR_B_ DQS2
DDR_B_ D18
DDR_B_ D19
DDR_B_ D24
DDR_B_ D25
DDR_B_ D26
DDR_B_ D27
DDR_CK E0_DIMMB
DDR_B_ BS2
DDR_B_ MA12
DDR_B_ MA9
DDR_B_ MA8
DDR_B_ MA5
DDR_B_ MA3
DDR_B_ MA1
M_CLK_B _DDR0
M_CLK_B _DDR#0
DDR_B_ MA10
DDR_B_ BS0
DDR_B_ WE#
DDR_B_ CAS#
DDR_B_ MA13
DDR_CS 1_DIMMB#
DDR_B_ D32
DDR_B_ D33
DDR_B_ DQS#4
DDR_B_ DQS4
DDR_B_ D34
DDR_B_ D35
DDR_B_ D40
DDR_B_ D41
DDR_B_ D42
DDR_B_ D43
DDR_B_ D48
DDR_B_ D49
DDR_B_ DQS#6
DDR_B_ DQS6
DDR_B_ D50
DDR_B_ D51
DDR_B_ D56
DDR_B_ D57
DDR_B_ D58
DDR_B_ D59
+0.675VS
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
08/07 Change JDIMM2 footprint
J
J
DIMM2
DIMM2
V
REF_DQ
V
SS2
D
Q0
D
Q1
SS4
V
M0
D
SS5
V
Q2
D
Q3
D
V
SS7
D
Q8
D
Q9
V
SS9
D
QS#1
D
QS1
V
SS11
Q10
D
Q11
D
SS13
V
D
Q16
DQ1741DQ21
VSS1543VSS16
DQS#245DM2
DQS247VSS17
VSS1849DQ22
DQ1851DQ23
DQ1953VSS19
VSS2055DQ28
DQ2457DQ29
DQ2559VSS21
VSS2261DQS#3
DM363DQS3
VSS2365VSS24
DQ2667DQ30
DQ2769DQ31
VSS2571VSS26
CKE073CKE1
VDD175VDD2
NC177A15
BA279A14
VDD381VDD4
A12/BC#83A11
A985A7
VDD587VDD6
A889A6
A591A4
VDD793VDD8
A395A2
A197A0
VDD999VDD10
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VREF_CA
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
G1
TYCO_2-2 013311 -4
TYCO_2-2 013311 -4
CONN@
CONN@
Reverse
R
EVENT#
3
UN_ON_CPU1.5 VS3[11 ,9]
R
+
+
1.35V
2
V
SS1
4
DR_B_D 4
D
D
Q4
6
D
DR_B_D 5
D
Q5
8
V
SS3
10
D
DR_B_D QS#0
QS#0
D
12
D
DR_B_D QS0
QS0
D
14
SS6
V
16
D
DR_B_D 6
Q6
D
18
D
DR_B_D 7
Q7
D
20
V
SS8
22
D
DR_B_D 12
D
Q12
24
D
DR_B_D 13
D
Q13
26
V
SS10
28
D
M1
30
DR3_DR AMRST#_ R
D
ESET#
32
V
SS12
34
D
DR_B_D 14
Q14
D
36
DR_B_D 15
D
Q15
D
38
SS14
V
40
D
DR_B_D 20
D
Q20
42
DDR_B_ D21
44
46
48
50
DDR_B_ D22
52
DDR_B_ D23
54
56
DDR_B_ D28
58
DDR_B_ D29
60
62
DDR_B_ DQS#3
64
DDR_B_ DQS3
66
68
DDR_B_ D30
70
DDR_B_ D31
72
74
DDR_CK E1_DIMMB
76
78
DDR_B_ MA15
80
DDR_B_ MA14
82
84
DDR_B_ MA11
86
DDR_B_ MA7
88
90
DDR_B_ MA6
92
DDR_B_ MA4
94
96
DDR_B_ MA2
98
DDR_B_ MA0
100
102
M_CLK_B _DDR1
CK1
104
M_CLK_B _DDR#1
CK1#
106
VDD12
108
DDR_B_ BS1
BA1
110
DDR_B_ RAS#
RAS#
112
VDD14
114
DDR_CS 0_DIMMB#
S0#
116
M_B_ODT 0
ODT0
118
VDD16
120
M_B_ODT 1
ODT1
122
NC2
124
VDD18
126
128
VSS28
130
DDR_B_ D36
DQ36
132
DDR_B_ D37
DQ37
134
VSS30
136
DM4
138
VSS31
140
DDR_B_ D38
DQ38
142
DDR_B_ D39
DQ39
144
VSS33
146
DDR_B_ D44
DQ44
148
DDR_B_ D45
DQ45
150
VSS35
152
DDR_B_ DQS#5
DQS#5
154
DDR_B_ DQS5
DQS5
156
VSS38
158
DDR_B_ D46
DQ46
160
DDR_B_ D47
DQ47
162
VSS40
164
DDR_B_ D52
DQ52
166
DDR_B_ D53
DQ53
168
VSS42
170
DM6
172
VSS43
174
DDR_B_ D54
DQ54
176
DDR_B_ D55
DQ55
178
VSS45
180
DDR_B_ D60
DQ60
182
DDR_B_ D61
DQ61
184
VSS47
186
DDR_B_ DQS#7
DQS#7
188
DDR_B_ DQS7
DQS7
190
VSS50
192
DDR_B_ D62
DQ62
194
DDR_B_ D63
DQ63
196
VSS52
198
200
SDA
202
SCL
204
VTT2
+0.675VS
206
G2
DIMM23_V REF_DQ
DR3_DR AMRST#_ R [11]
D
DDR_CK E1_DIMMB [6]
M_CLK_B _DDR1 [6]
M_CLK_B _DDR#1 [6 ]
DDR_B_ BS1 [6]
DDR_B_ RAS# [6]
DDR_CS 0_DIMMB# [6]
M_B_ODT0 [6]
+DIMM_VRE F_CA
M_B_ODT1 [6]
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
CD48
CD48
CD47
CD47
1
1
2
2
DDR_XD P_WAN_ SMBDAT [11 ,13,16,2 8,38,5]
DDR_XD P_WAN_ SMBCLK [1 1,13,16 ,28,38,5]
07/10 Change by HP request
G
G
2
D3
D3
Q
Q
2N7002K W_SOT 323-3
2N7002K W_SOT 323-3
13
D
S
D
S
+
1.35V
All VREF traces should
have 10 mil trace width
1 2
D27 1K_0402_1%
D27 1K_0402_1%
R
R
+
DIMM_B_D Q
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R
R
D28
D28
12
1K_0402_1%
1K_0402_1%
1
CD30
CD30
2
DDR_CK E2_DIMMB[6]
M_CLK_B_ DDR2[6]
M_CLK_B_ DDR#2[6]
DDR_CS 3_DIMMB#[6]
+3VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
CD54
CD54
1
1
CD53
CD53
2
2
JDIMM4 H=5.2mm BOT
/16 change by HP requirement
4
+
1.35V
D
DR_B_D 0
D
DR_B_D 1
D
DR_B_D 2
D
DR_B_D 3
D
DR_B_D 8
D
DR_B_D 9
D
DR_B_D QS#1
D
DR_B_D QS1
D
DR_B_D 10
DR_B_D 11
D
D
DR_B_D 16
DR_B_D 17
D
D
DR_B_D QS#2
DDR_B_ DQS2
DDR_B_ D18
DDR_B_ D19
DDR_B_ D24
DDR_B_ D25
DDR_B_ D26
DDR_B_ D27
DDR_CK E2_DIMMB
DDR_B_ BS2
DDR_B_ MA12
DDR_B_ MA9
DDR_B_ MA8
DDR_B_ MA5
DDR_B_ MA3
DDR_B_ MA1
M_CLK_B_ DDR2
M_CLK_B_ DDR#2
DDR_B_ MA10
DDR_B_ BS0
DDR_B_ WE#
DDR_B_ CAS#
DDR_B_ MA13
DDR_CS 3_DIMMB#
DDR_B_ D32
DDR_B_ D33
DDR_B_ DQS#4
DDR_B_ DQS4
DDR_B_ D34
DDR_B_ D35
DDR_B_ D40
DDR_B_ D41
DDR_B_ D42
DDR_B_ D43
DDR_B_ D48
DDR_B_ D49
DDR_B_ DQS#6
DDR_B_ DQS6
DDR_B_ D50
DDR_B_ D51
DDR_B_ D56
DDR_B_ D57
DDR_B_ D58
DDR_B_ D59
+0.675VS
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207
J
J
DIMM4
DIMM4
1
V
REF_DQ
3
V
SS
5
D
Q0
7
D
Q1
9
V
SS
D
M0
V
SS
Q2
D
Q3
D
SS
V
Q8
D
Q9
D
V
SS
D
QS1#
D
QS1
V
SS
D
Q10
D
Q11
V
SS
Q16
D
Q17
D
SS
V
D
QS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
GND1
BOSS1
LCN_DAN0 6-K4406 -0103
LCN_DAN0 6-K4406 -0103
CONN@
CONN@
D
R
DQS3#
VREF_CA
DQS5#
DQS7#
EVENT#
BOSS2
2
+
1.35V
2
V
SS
4
DR_B_D 4
D
D
Q4
6
D
DR_B_D 5
D
Q5
8
V
SS
10
DR_B_D QS#0
D
QS0#
12
D
DR_B_D QS0
D
QS0
14
V
SS
16
D
DR_B_D 6
Q6
D
18
D
DR_B_D 7
Q7
D
20
SS
V
22
D
DR_B_D 12
Q12
D
24
D
DR_B_D 13
Q13
D
26
V
SS
28
D
M1
30
D
DR3_DR AMRST#_ R
ESET#
32
V
SS
34
D
DR_B_D 14
D
Q14
36
DR_B_D 15
D
D
Q15
38
V
SS
40
D
DR_B_D 20
Q20
D
42
DR_B_D 21
D
Q21
D
44
SS
V
46
D
M2
48
VSS
50
DDR_B_ D22
DQ22
52
DDR_B_ D23
DQ23
54
VSS
56
DDR_B_ D28
DQ28
58
DDR_B_ D29
DQ29
60
VSS
62
DDR_B_ DQS#3
64
DDR_B_ DQS3
DQS3
66
VSS
68
DDR_B_ D30
DQ30
70
DDR_B_ D31
DQ31
72
VSS
74
DDR_CK E3_DIMMB
CKE1
76
VDD
78
DDR_B_ MA15
A15
80
DDR_B_ MA14
A14
82
VDD
84
DDR_B_ MA11
A11
86
DDR_B_ MA7
A7
88
VDD
90
DDR_B_ MA6
A6
92
DDR_B_ MA4
A4
94
VDD
96
DDR_B_ MA2
A2
98
DDR_B_ MA0
A0
100
VDD
102
M_CLK_B_ DDR3
CK1
104
M_CLK_B_ DDR#3
CK1#
106
VDD
108
DDR_B_ BS1
BA1
110
DDR_B_ RAS#
RAS#
112
VDD
114
DDR_CS 2_DIMMB#
S0#
116
M_B_ODT2
ODT0
118
VDD
120
M_B_ODT3
ODT1
122
NC
124
VDD
126
128
VSS
130
DDR_B_ D36
DQ36
132
DDR_B_ D37
DQ37
134
VSS
136
DM4
138
VSS
140
DDR_B_ D38
DQ38
142
DDR_B_ D39
DQ39
144
VSS
146
DDR_B_ D44
DQ44
148
DDR_B_ D45
DQ45
150
VSS
152
DDR_B_ DQS#5
154
DDR_B_ DQS5
DQS5
156
VSS
158
DDR_B_ D46
DQ46
160
DDR_B_ D47
DQ47
162
VSS
164
DDR_B_ D52
DQ52
166
DDR_B_ D53
DQ53
168
VSS
170
DM6
172
VSS
174
DDR_B_ D54
DQ54
176
DDR_B_ D55
DQ55
178
VSS
180
DDR_B_ D60
DQ60
182
DDR_B_ D61
DQ61
184
VSS
186
DDR_B_ DQS#7
188
DDR_B_ DQS7
DQS7
190
VSS
192
DDR_B_ D62
DQ62
194
DDR_B_ D63
DQ63
196
VSS
198
200
DDR_XD P_WAN_ SMBDAT
SDA
202
DDR_XD P_WAN_ SMBCLK
SCL
204
VTT
GND2
+0.675VS
206
208
DDR_CKE 3_DIMMB [6]
M_CLK_B_ DDR3 [6]
M_CLK_B_ DDR#3 [6 ]
DDR_CS2 _DIMMB# [6]
M_B_ODT2 [6]
+DIMM_VRE F_CA
M_B_ODT3 [6]
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
CD45
CD45
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CD46
CD46
1
2
1
Reverse
5
4
3
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
Compal Secret Dat a
Compal Secret Dat a
Compal Secret Dat a
2012/03/23 2011/06/29
2012/03/23 2011/06/29
2012/03/23 2011/06/29
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
DDRIII DIMM3&4
DDRIII DIMM3&4
DDRIII DIMM3&4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
LA-9241P
LA-9241P
Date: Sheet of
Date: Sheet of
Date: Sheet of
LA-9241P
1
12 56Thursday, Dece mber 20 , 2012
12 56Thursday, Dece mber 20 , 2012
12 56Thursday, Dece mber 20 , 2012
0.5
0.5
0.5
CyberForum.ru
5
+
RTCVCC
330K_0402_5%
330K_0402_5%
12
R
R
H6
H6
P
D D
INTVRMEN - INTEGRATED SUS 1.05V VRM
ENABLE
High - Enable Internal VRs
Low - Enable External VRs
+3VS
1 2
@
@
RH29 10K_0402_5%
RH29 10K_0402_5%
NO REBOOT STRAP
DISABLED WHEN LOW (DEFAULT)
ENABLED WHEN HIGH
C C
B B
1 2
@
@
RH33 100K_0402_5%
RH33 100K_0402_5%
08/03 RH33.1 connection to GND
HDA_SYNC Isolation Circuit
A A
W=20mils
CH102
CH102
1
1U_0603_10V4Z
1U_0603_10V4Z
2
Place near PCH
CH_INTVRMEN
HDA_SPKR
HDD_HALTLED
CMOS_CLR1
Shunt Clear CMOS
Open
ME_CLR1
Shunt Clear ME RTC Registers
Open
SB000002X00
SB000002X00
BSS138W-7-F_SOT323-3
BSS138W-7-F_SOT323-3
RH43
RH43
1M_0402_5%
1M_0402_5%
1 2
D40
D40
1
DAN202U_SC70
DAN202U_SC70
5
BAT_GRNLED#[30,39]
+3V_PCH
RH30 2.2K_0402_5%RH30 2.2K_0402_5%
09/03 Instal RH31
09/19 Change QH11 to P MOS, change RH30 to 2.2K ohms
CMOS setting
Keep CMOS
TPM setting
Keep ME RTC Registers
+5VS
G
G
2
QH2
QH2
13
D
S
D
S
2
3
+BATT_D
W=20mils
1 2
07/09 Change by HP request.
10/26 Swap QH11A.2 and QH11B.5 connection
2
G
G
QH11A
1 6
S
S
MESS84DW-G_SC88-6
MESS84DW-G_SC88-6
1
1
@
@
ME1 SHORT PADS
ME1 SHORT PADS
CH15 1U_0402_6.3V6KCH15 1U_0402_6.3V6K
W=20mils
QH11A
D
D
1 2
W=20mils
12
FLASH DESCRIPTOR SECURITY OVERRIDE
LOW = DESABLED (DEFAULT)
HIGH = ENABLED
HDA_SYNCHDA_SYNC_R
+BATT1.1+RTCVCC +3VDS
RH233
RH233
1K_0402_5%
1K_0402_5%
4 3
S
S
MESS84DW-G_SC88-6
MESS84DW-G_SC88-6
+RTCVCC
2
2
ACES_50271-00201-001
ACES_50271-00201-001
08/07 Change JBATT1 footprint
4
PLT_RST#
5
G
G
QH11B
QH11B
HDA_SDOUT
D
D
1 2
RH34 20K_0402_5%RH34 20K_0402_5%
1 2
RH35 1M_0402_5%RH35 1M_0402_5%
1 2
RH36 20K_0402_5%RH36 20K_0402_5%
+3V_PCH
JBATT1
JBATT1
1
1
2
2
3
G1
4
G2
CONN@
CONN@
4
07/09 Delete by HP request.
RH28 10M_0402_5%RH28 10M_0402_5%
18P_0402_50V8J
18P_0402_50V8J
32.768KHZ_12.5PF_Q13FC1350000500
32.768KHZ_12.5PF_Q13FC1350000500
1
CH13
CH13
2
11/01 Change YH1 to small package
WWAN_DET#[25]
1
1
@
@
CMOS1 SHORT PADS
CMOS1 SHORT PADS
CH16
CH16
CMOS place near DIMM
2
2
1 2
1U_0402_6.3V6K
1U_0402_6.3V6K
1 2
@RH40
@
1 2
@RH41
@
1 2
@RH44
@
12
HDA_SDOUT_AUDIO[26]
HDA_RST_AUDIO#[26]
HDA_BITCLK_AUDIO[26]
200_0402_5%
200_0402_5%
200_0402_5%
200_0402_5%
200_0402_5%
200_0402_5%
HDA_SYNC_AUDIO[26]
RH39 51_0402_1%@RH39 51_0402_1%@
RH40
RH41
RH44
09/21 Non-install RH39, RH40,
RH41, RH44, RH48, RH47, RH46
1 2
YH1
YH1
1 2
PCH_RTCX1
PCH_RTCX2
1
CH14
CH14
18P_0402_50V8J
18P_0402_50V8J
2
1 2
RH230 0_0402_5%RH230 0_0402_5%
PCH_RTCRST#[14]
HDA_SPKR[26]
HDA_SDI0[26]
07/06 Follow HP's GPIO table
HDD_HALTLED[39]
ISO_PREP#[33,36]
100_0402_1%
100_0402_1%
100_0402_1%
100_0402_1%
100_0402_1%
100_0402_1%
12
12
12
RH46
RH46
RH48
RH48
RH47
RH47
@
@
@
@
@
@
27P_0402_50V8J
27P_0402_50V8J
@CH17
@
CH17
1
2
3
DDR_XDP_WAN_SMBDAT[11,12,16,28,38,5]
DDR_XDP_WAN_SMBCLK[11,12,16,28,38,5]
PCH_RTCX1
PCH_RTCX2
SRTCRST#
INTRUDER#
PCH_INTVRMEN
PCH_RTCRST#
HDA_BIT_CLK
HDA_SYNC
HDA_SPKR
HDA_RST#
HDA_SDI0
HDA_SDOUT
HDD_HALTLED
ISO_PREP#
PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
1 2
RH45 0_0402_5%RH45 0_0402_5%
1 2
RH51 33_0402_5%RH51 33_0402_5%
RP6
RP6
4 5
3 6
2 7
1 8
33_8P4R_5%
33_8P4R_5%
10/25 Delete RH50, RH52, RH53. Add RP6
3
PCH_TP25
HDA_SYNC_R
HDA_SDOUT
HDA_RST#
HDA_BIT_CLK
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
RH37
RH37
10K_0402_5%
10K_0402_5%
UH1A
UH1A
B5
RTCX1
B4
RTCX2
B9
SRTCRST#
A8
INTRUDER#
G10
INTVRMEN
D9
RTCRST#
B25
HDA_BCLK
A22
HDA_SYNC
AL10
SPKR
C24
HDA_RST#
L22
HDA_SDI0
K22
HDA_SDI1
G22
HDA_SDI2
F22
HDA_SDI3
A24
HDA_SDO
B17
DOCKEN#/GPIO33
C22
HDA_DOCK_RST #/GPIO13
AB3
JTAG_TCK
AD1
JTAG_TMS
AE2
JTAG_TDI
AD3
JTAG_TDO
F8
TP25
C26
TP22
AB6
TP20
2
RH38
RH38
10K_0402_5%
10K_0402_5%
1 2
1 2
+3VS
LPT_PCH_M_EDS
LPT_PCH_M_EDS
REV = 5
REV = 5
SATA_RXN_0
SATA_RXP_0
SATA_TXN_0
SATA_TXP_0
SATA_RXN_1
SATA_RXP_1
SATA_TXN_1
SATA_TXP_1
SATA
SATA
JTAGRTC AZALIA
JTAGRTC AZALIA
LYNXPOINT_BGA695
LYNXPOINT_BGA695
1 OF 11
1 OF 11
Compal Secret Data
Compal Secret Data
2012/03/23 2011/06/29
2012/03/23 2011/06/29
2012/03/23 2011/06/29
Compal Secret Data
SATA_RXN_2
SATA_RXP_2
SATA_TXN_2
SATA_TXP_2
SATA_RXN_3
SATA_RXP_3
SATA_TXN_3
SATA_TXP_3
SATA_RXN4/PERN1
SATA_RXP4/PERP1
SATA_TXN4/PETN1
SATA_TXP4/PETP1
SATA_RXN5/PERN2
SATA_RXP5/PERP2
SATA_TXN5/PETN2
SATA_TXP5/PETP2
SATA_RCOMP
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA_IREF
Deciphered Date
Deciphered Date
Deciphered Date
2
SATALED#
SATA Impedance Compensation
07/09 Delete by HP request.
BC8
SATA_PRX_DTX_N0
BE8
SATA_PRX_DTX_P0
AW8
SATA_PTX_DRX_N0
AY8
SATA_PTX_DRX_P0
BC10
SATA_PRX_DTX_N1
BE10
SATA_PRX_DTX_P1
AV10
SATA_PTX_DRX_N1
AW10
SATA_PTX_DRX_P1
BB9
SATA_PRX_DTX_N2
BD9
SATA_PRX_DTX_P2
AY13
SATA_PTX_DRX_N2
AW13
SATA_PTX_DRX_P2
BC12
SATA_PRX_DTX_N3
BE12
SATA_PRX_DTX_P3
AR13
SATA_PTX_DRX_N3
AT13
SATA_PTX_DRX_P3
BD13
BB13
AV15
AW15
BC14
SATA_PRX_DTX_N5
BE14
SATA_PRX_DTX_P5
AP15
SATA_PTX_DRX_N5
AR15
SATA_PTX_DRX_P5
AY5
SATA_COMP
AP3
SATA_ACT#
AT1
SG_IN
AU2
FN9
BD4
SATA_IREF
BA2
TP9
BB2
TP8
CAD note:
Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.
RH42 0_0402_5%RH42 0_0402_5%
SATA_COMP
1 2
R463 10K_0402_5%R463 10K_0402_5%
SATA_ACT# [33,39]
1 2
1 2
T72PAD~D @T72PAD~D @
RH497.5K_0402_1% RH497.5K_0402_1%
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
SATA_PRX_DTX_N0 [23]
SATA_PRX_DTX_P0 [23]
SATA_PTX_DRX_N0 [23]
SATA_PTX_DRX_P0 [23]
SATA_PRX_DTX_N1 [23]
SATA_PRX_DTX_P1 [23]
SATA_PTX_DRX_N1 [23]
SATA_PTX_DRX_P1 [23]
SATA_PRX_DTX_N2 [33]
SATA_PRX_DTX_P2 [33]
SATA_PTX_DRX_N2 [33]
SATA_PTX_DRX_P2 [33]
SATA_PRX_DTX_N3 [33]
SATA_PRX_DTX_P3 [33]
SATA_PTX_DRX_N3 [33]
SATA_PTX_DRX_P3 [33]
SATA_PRX_DTX_N5 [23]
SATA_PRX_DTX_P5 [23]
SATA_PTX_DRX_N5 [23]
SATA_PTX_DRX_P5 [23]
SG_IN [22]
+1.5VS
+3VS
PLT_RST#[14,25,28,29,30,35,37,39,5]
+1.5VS
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
PCH-RTC,HDA,SATA,XDP
PCH-RTC,HDA,SATA,XDP
PCH-RTC,HDA,SATA,XDP
1
+3VS
RH237
RH237
1 2
10K_0402_5%
10K_0402_5%
LA-9241P
LA-9241P
LA-9241P
1
2
G
G
mSATA
HDD
ODD
DOCK_SATA5
DOCK_SATA3
+3VS
12
12
UMA@
UMA@
13
D
D
Q70
Q70
2N7002KW_SOT323-3
2N7002KW_SOT323-3
S
S
13 56Thursday, December 20, 2012
13 56Thursday, December 20, 2012
13 56Thursday, December 20, 2012
10K_0402_5%
10K_0402_5%
R7
R7
10K_0402_5%
10K_0402_5%
R8
R8
0.5
0.5
0.5
CyberForum.ru
5
3V_PCH
+
X
1 2
R
R
H63 10K_ 0402_5%
H63 10K_ 0402_5%
1 2
R
R
H64 10K_ 0402_5%
H64 10K_ 0402_5%
1 2
H72 10K_ 0402_5%
H72 10K_ 0402_5%
R
D D
C C
B B
11/06 Change PCH.D2 pin connection to DDR3_SET
A A
R
1 2
R
R
H75 10K_ 0402_5%
H75 10K_ 0402_5%
10/26 change RH75.2 connection to BATLOW#
+
3VS
1 2
RH78 8.2K _0402_5%RH78 8.2K _0402_5%
1 2
RH70 200 K_0402_5%RH70 200 K_0402_5%
10/25 Change RH70 to 200K
DMI_CTX_PRX _N0[4]
DMI_CTX_PRX _N1[4]
DMI_CTX_PRX _N2[4]
DMI_CTX_PRX _N3[4]
DMI_CTX_PRX _P0[4]
DMI_CTX_PRX _P1[4]
DMI_CTX_PRX _P2[4]
DMI_CTX_PRX _P3[4]
DMI_CRX_P TX_N0[4]
DMI_CRX_P TX_N1[4]
DMI_CRX_P TX_N2[4]
DMI_CRX_P TX_N3[4]
DMI_CRX_P TX_P0[4] FDI_CSYNC [4]
DMI_CRX_P TX_P1[4]
DMI_CRX_P TX_P2[4]
DMI_CRX_P TX_P3[4]
+1.5VS
+1.5VS
09/11 Delete RH92, RH93, RH221, RH94, RH95
PM_PWR OK[30,5 ]
PCH_PW ROK_R[31]
PM_APW ROK[30,31]
PM_DRAM_P WRGD[5]
PM_RSMRST#[30]
SUS_PW R_ACK[30 ]
ON/OFFBTN#[30,5]
AC_PRES_ OUT[30,35]
BATLOW#[3 0]
DDR3_SET[45]
US_PWR _ACK
S
CH_PCIE_W AKE#
P
P
CH_RI#
ATLOW#
B
PM_CLKRUN#
SLP_LAN #
DMI_CTX_PRX _N0
DMI_CTX_PRX _N1
DMI_CTX_PRX _N2
DMI_CTX_PRX _N3
DMI_CTX_PRX _P0
DMI_CTX_PRX _P1
DMI_CTX_PRX _P2
DMI_CTX_PRX _P3
DMI_CRX_P TX_N0
DMI_CRX_P TX_N1
DMI_CRX_P TX_N2
DMI_CRX_P TX_N3
DMI_CRX_P TX_P0
DMI_CRX_P TX_P1
DMI_CRX_P TX_P2
DMI_CRX_P TX_P3
1 2
RH88 0_04 02_5%RH8 8 0_0402_5 %
RH90 7.5K _0402_1%RH90 7.5K _0402_1%
10/16 Delete R230
SYS_RESE T#
PCH_PW ROK_R
RH97 0_040 2_5%RH97 0_0402 _5%
ON/OFFBTN#
AC_PRES_ OUT
BATLOW#
10/26 change PCH.K7 connection to BATLOW#
PCH_RI#
DDR3_SET
DMI_IREF
1 2
1 2
ME_SUS_P WR_ACK_R
T90 PAD~D@ T90 PAD~D@
08/10 Change RH235 to 0ohms
DP_DBRES ET#[5]
08/10 Add RH245
10/12 Delete RH245. Add UH6, CH116
10/12 Delete VCC1_PWRGD connection to UH6.1 and 2. Then add R613
between +3VDS and UH6 pin 1,2. change UH6.5 pin connection to +3VDS
10/18 install R613, CH116 and UH6. Uninstall RH67
10/18 Uninstall R613, CH116 and UH6. Install RH68
12/12 Delete UH6, R613 and CH116
LPT_PCH_M_EDS
UH1B
UH1B
AW22
DMI_RXN_0
AR20
DMI_RXN_1
AP17
DMI_RXN_2
AV20
DMI_RXN_3
AY22
DMI_RXP_0
AP20
DMI_RXP_1
AR17
DMI_RXP_2
AW20
DMI_RXP_3
BD21
DMI_TXN_0
BE20
DMI_TXN_1
BD17
DMI_TXN_2
BE18
DMI_TXN_3
BB21
DMI_TXP_0
BC20
DMI_TXP_1
BB17
DMI_TXP_2
BC18
DMI_TXP_3
BE16
DMI_IREF
AW17
TP12
AV17
TP7
DMI_RCOMP
AY17
DMI_RCOMP
R6
SUSACK#
10/17 Change R614.1 connection to +3V_PCH
10/18 Change R614 to 10K ohms, and connection R614.1 to PM_RSMRST#
10/23 Uninstall Q79, R614
12/12 Delete Q79, R615
SUSACK#
AM1
SYS_RESET#
AD7
SYS_PWROK
F10
PWROK
AB7
APWROK
H3
DRAMPWROK
J2
RSMRST#
J4
SUSWARN#/SUSPWRNACK/GPIO30
K1
PWRBTN#
E6
ACPRESENT/GPIO31
K7
BATLOW#/GPIO72
N4
RI#
AB10
TP21
D2
SLP_WLAN#/GPIO29
LYNXPOINT_B GA695
LYNXPOINT_B GA695
08/10 Change UH7.5 connection to +3V_PCH power rail
LPT_PCH_M_EDS
DMI
DMI
System Power
System Power
Management
Management
4 OF 11
4 OF 11
4
1 2
R
R
H54 0_04 02_5%
H54 0_04 02_5%
P
CH_DPWR OK
REV = 5
REV = 5
FDI
FDI
H67 0_04 02_5%
H67 0_04 02_5%
R
R
FDI_RXN_0
FDI_RXN_1
FDI_RXP_0
FDI_RXP_1
FDI_CSYNC
FDI_IREF
FDI_RCOMP
DSWVRMEN
DPWROK
CLKRUN#
SUS_STAT#/GPIO61
SUSCLK/GPIO62
SLP_S5#/GPIO63
SLP_SUS#
PMSYNCH
SLP_LAN#
S
YS_RESET#
1 2
P
M_RSMRST#
AJ35
FDI_CTX_PRX _N0
AL35
FDI_CTX_PRX _N1
AJ36
FDI_CTX_PRX _P0
AL36
FDI_CTX_PRX _P1
AV43
TP16
AY45
TP5
AV45
TP15
AW44
TP10
AL39
FDI_CSYNC
AL40
FDI_INT
WAKE#
SLP_S4#
SLP_S3#
SLP_A#
FDI_INT
TP17
TP13
AT45
AU42
AU44
AR44
C8
L13
K3
AN7
U7
Y6
Y7
C6
H1
F3
F1
AY3
G5
SLP_LAN #_R
1 2
FDI_IREF
RH86 0_04 02_5%RH8 6 0_0402_5 %
FDI_RCOMP
DSWODV REN
PCH_DPW ROK
PCH_PCIE_ WAKE#
PM_CLKRUN #
10/26 change PCH.U7 connection to BT_OFF
BT_OFF DGPU_HOL D_RST#
SUSCLK_K BC
SLP_S5#
SLP_S4#
SLP_S3#
SIO_SLP _A#
SIO_SLP _SUS#
H_PM_SYNC
1 2
RH247 10K_0 402_5%RH247 10K_ 0402_5%
10/25 Add R247
Boot BIOS Strap
PCH_GPIO51
SATA1GP/
GPIO19
00 LPC
0 1 Reserved (NAND)
1 0
FDI_CTX_PRX _N0 [7]
FDI_CTX_PRX _N1 [7]
FDI_CTX_PRX _P0 [7]
FDI_CTX_PRX _P1 [7]
FDI_INT [4]
+1.5VS
12
+1.5VS
RH897. 5K_0402_1 % RH897 .5K_0402_ 1%
PCH_PCIE_ WAKE# [25]
PM_CLKRUN # [28, 30,32]
BT_OFF [25]
SUSCLK_K BC [30]
T85 PAD~D @T85 PAD~D@
T86 PA D~D
T86 PA D~D
SLP_S4# [45]
SLP_S3# [30,31 ,34,45]
SIO_SLP _A# [3 0,31,46]
T88 PA D~D
T88 PA D~D
SIO_SLP _SUS#
T89 PAD~D
T89 PAD~D
H_PM_SYNC [5]
SLP_LAN #
Boot BIOS Location
PCI
P
CH_RTCRST#[13 ]
07/20 Add ME debug circuit
@
@
@
@
@
@
SLP_LA N# [29 ,30]
3
+
3VDS
ME1
ME1
J
J
1
1
S
LP_S3#
S
LP_S5#
S
LP_S4#
IO_SLP_ A#
S
P
CH_RTCRST#
O
N/OFFBTN#
YS_RESET#
S
PCH_CRT_BL U[36]
PCH_CRT_GRN[36]
PCH_CRT_RED[36]
PCH_CRT_DDC_ CLK[36]
PCH_CRT_DDC_ DAT[36]
PCH_CRT_HSYNC[36]
PCH_CRT_VS YNC[36 ]
DGPU_HOL D_RST#[35]
+3VS
09/20 Change to +3VS
07/18 Delete PCH_GPIO55 PD RH186.
07/23 Add CR_SX_WARN# off page symbol
10/23 Change net name to TBT_RR_GPIO#
07/18 Add QH12 to invertion PCH_GPIO55 signal
07/23 Move QH12 to S/B.
2
3
4
5
6
7
8
9
10
11
12
13
14
FCI_1005 1922-1410E LF
FCI_1005 1922-1410E LF
CONN@
CONN@
DSWODVREN - ON DIE DSW VR ENABLE
1 2
RH84 20_ 0402_1%RH84 20_0402 _1%
1 2
RH85 20_ 0402_1%RH85 20_0402 _1%
1 2
RH87 649 _0402_1%RH87 649 _0402_1%
BKL_PW M_PCH[3 5]
PANEL_B KEN_PCH[35 ]
ENVDD_PCH[35 ]
DGPU_SEL ECT#[35,36]
DGPU_PW R_EN[15 ,35]
TBT_RR_GPIO#[3 9]
1 2
RH147 100K_0402_5%RH147 100K_0402_5%
Camera_ON[22]
2
3
4
5
6
16
7
G
2
15
8
G
1
9
0
1
1
1
1
2
1
3
1
4
HIGH = ENABLED (DEFAULT)
LOW = DISABLED
PCH_CRT_BL U
PCH_CRT_GRN
PCH_CRT_RED
PCH_CRT_DDC_ CLK
PCH_CRT_DDC_ DAT
DGPU_SELECT#
DGPU_PW R_EN
T45
VGA_BLUE
U44
VGA_GREEN
V45
VGA_RED
M43
VGA_DDC_CLK
M45
VGA_DDC_DATA
HSYNC
VSYNC
CRT_IREF
N42
VGA_HSYNC
N44
VGA_VSYNC
U40
DAC_IREF
U39
VGA_IRTN
N36
BKL_PW M_PCH
ENVDD_PCH
PCI_PIRQA #
PCI_PIRQB #
PCI_PIRQC #
PCI_PIRQD #
PCH_GPIO 51
Camera_ON
TBT_RR_GPIO#
EDP_BKLTCTL
K36
EDP_BKLTEN
G36
EDP_VDDEN
H20
PIRQA#
L20
PIRQB#
K17
PIRQC#
M20
PIRQD#
A12
GPIO50
B13
GPIO52
C12
GPIO54
C10
GPIO51
A10
GPIO53
AL6
GPIO55
LYNXPOINT_B GA695
LYNXPOINT_B GA695
10/25 Delete RH98, RH99, RH100. Add RP9
RH101 100K_0402_5%RH101 100K_0402_5%
RP9
RP9
18
27
36
45
150_120 6_8P4R_1%
150_120 6_8P4R_1%
1 2
2
STP_A16OVR
LPT_PCH_M_EV
LPT_PCH_M_EV
LVDSCRT
LVDSCRT
PCH_CRT_BL U
PCH_CRT_GRN
PCH_CRT_RED
ENVDD_PCH
PCI
PCI
5 OF 11
5 OF 11
A16 SWAP OVERRIDE STRAP
LOW = A16 SWAP OVERRIDE
HIGH = DEFAULT
REV = 5UH1E
REV = 5UH1E
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPB_AUXN
DDPC_AUXN
DDPD_AUXN
DISPLAY
DISPLAY
DDPB_AUXP
DDPC_AUXP
DDPD_AUXP
DDPB_HPD
DDPC_HPD
DDPD_HPD
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
PME#
PLTRST#
PLTRST#
MC74VHC1G 08DFT2G_SC70 -5
MC74VHC1G 08DFT2G_SC70 -5
07/23 Connection RH55.2 to +RTCVCC
RTCVCC
+
330K_0402_5%
330K_0402_5%
1 2
07/31 Correct netname
D
SWODVR EN
10/25 Delete RH66, RH69, RH71. Add RP8
09/20 Change RH74 to 100k
R40
R39
R35
R36
N40
N38
H45
K43
J42
H43
K45
J44
K40
K38
H39
07/06 Correct netname to follow GPIO table
G17
PWRSV _SEL#
F17
ODD_DA#
L15
NMI_SMI_DB G#
M15
ACCEL_INT_ R#
AD10
T87 PAD~D@ T87 PAD~D@
Y11
PLTRST#
08/10 Change UH3.5 connection to +3V_PCH power rail
+3V_PCH
CH20
CH20
1 2
0.1U_040 2_16V4Z
0.1U_040 2_16V4Z
5
UH3
UH3
1
IN1
VCC
OUT
2
IN2
GND
3
10/25 Delete RH56, RH57, RH59, RH60. Add RP7
P
CI_PIRQC#
P
CI_PIRQA#
CI_PIRQB#
P
P
RH55
RH55
4
CI_PIRQD#
P
WRSV_S EL#
D
GPU_PW R_EN
D
GPU_HOLD _RST#
O
DD_DA#
NMI_SMI_DB G#
PCH_CRT_DDC_ CLK
PCH_CRT_DDC_ DAT
DGPU_SEL ECT#
Camera_ON
ACCEL_INT_ R#
TBT_RR_GPIO #
07/23 Add CR_SX_WARN# PU RH244
10/23 Change netname to TBT_RR_GPIO#
PWRSV _SEL# [37]
ODD_DA# [23]
NMI_SMI_DB G# [30]
12
RH960_0 402_5% RH960 _0402_5%
PLT_RST#
1
@
@
CH107
CH107
22P_040 2_50V8J
22P_040 2_50V8J
2
07/16 Add for ESD's request
PLT_RST# [13,2 5,28,29,30 ,35,37,39,5 ]
1
R
R
8.2K_8P 4R_5%
8.2K_8P 4R_5%
R
R
1 8
2 7
3 6
4 5
10K_8P4 R_5%
10K_8P4 R_5%
1 2
ACCEL_INT# [28]
+
P7
P7
P8
P8
3VS
18
27
36
45
12
R
R
H6210K_0 402_5%
H6210K_0 402_5%
RH74100K_0402 _5% RH74100K_0402 _5%
12
RH762.2 K_0402_5% RH762.2 K_0402_5%
12
RH772.2 K_0402_5% RH772.2 K_0402_5%
12
RH8010K_ 0402_5% RH8010K_0402_5 %
12
RH8210K_ 0402_5% RH8 210K_0402_ 5%
12
RH838.2K _0402_5% RH838.2K_040 2_5%
12
RH24410K_0402 _5% RH24410K_0402 _5%
11 SPI
Security Classification
Security Classification
9/13 Delete UH7, RH235. Move RH236, CH106 to page 31
5
4
3
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
2012/03/23 2011/06/29
2012/03/23 2011/06/29
2012/03/23 2011/06/29
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Numb er Rev
Size Document Numb er Rev
Size Document Numb er Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH -DMI,FDI,PM,DP,CRT
PCH -DMI,FDI,PM,DP,CRT
PCH -DMI,FDI,PM,DP,CRT
LA-9241P
LA-9241P
LA-9241P
1
of
14 56Thursday, December 20, 2012
14 56Thursday, December 20, 2012
14 56Thursday, December 20, 2012
0.5
0.5
0.5
CyberForum.ru
5
D D
4
3
2
10K_0402_5%
10K_0402_5%
1
3V_PCH
+
RH106
RH106
1 2
G
FX_CLK_REQ#
07/23 Delete FN14 and FN15 off page symbol
09/11 Delete RH107, RH103, RH203, RH114, RH116,
RH205, RH122, RH124, RH126, RH127, RH128, RH130
+3V_PCH
CLK_PCIE_CR#[39]
CLK_PCIE_CR[39]
+3VS
CR_CLK_REQ#[39]
CLK_TB_REFCLK#[39]
CLK_TB_REFCLK[39]
+3VS
C C
B B
TB_CLKREQ#[39]
+3V_PCH
CLK_PCIE_EXP#[39]
CLK_PCIE_EXP[39]
CLKREQ_EXP#[39]
+3V_PCH
CLK_PCIE_LAN#[29]
CLK_PCIE_LAN[29]
CLK_PCIE_LAN_REQ1#[29]
CLK_PCI_DEBUG_KBC[30]
CLK_PCI_DEBUG[25]
+3V_PCH
CLK_PCIE_MINI1#[25]
CLK_PCIE_MINI1[25]
+3V_PCH
MINI1_CLKREQ#[25]
CLK_PCI_KBC[30]
CLK_PCI_SIO[32]
CLK_PCI_TPM[28]
RH104 10K_0402_5%RH104 10K_0402_5%
RH105 10K_0402_5%RH105 10K_0402_5%
RH113 10K_0402_5%RH113 10K_0402_5%
RH118 10K_0402_5%RH118 10K_0402_5%
+3V_PCH
RH121 10K_0402_5%RH121 10K_0402_5%
RH125 10K_0402_5%RH125 10K_0402_5%
RH128 10K_0402_5%RH128 10K_0402_5%
RH131 10K_0402_5%RH131 10K_0402_5%
RH135 10_0402_5%RH135 10_0402_5%
RH137 10_0402_5%RH137 10_0402_5%
RH138 22_0402_5%RH138 22_0402_5%
10/25 Delete RH141, RH234, RH139. Add RP10.
12
12
12
12
12
12
12
12
12
12
12
RP10
RP10
18
27
36
45
22_1206_8P4R_5%
22_1206_8P4R_5%
CLKREQ_EXP#
CLK_PCIE_LAN_REQ1#
MINI1_CLKREQ#
CLK_PCI0
PCI_LOOPBACKOUTCLK_PCI_LOOPBACK
CLK_PCI2
CLK_PCI4
UH1C
UH1C
Y43
CLKOUT_PCIE_N_0
Y45
CLKOUT_PCIE_P_0
AB1
PCIECLKRQ0#/GPIO73
AA44
CLKOUT_PCIE_N_1
AA42
CLKOUT_PCIE_P_1
AF1
PCIECLKRQ1#/GPIO18
AB43
CLKOUT_PCIE_N_2
AB45
CLKOUT_PCIE_P_2
AF3
PCIECLKRQ2#/GPIO20/SMI#
AD43
CLKOUT_PCIE_N_3
AD45
CLKOUT_PCIE_P_3
T3
PCIECLKRQ3#/GPIO25
AF43
CLKOUT_PCIE_N_4
AF45
CLKOUT_PCIE_P_4
V3
PCIECLKRQ4#/GPIO26
AE44
CLKOUT_PCIE_N5
AE42
CLKOUT_PCIE_P_5
AA2
PCIECLKRQ5#/GPIO44
AB40
CLKOUT_PCIE_N_6
AB39
CLKOUT_PCIE_P_6
AE4
PCIECLKRQ6#/GPIO45
AJ44
CLKOUT_PCIE_N_7
AJ42
CLKOUT_PCIE_P_7
Y3
PCIECLKRQ7#/GPIO46
AH43
CLKOUT_ITPXDP
AH45
CLKOUT_ITPXDP_P
D44
CLKOUT_33MHZ0
E44
CLKOUT_33MHZ1
B42
CLKOUT_33MHZ2
F41
CLKOUT_33MHZ3
A40
CLKOUT_33MHZ4
CLOCK SIGNAL
CLOCK SIGNAL
PCIECLK REQ Pull UP Power Rail:
SUS Rail : 0 3 4 5 6 7
Core Rail: 1 2
A A
LPT_PCH_M_EDS
LPT_PCH_M_EDS
LYNXPOINT_BGA695
LYNXPOINT_BGA695
2 OF 11
2 OF 11
REV = 5
REV = 5
CLKOUT_PEG_A
CLKOUT_PEG_A_P
PEGA_CLKRQ#/GPIO47
CLKOUT_PEG_B
CLKOUT_PEG_B_P
PEGB_CLKRQ#/GPIO56
CLKOUT_DMI
CLKOUT_DMI_P
CLKOUT_DP
CLKOUT_DP_P
CLKOUT_DPNS
CLKOUT_DPNS_P
CLKIN_DMI
CLKIN_DMI_P
CLKIN_GND
CLKIN_GND_P
CLKIN_DOT96N
CLKIN_DOT96P
CLKIN_SATA
CLKIN_SATA_P
REFCLK14IN
CLKIN_33MHZLOOPBACK
XTAL25_IN
XTAL25_OUT
CLKOUTFLEX0/GPIO64
CLKOUTFLEX1/GPIO65
CLKOUTFLEX2/GPIO66
CLKOUTFLEX3/GPIO67
ICLK_IREF
DIFFCLK_BIASREF
TP19
TP18
AB35
CLK_PCIE_VGA#
AB36
CLK_PCIE_VGA
AF6
GFX_CLK_REQ#
Y39
Y38
U4
WLAN_TRAMSIT_OFF#
AF39
CLK_CPU_DMI#
AF40
CLK_CPU_DMI
AJ40
CLK_CPU_SSC_DPLL#
AJ39
CLK_CPU_SSC_DPLL
AF35
CLK_CPU_DPLL#
AF36
CLK_CPU_DPLL
AY24
CLK_BUF_DMI#
AW24
CLK_BUF_DMI
AR24
CLK_BUF_BCLK#
AT24
CLK_BUF_BCLK
H33
CLK_BUF_DOT96#
G33
CLK_BUF_DOT96
BE6
CLK_BUF_CKSSCD#
BC6
CLK_BUF_CKSSCD
F45
CLK_PCH_14M
D17
CLK_PCI_LOOPBACK
08/06 Change ball name
AM43
AL44
C40
F38
SIO_14M
F36
F39
AM45
ICLK_IREF
AD39
AD38
AN44
PCH_CLK_BIASREF
CLK_PCIE_VGA# [35]
CLK_PCIE_VGA [35]
RH109
RH109
12
10K_0402_5%
10K_0402_5%
WLAN_TRAMSIT_OFF# [25]
CLK_CPU_DMI# [5]
CLK_CPU_DMI [5]
CLK_CPU_SSC_DPLL# [5]
CLK_CPU_SSC_DPLL [5]
CLK_CPU_DPLL# [5]
CLK_CPU_DPLL [5]
T91PAD~D @T91PAD~D @
T92PAD~D @T92PAD~D @
1 2
1 2
12
RH1400_0402_5% RH1400_0402_5%
RH1427.5K_0402_1% RH1427.5K_0402_1%
RH136 22_0402_5%RH136 22_0402_5%
+3V_PCH
07/06 Follow HP's GPIO table
XTAL25_IN
XTAL25_OUT
CLK_SIO_14M [32]
+1.5VS
+1.5VS
2
1 3
D
D
Q55
Q55
DGPU_PWR_EN [14,35]
G
G
2N7002KW_SOT323-3
2N7002KW_SOT323-3
S
S
10/25 Delete RH108, RH110, RH111, RH112. Add RP11
CLK_BUF_DMI
CLK_BUF_DMI#
CLK_BUF_BCLK
CLK_BUF_BCLK#
CLK_BUF_DOT96#
CLK_BUF_DOT96
CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD
CLK_PCH_14M
PEG_CLK_REQ# [35]
11/01 Change YH2 to
small package
18P_0402_50V8J
18P_0402_50V8J
RP11
RP11
1 8
2 7
3 6
4 5
10K_8P4R_5%
10K_8P4R_5%
1 2
RH115 10K_0402_5%R H115 10K_0402_5%
1 2
RH117 10K_0402_5%R H117 10K_0402_5%
1 2
RH119 10K_0402_5%R H119 10K_0402_5%
1 2
RH120 10K_0402_5%R H120 10K_0402_5%
1 2
RH123 10K_0402_5%R H123 10K_0402_5%
RH132 1M _0402_5%RH1 32 1M_0402_5%
3
4
25MHZ_20PF_5YEA2500020BIF50Q3
25MHZ_20PF_5YEA2500020BIF50Q3
1
CH21
CH21
2
1 2
YH2
YH2
OUT
NC
1
IN
2
NC
18P_0402_50V8J
18P_0402_50V8J
1
CH22
CH22
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2012/03/23 2011/06/29
2012/03/23 2011/06/29
2012/03/23 2011/06/29
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
CLOCK TERMINATION for FCIM and need close to PCH
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PCH- CLK
PCH- CLK
PCH- CLK
LA-9241P
LA-9241P
LA-9241P
1
15 56Thursday, December 20, 2012
15 56Thursday, December 20, 2012
15 56Thursday, December 20, 2012
0.5
0.5
0.5
CyberForum.ru
5
D D
3VS
+
1 2
RH145 10K_0402_5 %RH1 45 10K_0402_5%
C C
PCH_SPI_CLK[30]
PCH_SPI_CS0#[30]
PCH_SPI_SI[30]
PCH_SPI_SO[30]
PCH_SPI_WP#[30]
PCH_SPI_HOLD#[30]
B B
SIRQ
1 2
1 2
1 2
1 2
1
CH113
22P_0402_50V8J
22P_0402_50V8J
2
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
SIRQ
PCH_SPI_CLK_R
PCH_SPI_CS0#_R
12
PCH_SPI_SI_R
12
PCH_SPI_SO_R
PCH_SPI_WP#_RPCH_SPI_WP#
07/09 Delete by HP request.
LPC_LAD0[25,28,30,32]
LPC_LAD1[25,28,30,32]
LPC_LAD2[25,28,30,32]
LPC_LAD3[25,28,30,32]
LPC_LFRAME#[25,28,30,32]
LPC_LDRQ0#[32]
SIRQ[28,30,32]
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_SI
PCH_SPI_SO
PCH_SPI_HOLD# PCH_SPI_HOLD#_R
07/30 Add CH113 by RF request.
RH154 5_0402_1%RH154 5_0402_1%
RH155 5_0402_1%RH155 5_0402_1%
RH156 5_0402_1%RH156 5_0402_1%
RH157 5_0402_1%RH157 5_0402_1%
RH242 15_0402_5%RH242 15_0402_5%
RH243 15_0402_5%RH243 15_0402_5%
07/19 Add RH242 and RH243
07/26 Install RH242 and RH244
PCH_SPI_CLK
@ CH113
@
4
A20
LAD_0
C20
LAD_1
A18
LAD_2
C18
LAD_3
B21
LFRAME#
D21
LDRQ0#
G20
LDRQ1#/GPIO23
AL11
SERIRQ
AJ11
SPI_CLK
AJ7
SPI_CS0#
AL7
SPI_CS1#
AJ10
SPI_CS2#
AH1
SPI_MOSI
AH3
SPI_MISO
AJ4
SPI_IO2
AJ2
SPI_IO3
LYNXPOINT_BGA695
LYNXPOINT_BGA695
M
EM_SMBCLK
M
EM_SMBDATA
SPILPC
SPILPC
LPT_PCH_M_EDS
LPT_PCH_M_EDS
SMBus
SMBus
C-Link
C-Link
Thermal
Thermal
3 OF 11
3 OF 11
2N7002DWH_SOT363-6
2N7002DWH_SOT363-6
3 4
2N7002DWH_SOT363-6
2N7002DWH_SOT363-6
QH3B
QH3B
REV = 5UH1D
REV = 5UH1D
SML1ALERT#/PCHHOT#/GPIO74
3VS
+
2
6 1
H3A
H3A
Q
Q
5
SMBALERT#/GPIO11
SMBDATA
SML0ALERT#/GPIO60
SML0CLK
SML0DATA
SML1CLK/GPIO58
SML1DATA/GPIO75
CL_DATA
CL_RST#
SMBCLK
CL_CLK
TD_IREF
3
DR_XDP_WAN_SM BCLK [11,12,13,28,38,5]
D
D
DR_XDP_WAN_SM BDAT [11,12,13,28,38,5]
N7
FPR_OFF
R10
MEM_SMBCLK
U11
MEM_SMBDATA
N8
DDR_RST_EN
U8
LAN_SMBCLK
R7
LAN_SMBDATA
H6
NFC_RST#
K6
SML1_SMBCLK
N11
SML1_SMBDATA
AF11
CL_CLK1
AF10
CL_DATA1
AF7
CL_RST1#
BA45
TP1
BC45
TP2
BE43
TP4
BE44
TP3
AY43
PCH_TD_IREF
1 2
RH158 8.2K_0402_1%RH158 8.2K_0402_1%
H1
H1
H_3P0
H_3P0
HOLEA
HOLEA
@
@
1
H27
H27
H_3P3
H_3P3
HOLEA
HOLEA
@
@
1
FPR_OFF [28]
DDR_RST_EN [5]
LAN_SMBCLK [29]
LAN_SMBDATA [29]
NFC_RST# [39]
07/06 Add for NFC function
CL_CLK1 [25]
CL_DATA1 [25]
CL_RST1# [25]
H2
H2
H6
H6
H_3P3
H_3P3
H_3P8
H_3P8
HOLEA
HOLEA
HOLEA
HOLEA
@
@
@
@
1
1
H28
H28
H29
H29
H_3P3
H_3P3
H_3P3
H_3P3
HOLEA
HOLEA
HOLEA
HOLEA
@
@
@
@
1
1
H7
H7
H_3P8
H_3P8
HOLEA
HOLEA
1
H30
H30
H_3P0
H_3P0
HOLEA
HOLEA
1
@
@
@
@
H8
H8
H_3P0
H_3P0
HOLEA
HOLEA
1
H31
H31
H_3P8
H_3P8
HOLEA
HOLEA
1
2
07/06 Add for NFC function
LAN_SMBCLK
LAN_SMBDATA
SML1_SMBCLK
SML1_SMBDATA
H9
H9
H_3P8
H_3P8
H_3P8
H_3P8
HOLEA
HOLEA
@
@
@
@
1
H33
H33
H_3P1N
H_3P1N
HOLEA
HOLEA
@
@
@
@
1
PR_OFF
F
M
EM_SMBCLK
M
08/07 Install RH148 and
change value to 2.2K
10/18 Uninstall RH148
07/06 Add for NFC function
10/09 Change to RH152, RH153 to 499ohms
11/09 Change RH152, RH153 to 2.2K ohms
2N7002DWH_SOT363-6
2N7002DWH_SOT363-6
3 4
2N7002DWH_SOT363-6
2N7002DWH_SOT363-6
2N7002DWH_SOT363-6
2N7002DWH_SOT363-6
H10
H10
H19
H19
H_4P8X3P8
H_4P8X3P8
HOLEA
HOLEA
HOLEA
HOLEA
@
@
@
@
1
1
H37
H37
H35
H35
H_3P0
H_3P0
H_3P8
H_3P8
HOLEA
HOLEA
HOLEA
HOLEA
@
@
@
@
1
1
EM_SMBDATA
D
DR_RST_EN
N
FC_RST#
S
ML1_SMBCLK
S
ML1_SMBDATA
LAN_SMBCLK
LAN_SMBDATA
+3VS +3VS +3VS
2
6 1
@
@
QH10A
QH10A
5
@
@
QH10B
QH10B
2N7002DWH_SOT363-6
2N7002DWH_SOT363-6
QH9B
QH9B
5
H21
H21
H20
H20
H_3P8
H_3P8
H_4P3
H_4P3
HOLEA
HOLEA
HOLEA
HOLEA
@
@
@
@
1
1
H40
H40
H38
H38
H_3P0
H_3P0
H_3P8
H_3P8
HOLEA
HOLEA
HOLEA
HOLEA
@
@
@
@
1
1
QH9A
QH9A
2
34
H_4P8X3P8
H_4P8X3P8
12
@
@
H22
H22
HOLEA
HOLEA
1
H42
H42
H_2P8
H_2P8
HOLEA
HOLEA
1
RH238
RH238
61
@
@
@
@
2.2K_0402_5%
2.2K_0402_5%
1 2
1 2
RH239
RH239
12
2.2K_0402_5%
2.2K_0402_5%
@
@
H24
H24
H_3P3
H_3P3
HOLEA
HOLEA
@
@
1
H43
H43
H_2P8
H_2P8
HOLEA
HOLEA
@
@
1
1
12
12
12
12
@
@
12
12
12
H25
H25
H_2P8
H_2P8
HOLEA
HOLEA
1
H44
H44
H_2P4X3P9N
H_2P4X3P9N
HOLEA
HOLEA
1
3V_PCH
+
H14310K_0402_5%
H14310K_0402_5%
R
R
R
R
H1442.2K_0402_5%
H1442.2K_0402_5%
R
R
H1462.2K_0402_5%
H1462.2K_0402_5%
R
R
H1482.2K_0402_5%
H1482.2K_0402_5%
R
R
H14910K_0402_5%
H14910K_0402_5%
H1502.2K_0402_5%
H1502.2K_0402_5%
R
R
R
R
H1512.2K_0402_5%
H1512.2K_0402_5%
+3VM_LAN
RH1522.2K_0402_5% RH1522.2K_0402_5%
RH1532.2K_0402_5% RH1532.2K_0402_5%
NFC_3S_SMBCLK [39]
NFC_3S_SMBDAT [39]
PCH_KBC_I2CLK [30,35]
PCH_KBC_I2CDAT [30,35]
H26
H26
H_3P3
H_3P3
HOLEA
HOLEA
@
@
@
@
1
H45
H45
H_3P8X4P8N
H_3P8X4P8N
HOLEA
HOLEA
@
@
@
@
1
+3V_PCH
+3V_PCH
ZZZ1
ZZZ1
PCB
PCB
MB
MB
H47
H47
H46
H46
H_3P0N
H_3P0N
H_3P8
H_3P8
HOLEA
HOLEA
HOLEA
HOLEA
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2012/03/23 2011/06/29
2012/03/23 2011/06/29
2012/03/23 2011/06/29
@
@
@
@
1
1
H49
H49
H48
H48
H_3P3
H_3P3
H_3P0N
H_3P0N
HOLEA
HOLEA
HOLEA
HOLEA
@
@
@
@
1
1
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
H50
H50
H_3P0
H_3P0
HOLEA
HOLEA
1
FD4
@
@
FD4
FIDUCIAL_C40M80
FIDUCIAL_C40M80
@
@
1
1
0.5
0.5
16 56Thursday, December 20, 2012
16 56Thursday, December 20, 2012
16 56Thursday, December 20, 2012
0.5
FD2
FD1
FD1
FIDUCIAL_C40M80
FIDUCIAL_C40M80
@
@
2
1
07/20 Modify screw hole
07/23 Modify screw hole
08/06 Delete H23
09/12 Delete H4, H32, H34, H41. Add H42, H43, H44, H45, H46
09/21 Add H47, H48
FD2
FIDUCIAL_C40M80
FIDUCIAL_C40M80
@
@
1
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
FD3
FD3
FIDUCIAL_C40M80
FIDUCIAL_C40M80
@
@
1
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
PCH - SPI, SMBUS,LPC
PCH - SPI, SMBUS,LPC
PCH - SPI, SMBUS,LPC
LA-9241P
LA-9241P
LA-9241P
CyberForum.ru
5
D D
07/17 Add by HP request.
PCIE_PRX_DTX_N1[39]
PCIE_PRX_DTX_P1[39]
PCIE_PTX_C_DRX_N1[39]
PCIE_PTX_C_DRX_P1[39]
PCIE_PRX_DTX_N2[39]
PCIE_PRX_DTX_P2[39]
PCIE_PTX_C_DRX_N2[39]
PCIE_PTX_C_DRX_P2[39]
PCIE_PRX_DTX_N3[39]
PCIE_PRX_DTX_P3[39]
PCIE_PTX_C_DRX_N3[39]
PCIE_PTX_C_DRX_P3[39]
PCIE_PRX_DTX_N4[39]
C C
Express card slot
GIGA LAN
WLAN
Card Reader
B B
PCIE_PRX_DTX_P4[39]
PCIE_PTX_C_DRX_N4[39]
PCIE_PTX_C_DRX_P4[39]
PCIE_PRX_EXPTX_N5[39]
PCIE_PRX_EXPTX_P5[39]
PCIE_PTX_EXPRX_N5[39]
PCIE_PTX_EXPRX_P5[39]
PCIE_PRX_DTX_N6[29]
PCIE_PRX_DTX_P6[29]
PCIE_PTX_C_DRX_N6[29]
PCIE_PTX_C_DRX_P6[29]
PCIE_PRX_DTX_N7[25]
PCIE_PRX_DTX_P7[25]
PCIE_PTX_C_DRX_N7[25]
PCIE_PTX_C_DRX_P7[25]
PCIE_PRX_DTX_N8[39]
PCIE_PRX_DTX_P8[39]
PCIE_PTX_C_DRX_N8[39]
PCIE_PTX_C_DRX_P8[39]
1 2
CH108 0.1U_0402_10V7KCH108 0.1U_0402_10V7K
1 2
CH109 0.1U_0402_10V7KCH109 0.1U_0402_10V7K
1 2
CH110 0.1U_0402_10V7KCH110 0.1U_0402_10V7K
1 2
CH111 0.1U_0402_10V7KCH111 0.1U_0402_10V7K
1 2
CH27 0.1U_0402_10V7KCH 27 0 .1U_0402_10V7K
1 2
CH28 0.1U_0402_10V7KCH 28 0 .1U_0402_10V7K
1 2
CH29 0.1U_0402_10V7KCH29 0.1U_0402_10V7K
1 2
CH30 0.1U_0402_10V7KCH30 0.1U_0402_10V7K
1 2
CH100 0.1U_0402_ 10V7KCH100 0.1U_0402_10V7K
1 2
CH99 0.1U_0402_10V7KCH99 0.1U_0402_10V7K
1 2
CH31 0.1U_0402_10V7KCH31 0.1U_0402_10V7K
1 2
CH32 0.1U_0402_10V7KCH32 0.1U_0402_10V7K
1 2
CH33 0.1U_0402_10V7KCH 33 0 .1U_0402_10V7K
1 2
CH34 0.1U_0402_10V7KCH 34 0 .1U_0402_10V7K
1 2
CH35 0.1U_0402_10V7KCH35 0.1U_0402_10V7K
1 2
CH36 0.1U_0402_10V7KCH36 0.1U_0402_10V7K
+1.5VS
+1.5VS
4
PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1
PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2
PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3
PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3
PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4
PCIE_PRX_EXPTX_N5
PCIE_PRX_EXPTX_P5
PCIE_PTX_EXPRX_N5_C
PCIE_PTX_EXPRX_P5_C
PCIE_PRX_DTX_N6
PCIE_PRX_DTX_P6
PCIE_PTX_DRX_N6
PCIE_PTX_DRX_P6
PCIE_PRX_DTX_N7
PCIE_PRX_DTX_P7
PCIE_PTX_DRX_N7
PCIE_PTX_DRX_P7
PCIE_PRX_DTX_N8
PCIE_PRX_DTX_P8
PCIE_PTX_DRX_N8
PCIE_PTX_DRX_P8
1 2
RH160 0_0402_5%RH160 0_0402_5%
1 2
RH164 7.5K_0402_1%RH164 7.5K_0402 _1%
PCH_PCIE_IREF
PCH_PCIE_RCOMP
AW31
PERN1/USB3RN3
AY31
PERP1/USB3RP3
BE32
PETN1/USB3TN3
BC32
PETP1/USB3TP3
AT31
PERN2/USB3RN4
AR31
PERP2/USB3RP4
BD33
PETN2/USB3TN4
BB33
PETP2/USB3TP4
AW33
PERN_3
AY33
PERP_3
BE34
PETN_3
BC34
PETP_3
AT33
PERN_4
AR33
PERP_4
BE36
PETN_4
BC36
PETP_4
AW36
PERN_5
AV36
PERP_5
BD37
PETN_5
BB37
PETP_5
AY38
PERN_6
AW38
PERP_6
BC38
PETN_6
BE38
PETP_6
AT40
PERN_7
AT39
PERP_7
BE40
PETN_7
BC40
PETP_7
AN38
PERN_8
AN39
PERP_8
BD42
PETN_8
BD41
PETP_8
BE30
PCIE_IREF
BC30
TP11
BB29
TP6
BD29
PCIE_RCOMP
LYNXPOINT_BGA695
LYNXPOINT_BGA695
LPT_PCH_M_EDS
LPT_PCH_M_EDS
PCIe
PCIe
9 OF 11
9 OF 11
3
REV = 5UH1I
REV = 5UH1I
USB
USB
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC6#/GPIO10
OC7#/GPIO14
USB2N0
USB2P0
USB2N1
USB2P1
USB2N2
USB2P2
USB2N3
USB2P3
USB2N4
USB2P4
USB2N5
USB2P5
USB2N6
USB2P6
USB2N7
USB2P7
USB2N8
USB2P8
USB2N9
USB2P9
USB2N10
USB2P10
USB2N11
USB2P11
USB2N12
USB2P12
USB2N13
USB2P13
USB3RN1
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USB3RN5
USB3RP5
USB3TN5
USB3TP5
USB3RN6
USB3RP6
USB3TN6
USB3TP6
USBRBIAS#
USBRBIAS
TP24
TP23
OC5#/GPIO9
B37
USBP0-
D37
USBP0+
A38
USBP1-
C38
USBP1+
A36
C36
A34
C34
B33
USBP4-
D33
USBP4+
F31
USBP5-
G31
USBP5+
K31
USBP6-
L31
USBP6+
G29
USBP7-
H29
USBP7+
A32
USBP8-
C32
USBP8+
A30
USBP9-
C30
USBP9+
B29
USBP10-
D29
USBP10+
A28
USBP11-
C28
USBP11+
G26
USBP12-
F26
USBP12+
F24
USBP13-
G24
USBP13+
AR26
USB3RN1
AP26
USB3RP1
BE24
USB3TN1
BD23
USB3TP1
AW26
USB3RN2
AV26
USB3RP2
BD25
USB3TN2
BC24
USB3TP2
AW29
USB3RN5
AV29
USB3RP5
BE26
USB3TN5
BC26
USB3TP5
AR29
USB3RN6
AP29
USB3RP6
BD27
USB3TN6
BE28
USB3TP6
K24
USBRBIAS
K26
M33
L33
P3
WWAN_DET #_PCH
V1
USB_OC1#_R
U2
USB_OC2#
P1
USB_OC3#
M3
USB_OC4#_R
T1
dGPU_HPD_INTR
N2
M1
USBP0- [33]
USBP0+ [33]
USBP1- [40]
USBP1+ [40]
USBP4- [39]
USBP4+ [39]
USBP5- [39]
USBP5+ [39]
USBP6- [39]
USBP6+ [39]
USBP7- [37]
USBP7+ [37]
USBP8- [28]
USBP8+ [28]
USBP9- [39]
USBP9+ [39]
USBP10- [22]
USBP10+ [22]
USBP11- [33]
USBP11+ [33]
USBP12- [25]
USBP12+ [25]
USBP13- [25]
USBP13+ [25]
USB3RN1 [33]
USB3RP1 [33]
USB3TN1 [33]
USB3TP1 [33]
USB3RN2 [40]
USB3RP2 [40]
USB3TN2 [40]
USB3TP2 [40]
USB3RN5 [39]
USB3RP5 [39]
USB3TN5 [39]
USB3TP5 [39]
USB3RN6 [39]
USB3RP6 [39]
USB3TN6 [39]
USB3TP6 [39]
10/26 Change PCH.P3 and RPH2.4 connection to WWAN_DET#_PCH
07/18 Change net name to TB_HOT_PLUG# follow HP request.
09/11 Delete RH165
2
----->Docking USB 3.0
----->USB 3.0 Walkup port 2
----->NA
----->NA
----->USB 3.0 Walkup port 3
----->USB 3.0 Walkup port 4
----->Express card slot
----->Smart card reader
----->Finger Print Reader
----->Walkup USB 2.0 port
----->USB Camera
----->Docking USB 2.0 port
----->WWAN
----->BT/WLAN Combo
----->Docking USB 3.0
----->USB 3.0 Walkup port 2
----->USB 3.0 Walkup port 3
----->USB 3.0 Walkup port 4
WWAN_DET #_PCH [25]
07/23 Delete off page symbol
dGPU_HPD_INTR [35]
LED_LINK_LAN#_R [29]
TB_HOT_PLUG# [39]
1
USBRBIAS
CAD NOTE:
Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15 mils.
09/11 Change RPH1.3
connection to TB_HOT_PLUG#
TB_HOT_PLUG#
LED_LINK_LAN#_R
WWAN_DET #_PCH
07/23 Modify pin define for layout smooth
12
USB_OC4#_R
USB_OC3#
10K_1206_8P4R_5%
10K_1206_8P4R_5%
dGPU_HPD_INTR
USB_OC2#
USB_OC1#_R
10K_1206_8P4R_5%
10K_1206_8P4R_5%
22.6_0402_1%
22.6_0402_1%
RH159
RH159
4 5
3 6
2 7
1 8
4 5
3 6
2 7
1 8
RPH1
RPH1
RPH2
RPH2
+3V_PCH
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2012/03/23 2011/06/29
2012/03/23 2011/06/29
2012/03/23 2011/06/29
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PCH-PCIE,USB
PCH-PCIE,USB
PCH-PCIE,USB
LA-9241P
LA-9241P
LA-9241P
1
17 56Thursday, December 20, 2012
17 56Thursday, December 20, 2012
17 56Thursday, December 20, 2012
0.5
0.5
0.5
CyberForum.ru
5
13
3VS
+
R
R
H167 10K_0402_5%
H167 10K_0402_5%
R
R
H169 100K_0402_5%
H169 100K_0402_5%
R
R
H171 10K_0402_5%
H171 10K_0402_5%
R
R
H175 8.2K_0402_5%
H175 8.2K_0402_5%
H177 10K_0402_5%
H177 10K_0402_5%
R
D D
C C
R
R
R
H172 10K_0402_5%
H172 10K_0402_5%
H173 10K_0402_5%
H173 10K_0402_5%
R
R
RH178 10K_0402_5%RH178 10K_0402_5%
RH240 10K_0402_5%RH240 10K_0402_5%
RH241 10K_0402_5%RH241 10K_0402_5%
+3V_PCH
RH182 10K_0402_5%RH182 10K_0402_5%
RH183 10K_0402_5%RH183 10K_0402_5%
RH184 10K_0402_5%
RH184 10K_0402_5%
RH185 10K_0402_5%RH185 10K_0402_5%
RH176 10K_0402_5%RH176 10K_0402_5%
+3VDS
RH248 100K_0402_5%RH248 100K_0402_5%
10/25 Add LANWAKE# PU RH248 to +3VDS
+3V_PCH
4.7K_0402_5%
4.7K_0402_5%
R
R
H193
H193
1 2
PCH_GPIO28
1K_0402_1%
1K_0402_1%
12
@
@
R
R
H194
H194
12
P
12
O
12
07/06 Add PU resistor
12
12
12
@
@
12
07/06 Change for NFC
07/23 Follow VBK10.
10/24 Install RH185
12
12
O
D
D
D
K
EC_SCI#
THERM_SCI#
WWA N_TRANSMIT_OFF#
PCH_GPIO24
PCH_GPIO8
LAN_DIS#
NFC_INT
FPR_LOCK#
1 2
1 2
1 2
1 2
1 2
1 2
1 2
10/24 Change RH176.2 connection to GND. Install RH176
CH_GPIO0
CP_OC#
DD_EN
GPU_PWROK
OCK_ID0
OCK_ID1
BC_SIO_RST#
LANWAKE#
O
CP_PWM_OUT[30]
07/23 Correct Net name
07/06 Follow HP's GPIO table
+3VS
2
G
G
WWA N_TRANSMIT_OFF#[25]
07/23 Delete PCH_GPIO24 off page symbol
07/23 Delete FN_CLK2 off page symbol
08/01 Change net name to mSATA_DET#
10/26 Change net name to PCH_GPIO_35
10/26 Change net name to PCH_GPIO_36
08/01 Change net name to Sec_HDD_DET
07/23 Delete PCH_GPIO37 off page symbol
07/06 Change for NFC
1 2
RH181 1K_0402_1%RH181 1K_0402_1%
1 2
RH180 100K_0402_5%RH180 100K_0402_5%
1 2
RH170 100K_0402_5%RH170 100K_0402_5%
582N7002KW_SOT323-3
582N7002KW_SOT323-3
Q
Q
D
D
S
S
C_SCI#[30]
E
DGPU_PWROK[35]
LANWAKE#[29]
FPR_LOCK#[28]
DGPU_PRSNT#[35]
D3E_WAKE#
KBC_SIO_RST#[30,32]
GPS_XMIT_OFF#[25]
PCH_GPIO15
PCH_GPIO_35
PCH_GPIO34
4
P
CH_GPIO0
CP_OC#
O
E
C_SCI#
HERM_SCI#
T
P
P
CH_GPIO8
AN_DIS#[29]
L
KBL_DET#[38]
NFC_INT[39]
ODD_EN[23]
08/01 Change net name to mSATA_DET#
10/26 Change RH180.2 connection to PCH_GPIO_35.
Change RH180.1 connection to +3VS
CH_GPIO8
L
AN_DIS#
CH_GPIO15
P
KBL_DET#
DGPU_PWROK
WWA N_TRANSMIT_OFF#
PCH_GPIO24
LANWAKE#
PCH_GPIO28
PCH_GPIO34
PCH_GPIO_35
PCH_GPIO_36
PCH_GPIO37
DOCK_ID0
DOCK_ID1
FPR_LOCK#
DGPU_PRSNT#
NFC_INT
ODD_EN
D3E_WAKE#
KBC_SIO_RST#
GPS_XMIT_OFF#
UH1F
UH1F
AT8
B
MBUSY#/GPIO0
F13
ACH1/GPIO1
T
A14
T
ACH2/GPIO6
G15
ACH3/GPIO7
T
Y1
G
PIO8
K13
L
AN_PHY_PWR_CTRL/GPIO12
AB11
PIO15
G
AN2
SATA4GP/GPIO16
C14
TACH0/GPIO17
BB4
SCLOCK/GPIO22
Y10
GPIO24
R11
GPIO27
AD11
GPIO28
AN6
GPIO34
AP1
GPIO35/NMI#
AT3
SATA2GP/GPIO36
AK1
SATA3GP/GPIO37
AT7
SLOAD/GPIO38
AM3
SDATAOUT0/GPIO39
AN4
SDATAOUT1/GPIO48
AK3
SATA5GP/GPIO49
U12
GPIO57
C16
TACH4/GPIO68
D13
TACH5/GPIO69
G13
TACH6/GPIO70
H15
TACH7/GPIO71
BE41
VSS
BE5
VSS
C45
VSS
A5
VSS
LYNXPOINT_BGA695
LYNXPOINT_BGA695
PT_PCH_M_EDS
PT_PCH_M_EDS
L
L
3
GPIO
GPIO
6 OF 11
6 OF 11
2
3VS
+
20GATE
REV = 5
REV = 5
CPU/Misc
CPU/Misc
AN10
T
P14
AY1
P
ECI
AT6
RCIN#
THRMTRIP#
AV3
AV1
AU4
N10
VSS
A2
VSS
A41
VSS
A43
VSS
A44
VSS
B1
VSS
B2
VSS
B44
VSS
B45
VSS
BA1
VSS
BC1
VSS
BD1
VSS
BD2
VSS
BD44
VSS
BD45
VSS
BE2
VSS
BE3
VSS
D1
VSS
E1
VSS
E45
VSS
A4
VSS
PROCPWRGD
PLTRST_PROC#
NCTF
NCTF
10/26 Delete A20GATE off page symbol
A
20GATE
RCIN#
H_CPUPWRGD
PCH_THERMTRIP#_R
CPU_PLTRST#
T
104PAD~D @T104PAD~D @
RCIN#
H_CPUPWRGD [5]
CPU_PLTRST# [5]
A
R
CIN#
10/29 Change RH179 to 100ohms
RH179 100_0402_5%RH179 100_0402_5%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
CH37
CH37
2
12
R
R
12
R
R
12
PCH_THERMTRIP#_R
H16610K_0402_5%
H16610K_0402_5%
H16810K_0402_5%
H16810K_0402_5%
+1.05VS
PCH_THERMTRIP#_R [24,35,5]
1
08/01 Change net name to Sec_HDD_DET
PLL ON DIE VR ENABLE
ENABLED - HIGH(DEFAULT)
B B
DISABLED - LOW
Config
USB X4,PCIEX8,SATAX6
GPIO16,49
11
+3VS
1 2
RH197 10K_0402_5%RH197 10K_0402_5%
RH199 10K_0402_5%RH199 10K_0402_5%
08/03 Delete RH201, RH202
12
KBL_DET#
DGPU_PRSNT#
SATA2GP/GPIO36 , SATA3GP/GPIO37 SAMPLED AT RISING EDGE OF PWROK.
WEAK INTERNAL PULL-DOWN.(WEAK INTERNAL PULL-DOWN IS DISABLED AFTER
PLRST_N DE-ASSERTS).
NOTE: THIS SIGNAL SHOLD NOT BE PULLED HIGH WHEN STRAP IS SAMPLED.
RH198 10K_0402_5%RH198 10K_0402_5%
RH200 10K_0402_5%RH200 10K_0402_5%
10/26 Change netname to PCH_GPIO_36
12
PCH_GPIO_36
12
PCH_GPIO37
01USB X6,PCIEX8,SATAX4
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2012/03/23 2011/06/29
2012/03/23 2011/06/29
2012/03/23 2011/06/29
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PCH -GPIO,MISC,NTFC
PCH -GPIO,MISC,NTFC
PCH -GPIO,MISC,NTFC
LA-9241P
LA-9241P
LA-9241P
1
18 56Thursday, December 20, 2012
18 56Thursday, December 20, 2012
18 56Thursday, December 20, 2012
0.5
0.5
0.5
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