Compal LA-9201P Schematics
A
B
C
D
E
MODEL NAME :
PCB NO :
BOM P/N :
LA-9201P
4619KO31L01
VAR00
4619K031L02
1 1
Dell/Compal Confidential
2 2
Mariner 14
Schematic Document
DISCRETE VGA N14P-GT and N14E-GE (optimus)
2012-06-06
3 3
Highlight the short pad for 0 ohm
CONN@ Connector Component
up@ Upsell
en@ Entry
Rev: 0.1
X76@ VARM(SAMSUNG,Hynix)
N14P@ N14P-GT
N14E@ N14E-GE
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
2011/06/02 2012/06/02
2011/06/02 2012/06/02
2011/06/02 2012/06/02
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Cover Page
Cover Page
Cover Page
LA-9201P
LA-9201P
LA-9201P
E
1 66Friday, August 10, 2012
1 66Friday, August 10, 2012
1 66Friday, August 10, 2012
0.1
0.1
0.1
A
B
C
D
E
FFS
eDP
Conn.
eDP MUX
PS8321
HDMI to LVDS SW
STDP6038
1 1
HDMI 1.3 In
HDMI 1.4a Out
Conn.
HDMI SW
TS3DV421
Re-driver
PS121
eDP MUX
PS8321
LVDS to eDP SW
STDP4028
HDMI MUX
PS8271
eDP
HDMI
DP1.2
HDMI
mini DP Conn.
PS8330
2 2
Mini Card #1(Half)
WLAN/WiMax
BT4.0+LE/WiGig
HDMI MUX
PS8271
DMC
Display MiniCard
Re-Driver
PS121
2-lane eDP
N14P-GT
N14E-GE
VRAM x 8
GDDR5
HDMI
HDMI
PEGx16
USB2.0
PCI-E 2.0
USB2.0
PCI-E 2.0
Gen 3
Intel
Haswell
Processor
4C 47W
Scoket G3
rPGA-947
Page 4, 5, 6, 7, 8, 9, 10
DMI x4
100MHz
5GT/s
Intel
Lynx Point
PCH
BGA 695 Balls
Memory Bus (DDRIII)
Dual Channel
1.35V DDRIII 1600 MHz
USB3.0
USB 2.0
USB3.0
USB 2.0
USB3.0
USB 2.0
USB2.0
USB2.0
USB Rediver
PS8713
USB Rediver
PS8713DP Rediver
USB Rediver
PS8713
LNG3DMTR
204pin DDRIII SO-DIMM x2
BANK 0, 1, 2, 3
Fan Control
EMC1412
Page 11, 12, 13, 14
USB 3.0/USB 2.0 Conn.
( USB Charger Port )
USB 3.0/USB 2.0 Conn.
USB 3.0/USB 2.0 Conn.
Digital Camera
( H264 Encode )
AlienFX/ELC
MAX7313ATG+T
CPU XDP
Conn.
SATA 3.0
3 3
RJ45
Conn.
LAN(GbE)
E2201 KILLER
PCI-E 2.0
SATA 3.0
SATA Rediver
PS8520BT
HDD Conn. 1
ODD Conn.
ODD Bay
2nd HDD
SATA 3.0 Mini Card #3(Full)
mSATA
TPA3111
sub-woofer 2W
9 in 1
Conn.
RTC conn.
Card Reader
RTS5209
SPI ROM
8MB
PCI-E 2.0
SPI
Page 16, 17, 18, 19, 20, 21, 22, 23
LPC Bus
HD Audio
Realtek
ALC3661
Power On/Off CKT.
ENE KC3810
ENE KB9012
Audio JacK
TI TAP3113D2
DC/DC Interface CKT.
Headphone Jack
Int. Speaker 2W *2
4 4
VPK MCU
Power Circuit DC/DC
VPK Borad
Touch PadInt.KBD
Headphone Jack
Digital MIC
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
2011/02/23 2012/02/23
2011/02/23 2012/02/23
2011/02/23 2012/02/23
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Block Diagram
Block Diagram
Block Diagram
LA-9201P
LA-9201P
LA-9201P
E
2 66Friday, August 10, 2012
2 66Friday, August 10, 2012
2 66Friday, August 10, 2012
0.1
0.1
0.1
A
Compal Confidential
Project Code : VAR00
File Name : LA-9201P
B
C
D
E
1 1
LA-XXXXP M/B
Camera
LS-XXXXP
POWER BUTTON/B
on/off SW
Led x 1
FFC
8 pin
44 pin
Coaxial
22 pin
Coaxial
LCD Panel
HDD
LS-XXXXP
INDICATOR+SPK/B
2 2
Led-HDD
Led-Wireless
Led-CapsLock
SPK
FFC
20pin
22 pin
LF-XXXXP
FPC
HDD in ODD Bay Cable
ODD
FFC
50 pin
KSI/KSO
30 pin
VPK Keyboard
LS-XXXXP
VPK Daughter/B
40 pin
FFC for VPK
VPK MAX7313
VPK or N/VPK
3 3
30 pin
N/VPK Keyboard
16 pin
FFC for N/VPK
LS-XXXXP
Touch Pad
TP LED/B
FFC
8 pin
Lid
FFC
16 pin
LS-XXXXP LS-XXXXP LS-XXXXP
Led x 6
Wire
12pin
LS-XXXXP
LOGO /B
Led x 2
WireWireWire
6pin 6pin6pin
Alien head badge/B Alien Slits-L Light/BAlien Slits-R Light/B
Led x 2Led x 2 Led x 2
4 4
Security Classification
Security Classification
Security Classification
2011/06/02 2012/06/02
2011/06/02 2012/06/02
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
2011/06/02 2012/06/02
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Block Diagram
Block Diagram
Block Diagram
E
0.1
0.1
0.1
3 66Friday, August 10, 2012
3 66Friday, August 10, 2012
3 66Friday, August 10, 2012
Board ID Table for AD channel
Vcc 3.3V +/- 5%
Board ID
0
1
2
3
4
5
6
7 NC
100K +/- 5%Ra
Rb V min
AD_BID
0 0 V
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
0.168 V
0.375 V 0.503 V
0.634 V
0.958 V
1.372 V
1.851 V 2.200 V
2.433 V
V typ
AD_BID
0 V 0.155 V
0.250 V
0.819 V
1.185 V
1.650 V
3.300 V
V
AD_BID
0.362 V
0.621 V
0.945 V
1.359 V
1.838 V
2.420 V
3.300 V
max
EC AD3
0x00-0x0C
0x0D-0x1C
0x1D-0x30
0x31-0x49
0x4A-0x69
0x6A-0x8E
0x8F-0xBB
0xBC-0xFF
A
BOARD ID Table
Board ID
0
1
2
3
4
5
6
7
PCB Revision
0.1 (SSI)
0.2 (PT)
0.3 (ST)
0.4 (QT)
1.0 (MP)
USB PORT#0DESTINATION
JUSB1(USB3.0 P1)
1
2
3
JUSB2(USB3.0 P2)
JUSB3(USB3.0 P3)
JUSB4(USB3.0 P4)
POWER STATES
Signal
State
S0 (Full ON) / M0
S5 (SOFT OFF) / M-OFF
SLP
S3#
HIGH
LOW HIGH
LOW
SLP
SLP
S4#
HIGH ON
LOW LOW LOW LOW ON
S5#
HIGH
S4
STATE#
HIGHHIGH
HIGH LOW ONS3 (Suspend to RAM) / M-OFF
LOW
Symbol Note :
: means Digital Ground
SLP
M#
HIGH
LOW ONLOW LOWS4 (Suspend to DISK) / M-OFF
ALWAYS
PLANE
SUS
PLANE
ON
OFF
RUN
PLANE
CLOCKS
ON ON
OFFOFF OFF
PM TABLE
+5VS
+5VALW
power
plane
OFFOFFON
OFFOFF
State
S0 ON
S3
S5 S4/AC
+3VALW
+3VLP
+3V_PCH
ON OFF
ON
+1.5V
ON
OFF
+3VS
+1.8VS
+1.5VS
+0.75VS
+3VMXM
+5VMXM
+VCCP
+VCCSA
+VCC_CORE
+1.5V_CPU_VDDQ
ONON
OFF
USB2.0
4
5
6
7
8
9 JESATA
10
11
12
13
1 1
CLKOUT_PCIE0
: means Analog Ground
DESTINATIONDIFFERENTIAL
MINI CARD-1 WLAN
FLEX CLOCKS DESTINATION
CLKOUTFLEX0
S5 S4/AC don't exist
None
OFF
SATA III
CLKOUT_PCIE1
MINI CARD-2 DMC
CLKOUTFLEX1
None
SATA0
CLKOUT_PCIE2
10/100/1G LAN
CLKOUTFLEX2
None
SATA1
CLK
CLKOUT_PCIE3
CARD READER
CLKOUTFLEX3
None
SATA2
CLKOUT_PCIE4
CLKOUT_PCIE5
CLKOUT_PCIE6
CLKOUT_PCIE7
CLKOUT_PEG_A
None
None
None
None
NV
CLKOUT
PCI0
PCI1
PCI2
PCI3
DESTINATION
PCH_LOOPBACK
EC
80port debug card
None
SATA3
SATA4
SATA5
OFF
OFF
DESTINATION
HDD1
None
ODD
mSATA
MINI CARD-1 WLAN
MINI CARD-2 MDC
PCI EXPRESS
Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6
Lane 7
Lane 8
JMINI1 (WLAN)
JMINI2 (DMC)
AlienFX/ELC
IR SENSOR
Bluetooth
None
eDP CAMERA
LVDS CAMERA
VPK K/B
DESTINATION
None
None
10/100/1G LAN
CARD READER
None
None
None
None
PCI4
None
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
2012/05/14 2013/05/13
2012/05/14 2013/05/13
2012/05/14 2013/05/13
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Notes List
Notes List
Notes List
LA-9201P
LA-9201P
LA-9201P
4 66Friday, August 1 0, 2012
4 66Friday, August 1 0, 2012
4 66Friday, August 1 0, 2012
0.1
0.1
0.1
5
4
3
2
1
D D
PEG_COMP
12
RC224.9_0402_1%~D
+VCOMP_OUT
CAD Note:
Trace width=12 mils ,Spacing=15mil
Max length= 400 mils.
Haswell rPGA EDS
JCPU1A
E23
PEG_RCOMP
DMI_CRX_PTX_N015
DMI_CRX_PTX_N115
DMI_CRX_PTX_N215
DMI_CRX_PTX_N315
DMI_CRX_PTX_P015
DMI_CRX_PTX_P115
DMI_CRX_PTX_P215
DMI_CRX_PTX_P315
DMI_CTX_PRX_N015
DMI_CTX_PRX_N115
DMI_CTX_PRX_N215
C C
FDI_CSYNC15
FDI_INT15
B B
DMI_CTX_PRX_N315
DMI_CTX_PRX_P015
DMI_CTX_PRX_P115
DMI_CTX_PRX_P215
DMI_CTX_PRX_P315
RC3 0_0402_5%~D
RC87 0_0402_5%~D
12
12
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
FDI_CSYNC_R
FDI_INT_R
D21
C21
B21
A21
D20
C20
B20
A20
D18
C17
B17
A17
D17
C18
B18
A18
H29
J29
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
FDI_CSYNC
FDI_INT
PEG
DMI FDI
PEG_RXN_0
PEG_RXN_1
PEG_RXN_2
PEG_RXN_3
PEG_RXN_4
PEG_RXN_5
PEG_RXN_6
PEG_RXN_7
PEG_RXN_8
PEG_RXN_9
PEG_RXN_10
PEG_RXN_11
PEG_RXN_12
PEG_RXN_13
PEG_RXN_14
PEG_RXN_15
PEG_RXP_0
PEG_RXP_1
PEG_RXP_2
PEG_RXP_3
PEG_RXP_4
PEG_RXP_5
PEG_RXP_6
PEG_RXP_7
PEG_RXP_8
PEG_RXP_9
PEG_RXP_10
PEG_RXP_11
PEG_RXP_12
PEG_RXP_13
PEG_RXP_14
PEG_RXP_15
PEG_TXN_0
PEG_TXN_1
PEG_TXN_2
PEG_TXN_3
PEG_TXN_4
PEG_TXN_5
PEG_TXN_6
PEG_TXN_7
PEG_TXN_8
PEG_TXN_9
PEG_TXN_10
PEG_TXN_11
PEG_TXN_12
PEG_TXN_13
PEG_TXN_14
PEG_TXN_15
PEG_TXP_0
PEG_TXP_1
PEG_TXP_2
PEG_TXP_3
PEG_TXP_4
PEG_TXP_5
PEG_TXP_6
PEG_TXP_7
PEG_TXP_8
PEG_TXP_9
PEG_TXP_10
PEG_TXP_11
PEG_TXP_12
PEG_TXP_13
PEG_TXP_14
PEG_TXP_15
PEG_COMP
M29
PEG_CRX_GTX_N0
K28
PEG_CRX_GTX_N1
M31
PEG_CRX_GTX_N2
L30
PEG_CRX_GTX_N3
M33
PEG_CRX_GTX_N4
L32
PEG_CRX_GTX_N5
M35
PEG_CRX_GTX_N6
L34
PEG_CRX_GTX_N7
E29
PEG_CRX_GTX_N8
D28
PEG_CRX_GTX_N9
E31
PEG_CRX_GTX_N10
D30
PEG_CRX_GTX_N11
E35
PEG_CRX_GTX_N12
D34
PEG_CRX_GTX_N13
E33
PEG_CRX_GTX_N14
E32
PEG_CRX_GTX_N15
L29
PEG_CRX_GTX_P0
L28
PEG_CRX_GTX_P1
L31
PEG_CRX_GTX_P2
K30
PEG_CRX_GTX_P3
L33
PEG_CRX_GTX_P4
K32
PEG_CRX_GTX_P5
L35
PEG_CRX_GTX_P6
K34
PEG_CRX_GTX_P7
F29
PEG_CRX_GTX_P8
E28
PEG_CRX_GTX_P9
F31
PEG_CRX_GTX_P10
E30
PEG_CRX_GTX_P11
F35
PEG_CRX_GTX_P12
E34
PEG_CRX_GTX_P13
F33
PEG_CRX_GTX_P14
D32
PEG_CRX_GTX_P15
H35
PEG_CTX_GRX_C_N0
H34
PEG_CTX_GRX_C_N1
J33
PEG_CTX_GRX_C_N2
H32
PEG_CTX_GRX_C_N3
J31
PEG_CTX_GRX_C_N4
G30
PEG_CTX_GRX_C_N5
C33
PEG_CTX_GRX_C_N6
B32
PEG_CTX_GRX_C_N7
B31
PEG_CTX_GRX_C_N8
A30
PEG_CTX_GRX_C_N9
B29
PEG_CTX_GRX_C_N10
A28
PEG_CTX_GRX_C_N11
B27
PEG_CTX_GRX_C_N12
A26
PEG_CTX_GRX_C_N13
B25
PEG_CTX_GRX_C_N14
A24
PEG_CTX_GRX_C_N15
J35
PEG_CTX_GRX_C_P0
G34
PEG_CTX_GRX_C_P1
H33
PEG_CTX_GRX_C_P2
G32
PEG_CTX_GRX_C_P3
H31
PEG_CTX_GRX_C_P4
H30
PEG_CTX_GRX_C_P5
B33
PEG_CTX_GRX_C_P6
A32
PEG_CTX_GRX_C_P7
C31
PEG_CTX_GRX_C_P8
B30
PEG_CTX_GRX_C_P9
C29
PEG_CTX_GRX_C_P10
B28
PEG_CTX_GRX_C_P11
C27
PEG_CTX_GRX_C_P12
B26
PEG_CTX_GRX_C_P13
C25
PEG_CTX_GRX_C_P14
B24
PEG_CTX_GRX_C_P15
PEG_CRX_GTX_N[0..15] 46
PEG_CRX_GTX_P[0..15] 46
PEG_CTX_GRX_C_P0
PEG_CTX_GRX_C_P1
PEG_CTX_GRX_C_N1
PEG_CTX_GRX_C_P2
PEG_CTX_GRX_C_N2
PEG_CTX_GRX_C_P3
PEG_CTX_GRX_C_N3
PEG_CTX_GRX_C_P4
PEG_CTX_GRX_C_N4
PEG_CTX_GRX_C_P5
PEG_CTX_GRX_C_N5
PEG_CTX_GRX_C_P6
PEG_CTX_GRX_C_N6
PEG_CTX_GRX_C_P7
PEG_CTX_GRX_C_N7
PEG_CTX_GRX_C_P8
PEG_CTX_GRX_C_N8
PEG_CTX_GRX_C_P9
PEG_CTX_GRX_C_N9
PEG_CTX_GRX_C_P10
PEG_CTX_GRX_C_N10
PEG_CTX_GRX_C_P11
PEG_CTX_GRX_C_N11
PEG_CTX_GRX_C_P12
PEG_CTX_GRX_C_N12
PEG_CTX_GRX_C_P13
PEG_CTX_GRX_C_N13
PEG_CTX_GRX_C_P14
PEG_CTX_GRX_C_N14
PEG_CTX_GRX_C_P15
PEG_CTX_GRX_C_N15
PEG_CTX_GRX_P[0..15]
PEG_CTX_GRX_N[0..15]
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
CC1 0.22U_0402_16V7K~D
CC2 0.22U_0402_16V7K~D
CC3 0.22U_0402_16V7K~D
CC4 0.22U_0402_16V7K~D
CC5 0.22U_0402_16V7K~D
CC6 0.22U_0402_16V7K~D
CC7 0.22U_0402_16V7K~D
CC8 0.22U_0402_16V7K~D
CC9 0.22U_0402_16V7K~D
CC10 0.22U_0402_16V7K~D
CC11 0.22U_0402_16V7K~D
CC12 0.22U_0402_16V7K~D
CC13 0.22U_0402_16V7K~D
CC14 0.22U_0402_16V7K~D
CC15 0.22U_0402_16V7K~D
CC16 0.22U_0402_16V7K~D
CC17 0.22U_0402_16V7K~D
CC18 0.22U_0402_16V7K~D
CC19 0.22U_0402_16V7K~D
CC20 0.22U_0402_16V7K~D
CC21 0.22U_0402_16V7K~D
CC22 0.22U_0402_16V7K~D
CC23 0.22U_0402_16V7K~D
CC24 0.22U_0402_16V7K~D
CC25 0.22U_0402_16V7K~D
CC26 0.22U_0402_16V7K~D
CC27 0.22U_0402_16V7K~D
CC28 0.22U_0402_16V7K~D
CC29 0.22U_0402_16V7K~D
CC30 0.22U_0402_16V7K~D
CC31 0.22U_0402_16V7K~D
CC32 0.22U_0402_16V7K~D
PEG_CTX_GRX_P[0..15] 46
PEG_CTX_GRX_N[0..15] 46
PEG_CTX_GRX_P0
PEG_CTX_GRX_N0PEG_CTX_GRX_C_N0
PEG_CTX_GRX_P1
PEG_CTX_GRX_N1
PEG_CTX_GRX_P2
PEG_CTX_GRX_N2
PEG_CTX_GRX_P3
PEG_CTX_GRX_N3
PEG_CTX_GRX_P4
PEG_CTX_GRX_N4
PEG_CTX_GRX_P5
PEG_CTX_GRX_N5
PEG_CTX_GRX_P6
PEG_CTX_GRX_N6
PEG_CTX_GRX_P7
PEG_CTX_GRX_N7
PEG_CTX_GRX_P8
PEG_CTX_GRX_N8
PEG_CTX_GRX_P9
PEG_CTX_GRX_N9
PEG_CTX_GRX_P10
PEG_CTX_GRX_N10
PEG_CTX_GRX_P11
PEG_CTX_GRX_N11
PEG_CTX_GRX_P12
PEG_CTX_GRX_N12
PEG_CTX_GRX_P13
PEG_CTX_GRX_N13
PEG_CTX_GRX_P14
PEG_CTX_GRX_N14
PEG_CTX_GRX_P15
PEG_CTX_GRX_N15
INTEL_HASWELL_HASWELL
CONN@
A A
5
4
1 OF 9
Security Classification
Security Classification
Security Classification
2012/02/28 2013/02/27
2012/02/28 2013/02/27
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2012/02/28 2013/02/27
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (1/7) DMI,PEG
CPU (1/7) DMI,PEG
CPU (1/7) DMI,PEG
LA-9201P
LA-9201P
LA-9201P
1
5 66Tuesday, August 14, 2012
5 66Tuesday, August 14, 2012
5 66Tuesday, August 14, 2012
0.1
0.1
0.1
5
SM_DRAMPWROK with DDR Power Gating Topology
+3V_PCH
100K_0402_5%~D
+3V_PCH
@
RC89
0.1U_0402_2 5V6K~D
5
1
P
B
O
2
A
G
74AHC1G09GW_ TSSOP5~D
3
RC36 0_0 402_5%~D@
RUN_ON_CPU1.5VS3#10,45
PCH_PLTRST#_BUF
12
1 2
RC57 56_0402_5%~D
1 2
RC134 0_0402_5 %~D
place RC134 near CPU
1 2
RC25 0_0402_5%~ D
RC51 0_0402_5%~D
RC52 0_0402_5%~D
RC43 0_0402_5%~D
RC22 0_0402_5%~D
RC15 0_0402_5%~D
RC13 0_0402_5%~D
+1.05VS
0.1U_0402_25V6K~D
1
CC140
2
CC156
1 2
4
RUNPWROK_AND PM_DRAM_PW RGD_CPU
UC2
H_PECI19,32
12
12
12
12
12
12
1K_0402_1%~D
12
RC17
1 2
RC10 43_ 0402_5%~D
20K_0402_5%~D
12
RC11
12
H_THERMTRIP#
H_CATERR#
H_PROCHOT#
H_PROCHOT#32,63
H_THERMTRIP#19,46
H_PM_SYNC15
H_CPUPWRGD19
CLK_CPU_DPLL#16
CLK_CPU_DPLL1 6
CLK_CPU_DMI#16
CLK_CPU_DMI16
RC2010K_0402_ 5%~D @
RC2110K_0402_ 5%~D @
5
VCC
4
12
place RC57 near CPU
+VCCIO_OUT
+3VS
D D
SYS_PWROK15
PM_DRAM_PW RGD15
C C
B B
SSC CLOCK TERMINATION, IF NOT USED, stuff RC20,RC21
RC88 0_0 402_5%~D
+3V_PCH
RC18 200_0402_1 %~D
+VCCIO_OUT
1 2
RC136 56_0402_5% ~D@
1 2
RC128 49.9_0402_1 %~D@
1 2
RC44 62_ 0402_5%~D
place RC44 near CPU
CPU_SSC_DPLL
CPU_SSC_DPLL#
1 2
1 2
1 2
CLK_CPU_SSC_DPLL #16
CLK_CPU_SSC_DPLL16
Buffered reset to CPU
UC1
1
NC
PLT_RST#15,31,32,33 ,40
2
A
GND3Y
SN74LVC1G07DCKR_ SC70-5~D
+1.35V_CPU_VDDQ
39_0402_5%~D
@
RC64
SSM3K7002FU_SC70-3~D
1 2
13
D
2
G
S
T66PA D~D @
H_PROCHOT#_R
H_THERMTRIP#_R
H_PM_SYNC
VCCPWRGOOD_0_R
PM_DRAM_PW RGD_CPU
CPU_PLTRST#_R
CPU_DPLL#
CPU_DPLL
CPU_SSC_DPLL#
CPU_SSC_DPLL
CPU_DMI#
CPU_DMI
CPU_PLTRST#19
4
1.8K_0402_1%
12
RC16
RC28 0_0 402_5%~D
3.3K_0402_1%~D
12
RC14
@
QC1
AP32
H_CATERR#
H_PECI
AN32
AR27
AK31
AM30
AM35
AT28
AL34
AC10
AT26
G28
H28
F27
E27
D26
E26
RC54 0_0 402_5%~D@
RC53 0_0 402_5%~D
12
Haswell rPGA EDS
SKTOCC
CATERR
PECI
RSVD
PROCHOT
THERMTRIP
PM_SYNC
PWRGOOD
SM_DRAMPWROK
PLTRSTIN
DPLL_REF_CLKN
DPLL_REF_CLKP
SSC_DPLL_REF_CLKN
SSC_DPLL_REF_CLKP
BCLKN
BCLKP
CONN@
12
12
MISC
INTEL_HASWELL_ HASWELL
JCPU1B
THERMAL
PWR
CLOCK
CPU_PLTRST#_R
DDR3
+3V_PCH
RC125 1K_0402_1%~ D@
PCH_SMBDATA12,13,17,38 ,39,40,42
PCH_SMBCLK12,13,17,38 ,39,40,42
AP3
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
SM_DRAMRST
PRDY
PREQ
TCK
TMS
TRST
JTAG
TDI
TDO
DBR
BPM_N_0
BPM_N_1
BPM_N_2
BPM_N_3
BPM_N_4
BPM_N_5
BPM_N_6
BPM_N_7
2 OF 9
CAD Note:
Avoid stub in the PWRGD path
while placing resistors RC25 & RC130
SM_RCOMP0
AR3
SM_RCOMP1
AP2
SM_RCOMP2
AN3
DDR3_DRAMRST#_CPU
AR29
XDP_PRDY#
AT29
XDP_PREQ#
AM34
XDP_TCLK
AN33
XDP_TMS
AM33
XDP_TRST#
AM31
XDP_TDI_R
AL33
XDP_TDO_R
AP33
XDP_DBRESET#_R
AR30
XDP_OBS0_R
AN31
XDP_OBS1_R
AN29
XDP_OBS2_R
AP31
XDP_OBS3_R
AP30
XDP_OBS4_R
AN28
XDP_OBS5_R
AP29
XDP_OBS6_R
AP28
XDP_OBS7_R
VCCPWRGOOD_0_R
3
+VCCIO_OUT
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1
1
2
CC66
CC65
2
Place near JXDP1
1 2
PBTN_OUT#15,32
CPU_PWR_DEBUG10
IMVP_PWRGD15,32,61
SYS_PWROK_XDP
H_CPUPWRGD H_CPUPWRGD_XDP
RC5 need to close to JCPU1
RC5 1K_0402_1% ~D
RC6 0_0402_5%~ D
RC8 0_0402_5%~ D
RC12 0_0 402_5%~D
RC126 0_0402_5 %~D
RC127 0_0402_5 %~D
DDR3_DRAMRST#_CPU 12
1 2
RC148 0_0402_5%~ D
1 2
RC149 0_0402_5%~ D
1 2
RC150 0_0402_5%~ D
1 2
RC151 0_0402_5%~ D
1 2
RC23 0_0 402_5%~D
1 2
RC24 0_0 402_5%~D
RC26 0_0 402_5%~D
1 2
RC30 0_0 402_5%~D
1 2
RC31 0_0 402_5%~D
1 2
RC33 0_0 402_5%~D
1 2
RC34 0_0 402_5%~D
1 2
RC37 0_0 402_5%~D
1 2
RC40 0_0 402_5%~D
1 2
RC38 0_0 402_5%~D
1 2
RC39 0_0 402_5%~D
1 2
1 2
1 2
1 2
1 2
1 2
12
CFG39
For ESD concern, please put near CPU
10K_0402_5%~D
12
RC135
CRB Rev 0.7 is depop
+VCCIO_OUT +VCCIO_OUT
XDP_PREQ#_R
XDP_PRDY#
CFG09
CFG19
CFG29
1 2
RC129 1K_0 402_1%~D
CFG49
CFG59
CFG69
CFG79
XDP_PREQ#_R
XDP_TCLK_R
XDP_TDI
XDP_TDO
XDP_DBRESET#
XDP_OBS0
XDP_OBS1
CFG0
CFG1
CFG2
CFG3_R
XDP_OBS0
XDP_OBS1
CFG4
CFG5
CFG6
CFG7
CFD_PWRBTN#_XDP
SYS_PWROK_XDP
DDR_XDP_SMBDAT_R1
DDR_XDP_SMBCLK_R1
XDP_TCLK_R
XDP_DBRESET# 15
DDR3 COMPENSATION SIGNALS
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil
1 2
RC45 100 _0402_1%~D
1 2
RC55 75_ 0402_1%~D
1 2
RC49 100 _0402_1%~D
2
JXDP1
1
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
9
OBSDATA_A0
11
OBSDATA_A1
13
GND4
15
OBSDATA_A2
17
OBSDATA_A3
19
GND6
21
OBSFN_B0
23
OBSFN_B1
25
GND8
27
OBSDATA_B0
29
OBSDATA_B1
31
GND10
33
OBSDATA_B2
35
OBSDATA_B3
37
GND12
39
PWRGOOD/HOOK0
41
HOOK1
43
VCC_OBS_AB
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
SAMTE_BSH-030-01 -L-D-A CONN@
CRB Rev 0.7 no pull up
GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TD0
TRST#
TMS
GND17
1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
TDI
58
60
CFG17
CFG16
CFG8
CFG9
CFG10
CFG11
CFG19
CFG18
CFG12
CFG13
CFG14
CFG15
CLK_XDP
CLK_XDP#
XDP_RST#_RCPU_PWR_DEBUG_ R
XDP_DBRESET#
XDP_TDO
XDP_TRST#
XDP_TDI
CFG3_R
CFG17 9
CFG16 9
CFG8 9
CFG9 9
CFG10 9
CFG11 9
CFG19 9
CFG18 9
CFG12 9
CFG13 9
CFG14 9
CFG15 9
1 2
RH108 0_0402_5 %~D
1 2
RH113 0_0402_5 %~D
12
RC9 1K_0402_1% ~D
CPU_PLTRST#_R
CLK_CPU_ITP 16
CLK_CPU_ITP# 16
PU/PD for JTAG signals
+3VS
XDP_DBRESET#_R
XDP_TMS
XDP_TDI_R
XDP_PREQ#
XDP_TDO_R
XDP_TCLK
XDP_TRST#
RC19 1 K_0402_1%~D
RC27 5 1_0402_1%~D@
RC29 5 1_0402_1%~D
RC32 5 1_0402_1%~D@
RC35 5 1_0402_1%~D
RC42 5 1_0402_1%~D
RC41 5 1_0402_1%~D
12
+1.05VS
12
12
12
12
12
12
CAD Note:
PLACE PULL-UP RESISTOR WITHIN 2 INCH OF THE CPU
A A
Security Classification
Security Classification
Security Classification
2012/02/28 2013/02/27
2012/02/28 2013/02/27
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
5
4
3
2012/02/28 2013/02/27
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (2/7) PM,XDP,CLK
CPU (2/7) PM,XDP,CLK
CPU (2/7) PM,XDP,CLK
LA-9201P
LA-9201P
LA-9201P
1
6 66Monday, Augu st 20, 2012
6 66Monday, Augu st 20, 2012
6 66Monday, Augu st 20, 2012
0.1
0.1
0.1
5
4
3
2
1
DDR_A_D[0..63]12
D D
C C
+V_SM_VREF
+DIMM0_1_VREF
+DIMM0_1_CA
B B
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
+DIMM0_1_VREF +DIMM0_1_CA +V_SM_VREF
AR15
AT14
AM14
AN14
AT15
AR14
AN15
AM15
AM9
AN9
AM8
AN8
AR9
AT9
AR8
AT8
AJ9
AK9
AJ6
AK6
AJ10
AK10
AJ7
AK7
AF4
AF5
AF1
AF2
AG4
AG5
AG1
AG2
E12
D12
B11
A11
E11
D11
B12
A12
AM3
F16
F13
J1
J2
J5
H5
H2
H1
J4
H4
F2
F1
D2
D3
D1
F3
C3
B3
B5
E6
A5
D6
D5
E5
B6
A6
CONN@
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
SM_VREF
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
JCPU1C
INTEL_HASWELL_HASWELL
3 OF 9
1K_0402_1%~D
12
RC144
Haswell rPGA EDS
SA_WE
AC7
U4
M_CLK_DDR#0
V4
M_CLK_DDR0
AD9
DDR_CKE0_DIMMA
U3
M_CLK_DDR#1
V3
M_CLK_DDR1
AC9
DDR_CKE1_DIMMA
U2
V2
AD8
U1
V1
AC8
M7
DDR_CS0_DIMMA#
L9
DDR_CS1_DIMMA#
M9
M10
M8
M_ODT0
L7
M_ODT1
L8
L10
V5
DDR_A_BS0
U5
DDR_A_BS1
AD1
DDR_A_BS2
V10
U6
DDR_A_RAS#
U7
DDR_A_WE#
U8
DDR_A_CAS#
V8
DDR_A_MA0
AC6
DDR_A_MA1
V9
DDR_A_MA2
U9
DDR_A_MA3
AC5
DDR_A_MA4
AC4
DDR_A_MA5
AD6
DDR_A_MA6
AC3
DDR_A_MA7
AD5
DDR_A_MA8
AC2
DDR_A_MA9
V6
DDR_A_MA10
AC1
DDR_A_MA11
AD4
DDR_A_MA12
V7
DDR_A_MA13
AD3
DDR_A_MA14
AD2
DDR_A_MA15
AP15
DDR_A_DQS#0
AP8
DDR_A_DQS#1
AJ8
DDR_A_DQS#2
AF3
DDR_A_DQS#3
J3
DDR_A_DQS#4
E2
DDR_A_DQS#5
C5
DDR_A_DQS#6
C11
DDR_A_DQS#7
AP14
DDR_A_DQS0
AP9
DDR_A_DQS1
AK8
DDR_A_DQS2
AG3
DDR_A_DQS3
H3
DDR_A_DQS4
E3
DDR_A_DQS5
C6
DDR_A_DQS6
C12
DDR_A_DQS7
RSVD_AC7
SA_CK_N_0
SA_CK_P_0
SA_CKE_0
SA_CK_N_1
SA_CK_P_1
SA_CKE_1
SA_CK_N_2
SA_CK_P_2
SA_CKE_2
SA_CK_N_3
SA_CK_P_3
SA_CKE_3
SA_CS_N_0
SA_CS_N_1
SA_CS_N_2
SA_CS_N_3
SA_ODT_0
SA_ODT_1
SA_ODT_2
SA_ODT_3
SA_BS_0
SA_BS_1
SA_BS_2
RSVD_V10
SA_RAS
SA_CAS
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_MA_15
SA_DQS_N_0
SA_DQS_N_1
SA_DQS_N_2
SA_DQS_N_3
SA_DQS_N_4
SA_DQS_N_5
SA_DQS_N_6
SA_DQS_N_7
SA_DQS_P_0
SA_DQS_P_1
SA_DQS_P_2
SA_DQS_P_3
SA_DQS_P_4
SA_DQS_P_5
SA_DQS_P_6
SA_DQS_P_7
+DIMM0_1_VREF_CPU +DIMM0_1_CA_CPU
T67 PAD~D@
M_CLK_DDR#0 12
M_CLK_DDR0 12
DDR_CKE0_DIMMA 12
M_CLK_DDR#1 12
M_CLK_DDR1 12
DDR_CKE1_DIMMA 12
DDR_CS0_DIMMA# 12
DDR_CS1_DIMMA# 12
M_ODT0 12
M_ODT1 12
DDR_A_BS0 12
DDR_A_BS1 12
DDR_A_BS2 12
DDR_A_RAS# 12
DDR_A_WE# 12
DDR_A_CAS# 12
DDR_A_MA[0..15] 12
DDR_A_DQS#[0..7] 12
DDR_A_DQS[0..7] 12
+1.35V+1.35V
1K_0402_1%~D
12
RC145
DDR_B_D[0..63]13
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
AR18
AT18
AM17
AM18
AR17
AT17
AN17
AN18
AT12
AR12
AN12
AM11
AT11
AR11
AM12
AN11
AR5
AR6
AM5
AM6
AT5
AT6
AN5
AN6
AJ4
AK4
AJ1
AJ2
AM1
AN1
AK2
AK1
M2
M4
M1
M5
G10
J10
E15
D15
A15
B15
E14
D14
A14
B14
L2
L4
L1
L5
G7
J8
G8
G9
J7
J9
A8
B8
A9
B9
D8
E8
D9
E9
+1.35V
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
CONN@
1K_0402_1%~D
12
RC86
JCPU1D
INTEL_HASWELL_HASWELL
4 OF 9
+V_SM_VREF_CNT
Haswell rPGA EDS
RSVD
SB_CKN0
SB_CK0
SB_CKE_0
SB_CKN1
SB_CK1
SB_CKE_1
SB_CKN2
SB_CK2
SB_CKE_2
SB_CKN3
SB_CK3
SB_CKE_3
SB_CS_N_0
SB_CS_N_1
SB_CS_N_2
SB_CS_N_3
SB_ODT_0
SB_ODT_1
SB_ODT_2
SB_ODT_3
SB_BS_0
SB_BS_1
SB_BS_2
RSVD
SB_RAS
SB_WE
SB_CAS
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_MA_15
SB_DQS_N_0
SB_DQS_N_1
SB_DQS_N_2
SB_DQS_N_3
SB_DQS_N_4
SB_DQS_N_5
SB_DQS_N_6
SB_DQS_N_7
SB_DQS_P_0
SB_DQS_P_1
SB_DQS_P_2
SB_DQS_P_3
SB_DQS_P_4
SB_DQS_P_5
SB_DQS_P_6
SB_DQS_P_7
AG8
Y4
M_CLK_DDR#2
AA4
M_CLK_DDR2
AF10
DDR_CKE2_DIMMB
Y3
M_CLK_DDR#3
AA3
M_CLK_DDR3
AG10
DDR_CKE3_DIMMB
Y2
AA2
AG9
Y1
AA1
AF9
P4
DDR_CS2_DIMMB#
R2
DDR_CS3_DIMMB#
P3
P1
R4
M_ODT2
R3
M_ODT3
R1
P2
R7
DDR_B_BS0
P8
DDR_B_BS1
AA9
DDR_B_BS2
R10
R6
DDR_B_RAS#
P6
DDR_B_WE#
P7
DDR_B_CAS#
R8
DDR_B_MA0
Y5
DDR_B_MA1
Y10
DDR_B_MA2
AA5
DDR_B_MA3
Y7
DDR_B_MA4
AA6
DDR_B_MA5
Y6
DDR_B_MA6
AA7
DDR_B_MA7
Y8
DDR_B_MA8
AA10
DDR_B_MA9
R9
DDR_B_MA10
Y9
DDR_B_MA11
AF7
DDR_B_MA12
P9
DDR_B_MA13
AA8
DDR_B_MA14
AG7
DDR_B_MA15
AP18
DDR_B_DQS#0
AP11
DDR_B_DQS#1
AP5
DDR_B_DQS#2
AJ3
DDR_B_DQS#3
L3
DDR_B_DQS#4
H9
DDR_B_DQS#5
C8
DDR_B_DQS#6
C14
DDR_B_DQS#7
AP17
DDR_B_DQS0
AP12
DDR_B_DQS1
AP6
DDR_B_DQS2
AK3
DDR_B_DQS3
M3
DDR_B_DQS4
H8
DDR_B_DQS5
C9
DDR_B_DQS6
C15
DDR_B_DQS7
T76 PAD~D@
M_CLK_DDR#2 13
M_CLK_DDR2 13
DDR_CKE2_DIMMB 13
M_CLK_DDR#3 13
M_CLK_DDR3 13
DDR_CKE3_DIMMB 13
DDR_CS2_DIMMB# 13
DDR_CS3_DIMMB# 13
M_ODT2 13
M_ODT3 13
DDR_B_BS0 13
DDR_B_BS1 13
DDR_B_BS2 13
DDR_B_RAS# 13
DDR_B_WE# 13
DDR_B_CAS# 13
DDR_B_MA[0..15] 13
DDR_B_DQS#[0..7] 13
DDR_B_DQS[0..7] 13
1 2
RC152 0_0402_1%~D
1
0.022U_0402_25V7K~D
A A
CC184
RC154
24.9_0402_1%
5
2
12
1K_0402_1%~D
12
RC146
0.022U_0402_25V7K~D
CC183
RC155
24.9_0402_1%
4
1 2
RC153 0_0402_1%~D
1
2
12
1K_0402_1%~D
12
RC147
0.022U_0402_25V7K~D
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
24.9_0402_1%
3
CC185
RC157
1 2
RC156 0_0402_1%~D
1
2
12
2011/06/02 2012/06/02
2011/06/02 2012/06/02
2011/06/02 2012/06/02
1K_0402_1%~D
12
RC78
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (3/7) DDRIII
CPU (3/7) DDRIII
CPU (3/7) DDRIII
7 66Tuesday, August 14, 2012
7 66Tuesday, August 14, 2012
1
7 66Tuesday, August 14, 2012
0.1
0.1
0.1
5
4
3
2
1
COMPENSATION PU FOR eDP
+VCOMP_OUT
EDP_COMP
D D
CAD Note:Trace width=20 mils ,Spacing=25mil,
12
RC124.9_0402_1%~D
Max length=100 mils.
Haswell rPGA EDS
CPU_HDMI_N0
CPU_HDMI_P0
CPU_HDMI_N1
CPU_HDMI_P1
CPU_HDMI_N2
CPU_HDMI_P2
CPU_HDMI_N3
CPU_HDMI_P3
HDMI
CPU_HDMI_N027
CPU_HDMI_P027
CPU_HDMI_N127
CPU_HDMI_P127
CPU_HDMI_N227
CPU_HDMI_P227
CPU_HDMI_N327
CPU_HDMI_P327
mDP
C C
DMC
CPU_DPD_DMC_N030
CPU_DPD_DMC_P030
CPU_DPD_DMC_N130
CPU_DPD_DMC_P130
CPU_DPD_DMC_N230
CPU_DPD_DMC_P230
CPU_DPD_DMC_N330
CPU_DPD_DMC_P330
CPU_DPD_DMC_N0
CPU_DPD_DMC_P0
CPU_DPD_DMC_N1
CPU_DPD_DMC_P1
CPU_DPD_DMC_N2
CPU_DPD_DMC_P2
CPU_DPD_DMC_N3
CPU_DPD_DMC_P3
T28
DDIB_TXBN_0
U28
DDIB_TXBP_0
T30
DDIB_TXBN_1
U30
DDIB_TXBP_1
U29
DDIB_TXBN_2
V29
DDIB_TXBP_2
U31
DDIB_TXBN_3
V31
DDIB_TXBP_3
T34
DDIC_TXCN_0
U34
DDIC_TXCP_0
U35
DDIC_TXCN_1
V35
DDIC_TXCP_1
U32
DDIC_TXCN_2
T32
DDIC_TXCP_2
U33
DDIC_TXCN_3
V33
DDIC_TXCP_3
P29
DDID_TXDN_0
R29
DDID_TXDP_0
N28
DDID_TXDN_1
P28
DDID_TXDP_1
P31
DDID_TXDN_2
R31
DDID_TXDP_2
N30
DDID_TXDN_3
P30
DDID_TXDP_3
INTEL_HASWELL_HASWELL
CONN@
JCPU1H
eDP
EDP_AUXN
EDP_AUXP
EDP_HPD
EDP_RCOMP
RSVD
EDP_TXN_0
EDP_TXP_0
EDP_TXN_1
EDP_TXP_1
FDI_TXN_0
FDI_TXP_0
FDI_TXN_1
FDI_TXP_1
DDI
8 OF 9
M27
N27
P27
E24
R27
P35
R35
N34
P34
P33
R33
N32
P32
CPU_EDP_AUX#
CPU_EDP_AUX
EDP_HPD_R
EDP_COMP
CPU_EDP_TX0N
CPU_EDP_TX0P
CPU_EDP_TX1N
CPU_EDP_TX1P
CPU_EDP_TX2N
CPU_EDP_TX2P
CPU_EDP_TX3N
CPU_EDP_TX3P
CPU_EDP_AUX# 24
CPU_EDP_AUX 24
T77PAD~D @
CPU_EDP_TX0N 24
CPU_EDP_TX0P 24
CPU_EDP_TX1N 24
CPU_EDP_TX1P 24
CPU_EDP_TX2N 24
CPU_EDP_TX2P 24
CPU_EDP_TX3N 24
CPU_EDP_TX3P 24
+VCCIO_OUT
B B
A A
HPD INVERSION FOR EDP
CPU_EDP_HPD#24
100K_0402_5%~D
12
RC75
12
10K_0402_5%~D
RC65
EDP_HPD_R
BSS138_SOT23~D
13
D
2
G
QC10
S
Security Classification
Security Classification
Security Classification
2012/02/28 2013/02/27
2012/02/28 2013/02/27
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2012/02/28 2013/02/27
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
CPU (4/7) FDI,eDP,DDI
CPU (4/7) FDI,eDP,DDI
CPU (4/7) FDI,eDP,DDI
LA-9201P
LA-9201P
LA-9201P
1
0.1
0.1
0.1
8 66Tuesday, August 14, 2012
8 66Tuesday, August 14, 2012
8 66Tuesday, August 14, 2012
5
4
3
2
1
CFG STRAPS for CPU
CFG2
D D
1K_0402_1%~D
12
@
RC76
PEG Static Lane Reversal - CFG2 is for the 16x
1:(Default) Normal Operation; Lane #
CFG2
definition matches socket pin map definition
0:Lane Reversed
Haswell rPGA EDS
T103PAD~D@
T80 PAD~D@ T99PAD~D @
T78 PAD~D@
T110PAD~D@
T81 PAD~D@
T79 PAD~D@
C C
B B
12
RC60 49.9_0402_1%~D
RC58 49.9_0402_1%~D
RC59 49.9_0402_1%~D
H_CPU_TESTLO
12
CFG_RCOMP
12
H_CPU_RSVD
T101PAD~D@
T83 PAD~D@
T108PAD~D@
+VCC_CORE
T82 PAD~D@
T94 PAD~D@
T85 PAD~D@
T84 PAD~D@ T95PAD~D @
T86 PAD~D@
CFG06
CFG16
CFG26
CFG36
CFG46
CFG56
CFG66
CFG76
CFG86
CFG96
CFG106
CFG116
CFG126
CFG136
CFG146
CFG156
H_CPU_RSVD
H_CPU_TESTLO
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
AT1
AT2
AD10
A34
A35
W29
W28
G26
W33
AL30
AL29
F25
C35
B35
AL25
W30
W31
W34
AT20
AR20
AP20
AP22
AT22
AN22
AT25
AN23
AR24
AT23
AN20
AP24
AP26
AN25
AN26
AP25
RSVD_TP
RSVD_TP
RSVD
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VCC
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
TESTLO
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
INTEL_HASWELL_HASWELL
CONN@
JCPU1I
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
CFG_RCOMP
CFG_16
CFG_18
CFG_17
CFG_19
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
NC
RSVD
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
9 OF 9
C23
B23
D24
D23
AT31
AR21
AR23
AP21
AP23
AR33
G6
AM27
AM26
F5
AM2
K6
E18
U10
P10
B1
A2
AR1
E21
E20
AP27
AR26
AL31
AL32
CFG_RCOMP
CFG16
CFG18
CFG17
CFG19
T90PAD~D @
T87PAD~D @
T88PAD~D @
CFG16 6
CFG18 6
CFG17 6
CFG19 6
T91PAD~D @
T104PAD~D @
T92PAD~D @
T89PAD~D @
T93PAD~D @
T111PAD~D @
T96PAD~D @
T98PAD~D @
T97PAD~D @
T100PAD~D @
T109PAD~D @
T102PAD~D @
T107PAD~D @
T105PAD~D @
T106PAD~D @
CFG4
CFG[6:5]
CFG4
1K_0402_1%~D
12
RC77
Display Port Presence Strap
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
CFG6
CFG5
1K_0402_1%~D
12
@
RC90
1K_0402_1%~D
12
@
RC92
PCIE Port Bifurcation Straps
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CFG7
1K_0402_1%~D
12
@
RC91
PEG DEFER TRAINING
1: (Default) PEG Train immediately
A A
CFG7
following xxRESETB de assertion
0: PEG Wait for BIOS for training
Security Classification
Security Classification
Security Classification
2012/02/28 2013/02/27
2012/02/28 2013/02/27
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2012/02/28 2013/02/27
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
CPU (5/7) RSVD,CFG
CPU (5/7) RSVD,CFG
CPU (5/7) RSVD,CFG
LA-9201P
LA-9201P
LA-9201P
1
0.1
0.1
0.1
9 66Tuesday, August 14, 2012
9 66Tuesday, August 14, 2012
9 66Tuesday, August 14, 2012
5
4
3
2
1
K27
L27
T27
V27
AB11
AB2
AB5
AB8
AE11
AE2
AE5
AE8
AH11
K11
N11
T11
W11
N26
K26
AL27
AK27
AL35
E17
AN35
A23
F22
W32
AL16
AL13
AM28
AM29
AL28
AP35
H27
AP34
AT35
AR35
AR32
AL26
AT34
AL22
AT33
AM21
AM25
AM22
AM20
AM24
AL19
AM23
AT32
Y25
Y26
Y27
Y28
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Haswell rPGA EDS
RSVD
RSVD
RSVD
RSVD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
N8
VDDQ
VDDQ
T2
VDDQ
T5
VDDQ
T8
VDDQ
VDDQ
W2
VDDQ
W5
VDDQ
W8
VDDQ
RSVD
VCC
RSVD
RSVD
VCC_SENSE
RSVD
VCCIO_OUT
VCCIO2PCH
VCCIOA_OUT
RSVD
RSVD
J27
VSS
RSVD
VIDALERT
VIDSCLK
VIDSOUT
VSS
PWR_DEBUG
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
INTEL_HASWELL_ HASWELL
CONN@
JCPU1E
5 OF 9
D D
C C
B B
+1.35V_CPU_VDDQ Source
SUSP#32,45 ,58,60
CPU1.5V_S3_GATE32
SVID ALERT
VIDALERT_N61
SVID DATA
VIDSOUT61
VCC_SENSE
VCCSENSE6 1
VSSSENSE61
1 2
RC93 0_ 0402_5%~D@
1 2
RC79 0_ 0402_5%~D
+VCCIO_OUT
75_0402_1%~D
12
RC61
+VCCIO_OUT
110_0402_1%~D
12
RC63
VIDSOUT
+VCC_CORE
100_0402_1%~D
12
RC66
VCCSENSE
VSSSENSE
100_0402_1%~D
12
RC70
+3VALW
100K_0402_5%~D
12
RC74
RUN_ON_CPU1.5VS3#
DMN66D0LDW-7_SOT363-6~D
61
QC4A
2
CAD Note: Place the PU resistors close to CPU
RC60 close to CPU 300 - 1500mils
12
H_CPU_SVIDALRT#
RC6943_0402_5% ~D
CAD Note: Place the PU resistors close to CPU
RC63 close to CPU 300 - 1500mils
B+_BIAS
330K_0402_5%~D
12
RC72
3
5
4
RUN_ON_CPU1.5VS3# 6,4 5
CAD Note: RC67 SHOULD BE PLACED CLOSE TO CPU
12
VCCSENSE_R
RC670_040 2_5%~D
CAD Note: RC68 SHOULD BE PLACED CLOSE TO CPU
12
VSSSENSE_R
RC680_0402_5%~D
VSSSENSE_R 11
RUN_ON_CPU1.5VS3R UN_ON_CPU1.5VS3
DMN66D0LDW-7_SOT363-6~D
QC4B
+1.35V
QC3
AO4304L_SO8
8
7
6
5
4
0.022U_0402_25V7K~D
1M_0402_5%~D
12
RC143
1
CC136
2
+1.05VS
RC4 0_0603_5%~ D@
RESISTOR STUFFING OPTIONS ARE
PROVIDED FOR TESTING PURPOSES
+1.35V_CPU_VDDQ
1
2
3
10U_0603_6.3V6M~D
1
2
+1.35V_CPU_VDDQ
10U_0603_6.3V6M~D
20K_0402_5%~D
12
CC135
1
2
12
10U_0603_6.3V6M~D
1
1
CC170
CC180
2
2
@
RC73
+VCCIO_OUT
VDDQ DECOUPLING
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CC169
10U_0603_6.3V6M~D
1
1
CC168
2
2
T113 PAD~D@
T114 PAD~D@
T112 PAD~D@
T116 PAD~D@
CC186
+1.35V_CPU_VDDQ
VCCSENSE_R
H_CPU_SVIDALRT#
VR_SVID_CLK
VIDSOUT
+VCC_CORE
+1.35V
CC151 0.1U_0402_10V7 K~D
CC152 0.1U_0402_10V7 K~D
+1.05VS
10K_0402_5%~D
12
@
RC80
CPU_PWR_DEBUG
10K_0402_5%~D
12
@
RC71
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
1
CC161
2
CC163
CC162
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
CC164
2
10U_0603_6.3V6M~D
1
1
CC165
2
2
12
12
T115 PAD~D@
+VCC_CORE
T151 PAD~D@
T152 PAD~D@
T153 PAD~D@
+VCCIO_OUT
T156 PAD~D@
+VCOMP_OUT
T160 PAD~D@
T159 PAD~D@
T184 PAD~D@
T154 PAD~D@
VIDSCLK61
CPU_PWR_DEBUG6
T157 PAD~D@
T158 PAD~D@
T162 PAD~D@
T163 PAD~D@
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
1
1
CC167
+
CC166
+
2
2
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AA26
AA28
AA34
AA30
AA32
AB26
AB29
AB25
AB27
AB28
AB30
AB31
AB33
AB34
AB32
AC26
AB35
AC28
AD25
AC30
AD28
AC32
AD31
AC34
AD34
AD26
AD27
AD29
AD30
AD32
AD33
AD35
AE26
AE32
AE28
AE30
AG28
AG34
AE34
AF25
AF26
AF27
AF28
AF29
AF30
AF31
AF32
AF33
AF34
AF35
AG26
AH26
AH29
AG30
AG32
AH32
AH35
AH25
AH27
AH28
AH30
AH31
AH33
AH34
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
G25
H25
J25
K25
L25
M25
N25
P25
R25
T25
U25
U26
V25
V26
W26
W27
+VCC_CORE
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
CH88
1
2
A A
5
4
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
CH139
CH89
1
1
2
2
3
22U_0805_6.3V6M~D
CH138
1
2
CH136
1
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
CH133
1
2
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
CH132
CH131
1
1
2
2
CH137
1
2
2012/02/28 2013/02/27
2012/02/28 2013/02/27
2012/02/28 2013/02/27
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
CH135
CH134
1
1
2
2
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (6/7) PWR
CPU (6/7) PWR
CPU (6/7) PWR
LA-9201P
LA-9201P
LA-9201P
1
0.1
0.1
0.1
10 6 6Tuesday, August 14 , 2012
10 6 6Tuesday, August 14 , 2012
10 6 6Tuesday, August 14 , 2012
5
4
3
2
1
D D
C C
B B
Haswell rPGA EDS
A10
A13
A16
A19
A22
A25
A27
A29
A3
A31
A33
A4
A7
AA11
AA25
AA27
AA31
AA29
AB1
AB10
AA33
AA35
AB3
AC25
AC27
AB4
AB6
AB7
AB9
AC11
AD11
AC29
AC31
AC33
AC35
AD7
AE1
AE10
AE25
AE29
AE3
AE27
AE35
AE4
AE6
AE7
AE9
AF11
AF6
AF8
AG11
AG25
AE31
AG31
AE33
AG6
AH1
AH10
AH2
AG27
AG29
AH3
AG33
AG35
AH4
AH5
AH6
AH7
AH8
AH9
AJ11
AJ5
AK11
AK25
AK26
AK28
AK29
AK30
AK32
E19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
JCPU1F
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RSVD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AK34
AK5
AL1
AL10
AL11
AL12
AL14
AL15
AL17
AL18
AL2
AL20
AL21
AL23
E22
AL3
AL4
AL5
AL6
AL7
AL8
AL9
AM10
AM13
AM16
AM19
E25
AM32
AM4
AM7
AN10
AN13
AN16
AN19
AN2
AN21
AN24
AN27
AN30
AN34
AN4
AN7
AP1
AP10
AP13
AP16
AP19
AP4
AP7
W25
AR10
AR13
AR16
AR19
AR2
AR22
AR25
AR28
AR31
AR34
AR4
AR7
AT10
AT13
AT16
AT19
AT21
AT24
AT27
AT3
AT30
AT4
AT7
B10
B13
B16
B19
B2
B22
Haswell rPGA EDS
B34
VSS
B4
VSS
B7
VSS
C1
VSS
C10
VSS
C13
VSS
C16
VSS
C19
VSS
C2
VSS
C22
VSS
C24
VSS
C26
VSS
C28
VSS
C30
VSS
C32
VSS
C34
VSS
C4
VSS
C7
VSS
D10
VSS
D13
VSS
D16
VSS
D19
VSS
D22
VSS
D25
VSS
D27
VSS
D29
VSS
D31
VSS
D33
VSS
D35
VSS
D4
VSS
D7
VSS
E1
VSS
E10
VSS
E13
VSS
E16
VSS
E4
VSS
E7
VSS
F10
VSS
F11
VSS
F12
VSS
F14
VSS
F15
VSS
F17
VSS
F18
VSS
F20
VSS
F21
VSS
F23
VSS
F24
VSS
F26
VSS
F28
VSS
F30
VSS
F32
VSS
F34
VSS
F4
VSS
F6
VSS
F7
VSS
F8
VSS
F9
VSS
G1
VSS
G11
VSS
G2
VSS
G27
VSS
G29
VSS
G3
VSS
G31
VSS
G33
VSS
G35
VSS
G4
VSS
G5
VSS
H10
VSS
H26
VSS
H6
VSS
H7
VSS
J11
VSS
J26
VSS
J28
RSVD
J30
VSS
J32
VSS
J34
VSS
J6
VSS
K1
VSS
JCPU1G
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RSVD
RSVD
RSVD
RSVD
VSS_SENSE
RSVD
K10
K2
K29
K3
K31
K33
K35
K4
K5
K7
K8
K9
L11
L26
L6
M11
M26
M28
M30
M32
M34
M6
N1
N10
N2
N29
N3
N31
N33
N35
N4
N5
N6
N7
N9
P11
P26
P5
R11
R26
R28
R30
R32
R34
R5
T1
T10
T29
T3
T31
T33
T35
T4
T6
T7
T9
U11
U27
V11
V28
V30
V32
V34
W1
W10
W3
W35
W4
W6
W7
W9
Y11
H11
AL24
F19
T26
AK35
AK33
VSSSENSE_R 10
T120PAD~D @
INTEL_HASWELL_HASWELL
CONN@
A A
5
6 OF 9
Security Classification
Security Classification
Security Classification
2012/02/28 2013/02/27
2012/02/28 2013/02/27
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
3
2012/02/28 2013/02/27
INTEL_HASWELL_HASWELL
CONN@
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
7 OF 9
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
CPU (7/7) VSS
CPU (7/7) VSS
CPU (7/7) VSS
LA-9201P
LA-9201P
LA-9201P
1
0.1
0.1
0.1
11 66Tuesday, August 14, 2012
11 66Tuesday, August 14, 2012
11 66Tuesday, August 14, 2012
5
4
3
2
1
H:5.2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
+1.35V+1.35V
DDR_A_D4
DDR_A_D5
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR3_DRAMRST#_R
DDR_A_D14
DDR_A_D15
DDR_A_D20DDR_A_D16
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_CKE1_DIMM A
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11DDR_A_MA12
DDR_A_MA7DDR_A_MA9
DDR_A_MA6DDR_A_MA8
DDR_A_MA4DDR_A_MA5
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA #
M_ODT0
M_ODT1
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
M_THERMAL#
PCH_SMBDATA
PCH_SMBCLK
+0.675VS
DDR_CKE1_DIMM A 7
M_CLK_DDR1 7
M_CLK_DDR#1 7
DDR_A_BS1 7
DDR_A_RAS# 7
DDR_CS0_DIMMA # 7
M_ODT0 7
M_ODT1 7
+V_SM_VREF_CN T
2.2U_0603_6.3V6K~D
1
2
M_THERMAL# 13,32
PCH_SMBDATA 6,13,17,38,39,40,42
PCH_SMBCLK 6,13,17,38,39,4 0,42
+1.35V
+1.35V
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD3
2
10U_0603_6.3V6M~D
1
CD7
2
1U_0402_6.3V6K~D
1
1
CD4
CD5
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
1
CD8
CD9
2
2
Layout Note:
Place near JDIMM1.203,204
Layout Note:
Place near JDIMM1
1U_0402_6.3V6K~D
1
CD6
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD10
1
2
CD11
1
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD12
1
2
330U_SX_2VY~D
1
@
CD14
CD13
1
+
2
2
2011/11/25 change to +0.675V
+0.675VS
1U_0402_6.3V6K~D
0.1U_0402_16V4Z~D
CD16
CD15
1
2
1U_0402_6.3V6K~D
CD18
CD17
1
1
2
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD20
CD19
1
2
1 2
DDR_A_DQS#[0..7]7
DDR_A_DQS[0..7]7
DDR_A_D[0..63]7
DDR_A_MA[0..15 ]7
+1.35V
D D
DDR3_DRAMRST#_R13
C C
B B
1 2
RD24 1K_0402_ 1%~D
12
@
+DIMM0_1_V REF_CPU
1K_0402_1%~D
RD23
DDR3_DRAMRST#_CPU 6
RD1 0 _0402_5%~D
RD12
10K_0402_5 %~D
@
RD14
10K_0402_5 %~D
+3VS
1 2
1 2
DDR_CKE0_DIMM A7
DDR_CS1_DIMMA #7
RD13
@
10K_0402_5 %~D
1 2
+3VS
RD15
10K_0402_5 %~D
1 2
2.2U_0603_6.3V6K~D
CD2
1
1
2
2
DDR_A_BS27
M_CLK_DDR07
M_CLK_DDR#07
DDR_A_BS07
DDR_A_WE#7
DDR_A_CAS#7
0.1U_0402_16V4Z~D
1
2
0.1U_0402_16V4Z~D
CD1
DDR_CKE0_DIMM A
DDR_CS1_DIMMA #
2.2U_0603_6.3V6K~D
CD21
1
2
+DIMM0_VREF
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9 DDR_A_D13
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_BS2
DDR_A_MA3
DDR_A_MA1
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
+0.675VS
CD22
JDIMM1
1
VREF_DQ
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DM0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
DQ16
41
DQ17
43
VSS
45
DQS2#
47
DQS2
49
VSS
51
DQ18
53
DQ19
55
VSS
57
DQ24
59
DQ25
61
VSS
63
DM3
65
VSS
67
DQ26
69
DQ27
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
VDD
83
A12/BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
A10/AP
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1#
123
VDD
125
TEST
127
VSS
129
DQ32
131
DQ33
133
VSS
135
DQS4#
137
DQS4
139
VSS
141
DQ34
143
DQ35
145
VSS
147
DQ40
149
DQ41
151
VSS
153
DM5
155
VSS
157
DQ42
159
DQ43
161
VSS
163
DQ48
165
DQ49
167
VSS
169
DQS6#
171
DQS6
173
VSS
175
DQ50
177
DQ51
179
VSS
181
DQ56
183
DQ57
185
VSS
187
DM7
189
VSS
191
DQ58
193
DQ59
195
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
207
BOSS1
LCN_DAN06-K452 6-0102
CONN@
OK
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
CKE1
VDD
A15
A14
VDD
A11
VDD
VDD
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
GND2
BOSS2
A7
A6
A4
A2
A0
NC
2011/11/25 change to +0.675V
A A
Security Classification
Security Classification
Security Classification
2011/06/02 2012/06/02
2011/06/02 2012/06/02
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
5
4
3
2011/06/02 2012/06/02
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
DDRIII DIMMA
DDRIII DIMMA
DDRIII DIMMA
12 6 6Tuesday, August 14 , 2012
12 6 6Tuesday, August 14 , 2012
1
12 6 6Tuesday, August 14 , 2012
0.1
0.1
0.1
5
4
3
2
1
H:9.2
2011/11/25 change to +1.35V
+1.35V
1 2
+DIMM0_1_CA _CPU
DDR_B_DQS#[0..7]7
DDR_B_DQS[0..7]7
D D
DDR_B_D[0..63]7
DDR_B_MA[0..15 ]7
Layout Note:
Place near JDIMMB
RD16 0_ 0402_5%~D
2.2U_0603_6.3V6K~D
CD23
1
1
2
2
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
2011/11/25 change to +1.35V
+1.35V
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD25
1
2
C C
+1.35V
10U_0603_6.3V6M~D
CD29
1
2
CD26
1
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD31
CD30
1
1
2
2
Layout Note:
Place near JDIMMB.203,204
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD28
CD27
1
1
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD33
CD32
1
1
2
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD34
1
2
330U_SX_2VY~D
1
@
CD35
1
2
CD36
+
2
DDR_CKE2_DIMM B7
DDR_B_BS27
M_CLK_DDR27
M_CLK_DDR#27
DDR_B_BS07
DDR_B_WE#7
DDR_B_CAS#7
DDR_CS3_DIMMB #7
2011/11/25 change to +0.675V
+0.675VS
B B
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD40
CD39
1
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD42
CD41
1
2
10K_0402_5 %~D
10K_0402_5 %~D
RD19
RD21
+3VS
@
1 2
12
RD20
10K_0402_5 %~D
1 2
12
RD22
@
10K_0402_5 %~D
+3VS
0.1U_0402_16V4Z~D
CD24
+DIMM1_VREF
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_CKE2_DIMM B
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_CS3_DIMMB #
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
+0.675VS
0.1U_0402_16V4Z~D
2.2U_0603_6.3V6K~D
CD43
1
1
2
2
CD44
JDIMM2
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
LCN_DAN06-K492 6-0102
CONN@
OK
VREF_DQ1VSS1
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
G1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
CKE1
VDD2
A15
A14
VDD4
A11
VDD6
VDD8
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
A7
88
90
A6
92
A4
94
96
A2
98
A0
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
G2
2011/11/25 change to +0.675V
+1.35V
DDR_B_D4
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR3_DRAMRST#
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_CKE3_DIMM B
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB #
M_ODT2
M_ODT3
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
M_THERMAL#
PCH_SMBDATA
PCH_SMBCLK
+0.675VS
DDR3_DRAMRST#_R 12
DDR_CKE3_DIMM B 7
2011/11/25 change to +1.35V
M_CLK_DDR3 7
M_CLK_DDR#3 7
DDR_B_BS1 7
DDR_B_RAS# 7
DDR_CS2_DIMMB # 7
M_ODT2 7
M_ODT3 7
1
2
M_THERMAL# 12,3 2
PCH_SMBDATA 6,12,17,38,39,40,42
PCH_SMBCLK 6,12,17,38,39,4 0,42
+V_SM_VREF_CN T
0.1U_0402_16V4Z~D
2.2U_0603_6.3V6K~D
CD38
CD37
1
2
A A
Security Classification
Security Classification
Security Classification
2011/06/02 2012/06/02
2011/06/02 2012/06/02
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
5
4
3
2011/06/02 2012/06/02
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
DDRIII DIMMB
DDRIII DIMMB
DDRIII DIMMB
13 6 6Tuesday, August 14 , 2012
13 6 6Tuesday, August 14 , 2012
1
13 6 6Tuesday, August 14 , 2012
0.1
0.1
0.1
5
+RTC_CELL
330K_0402_1%~D
12
4
RH38
3
2
1
D D
INTVRMEN - INTEGRATED SUS 1.05V VRM
ENABLE
High - Enable Internal VRs
Low - Enable External VRs
+3VS
1 2
RH35 10K_ 0402_5%~D@
NO REBOOT STRAP
DISABLED WHEN LOW (DEFAULT)
ENABLED WHEN HIGH
C C
+3VS
1 2
RH355 100K_0402_5 %~D
CMOS_CLR1
Shunt Clear CMOS
Open
ME_CLR1
Shunt Clear ME RTC Registers
Open
HDA_SYNC Isolation Circuit
B B
A A
PCH_INTVRMEN
330K_0402_1%~D
12
@
RH39
HDA_SPKR
PCH_GPIO33
CMOS setting
Keep CMOS
TPM setting
Keep ME RTC Registers
S
1M_0402_5%~D
SSM3K7002FU_ SC70-3~D
RH31
1 2
+3V_PCH
1 2
RH287 1K_0402_1%~ D@
FLASH DESCRIPTOR SECURITY OVERRIDE
LOW = DESABLED (DEFAULT)
HIGH = ENABLED
+RTC_CELL
1
1
@
ME1 SHORT PADS~D
1 2
CH5 1U_ 0402_6.3V6K~D
G
2
13
PCH_AZ_SYNCPCH_AZ_SYNC_Q
D
QH8
PCH_AZ_SDOUT
1 2
RH22 20K_ 0402_5%~D
1 2
RH11 1M_ 0402_5%~D
1 2
RH23 20K_ 0402_5%~D
2
2
+3V_PCH
0_0603_5%~D
12
RH288
+3.3V_ALW_ PCH_JTAG PCH_JTAG_TMS
1
1
@
CMOS1 SHORT PADS~D
1 2
CH4
CMOS place near DIMM
RH59 51_ 0402_1%~D
RH44 210 _0402_1%~D
RH45 210 _0402_1%~D
RH46 210 _0402_1%~D
HDA for Codec and MDC
PCH_AZ_CODEC_SDOUT34
PCH_AZ_CODEC_SYNC34
PCH_AZ_CODEC_RST#34
PCH_AZ_CODEC_BITCLK34
1
CH2
1 2
18P_0402_5 0V8J~D
CH3
1 2
18P_0402_5 0V8J~D
2
2
1U_0402_6.3 V6K~D
12
1 2
@
1 2
@
1 2
@
1 2
RH33 33_ 0402_5%~D
1 2
RH32 33_ 0402_5%~D
1 2
RH36 33_ 0402_5%~D
1 2
RH34 33_ 0402_5%~D
27P_0402_50V8J~D
@
CH141
PCH_AZ_SDOUT
PCH_AZ_SYNC_Q
PCH_AZ_RST#
PCH_AZ_BITCLK
PCH_RTCX1_R
12
1 2
RH286 0_0402_5% ~D
YH1
32.768KHZ_12 .5PF_Q13FC1350000~D
PCH_AZ_CODEC_SDIN034
HDA_SDO32
DP_PCH_HPD23
100_0402_1%~D
12
RH48
RH50 1K _0402_1%~D
100_0402_1%~D
100_0402_1%~D
12
12
RH47
RH49
PCH_RTCX1
12
RH2
10M_0402_ 5%~D
PCH_RTCX2
SRTCRST#
INTRUDER#
PCH_INTVRMEN
PCH_RTCRST#
PCH_AZ_BITCLK
PCH_AZ_SYNC
HDA_SPKR34
1 2
DP_PCH_HPD+5VS
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
HDA_SPKR
PCH_AZ_RST#
PCH_AZ_CODEC_SDIN0
PCH_AZ_SDOUT
PCH_GPIO33
1 2
RH289 0_0402_5%~ D
T122 PAD~D@
PCH_TP25
UH1A
B5
RTCX1
B4
RTCX2
B9
SRTCRST#
A8
INTRUDER#
G10
INTVRMEN
D9
RTCRST#
B25
HDA_BCLK
A22
HDA_SYNC
AL10
SPKR
C24
HDA_RST#
L22
HDA_SDI0
K22
HDA_SDI1
G22
HDA_SDI2
F22
HDA_SDI3
A24
HDA_SDO
B17
DOCKEN#/GPIO33
C22
HDA_DOCK_RST#/GPIO13
AB3
JTAG_TCK
AD1
JTAG_TMS
AE2
JTAG_TDI
AD3
JTAG_TDO
F8
TP25
C26
TP22
AB6
TP20
LPT_PCH_M_EDS
JTAGRTC AZALIA
LYNXPOINT_BGA695
5
1 OF 11
+3VS
PCH_GPIO21
BBS_BIT0_R
PCH_SATALED#
BC8
SATA_RXN_0
SATA_RXP_0
SATA_TXN_0
SATA_TXP_0
SATA_RXN_1
SATA_RXP_1
SATA_TXN_1
SATA_TXP_1
SATA
SATA_RXN_2
SATA_RXP_2
SATA_TXN_2
SATA_TXP_2
SATA_RXN_3
SATA_RXP_3
SATA_TXN_3
SATA_TXP_3
SATA_RXN4/PERN1
SATA_RXP4/PERP1
SATA_TXN4/PETN1
SATA_TXP4/PETP1
SATA_RXN5/PERN2
SATA_RXP5/PERP2
SATA_TXN5/PETN2
SATA_TXP5/PETP2
SATA_RCOMP
SATALED#
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA_IREF
TP9
TP8
SATA_PRX_DTX_N0
BE8
SATA_PRX_DTX_P0
AW8
SATA_PTX_DRX_N0
AY8
SATA_PTX_DRX_P0
BC10
BE10
AV10
AW10
BB9
SATA_ODD_PRX_DTX_N2
BD9
SATA_ODD_PRX_DTX_P2
AY13
SATA_ODD_PTX_DRX_N2
AW13
SATA_ODD_PTX_DRX_P2
BC12
MSATA_PRX_DTX_N3
BE12
MSATA_PRX_DTX_P3
AR13
MSATA_PTX_DRX_N3
AT13
MSATA_PTX_DRX_P3
BD13
PCIE_PRX_WLANTX_N1
BB13
PCIE_PRX_WLANTX_P1
AV15
PCIE_PTX_WLANRX_N1
AW15
PCIE_PTX_WLANRX_P1
BC14
PCIE_PRX_WANTX_N2
BE14
PCIE_PRX_WANTX_P2
AP15
PCIE_PTX_WANRX_N2
AR15
PCIE_PTX_WANRX_P2
AY5
SATA_COMP
AP3
PCH_SATALED#
AT1
PCH_GPIO21
AU2
BBS_BIT0_R
BD4
SATA_IREF
BA2
BB2
T161PAD~ D @
T155PAD~ D @
SATA_PRX_DTX_N0 38
SATA_PRX_DTX_P0 38
SATA_PTX_DRX_N0 38
SATA_PTX_DRX_P0 38
SATA_ODD_PRX_DTX_N2 39
SATA_ODD_PRX_DTX_P2 39
SATA_ODD_PTX_DRX_N2 39
SATA_ODD_PTX_DRX_P2 39
MSATA_PRX_DTX_N3 39
MSATA_PRX_DTX_P3 39
MSATA_PTX_DRX_N3 39
MSATA_PTX_DRX_P3 39
PCIE_PRX_WLANTX_N1 40
PCIE_PRX_WLANTX_P1 40
PCIE_PTX_WLANRX_N1 40
PCIE_PTX_WLANRX_P1 40
PCIE_PRX_WANTX_N2 40
PCIE_PRX_WANTX_P2 40
PCIE_PTX_WANRX_N2 40
PCIE_PTX_WANRX_P2 40
PCH_SATALED# 37
12
+1.5VS
RH410_0402_1%~ D
1 2
1 2
RH3010K_0402_5 %~D
12
RH524.7K_0402_5 %~D
RH5510K_0402_5 %~D
HDD1
ODD/HDD2 Bay
mSATA
MiniWLAN (Mini Card 1)
MiniDMC (Mini Card 2)
SATA Impedance Compensation
+1.5VS
SATA_COMP
CAD note:
Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.
1 2
RH407.5K_0402_1 %~D
2
Security Classification
Security Classification
Security Classification
2012/02/28 2013/02/27
2012/02/28 2013/02/27
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
5
4
3
2012/02/28 2013/02/27
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (1/9) RTC,HDA,SATA,XDP
PCH (1/9) RTC,HDA,SATA,XDP
PCH (1/9) RTC,HDA,SATA,XDP
LA-9201P
LA-9201P
LA-9201P
1
14 6 6Thursday, August 16 , 2012
14 6 6Thursday, August 16 , 2012
14 6 6Thursday, August 16 , 2012
0.1
0.1
0.1
5
4
3
2
1
+3VS
5
1
B
2
A
3
RH139 64 9_0402_1%~D
PCH_INV_PWM24
IGPU_BKLT_EN24
PCH_ENVDD24 ,32
DGPU_SELECT#24, 27
HDMI_IN_PWM SEL#24
WL_OFF#40
DSWODVREN - ON DIE DSW VR ENABLE
HIGH = ENABLED (DEFAULT)
LOW = DISABLED
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
+1.5VS
+1.5VS
330K_0402_1%~D
1 2
330K_0402_1%~D
1 2
@
@
@
@
RH191
@
RH178
PCH_PWROK
IMVP_PWRGD
PCH_RSMRST#_R
PCH_DPWROK 32
PCIE_WAKE# 32,33,40
1 2
RH357 0_0402_5%~ D
+3VS
CH143
@
1 2
5
0.1U_0402_2 5V6K~D
1
D D
+3V_PCH
1 2
RH318 10K_0402 _5%~D@
1 2
RH149 10K_0402 _5%~D
1 2
@
RH148 10K_0402 _5%~D
1 2
RH153 10K_0402 _5%~D
1 2
RH172 10K_0402 _5%~D
+3VS
1 2
RH138 8.2K_0402 _5%~D
1 2
RH152 8.2K_0402 _5%~D@
DMI_CTX_PRX_N05
DMI_CTX_PRX_N15
DMI_CTX_PRX_N25
DMI_CTX_PRX_N35
DMI_CTX_PRX_P05
+1.5VS
+1.5VS
RH379
10K_0402_5 %
QH21A
DMI_CTX_PRX_P15
DMI_CTX_PRX_P25
DMI_CTX_PRX_P35
DMI_CRX_PTX_N05
DMI_CRX_PTX_N15
DMI_CRX_PTX_N25
DMI_CRX_PTX_N35
DMI_CRX_PTX_P05
DMI_CRX_PTX_P15
DMI_CRX_PTX_P25
DMI_CRX_PTX_P35
RH43 0_0402_1%~D
RH204 7.5K_0402 _1%~D
RH114 0_0402_5%~ D@
RH193 0_0402_5%~ D
RH144 0_0402_5%~ D
RH150 0_0402_5%~ D
RH320 0_0402_5%~ D
RH185 0_0402_5%~ D
RH200 0_0402_5%~ D
RH163 0_0402_5%~ D
RH156 8.2K_0402_5 %~D
+3V_PCH
12
61
2
C C
SG_AMD_BKL24,32
SYS_PWROK6
PCH_PWROK32
PM_DRAM_PW RGD6
PCH_RSMRST#32
B B
A A
SUSPWRDNACK32
PBTN_OUT#6,32
+PCH_VCCDSW3_ 3
ACIN32,36,56 ,63
2N7002DW-T/R7 _SOT363-6
SUS_STAT#
SUSPWRDNACK
PCIE_WAKE#
WAKE#
PCH_RI#
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
T140 PAD~D@
+3V_PCH
5
PM_CLKRUN#
ME_RESET#
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
12
DMI_IREF
T139 PAD~D@
T123 PAD~D@
12
3
4
DMI_RCOMP
SUSACK#_R
SYS_RESET#
SYS_PWROK_R
PCH_PWROK_R
PM_APWROK_R
PM_DRAM_PW RGD_R
PCH_RSMRST#_R
ME_SUS_PWR_ ACK_R
SIO_PWRBTN#_R
PCH_BATLOW#
PCH_RI#
RH378
10K_0402_5 %
ACIN_PCH
QH21B
2N7002DW-T/R7 _SOT363-6
ACIN_PCH
XDP_DBRESET#6
RH199 8.2K_0402_5%~ D@
UH1B
AW22
DMI_RXN_0
AR20
DMI_RXN_1
AP17
DMI_RXN_2
AV20
DMI_RXN_3
AY22
DMI_RXP_0
AP20
DMI_RXP_1
AR17
DMI_RXP_2
AW20
DMI_RXP_3
BD21
DMI_TXN_0
BE20
DMI_TXN_1
BD17
DMI_TXN_2
BE18
DMI_TXN_3
BB21
DMI_TXP_0
BC20
DMI_TXP_1
BB17
DMI_TXP_2
BC18
DMI_TXP_3
BE16
DMI_IREF
AW17
TP12
AV17
TP7
AY17
DMI_RCOMP
R6
SUSACK#
AM1
SYS_RESET#
AD7
SYS_PWROK
F10
PWROK
AB7
APWROK
H3
DRAMPWROK
J2
RSMRST#
J4
SUSWARN#/SUSPWRNACK/GPIO30
K1
PWRBTN#
E6
ACPRESENT/GPIO31
K7
BATLOW#/GPIO72
N4
RI#
AB10
TP21
D2
SLP_WLAN#/GPIO29
BBS_BIT1
1K_0402_1%~D
12
@
RH342
12
ME_RESET#
ME_SUS_PWR_ ACK_R SUSACK#_R
LPT_PCH_M_EDS
DMI
LYNXPOINT_BGA695
RH323 0_0402_5 %~D
5
System Power
Management
4 OF 11
BBS_BIT1 Boot BIOS Location
0 1 Reserved (NAND)
1 0
*
P
B
4
O
2
A
G
@
74AHC1G09GW_ TSSOP5~D
3
1 2
FDI_RXN_0
FDI_RXN_1
FDI
FDI_RXP_0
FDI_RXP_1
FDI_CSYNC
FDI_IREF
FDI_RCOMP
DSWVRMEN
DPWROK
CLKRUN#
SUS_STAT#/GPIO61
SUSCLK/GPIO62
SLP_S5#/GPIO63
SLP_S4#
SLP_S3#
SLP_SUS#
PMSYNCH
SLP_LAN#
Boot BIOS Strap
SATA_SLPD
(BBS_BIT0)
00 LPC
11 SPI
UC3
TP16
TP5
TP15
TP10
FDI_INT
TP17
TP13
WAKE#
SLP_A#
AJ35
AL35
AJ36
AL36
AV43
AY45
AV45
AW44
AL39
AL40
AT45
AU42
AU44
AR44
C8
L13
K3
AN7
U7
Y6
Y7
C6
H1
F3
F1
AY3
G5
PCI
SYS_RESET#
FDI_CSYNC
FDI_INT
FDI_IREF
FDI_RCOMP
DSWODVREN
PCH_DRWROK_R
WAKE#
RH188 0_04 02_5%~D@
PM_CLKRUN#
SUS_STAT#
PM_SLP_S5#
PM_SLP_S4#
PM_SLP_S3#
PM_SLP_SUS#
H_PM_SYNC
IMVP_PWRGD6,32,61
T175PAD~D @
T177PAD~D @
T178PAD~D @
T179PAD~D @
T144PAD~D @
T141PAD~D @
T147PAD~D @
T148PAD~D @
FDI_CSYNC 5
FDI_INT 5
12
RH420_0402_1% ~D
T145PAD~D @
T146PAD~D @
12
RH2067.5K_0402_1% ~D
1 2
RH167 0_ 0402_5%~D
1 2
RH186 0_ 0402_5%~D@
1 2
T129 PAD~D@
T126 PAD~D@
PM_SLP_S5# 32,36
T125 PAD~D
PM_SLP_S4# 32
T143 PAD~D
PM_SLP_S3# 32,36
T128 PAD~D
PM_SLP_SUS# 32
T127 PAD~D
H_PM_SYNC 6
+RTC_CELL
DSWODVREN
GPIO51 has internal pull up.
5
4
3
CH142
1 2
0.1U_0402_2 5V6K~D
P
4
SYS_PWROK
O
G
UH8
TC7SH08FU_SSOP5~D
1 2
PCH_INV_PWM
IGPU_BKLT_EN
PCH_ENVDD
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
DGPU_SELECT#
BBS_BIT1
HDMI_IN_PWM SEL#
WL_OFF#
T45
U44
V45
M43
M45
N42
N44
U40
U39
N36
K36
G36
H20
L20
K17
M20
A12
B13
C12
C10
A10
AL6
VGA_BLUE
VGA_GREEN
VGA_RED
VGA_DDC_CLK
VGA_DDC_DATA
VGA_HSYNC
VGA_VSYNC
DAC_IREF
VGA_IRTN
EDP_BKLTCTL
EDP_BKLTEN
EDP_VDDEN
PIRQA#
PIRQB#
PIRQC#
PIRQD#
GPIO50
GPIO52
GPIO54
GPIO51
GPIO53
GPIO55
LYNXPOINT_BGA695
LPT_PCH_M_EV
LVDSCRT
5UH1E
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPB_AUXN
DDPC_AUXN
DISPLAY
PCI
5 OF 11
DDPD_AUXN
DDPB_AUXP
DDPC_AUXP
DDPD_AUXP
DDPB_HPD
DDPC_HPD
DDPD_HPD
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
PME#
PLTRST#
PCH_PLTRST#
A16 SWAP OVERRIDE STRAP
STP_A16OVR
Compal Secret Data
Compal Secret Data
2012/02/28 2013/02/27
2012/02/28 2013/02/27
2012/02/28 2013/02/27
Compal Secret Data
LOW = A16 SWAP OVERRIDE
HIGH = DEFAULT
Deciphered Date
Deciphered Date
Deciphered Date
2
R40
PCH_DPB_HDMI_CL K
R39
PCH_DPB_HDMI_DAT
R35
R36
N40
PCH_DPD_CLK
N38
PCH_DPD_DAT
H45
K43
J42
H43
K45
J44
K40
PCH_HDMI_HPD
K38
H39
PCH_DMC_HPD
G17
BT_ON#
F17
DP_CBL_DET
L15
ODD_DA#
M15
FFS_INT1
AD10
Y11
PCH_PLTRST#
+3VS
5
1
P
B
2
A
G
3
PCH_DPB_HDMI_CL K 2 7
PCH_DPB_HDMI_DAT 27
PCH_DPD_CLK 30
PCH_DPD_DAT 30
PCH_HDMI_HPD 27
PCH_DMC_HPD 30
BT_ON# 40
DP_CBL_DET 23
ODD_DA# 39
T124 PAD~D@
0.1U_0402_2 5V6K~D
O
TC7SH08FU_SSOP5~D
FFS_INT1 38
PCH_PLTRST# 46
CH144
1 2
4
PLT_RST
UH3
BT_ON#
ODD_DA#
WL_OFF#
HDMI_IN_PWM SEL#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
LA-9201P
LA-9201P
LA-9201P
Date: Sheet of
Date: Sheet of
Date: Sheet of
+3VS
12
RH367
10K_0402_5 %~D
@
PLT_RST# 6,31,32 ,33,40
12
RH201
100K_0402_ 5%~D
+3VS
12
RH3668.2K_0402_5 %~D
12
RH3658.2K_0402 _5%~D
12
RH3628.2K_0402 _5%~D
12
RH3528.2K_0402 _5%~D
12
RH3248.2K_0402 _5%~D
12
RH3258.2K_0402 _5%~D
12
RH3268.2K_0402 _5%~D
12
RH3298.2K_0402 _5%~D
1 2
RH351 10K_0402 _5%~D@
PM_CLKRUN#
Compal Electronics, Inc.
PCH (2/9) DMI,FDI,PM,DP,CRT
PCH (2/9) DMI,FDI,PM,DP,CRT
PCH (2/9) DMI,FDI,PM,DP,CRT
15 6 6Tuesday, August 14 , 2012
15 6 6Tuesday, August 14 , 2012
1
15 6 6Tuesday, August 14 , 2012
HDMI
DMC
0.1
0.1
0.1
5
D D
4
3
2
1
UH1C
Y43
CLKOUT_PCIE_N_0
Y45
CLKOUT_PCIE_P_0
AB1
PCIECLKRQ0#/GPIO73
AA44
CLKOUT_PCIE_N_1
AA42
CLKOUT_PCIE_P_1
AF1
PCIECLKRQ1#/GPIO18
AB43
CLKOUT_PCIE_N_2
AB45
CLKOUT_PCIE_P_2
AF3
PCIECLKRQ2#/GPIO20/SMI#
AD43
CLKOUT_PCIE_N_3
AD45
CLKOUT_PCIE_P_3
T3
PCIECLKRQ3#/GPIO25
AF43
CLKOUT_PCIE_N_4
AF45
CLKOUT_PCIE_P_4
V3
PCIECLKRQ4#/GPIO26
AE44
CLKOUT_PCIE_N5
AE42
CLKOUT_PCIE_P_5
AA2
PCIECLKRQ5#/GPIO44
AB40
CLKOUT_PCIE_N_6
AB39
CLKOUT_PCIE_P_6
AE4
PCIECLKRQ6#/GPIO45
AJ44
CLKOUT_PCIE_N_7
AJ42
CLKOUT_PCIE_P_7
Y3
PCIECLKRQ7#/GPIO46
AH43
CLKOUT_ITPXDP
AH45
CLKOUT_ITPXDP_P
D44
CLKOUT_33MHZ0
E44
CLKOUT_33MHZ1
B42
CLKOUT_33MHZ2
F41
CLKOUT_33MHZ3
A40
CLKOUT_33MHZ4
CLOCK SIGNAL
LYNXPOINT_BGA695
1 2
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
T142 PAD~D@
T138 PAD~D@
MiniWLAN
(Mini Card 1)
DMC (Mini Card 2)
10/100/1G LAN
C C
B B
Card Reader
CLK_PCI_LPC32
CLK_DEBUG40
CLK_PCIE_MINI1 #40
CLK_PCIE_MINI140
+3V_PCH
MINI1CLK_REQ#4 0
CLK_PCIE_MINI2 #40
CLK_PCIE_MINI240
MINI2CLK_REQ#4 0
CLK_PCIE_LAN#3 3
CLK_PCIE_LAN33
LANCLK_REQ#33
CLK_PCIE_CD#31
CLK_PCIE_CD31
CDCLK_REQ#31
+3V_PCH
CLK_CPU_ITP#6
CLK_CPU_ITP6
CLK_PCI_LPBACK CLK_PCI0
CLK_PCI_LPC CLK_PCI1
RH307 0_0402_5 %~D
RH308 0_0402_5 %~D
RH142 10K_0402 _5%~D
RH99 0_0402_5%~D
RH98 0_0402_5%~D
RH145 10K_0402_5% ~D
+3VS
RH158 0_0402_5 %~D
RH147 0_0402_5 %~D
+3VS
RH28 10K_ 0402_5%~D
RH129 0_0402_5 %~D
RH124 0_0402_5 %~D
RH126 10K_0402 _5%~D
+3V_PCH
+3V_PCH
+3V_PCH
+3V_PCH
RH128 10K_0402 _5%~D
RH132 10K_0402 _5%~D
RH133 10K_0402 _5%~D
RH127 10K_0402 _5%~D
RH280 0_0402_5 %~D
RH281 0_0402_5 %~D
RH169 22_0402_ 5%~D
RH111 22_0402_ 5%~D
RH151 22_0402_ 5%~D
PCIE_MINI1#
PCIE_MINI1
MINI1CLK_REQ#
PCIE_MINI2#
PCIE_MINI2
MINI2CLK_REQ#
PCIE_LAN#
PCIE_LAN
LANCLK_REQ#
PCIE_EXP#
PCIE_EXP
CDCLK_REQ#
CLK_BCLK_ITP#
CLK_BCLK_ITP
CLK_PCI2CLK_DEBUG
CLK_PCI3
CLK_PCI4
LPT_PCH_M_EDS
5
2 OF 11
CLKOUT_PEG_A
CLKOUT_PEG_A_P
PEGA_CLKRQ#/GPIO47
CLKOUT_PEG_B
CLKOUT_PEG_B_P
PEGB_CLKRQ#/GPIO56
CLKOUT_DMI
CLKOUT_DMI_P
CLKOUT_DP
CLKOUT_DP_P
CLKOUT_DPNS
CLKOUT_DPNS_P
CLKIN_DMI
CLKIN_DMI_P
CLKIN_GND
CLKIN_GND_P
CLKIN_DOT96N
CLKIN_DOT96P
CLKIN_SATA
CLKIN_SATA_P
REFCLK14IN
CLKIN_33MHZLOOPBACK
XTAL25_IN
XTAL25_OUT
CLKOUTFLEX0/GPIO64
CLKOUTFLEX1/GPIO65
CLKOUTFLEX2/GPIO66
CLKOUTFLEX3/GPIO67
ICLK_IREF
TP19
TP18
DIFFCLK_BIASREF
AB35
AB36
AF6
Y39
Y38
U4
AF39
CLK_CPU_DMI#
AF40
CLK_CPU_DMI
AJ40
CLK_CPU_SSC_DPLL #
AJ39
CLK_CPU_SSC_DPLL
AF35
CLK_CPU_DPLL#
AF36
CLK_CPU_DPLL
AY24
CLK_BUF_DMI#
AW24
CLK_BUF_DMI
AR24
CLK_BUF_BCLK#
AT24
CLK_BUF_BCLK
H33
CLK_BUF_DOT96#
G33
CLK_BUF_DOT96
BE6
CLK_BUF_CKSSCD#
BC6
CLK_BUF_CKSSCD
F45
CLK_PCH_14M
D17
CLK_PCI_LPBACK
AL44
AM43
C40
F38
DMC_PCH_DET#
F36
PCH_GPIO66
F39
CAM_DET#
AM45
ICLK_IREF
AD39
AD38
AN44
PCH_CLK_BIASREF
CLK_PCIE_VGA#
CLK_PCIE_VGA
CLK_REQ_VGA#
XTAL25_IN
XTAL25_OUT
CAM_DET#
DMC_PCH_DET#
PCH_GPIO66
CLK_PCIE_VGA# 46
CLK_PCIE_VGA 46
CLK_REQ_VGA# 4 6
1 2
RH76 10K_0402_5 %~D
12
RH12510K_0402_5 %~D
T176PAD~D @
1 2
T149PAD~D @
T150PAD~D @
1 2
+3V_PCH
+3V_PCH
CLK_CPU_DMI# 6
CLK_CPU_DMI 6
CLK_CPU_SSC_DPLL # 6
CLK_CPU_SSC_DPLL 6
CLK_CPU_DPLL# 6
CLK_CPU_DPLL 6
DMC_PCH_DET# 40
CAM_DET# 25
RH540_0402_1%~ D
+1.05V_+1.5V _RUN
RH2087.5K_0402 _1%~D
1 2
1 2
1 2
+1.5VS
RH21610K_0402_5 %~D
RH21710K_0402_5 %~D
RH21810K_0402_5 %~D
CLK_BUF_DMI#
CLK_BUF_DMI
CLK_BUF_BCLK#
CLK_BUF_BCLK
CLK_BUF_DOT96#
CLK_BUF_DOT96
CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD
CLK_PCH_14M
1 2
RH74 1 0K_0402_5%~D
1 2
RH75 1 0K_0402_5%~D
1 2
RH105 10K_0402_ 5%~D
1 2
RH157 10K_0402_ 5%~D
1 2
RH143 10K_0402_ 5%~D
1 2
RH130 10K_0402_ 5%~D
1 2
RH146 10K_0402_ 5%~D
1 2
RH155 10K_0402_ 5%~D
1 2
RH205 10K_0402_ 5%~D
CLOCK TERMINATION for FCIM and need close to PCH
12
1 2
RH309 0_0402_5 %~D
RH131 1M_0402 _5%~D
YH4
3
4
OUT
GND
IN
GND
+3VS
25MHZ_10PF_ Q22FA2380049900~D
8.2P_0402_50V8D~D
2
CH18
1
XTAL25_IN_R
1
2
8.2P_0402_50V8D~D
CH19
2
1
A A
Security Classification
Security Classification
Security Classification
2012/02/28 2013/02/27
2012/02/28 2013/02/27
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
5
4
3
2012/02/28 2013/02/27
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (3/9) CLK
PCH (3/9) CLK
PCH (3/9) CLK
LA-9201P
LA-9201P
LA-9201P
1
16 6 6Tuesday, August 14 , 2012
16 6 6Tuesday, August 14 , 2012
16 6 6Tuesday, August 14 , 2012
0.1
0.1
0.1
5
D D
+3VS
1 2
RH337 10K_0402_5%~D
C C
SERIRQ
LPC_AD032,40
LPC_AD132,40
LPC_AD232,40
LPC_AD332,40
LPC_FRAME#32,40
SERIRQ32
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
SERIRQ
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_SI
PCH_SPI_SO
PCH_SPI_DO2
PCH_SPI_DO3
4
A20
C20
A18
C18
B21
D21
G20
AL11
AJ11
AJ7
AL7
AJ10
AH1
AH3
AJ4
AJ2
MEM_SMBCLK
MEM_SMBDATA
UH1D
LAD_0
LAD_1
LAD_2
LAD_3
LFRAME#
LDRQ0#
LDRQ1#/GPIO23
SERIRQ
SPI_CLK
SPI_CS0#
SPI_CS1#
SPI_CS2#
SPI_MOSI
SPI_MISO
SPI_IO2
SPI_IO3
SPILPC
3
QH9B
DMN66D0LDW -7_SOT363-6~D
LPT_PCH_M_EDS
SMBus
C-Link
Thermal
+3VS
RH304
2
2.2K_0402_5 %~D
6 1
5
SML1ALERT#/PCHHOT#/GPIO74
QH9A
DMN66D0LDW -7_SOT363-6~D
4
SMBALERT#/GPIO11
SMBDATA
SML0ALERT#/GPIO60
SML0CLK
SML0DATA
SML1CLK/GPIO58
SML1DATA/GPIO75
+3VS
12
SMBCLK
CL_CLK
CL_DATA
CL_RST#
TP1
TP2
TP4
TP3
TD_IREF
3
12
N7
R10
U11
N8
U8
R7
H6
K6
N11
AF11
AF10
AF7
BA45
BC45
BE43
BE44
AY43
RH310
2.2K_0402_5 %~D
PCH_SMBCLK 6,1 2,13,38,39,40,42
PCH_SMBDATA 6,12, 13,38,39,40,42
1 2
RH368 0_0402_5%~D
PCH_LID_SW_ IN#
MEM_SMBCLK
MEM_SMBDATA
DDR_HVREF_RST_PCH
LAN_SMBCLK
LAN_SMBDATA
PCH_GPIO74
SML1CLK
SML1DATA
PCH_TD_IREF
RH322 8.2K_0402 _1%
1 2
RH369 0_0402_5%~D
@
T130PAD~D @
T133PAD~D @
T131PAD~D @
T132PAD~D @
1 2
SML1CLK
SML1DATA
+3VS
5
3
QH10B
DMN66D0LDW -7
EC_LID_OUT# 32
LID_SW_IN# 32,3 6,37
2
6 1
QH10A
4
2
DMN66D0LDW -7
EC_SMB_CK2 32,42,4 3,46
EC_SMB_DA2 32,42,4 3,46
MEM_SMBCLK
MEM_SMBDATA
DDR_HVREF_RST_PCH
PCH_GPIO74
SML1CLK
SML1DATA
LAN_SMBCLK
LAN_SMBDATA
1 2
1 2
1
+3V_PCH
12
RH3022.2K_0402_5 %~D
12
RH3032.2K_0402_5 %~D
12
RH3001K_0402_1% ~D
12
RH30110K_0402_5 %~D
RH2982.2K_0402_5 %~D
RH2992.2K_0402_5 %~D
+3V_PCH
12
RH3052.2K_0402_5 %~D
12
RH3062.2K_0402_5 %~D
VCC
/HOLD
CLK
DIO
3 OF 11 5
+3V_PCH
8
7
6
PCH_SPI_CLK_R
5
PCH_SPI_SI_R
CH155
1 2
0.1U_0402_2 5V6K~D
1 2
RH373 33_0402_5% ~D
1 2
RH376 33_0402_5% ~D
1 2
RH377 33_0402_5% ~D
PCH_SPI_DO3SPI_PCH_DO3_R
PCH_SPI_CLK
PCH_SPI_SI
PCH_SPI_CLK
RH60
@
33_0402_5% ~D
1 2
22P_0402_50V8J~D
1
@
CH8
2
Reserve for EMI please
close to UH14
LYNXPOINT_BGA695
+3V_PCH
1 2
RH370 3.3K_0402_5%~ D
1 2
RH371 3.3K_0402_5%~ D
B B
A A
SPI_PCH_DO3_R
SPI_PCH_DO2_R
PCH_SPI_CS0# PCH_SPI _CS0#_R
PCH_SPI_SO PCH_SPI_S0_R
PCH_SPI_DO2
1 2
RH374 47_0402_5 %~D
1 2
RH372 33_0402_5 %~D
1 2
RH375 33_0402_5 %~D
+3V_PCH
1 2
RH58
3.3K_0402_5 %~D
@
SPI_PCH_DO2_R
200 MIL SO8
64Mb Flash ROM
UH14
1
/CS
2
DO
3
/WP
4
GND
W25Q64FVSSI G_SO8~D
Security Classification
Security Classification
Security Classification
2012/02/28 2013/02/27
2012/02/28 2013/02/27
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
5
4
3
2012/02/28 2013/02/27
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (4/9) SPI, SMBUS,LPC
PCH (4/9) SPI, SMBUS,LPC
PCH (4/9) SPI, SMBUS,LPC
LA-9201P
LA-9201P
LA-9201P
1
17 6 6Monday, Augu st 20, 2012
17 6 6Monday, Augu st 20, 2012
17 6 6Monday, Augu st 20, 2012
0.1
0.1
0.1
5
D D
4
3
2
1
UH1I
AW31
PERN1/USB3RN3
AY31
PERP1/USB3RP3
BE32
PETN1/USB3TN3
BC32
PETP1/USB3TP3
AT31
PERN2/USB3RN4
AR31
PERP2/USB3RP4
BD33
PETN2/USB3TN4
BB33
PETP2/USB3TP4
PCIE_PRX_GLANTX_N133
10/100/1G LAN
CARD READER
C C
B B
PCIE_PRX_GLANTX_P13 3
PCIE_PTX_GLANRX_N133
PCIE_PTX_GLANRX_P133
PCIE_PRX_CARDTX_N431
PCIE_PRX_CARDTX_P431
PCIE_PTX_CARDRX_N431
PCIE_PTX_CARDRX_P431
1 2
CH149 0.1U_0402_25V6 K~D
1 2
CH150 0.1U_0402_25V6 K~D
1 2
CH153 0.1U_0402_25V6 K~D
1 2
CH154 0.1U_0402_25V6 K~D
+1.5VS
+1.5VS
RH51 0_0402_1%~D
RH210 7.5K_0402_1 %~D
PCIE_PRX_GLANTX_N1
PCIE_PRX_GLANTX_P1
PCIE_PTX_GLANRX_N1_C
PCIE_PTX_GLANRX_P1_C
PCIE_PRX_CARDTX_N4
PCIE_PRX_CARDTX_P4
PCIE_PTX_CARDRX_N4_C
PCIE_PTX_CARDRX_P4_C
1 2
T134 PAD~D@
T136 PAD~D@
1 2
PCH_PCIE_IREF
PCH_PCIE_RCOMP
AW33
AY33
BE34
BC34
AT33
AR33
BE36
BC36
AW36
AV36
BD37
BB37
AY38
AW38
BC38
BE38
AT40
AT39
BE40
BC40
AN38
AN39
BD42
BD41
BE30
BC30
BB29
BD29
PERN_3
PERP_3
PETN_3
PETP_3
PERN_4
PERP_4
PETN_4
PETP_4
PERN_5
PERP_5
PETN_5
PETP_5
PERN_6
PERP_6
PETN_6
PETP_6
PERN_7
PERP_7
PETN_7
PETP_7
PERN_8
PERP_8
PETN_8
PETP_8
PCIE_IREF
TP11
TP6
PCIE_RCOMP
LPT_PCH_M_EDS
LYNXPOINT_BGA695
PCIe
USB
9 OF 11 5
USB2N0
USB2P0
USB2N1
USB2P1
USB2N2
USB2P2
USB2N3
USB2P3
USB2N4
USB2P4
USB2N5
USB2P5
USB2N6
USB2P6
USB2N7
USB2P7
USB2N8
USB2P8
USB2N9
USB2P9
USB2N10
USB2P10
USB2N11
USB2P11
USB2N12
USB2P12
USB2N13
USB2P13
USB3RN1
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USB3RN5
USB3RP5
USB3TN5
USB3TP5
USB3RN6
USB3RP6
USB3TN6
USB3TP6
USBRBIAS#
USBRBIAS
TP24
TP23
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14
B37
D37
A38
C38
A36
C36
A34
C34
B33
D33
F31
G31
K31
L31
G29
H29
A32
C32
A30
C30
B29
D29
A28
C28
G26
F26
F24
G24
AR26
AP26
BE24
BD23
AW26
AV26
BD25
BC24
AW29
AV29
BE26
BC26
AR29
AP29
BD27
BE28
K24
K26
M33
L33
P3
USB_OC0#
V1
USB_OC1#
U2
USB_OC2#
P1
M3
USB_OC4#
T1
USB_OC5#
N2
USB_OC6#
M1
USB_OC7#
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N11
USB20_P11
USB20_N12
USB20_P12
USB3RN1
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USB3RN5
USB3RP5
USB3TN5
USB3TP5
USBRBIAS
USB20_N0 41
USB20_P0 41
USB20_N1 41
USB20_P1 41
USB20_N2 42
USB20_P2 42
USB20_N4 40
USB20_P4 40
USB20_N5 40
USB20_P5 40
USB20_N6 36
USB20_P6 36
USB20_N11 25
USB20_P11 25
USB20_N12 42
USB20_P12 42
USB3RN1 41
USB3RP1 41
USB3TN1 41
USB3TP1 41
USB3RN2 41
USB3RP2 41
USB3TN2 41
USB3TP2 41
USB3RN5 42
USB3RP5 42
USB3TN5 42
USB3TP5 42
T135PAD~ D @
T137PAD~ D @
USB_OC0# 41
USB_OC1# 41
USB_OC2# 42
JUSB1
JUSB2
JUSB3
Mini Card(WLAN)
Mini Card(DMC)
ELC LED
eDP Camera
VPK K/B
P1: JUSB1
P2: JUSB2
P5: JUSB3
USBRBIAS
CAD NOTE:
Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15 mils.
22.6_0402_1%~D
12
USB_OC4#
USB_OC7#USB_OC3#
USB_OC6#
USB_OC3#
USB_OC0#
USB_OC5#
USB_OC2#
USB_OC1#
RH160
RPH1
4 5
3 6
2 7
1 8
10K_1206_8 P4R_5%~D
RPH2
4 5
3 6
2 7
1 8
10K_1206_8 P4R_5%~D
+3V_PCH
A A
Security Classification
Security Classification
Security Classification
2012/02/28 2013/02/27
2012/02/28 2013/02/27
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
5
4
3
2012/02/28 2013/02/27
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (5/9) PCIE,USB
PCH (5/9) PCIE,USB
PCH (5/9) PCIE,USB
LA-9201P
LA-9201P
LA-9201P
1
18 6 6Tuesday, August 14 , 2012
18 6 6Tuesday, August 14 , 2012
18 6 6Tuesday, August 14 , 2012
0.1
0.1
0.1
5
4
3
2
1
D D
+3VS
1 2
RH270 10K_0402 _5%~D
1 2
RH271 10K_0402 _5%~D
1 2
RH164 10K_0402 _5%~D
RH179 10K_0402 _5%~D
1 2
RH256 10K_0402 _5%~D
1 2
RH258 10K_0402 _5%~D
1 2
RH261 10K_0402 _5%~D
1 2
RH263 10K_0402 _5%~D
+3V_PCH
RH187 10K_0402 _5%~D
1 2
RH354 1K_0402_ 1%~D
RH182 10K_0402 _5%~D
RH264 10K_0402 _5%~D
RH269 10K_0402_5% ~D@
C C
+3V_PCH
4.7K_0402_5%~D
RH53
1 2
PCH_GPIO28
1K_0402_1%~D
12
@
RH353
12
PCH_GPIO22
PCH_GPIO39
PCH_GPIO70
EDP_CAB_DET#
12
12
12
12
PCH_GPIO27
DMC_RADIO_OFF#
DGPU_EDIDSEL#
DGPU_HPD_INT#
STP_PCI#
HDD_DET#
PCH_GPIO15
ODD_EN#
PCH_GPIO35
DMC_RADIO_OFF#40
DGPU_EDIDSEL#24,27
DGPU_HPD_INT#27,30
EC_SCI#32
EC_SMI#32
ODD_EN#39
PCH_GPIO3527
ODD_DETECT#39
FFS_INT238,39
HDD_DET#38
DGPU_BKL_PWM _SEL#24
EDP_CAB_DET#25
WiGi_RADIO_DIS #40
1 2
RH162 0_0402_5 %~D
DMC_RDIO_OFF#
DGPU_EDIDSEL#
DGPU_HPD_INT#
EC_SCI#
EC_SMI#
PCH_GPIO15
PCH_GPIO16
PCH_GPIO22
ODD_EN#
PCH_GPIO27
PCH_GPIO28
STP_PCI#
PCH_GPIO35
ODD_DETECT#
PCH_GPIO37
DGPU_PRSNT#
PCH_GPIO39
FFS_INT2
PCH_GPIO49
HDD_DET#
DGPU_BLK_PWM _SLE#
EDP_CAB_DET#
PCH_GPIO70
WiGi_RADIO_DIS #
TP_VSS_NCTF
UH1F
AT8
BMBUSY#/GPIO0
F13
TACH1/GPIO1
A14
TACH2/GPIO6
G15
TACH3/GPIO7
Y1
GPIO8
K13
LAN_PHY_PWR_CTRL/GPIO12
AB11
GPIO15
AN2
SATA4GP/GPIO16
C14
TACH0/GPIO17
BB4
SCLOCK/GPIO22
Y10
GPIO24
R11
GPIO27
AD11
GPIO28
AN6
GPIO34
AP1
GPIO35/NMI#
AT3
SATA2GP/GPIO36
AK1
SATA3GP/GPIO37
AT7
SLOAD/GPIO38
AM3
SDATAOUT0/GPIO39
AN4
SDATAOUT1/GPIO48
AK3
SATA5GP/GPIO49
U12
GPIO57
C16
TACH4/GPIO68
D13
TACH5/GPIO69
G13
TACH6/GPIO70
H15
TACH7/GPIO71
BE41
VSS
BE5
VSS
C45
VSS
A5
VSS
LPT_PCH_M_EDS
LYNXPOINT_BGA695
GPIO
NCTF
6 OF 11 5
CPU/Misc
TP14
PECI
RCIN#
PROCPWRGD
THRMTRIP#
PLTRST_PROC#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AN10
AY1
AT6
AV3
AV1
AU4
N10
A2
A41
A43
A44
B1
B2
B44
B45
BA1
BC1
BD1
BD2
BD44
BD45
BE2
BE3
D1
E1
E45
A4
GATEA20
12
RH184
@
0_0402_5%~ D
KB_RST#
H_CPUPWRGD
PCH_THRMTRIP#_R_R
CPU_PLTRST#
PCH_VSS_A44
PCH_VSS_B45
PCH_VSS_BD1
GATEA20 32
H_PECI 6,32
KB_RST# 32
H_CPUPWRGD 6
CPU_PLTRST# 6
RH262 39 0_0402_5%
1 2
0_0402_5%~D
@
RH166
0_0402_5%~D
RH165
GATEA20
KB_RST#
1 2
PCH_VSS_A44
1 2
H_THERMTRIP# 6, 46
0_0402_5%~D
0_0402_5%~D
+5VALW+5VS
@
RH175
RH168
12
RH16110K_0402_ 5%~D
12
RH20310K_0402_ 5%~D
1 2
PCH_VSS_B45
1 2
+3VS
0_0402_5%~D
RH170
PCH_VSS_BD1
1 2
PLL ON DIE VR ENABLE
ENABLED - HIGH(DEFAULT)
DISABLED - LOW
B B
A A
+3VS
1 2
RH272 10K_0402_5% ~D@
RH266 10K_0402_5% ~D
RH265 10K_0402_5% ~D
RH268 10K_0402_5% ~D@
Config
USB X4,PCIEX8,SATAX6
12
12
12
PCH_GPIO16
PCH_GPIO49
PCH_GPIO16
PCH_GPIO49
GPIO16,49
11
01USB X6,PCIEX8,SATAX4
For BIOS setting dGPU present
LOW - dGPU exist*
+3VS
@
1 2
RH260 10K_0402 _5%~D
1 2
RH259 10K_0402 _5%~D
DGPU_PRSNT#
DGPU_PRSNT#
+3VS
12
12
12
ODD_DETECT#
PCH_GPIO37
ODD_DETECT#
PCH_GPIO37
RH176 1K_0402_ 1%~D
1 2
RH171 200K_040 2_5%@
RH174 10K_0402 _5%~D@
RH181 10K_0402 _5%~D
SATA2GP/GPIO36 , SATA3GP/GPIO37 SAMPLED AT RISING EDGE OF PWROK.
WEAK INTERNAL PULL-DOWN.(WEAK INTERNAL PULL-DOWN IS DISABLED AFTER
PLRST_N DE-ASSERTS).
NOTE: THIS SIGNAL SHOLD NOT BE PULLED HIGH WHEN STRAP IS SAMPLED.
Security Classification
Security Classification
Security Classification
2012/02/28 2013/02/27
2012/02/28 2013/02/27
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
5
4
3
2012/02/28 2013/02/27
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (6/9) GPIO,MISC,NTFC
PCH (6/9) GPIO,MISC,NTFC
PCH (6/9) GPIO,MISC,NTFC
LA-9201P
LA-9201P
LA-9201P
1
19 6 6Tuesday, August 14 , 2012
19 6 6Tuesday, August 14 , 2012
19 6 6Tuesday, August 14 , 2012
0.1
0.1
0.1
5
D D
C C
B B
+1.05VS
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1
1
CH30
CH32
2
2
+1.05V
22U_0805_6.3V6M~D
1
CH64
2
C_0805NEW
1 2
RH37 5.11 _0402_1%~D@
1U_0402_6.3V6K~D
+PCH_VCCDSW_R
@
1
CH34
2
1U_0402_6.3V6K~D
1
2
1U_0402_6.3V6K~D
1
2
1U_0402_6.3V6K~D
1
CH33
2
1U_0402_6.3V6K~D
1
CH35
2
+PCH_VCCDSW
CH31
+PCH_VCCDSW
CH36
AA24
AA26
AD20
AD22
AD24
AD26
AD28
AE18
AE20
AE22
AE24
AE26
AG18
AG20
AG22
AG24
AA18
Y26
U14
U18
U20
U22
U24
V18
V20
V22
V24
Y18
Y20
Y22
4
UH1G
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
DCPSUSBYP
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
+1.5VS +1.05V_+1.5V _RUN
+1.05VS
LPT_PCH_M_EDS
CRT DAC
FDI
HVCMOS
Core
USB3
PCIe/DMI
SATA
VCCMPHY
LYNXPOINT_BGA695
RH197 0_0603_5 %~D
RH198 0_0603_5 %~D@
7 OF 11 5
12
12
VCCADAC1_5
VSS
VCCADACBG3_3
VCCVRM
VCCIO
VCCIO
VCC3_3_R30
VCC3_3_R32
DCPSUS1
VCCSUS3_3
VCCSUS3_3
DCPSUS3
DCPSUS3
VCCIO
VCCVRM
VCCVRM
VCCVRM
VCCIO
VCCVRM
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
P45
P43
M31
BB44
AN34
AN35
R30
R32
Y12
+PCH_USB_DCPSUS1
AJ30
AJ32
AJ26
+PCH_USB_DCPSUS3
AJ28
AK20
AK26
AK28
BE22
AK18
AN11
AK22
AM18
AM20
AM22
AP22
AR22
AT22
3
LH1
+VCCADAC
0.1U_0402_10V7K~D
0.01U_0402_16V7K~D
1
1
CH57
2
2
10U_0603_6.3V6M~D
1
CH80
2
BLM18PG181SN 1_0603~D
CH56
12
1 2
2
RH2110_0603_5%~ D
+1.5VS
1
PCH Power Rail Table
Voltage Rail
Voltage S0 Iccmax Current (A)
VCC 1.05V 1.29 A
+3VS
+1.05VS
+1.05VS
+1.05V_+1.5V _RUN
+1.05VS
+3VS
+3V_PCH
0.1U_0402_10V7K~D
1
CH60
2
+1.05V_+1.5V _RUN
+1.05V_+1.5V _RUN
10U_0603_6.3V6M~D
@
+1.05VS
1U_0402_6.3V6K~D
1
CH86
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CH47
2
1U_0402_6.3V6K~D
1
1
CH46
CH45
2
2
1
CH85
2
10U_0603_6.3V6M~D
1
CH44
2
1
2
0.1U_0402_10V7K~D
1
CH38
2
+1.05V_+1.5V _RUN
10U_0603_6.3V6M~D
@
1
CH83
2
+PCH_USB_DCPSUS1
+PCH_USB_DCPSUS3
10U_0603_6.3V6M~D
@
1
CH40
2
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1
2
1
2
1
2
@
1
CH81
CH48
2
10U_0603_6.3V6M~D
@
CH82
+1.05V
12
1U_0402_6.3V6K~D
@
CH61
1U_0402_6.3V6K~D
@
CH39
1 2
RH3600_0402_5 %~D @
+1.05V
RH2090_0603_5%~D @
VCCIO 1.05V 3.629 A
VCCADAC1_5 1.5V 0.070 A
VCCADAC3_3 0.0133 A3.3V
VCCCLK 0.306 A1.05V
VCCCLK3_3 0.055 A
3.3V
VCCVRM 0.179 A1.5V
VCC3_3 3.3V 0.133 A
VCCASW 1.05V 0.67 A
VCCSUSHDA 3.3V 0.01 A
VCCSPI 3.3V 0.022 A
VCCSUS3_3 3.3V 0.261 A
VCCDSW3_3 3.3V 0.015 A
V_PROC_IO 1.05V 0.004 A
A A
Security Classification
Security Classification
Security Classification
2012/02/28 2013/02/27
2012/02/28 2013/02/27
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
5
4
3
2012/02/28 2013/02/27
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (7/9) Power
PCH (7/9) Power
PCH (7/9) Power
LA-9201P
LA-9201P
LA-9201P
1
20 6 6Tuesday, August 14 , 2012
20 6 6Tuesday, August 14 , 2012
20 6 6Tuesday, August 14 , 2012
0.1
0.1
0.1
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