Compal LA-9201P Schematics

A

B

C

D

E

MODEL NAME :

PCB NO :

BOM P/N :

LA-9201P

4619KO31L01

VAR00

4619K031L02

1 1

Dell/Compal Confidential

2 2

Mariner 14

Schematic Document

DISCRETE VGA N14P-GT and N14E-GE (optimus)

2012-06-06

3 3

Highlight the short pad for 0 ohm

CONN@ Connector Component

up@ Upsell

en@ Entry

Rev: 0.1

X76@ VARM(SAMSUNG,Hynix)

N14P@ N14P-GT

N14E@ N14E-GE

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

2011/06/02 2012/06/02

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Date: Sheet of

Compal Electronics, Inc.

Cover Page

LA-9201P

E

1 66Friday, August 10, 2012

0.1

A

B

C

D

E

FFS eDP Conn.

eDP MUX

PS8321

HDMI to LVDS SW

STDP6038

1 1

HDMI 1.3 In HDMI 1.4a Out Conn.

HDMI SW TS3DV421

Re-driver

PS121

eDP MUX

PS8321

LVDS to eDP SW

STDP4028

HDMI MUX

PS8271

eDP

HDMI

DP1.2

HDMI

mini DP Conn.

PS8330

2 2

Mini Card #1(Half)

WLAN/WiMax

BT4.0+LE/WiGig

HDMI MUX

PS8271

DMC

Display MiniCard

Re-Driver

PS121

2-lane eDP

N14P-GT N14E-GE

VRAM x 8 GDDR5

HDMI

PEGx16

USB2.0 PCI-E 2.0

Gen 3

Intel

Haswell

Processor

4C 47W

Scoket G3 rPGA-947

Page 4, 5, 6, 7, 8, 9, 10

DMI x4

100MHz 5GT/s

Intel

Lynx Point

PCH

BGA 695 Balls

Memory Bus (DDRIII)

Dual Channel

1.35V DDRIII 1600 MHz

USB3.0

USB 2.0

USB3.0

USB 2.0

USB3.0

USB 2.0

USB2.0

USB Rediver

PS8713

USB Rediver

PS8713DP Rediver

USB Rediver

PS8713

LNG3DMTR

204pin DDRIII SO-DIMM x2

BANK 0, 1, 2, 3

Fan Control EMC1412

Page 11, 12, 13, 14

USB 3.0/USB 2.0 Conn.

( USB Charger Port )

USB 3.0/USB 2.0 Conn.

Digital Camera

( H264 Encode )

AlienFX/ELC MAX7313ATG+T

CPU XDP Conn.

SATA 3.0

3 3

RJ45 Conn.

LAN(GbE)

E2201 KILLER

PCI-E 2.0

SATA 3.0

SATA Rediver

PS8520BT

HDD Conn. 1

ODD Conn.

ODD Bay 2nd HDD

SATA 3.0 Mini Card #3(Full)

mSATA

TPA3111

sub-woofer 2W

9 in 1 Conn.

RTC conn.

Card Reader

RTS5209

SPI ROM 8MB

PCI-E 2.0

SPI

Page 16, 17, 18, 19, 20, 21, 22, 23

LPC Bus

HD Audio

Realtek

ALC3661

Power On/Off CKT.

ENE KC3810

ENE KB9012

Audio JacK

TI TAP3113D2

DC/DC Interface CKT.

Headphone Jack

Int. Speaker 2W *2

4 4

VPK MCU

Power Circuit DC/DC

VPK Borad

Touch PadInt.KBD

Headphone Jack

Digital MIC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

2011/02/23 2012/02/23

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

LA-9201P

E

2 66Friday, August 10, 2012

0.1

A

Compal Confidential

Project Code : VAR00 File Name : LA-9201P

B

C

D

E

1 1

LA-XXXXP M/B

Camera

LS-XXXXP

POWER BUTTON/B

on/off SW

Led x 1

FFC

8 pin

44 pin

Coaxial

22 pin

Coaxial

LCD Panel

HDD

LS-XXXXP

INDICATOR+SPK/B

2 2

Led-HDD

Led-Wireless

Led-CapsLock

SPK

FFC

20pin

22 pin

LF-XXXXP

FPC

HDD in ODD Bay Cable

ODD

FFC

50 pin

KSI/KSO

30 pin

VPK Keyboard

LS-XXXXP

VPK Daughter/B

40 pin

FFC for VPK

VPK MAX7313

VPK or N/VPK

3 3

30 pin

N/VPK Keyboard

16 pin

FFC for N/VPK

LS-XXXXP

Touch Pad

TP LED/B

FFC

8 pin

Lid

FFC

16 pin

LS-XXXXP LS-XXXXP LS-XXXXP

Led x 6

Wire

12pin

LS-XXXXP

LOGO /B

Led x 2

WireWireWire

6pin 6pin6pin

Alien head badge/B Alien Slits-L Light/BAlien Slits-R Light/B

Led x 2Led x 2 Led x 2

4 4

Security Classification

2011/06/02 2012/06/02

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

2011/06/02 2012/06/02

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

E

0.1

3 66Friday, August 10, 2012

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0 1 2 3 4 5 6 7 NC

100K +/- 5%Ra

Rb V min

AD_BID

0 0 V

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5%

100K +/- 5% 200K +/- 5%

0.168 V

0.375 V 0.503 V

0.634 V

0.958 V

1.372 V

1.851 V 2.200 V

2.433 V

V typ

AD_BID

0 V 0.155 V

0.250 V

0.819 V

1.185 V

1.650 V

3.300 V

V

AD_BID

0.362 V

0.621 V

0.945 V

1.359 V

1.838 V

2.420 V

3.300 V

max

EC AD3

0x00-0x0C 0x0D-0x1C 0x1D-0x30 0x31-0x49 0x4A-0x69 0x6A-0x8E 0x8F-0xBB 0xBC-0xFF

A

BOARD ID Table

Board ID

0 1 2 3 4 5 6 7

PCB Revision

0.1 (SSI)

0.2 (PT)

0.3 (ST)

0.4 (QT)

1.0 (MP)

USB PORT#0DESTINATION

JUSB1(USB3.0 P1)

1

2

3

JUSB2(USB3.0 P2)

JUSB3(USB3.0 P3)

JUSB4(USB3.0 P4)

POWER STATES

Signal

State

S0 (Full ON) / M0

S5 (SOFT OFF) / M-OFF

SLP S3#

HIGH

LOW HIGH

LOW

SLP

SLP S4#

HIGH ON

LOW LOW LOW LOW ON

S5#

HIGH

S4 STATE#

HIGHHIGH

HIGH LOW ONS3 (Suspend to RAM) / M-OFF

LOW

Symbol Note :

: means Digital Ground

SLP M#

HIGH

LOW ONLOW LOWS4 (Suspend to DISK) / M-OFF

ALWAYS PLANE

SUS PLANE

ON

OFF

RUN PLANE

CLOCKS

ON ON

OFFOFF OFF

PM TABLE

+5VS

+5VALW

power plane

OFFOFFON

OFFOFF

State

S0 ON

S3

S5 S4/AC

+3VALW

+3VLP

+3V_PCH

ON OFF

ON

+1.5V

ON

OFF

+3VS

+1.8VS

+1.5VS

+0.75VS

+3VMXM

+5VMXM

+VCCP

+VCCSA

+VCC_CORE

+1.5V_CPU_VDDQ

ONON

OFF

USB2.0

4

5

6

7

8

9 JESATA

10

11

12

13

1 1

CLKOUT_PCIE0

: means Analog Ground

DESTINATIONDIFFERENTIAL

MINI CARD-1 WLAN

FLEX CLOCKS DESTINATION

CLKOUTFLEX0

S5 S4/AC don't exist

None

OFF

SATA III

CLKOUT_PCIE1

MINI CARD-2 DMC

CLKOUTFLEX1

None

SATA0

CLKOUT_PCIE2

10/100/1G LAN

CLKOUTFLEX2

None

SATA1

CLK

CLKOUT_PCIE3

CARD READER

CLKOUTFLEX3

None

SATA2

CLKOUT_PCIE4

CLKOUT_PCIE5

CLKOUT_PCIE6

CLKOUT_PCIE7

CLKOUT_PEG_A

None

NV

CLKOUT

PCI0

PCI1

PCI2

PCI3

DESTINATION

PCH_LOOPBACK

EC

80port debug card

None

SATA3

SATA4

SATA5

OFF

DESTINATION

HDD1

None

ODD

mSATA

MINI CARD-1 WLAN

MINI CARD-2 MDC

PCI EXPRESS

Lane 1

Lane 2

Lane 3

Lane 4

Lane 5

Lane 6

Lane 7

Lane 8

JMINI1 (WLAN)

JMINI2 (DMC)

AlienFX/ELC

IR SENSOR

Bluetooth

None

eDP CAMERA

LVDS CAMERA

VPK K/B

DESTINATION

None

10/100/1G LAN

CARD READER

None

PCI4

None

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

2012/05/14 2013/05/13

Compal Secret Data

Deciphered Date

Title

Size Document Num ber Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Notes List

LA-9201P

4 66Friday, August 1 0, 2012

0.1

5

4

3

2

1

D D

PEG_COMP

12

RC224.9_0402_1%~D

+VCOMP_OUT

CAD Note: Trace width=12 mils ,Spacing=15mil Max length= 400 mils.

Haswell rPGA EDS

JCPU1A

E23

PEG_RCOMP

DMI_CRX_PTX_N015 DMI_CRX_PTX_N115 DMI_CRX_PTX_N215 DMI_CRX_PTX_N315

DMI_CRX_PTX_P015 DMI_CRX_PTX_P115 DMI_CRX_PTX_P215 DMI_CRX_PTX_P315

DMI_CTX_PRX_N015 DMI_CTX_PRX_N115 DMI_CTX_PRX_N215

C C

FDI_CSYNC15 FDI_INT15

B B

DMI_CTX_PRX_N315

DMI_CTX_PRX_P015 DMI_CTX_PRX_P115 DMI_CTX_PRX_P215 DMI_CTX_PRX_P315

RC3 0_0402_5%~D RC87 0_0402_5%~D

12 12

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

FDI_CSYNC_R FDI_INT_R

D21 C21 B21 A21

D20 C20 B20 A20

D18 C17 B17 A17

D17 C18 B18 A18

H29

J29

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

FDI_CSYNC FDI_INT

PEG

DMI FDI

PEG_RXN_0 PEG_RXN_1 PEG_RXN_2 PEG_RXN_3 PEG_RXN_4 PEG_RXN_5 PEG_RXN_6 PEG_RXN_7 PEG_RXN_8

PEG_RXN_9 PEG_RXN_10 PEG_RXN_11 PEG_RXN_12 PEG_RXN_13 PEG_RXN_14 PEG_RXN_15

PEG_RXP_0

PEG_RXP_1

PEG_RXP_2

PEG_RXP_3

PEG_RXP_4

PEG_RXP_5

PEG_RXP_6

PEG_RXP_7

PEG_RXP_8

PEG_RXP_9 PEG_RXP_10 PEG_RXP_11 PEG_RXP_12 PEG_RXP_13 PEG_RXP_14 PEG_RXP_15

PEG_TXN_0 PEG_TXN_1 PEG_TXN_2 PEG_TXN_3 PEG_TXN_4 PEG_TXN_5 PEG_TXN_6 PEG_TXN_7 PEG_TXN_8

PEG_TXN_9 PEG_TXN_10 PEG_TXN_11 PEG_TXN_12 PEG_TXN_13 PEG_TXN_14 PEG_TXN_15

PEG_TXP_0

PEG_TXP_1

PEG_TXP_2

PEG_TXP_3

PEG_TXP_4

PEG_TXP_5

PEG_TXP_6

PEG_TXP_7

PEG_TXP_8

PEG_TXP_9 PEG_TXP_10 PEG_TXP_11 PEG_TXP_12 PEG_TXP_13 PEG_TXP_14 PEG_TXP_15

PEG_COMP

M29

PEG_CRX_GTX_N0

K28

PEG_CRX_GTX_N1

M31

PEG_CRX_GTX_N2

L30

PEG_CRX_GTX_N3

M33

PEG_CRX_GTX_N4

L32

PEG_CRX_GTX_N5

M35

PEG_CRX_GTX_N6

L34

PEG_CRX_GTX_N7

E29

PEG_CRX_GTX_N8

D28

PEG_CRX_GTX_N9

E31

PEG_CRX_GTX_N10

D30

PEG_CRX_GTX_N11

E35

PEG_CRX_GTX_N12

D34

PEG_CRX_GTX_N13

E33

PEG_CRX_GTX_N14

E32

PEG_CRX_GTX_N15

L29

PEG_CRX_GTX_P0

L28

PEG_CRX_GTX_P1

L31

PEG_CRX_GTX_P2

K30

PEG_CRX_GTX_P3

L33

PEG_CRX_GTX_P4

K32

PEG_CRX_GTX_P5

L35

PEG_CRX_GTX_P6

K34

PEG_CRX_GTX_P7

F29

PEG_CRX_GTX_P8

E28

PEG_CRX_GTX_P9

F31

PEG_CRX_GTX_P10

E30

PEG_CRX_GTX_P11

F35

PEG_CRX_GTX_P12

E34

PEG_CRX_GTX_P13

F33

PEG_CRX_GTX_P14

D32

PEG_CRX_GTX_P15

H35

PEG_CTX_GRX_C_N0

H34

PEG_CTX_GRX_C_N1

J33

PEG_CTX_GRX_C_N2

H32

PEG_CTX_GRX_C_N3

J31

PEG_CTX_GRX_C_N4

G30

PEG_CTX_GRX_C_N5

C33

PEG_CTX_GRX_C_N6

B32

PEG_CTX_GRX_C_N7

B31

PEG_CTX_GRX_C_N8

A30

PEG_CTX_GRX_C_N9

B29

PEG_CTX_GRX_C_N10

A28

PEG_CTX_GRX_C_N11

B27

PEG_CTX_GRX_C_N12

A26

PEG_CTX_GRX_C_N13

B25

PEG_CTX_GRX_C_N14

A24

PEG_CTX_GRX_C_N15

J35

PEG_CTX_GRX_C_P0

G34

PEG_CTX_GRX_C_P1

H33

PEG_CTX_GRX_C_P2

G32

PEG_CTX_GRX_C_P3

H31

PEG_CTX_GRX_C_P4

H30

PEG_CTX_GRX_C_P5

B33

PEG_CTX_GRX_C_P6

A32

PEG_CTX_GRX_C_P7

C31

PEG_CTX_GRX_C_P8

B30

PEG_CTX_GRX_C_P9

C29

PEG_CTX_GRX_C_P10

B28

PEG_CTX_GRX_C_P11

C27

PEG_CTX_GRX_C_P12

B26

PEG_CTX_GRX_C_P13

C25

PEG_CTX_GRX_C_P14

B24

PEG_CTX_GRX_C_P15

PEG_CRX_GTX_N[0..15] 46

PEG_CRX_GTX_P[0..15] 46

PEG_CTX_GRX_C_P0

PEG_CTX_GRX_C_P1 PEG_CTX_GRX_C_N1

PEG_CTX_GRX_C_P2 PEG_CTX_GRX_C_N2

PEG_CTX_GRX_C_P3 PEG_CTX_GRX_C_N3

PEG_CTX_GRX_C_P4 PEG_CTX_GRX_C_N4

PEG_CTX_GRX_C_P5 PEG_CTX_GRX_C_N5

PEG_CTX_GRX_C_P6 PEG_CTX_GRX_C_N6

PEG_CTX_GRX_C_P7 PEG_CTX_GRX_C_N7

PEG_CTX_GRX_C_P8 PEG_CTX_GRX_C_N8

PEG_CTX_GRX_C_P9 PEG_CTX_GRX_C_N9

PEG_CTX_GRX_C_P10 PEG_CTX_GRX_C_N10

PEG_CTX_GRX_C_P11 PEG_CTX_GRX_C_N11

PEG_CTX_GRX_C_P12 PEG_CTX_GRX_C_N12

PEG_CTX_GRX_C_P13 PEG_CTX_GRX_C_N13

PEG_CTX_GRX_C_P14 PEG_CTX_GRX_C_N14

PEG_CTX_GRX_C_P15 PEG_CTX_GRX_C_N15

PEG_CTX_GRX_P[0..15]

PEG_CTX_GRX_N[0..15]

1 2 1 2

12 12

CC1 0.22U_0402_16V7K~D CC2 0.22U_0402_16V7K~D

CC3 0.22U_0402_16V7K~D CC4 0.22U_0402_16V7K~D

CC5 0.22U_0402_16V7K~D CC6 0.22U_0402_16V7K~D

CC7 0.22U_0402_16V7K~D CC8 0.22U_0402_16V7K~D

CC9 0.22U_0402_16V7K~D CC10 0.22U_0402_16V7K~D

CC11 0.22U_0402_16V7K~D CC12 0.22U_0402_16V7K~D

CC13 0.22U_0402_16V7K~D CC14 0.22U_0402_16V7K~D

CC15 0.22U_0402_16V7K~D CC16 0.22U_0402_16V7K~D

CC17 0.22U_0402_16V7K~D CC18 0.22U_0402_16V7K~D

CC19 0.22U_0402_16V7K~D CC20 0.22U_0402_16V7K~D

CC21 0.22U_0402_16V7K~D CC22 0.22U_0402_16V7K~D

CC23 0.22U_0402_16V7K~D CC24 0.22U_0402_16V7K~D

CC25 0.22U_0402_16V7K~D CC26 0.22U_0402_16V7K~D

CC27 0.22U_0402_16V7K~D CC28 0.22U_0402_16V7K~D

CC29 0.22U_0402_16V7K~D CC30 0.22U_0402_16V7K~D

CC31 0.22U_0402_16V7K~D CC32 0.22U_0402_16V7K~D

PEG_CTX_GRX_P[0..15] 46

PEG_CTX_GRX_N[0..15] 46

PEG_CTX_GRX_P0 PEG_CTX_GRX_N0PEG_CTX_GRX_C_N0

PEG_CTX_GRX_P1 PEG_CTX_GRX_N1

PEG_CTX_GRX_P2 PEG_CTX_GRX_N2

PEG_CTX_GRX_P3 PEG_CTX_GRX_N3

PEG_CTX_GRX_P4 PEG_CTX_GRX_N4

PEG_CTX_GRX_P5 PEG_CTX_GRX_N5

PEG_CTX_GRX_P6 PEG_CTX_GRX_N6

PEG_CTX_GRX_P7 PEG_CTX_GRX_N7

PEG_CTX_GRX_P8 PEG_CTX_GRX_N8

PEG_CTX_GRX_P9 PEG_CTX_GRX_N9

PEG_CTX_GRX_P10 PEG_CTX_GRX_N10

PEG_CTX_GRX_P11 PEG_CTX_GRX_N11

PEG_CTX_GRX_P12 PEG_CTX_GRX_N12

PEG_CTX_GRX_P13 PEG_CTX_GRX_N13

PEG_CTX_GRX_P14 PEG_CTX_GRX_N14

PEG_CTX_GRX_P15 PEG_CTX_GRX_N15

INTEL_HASWELL_HASWELL

CONN@

A A

5

4

1 OF 9

Security Classification

2012/02/28 2013/02/27

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/02/28 2013/02/27

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

CPU (1/7) DMI,PEG

LA-9201P

1

5 66Tuesday, August 14, 2012

0.1

5

SM_DRAMPWROK with DDR Power Gating Topology

+3V_PCH

100K_0402_5%~D

+3V_PCH

@

RC89

0.1U_0402_2 5V6K~D

5

1

P

B

O

2

A

G

74AHC1G09GW_ TSSOP5~D

3

RC36 0_0 402_5%~D@

RUN_ON_CPU1.5VS3#10,45

PCH_PLTRST#_BUF

12

1 2

RC57 56_0402_5%~D

1 2

RC134 0_0402_5 %~D

place RC134 near CPU

1 2

RC25 0_0402_5%~ D

RC51 0_0402_5%~D RC52 0_0402_5%~D RC43 0_0402_5%~D RC22 0_0402_5%~D RC15 0_0402_5%~D RC13 0_0402_5%~D

+1.05VS

0.1U_0402_25V6K~D

1

CC140

2

CC156

1 2

4

RUNPWROK_AND PM_DRAM_PW RGD_CPU

UC2

H_PECI19,32

12 12 12 12 12 12

1K_0402_1%~D

12

RC17

1 2

RC10 43_ 0402_5%~D

20K_0402_5%~D

12

RC11

12

H_THERMTRIP#

H_CATERR#

H_PROCHOT#

H_PROCHOT#32,63

H_THERMTRIP#19,46

H_PM_SYNC15

H_CPUPWRGD19

CLK_CPU_DPLL#16

CLK_CPU_DPLL1 6

CLK_CPU_DMI#16

CLK_CPU_DMI16

RC2010K_0402_ 5%~D @

RC2110K_0402_ 5%~D @

5

VCC

4

12

place RC57 near CPU

+VCCIO_OUT

+3VS

D D

SYS_PWROK15

PM_DRAM_PW RGD15

C C

B B

SSC CLOCK TERMINATION, IF NOT USED, stuff RC20,RC21

RC88 0_0 402_5%~D

+3V_PCH

RC18 200_0402_1 %~D

+VCCIO_OUT

1 2

RC136 56_0402_5% ~D@

1 2

RC128 49.9_0402_1 %~D@

1 2

RC44 62_ 0402_5%~D

place RC44 near CPU

CPU_SSC_DPLL

CPU_SSC_DPLL#

1 2

CLK_CPU_SSC_DPLL #16

CLK_CPU_SSC_DPLL16

Buffered reset to CPU

UC1

1

NC

PLT_RST#15,31,32,33 ,40

2

A GND3Y

SN74LVC1G07DCKR_ SC70-5~D

+1.35V_CPU_VDDQ

39_0402_5%~D

@

RC64

SSM3K7002FU_SC70-3~D

1 2

13

D

2

G

S

T66PA D~D @

H_PROCHOT#_R H_THERMTRIP#_R

H_PM_SYNC VCCPWRGOOD_0_R PM_DRAM_PW RGD_CPU CPU_PLTRST#_R

CPU_DPLL# CPU_DPLL CPU_SSC_DPLL# CPU_SSC_DPLL CPU_DMI# CPU_DMI

CPU_PLTRST#19

4

1.8K_0402_1%

12

RC16

RC28 0_0 402_5%~D

3.3K_0402_1%~D

12

RC14

@

QC1

AP32

H_CATERR# H_PECI

AN32 AR27

AK31 AM30 AM35

AT28

AL34 AC10

AT26

G28

H28 F27 E27 D26 E26

RC54 0_0 402_5%~D@

RC53 0_0 402_5%~D

12

Haswell rPGA EDS

SKTOCC

CATERR PECI RSVD PROCHOT THERMTRIP

PM_SYNC PWRGOOD SM_DRAMPWROK PLTRSTIN

DPLL_REF_CLKN DPLL_REF_CLKP SSC_DPLL_REF_CLKN SSC_DPLL_REF_CLKP BCLKN BCLKP

CONN@

12

MISC

INTEL_HASWELL_ HASWELL

JCPU1B

THERMAL

PWR

CLOCK

CPU_PLTRST#_R

DDR3

+3V_PCH

RC125 1K_0402_1%~ D@

PCH_SMBDATA12,13,17,38 ,39,40,42

PCH_SMBCLK12,13,17,38 ,39,40,42

AP3

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2 SM_DRAMRST

PRDY PREQ

TCK TMS

TRST

JTAG

TDI TDO DBR

BPM_N_0 BPM_N_1 BPM_N_2 BPM_N_3 BPM_N_4 BPM_N_5 BPM_N_6 BPM_N_7

2 OF 9

CAD Note:

Avoid stub in the PWRGD path

while placing resistors RC25 & RC130

SM_RCOMP0

AR3

SM_RCOMP1

AP2

SM_RCOMP2

AN3

DDR3_DRAMRST#_CPU

AR29

XDP_PRDY#

AT29

XDP_PREQ#

AM34

XDP_TCLK

AN33

XDP_TMS

AM33

XDP_TRST#

AM31

XDP_TDI_R

AL33

XDP_TDO_R

AP33

XDP_DBRESET#_R

AR30

XDP_OBS0_R

AN31

XDP_OBS1_R

AN29

XDP_OBS2_R

AP31

XDP_OBS3_R

AP30

XDP_OBS4_R

AN28

XDP_OBS5_R

AP29

XDP_OBS6_R

AP28

XDP_OBS7_R

VCCPWRGOOD_0_R

3

+VCCIO_OUT

0.1U_0402_25V6K~D

1

2

CC66

CC65

2

Place near JXDP1

1 2

PBTN_OUT#15,32

CPU_PWR_DEBUG10

IMVP_PWRGD15,32,61

SYS_PWROK_XDP

H_CPUPWRGD H_CPUPWRGD_XDP

RC5 need to close to JCPU1

RC5 1K_0402_1% ~D RC6 0_0402_5%~ D

RC8 0_0402_5%~ D RC12 0_0 402_5%~D

RC126 0_0402_5 %~D RC127 0_0402_5 %~D

DDR3_DRAMRST#_CPU 12

1 2

RC148 0_0402_5%~ D

1 2

RC149 0_0402_5%~ D

1 2

RC150 0_0402_5%~ D

1 2

RC151 0_0402_5%~ D

1 2

RC23 0_0 402_5%~D

1 2

RC24 0_0 402_5%~D RC26 0_0 402_5%~D

1 2

RC30 0_0 402_5%~D

1 2

RC31 0_0 402_5%~D

1 2

RC33 0_0 402_5%~D

1 2

RC34 0_0 402_5%~D

1 2

RC37 0_0 402_5%~D

1 2

RC40 0_0 402_5%~D

1 2

RC38 0_0 402_5%~D

1 2

RC39 0_0 402_5%~D

1 2 1 2

12

CFG39

For ESD concern, please put near CPU

10K_0402_5%~D

12

RC135

CRB Rev 0.7 is depop

+VCCIO_OUT +VCCIO_OUT

XDP_PREQ#_R XDP_PRDY#

CFG09 CFG19

CFG29

1 2

RC129 1K_0 402_1%~D

CFG49 CFG59

CFG69 CFG79

XDP_PREQ#_R XDP_TCLK_R

XDP_TDI XDP_TDO XDP_DBRESET#

XDP_OBS0 XDP_OBS1

CFG0 CFG1

CFG2 CFG3_R

XDP_OBS0 XDP_OBS1

CFG4 CFG5

CFG6 CFG7

CFD_PWRBTN#_XDP

SYS_PWROK_XDP

DDR_XDP_SMBDAT_R1 DDR_XDP_SMBCLK_R1

XDP_TCLK_R

XDP_DBRESET# 15

DDR3 COMPENSATION SIGNALS

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

CAD Note: Trace width=12~15 mil, Spcing=20 mils Max trace length= 500 mil

1 2

RC45 100 _0402_1%~D

1 2

RC55 75_ 0402_1%~D

1 2

RC49 100 _0402_1%~D

2

JXDP1

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01 -L-D-A CONN@

CRB Rev 0.7 no pull up

GND1 OBSFN_C0 OBSFN_C1

GND3

OBSDATA_C0 OBSDATA_C1

GND5

OBSDATA_C2 OBSDATA_C3

GND7 OBSFN_D0 OBSFN_D1

GND9

OBSDATA_D0 OBSDATA_D1

GND11 OBSDATA_D2 OBSDATA_D3

GND13

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND15

TD0

TRST#

TMS

GND17

1

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56

TDI

58 60

CFG17 CFG16

CFG8 CFG9

CFG10 CFG11

CFG19 CFG18

CFG12 CFG13

CFG14 CFG15

CLK_XDP CLK_XDP#

XDP_RST#_RCPU_PWR_DEBUG_ R XDP_DBRESET#

XDP_TDO XDP_TRST# XDP_TDI CFG3_R

CFG17 9 CFG16 9

CFG8 9 CFG9 9

CFG10 9 CFG11 9

CFG19 9 CFG18 9

CFG12 9 CFG13 9

CFG14 9 CFG15 9

1 2

RH108 0_0402_5 %~D

1 2

RH113 0_0402_5 %~D

12

RC9 1K_0402_1% ~D

CPU_PLTRST#_R

CLK_CPU_ITP 16 CLK_CPU_ITP# 16

PU/PD for JTAG signals

+3VS

XDP_DBRESET#_R

XDP_TMS

XDP_TDI_R

XDP_PREQ#

XDP_TDO_R

XDP_TCLK

XDP_TRST#

RC19 1 K_0402_1%~D

RC27 5 1_0402_1%~D@

RC29 5 1_0402_1%~D

RC32 5 1_0402_1%~D@

RC35 5 1_0402_1%~D

RC42 5 1_0402_1%~D

RC41 5 1_0402_1%~D

12

+1.05VS

12

CAD Note: PLACE PULL-UP RESISTOR WITHIN 2 INCH OF THE CPU

A A

Security Classification

2012/02/28 2013/02/27

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

5

4

3

2012/02/28 2013/02/27

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

CPU (2/7) PM,XDP,CLK

LA-9201P

1

6 66Monday, Augu st 20, 2012

0.1

5

4

3

2

1

DDR_A_D[0..63]12

D D

C C

+V_SM_VREF

+DIMM0_1_VREF

+DIMM0_1_CA

B B

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

+DIMM0_1_VREF +DIMM0_1_CA +V_SM_VREF

AR15 AT14

AM14

AN14 AT15 AR14 AN15

AM15

AM9 AN9 AM8 AN8 AR9

AT9

AR8

AT8 AJ9 AK9 AJ6 AK6

AJ10

AK10

AJ7 AK7 AF4 AF5 AF1

AF2 AG4 AG5 AG1 AG2

E12

D12

B11

A11

E11

D11

B12

A12 AM3

F16

F13

J1 J2

J5 H5 H2 H1

J4 H4 F2 F1 D2 D3 D1 F3 C3 B3 B5 E6 A5 D6 D5 E5 B6 A6

CONN@

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 SM_VREF SA_DIMM_VREFDQ SB_DIMM_VREFDQ

JCPU1C

INTEL_HASWELL_HASWELL

3 OF 9

1K_0402_1%~D

12

RC144

Haswell rPGA EDS

SA_WE

AC7 U4

M_CLK_DDR#0

V4

M_CLK_DDR0

AD9

DDR_CKE0_DIMMA

U3

M_CLK_DDR#1

V3

M_CLK_DDR1

AC9

DDR_CKE1_DIMMA

U2 V2 AD8 U1 V1 AC8

M7

DDR_CS0_DIMMA#

L9

DDR_CS1_DIMMA#

M9 M10 M8

M_ODT0

L7

M_ODT1

L8 L10 V5

DDR_A_BS0

U5

DDR_A_BS1

AD1

DDR_A_BS2

V10 U6

DDR_A_RAS#

U7

DDR_A_WE#

U8

DDR_A_CAS#

V8

DDR_A_MA0

AC6

DDR_A_MA1

V9

DDR_A_MA2

U9

DDR_A_MA3

AC5

DDR_A_MA4

AC4

DDR_A_MA5

AD6

DDR_A_MA6

AC3

DDR_A_MA7

AD5

DDR_A_MA8

AC2

DDR_A_MA9

V6

DDR_A_MA10

AC1

DDR_A_MA11

AD4

DDR_A_MA12

V7

DDR_A_MA13

AD3

DDR_A_MA14

AD2

DDR_A_MA15

AP15

DDR_A_DQS#0

AP8

DDR_A_DQS#1

AJ8

DDR_A_DQS#2

AF3

DDR_A_DQS#3

J3

DDR_A_DQS#4

E2

DDR_A_DQS#5

C5

DDR_A_DQS#6

C11

DDR_A_DQS#7

AP14

DDR_A_DQS0

AP9

DDR_A_DQS1

AK8

DDR_A_DQS2

AG3

DDR_A_DQS3

H3

DDR_A_DQS4

E3

DDR_A_DQS5

C6

DDR_A_DQS6

C12

DDR_A_DQS7

RSVD_AC7

SA_CK_N_0

SA_CK_P_0

SA_CKE_0

SA_CK_N_1

SA_CK_P_1

SA_CKE_1

SA_CK_N_2

SA_CK_P_2

SA_CKE_2

SA_CK_N_3

SA_CK_P_3

SA_CKE_3

SA_CS_N_0 SA_CS_N_1 SA_CS_N_2 SA_CS_N_3

SA_ODT_0 SA_ODT_1 SA_ODT_2 SA_ODT_3

SA_BS_0 SA_BS_1 SA_BS_2

RSVD_V10

SA_RAS

SA_CAS

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 SA_MA_15

SA_DQS_N_0 SA_DQS_N_1 SA_DQS_N_2 SA_DQS_N_3 SA_DQS_N_4 SA_DQS_N_5 SA_DQS_N_6 SA_DQS_N_7 SA_DQS_P_0 SA_DQS_P_1 SA_DQS_P_2 SA_DQS_P_3 SA_DQS_P_4 SA_DQS_P_5 SA_DQS_P_6 SA_DQS_P_7

+DIMM0_1_VREF_CPU +DIMM0_1_CA_CPU

T67 PAD~D@

M_CLK_DDR#0 12 M_CLK_DDR0 12 DDR_CKE0_DIMMA 12 M_CLK_DDR#1 12 M_CLK_DDR1 12 DDR_CKE1_DIMMA 12

DDR_CS0_DIMMA# 12 DDR_CS1_DIMMA# 12

M_ODT0 12 M_ODT1 12

DDR_A_BS0 12 DDR_A_BS1 12 DDR_A_BS2 12

DDR_A_RAS# 12

DDR_A_WE# 12

DDR_A_CAS# 12

DDR_A_MA[0..15] 12

DDR_A_DQS#[0..7] 12

DDR_A_DQS[0..7] 12

+1.35V+1.35V

1K_0402_1%~D

12

RC145

DDR_B_D[0..63]13

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AR18

AT18 AM17 AM18 AR17

AT17 AN17 AN18

AT12 AR12 AN12 AM11

AT11 AR11 AM12 AN11

AR5

AR6 AM5 AM6

AT5

AT6 AN5 AN6

AJ4

AK4

AJ1

AJ2 AM1 AN1

AK2 AK1

M2

M4

M1

M5

G10

J10

E15 D15 A15 B15 E14 D14 A14 B14

L2

L4

L1

L5

G7

J8 G8 G9

J7

J9

A8 B8 A9 B9 D8 E8 D9 E9

+1.35V

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

CONN@

1K_0402_1%~D

12

RC86

JCPU1D

INTEL_HASWELL_HASWELL

4 OF 9

+V_SM_VREF_CNT

Haswell rPGA EDS

RSVD

SB_CKN0

SB_CK0

SB_CKE_0

SB_CKN1

SB_CK1

SB_CKE_1

SB_CKN2

SB_CK2

SB_CKE_2

SB_CKN3

SB_CK3

SB_CKE_3

SB_CS_N_0 SB_CS_N_1 SB_CS_N_2 SB_CS_N_3

SB_ODT_0 SB_ODT_1 SB_ODT_2 SB_ODT_3

SB_BS_0 SB_BS_1 SB_BS_2

RSVD

SB_RAS

SB_WE

SB_CAS

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 SB_MA_15

SB_DQS_N_0 SB_DQS_N_1 SB_DQS_N_2 SB_DQS_N_3 SB_DQS_N_4 SB_DQS_N_5 SB_DQS_N_6 SB_DQS_N_7 SB_DQS_P_0 SB_DQS_P_1 SB_DQS_P_2 SB_DQS_P_3 SB_DQS_P_4 SB_DQS_P_5 SB_DQS_P_6 SB_DQS_P_7

AG8 Y4

M_CLK_DDR#2

AA4

M_CLK_DDR2

AF10

DDR_CKE2_DIMMB

Y3

M_CLK_DDR#3

AA3

M_CLK_DDR3

AG10

DDR_CKE3_DIMMB

Y2 AA2 AG9 Y1 AA1 AF9

P4

DDR_CS2_DIMMB#

R2

DDR_CS3_DIMMB#

P3 P1

R4

M_ODT2

R3

M_ODT3

R1 P2 R7

DDR_B_BS0

P8

DDR_B_BS1

AA9

DDR_B_BS2

R10 R6

DDR_B_RAS#

P6

DDR_B_WE#

P7

DDR_B_CAS#

R8

DDR_B_MA0

Y5

DDR_B_MA1

Y10

DDR_B_MA2

AA5

DDR_B_MA3

Y7

DDR_B_MA4

AA6

DDR_B_MA5

Y6

DDR_B_MA6

AA7

DDR_B_MA7

Y8

DDR_B_MA8

AA10

DDR_B_MA9

R9

DDR_B_MA10

Y9

DDR_B_MA11

AF7

DDR_B_MA12

P9

DDR_B_MA13

AA8

DDR_B_MA14

AG7

DDR_B_MA15

AP18

DDR_B_DQS#0

AP11

DDR_B_DQS#1

AP5

DDR_B_DQS#2

AJ3

DDR_B_DQS#3

L3

DDR_B_DQS#4

H9

DDR_B_DQS#5

C8

DDR_B_DQS#6

C14

DDR_B_DQS#7

AP17

DDR_B_DQS0

AP12

DDR_B_DQS1

AP6

DDR_B_DQS2

AK3

DDR_B_DQS3

M3

DDR_B_DQS4

H8

DDR_B_DQS5

C9

DDR_B_DQS6

C15

DDR_B_DQS7

T76 PAD~D@

M_CLK_DDR#2 13 M_CLK_DDR2 13 DDR_CKE2_DIMMB 13 M_CLK_DDR#3 13 M_CLK_DDR3 13 DDR_CKE3_DIMMB 13

DDR_CS2_DIMMB# 13 DDR_CS3_DIMMB# 13

M_ODT2 13 M_ODT3 13

DDR_B_BS0 13 DDR_B_BS1 13 DDR_B_BS2 13

DDR_B_RAS# 13

DDR_B_WE# 13

DDR_B_CAS# 13

DDR_B_MA[0..15] 13

DDR_B_DQS#[0..7] 13

DDR_B_DQS[0..7] 13

1 2

RC152 0_0402_1%~D

1

0.022U_0402_25V7K~D

A A

CC184

RC154

24.9_0402_1%

5

2

12

1K_0402_1%~D

12

RC146

0.022U_0402_25V7K~D

CC183

RC155

24.9_0402_1%

4

1 2

RC153 0_0402_1%~D

1

2

12

1K_0402_1%~D

12

RC147

0.022U_0402_25V7K~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

24.9_0402_1%

3

CC185

RC157

1 2

RC156 0_0402_1%~D

1

2

12

2011/06/02 2012/06/02

1K_0402_1%~D

12

RC78

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

CPU (3/7) DDRIII

7 66Tuesday, August 14, 2012

1

7 66Tuesday, August 14, 2012

0.1

5

4

3

2

1

COMPENSATION PU FOR eDP

+VCOMP_OUT

EDP_COMP

D D

CAD Note:Trace width=20 mils ,Spacing=25mil,

12

RC124.9_0402_1%~D

Max length=100 mils.

Haswell rPGA EDS

CPU_HDMI_N0 CPU_HDMI_P0 CPU_HDMI_N1 CPU_HDMI_P1 CPU_HDMI_N2 CPU_HDMI_P2 CPU_HDMI_N3 CPU_HDMI_P3

HDMI

CPU_HDMI_N027 CPU_HDMI_P027 CPU_HDMI_N127 CPU_HDMI_P127 CPU_HDMI_N227 CPU_HDMI_P227 CPU_HDMI_N327 CPU_HDMI_P327

mDP

C C

DMC

CPU_DPD_DMC_N030 CPU_DPD_DMC_P030 CPU_DPD_DMC_N130 CPU_DPD_DMC_P130 CPU_DPD_DMC_N230 CPU_DPD_DMC_P230 CPU_DPD_DMC_N330 CPU_DPD_DMC_P330

CPU_DPD_DMC_N0 CPU_DPD_DMC_P0 CPU_DPD_DMC_N1 CPU_DPD_DMC_P1 CPU_DPD_DMC_N2 CPU_DPD_DMC_P2 CPU_DPD_DMC_N3 CPU_DPD_DMC_P3

T28

DDIB_TXBN_0

U28

DDIB_TXBP_0

T30

DDIB_TXBN_1

U30

DDIB_TXBP_1

U29

DDIB_TXBN_2

V29

DDIB_TXBP_2

U31

DDIB_TXBN_3

V31

DDIB_TXBP_3

T34

DDIC_TXCN_0

U34

DDIC_TXCP_0

U35

DDIC_TXCN_1

V35

DDIC_TXCP_1

U32

DDIC_TXCN_2

T32

DDIC_TXCP_2

U33

DDIC_TXCN_3

V33

DDIC_TXCP_3

P29

DDID_TXDN_0

R29

DDID_TXDP_0

N28

DDID_TXDN_1

P28

DDID_TXDP_1

P31

DDID_TXDN_2

R31

DDID_TXDP_2

N30

DDID_TXDN_3

P30

DDID_TXDP_3

INTEL_HASWELL_HASWELL

CONN@

JCPU1H

eDP

EDP_AUXN EDP_AUXP

EDP_HPD

EDP_RCOMP

RSVD

EDP_TXN_0 EDP_TXP_0 EDP_TXN_1 EDP_TXP_1

FDI_TXN_0 FDI_TXP_0 FDI_TXN_1 FDI_TXP_1

DDI

8 OF 9

M27 N27 P27 E24 R27

P35 R35 N34 P34 P33 R33 N32 P32

CPU_EDP_AUX# CPU_EDP_AUX EDP_HPD_R EDP_COMP

CPU_EDP_TX0N CPU_EDP_TX0P CPU_EDP_TX1N CPU_EDP_TX1P CPU_EDP_TX2N CPU_EDP_TX2P CPU_EDP_TX3N CPU_EDP_TX3P

CPU_EDP_AUX# 24 CPU_EDP_AUX 24

T77PAD~D @

CPU_EDP_TX0N 24 CPU_EDP_TX0P 24 CPU_EDP_TX1N 24 CPU_EDP_TX1P 24 CPU_EDP_TX2N 24 CPU_EDP_TX2P 24 CPU_EDP_TX3N 24 CPU_EDP_TX3P 24

+VCCIO_OUT

B B

A A

HPD INVERSION FOR EDP

CPU_EDP_HPD#24

100K_0402_5%~D

12

RC75

12

10K_0402_5%~D RC65

EDP_HPD_R

BSS138_SOT23~D

13

D

2

G

QC10

S

Security Classification

2012/02/28 2013/02/27

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2012/02/28 2013/02/27

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

CPU (4/7) FDI,eDP,DDI

LA-9201P

1

0.1

8 66Tuesday, August 14, 2012

5

4

3

2

1

CFG STRAPS for CPU

CFG2

D D

1K_0402_1%~D

12

@

RC76

PEG Static Lane Reversal - CFG2 is for the 16x

1:(Default) Normal Operation; Lane #

CFG2

definition matches socket pin map definition

0:Lane Reversed

Haswell rPGA EDS

T103PAD~D@ T80 PAD~D@ T99PAD~D @ T78 PAD~D@

T110PAD~D@ T81 PAD~D@

T79 PAD~D@

C C

B B

12

RC60 49.9_0402_1%~D

RC58 49.9_0402_1%~D

RC59 49.9_0402_1%~D

H_CPU_TESTLO

12

CFG_RCOMP

12

H_CPU_RSVD

T101PAD~D@

T83 PAD~D@ T108PAD~D@

+VCC_CORE

T82 PAD~D@ T94 PAD~D@

T85 PAD~D@

T84 PAD~D@ T95PAD~D @ T86 PAD~D@

CFG06 CFG16 CFG26 CFG36 CFG46 CFG56 CFG66 CFG76 CFG86 CFG96 CFG106 CFG116 CFG126 CFG136 CFG146 CFG156

H_CPU_RSVD

H_CPU_TESTLO

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

AT1 AT2

AD10

A34 A35

W29 W28

G26

W33 AL30 AL29

F25

C35 B35

AL25

W30

W31

W34

AT20

AR20 AP20 AP22

AT22

AN22

AT25

AN23 AR24

AT23

AN20 AP24 AP26 AN25 AN26 AP25

RSVD_TP RSVD_TP RSVD

RSVD_TP RSVD_TP

RSVD RSVD RSVD RSVD RSVD RSVD VCC

RSVD_TP RSVD_TP

RSVD_TP

RSVD RSVD TESTLO

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15

INTEL_HASWELL_HASWELL

CONN@

JCPU1I

RSVD_TP RSVD_TP RSVD_TP RSVD_TP

CFG_RCOMP

CFG_16 CFG_18 CFG_17 CFG_19

RSVD RSVD RSVD RSVD RSVD RSVD RSVD

RSVD

RSVD RSVD

NC

RSVD

RSVD_TP

RSVD_TP RSVD_TP

RSVD RSVD

9 OF 9

C23 B23 D24 D23

AT31 AR21 AR23 AP21 AP23

AR33 G6 AM27 AM26 F5 AM2 K6

E18

U10 P10

B1 A2 AR1

E21 E20

AP27 AR26

AL31 AL32

CFG_RCOMP CFG16 CFG18 CFG17 CFG19

T90PAD~D @ T87PAD~D @ T88PAD~D @

CFG16 6 CFG18 6 CFG17 6 CFG19 6

T91PAD~D @ T104PAD~D @ T92PAD~D @ T89PAD~D @ T93PAD~D @

T111PAD~D @

T96PAD~D @

T98PAD~D @ T97PAD~D @

T100PAD~D @ T109PAD~D @

T102PAD~D @ T107PAD~D @

T105PAD~D @ T106PAD~D @

CFG4

CFG[6:5]

CFG4

1K_0402_1%~D

12

RC77

Display Port Presence Strap

1 : Disabled; No Physical Display Port attached to Embedded Display Port

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

CFG6

CFG5

1K_0402_1%~D

12

@

RC90

1K_0402_1%~D

12

@

RC92

PCIE Port Bifurcation Straps 11: (Default) x16 - Device 1 functions 1 and 2 disabled 10: x8, x8 - Device 1 function 1 enabled ; function 2

disabled 01: Reserved - (Device 1 function 1 disabled ; function

2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CFG7

1K_0402_1%~D

12

@

RC91

PEG DEFER TRAINING

1: (Default) PEG Train immediately

A A

CFG7

following xxRESETB de assertion

0: PEG Wait for BIOS for training

Security Classification

2012/02/28 2013/02/27

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2012/02/28 2013/02/27

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

CPU (5/7) RSVD,CFG

LA-9201P

1

0.1

9 66Tuesday, August 14, 2012

5

4

3

2

1

K27 L27 T27 V27

AB11

AB2 AB5 AB8

AE11

AE2 AE5 AE8

AH11

K11 N11

T11

W11

N26

K26 AL27 AK27

AL35

E17 AN35

A23

F22

W32

AL16

AL13

AM28 AM29

AL28

AP35

H27 AP34 AT35

AR35 AR32

AL26 AT34 AL22 AT33

AM21 AM25 AM22 AM20 AM24

AL19

AM23

AT32

Y25

Y26

Y27

Y28

Y29

Y30

Y31

Y32

Y33

Y34

Y35

Haswell rPGA EDS

RSVD RSVD RSVD RSVD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

N8

VDDQ VDDQ

T2

VDDQ

T5

VDDQ

T8

VDDQ VDDQ

W2

VDDQ

W5

VDDQ

W8

VDDQ

RSVD VCC RSVD RSVD

VCC_SENSE RSVD VCCIO_OUT VCCIO2PCH VCCIOA_OUT RSVD RSVD

J27

VSS RSVD

VIDALERT VIDSCLK VIDSOUT

VSS PWR_DEBUG RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

INTEL_HASWELL_ HASWELL

CONN@

JCPU1E

5 OF 9

D D

C C

B B

+1.35V_CPU_VDDQ Source

SUSP#32,45 ,58,60

CPU1.5V_S3_GATE32

SVID ALERT

VIDALERT_N61

SVID DATA

VIDSOUT61

VCC_SENSE

VCCSENSE6 1

VSSSENSE61

1 2

RC93 0_ 0402_5%~D@

1 2

RC79 0_ 0402_5%~D

+VCCIO_OUT

75_0402_1%~D

12

RC61

+VCCIO_OUT

110_0402_1%~D

12

RC63

VIDSOUT

+VCC_CORE

100_0402_1%~D

12

RC66

VCCSENSE

VSSSENSE

100_0402_1%~D

12

RC70

+3VALW

100K_0402_5%~D

12

RC74

RUN_ON_CPU1.5VS3#

DMN66D0LDW-7_SOT363-6~D

61

QC4A

2

CAD Note: Place the PU resistors close to CPU RC60 close to CPU 300 - 1500mils

12

H_CPU_SVIDALRT#

RC6943_0402_5% ~D

CAD Note: Place the PU resistors close to CPU RC63 close to CPU 300 - 1500mils

B+_BIAS

330K_0402_5%~D

12

RC72

3

5

4

RUN_ON_CPU1.5VS3# 6,4 5

CAD Note: RC67 SHOULD BE PLACED CLOSE TO CPU

12

VCCSENSE_R

RC670_040 2_5%~D

CAD Note: RC68 SHOULD BE PLACED CLOSE TO CPU

12

VSSSENSE_R

RC680_0402_5%~D

VSSSENSE_R 11

RUN_ON_CPU1.5VS3R UN_ON_CPU1.5VS3

DMN66D0LDW-7_SOT363-6~D

QC4B

+1.35V

QC3

AO4304L_SO8

8 7 6 5

4

0.022U_0402_25V7K~D

1M_0402_5%~D

12

RC143

1

CC136

2

+1.05VS

RC4 0_0603_5%~ D@

RESISTOR STUFFING OPTIONS ARE PROVIDED FOR TESTING PURPOSES

+1.35V_CPU_VDDQ

1 2 3

10U_0603_6.3V6M~D

1

2

+1.35V_CPU_VDDQ

10U_0603_6.3V6M~D

20K_0402_5%~D

12

CC135

1

2

12

10U_0603_6.3V6M~D

1

CC170

CC180

2

@

RC73

+VCCIO_OUT

VDDQ DECOUPLING

10U_0603_6.3V6M~D

CC169

10U_0603_6.3V6M~D

1

CC168

2

T113 PAD~D@ T114 PAD~D@ T112 PAD~D@ T116 PAD~D@

CC186

+1.35V_CPU_VDDQ

VCCSENSE_R

H_CPU_SVIDALRT# VR_SVID_CLK VIDSOUT

+VCC_CORE

+1.35V

CC151 0.1U_0402_10V7 K~D

CC152 0.1U_0402_10V7 K~D

+1.05VS

10K_0402_5%~D

12

@

RC80

CPU_PWR_DEBUG

10K_0402_5%~D

12

@

RC71

10U_0603_6.3V6M~D

1

CC161

2

CC163

CC162

2

10U_0603_6.3V6M~D

1

CC164

2

10U_0603_6.3V6M~D

1

CC165

2

12

T115 PAD~D@

+VCC_CORE

T151 PAD~D@ T152 PAD~D@

T153 PAD~D@

+VCCIO_OUT

T156 PAD~D@

+VCOMP_OUT

T160 PAD~D@ T159 PAD~D@ T184 PAD~D@ T154 PAD~D@

VIDSCLK61

CPU_PWR_DEBUG6

T157 PAD~D@ T158 PAD~D@ T162 PAD~D@ T163 PAD~D@

330U_D2_2VM_R6M~D

1

CC167

+

CC166

+

2

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

VCC VCC VCC VCC

VCC VCC

AA26 AA28 AA34 AA30 AA32 AB26 AB29 AB25 AB27 AB28 AB30 AB31 AB33 AB34 AB32 AC26 AB35 AC28 AD25 AC30 AD28 AC32 AD31 AC34 AD34 AD26 AD27 AD29 AD30 AD32 AD33 AD35 AE26 AE32 AE28 AE30 AG28 AG34 AE34 AF25 AF26 AF27 AF28 AF29 AF30 AF31 AF32 AF33 AF34 AF35 AG26 AH26 AH29 AG30 AG32 AH32 AH35 AH25 AH27 AH28 AH30 AH31 AH33 AH34 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AJ35 G25 H25 J25 K25 L25 M25 N25 P25 R25 T25

U25 U26 V25 V26

W26 W27

+VCC_CORE

22U_0805_6.3V6M~D

CH88

1

2

A A

5

4

22U_0805_6.3V6M~D

CH139

CH89

1

2

3

22U_0805_6.3V6M~D

CH138

1

2

CH136

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

22U_0805_6.3V6M~D

CH133

1

2

22U_0805_6.3V6M~D

CH132

CH131

1

2

CH137

1

2

2012/02/28 2013/02/27

22U_0805_6.3V6M~D

CH135

CH134

1

2

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

CPU (6/7) PWR

LA-9201P

1

0.1

10 6 6Tuesday, August 14 , 2012

5

4

3

2

1

D D

C C

B B

Haswell rPGA EDS

A10 A13 A16 A19 A22 A25 A27 A29

A3 A31 A33

A4

A7

AA11 AA25 AA27 AA31 AA29

AB1

AB10 AA33 AA35

AB3

AC25 AC27

AB4 AB6 AB7 AB9

AC11 AD11 AC29 AC31 AC33 AC35

AD7

AE1 AE10 AE25 AE29

AE3 AE27 AE35

AE4

AE6

AE7

AE9

AF11

AF6

AF8 AG11 AG25 AE31 AG31 AE33

AG6

AH1

AH10

AH2 AG27 AG29

AH3 AG33 AG35

AH4

AH5

AH6

AH7

AH8

AH9

AJ11

AJ5 AK11 AK25 AK26 AK28 AK29 AK30 AK32

E19

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

JCPU1F

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

RSVD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AK34 AK5 AL1 AL10 AL11 AL12 AL14 AL15 AL17 AL18 AL2 AL20 AL21 AL23 E22 AL3 AL4 AL5 AL6 AL7 AL8 AL9 AM10 AM13 AM16 AM19 E25 AM32 AM4 AM7 AN10 AN13 AN16 AN19 AN2 AN21 AN24 AN27 AN30 AN34 AN4 AN7 AP1 AP10 AP13 AP16 AP19 AP4 AP7 W25 AR10 AR13 AR16 AR19 AR2 AR22 AR25 AR28 AR31 AR34 AR4 AR7 AT10 AT13 AT16 AT19 AT21 AT24 AT27 AT3 AT30 AT4 AT7 B10 B13 B16 B19 B2 B22

Haswell rPGA EDS

B34

VSS

B4

VSS

B7

VSS

C1

VSS

C10

VSS

C13

VSS

C16

VSS

C19

VSS

C2

VSS

C22

VSS

C24

VSS

C26

VSS

C28

VSS

C30

VSS

C32

VSS

C34

VSS

C4

VSS

C7

VSS

D10

VSS

D13

VSS

D16

VSS

D19

VSS

D22

VSS

D25

VSS

D27

VSS

D29

VSS

D31

VSS

D33

VSS

D35

VSS

D4

VSS

D7

VSS

E1

VSS

E10

VSS

E13

VSS

E16

VSS

E4

VSS

E7

VSS

F10

VSS

F11

VSS

F12

VSS

F14

VSS

F15

VSS

F17

VSS

F18

VSS

F20

VSS

F21

VSS

F23

VSS

F24

VSS

F26

VSS

F28

VSS

F30

VSS

F32

VSS

F34

VSS

F4

VSS

F6

VSS

F7

VSS

F8

VSS

F9

VSS

G1

VSS

G11

VSS

G2

VSS

G27

VSS

G29

VSS

G3

VSS

G31

VSS

G33

VSS

G35

VSS

G4

VSS

G5

VSS

H10

VSS

H26

VSS

H6

VSS

H7

VSS

J11

VSS

J26

VSS

J28

RSVD

J30

VSS

J32

VSS

J34

VSS

J6

VSS

K1

VSS

JCPU1G

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS RSVD RSVD RSVD RSVD

VSS_SENSE

RSVD

K10 K2 K29 K3 K31 K33 K35 K4 K5 K7 K8 K9 L11 L26 L6 M11 M26 M28 M30 M32 M34 M6 N1 N10 N2 N29 N3 N31 N33 N35 N4 N5 N6 N7 N9 P11 P26 P5 R11 R26 R28 R30 R32 R34 R5 T1 T10 T29 T3 T31 T33 T35 T4 T6 T7 T9 U11 U27 V11 V28 V30 V32 V34 W1 W10 W3 W35 W4 W6 W7 W9 Y11 H11 AL24 F19 T26 AK35 AK33

VSSSENSE_R 10

T120PAD~D @

INTEL_HASWELL_HASWELL

CONN@

A A

5

6 OF 9

Security Classification

2012/02/28 2013/02/27

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

2012/02/28 2013/02/27

INTEL_HASWELL_HASWELL

CONN@

Compal Secret Data

Deciphered Date

7 OF 9

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

CPU (7/7) VSS

LA-9201P

1

0.1

11 66Tuesday, August 14, 2012

5

4

3

2

1

H:5.2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206 208

+1.35V+1.35V

DDR_A_D4 DDR_A_D5

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D6 DDR_A_D7

DDR_A_D12

DDR3_DRAMRST#_R

DDR_A_D14 DDR_A_D15

DDR_A_D20DDR_A_D16 DDR_A_D21

DDR_A_D22 DDR_A_D23

DDR_A_D28 DDR_A_D29

DDR_A_DQS#3 DDR_A_DQS3

DDR_A_D30 DDR_A_D31

DDR_CKE1_DIMM A

DDR_A_MA15 DDR_A_MA14

DDR_A_MA11DDR_A_MA12 DDR_A_MA7DDR_A_MA9

DDR_A_MA6DDR_A_MA8 DDR_A_MA4DDR_A_MA5

DDR_A_MA2 DDR_A_MA0

M_CLK_DDR1 M_CLK_DDR#1

DDR_A_BS1 DDR_A_RAS#

DDR_CS0_DIMMA # M_ODT0

M_ODT1

DDR_A_D36 DDR_A_D37

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D63

M_THERMAL# PCH_SMBDATA PCH_SMBCLK

+0.675VS

DDR_CKE1_DIMM A 7

M_CLK_DDR1 7 M_CLK_DDR#1 7

DDR_A_BS1 7 DDR_A_RAS# 7

DDR_CS0_DIMMA # 7 M_ODT0 7

M_ODT1 7

+V_SM_VREF_CN T

2.2U_0603_6.3V6K~D

1

2

M_THERMAL# 13,32

PCH_SMBDATA 6,13,17,38,39,40,42 PCH_SMBCLK 6,13,17,38,39,4 0,42

+1.35V

1U_0402_6.3V6K~D

1

CD3

2

10U_0603_6.3V6M~D

1

CD7

2

1U_0402_6.3V6K~D

1

CD4

CD5

2

10U_0603_6.3V6M~D

1

CD8

CD9

2

Layout Note: Place near JDIMM1.203,204

Layout Note: Place near JDIMM1

1U_0402_6.3V6K~D

1

CD6

2

10U_0603_6.3V6M~D

CD10

1

2

CD11

1

2

10U_0603_6.3V6M~D

CD12

1

2

330U_SX_2VY~D

1

@

CD14

CD13

1

+

2

2011/11/25 change to +0.675V

+0.675VS

1U_0402_6.3V6K~D

0.1U_0402_16V4Z~D

CD16

CD15

1

2

1U_0402_6.3V6K~D

CD18

CD17

1

2

1

2

1U_0402_6.3V6K~D

CD20

CD19

1

2

1 2

DDR_A_DQS#[0..7]7

DDR_A_DQS[0..7]7

DDR_A_D[0..63]7

DDR_A_MA[0..15 ]7

+1.35V

D D

DDR3_DRAMRST#_R13

C C

B B

1 2

RD24 1K_0402_ 1%~D

12

@

+DIMM0_1_V REF_CPU

1K_0402_1%~D

RD23

DDR3_DRAMRST#_CPU 6

RD1 0 _0402_5%~D

RD12

10K_0402_5 %~D

@

RD14

10K_0402_5 %~D

+3VS

1 2

DDR_CKE0_DIMM A7

DDR_CS1_DIMMA #7

RD13

@

10K_0402_5 %~D

1 2

+3VS

RD15

10K_0402_5 %~D

1 2

2.2U_0603_6.3V6K~D

CD2

1

2

DDR_A_BS27

M_CLK_DDR07 M_CLK_DDR#07

DDR_A_BS07

DDR_A_WE#7 DDR_A_CAS#7

0.1U_0402_16V4Z~D

1

2

0.1U_0402_16V4Z~D

CD1

DDR_CKE0_DIMM A

DDR_CS1_DIMMA #

2.2U_0603_6.3V6K~D

CD21

1

2

+DIMM0_VREF

DDR_A_D0 DDR_A_D1

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9 DDR_A_D13

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_D26 DDR_A_D27

DDR_A_BS2

DDR_A_MA3 DDR_A_MA1

M_CLK_DDR0 M_CLK_DDR#0

DDR_A_MA10 DDR_A_BS0

DDR_A_WE# DDR_A_CAS#

DDR_A_MA13

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_D58 DDR_A_D59

+0.675VS

CD22

JDIMM1

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

LCN_DAN06-K452 6-0102

CONN@

OK

VSS DQ4 DQ5 VSS

DQS0#

DQS0

VSS DQ6 DQ7 VSS

DQ12 DQ13

VSS DM1

RESET#

VSS

DQ14 DQ15

VSS

DQ20 DQ21

VSS DM2 VSS

DQ22 DQ23

VSS

DQ28 DQ29

VSS

DQS3#

DQS3

VSS

DQ30 DQ31

VSS

CKE1

VDD

A15

A14 VDD

A11

VDD

VDD CK1

CK1#

VDD

BA1

RAS#

VDD

S0#

ODT0

VDD

ODT1

VDD

VREF_CA

VSS

DQ36 DQ37

VSS DM4 VSS

DQ38 DQ39

VSS

DQ44 DQ45

VSS

DQS5#

DQS5

VSS

DQ46 DQ47

VSS

DQ52 DQ53

VSS DM6 VSS

DQ54 DQ55

VSS

DQ60 DQ61

VSS

DQS7#

DQS7

VSS

DQ62 DQ63

VSS

EVENT#

SDA SCL

VTT

GND2

BOSS2

A7

A6 A4

A2 A0

NC

2011/11/25 change to +0.675V

A A

Security Classification

2011/06/02 2012/06/02

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

5

4

3

2011/06/02 2012/06/02

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMMA

12 6 6Tuesday, August 14 , 2012

1

12 6 6Tuesday, August 14 , 2012

0.1

5

4

3

2

1

H:9.2

2011/11/25 change to +1.35V

+1.35V

1 2

+DIMM0_1_CA _CPU

DDR_B_DQS#[0..7]7

DDR_B_DQS[0..7]7

D D

DDR_B_D[0..63]7

DDR_B_MA[0..15 ]7

Layout Note: Place near JDIMMB

RD16 0_ 0402_5%~D

2.2U_0603_6.3V6K~D

CD23

1

2

Note: Check voltage tolerance of VREF_DQ at the DIMM socket

2011/11/25 change to +1.35V

+1.35V

1U_0402_6.3V6K~D

CD25

1

2

C C

+1.35V

10U_0603_6.3V6M~D

CD29

1

2

CD26

1

2

10U_0603_6.3V6M~D

CD31

CD30

1

2

Layout Note: Place near JDIMMB.203,204

1U_0402_6.3V6K~D

CD28

CD27

1

2

10U_0603_6.3V6M~D

CD33

CD32

1

2

10U_0603_6.3V6M~D

CD34

1

2

330U_SX_2VY~D

1

@

CD35

1

2

CD36

+

2

DDR_CKE2_DIMM B7

DDR_B_BS27

M_CLK_DDR27 M_CLK_DDR#27

DDR_B_BS07

DDR_B_WE#7 DDR_B_CAS#7

DDR_CS3_DIMMB #7

2011/11/25 change to +0.675V

+0.675VS

B B

1

2

1U_0402_6.3V6K~D

CD40

CD39

1

2

1U_0402_6.3V6K~D

CD42

CD41

1

2

10K_0402_5 %~D

RD19

RD21

+3VS

@

1 2

12

RD20

10K_0402_5 %~D

1 2

12

RD22

@

10K_0402_5 %~D

+3VS

0.1U_0402_16V4Z~D

CD24

+DIMM1_VREF

DDR_B_D0 DDR_B_D1

DDR_B_D2 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_D26 DDR_B_D27

DDR_CKE2_DIMM B

DDR_B_BS2

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

M_CLK_DDR2 M_CLK_DDR#2

DDR_B_MA10 DDR_B_BS0

DDR_B_WE# DDR_B_CAS#

DDR_B_MA13

DDR_CS3_DIMMB #

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51

DDR_B_D56 DDR_B_D57

DDR_B_D58 DDR_B_D59

+0.675VS

0.1U_0402_16V4Z~D

2.2U_0603_6.3V6K~D

CD43

1

2

CD44

JDIMM2

3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

73 75 77 79 81 83 85 87 89 91 93 95 97 99

101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205

LCN_DAN06-K492 6-0102

CONN@

OK

VREF_DQ1VSS1 VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25

CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1

G1

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6

DQ7 VSS8 DQ12 DQ13

VSS10

DM1

RESET#

VSS12

DQ14 DQ15

VSS14

DQ20 DQ21

VSS16

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS#3

DQS3

VSS24

DQ30 DQ31

VSS26

CKE1 VDD2

A15 A14

VDD4

A11

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

BA1

RAS#

VDD14

S0#

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

SCL

VTT2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

G2

2011/11/25 change to +0.675V

+1.35V

DDR_B_D4 DDR_B_D5

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D6 DDR_B_D7

DDR_B_D12 DDR_B_D13

DDR3_DRAMRST#

DDR_B_D14 DDR_B_D15

DDR_B_D20 DDR_B_D21

DDR_B_D22 DDR_B_D23

DDR_B_D28 DDR_B_D29

DDR_B_DQS#3 DDR_B_DQS3

DDR_B_D30 DDR_B_D31

DDR_CKE3_DIMM B

DDR_B_MA15 DDR_B_MA14

DDR_B_MA11 DDR_B_MA7

DDR_B_MA6 DDR_B_MA4

DDR_B_MA2 DDR_B_MA0

M_CLK_DDR3 M_CLK_DDR#3

DDR_B_BS1 DDR_B_RAS#

DDR_CS2_DIMMB # M_ODT2

M_ODT3

DDR_B_D36 DDR_B_D37

DDR_B_D38 DDR_B_D39

DDR_B_D44 DDR_B_D45

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D46 DDR_B_D47

DDR_B_D52 DDR_B_D53

DDR_B_D54 DDR_B_D55

DDR_B_D60 DDR_B_D61

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D62 DDR_B_D63

M_THERMAL# PCH_SMBDATA PCH_SMBCLK

+0.675VS

DDR3_DRAMRST#_R 12

DDR_CKE3_DIMM B 7

2011/11/25 change to +1.35V

M_CLK_DDR3 7 M_CLK_DDR#3 7

DDR_B_BS1 7 DDR_B_RAS# 7

DDR_CS2_DIMMB # 7 M_ODT2 7

M_ODT3 7

1

2

M_THERMAL# 12,3 2

PCH_SMBDATA 6,12,17,38,39,40,42

PCH_SMBCLK 6,12,17,38,39,4 0,42

+V_SM_VREF_CN T

0.1U_0402_16V4Z~D

2.2U_0603_6.3V6K~D

CD38

CD37

1

2

A A

Security Classification

2011/06/02 2012/06/02

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

5

4

3

2011/06/02 2012/06/02

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMMB

13 6 6Tuesday, August 14 , 2012

1

13 6 6Tuesday, August 14 , 2012

0.1

5

+RTC_CELL

330K_0402_1%~D

12

4

RH38

3

2

1

D D

INTVRMEN - INTEGRATED SUS 1.05V VRM ENABLE

High - Enable Internal VRs Low - Enable External VRs

+3VS

1 2

RH35 10K_ 0402_5%~D@

NO REBOOT STRAP

DISABLED WHEN LOW (DEFAULT) ENABLED WHEN HIGH

C C

+3VS

1 2

RH355 100K_0402_5 %~D

CMOS_CLR1

Shunt Clear CMOS

Open

ME_CLR1

Shunt Clear ME RTC Registers

Open

HDA_SYNC Isolation Circuit

B B

A A

PCH_INTVRMEN

330K_0402_1%~D

12

@

RH39

HDA_SPKR

PCH_GPIO33

CMOS setting

Keep CMOS

TPM setting

Keep ME RTC Registers

S

1M_0402_5%~D

SSM3K7002FU_ SC70-3~D

RH31

1 2

+3V_PCH

1 2

RH287 1K_0402_1%~ D@

FLASH DESCRIPTOR SECURITY OVERRIDE

LOW = DESABLED (DEFAULT) HIGH = ENABLED

+RTC_CELL

1

@

ME1 SHORT PADS~D

1 2

CH5 1U_ 0402_6.3V6K~D

G

2

13

PCH_AZ_SYNCPCH_AZ_SYNC_Q

D

QH8

PCH_AZ_SDOUT

1 2

RH22 20K_ 0402_5%~D

1 2

RH11 1M_ 0402_5%~D

1 2

RH23 20K_ 0402_5%~D

2

+3V_PCH

0_0603_5%~D

12

RH288

+3.3V_ALW_ PCH_JTAG PCH_JTAG_TMS

1

@

CMOS1 SHORT PADS~D

1 2

CH4

CMOS place near DIMM

RH59 51_ 0402_1%~D

RH44 210 _0402_1%~D

RH45 210 _0402_1%~D

RH46 210 _0402_1%~D

HDA for Codec and MDC

PCH_AZ_CODEC_SDOUT34

PCH_AZ_CODEC_SYNC34

PCH_AZ_CODEC_RST#34

PCH_AZ_CODEC_BITCLK34

1

CH2

1 2

18P_0402_5 0V8J~D

CH3

1 2

18P_0402_5 0V8J~D

2

1U_0402_6.3 V6K~D

12

1 2

@

1 2

@

1 2

@

1 2

RH33 33_ 0402_5%~D

1 2

RH32 33_ 0402_5%~D

1 2

RH36 33_ 0402_5%~D

1 2

RH34 33_ 0402_5%~D

27P_0402_50V8J~D

@

CH141

PCH_AZ_SDOUT

PCH_AZ_SYNC_Q

PCH_AZ_RST#

PCH_AZ_BITCLK

PCH_RTCX1_R

12

1 2

RH286 0_0402_5% ~D

YH1

32.768KHZ_12 .5PF_Q13FC1350000~D

PCH_AZ_CODEC_SDIN034

HDA_SDO32

DP_PCH_HPD23

100_0402_1%~D

12

RH48

RH50 1K _0402_1%~D

100_0402_1%~D

12

RH47

RH49

PCH_RTCX1

12

RH2 10M_0402_ 5%~D

PCH_RTCX2

SRTCRST#

INTRUDER#

PCH_INTVRMEN

PCH_RTCRST#

PCH_AZ_BITCLK

PCH_AZ_SYNC

HDA_SPKR34

1 2

DP_PCH_HPD+5VS

PCH_JTAG_TCK

PCH_JTAG_TDI

PCH_JTAG_TDO

HDA_SPKR

PCH_AZ_RST#

PCH_AZ_CODEC_SDIN0

PCH_AZ_SDOUT

PCH_GPIO33

1 2

RH289 0_0402_5%~ D

T122 PAD~D@

PCH_TP25

UH1A

B5

RTCX1

B4

RTCX2

B9

SRTCRST#

A8

INTRUDER#

G10

INTVRMEN

D9

RTCRST#

B25

HDA_BCLK

A22

HDA_SYNC

AL10

SPKR

C24

HDA_RST#

L22

HDA_SDI0

K22

HDA_SDI1

G22

HDA_SDI2

F22

HDA_SDI3

A24

HDA_SDO

B17

DOCKEN#/GPIO33

C22

HDA_DOCK_RST#/GPIO13

AB3

JTAG_TCK

AD1

JTAG_TMS

AE2

JTAG_TDI

AD3

JTAG_TDO

F8

TP25

C26

TP22

AB6

TP20

LPT_PCH_M_EDS

JTAGRTC AZALIA

LYNXPOINT_BGA695

5

1 OF 11

+3VS

PCH_GPIO21

BBS_BIT0_R

PCH_SATALED#

BC8

SATA_RXN_0 SATA_RXP_0

SATA_TXN_0 SATA_TXP_0

SATA_RXN_1 SATA_RXP_1

SATA_TXN_1 SATA_TXP_1

SATA

SATA_RXN_2 SATA_RXP_2

SATA_TXN_2 SATA_TXP_2

SATA_RXN_3 SATA_RXP_3

SATA_TXN_3 SATA_TXP_3

SATA_RXN4/PERN1 SATA_RXP4/PERP1

SATA_TXN4/PETN1 SATA_TXP4/PETP1

SATA_RXN5/PERN2

SATA_RXP5/PERP2

SATA_TXN5/PETN2 SATA_TXP5/PETP2

SATA_RCOMP

SATALED#

SATA0GP/GPIO21

SATA1GP/GPIO19

SATA_IREF

TP9

TP8

SATA_PRX_DTX_N0

BE8

SATA_PRX_DTX_P0

AW8

SATA_PTX_DRX_N0

AY8

SATA_PTX_DRX_P0

BC10 BE10

AV10 AW10

BB9

SATA_ODD_PRX_DTX_N2

BD9

SATA_ODD_PRX_DTX_P2

AY13

SATA_ODD_PTX_DRX_N2

AW13

SATA_ODD_PTX_DRX_P2

BC12

MSATA_PRX_DTX_N3

BE12

MSATA_PRX_DTX_P3

AR13

MSATA_PTX_DRX_N3

AT13

MSATA_PTX_DRX_P3

BD13

PCIE_PRX_WLANTX_N1

BB13

PCIE_PRX_WLANTX_P1

AV15

PCIE_PTX_WLANRX_N1

AW15

PCIE_PTX_WLANRX_P1

BC14

PCIE_PRX_WANTX_N2

BE14

PCIE_PRX_WANTX_P2

AP15

PCIE_PTX_WANRX_N2

AR15

PCIE_PTX_WANRX_P2

AY5

SATA_COMP

AP3

PCH_SATALED#

AT1

PCH_GPIO21

AU2

BBS_BIT0_R

BD4

SATA_IREF

BA2

BB2

T161PAD~ D @

T155PAD~ D @

SATA_PRX_DTX_N0 38 SATA_PRX_DTX_P0 38

SATA_PTX_DRX_N0 38 SATA_PTX_DRX_P0 38

SATA_ODD_PRX_DTX_N2 39 SATA_ODD_PRX_DTX_P2 39

SATA_ODD_PTX_DRX_N2 39 SATA_ODD_PTX_DRX_P2 39

MSATA_PRX_DTX_N3 39 MSATA_PRX_DTX_P3 39

MSATA_PTX_DRX_N3 39 MSATA_PTX_DRX_P3 39

PCIE_PRX_WLANTX_N1 40 PCIE_PRX_WLANTX_P1 40

PCIE_PTX_WLANRX_N1 40 PCIE_PTX_WLANRX_P1 40

PCIE_PRX_WANTX_N2 40 PCIE_PRX_WANTX_P2 40

PCIE_PTX_WANRX_N2 40 PCIE_PTX_WANRX_P2 40

PCH_SATALED# 37

12

+1.5VS

RH410_0402_1%~ D

1 2

RH3010K_0402_5 %~D

12

RH524.7K_0402_5 %~D

RH5510K_0402_5 %~D

HDD1

ODD/HDD2 Bay

mSATA

MiniWLAN (Mini Card 1)

MiniDMC (Mini Card 2)

SATA Impedance Compensation

+1.5VS

SATA_COMP

CAD note: Place the resistor within 500 mils of the PCH. Avoid routing next to clock pins.

1 2

RH407.5K_0402_1 %~D

2

Security Classification

2012/02/28 2013/02/27

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

5

4

3

2012/02/28 2013/02/27

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PCH (1/9) RTC,HDA,SATA,XDP

LA-9201P

1

14 6 6Thursday, August 16 , 2012

0.1

5

4

3

2

1

+3VS

5

1

B

2

A

3

RH139 64 9_0402_1%~D

PCH_INV_PWM24

IGPU_BKLT_EN24

PCH_ENVDD24 ,32

DGPU_SELECT#24, 27

HDMI_IN_PWM SEL#24

WL_OFF#40

DSWODVREN - ON DIE DSW VR ENABLE

HIGH = ENABLED (DEFAULT) LOW = DISABLED

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

+1.5VS

330K_0402_1%~D

1 2

330K_0402_1%~D

1 2

@

RH191

@

RH178

PCH_PWROK

IMVP_PWRGD

PCH_RSMRST#_R

PCH_DPWROK 32

PCIE_WAKE# 32,33,40

1 2

RH357 0_0402_5%~ D

+3VS

CH143

@

1 2

5

0.1U_0402_2 5V6K~D

1

D D

+3V_PCH

1 2

RH318 10K_0402 _5%~D@

1 2

RH149 10K_0402 _5%~D

1 2

@

RH148 10K_0402 _5%~D

1 2

RH153 10K_0402 _5%~D

1 2

RH172 10K_0402 _5%~D

+3VS

1 2

RH138 8.2K_0402 _5%~D

1 2

RH152 8.2K_0402 _5%~D@

DMI_CTX_PRX_N05 DMI_CTX_PRX_N15

DMI_CTX_PRX_N25 DMI_CTX_PRX_N35

DMI_CTX_PRX_P05

+1.5VS

RH379

10K_0402_5 %

QH21A

DMI_CTX_PRX_P15

DMI_CTX_PRX_P25 DMI_CTX_PRX_P35

DMI_CRX_PTX_N05 DMI_CRX_PTX_N15

DMI_CRX_PTX_N25 DMI_CRX_PTX_N35

DMI_CRX_PTX_P05 DMI_CRX_PTX_P15

DMI_CRX_PTX_P25 DMI_CRX_PTX_P35

RH43 0_0402_1%~D

RH204 7.5K_0402 _1%~D

RH114 0_0402_5%~ D@

RH193 0_0402_5%~ D

RH144 0_0402_5%~ D

RH150 0_0402_5%~ D

RH320 0_0402_5%~ D

RH185 0_0402_5%~ D

RH200 0_0402_5%~ D

RH163 0_0402_5%~ D

RH156 8.2K_0402_5 %~D

+3V_PCH

12

61

2

C C

SG_AMD_BKL24,32

SYS_PWROK6

PCH_PWROK32

PM_DRAM_PW RGD6

PCH_RSMRST#32

B B

A A

SUSPWRDNACK32

PBTN_OUT#6,32

+PCH_VCCDSW3_ 3

ACIN32,36,56 ,63

2N7002DW-T/R7 _SOT363-6

SUS_STAT#

SUSPWRDNACK

PCIE_WAKE#

WAKE#

PCH_RI#

1 2

T140 PAD~D@

+3V_PCH

5

PM_CLKRUN#

ME_RESET#

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1

DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1

DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1

DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1

DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

12

DMI_IREF

T139 PAD~D@

T123 PAD~D@

12

3

4

DMI_RCOMP

SUSACK#_R

SYS_RESET#

SYS_PWROK_R

PCH_PWROK_R

PM_APWROK_R

PM_DRAM_PW RGD_R

PCH_RSMRST#_R

ME_SUS_PWR_ ACK_R

SIO_PWRBTN#_R

PCH_BATLOW#

PCH_RI#

RH378 10K_0402_5 %

ACIN_PCH

QH21B 2N7002DW-T/R7 _SOT363-6

ACIN_PCH

XDP_DBRESET#6

RH199 8.2K_0402_5%~ D@

UH1B

AW22

DMI_RXN_0

AR20

DMI_RXN_1

AP17

DMI_RXN_2

AV20

DMI_RXN_3

AY22

DMI_RXP_0

AP20

DMI_RXP_1

AR17

DMI_RXP_2

AW20

DMI_RXP_3

BD21

DMI_TXN_0

BE20

DMI_TXN_1

BD17

DMI_TXN_2

BE18

DMI_TXN_3

BB21

DMI_TXP_0

BC20

DMI_TXP_1

BB17

DMI_TXP_2

BC18

DMI_TXP_3

BE16

DMI_IREF

AW17

TP12

AV17

TP7

AY17

DMI_RCOMP

R6

SUSACK#

AM1

SYS_RESET#

AD7

SYS_PWROK

F10

PWROK

AB7

APWROK

H3

DRAMPWROK

J2

RSMRST#

J4

SUSWARN#/SUSPWRNACK/GPIO30

K1

PWRBTN#

E6

ACPRESENT/GPIO31

K7

BATLOW#/GPIO72

N4

RI#

AB10

TP21

D2

SLP_WLAN#/GPIO29

BBS_BIT1

1K_0402_1%~D

12

@

RH342

12

ME_RESET#

ME_SUS_PWR_ ACK_R SUSACK#_R

LPT_PCH_M_EDS

DMI

LYNXPOINT_BGA695

RH323 0_0402_5 %~D

5

System Power

Management

4 OF 11

BBS_BIT1 Boot BIOS Location

0 1 Reserved (NAND)

1 0

*

P

B

4

O

2

A

G

@

74AHC1G09GW_ TSSOP5~D

3

1 2

FDI_RXN_0

FDI_RXN_1

FDI

FDI_RXP_0

FDI_RXP_1

FDI_CSYNC

FDI_IREF

FDI_RCOMP

DSWVRMEN

DPWROK

CLKRUN#

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

SLP_S4#

SLP_S3#

SLP_SUS#

PMSYNCH

SLP_LAN#

Boot BIOS Strap

SATA_SLPD (BBS_BIT0)

00 LPC

11 SPI

UC3

TP16

TP5

TP15

TP10

FDI_INT

TP17

TP13

WAKE#

SLP_A#

AJ35

AL35

AJ36

AL36

AV43

AY45

AV45

AW44

AL39

AL40

AT45

AU42

AU44

AR44

C8

L13

K3

AN7

U7

Y6

Y7

C6

H1

F3

F1

AY3

G5

PCI

SYS_RESET#

FDI_CSYNC

FDI_INT

FDI_IREF

FDI_RCOMP

DSWODVREN

PCH_DRWROK_R

WAKE#

RH188 0_04 02_5%~D@

PM_CLKRUN#

SUS_STAT#

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

PM_SLP_SUS#

H_PM_SYNC

IMVP_PWRGD6,32,61

T175PAD~D @

T177PAD~D @

T178PAD~D @

T179PAD~D @

T144PAD~D @

T141PAD~D @

T147PAD~D @

T148PAD~D @

FDI_CSYNC 5

FDI_INT 5

12

RH420_0402_1% ~D

T145PAD~D @

T146PAD~D @

12

RH2067.5K_0402_1% ~D

1 2

RH167 0_ 0402_5%~D

1 2

RH186 0_ 0402_5%~D@

1 2

T129 PAD~D@

T126 PAD~D@

PM_SLP_S5# 32,36

T125 PAD~D

PM_SLP_S4# 32

T143 PAD~D

PM_SLP_S3# 32,36

T128 PAD~D

PM_SLP_SUS# 32

T127 PAD~D

H_PM_SYNC 6

+RTC_CELL

DSWODVREN

GPIO51 has internal pull up.

5

4

3

CH142

1 2

0.1U_0402_2 5V6K~D

P

4

SYS_PWROK

O

G

UH8

TC7SH08FU_SSOP5~D

1 2

PCH_INV_PWM

IGPU_BKLT_EN

PCH_ENVDD

PCI_PIRQA#

PCI_PIRQB#

PCI_PIRQC#

PCI_PIRQD#

DGPU_SELECT#

BBS_BIT1

HDMI_IN_PWM SEL#

WL_OFF#

T45

U44

V45

M43

M45

N42

N44

U40

U39

N36

K36

G36

H20

L20

K17

M20

A12

B13

C12

C10

A10

AL6

VGA_BLUE

VGA_GREEN

VGA_RED

VGA_DDC_CLK

VGA_DDC_DATA

VGA_HSYNC

VGA_VSYNC

DAC_IREF

VGA_IRTN

EDP_BKLTCTL

EDP_BKLTEN

EDP_VDDEN

PIRQA#

PIRQB#

PIRQC#

PIRQD#

GPIO50

GPIO52

GPIO54

GPIO51

GPIO53

GPIO55

LYNXPOINT_BGA695

LPT_PCH_M_EV

LVDSCRT

5UH1E

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPB_AUXN

DDPC_AUXN

DISPLAY

PCI

5 OF 11

DDPD_AUXN

DDPB_AUXP

DDPC_AUXP

DDPD_AUXP

DDPB_HPD

DDPC_HPD

DDPD_HPD

PIRQE#/GPIO2

PIRQF#/GPIO3

PIRQG#/GPIO4

PIRQH#/GPIO5

PME#

PLTRST#

PCH_PLTRST#

A16 SWAP OVERRIDE STRAP

STP_A16OVR

Compal Secret Data

2012/02/28 2013/02/27

Compal Secret Data

LOW = A16 SWAP OVERRIDE HIGH = DEFAULT

Deciphered Date

2

R40

PCH_DPB_HDMI_CL K

R39

PCH_DPB_HDMI_DAT

R35

R36

N40

PCH_DPD_CLK

N38

PCH_DPD_DAT

H45

K43

J42

H43

K45

J44

K40

PCH_HDMI_HPD

K38

H39

PCH_DMC_HPD

G17

BT_ON#

F17

DP_CBL_DET

L15

ODD_DA#

M15

FFS_INT1

AD10

Y11

PCH_PLTRST#

+3VS

5

1

P

B

2

A

G

3

PCH_DPB_HDMI_CL K 2 7

PCH_DPB_HDMI_DAT 27

PCH_DPD_CLK 30

PCH_DPD_DAT 30

PCH_HDMI_HPD 27

PCH_DMC_HPD 30

BT_ON# 40

DP_CBL_DET 23

ODD_DA# 39

T124 PAD~D@

0.1U_0402_2 5V6K~D

O

TC7SH08FU_SSOP5~D

FFS_INT1 38

PCH_PLTRST# 46

CH144

1 2

4

PLT_RST

UH3

BT_ON#

ODD_DA#

WL_OFF#

HDMI_IN_PWM SEL#

PCI_PIRQA#

PCI_PIRQB#

PCI_PIRQC#

PCI_PIRQD#

Title

Size Document Number Rev

Custom

LA-9201P

Date: Sheet of

+3VS

12

RH367 10K_0402_5 %~D

@

PLT_RST# 6,31,32 ,33,40

12

RH201 100K_0402_ 5%~D

+3VS

12

RH3668.2K_0402_5 %~D

12

RH3658.2K_0402 _5%~D

12

RH3628.2K_0402 _5%~D

12

RH3528.2K_0402 _5%~D

12

RH3248.2K_0402 _5%~D

12

RH3258.2K_0402 _5%~D

12

RH3268.2K_0402 _5%~D

12

RH3298.2K_0402 _5%~D

1 2

RH351 10K_0402 _5%~D@

PM_CLKRUN#

Compal Electronics, Inc.

PCH (2/9) DMI,FDI,PM,DP,CRT

15 6 6Tuesday, August 14 , 2012

1

15 6 6Tuesday, August 14 , 2012

HDMI

DMC

0.1

5

D D

4

3

2

1

UH1C

Y43

CLKOUT_PCIE_N_0

Y45

CLKOUT_PCIE_P_0

AB1

PCIECLKRQ0#/GPIO73

AA44

CLKOUT_PCIE_N_1

AA42

CLKOUT_PCIE_P_1

AF1

PCIECLKRQ1#/GPIO18

AB43

CLKOUT_PCIE_N_2

AB45

CLKOUT_PCIE_P_2

AF3

PCIECLKRQ2#/GPIO20/SMI#

AD43

CLKOUT_PCIE_N_3

AD45

CLKOUT_PCIE_P_3

T3

PCIECLKRQ3#/GPIO25

AF43

CLKOUT_PCIE_N_4

AF45

CLKOUT_PCIE_P_4

V3

PCIECLKRQ4#/GPIO26

AE44

CLKOUT_PCIE_N5

AE42

CLKOUT_PCIE_P_5

AA2

PCIECLKRQ5#/GPIO44

AB40

CLKOUT_PCIE_N_6

AB39

CLKOUT_PCIE_P_6

AE4

PCIECLKRQ6#/GPIO45

AJ44

CLKOUT_PCIE_N_7

AJ42

CLKOUT_PCIE_P_7

Y3

PCIECLKRQ7#/GPIO46

AH43

CLKOUT_ITPXDP

AH45

CLKOUT_ITPXDP_P

D44

CLKOUT_33MHZ0

E44

CLKOUT_33MHZ1

B42

CLKOUT_33MHZ2

F41

CLKOUT_33MHZ3

A40

CLKOUT_33MHZ4

CLOCK SIGNAL

LYNXPOINT_BGA695

1 2

12

12 12

12 12 12

12

12 12

12

T142 PAD~D@

T138 PAD~D@

MiniWLAN (Mini Card 1)

DMC (Mini Card 2)

10/100/1G LAN

C C

B B

Card Reader

CLK_PCI_LPC32

CLK_DEBUG40

CLK_PCIE_MINI1 #40

CLK_PCIE_MINI140

+3V_PCH

MINI1CLK_REQ#4 0

CLK_PCIE_MINI2 #40

CLK_PCIE_MINI240

MINI2CLK_REQ#4 0

CLK_PCIE_LAN#3 3

CLK_PCIE_LAN33

LANCLK_REQ#33

CLK_PCIE_CD#31

CLK_PCIE_CD31

CDCLK_REQ#31

+3V_PCH

CLK_CPU_ITP#6

CLK_CPU_ITP6

CLK_PCI_LPBACK CLK_PCI0

CLK_PCI_LPC CLK_PCI1

RH307 0_0402_5 %~D

RH308 0_0402_5 %~D RH142 10K_0402 _5%~D

RH99 0_0402_5%~D RH98 0_0402_5%~D RH145 10K_0402_5% ~D

+3VS

RH158 0_0402_5 %~D

RH147 0_0402_5 %~D

+3VS

RH28 10K_ 0402_5%~D

RH129 0_0402_5 %~D RH124 0_0402_5 %~D

RH126 10K_0402 _5%~D

+3V_PCH

RH128 10K_0402 _5%~D

RH132 10K_0402 _5%~D

RH133 10K_0402 _5%~D

RH127 10K_0402 _5%~D

RH280 0_0402_5 %~D

RH281 0_0402_5 %~D

RH169 22_0402_ 5%~D

RH111 22_0402_ 5%~D

RH151 22_0402_ 5%~D

PCIE_MINI1#

PCIE_MINI1

MINI1CLK_REQ#

PCIE_MINI2# PCIE_MINI2

MINI2CLK_REQ#

PCIE_LAN#

PCIE_LAN

LANCLK_REQ#

PCIE_EXP# PCIE_EXP CDCLK_REQ#

CLK_BCLK_ITP#

CLK_BCLK_ITP

CLK_PCI2CLK_DEBUG

CLK_PCI3

CLK_PCI4

LPT_PCH_M_EDS

5

2 OF 11

CLKOUT_PEG_A

CLKOUT_PEG_A_P

PEGA_CLKRQ#/GPIO47

CLKOUT_PEG_B

CLKOUT_PEG_B_P

PEGB_CLKRQ#/GPIO56

CLKOUT_DMI

CLKOUT_DMI_P

CLKOUT_DP

CLKOUT_DP_P

CLKOUT_DPNS

CLKOUT_DPNS_P

CLKIN_DMI

CLKIN_DMI_P

CLKIN_GND

CLKIN_GND_P

CLKIN_DOT96N CLKIN_DOT96P

CLKIN_SATA

CLKIN_SATA_P

REFCLK14IN

CLKIN_33MHZLOOPBACK

XTAL25_IN

XTAL25_OUT

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

ICLK_IREF

TP19 TP18

DIFFCLK_BIASREF

AB35

AB36

AF6

Y39

Y38

U4

AF39

CLK_CPU_DMI#

AF40

CLK_CPU_DMI

AJ40

CLK_CPU_SSC_DPLL #

AJ39

CLK_CPU_SSC_DPLL

AF35

CLK_CPU_DPLL#

AF36

CLK_CPU_DPLL

AY24

CLK_BUF_DMI#

AW24

CLK_BUF_DMI

AR24

CLK_BUF_BCLK#

AT24

CLK_BUF_BCLK

H33

CLK_BUF_DOT96#

G33

CLK_BUF_DOT96

BE6

CLK_BUF_CKSSCD#

BC6

CLK_BUF_CKSSCD

F45

CLK_PCH_14M

D17

CLK_PCI_LPBACK

AL44 AM43

C40

F38

DMC_PCH_DET#

F36

PCH_GPIO66

F39

CAM_DET#

AM45

ICLK_IREF

AD39 AD38

AN44

PCH_CLK_BIASREF

CLK_PCIE_VGA#

CLK_PCIE_VGA

CLK_REQ_VGA#

XTAL25_IN XTAL25_OUT

CAM_DET#

DMC_PCH_DET#

PCH_GPIO66

CLK_PCIE_VGA# 46

CLK_PCIE_VGA 46

CLK_REQ_VGA# 4 6

1 2

RH76 10K_0402_5 %~D

12

RH12510K_0402_5 %~D

T176PAD~D @

1 2

T149PAD~D @ T150PAD~D @

1 2

+3V_PCH

CLK_CPU_DMI# 6

CLK_CPU_DMI 6

CLK_CPU_SSC_DPLL # 6 CLK_CPU_SSC_DPLL 6

CLK_CPU_DPLL# 6 CLK_CPU_DPLL 6

DMC_PCH_DET# 40

CAM_DET# 25

RH540_0402_1%~ D

+1.05V_+1.5V _RUN

RH2087.5K_0402 _1%~D

1 2

+1.5VS

RH21610K_0402_5 %~D

RH21710K_0402_5 %~D

RH21810K_0402_5 %~D

CLK_BUF_DMI# CLK_BUF_DMI

CLK_BUF_BCLK# CLK_BUF_BCLK

CLK_BUF_DOT96# CLK_BUF_DOT96

CLK_BUF_CKSSCD# CLK_BUF_CKSSCD

CLK_PCH_14M

1 2

RH74 1 0K_0402_5%~D

1 2

RH75 1 0K_0402_5%~D

1 2

RH105 10K_0402_ 5%~D

1 2

RH157 10K_0402_ 5%~D

1 2

RH143 10K_0402_ 5%~D

1 2

RH130 10K_0402_ 5%~D

1 2

RH146 10K_0402_ 5%~D

1 2

RH155 10K_0402_ 5%~D

1 2

RH205 10K_0402_ 5%~D

CLOCK TERMINATION for FCIM and need close to PCH

12

1 2

RH309 0_0402_5 %~D RH131 1M_0402 _5%~D

YH4

3

4

OUT

GND

IN

GND

+3VS

25MHZ_10PF_ Q22FA2380049900~D

8.2P_0402_50V8D~D

2

CH18

1

XTAL25_IN_R

1

2

8.2P_0402_50V8D~D

CH19

2

1

A A

Security Classification

2012/02/28 2013/02/27

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

5

4

3

2012/02/28 2013/02/27

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PCH (3/9) CLK

LA-9201P

1

16 6 6Tuesday, August 14 , 2012

0.1

5

D D

+3VS

1 2

RH337 10K_0402_5%~D

C C

SERIRQ

LPC_AD032,40

LPC_AD132,40

LPC_AD232,40

LPC_AD332,40

LPC_FRAME#32,40

SERIRQ32

LPC_AD0

LPC_AD1

LPC_AD2

LPC_AD3

LPC_FRAME#

SERIRQ

PCH_SPI_CLK

PCH_SPI_CS0#

PCH_SPI_SI

PCH_SPI_SO

PCH_SPI_DO2

PCH_SPI_DO3

4

A20

C20

A18

C18

B21

D21

G20

AL11

AJ11

AJ7

AL7

AJ10

AH1

AH3

AJ4

AJ2

MEM_SMBCLK

MEM_SMBDATA

UH1D

LAD_0

LAD_1

LAD_2

LAD_3

LFRAME#

LDRQ0#

LDRQ1#/GPIO23

SERIRQ

SPI_CLK

SPI_CS0#

SPI_CS1#

SPI_CS2#

SPI_MOSI

SPI_MISO

SPI_IO2

SPI_IO3

SPILPC

3

QH9B

DMN66D0LDW -7_SOT363-6~D

LPT_PCH_M_EDS

SMBus

C-Link

Thermal

+3VS

RH304

2

2.2K_0402_5 %~D

6 1

5

SML1ALERT#/PCHHOT#/GPIO74

QH9A

DMN66D0LDW -7_SOT363-6~D

4

SMBALERT#/GPIO11

SMBDATA

SML0ALERT#/GPIO60

SML0CLK

SML0DATA

SML1CLK/GPIO58

SML1DATA/GPIO75

+3VS

12

SMBCLK

CL_CLK

CL_DATA

CL_RST#

TP1

TP2

TP4

TP3

TD_IREF

3

12

N7

R10

U11

N8

U8

R7

H6

K6

N11

AF11

AF10

AF7

BA45

BC45

BE43

BE44

AY43

RH310

2.2K_0402_5 %~D

PCH_SMBCLK 6,1 2,13,38,39,40,42

PCH_SMBDATA 6,12, 13,38,39,40,42

1 2

RH368 0_0402_5%~D

PCH_LID_SW_ IN#

MEM_SMBCLK

MEM_SMBDATA

DDR_HVREF_RST_PCH

LAN_SMBCLK

LAN_SMBDATA

PCH_GPIO74

SML1CLK

SML1DATA

PCH_TD_IREF

RH322 8.2K_0402 _1%

1 2

RH369 0_0402_5%~D

@

T130PAD~D @

T133PAD~D @

T131PAD~D @

T132PAD~D @

1 2

SML1CLK

SML1DATA

+3VS

5

3

QH10B

DMN66D0LDW -7

EC_LID_OUT# 32

LID_SW_IN# 32,3 6,37

2

6 1

QH10A

4

2

DMN66D0LDW -7

EC_SMB_CK2 32,42,4 3,46

EC_SMB_DA2 32,42,4 3,46

MEM_SMBCLK

MEM_SMBDATA

DDR_HVREF_RST_PCH

PCH_GPIO74

SML1CLK

SML1DATA

LAN_SMBCLK

LAN_SMBDATA

1 2

1

+3V_PCH

12

RH3022.2K_0402_5 %~D

12

RH3032.2K_0402_5 %~D

12

RH3001K_0402_1% ~D

12

RH30110K_0402_5 %~D

RH2982.2K_0402_5 %~D

RH2992.2K_0402_5 %~D

+3V_PCH

12

RH3052.2K_0402_5 %~D

12

RH3062.2K_0402_5 %~D

VCC

/HOLD

CLK

DIO

3 OF 11 5

+3V_PCH

8

7

6

PCH_SPI_CLK_R

5

PCH_SPI_SI_R

CH155

1 2

0.1U_0402_2 5V6K~D

1 2

RH373 33_0402_5% ~D

1 2

RH376 33_0402_5% ~D

1 2

RH377 33_0402_5% ~D

PCH_SPI_DO3SPI_PCH_DO3_R

PCH_SPI_CLK

PCH_SPI_SI

PCH_SPI_CLK

RH60

@

33_0402_5% ~D

1 2

22P_0402_50V8J~D

1

@

CH8

2

Reserve for EMI please close to UH14

LYNXPOINT_BGA695

+3V_PCH

1 2

RH370 3.3K_0402_5%~ D

1 2

RH371 3.3K_0402_5%~ D

B B

A A

SPI_PCH_DO3_R

SPI_PCH_DO2_R

PCH_SPI_CS0# PCH_SPI _CS0#_R

PCH_SPI_SO PCH_SPI_S0_R

PCH_SPI_DO2

1 2

RH374 47_0402_5 %~D

1 2

RH372 33_0402_5 %~D

1 2

RH375 33_0402_5 %~D

+3V_PCH

1 2

RH58

3.3K_0402_5 %~D

@

SPI_PCH_DO2_R

200 MIL SO8

64Mb Flash ROM

UH14

1

/CS

2

DO

3

/WP

4

GND

W25Q64FVSSI G_SO8~D

Security Classification

2012/02/28 2013/02/27

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

5

4

3

2012/02/28 2013/02/27

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PCH (4/9) SPI, SMBUS,LPC

LA-9201P

1

17 6 6Monday, Augu st 20, 2012

0.1

5

D D

4

3

2

1

UH1I

AW31

PERN1/USB3RN3

AY31

PERP1/USB3RP3

BE32

PETN1/USB3TN3

BC32

PETP1/USB3TP3

AT31

PERN2/USB3RN4

AR31

PERP2/USB3RP4

BD33

PETN2/USB3TN4

BB33

PETP2/USB3TP4

PCIE_PRX_GLANTX_N133

10/100/1G LAN

CARD READER

C C

B B

PCIE_PRX_GLANTX_P13 3

PCIE_PTX_GLANRX_N133 PCIE_PTX_GLANRX_P133

PCIE_PRX_CARDTX_N431 PCIE_PRX_CARDTX_P431

PCIE_PTX_CARDRX_N431 PCIE_PTX_CARDRX_P431

1 2

CH149 0.1U_0402_25V6 K~D

1 2

CH150 0.1U_0402_25V6 K~D

1 2

CH153 0.1U_0402_25V6 K~D

1 2

CH154 0.1U_0402_25V6 K~D

+1.5VS

RH51 0_0402_1%~D

RH210 7.5K_0402_1 %~D

PCIE_PRX_GLANTX_N1 PCIE_PRX_GLANTX_P1

PCIE_PTX_GLANRX_N1_C PCIE_PTX_GLANRX_P1_C

PCIE_PRX_CARDTX_N4 PCIE_PRX_CARDTX_P4

PCIE_PTX_CARDRX_N4_C PCIE_PTX_CARDRX_P4_C

1 2

T134 PAD~D@

T136 PAD~D@

1 2

PCH_PCIE_IREF

PCH_PCIE_RCOMP

AW33

AY33

BE34 BC34

AT33 AR33

BE36 BC36

AW36

AV36

BD37 BB37

AY38

AW38

BC38 BE38

AT40 AT39

BE40 BC40

AN38 AN39

BD42 BD41

BE30

BC30

BB29

BD29

PERN_3 PERP_3

PETN_3 PETP_3

PERN_4 PERP_4

PETN_4 PETP_4

PERN_5 PERP_5

PETN_5 PETP_5

PERN_6 PERP_6

PETN_6 PETP_6

PERN_7 PERP_7

PETN_7 PETP_7

PERN_8 PERP_8

PETN_8 PETP_8

PCIE_IREF

TP11

TP6

PCIE_RCOMP

LPT_PCH_M_EDS

LYNXPOINT_BGA695

PCIe

USB

9 OF 11 5

USB2N0

USB2P0

USB2N1

USB2P1

USB2N2

USB2P2

USB2N3

USB2P3

USB2N4

USB2P4

USB2N5

USB2P5

USB2N6

USB2P6

USB2N7

USB2P7

USB2N8

USB2P8

USB2N9

USB2P9 USB2N10 USB2P10 USB2N11 USB2P11 USB2N12 USB2P12 USB2N13 USB2P13

USB3RN1 USB3RP1 USB3TN1

USB3TP1

USB3RN2 USB3RP2 USB3TN2

USB3TP2

USB3RN5 USB3RP5 USB3TN5

USB3TP5

USB3RN6 USB3RP6 USB3TN6

USB3TP6

USBRBIAS#

USBRBIAS

TP24 TP23

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

B37 D37 A38 C38 A36 C36 A34 C34 B33 D33 F31 G31 K31 L31 G29 H29 A32 C32 A30 C30 B29 D29 A28 C28 G26 F26 F24 G24

AR26 AP26 BE24 BD23 AW26 AV26 BD25 BC24 AW29 AV29 BE26 BC26 AR29 AP29 BD27 BE28

K24 K26

M33 L33

P3

USB_OC0#

V1

USB_OC1#

U2

USB_OC2#

P1 M3

USB_OC4#

T1

USB_OC5#

N2

USB_OC6#

M1

USB_OC7#

USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2

USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6

USB20_N11 USB20_P11 USB20_N12 USB20_P12

USB3RN1 USB3RP1 USB3TN1 USB3TP1 USB3RN2 USB3RP2 USB3TN2 USB3TP2 USB3RN5 USB3RP5 USB3TN5 USB3TP5

USBRBIAS

USB20_N0 41 USB20_P0 41 USB20_N1 41 USB20_P1 41 USB20_N2 42 USB20_P2 42

USB20_N4 40 USB20_P4 40 USB20_N5 40 USB20_P5 40 USB20_N6 36 USB20_P6 36

USB20_N11 25 USB20_P11 25 USB20_N12 42 USB20_P12 42

USB3RN1 41 USB3RP1 41

USB3TN1 41

USB3TP1 41 USB3RN2 41 USB3RP2 41

USB3TN2 41

USB3TP2 41 USB3RN5 42 USB3RP5 42

USB3TN5 42

USB3TP5 42

T135PAD~ D @ T137PAD~ D @

USB_OC0# 41 USB_OC1# 41 USB_OC2# 42

JUSB1

JUSB2

JUSB3

Mini Card(WLAN)

Mini Card(DMC)

ELC LED

eDP Camera

VPK K/B

P1: JUSB1

P2: JUSB2

P5: JUSB3

USBRBIAS

CAD NOTE: Route single-end 50-ohms and max 500-mils length. Avoid routing next to clock pins or under stitching capacitors. Recommended minimum spacing to other signal traces is 15 mils.

22.6_0402_1%~D

12

USB_OC4# USB_OC7#USB_OC3# USB_OC6# USB_OC3#

USB_OC0# USB_OC5# USB_OC2# USB_OC1#

RH160

RPH1

4 5 3 6 2 7 1 8

10K_1206_8 P4R_5%~D

RPH2

4 5 3 6 2 7 1 8

10K_1206_8 P4R_5%~D

+3V_PCH

A A

Security Classification

2012/02/28 2013/02/27

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

5

4

3

2012/02/28 2013/02/27

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PCH (5/9) PCIE,USB

LA-9201P

1

18 6 6Tuesday, August 14 , 2012

0.1

5

4

3

2

1

D D

+3VS

1 2

RH270 10K_0402 _5%~D

1 2

RH271 10K_0402 _5%~D

1 2

RH164 10K_0402 _5%~D

RH179 10K_0402 _5%~D

1 2

RH256 10K_0402 _5%~D

1 2

RH258 10K_0402 _5%~D

1 2

RH261 10K_0402 _5%~D

1 2

RH263 10K_0402 _5%~D

+3V_PCH

RH187 10K_0402 _5%~D

1 2

RH354 1K_0402_ 1%~D

RH182 10K_0402 _5%~D

RH264 10K_0402 _5%~D

RH269 10K_0402_5% ~D@

C C

+3V_PCH

4.7K_0402_5%~D

RH53

1 2

PCH_GPIO28

1K_0402_1%~D

12

@

RH353

12

PCH_GPIO22

PCH_GPIO39

PCH_GPIO70

EDP_CAB_DET#

12

PCH_GPIO27

DMC_RADIO_OFF#

DGPU_EDIDSEL#

DGPU_HPD_INT#

STP_PCI#

HDD_DET#

PCH_GPIO15

ODD_EN#

PCH_GPIO35

DMC_RADIO_OFF#40

DGPU_EDIDSEL#24,27

DGPU_HPD_INT#27,30

EC_SCI#32

EC_SMI#32

ODD_EN#39

PCH_GPIO3527

ODD_DETECT#39

FFS_INT238,39

HDD_DET#38

DGPU_BKL_PWM _SEL#24

EDP_CAB_DET#25

WiGi_RADIO_DIS #40

1 2

RH162 0_0402_5 %~D

DMC_RDIO_OFF#

DGPU_EDIDSEL#

DGPU_HPD_INT#

EC_SCI#

EC_SMI#

PCH_GPIO15

PCH_GPIO16

PCH_GPIO22

ODD_EN#

PCH_GPIO27

PCH_GPIO28

STP_PCI#

PCH_GPIO35

ODD_DETECT#

PCH_GPIO37

DGPU_PRSNT#

PCH_GPIO39

FFS_INT2

PCH_GPIO49

HDD_DET#

DGPU_BLK_PWM _SLE#

EDP_CAB_DET#

PCH_GPIO70

WiGi_RADIO_DIS #

TP_VSS_NCTF

UH1F

AT8

BMBUSY#/GPIO0

F13

TACH1/GPIO1

A14

TACH2/GPIO6

G15

TACH3/GPIO7

Y1

GPIO8

K13

LAN_PHY_PWR_CTRL/GPIO12

AB11

GPIO15

AN2

SATA4GP/GPIO16

C14

TACH0/GPIO17

BB4

SCLOCK/GPIO22

Y10

GPIO24

R11

GPIO27

AD11

GPIO28

AN6

GPIO34

AP1

GPIO35/NMI#

AT3

SATA2GP/GPIO36

AK1

SATA3GP/GPIO37

AT7

SLOAD/GPIO38

AM3

SDATAOUT0/GPIO39

AN4

SDATAOUT1/GPIO48

AK3

SATA5GP/GPIO49

U12

GPIO57

C16

TACH4/GPIO68

D13

TACH5/GPIO69

G13

TACH6/GPIO70

H15

TACH7/GPIO71

BE41

VSS

BE5

VSS

C45

VSS

A5

VSS

LPT_PCH_M_EDS

LYNXPOINT_BGA695

GPIO

NCTF

6 OF 11 5

CPU/Misc

TP14

PECI

RCIN#

PROCPWRGD

THRMTRIP#

PLTRST_PROC#

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AN10

AY1

AT6

AV3

AV1

AU4

N10

A2 A41 A43 A44 B1 B2 B44 B45 BA1 BC1 BD1 BD2 BD44 BD45 BE2 BE3 D1 E1 E45 A4

GATEA20

12

RH184

@

0_0402_5%~ D

KB_RST#

H_CPUPWRGD

PCH_THRMTRIP#_R_R

CPU_PLTRST#

PCH_VSS_A44

PCH_VSS_B45

PCH_VSS_BD1

GATEA20 32

H_PECI 6,32

KB_RST# 32

H_CPUPWRGD 6

CPU_PLTRST# 6

RH262 39 0_0402_5%

1 2

0_0402_5%~D

@

RH166

0_0402_5%~D

RH165

GATEA20

KB_RST#

1 2

PCH_VSS_A44

1 2

H_THERMTRIP# 6, 46

0_0402_5%~D

+5VALW+5VS

@

RH175

RH168

12

RH16110K_0402_ 5%~D

12

RH20310K_0402_ 5%~D

1 2

PCH_VSS_B45

1 2

+3VS

0_0402_5%~D

RH170

PCH_VSS_BD1

1 2

PLL ON DIE VR ENABLE

ENABLED - HIGH(DEFAULT) DISABLED - LOW

B B

A A

+3VS

1 2

RH272 10K_0402_5% ~D@

RH266 10K_0402_5% ~D

RH265 10K_0402_5% ~D

RH268 10K_0402_5% ~D@

Config

USB X4,PCIEX8,SATAX6

12

PCH_GPIO16

PCH_GPIO49

PCH_GPIO16

PCH_GPIO49

GPIO16,49

11

01USB X6,PCIEX8,SATAX4

For BIOS setting dGPU present

LOW - dGPU exist*

+3VS

@

1 2

RH260 10K_0402 _5%~D

1 2

RH259 10K_0402 _5%~D

DGPU_PRSNT#

+3VS

12

ODD_DETECT#

PCH_GPIO37

ODD_DETECT#

PCH_GPIO37

RH176 1K_0402_ 1%~D

1 2

RH171 200K_040 2_5%@

RH174 10K_0402 _5%~D@

RH181 10K_0402 _5%~D

SATA2GP/GPIO36 , SATA3GP/GPIO37 SAMPLED AT RISING EDGE OF PWROK. WEAK INTERNAL PULL-DOWN.(WEAK INTERNAL PULL-DOWN IS DISABLED AFTER PLRST_N DE-ASSERTS). NOTE: THIS SIGNAL SHOLD NOT BE PULLED HIGH WHEN STRAP IS SAMPLED.

Security Classification

2012/02/28 2013/02/27

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

5

4

3

2012/02/28 2013/02/27

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PCH (6/9) GPIO,MISC,NTFC

LA-9201P

1

19 6 6Tuesday, August 14 , 2012

0.1

5

D D

C C

B B

+1.05VS

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1

CH30

CH32

2

+1.05V

22U_0805_6.3V6M~D

1

CH64

2

C_0805NEW

1 2

RH37 5.11 _0402_1%~D@

1U_0402_6.3V6K~D

+PCH_VCCDSW_R

@

1

CH34

2

1U_0402_6.3V6K~D

1

2

1U_0402_6.3V6K~D

1

2

1U_0402_6.3V6K~D

1

CH33

2

1U_0402_6.3V6K~D

1

CH35

2

+PCH_VCCDSW

CH31

+PCH_VCCDSW

CH36

AA24 AA26 AD20 AD22 AD24 AD26 AD28 AE18 AE20 AE22 AE24

AE26 AG18 AG20 AG22 AG24

AA18

Y26

U14

U18 U20 U22 U24 V18 V20 V22 V24 Y18 Y20 Y22

4

UH1G

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

DCPSUSBYP VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW VCCASW

+1.5VS +1.05V_+1.5V _RUN

+1.05VS

LPT_PCH_M_EDS

CRT DAC

FDI

HVCMOS

Core

USB3

PCIe/DMI

SATA

VCCMPHY

LYNXPOINT_BGA695

RH197 0_0603_5 %~D

RH198 0_0603_5 %~D@

7 OF 11 5

12

VCCADAC1_5

VSS

VCCADACBG3_3

VCCVRM

VCCIO

VCC3_3_R30 VCC3_3_R32

DCPSUS1

VCCSUS3_3 VCCSUS3_3

DCPSUS3 DCPSUS3

VCCIO VCCVRM VCCVRM

VCCVRM

VCCIO

VCCVRM

VCCIO

P45

P43

M31

BB44

AN34

AN35

R30 R32

Y12

+PCH_USB_DCPSUS1

AJ30 AJ32

AJ26

+PCH_USB_DCPSUS3

AJ28 AK20 AK26 AK28

BE22

AK18

AN11

AK22

AM18 AM20 AM22 AP22 AR22 AT22

3

LH1

+VCCADAC

0.1U_0402_10V7K~D

0.01U_0402_16V7K~D

1

CH57

2

10U_0603_6.3V6M~D

1

CH80

2

BLM18PG181SN 1_0603~D

CH56

12

1 2

2

RH2110_0603_5%~ D

+1.5VS

1

PCH Power Rail Table

Voltage Rail

Voltage S0 Iccmax Current (A)

VCC 1.05V 1.29 A

+3VS

+1.05VS

+1.05V_+1.5V _RUN

+1.05VS

+3VS

+3V_PCH

0.1U_0402_10V7K~D

1

CH60

2

+1.05V_+1.5V _RUN

10U_0603_6.3V6M~D

@

+1.05VS

1U_0402_6.3V6K~D

1

CH86

2

1U_0402_6.3V6K~D

1

CH47

2

1U_0402_6.3V6K~D

1

CH46

CH45

2

1

CH85

2

10U_0603_6.3V6M~D

1

CH44

2

1

2

0.1U_0402_10V7K~D

1

CH38

2

+1.05V_+1.5V _RUN

10U_0603_6.3V6M~D

@

1

CH83

2

+PCH_USB_DCPSUS1

+PCH_USB_DCPSUS3

10U_0603_6.3V6M~D

@

1

CH40

2

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1

2

1

2

1

2

@

1

CH81

CH48

2

10U_0603_6.3V6M~D

@

CH82

+1.05V

12

1U_0402_6.3V6K~D

@

CH61

1U_0402_6.3V6K~D

@

CH39

1 2

RH3600_0402_5 %~D @

+1.05V

RH2090_0603_5%~D @

VCCIO 1.05V 3.629 A

VCCADAC1_5 1.5V 0.070 A

VCCADAC3_3 0.0133 A3.3V

VCCCLK 0.306 A1.05V

VCCCLK3_3 0.055 A

3.3V

VCCVRM 0.179 A1.5V

VCC3_3 3.3V 0.133 A

VCCASW 1.05V 0.67 A

VCCSUSHDA 3.3V 0.01 A

VCCSPI 3.3V 0.022 A

VCCSUS3_3 3.3V 0.261 A

VCCDSW3_3 3.3V 0.015 A

V_PROC_IO 1.05V 0.004 A

A A

Security Classification

2012/02/28 2013/02/27

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

5

4

3

2012/02/28 2013/02/27

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PCH (7/9) Power

LA-9201P

1

20 6 6Tuesday, August 14 , 2012

0.1

5

D D

+3V_PCH

0.1U_0402_10V7K~D

+1.05VS

1

CH66

2

C C

+1.05V

RH361 0_0402_5%~D@

1 2

+PCH_USB_DCPSUS2

0.1U_0402_10V7K~D

+3VS

1

CH62

2

0.1U_0402_10V7K~D

+1.05VS

CH63

1

2

1U_0402_6.3V6K~D

@

1

CH87

2

1U_0402_6.3V6K~D

1

2

+1.05V_+1.5V _RUN

CH37

10U_0603_6.3V6M~D

1

CH42

2

4

+PCH_USB_DCPSUS2

+PCH_VCCCLK

+PCH_VCCCLK3_3

+PCH_VCCCLK

+PCH_VCC

R24 R26 R28 U26

M24

U35

L24

U30 V28 V30 Y30

Y35

AF34

AP45

Y32

M29

L29

L26

M26

U32 V32

AD34

AA30 AA32

AD35

AG30 AG32

AD36

AE30 AE32

UH1H

VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3

VSS

VCCUSBPLL

VCC3_3

VCCIO VCCIO VCCIO VCCIO

DCPSUS2

VCCVRM

VCC

VCCCLK

VCCCLK3_3

VCCCLK3_3 VCCCLK3_3

VCCCLK

VCCCLK VCCCLK

VCCCLK

VCCCLK VCCCLK

VCCCLK

VCCCLK VCCCLK

LPT_PCH_M_EDS

LYNXPOINT_BGA695

USB

ICC

GPIO/LPC

Azalia

RTC

CPU

SPI

Fuse

Thermal

8 OF 11 5

3

VCCSUS3_3 VCCSUS3_3

VCCDSW3_3

VCCSUSHDA

VCCSUS3_3

V_PROC_IO V_PROC_IO

DCPSST

VCC3_3 VCC3_3 VCC3_3

VCCIO

VCCRTC

DCPRTC DCPRTC

VCCSPI

VCC VCC

VCCASW

VCCVRM

VCC3_3

+3V_PCH

R20 R22

A16

+PCH_VCCDSW3_ 3

AA14

+PCH_VCCSST

AE14 AF12 AG14

U36

A26

K8

A6

P14

+PCH_DCPRTC

P16

AJ12

+PCH_VPROC

AJ14

AD12

P18

+PCH_VCCCFUSE

P20

L17

R18

AW40

AK30

AK32

+PCH_VCCDSW3_ 3

1

2

1 2

CH84 0.1U_0402 _10V7K~D

+1.05VS

CH70

1 2

0.1U_0402_1 0V7K~D

+1.05V

+1.5VS

+3V_PCH

1

2

+3VS

1

2

1U_0402_6.3V6K~D

CH74

0.1U_0402_10V7K~D

1

CH76

2

12

1

2

1U_0402_6.3V6K~D

1

2

+3V_PCH

CH59

0.1U_0402_10V7K~D

CH72

RH2130_0402_5%~D

12

RH2530_0402_5%~D @

1

2

1

2

0.1U_0402_10V7K~D

CH55

+3V_PCH

+RTC_CELL

0.1U_0402_10V7K~D

CH69

1U_0402_6.3V6K~D

0.1U_0402_10V7K~D

1

2

CH68

CH67

2

+PCH_VPROC

0.1U_0402_10V7K~D

1

CH73

2

+3V_PCH

+3VALW

+3VS

0.1U_0402_10V7K~D

1

CH65

2

0.1U_0402_10V7K~D

CH90

+1.05VS

12

1U_0402_6.3V6K~D

CH71

RH2190_0805_5%~ D

1

+1.05VS

1 2

RH214 0_0805_5%~ D

B B

+PCH_VCCCLK

10U_0603_6.3V6M~D

1

2

1U_0402_6.3V6K~D

@

CH49

CH43

1

2

1U_0402_6.3V6K~D

CH50

1

2

1U_0402_6.3V6K~D

CH77

1

2

1U_0402_6.3V6K~D

CH78

1

2

1U_0402_6.3V6K~D

CH79

1

2

+PCH_VCCCFUSE

1U_0402_6.3V6K~D

1

CH75

2

12

RH2200_0805_5 %~D

RH2210_0805_5 %~D @

+3VS

+1.05VS

Place near pin AP45 Place near pin Y32,AA30,AA32 Place near pin AD34 Place near pin AD35,AD36 Place near pin AG30,AG32,AE30,AE32

+3VS

1 2

RH212 0_0805_5%~ D

+PCH_VCCCLK3_3

1U_0402_6.3V6K~D

CH52

1

2

1U_0402_6.3V6K~D

CH54

1

2

1U_0402_6.3V6K~D

CH53

1

2

1U_0402_6.3V6K~D

CH58

1

2

Place near pin M29 Place near pin L29 Place near pin L26,M26 Place near pin U32,V32

+1.05VS_VCC+1.05VS

LH2

1 2

4.7UH_LQM18F N4R7M00D_20%~D

1 2

RH380 0_0603_5%~D

+PCH_VCC+PCH_VCC

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

CH157

CH156

1

2

Place near pin AP45

A A

Security Classification

2012/02/28 2013/02/27

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

5

4

3

2012/02/28 2013/02/27

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PCH (8/9) Power

LA-9201P

1

21 6 6Tuesday, August 14 , 2012

0.1

5

D D

4

3

2

1

LPT_PCH_M_EDS

UH1J

AL34

VSS

AL38

VSS

AL8

VSS

AM14

VSS

AM24

VSS

AM26

VSS

AM28

VSS

AM30

VSS

AM32

VSS

AM16

VSS

AN36

VSS

AN40

VSS

AN42

VSS

AN8

VSS

AP13

C C

B B

VSS

AP24

VSS

AP31

VSS

AP43

VSS

AR2

VSS

AK16

VSS

AT10

VSS

AT15

VSS

AT17

VSS

AT20

VSS

AT26

VSS

AT29

VSS

AT36

VSS

AT38

VSS

D42

VSS

AV13

VSS

AV22

VSS

AV24

VSS

AV31

VSS

AV33

VSS

BB25

VSS

AV40

VSS

AV6

VSS

AW2

VSS

F43

VSS

AY10

VSS

AY15

VSS

AY20

VSS

AY26

VSS

AY29

VSS

AY7

VSS

B11

VSS

B15

VSS

LYNXPOINT_BGA695

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

K39 L2 L44 M17 M22 N12 N35 N39 N6 P22 P24 P26 P28 P30 P32 R12 R14 R16 R2 R34 R38 R44 R8 T43 U10 U16 U28 U34 U38 U42 U6 V14 V16 V26 V43 W2 W44 Y14 Y16 Y24 Y28 Y34 Y36 Y40 Y8

510 OF 11

AA16 AA20 AA22 AA28

AA4 AB12 AB34 AB38

AB8

AC2 AC44 AD14 AD16 AD18 AD30 AD32 AD40

AD6

AD8 AE16 AE28

AF38

AF8

AG16

AG2 AG26 AG28 AG44

AJ16 AJ18 AJ20 AJ22 AJ24 AJ34 AJ38

AJ6

AJ8 AK14 AK24 AK43 AK45

AL12

AL2 BC22 BB42

LPT_PCH_M_EDS

UH1K

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

LYNXPOINT_BGA695

B19

VSS

B23

VSS

B27

VSS

B31

VSS

B35

VSS

B39

VSS

B7

VSS

BA40

VSS

BD11

VSS

BD15

VSS

BD19

VSS

AY36

VSS

AT43

VSS

BD31

VSS

BD35

VSS

BD39

VSS

BD7

VSS

D25

VSS

AV7

VSS

F15

VSS

F20

VSS

F29

VSS

F33

VSS

BC16

VSS

D4

VSS

G2

VSS

G38

VSS

G44

VSS

G8

VSS

H10

VSS

H13

VSS

H17

VSS

H22

VSS

H24

VSS

H26

VSS

H31

VSS

H36

VSS

H40

VSS

H7

VSS

K10

VSS

K15

VSS

K20

VSS

K29

VSS

K33

VSS

BC28

VSS

511 OF 11

A A

Security Classification

2012/02/28 2013/02/27

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2012/02/28 2013/02/27

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PCH (9/9) Power

LA-9201P

1

0.1

22 66Tuesday, August 14, 2012

5

+3VS

CV487

0.1U_0402_1 6V4Z~D

SN74AHC1G08DCKR_ SC70-5

VGA_DPC_HPD46

D D

+3VS

VGA_DPC_HPD

UV37

4

RV655 0_0402_5%~ D

1 2

5

1

P

IN1

O

IN2

G

3

@

DGPU_PWROK 32,49

2

DP_PCH_HPD

12

4

3

2

1

12

RV984.7 K_0402_5%~D @

12

RV994.7 K_0402_5%~D @

12

RV1004.7K_0 402_5%~D @

12

RV10210K_040 2_1%~D

12

RV6564.7K_0 402_5%~D @

12

RV6644.7K_0 402_5%~D @

12

RV6844.7K_0 402_5%~D

12

RV6854.7K_0 402_5%~D @

12

RV6654.7K_0 402_5%~D @

12

RV6574.7K_0 402_5%~D

12

RV1044.7K_0 402_5%~D @

12

RV1054.7K_0 402_5%~D @

12

RV1064.7K_0 402_5%~D @

C C

B B

DP_PEQ DP_CFG1_INPUT

DP_CFG0 DP_RST# OC_1 OC_0

DP_POWER_DOW N#

OC_0 OC_1 DP_PEQ DP_CFG1_INPUT DP_CFG0

GPU

DP Redriver

+3VS

1

2

CV499

25

1

6

UV6

12

VGA_DPC_P047 VGA_DPC_N047 VGA_DPC_P147 VGA_DPC_N147 VGA_DPC_P247 VGA_DPC_N247 VGA_DPC_P347 VGA_DPC_N347

VGA_DPC_AUXP/DDC47 VGA_DPC_AUXN/DDC47

CV390.1U_04 02_10V6K~D

12

CV400.1U_04 02_10V6K~D

12

CV420.1U_04 02_10V6K~D

12

CV430.1U_04 02_10V6K~D

12

CV440.1U_04 02_10V6K~D

12

CV450.1U_04 02_10V6K~D

12

CV460.1U_04 02_10V6K~D

12

CV470.1U_04 02_10V6K~D

DP_PCH_HPD14

1 2

12

CV4960.1U_0 402_10V7K~D

12

CV4970.1U_0 402_10V7K~D

VGA_DPC_P0_C VGA_DPC_N0_C VGA_DPC_P1_C VGA_DPC_N1_C VGA_DPC_P2_C VGA_DPC_N2_C VGA_DPC_P3_C VGA_DPC_N3_C

OC_1

DP_PEQ DP_CFG0

DP_POWER_DOW N#

RV1034.99K_0 402_1%

MDP_CAB_DET

DP_PCH_HPD

VGA_DPC_AUXP/DDC_RC VGA_DPC_AUXN/DDC_RC

38

IN0p

39

IN0n

41

IN1p

42

IN1n

44

IN2p

45

IN2n

47

IN3p

48

IN3n

3

I2C_ADDR

4

SCL_CTL/PEQ

5

SDA_CTL/CFG0

26

PD#

7

REXT

8

CAD_SRC

9

HPD_SRC

33

SCL_DDC

34

SDA_DDC

30

AUX_SRCP

29

AUX_SRCN

12

VCC4

VCC1

VCC2

VCC3

CV498

36

VCC532VCC6

OUT0p OUT0n OUT1p OUT1n OUT2p OUT2n OUT3p OUT3n

CFG1

RST#

CAD_SNK

HPD_SINK

AUX_SNKP

AUX_SNKN

CEXT

NC2 NC3 NC4 NC5

EPAD

GND3

GND118GND2

49

31

24

PS8330BQFN48GTR2- A0_QFN48_7X7

NC

0.1U_0402_10V7K~D

23 22 20 19 17 16 14 13

40

46

35

10

11

28 27

2 15 21 37 43

0.1U_0402_10V7K~D

MDP_P0_C MDP_N0_C MDP_P1_C MDP_N1_C MDP_P2_C MDP_N2_C MDP_P3_C MDP_N3_C

DP_CFG1_INPUT

OC_0

DP_RST#

DP_CBL_DET

DISP_HPD_SINK

1

2

CV500

CV501

0.1U_0402_10V7K~D

CV14 0.1U_0402_10 V6K~D CV16 0.1U_0402_10 V6K~D CV18 0.1U_0402_10 V6K~D CV20 0.1U_0402_10 V6K~D CV22 0.1U_0402_10 V6K~D CV24 0.1U_0402_10 V6K~D CV26 0.1U_0402_10 V6K~D CV28 0.1U_0402_10 V6K~D

CV29 2.2U_0402 _6.3V6M~D

VGA_DPC_AUXP/DDC_C VGA_DPC_AUXN/DDC_C

12 12 12 12 12 12 12 12

12

1 2

CV302.2U_04 02_6.3V6M~D

VGA_DPC_AUXN/DDC_C VGA_DPC_AUXP/DDC_C

MDP_P0 MDP_N0 MDP_P1 MDP_N1 MDP_P2 MDP_N2 MDP_P3 MDP_N3

DP_CBL_DET15

+3VS

1 2

12

RV112 100K_ 0402_5%~D RV113 100K_ 0402_5%~D

+3VS

1 2

RV666 0_0402_5 %~D

VGA_DPC_AUXP/DDC_C

VGA_DPC_AUXN/DDC_C

Co-lay

FV4

1 2

1.5A_6V_120 6L150PR~D

RV114 0_1206_ 5%~D@

DISP_HPD_SINK MDP_P0

CAB_DET_SINK

MDP_N0 DISP_CEC

MDP_P1 MDP_P3 MDP_N1 MDP_N3

MDP_P2

MDP_N2

+3VS_DP

12

Need apply CIS part

+3VS_DP

22U_0805_6.3V6M~D

CV36

.1U_0402_16V7K~D

CV35

10U_0603_6.3V6M~D

1

2

CV37

1

2

Mini DP CONN

JMDP1

1

GND

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

21 22 23 24

LOTES_ADIS0015-P0 02A

LANE0_P

LANE0_N

GND

LANE1_P

LANE1_N

GND

LANE2_P

LANE2_N

RETURN

GND

HPD

CONFIG1

CONFIG2

GND

LANE3_P

LANE3_N

GND

AUX_CHP

AUX_CHN

DP_PWR

0.1U_0402_25V6K~D

CV38

1

2

OK

+5VS

0.1U_0402_16V4Z~D

+3VS

100K_0402_5%~D

12

RV670

13

D

MDP_CAB_DET

A A

5

2

G

S

VGA_DPC_AUXN/DDC VGA_DPC_AUXP/DDC

MDP_CAB_DET#

QV9 BSS138_SOT23~D

UV38

2

1A

VCC

2A51B

1

1OE#

2B

7

GND

2OE#

CBTD3306PW_TSSOP 8

1

2

8 3 6 4

4

+3VS

4.7K_0402_5%~D

RV668

CV518

RV669

1 2

Security Classification

2012/05/14 2013/05/13

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

3

2012/05/14 2013/05/13

Compal Secret Data

Deciphered Date

2

RV121

1 2

@

RV124

1 2

RV125

1 2

DISP_HPD_SINK

1M_0402_5 %~D

DP_CBL_DET

1M_0402_5 %~D

DISP_CEC

5.1M_0402_ 5%

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Mini DP/Thunder Bolt power

LA-9201P

1

23 6 6Tuesday, August 14 , 2012

0.1

5

+3VS +3 VS

1

CV484

UV34

6

1B1

5

1B2

4

1B3

3

1B4

10

2B1

DGPU_ENVDD46

HDMI_IN_ENVDD28

PCH_ENVDD15,32

D D

11

2B2

12

2B3

13

2B4

1

1OE

SN74CB3Q3253PW R_TSSOP16

VCC

2OE

GND

16

14

S0

2

S1

7

1A

9

2A

15

8

0.1U_0402_1 6V4Z~D

2

DGPU_SELECT#

LCDVDD_ON

0

12

RV601

@

10K_0402_5 %~D

HDMI_IN_SELECT#

DGPU_SELECT# 1 5,24,27

LCDVDD_ON 2 5

S0S1 Y

1A 2A

0

1B1 2B1

1 DSC

1B2 2B2

0111

1B3 2B3

1B4 2B4

C C

GPU

GPU_DPB_AUXP/DDC47 GPU_DPB_AUXN/DDC47

CPU

B B

MXM_TX0P47 MXM_TX0N47 MXM_TX1P47 MXM_TX1N47 MXM_TX2P47 MXM_TX2N47 MXM_TX3P47 MXM_TX3N47

CPU_EDP_TX0P8 CPU_EDP_TX0N8 CPU_EDP_TX1P8 CPU_EDP_TX1N8 CPU_EDP_TX2P8 CPU_EDP_TX2N8 CPU_EDP_TX3P8 CPU_EDP_TX3N8

CPU_EDP_AUX8 CPU_EDP_AUX#8

GPU_DPB_HPD46 CPU_EDP_HPD#8

4

HDMI_IN_SELECT# 25 ,32

HDMI IN

UMA

+3VS

1

2

12 12 12 12 12 12 12 12

12

CV730.1U_ 0402_10V6K~D

12

CV740.1U_ 0402_10V6K~D

12 12 12 12 12 12 12 12

12 12

0.1U_0402_16V4Z~D

CV62

CV61

1

2

DP_IN3_PEQ# DP_IN4_PEQ# DP_IN3_AEQ# DP_IN4_AEQ#

GPU_C_TX0P

CV650.1U_0402_10V6K~D

GPU_C_TX0N

CV660.1U_0402_10V6K~D

GPU_C_TX1P

CV670.1U_0402_10V6K~D

GPU_C_TX1N

CV680.1U_0402_10V6K~D

GPU_C_TX2P

CV690.1U_0402_10V6K~D

GPU_C_TX2N

CV700.1U_0402_10V6K~D

GPU_C_TX3P

CV710.1U_0402_10V6K~D

GPU_C_TX3N

CV720.1U_0402_10V6K~D

GPU_DPB_AUXP/DDC_C GPU_DPB_AUXN/DDC_C

CPU_EDP_TX0P_C

CV750.1U_0402_10V6K~D

CPU_EDP_TX0N_C

CV760.1U_0402_10V6K~D

CPU_EDP_TX1P_C

CV770.1U_0402_10V6K~D

CPU_EDP_TX1N_C

CV780.1U_0402_10V6K~D

CPU_EDP_TX2P_C

CV1010.1U_0402_10 V6K~D

CPU_EDP_TX2N_C

CV1020.1U_0402_10 V6K~D

CPU_EDP_TX3P_C

CV1030.1U_0402_10 V6K~D

CPU_EDP_TX3N_C

CV1040.1U_0402_10 V6K~D

CPU_EDP_AUX_C

CV790.1U_04 02_10V6K~D

CPU_EDP_AUX#_C

CV800.1U_04 02_10V6K~D

3

LCD Backlight Selector

1 2

EC_INV_PWM32

DGPU_BL_PWM4 6 HDMI_IN_PWM28 PCH_INV_PWM15

EC_INV_PWM

DGPU_BKL_EN46

HDMI_IN_BKL_EN28

IGPU_BKLT_EN15

SG_AMD_BKL15,32

RV602 0_0402_ 5%~D@

0_0402_5%~ D

1 2

RV600

1 2

RV654 0_0402_ 5%~D@

1 2

RV606 0_0402_ 5%~D

VGA_EC_PWM HDMI_IN_PWM PCH_INV_PWM

SN74CB3Q3253PW R_TSSOP16

CPU & GPU SW for EDP

UV9

54

VDD

31

VDD

49

IN2_PEQ/SDA_CTL

50

IN1_PEQ/SCL_CTL

3

IN1_AEQ#

51

IN2_AEQ#

52

IN1_D0p

53

IN1_D0n

55

IN1_D1p

56

IN1_D1n

1

IN1_D2p

2

IN1_D2n

4

IN1_D3p

5

IN1_D3n

24

IN1_AUXp

23

IN1_AUXn

20

IN1_SCL

19

IN1_SDA

7

IN2_D0p

8

IN2_D0n

10

IN2_D1p

11

IN2_D1n

13

IN2_D2p

14

IN2_D2n

15

IN2_D3p

16

IN2_D3n

26

IN2_AUXp

25

IN2_AUXn

22

IN2_SCL

21

IN2_SDA

6

IN1_HPD

9

IN2_HPD

PS8321QFN56GTR-A0 _QFN56_7X7

MXM_MFG_SEL

0

1

OUT_AUXp_SCL

OUT_AUXn_SDA

I2C_CTL_EN

CFG_OUTPUT

OUT2_D2p OUT2_D2n

SW_ML/I2C_ADDR

GPU Source

GPU

CPU

SW_AUX

AC_AUXp AC_AUXn

CA_DET

OUT_D0p OUT_D0n OUT_D1p OUT_D1n

OUT_D3p OUT_D3n

CFG_HPD OUT_HPD

REXT CEXT

GND GND

Epad

47

28 27

30 29

37

34

44

42 41 39 38 36 35 33 32

48

46 43

18 17

45 12 57 40

PD

CPU_GPU_EDP_AUXP CPU_GPU_EDP_AUXN

CPU_GPU_EDP_AUXP_L CPU_GPU_EDP_AUXN_L

CFG_OUTPUT_1

RV667 1M_0 402_5%~D

CPU_GPU_EDP_A0P

CPU_GPU_EDP_A0N

CPU_GPU_EDP_A1P CPU_GPU_EDP_A1N CPU_GPU_EDP_A2P CPU_GPU_EDP_A2N CPU_GPU_EDP_A3P CPU_GPU_EDP_A3N

DGPU_SELECT#

CFG_HPD_1 LV_DP_HPD

UV35

6

1B1

5

1B2

4

1B3

3

1B4

10

2B1

11

2B2

12

2B3

13

2B4

1

1OE

1 2

2.2U_0402_6.3V6M~D

1

2

0.1U_0402_16V4Z~D

+3VS

1

CV485

2

16

VCC

14

HDMI_IN_PWM _SELECT#

S0

2

S1

7

INV_PWM

1A

9

ENBKL

2A

15

2OE

8

GND

DGPU_EDIDSEL# 19,27

CV63 0.1U_0 402_10V6K~D CV64 0.1U_0 402_10V6K~D

CV81

12 12

CPU_GPU_EDP_A0P 25 CPU_GPU_EDP_A0N 25 CPU_GPU_EDP_A1P 25 CPU_GPU_EDP_A1N 25 CPU_GPU_EDP_A2P 25 CPU_GPU_EDP_A2N 25 CPU_GPU_EDP_A3P 25 CPU_GPU_EDP_A3N 25

DGPU_SELECT# 15, 24,27

LV_DP_HPD 2 5

4.99K_0402_1%

12

RV134

2

+3VS

12

RV603

@

10K_0402_5 %~D

DGPU_BKL_PWM _SEL# 19

INV_PWM 25

100K_0402_5%~D

12

RV607

RV608

ENBKL 32

HDMI_IN_PWM SEL#15

S1 S0 Y1A 2A

1

0

1 1

+3VS

INy_AEQ# (y=1, 2),Automatic RX equalization enable L:Enable input automatic equalization H:Disable input automatic equalization

CPU_GPU_EDP_AUXP 25 CPU_GPU_EDP_AUXN 25

CFG_OUTPUT: output configuration L:Output is tracking DPCD register setting (auto interception) H:Output swing level fixed at 600mV and no pre-emphasis M:Output swing level is fixed at 400mV and no pre-emphasis

DGPU_SELECT#

1B1 2B1

1B2 2B2

1B3 2B3

1B4 2B4

RV128 4.7K_ 0402_1%~D

RV129 4.7K_ 0402_1%~D

RV130

4.7K_0402_1 %~D

1 2

DP_IN3_PEQ#

12

RV132

4.7K_0402_1 %~D

INy_PEQ(y = 1, 2),Programmable input equalization level setting L:Low EQ setting (LEQ), default H:High EQ setting (HEQ) M:No EQ

RV135

4.7K_0402_1 %~D

1 2

CFG_OUTPUT_1

12

RV139

4.7K_0402_1 %~D

@

HDMI IN (D)

DSC1000

HDMI IN (I)

UMA

12

@

1 2

RV604 0_04 02_5%~D@

1 2

RV605 0_04 02_5%~D

DP_IN3_AEQ#

DP_IN4_AEQ#

+3VS+3VS

RV131

@

4.7K_0402_1 %~D

1 2

DP_IN4_PEQ#

12

RV133

@

4.7K_0402_1 %~D

+3VS+3 VS

RV136

4.7K_0402_1 %~D

@

1 2

CFG_HPD_1

12

RV140

4.7K_0402_1 %~D

1

HDMI_IN_PWM _SELECT#

CFG_HPD,HPD switching configuration L:HPD is switched by SW_ML H:HPD is switched by SW_AUX M:HPD is switched with overlap

A A

Security Classification

2012/05/14 2013/05/13

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

5

4

3

2012/05/14 2013/05/13

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

eDP SW-CPU & MXM

LA-9201P

1

24 6 6Tuesday, August 14 , 2012

0.1

5

eDP POWER

+EDPVDD

D D

1

2

10U_0805_10V4Z~D

0.1U_0402_16V4Z~D

1

CV82

2

Close to JEDP1

LCDVDD_ON24

EC_ENVDD32

Back light power

C C

Inverter power

1 2

LV1

@

FBMA-L11-201 209-221LMA30T_0805

80 mil

CV83

0.1U_0402_16V4Z~D

1

CV84

2

0_0402_5%~ D

+INVPWR_B+B+

0.1U_0402_16V4Z~D

1

CV85

2

1 2

100_0402_5%~D

12

RV149

61

QV4A 2N7002DW-T/R7 _SOT363-6

2

RV154

RV156

@

B+

80 mil

1000P_0402_50V7K~D

1

CV94

2

LCD_BKL_EN32

200K_0402_5%

12

RV152

5

12

RV157 100K_0402_ 5%~D

PWR_SRC_ON

1 2

RV158 47K_040 2_5%~D

Panel backlight power control by EC

OK

JEDP1

55

GND11

54

GND10

53

GND9

52

GND8

51

GND7

50

GND6

49

GND5

48

GND4

47

GND3

B B

A A

46

GND2

45

GND1

JAE_FI-TD44SB-E-R7 50~D

CONN@

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

EDP_A0P_CONN EDP_A0N_CONN

EDP_A1P_CONN EDP_A1N_CONN

EDP_A2P_CONN EDP_A2N_CONN

EDP_A3P_CONN EDP_A3N_CONN

EDP_AUX-_CONN EDP_AUX+_CONN

EDP_HPD LCD_TEST

USB20_N11_CONN

DMIC_CLK_CONN DMIC0_CONN

EDP_CAB_DET#

CAM_DET# DISPOFF#

1 2

CV116

0.1U_0603_5 0V4Z~D

+3VS

LCD_TEST 32

EDP_CAB_DET# 19

CAM_DET# 16 BKOFF# 32

+3VS_CAM

+EDPVDD

+INVPWR_B+

+EDPVDD+I NVPWR_B++EDPVDD +3VS

47K_0402_5%~D

12

RV150

RV151

220K_0402_ 1%

3

QV4B 2N7002DW-T/R7 _SOT363-6

4

QV11

FDC654P-G_SSOT-6~D

D

S

4 5

G

3

1 3

D

FDC654P: P CHANNAL

1 2

RV159 100K_04 02_5%~D

1 2

RV160 100K_04 02_5%~D@

1 2

RV162 100K_04 02_5%~D

PV163 1M_ 0402_1%

Reserve

+3VS

0.1U_0402_1 6V4Z~D

4

W=60mils

QV10

FDS4435BZ_SO8 ~D

8 7

4.7U_0805_10V4Z~D

6 5

1

CV86

2

12

6

2 1

QV12 SSM3K7002FU_ SC70-3~D

G

2

12

EDP_CAB_DET#_R

USB20_P11_CONN

USB20_N11_CONN

+3VS

4

2

1

80 mil

1

CV93

0.1U_0603_5 0V4Z~D

2

S

EDP_AUX-

EDP_HPD

EDP_AUX+

12

RV166

@

10K_0402_5 %~D

LV6

1 2

BLM18BB221S N1D_2P~D

+EDPVDD

1

CV114

2

1 2 3

0.1U_0603_25V7K~D

CV88

+INVPWR_B+

DV3

1

V I/O

Ground2V BUS

3

V I/O

IP4223CZ6_SO6 ~D

+3VS_CAM

1

CV115

0.1U_0402_1 6V4Z~D

2

+3VS

12

RV141

4.7K_0402_1 %~D

4.7U_0805_10V4Z~D

1

CV87

2

12

RV145

4.7K_0402_1 %~D

CFG_HPD,HPD switching configuration L:HPD is switched by SW_ML H:HPD is switched by SW_AUX M:HPD is switched with overlap

+3VS

INy_AEQ# (y=1, 2),Automatic RX equalization enable L:Disable input automatic equalization H:Enable input automatic equalization

DP to LVDS 4028

CPU/GPU

12

CV107 0.1U_0402_1 6V4Z~D

CV108 0.1U_0402_1 6V4Z~D

EDP_HPD

12

DISPOFF#

Close to JEDP1

6

V I/O

1

2

DMIC0_CONN

5

4

DMIC_CLK_CONN

INV_PWM 24

CV113

@

120P_0402_ 50VNPO~D

USB20_P111 8

USB20_N1118

20111216 add for EMI

CFG_HPD_2

@

RV153 4.7K_ 0402_1%~D

RV155 4.7K_ 0402_1%~D

CPU_GPU_EDP_AUXP2 4 CPU_GPU_EDP_AUXN24

12

4028_EDP_L0 P29 4028_EDP_L0 N29 4028_EDP_L1 P29 4028_EDP_L1 N29 4028_EDP_L2 P29 4028_EDP_L2 N29 4028_EDP_L3 P29 4028_EDP_L3 N29

4028_EDP_AUXP29 4028_EDP_AUXN29

CPU_GPU_EDP_A0P24 CPU_GPU_EDP_A0N24 CPU_GPU_EDP_A1P24 CPU_GPU_EDP_A1N24 CPU_GPU_EDP_A2P24 CPU_GPU_EDP_A2N24 CPU_GPU_EDP_A3P24 CPU_GPU_EDP_A3N24

DP_4028_HPD29 LV_DP_HPD24

20111216 add for EMI

+5VS

DMIC034

DMIC_CLK34

RV171 0_040 2_5%~D

LV9

USB20_P11

USB20_N11

1 2

DLW21SN670 HQ2L_4P~D

RV175 0_0402_ 5%~D

3

DP_IN5_AEQ#

DP_IN6_AEQ#

AUX_SEL/SEL1&2

1 2

BLM18BB221S N1D_2P~D

1 2

BLM18BB221S N1D_2P~D

@

1 2

@

+3VS

RV142

4.7K_0402_1 %~D

1 2

DP_IN5_PEQ#

12

RV146

4.7K_0402_1 %~D

INy_PEQ(y = 1, 2),Programmable input equalization level setting L:Low EQ setting (LEQ), default H:High EQ setting (HEQ) M:No EQ

1 2 1 2

CV502 0.1U_0402_ 10V7K~D

1 2

CV503 0.1U_0402_ 10V7K~D

1 2

CV504 0.1U_0402_ 10V7K~D

1 2

CV505 0.1U_0402_ 10V7K~D

1 2

CV506 0.1U_0402_ 10V7K~D

1 2

CV507 0.1U_0402_ 10V7K~D

1 2

CV508 0.1U_0402_ 10V7K~D

CV509 0.1U_0402_ 10V7K~D

1 2 1 2

RV686 0_0402_5%~ D RV687 0_0402_5%~ D

1 2 1 2

CV510 0.1U_0402_ 10V7K~D

1 2

CV511 0.1U_0402_ 10V7K~D

1 2

CV512 0.1U_0402_ 10V7K~D

1 2

CV513 0.1U_0402_ 10V7K~D

1 2

CV514 0.1U_0402_ 10V7K~D

1 2

CV515 0.1U_0402_ 10V7K~D

1 2

CV516 0.1U_0402_ 10V7K~D

CV517 0.1U_0402_ 10V7K~D

1 2 1 2

RV688 0_0402_5%~ D RV689 0_0402_5%~ D

+3VS +3VS

@

0.1U_0402_16V4Z~D

1

2

DP_IN5_PEQ# DP_IN6_PEQ# DP_IN5_AEQ# DP_IN6_AEQ#

RV143

@

4.7K_0402_1 %~D

1 2

DP_IN6_PEQ#

12

RV147

@

4.7K_0402_1 %~D

+3VS

0.1U_0402_16V4Z~D

CV90

CV89

1

2

4028_EDP_L0 P_C 4028_EDP_L0 N_C 4028_EDP_L1 P_C 4028_EDP_L1 N_C 4028_EDP_L2 P_C 4028_EDP_L2 N_C 4028_EDP_L3 P_C 4028_EDP_L3 N_C

4028_EDP_AUXP_C 4028_EDP_AUXN_C

CPU_GPU_EDP_A0P_ C CPU_GPU_EDP_A0N_ C CPU_GPU_EDP_A1P_ C CPU_GPU_EDP_A1N_ C CPU_GPU_EDP_A2P_ C CPU_GPU_EDP_A2N_ C CPU_GPU_EDP_A3P_ C CPU_GPU_EDP_A3N_ C

CPU_GPU_EDP_AUXP_R CPU_GPU_EDP_AUXN_R

54 31

49 50

51

52 53 55 56

24 23 20 19

10 11 13 14 15 16

26 25 22 21

SourceChanel

0

4028

BACPU/GPU1

LV4

LV5

34

USB20_P11_CONN

USB20_N11_CONN

DMIC0_CONN

12

CV111

@

10P_0402_5 0V8J~D

DMIC_CLK_CONN

12

CV112

@

10P_0402_5 0V8J~D

EDP_A0NUSB20_P11_CONN

EDP_A1N

20111216 add for EMI

2

RV144

@

4.7K_0402_1 %~D

1 2

CFG_OUTPUT_2

12

RV148

4.7K_0402_1 %~D

CFG_OUTPUT: output configuration L:Output is tracking DPCD register setting (auto interception) H:Output swing level fixed at 600mV and no pre-emphasis M:Output swing level is fixed at 400mV and no pre-emphasis

EN_CAM32

CPU/GPU & 4028 SW for DPB

UV10

VDD VDD

IN2_PEQ/SDA_CTL IN1_PEQ/SCL_CTL

3

IN1_AEQ# IN2_AEQ#

IN1_D0p IN1_D0n IN1_D1p IN1_D1n

1

IN1_D2p

2

IN1_D2n

4

IN1_D3p

5

IN1_D3n

IN1_AUXp IN1_AUXn IN1_SCL IN1_SDA

7

IN2_D0p

8

IN2_D0n IN2_D1p IN2_D1n IN2_D2p IN2_D2n IN2_D3p IN2_D3n

IN2_AUXp IN2_AUXn IN2_SCL IN2_SDA

6

IN1_HPD

9

IN2_HPD

PS8321QFN56GTR-A0 _QFN56_7X7

RV165 0_040 2_5%~D@

1 2

RV168 0_04 02_5%~D@

RV170 0_040 2_5%~D@

1 2

RV173 0_04 02_5%~D@

RV169 0_0402_ 5%~D@

EDP_AUX+

1 2

RV172

OUT_AUXp_SCL OUT_AUXn_SDA

I2C_CTL_EN

CFG_OUTPUT

OUT2_D2p OUT2_D2n

SW_ML/I2C_ADDR

1 2

LV3

DLW21SN670 HQ2L_4P~D

1 2

LV8

DLW21SN670 HQ2L_4P~D

1 2

LV7

DLW21SN670 HQ2L_4P~D

1 2

SW_AUX

AC_AUXp AC_AUXn

CA_DET

OUT_D0p OUT_D0n OUT_D1p OUT_D1n

OUT_D3p OUT_D3n

CFG_HPD OUT_HPD

REXT CEXT

GND GND

Epad

34

PD

34

0_0402_5%~ D@

47

28 27

30

EDP_AUX+_C

29

EDP_AUX-_C

37

34

CFG_OUTPUT_2

44

EDP_CAB_DET#_R

42

EDP_A0P_L

41

EDP_A0N_L

39

EDP_A1P_L

38

EDP_A1N_L

36

EDP_A2P_L

35

EDP_A2N_L

33

EDP_A3P_L

32

EDP_A3N_L

48

HDMI_IN_SELECT#

46

CFG_HPD_2

43

EDP_HPD

18 17

45 12 57 40

EDP_A0N_CONN

EDP_A0P_CONNEDP_A0P

EDP_A1N_CONN

EDP_A1P_CONNEDP_A1P

EDP_AUX+_CONN

EDP_AUX-_CONNEDP_AUX-

HDMI_IN_SELECT# 24 ,32

1 2

CV91 0.1U_04 02_10V7K~D

1 2

CV92 0.1U_04 02_10V7K~D

2.2U_0402_6.3V6M~D

1

CV110

2

EDP_A2P

EDP_A3P

0.1U_0402_16V4Z~D 100K_0402_5%~D

12

CV519

2

1

4.99K_0402_1%

12

RV161

RV673

SSM3K7002F_SC59-3~D

1

D

2

G

S

3

1 2

CV950.1U_0402_10 V7K~D

1 2

CV960.1 U_0402_10V7K~D

1 2

CV980.1 U_0402_10V7K~D

1 2

CV1000.1U_0 402_10V7K~D

1 2

CV4800.1U_0 402_10V7K~D

1 2

CV4810.1U_0 402_10V7K~D

1 2

CV4820.1U_0 402_10V7K~D

1 2

CV4830.1U_0 402_10V7K~D

20111216 add for EMI

1 2

RV578 0_0402_ 5%~D@

LV10

1 2

DLW21SN670 HQ2L_4P~D

RV577 0_04 02_5%~D@

RV579 0_0402_ 5%~D@

1 2

RV167 0_04 02_5%~D@

1

SI2301CDS-T1-GE3_ SOT23-3~D

QV57

QV56

S

G

2

EN_CAM control circuit

EDP_AUX+ EDP_AUX-

EDP_A0P EDP_A0N EDP_A1P EDP_A1N EDP_A2P EDP_A2N EDP_A3P EDP_A3N

34

1 2

LV2

34

DLW21SN670 HQ2L_4P~D

1 2

+3VS_CAM+3VS

D

13

0.1U_0402_16V4Z~D

CV520

2

1

EDP_A2P_CONN

EDP_A2N_CONNEDP_A2N

EDP_A3P_CONN

EDP_A3N_CONNEDP_A3N

10U_0805_10V4Z~D

CV521

1

2

Security Classification

2012/05/14 2013/05/13

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

5

4

3

2012/05/14 2013/05/13

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

eDP SW-eDP CONN

LA-9201P

1

25 6 6Tuesday, August 14 , 2012

0.1

A

1 1

+3VS

0.1U_0402_16V4Z~D

CV119

1

2

HDMI_IN_OUT_TXC-_R HDMI_IN_OUT_TXC+_R HDMI_IN_OUT_TXD0-_R HDMI_IN_OUT_TXD0+_R HDMI_IN_OUT_TXD1-_R

HDMI CONN

2 2

HDMI_SW32

HDMI_IN_OUT_TXD1+_R HDMI_IN_OUT_TXD2-_R HDMI_IN_OUT_TXD2+_R

+3VS

RV680 1K_0402_1 %~D

RV681 1K_0402_1 %~D

0.1U_0402_16V4Z~D

10U_1206_16V4Z

CV121

CV120

1

2

12

+1.5VS

UV11

42

VDD

40 30 20 18 16

8 2

15 14 12 11

7 6 4 3

9

43

BTMDSCLK-

VDD

BTMDSCLK+ VDD VDD VDD VDD VDD VDD

TMDSCLKTMDSCLK+ TMDS0TMDS0+ TMDS1TMDS1+ TMDS2TMDS2+

SEL

GND_PAD

TS3DV421RUAR_W QFN42_9X3P5

BMTDS0-

BTMDS0+

BTMDS1-

BMTDS1+

BTMDS2-

BTMDS2+

ATMDSCLK-

ATMDSCLK+

ATMDS0-

ATMDS0+

ATMDS1-

ATMDS1+

ATMDS2-

ATMDS2+

VSS VSS VSS VSS VSS VSS VSS VSS VSS

22

HDMI_IN_CK-

23

HDMI_IN_CK+

24

HDMI_IN_D0-

25

HDMI_IN_D0+

26

HDMI_IN_D1-

27

HDMI_IN_D1+

28

HDMI_IN_D2-

29

HDMI_IN_D2+

31

HDMI_OUT_TXC-

32

HDMI_OUT_TXC+

33

HDMI_OUT_TXD0-

34

HDMI_OUT_TXD0+

35

HDMI_OUT_TXD1-

36

HDMI_OUT_TXD1+

37

HDMI_OUT_TXD2-

38

HDMI_OUT_TXD2+

+1.5VS 39 41 21 19 17 13 10 5 1

SEL OUTPUT

UV12

1A 2A 3A 4A

OE# S

GND

1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2

A

B

+5VS

16

Vcc

2

DVI_SDATA

3

HDMI_DAT

5

DVI_SCLK

6

HDMI_CLK

11

HDMI_SINK_HPD_R

10

HDMI_IN_HPD_R

14 13

HDMI_IN_DET#

L

H

HDMI_IN_OUT_SDATA HDMI_IN_OUT_SCLK HDMI_IN_OUT_HPD HDMI_IN_OUT_DDC

HDMI_SW

2011/11/30 need confirm with PCH

3 3

4 7 9

12

15

1

8

SN74CBT3257CPW R_TSSOP16~D

SEL OUTPUT

L

H

B1

B2

B

HDMI_IN_CK- 28 HDMI_IN_CK+ 28 HDMI_IN_D0- 28 HDMI_IN_D0+ 28 HDMI_IN_D1- 28 HDMI_IN_D1+ 28 HDMI_IN_D2- 28 HDMI_IN_D2+ 28

HDMI_OUT_TXC- 27 HDMI_OUT_TXC+ 27 HDMI_OUT_TXD0- 27 HDMI_OUT_TXD0+ 27 HDMI_OUT_TXD1- 27 HDMI_OUT_TXD1+ 27 HDMI_OUT_TXD2- 27 HDMI_OUT_TXD2+ 27

10U_1206_16V4Z

0.1U_0402_16V4Z~D

CV124

CV123

1

2

DVI_SDATA 27 HDMI_DAT 28

DVI_SCLK 2 7 HDMI_CLK 2 8

HDMI_SINK_HPD_R 27 HDMI_IN_HPD_R 28

HDMI_IN_DET# 28

C

STDP6038

HDMI_OUT_EN32

CPU/GPU

PCH_PWR_EN3 2,45

1 2

0.1U_0402_16V4Z~D

CV125

1

2

+5VS

0.1U_0402_16V4Z~D

CV127

CV126

1

2

HDMI_IN_OUT_TXD2+_R

HDMI_IN_OUT_TXD2-_R

HDMI_IN_OUT_TXD1-_R

HDMI_IN_OUT_TXD1+_R

HDMI_IN_OUT_TXD0+_R

HDMI_IN_OUT_TXD0-_R

HDMI_IN_OUT_TXC-_R

HDMI_IN_OUT_TXC+_R

RV180 0_0402_ 5%~D@

LV11

DLW21SN900 HQ2L_0805_4P~D

2

3

1 2

RV181 0_0402_ 5%~D@

1 2

RV182 0_0402_ 5%~D@

DLW21SN900 HQ2L_0805_4P~D

3

2

1 2

RV183 0_0402_ 5%~D@

1 2

RV186 0_040 2_5%~D@

DLW21SN900 HQ2L_0805_4P~D

2

3

1 2

RV187 0_040 2_5%~D@

1 2

RV188 0_040 2_5%~D@

3

2

DLW21SN900 HQ2L_0805_4P~D

1 2

RV189 0_0402_5 %~D@

LV12

LV13

LV14

1

4

1

4

1

HDMI_IN_OUT_TXD2+

HDMI_IN_OUT_TXD2-

HDMI_IN_OUT_TXD1-

HDMI_IN_OUT_TXD1+

HDMI_IN_OUT_TXD0+

HDMI_IN_OUT_TXD0-

HDMI_IN_OUT_TXC-

HDMI_IN_OUT_TXC+

3.3P_0402_50V8C~D

CV489

1

2

1

2

1

2

1

2

CV488

1

2

3.3P_0402_50V8C~D

CV490

CV491

1

2

3.3P_0402_50V8C~D

CV492

CV493

1

2

3.3P_0402_50V8C~D

CV494

CV495

1

2

PCH_PWR_EN

SSM3K7002FU_ SC70-3~D

辦辦

D

+5VALW +HDMI_ 5V_OUT

QV13 SI3456DDV-T1-GE3_ TSOP6~D

D

6

2

CV117

10U_0603_6.3V6M~D

1

2

1 2

RV177 102K_0402_ 1%

2

G

QV14

HDMI IN/OUT

HDMI_IN_OUT_HPD32

HDMI_IN_OUT_DDC32

HDMI IN/OUT Cable

UART_TX_603828 UART_RX_603828

1

G

RV178

0_0402_5%~ D

13

D

S

部部

1 2

RV184 0_0402_ 5%~D

1 2

RV185 0_0402_ 5%~D

S

45

3

1

CV122

0.1U_0603_50V7K~D

2

+5VS

12

RV678

4.7K_0402_1 %~D

RV679 100K_0 402_1%

部部

E

1

CV118

1U_0402_6.3V6K~D

2

@

RV179

0_0402_5%~D

HDMI Input/Output Connector

+HDMI_5V_OUT

JHDMI1

HDMI_IN_OUT_HPD

HDMI_IN_OUT_DDC HDMI_IN_OUT_SDATA HDMI_IN_OUT_SCLK HDMI_UART_TX HDMI_UART_RX HDMI_IN_OUT_TXC-

HDMI_IN_OUT_TXC+ HDMI_IN_OUT_TXD0-

HDMI_IN_OUT_TXD0+ HDMI_IN_OUT_TXD1-

HDMI_IN_OUT_TXD1+ HDMI_IN_OUT_TXD2-

HDMI_IN_OUT_TXD2+

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

SUYIN_100042GR01 9M27SZL

CONN@

GND GND GND GND

OK

20 21 22 23

Reserve for EMI please close to JHDMI1

4 4

Security Classification

2012/05/14 2013/05/13

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

A

B

C

2012/05/14 2013/05/13

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

HDMI In/Out SW/Connector

LA-9201P

E

26 6 6Tuesday, August 14 , 2012

0.1

5

4

3

2

1

+3VS

1 2

RV191 4.7K_0402_5%~D@

1 2

RV192 4.7K_0402_5%~D@

1 2

RV194 4.7K_0402_5%~D@

1 2

D D

RV195 4.7K_0402_5%~D@

RV197 4.7K_0402_5%~D@

RV199 4.7K_0402_5%~D@

RV201 4.7K_0402_5%~D@

RV202 4.7K_0402_5%~D@

1 2

HDMI_DDCBUF

HDMI_CFG_HPD

HDMI_IN2_PEQ

HDMI_IN1_PEQ

1

2

+3VS

MMST3904-7-F_SOT323-3~D

.1U_0402_16V7K~D

10U_0603_6.3V6M~D

CV135

1

CV133

CV134

2

HDMI_SW_DETECT

Close to U3 VCC pins

PS8271 PEQ=L, Middle level receiving equalization selection PEQ=H, High level receiving equalization selection PEQ=M, Low level receiving equalization selection

PS121 When DDCBUF_EN# is HIGH, the DDC channel is disabled, SCL/SDA and SCLZ/SDAZ are disconnected

GPU_HDMI_TXD2-47 GPU_HDMI_TXD2+47 GPU_HDMI_TXD1-47

GPU

C C

CPU

B B

DGPU_EDIDSEL#

+5VS +HDMI_5V_OUT

1

2

A A

GPU_HDMI_TXD1+47 GPU_HDMI_TXD0-47 GPU_HDMI_TXD0+47 GPU_HDMI_TXC-47 GPU_HDMI_TXC+47

CPU_HDMI_N28 CPU_HDMI_P28 CPU_HDMI_N18 CPU_HDMI_P18 CPU_HDMI_N08 CPU_HDMI_P08 CPU_HDMI_N38 CPU_HDMI_P38

+3VS

RV207 2.2K_0402 _5%

RV210 2.2K_0402 _5%

0.01U_0402_16V7K~D

DGPU_EDIDSEL#19,24

PCH_GPIO3519

SN74AHC1G08DCKR_SC70-5

DV7

BAT1000-7-F_SOT23-3~D

3

NC

2 1

1U_0603_10V6K~D

@

CV158

DGPU_SELECT#15,24

SN74AHC1G08DCKR_SC70-5

CV154

W=40mils

+HDMI_5V

0.01U_0402_16V7K~D

PCH_GPIO35

GPU_HDMI_TXD2GPU_HDMI_TXD2+ GPU_HDMI_TXD1GPU_HDMI_TXD1+ GPU_HDMI_TXD0GPU_HDMI_TXD0+ GPU_HDMI_TXCGPU_HDMI_TXC+ GPU_HDMI_TXC+_C

CPU_HDMI_N2 CPU_HDMI_P2 CPU_HDMI_N1 CPU_HDMI_P1 CPU_HDMI_N0 CPU_HDMI_P0 CPU_HDMI_N3 CPU_HDMI_P3

12

UV15

CV159

PCH_DPB_HDMI_DAT

PCH_DPB_HDMI_CL K

+3VS

5

1

P

IN1

O

2

IN2

G

3

12

RV2270_0402_5%~D

@

1 2

5A_125V_R451005.MRL~D

+3VS

12

5

1

IN1

2

IN2

UV16

3

CV136 .1U_0402_16 V7K~D CV137 .1U_0402_16 V7K~D CV138 .1U_0402_16 V7K~D CV139 .1U_0402_16 V7K~D CV140 .1U_0402_16 V7K~D CV141 .1U_0402_16 V7K~D CV142 .1U_0402_16 V7K~D CV143 .1U_0402_16 V7K~D

CV145 .1U_0402_ 16V7K~D CV146 .1U_0402_ 16V7K~D CV147 .1U_0402_ 16V7K~D CV148 .1U_0402_ 16V7K~D CV149 .1U_0402_ 16V7K~D CV150 .1U_0402_ 16V7K~D CV151 .1U_0402_ 16V7K~D CV152 .1U_0402_ 16V7K~D

4

DGPU_EDIDSEL#_R

FV5

12

RV2280_1206_5%~D

P

4

DGPU_SEL#

O

G

12 12 12 12 12 12 12 12

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

VGA_HDMI_DET46 PCH_HDMI_HPD15

GPU_HDMI_SCLK47

GPU_HDMI_SDATA47

PCH_DPB_HDMI_CLK15 PCH_DPB_HDMI_DAT15

DGPU_EDIDSEL#_R 30

1U_0603_10V4Z~D

1

CV157

2

GPU_HDMI_TXD2-_C GPU_HDMI_TXD2+_C GPU_HDMI_TXD1-_C GPU_HDMI_TXD1+_C GPU_HDMI_TXD0-_C GPU_HDMI_TXD0+_C GPU_HDMI_TXC-_C

CPU_HDMI_N2_C CPU_HDMI_P2_C CPU_HDMI_N1_C CPU_HDMI_P1_C CPU_HDMI_N0_C CPU_HDMI_P0_C CPU_HDMI_N3_C CPU_HDMI_P3_C

GPU_HDMI_SCLK GPU_HDMI_SDATA PCH_DPB_HDMI_CLK PCH_DPB_HDMI_DAT

DGPU_EDIDSEL#_R

DGPU_SEL#

HDMI_IN1_PEQ HDMI_IN2_PEQ

2.2U_0603_10V7K~D CV153

499_0402_1%~D

1

2

8/25 change RV53 from 430 to 499ohm

CPU_HDMI_N2_C CPU_HDMI_P2_C CPU_HDMI_N1_C CPU_HDMI_P1_C CPU_HDMI_N0_C CPU_HDMI_P0_C CPU_HDMI_N3_C CPU_HDMI_P3_C

PCH_DPB_HDMI_CLK PCH_DPB_HDMI_DAT

44 45 47 48

11 12 13 14 16 17

46 10 41 42 19 20

22 21

15

23 24

12

RV218

18 43 49

+3VS

2

B

E

3 1

10K_0402_5%~D

RV196 0_0402_5%~D

@

RV200

1 2

HDMI_SINK_HPDPCH_HDMI_HPD

@

200K_0402_5%

1 2

C

QV15

@

DGPU_HPD_INT#19,30

UV14

IN1_D1n IN1_D1p IN1_D2n IN1_D2p

1

IN1_D3n

2

IN1_D3p

4

IN1_D4n

5

IN1_D4p

8

IN2_D1n

9

IN2_D1p IN2_D2n IN2_D2p IN2_D3n IN2_D3p IN2_D4n IN2_D4p

IN1_HPD IN2_HPD IN1_SCL IN1_SDA IN2_SCL IN2_SDA

SW_DDC SW_MAIN

3

IN1_PEQ IN2_PEQ

CEXT REXT

GND GND PAD

PS8271QFN48GTR-A1_QFN48_7X7

up@

1 2 1 2

RV614 0_04 02_5%~De n@

1 2

RV616 0_04 02_5%~De n@

1 2

RV618 0_04 02_5%~De n@

1 2

RV620 0_04 02_5%~De n@

1 2

RV622 0_04 02_5%~De n@

1 2

RV624 0_04 02_5%~De n@

1 2

RV626 0_04 02_5%~De n@ RV628 0_04 02_5%~De n@

1 2 1 2

RV630 0_04 02_5%~De n@ RV632 0_04 02_5%~De n@

1 2

RV674 0_04 02_5%~De n@

RV193

DGPU_HPD_INT#

HDMI_TXD2-_R HDMI_TXD2+_R HDMI_TXD1-_R HDMI_TXD1+_R HDMI_TXD0-_R HDMI_TXD0+_R HDMI_TXC-_R HDMI_TXC+_R

HDMI_SDA_R

200K_0402_5%

1 2

1 2 1 2

RV615 0_04 02_5%~Den@

1 2

RV617 0_04 02_5%~Den@

1 2

RV619 0_04 02_5%~Den@

1 2

RV621 0_04 02_5%~Den@

1 2

RV623 0_04 02_5%~Den@

1 2

RV625 0_04 02_5%~Den@

1 2

RV627 0_04 02_5%~Den@ RV629 0_04 02_5%~Den@

1 2 1 2

RV631 0_04 02_5%~Den@ RV633 0_04 02_5%~Den@

RV198

2

G

QV16

D

VDD VDD

PWDN_ASQ

CFG_HPD

DDCBUF

PRE_EMI

RTERM

OUT_D1n

OUT_D1p

OUT_D2n OUT_D2p OUT_D3n OUT_D3p

OUT_D4n

OUT_D4p

OUT_HPD

OUT_SCL

OUT_SDA

S

6 31

25

28

40 34 7

36 35 33 32 30 29 27 26

39 38 37

1 3

SSM3K7002F_SC59-3~D

LV15

MBK1608221YZF_2P

1 2

BAV99-7-F_SOT23-3

1

DV4

@

2

3

+3VS

HDMI_CFG_HPD

HDMI_DDCBUF

1 2

@

1 2

RV204 4.7K_0402_5%~D RV545 4.7K_0402_5%~D@

HDMI_TXD2HDMI_TXD2+ HDMI_TXD1HDMI_TXD1+ HDMI_TXD0HDMI_TXD0+ HDMI_TXCHDMI_TXC+

HDMI_SW_DETECT HDMI_SW_SCL HDMI_SW_SDA

Y

HDMI_TXD2HDMI_TXD2+ HDMI_TXD1HDMI_TXD1+ HDMI_TXD0HDMI_TXD0+ HDMI_TXCHDMI_TXC+

HDMI_SW_SCLHDMI_SCL_R HDMI_SW_SDA

+5VS

+3VS

HDMI_SINK_HPD

220P_0402_50V7K~D

1

2

0

GPU PCH

+3VS

12

RV190 100K_0402_5%~D

CV132

2

G

HDMI_OE#

1

D

QV17

SSM3K7002F_SC59-3~D

S

3

HDMI_SINK_HPD_R2 6

+3VS

1 2

RV203 4.7K_0402_5%~D

PS121 CFG0/ CFG1 SCLZ/SDAZ output voltage select; CFG1:0=00 LOW-level input voltage: <0.40V LOW-level output voltage: 0.60V PS121 PC0/PC1/PC2 Inputs equalization control, default inputs equalization setting at 12 dB 000: 12 dB, 001: 16 dB, 010: 10 dB, 011: 7 dB 100: 1.5 dB, 101: 4 dB, 110: 9 dB, 111: 7 dB

+3VS

HDMI_TXD2+ HDMI_TXD2HDMI_TXD1+ HDMI_TXD1HDMI_TXD0+ HDMI_TXD0HDMI_TXC+ HDMI_TXC-

HDMI_SINK_HPD_R

HDMI_DDCBUF

HDMI_OE#

DVI_SDATA DVI_SCLK

HDMI_CFG1 HDMI_CFG0

HDMI_PC0 HDMI_PC1

HDMI_PC2

12

RV205499_0402 _1%~D

CV1442.2U_0402_ 6.3V6M~D

UV13

38

IN1p

39

IN1n

41

IN2p

42

IN2n

44

IN3p

45

IN3n

47

IN4p

48

IN4n

2

POW

30

HPD_SINK

26

I2C_CTL_EN#

32

NC/DDCBUF_EN#

25

NC/OE#

8

SDA

9

SCL

34

SDA_CTL/CFG1

35

SCL_CTL/CFG0

3

I2C_ADDR0/PC0

4

I2C_ADDR1/PC1

1

GND/PC2

6

REXT

10

CEXT

1HDMI_SW_DET

12

RV2064.7K_0402_5%~D @

12

RV2084.7K_0402_5%~D @

12

RV2094.7K_0402_5%~D @

12

RV2114.7K_0402_5%~D @

12

RV2124.7K_0402_5%~D @

12

RV2132.2K_0402_5%~D

12

RV2142.2K_0402_5%~D

12

RV2154.7K_0402_5%~D @

12

RV2174.7K_0402_5%~D @

12

RV2194.7K_0402_5%~D @

12

RV2214.7K_0402_5%~D @

12

RV2224.7K_0402_5%~D @

GND15GND2

+3VS

12

11

15

VCC1

VCC2

GND424GND631GND5

GND3

18

33

46

21

VCC4

VCC540VCC6

VCC3

GND7

GND837GND9

36

27

HDMI_CFG1 HDMI_CFG0 HDMI_PC0 HDMI_PC1 HDMI_PC2 HDMI_SW_SDA HDMI_SW_SCL

HDMI_CFG1 HDMI_CFG0 HDMI_PC0 HDMI_PC1

HDMI_PC2

23

OUT1p

22

OUT1n

20

OUT2p

19

OUT2n

17

OUT3p

16

OUT3n

14

OUT4p

13

OUT4n

7

HPD

29

SDAZ

28

SCLZ

GND10

PS121QFN48G_QFN48_7X7

43

49

HDMI_OUT_TXD2+ HDMI_OUT_TXD2HDMI_OUT_TXD1+ HDMI_OUT_TXD1HDMI_OUT_TXD0+ HDMI_OUT_TXD0HDMI_OUT_TXC+ HDMI_OUT_TXC-

HDMI_SINK_HPD

HDMI_SW_SDA HDMI_SW_SCL

Close to UV2 VCC pins

0.01U_0402_16V7K~D

0.1U_0402_16V4Z~D

1

CV128

2

HDMI_OUT_TXD2+ 26 HDMI_OUT_TXD2- 26 HDMI_OUT_TXD1+ 26 HDMI_OUT_TXD1- 26 HDMI_OUT_TXD0+ 26 HDMI_OUT_TXD0- 26 HDMI_OUT_TXC+ 26 HDMI_OUT_TXC- 26

IN2IN1

+HDMI_5V_OUT

RV224

1.5K_0402_5%

RV223

1.5K_0402_5%

12

DVI_SDATA DVI_SCLK

DVI_SDATA 26 DVI_SCLK 26

+3VS

0.1U_0402_16V4Z~D

0.01U_0402_16V7K~D

1

CV130

CV129

2

CV131

2

DGPU_SELECT# DGPU_SEL#

5

12

RV2290_0402_5%~D @

DGPU_SEL# 30

Security Classification

2012/05/14 2013/05/13

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

4

3

2012/05/14 2013/05/13

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

HDMI SW-CPU & MXM/Re-driver

LA-9201P

1

27 66Thursday, August 16, 2012

0.1

5

4

3

2

1

LV16

1 2

BLM18BD601SN1D_0603~D

D D

+3VS +3.3V_DVDDA

LV21

1 2

BLM18BD601SN1D_0603~D

+3.3VS_AVDD+3VS

22U_0805_6.3VAM~D

0.1U_0402_25V6K~D

CV161

CV160

1

2

22U_0805_6.3VAM~D

1

CV177

2

CV162

1

2

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D CV179

CV178

1

2

Close to respective power Pins

10P_0402_50V8J~D

CV192

TCLK

C C

HDMI_IN_EN32

辦辦

HDMI IN

B B

A A

HDMI_IN_CK-26

HDMI_IN_CK+26

HDMI_IN_D0-26

HDMI_IN_D0+26

HDMI_IN_D1-26

HDMI_IN_D1+26

HDMI_IN_D2-26

HDMI_IN_D2+26

部部部

27MHZ_10PF_X3S027000BA1H-U~D

RV676

4.7K_0402_1%~D

EC

RV677

4.7K_0402_1%~D

HDMI_IN_CKHDMI_IN_CK+ HDMI_IN_D0HDMI_IN_D0+ HDMI_IN_D1HDMI_IN_D1+ HDMI_IN_D2HDMI_IN_D2+

+3.3VS_AVDD

I2S_DAT/SPDIF_IN34

BS_INTERFACE_SEL1 BS_INTERFACE_SEL0 BS_UART_FUNCTION_SEL

5

+3.3VS_AVDD

LV17

1 2

0.1U_0402_25V6K~D CV163

1

2

0.1U_0402_25V6K~D

CV180

1

2

1

2

YV1

1 2

G1

+3.3V_DVDDA

2.2K_0402_5%~D

RV261

1 2

4700P_0402_25V7K~D

CV197

1

2

+3.3V_DVDDA

12

@

RV278 10_0402_5%~D

RV279 10_0402_5%~D

RV280 10_0402_5%~D

RV281 10_0402_5%~D

RV284 10_0402_5%~D

RV286 10_0402_5%~D

RV288 10_0402_5%~D

RV289 10_0402_5%~D

BLM18BD601SN1D_0603~D

0.1U_0402_25V6K~D CV164

Can not place large capacitor to prevent pulse happened when LVDS power switch off/on

+3.3VS_AVDD

1 2

BLM18BD601SN1D_0603~D

AVDD_RPLL pin10 C610 0.1uF to AVSS_RPLL pin7

+3.3V_AVDD_RPLL

10P_0402_50V8J~D

CV193

1

2

3

XTAL

4

G2

HDMI_RST#

1 2

RV264 10K_0402_5%~D

CV195 0.1U_0 402_16V4Z~D CV196 0.1U_0 402_16V4Z~D CV198 0.1U_0 402_16V4Z~D CV199 0.1U_0 402_16V4Z~D CV200 0.1U_0 402_16V4Z~D CV201 0.1U_0 402_16V4Z~D CV202 0.1U_0 402_16V4Z~D CV203 0.1U_0 402_16V4Z~D

CV204 0.1U_0 402_16V4Z~D

+1.2V_AVDD

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

RV291 249_040 2_1%~D

1 2

RV293 0_04 02_5%~D@

1 2

RV295 0_0402_5%~D

1 2

RV296 0_0402_5%~D

1 2

RV297 0_0402_5%~D

LV23

+3.3V_AVDD_RPLL

+3.3V_AVDD_LVTX

+3.3VS_AVDD

+3.3V_DVDDA

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2

T60PAD~D @ T58PAD~D @

1 2

RV276 300_0402_1%

HDMI_IN_SW_HPD

+3.3V_AVDD_LVTX

1

2

+3.3V_AVDD_RPLL

1

2

XTAL TCLK

+3.3V_DVDDA

EC_HDMI_DAT EC_HDMI_CLK HDMI_SW_DAT HDMI_SW_CLK

HDMI_IN_CK-_R HDMI_IN_CK+_R HDMI_IN_D0-_R HDMI_IN_D0+_R HDMI_IN_D1-_R HDMI_IN_D1+_R HDMI_IN_D2-_R HDMI_IN_D2+_R

BS_RESERVED_R BS_SPI_R BS_I2C_SRC_R

BS_I2C_ON_R

HDMI_SPI_CS# HDMI_SPI_CLK HDMI_SPI_SO HDMI_SPI_SI

0.1U_0402_25V6K~D CV170

1

2

22U_0805_6.3VAM~D

2

CV181

1

EC_SMB_CK2_R32 EC_HDMI_CLK 29

10

11 23

80 86 90

100

38 109 128

8 9

36

4

125

92

93

95

96

98

99 105 106

70

71

72

73

74

44

45

111 112

48

49

53

54

56

57

59

60

62

63

51

43

75

76

78

79

81

82

84

85

87 113 114

39

40

41

42

65

66

67

68

47

55

61

77

83

+1.2VS_HDMI +1.2V_AVDD

LV18

1 2

0.1U_0402_25V6K~D CV171

0.1U_0603_25V7K~D

CV182

UV1

VDDA_3V3

AVDD_OUT_33 AVDD_OUT_33

HDMI_VDDA_3V3 HDMI_VDDA_3V3 ADC_AVDD_3V3 ADC_AVDD_3V3

RVDD_33 RVDD_33 RVDD_33

XTAL TCLK

NC

RESETn STI_TM2

ADC_A_N ADC_A_P ADC_B_N ADC_B_P ADC_C_N ADC_C_P HSYNC_IN VSYNC_IN

VEDID_VDD_3V3

A_I2C_SDA A_I2C_SCL D1_I2C_SDA / GPIO_28 D1_I2C_SCL / GPIO_29 D2_I2C_SDA / GPIO_24 D2_I2C_SCL / GPIO_25

GPIO_44 / S_I2C_SCL GPIO_43 / S_I2C_SDA

DPRX_AUXN DPRX_AUXP DPRX_ML_L0P DPRX_ML_L0N DPRX_ML_L1P DPRX_ML_L1N DPRX_ML_L2P DPRX_ML_L2N DPRX_ML_L3P DPRX_ML_L3N DPRX_REXT DPRX_HPD_OUT / GPO_5

HDMI_RXCN HDMI_RXCP HDMI_RX0N HDMI_RX0P HDMI_RX1N HDMI_RX1P HDMI_RX2N HDMI_RX2P HDMI_REXT HDMI_HPD / GPIO_22 HDMI_CEC / GPIO_23

I2S_0 (S/PDIF) / GPO_12(BS_RESERVED) I2S_AUMCLK / GPO_13(BS_SPI_FUN_SEL) I2S_WS / GPO_14(BS_I2C_SRC_SEL) I2S_SCLK / GPO_15(BS_I2C_ON_SPI_EN)

SPI_CSn / IRQ_IN / GPO_8 SPI_CLK / GPO_9(BS_INTERFACE_SEL1) SPI_DI / GPO_10(BS_INTERFACE_SEL0) SPI_DO / GPO_11(BS_UART_FUNCTION_SEL)

DPRX_VSSD DPRX_VSSA DPRX_VSSA

HDMI_VSSA HDMI_VSSA

STDP6038-AC_PQFP128_20X14~D

BLM18BD601SN1D_0603~D

0.1U_0402_25V6K~D CV172

1

1.2V

2

TDC 0.52A Peak Current 0.73A OCP current 3.5A

+1.2VS_HDMI +1.2V_DVDD

LV22

1 2

BLM18AG601SN1D_0603~D

1 2

RV250 22_0402_5%

1 2

RV251 22_0402_5%

22U_0805_6.3VAM~D

1

2

LVDS

GPO_2 / TTL_D7 / PWM2(BS_OCM_BOOT_SEL)

STI_TM1 / PWM1 / TTL_D6 / GPO_1

GPO_0 / PWM0 / TTL_D5(BS_OSC_SEL)

TTL_D4 / GPIO_21(BS_I2C_DEV_ID2) TTL_D3 / GPIO_20(BS_I2C_DEV_ID1) TTL_D2 / GPIO_19(BS_I2C_DEV_ID0)

UART_TX / TTL_SYNC1 / GPO_7(BS_XTAL_TCLK_SEL)

TTL_CKOUT / GPIO16(BS_EXTKEY_EN)

HDMI

LBADC_IN2 / GPIO_33 / TTL_SYNC4 LBADC_IN1 / GPIO_32 / TTL_SYNC3

4

22U_0805_6.3VAM~D

0.1U_0402_25V6K~D

1

CV165

1

2

0.1U_0402_25V6K~D CV184

1

CV183

2

O_CH0N_LV / TTL_D29 / GPIO_67 O_CH0P_LV / TTL_D28 / GPIO_66 O_CH1N_LV / TTL_D27 / GPIO_65 O_CH1P_LV / TTL_D26 / GPIO_64 O_CH2N_LV / TTL_D25 / GPIO_63 O_CH2P_LV / TTL_D24 / GPIO_62 O_CLKN_LV / TTL_D23 / GPIO_61 O_CLKP_LV / TTL_D22 / GPIO_60 O_CH3N_LV / TTL_D21 / GPIO_59 O_CH3P_LV / TTL_D20 / GPIO_58

E_CH0N_LV / TTL_D19 / GPIO_57 E_CH0P_LV / TTL_D18 / GPIO_56 E_CH1N_LV / TTL_D17 / GPIO_55 E_CH1P_LV / TTL_D16 / GPIO_54 E_CH2N_LV / TTL_D15 / GPIO_53 E_CH2P_LV / TTL_D14 / GPIO_52 E_CLKN_LV / TTL_D13 / GPIO_51

E_CLKP_LV / TTL_D12 / GPIO_50 E_CH3N_LV / TTL_D11 / GPIO_49 E_CH3P_LV / TTL_D10 / GPIO_48

PBIAS / TTL_D9 / GPO_4

PPOWER / TTL_D8 / GPO_3

TTL_D1 / GPIO18 / M_I2C_SCL

TTL_D0 / GPIO17 / M_I2C_SDA

UART_RX / TTL_SYNC2 / GPO_6

CV167

CV166

1

2

EC_HDMI_CLK EC_HDMI_DAT

LBADC_IN4 / GPIO_35 LBADC_IN3 / GPIO_34

1

2

0.1U_0402_25V6K~D

CV185

CV186

1

2

CVDD_12 CVDD_12 CVDD_12 CVDD_12

ADC_DVDD_1V2

DPRX_VDDD_1V2

DPRX_VDDA_1V2 DPRX_VDDA_1V2 DPRX_VDDA_1V2

VDDA_1V2

VBUFC_RPLL

GPIO_45

VSSA_33

LVVSS LVVSS

CRVSS CRVSS CRVSS CRVSS

ADC_VSSA ADC_VSSA ADC_VSSA ADC_VSSD

0.1U_0402_25V6K~D

CV168

CV169

1

2

0.1U_0402_25V6K~D

CV187

1

2

CV188

1

2

EC_HDMI_DAT 29EC_SMB_DA2_R32

116 108 46 35

88

50

64 58 52

6

33

LVDS_6038_TXOUT0-

32

LVDS_6038_TXOUT0+

31

LVDS_6038_TXOUT1-

30

LVDS_6038_TXOUT1+

29

LVDS_6038_TXOUT2-

28

LVDS_6038_TXOUT2+

27

LVDS_6038_TXCLK-

26

LVDS_6038_TXCLK+

25 24

21

LVDS_6038_TZOUT0-

20

LVDS_6038_TZOUT0+

19

LVDS_6038_TZOUT1-

18

LVDS_6038_TZOUT1+

17

LVDS_6038_TZOUT2-

16

LVDS_6038_TZOUT2+

15

LVDS_6038_TZCLK-

14

LVDS_6038_TZCLK+

13 12

3

HDMI_IN_BKL_EN

2

HDMI_IN_ENVDD

1

BS_OCM_BOOT_SEL

127

HDMI_IN_AUD_CODEC

126

HDMI_IN_PWM

124

BS_I2C_DEV_ID2

123

BS_I2C_DEV_ID1

122

BS_I2C_DEV_ID0

121

DHMI_IN_NV_CLK_R

120

DHMI_IN_NV_DAT_R

1 2

RV274 0_04 02_5%~D

119

BS_EXTKEY_EN

118

UART_TX_6038

117

UART_RX_6038

5

103

RV287 10K_0402_5%~D

104

HDMI_PLUG_IN_CAB_DET

101

RV290 10K_0402_5%~D

102

RV292 10K_0402_5%~D

110

7

34 22

115 107 69 37

97 94 91 89

+5VS+3VS

12

RV234

0_0402_5%~D

1

CV176

2

0.1U_0402_25V6K~D 10U_0805_4VAM~D

CV189

+1.2V_DVDD

+1.2V_AVDD

RV270 0_0402_5%~D

BS_XTAL_TCLK_SEL

12

12 12

HDMI_TOGGLE 32

3

+1.2VS_HDMI

1 2

RV231 100K_0402_5%~D

1U_0402_6.3V6K~D

CV174

1

2

UV17

4

VDD

3

VIN

VOUT

2

EN

1

PGOOD

GND GND

RT9025-25PSP_SO8

ADJ

5

NC

6

7

8 9

.1U_0402_16V7K~D

CV175

12

LV19

BLM18AG601SN1D_0603~D

10K_0402_5%~D

RV236

20K_0402_5%~D

RV241

12

For 4028

BLM18AG601SN1D_0603~D

HDMI_SPI_CLK_R

LV20

+1.2VS_A+1.2VS

12

15_0402_5%~D

@

12

RV244

15P_0402_50V8J~D

1

@

CV190

2

2Mbit

RV252

15_0402_5%~D

HDMI_SPI_CS# HDMI _SPI_CS#_R HDMI_SPI_SO

RV253 15_0402_5%~D RV255 10K_0402_5%~D

EDID_WP

2

B

E

3 1

LVDS_6038_TXOUT0- 29 LVDS_6038_TXOUT0+ 29 LVDS_6038_TXOUT1- 29 LVDS_6038_TXOUT1+ 29 LVDS_6038_TXOUT2- 29 LVDS_6038_TXOUT2+ 29 LVDS_6038_TXCLK- 29 LVDS_6038_TXCLK+ 29

LVDS_6038_TZOUT0- 29 LVDS_6038_TZOUT0+ 29 LVDS_6038_TZOUT1- 29 LVDS_6038_TZOUT1+ 29 LVDS_6038_TZOUT2- 29 LVDS_6038_TZOUT2+ 29 LVDS_6038_TZCLK- 29 LVDS_6038_TZCLK+ 29

HDMI_IN_BKL_EN 24 HDMI_IN_ENVDD 2 4

1 2

RV273 0_04 02_5%~D

HDMI_IN_PWM 24

BS_OSC_SEL

+3.3V_DVDDA

1 2

HDMI_IN_AUDIO_CODEC 34

RV26822_0402_5%

2011/11/25 remove LVDS conn

T182PAD~D @

UART_TX_6038 26 UART_RX_6038 26

T183PAD~D @

Security Classification

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

0.1U_0402_16V4Z~D

Issued Date

+5VS

CV207

1

2

HDMI_IN_HPD

+HDMI_5V_OUT

RV282

4.7K_0402_5%~D

1 2

UART_RX_6038

1 2

2012/05/14 2013/05/13

2

B

RV29422_0402_5%

12 1 2 1 2

+3.3V_DVDDA

+HDMI_5V_OUT

1SS355TE-17_SOD323-2

MMST3904-7-F_SOT323-3~D

C

QV18

RV283

1K_0402_1%~D

1 2

MMST3904-7-F_SOT323-3~D

HDMI_IN_HPD_R

QV20

C

E

3 1

Compal Secret Data

Deciphered Date

2

HDMI_SPI_SO_R

4.7K_0402_1%~D

12

@

RV258

DV8

0.1U_0402_16V4Z~D

UV20

1

E0

2

E1

3

E2

4

VSS

CAT24C02WI-GT3A_SO8

2Kbit

HDMI_PLUG_IN_CAB_DET

SPI ROM

UV18

1

S#

2

Q

RESET#

3

W#

4

VSS

MX25L2006EM1I-12G_SOP8

16KBit NVRAM

UV19

1

E0

2

E1

3

E2

4

VSS

CAT24C16WI-GT3_SO8

1

221

CV205

HDMI_IN_HPD_R 26

1

DV9 1SS355TE-17_SOD323-2

+5VS_HDMI_IN_EDID

1

2

8

VCC

7

WC

6

SCL

5

SDA

+3.3V_DVDDA

+HDMI_5V_OUT

HDMI_IN_CAB_DET#

VCC

C D

221

4.7K_0402_1%~D

12

HDMI_SW_CLK HDMI_SW_DAT

12

1

2

+3.3V_DVDDA

1 2

RV230 10K_0402_5%~D

22U_0805_6.3VAM~D

CV173

1

2

8 7 6 5

HDMI_SPI_SI_R HDMI_SPI_SI

8

VCC

7

WC

6

SCL

5

SDA

+5VS

4.7K_0402_1%~D

12

RV265

RV266

10K_0402_5%~D

RV275

RV277 33K_0402_5%

.1U_0402_16V7K~D

CV206

HDMI_IN_SW_HPD

1

2

3

RV298 0_0402_5%~D

1 2

RV232 10K_0402_5%~D

1 2

RV233 10K_0402_5%~D

1 2

RV235 10K_0402_5%~D

1 2

RV237 10K_0402_5%~D

1 2

RV238 10K_0402_5%~D

1 2

RV239 10K_0402_5%~D

1 2

RV240 10K_0402_5%~D

1 2

RV242 10K_0402_5%~D

1 2

RV243 10K_0402_5%~D

1 2

RV245 10K_0402_5%~D

1 2

RV246 10K_0402_5%~D

1 2

RV247 10K_0402_5%~D

1 2

RV248 10K_0402_5%~D

1 2

RV249 10K_0402_5%~D

12

RV25410K_0402_ 5%~D

+3.3V_DVDDA

0.1U_0402_16V4Z~D

1

CV194

2

1 2

RV262 22_0402_5%

1 2

RV263 22_0402_5%

4.7K_0402_1%~D

RV267

1 2

RV269 22_0402_5%

1 2

RV271 100_0402_1%~D

1 2

RV272 100_0402_1%~D

BS_UART_FUNCTION_SEL

+3.3V_DVDDA

.1U_0402_16V7K~D

2

CV191

1

1 2 1 2

4.7K_0402_1%~D

12

RV259

EDID_WP HDMI_CLK HDMI_DAT

HDMI_IN_CAB_DET# 32

2KBit

12

HDMI_IN_CAB_DET#

13

D

SSM3K7002FU_SC70-3~D

MBK1608221YZF_2P

BAV99-7-F_SOT23-3 DV10

@

1 2

Title

Size Document Number Rev

Custom

LA-9201P

Date: Sheet of

QV19

LV24

12

HDMI_IN_DET#

Compal Electronics, Inc.

HDMI to LVDS-STDP6038

2

G

S

HDMI_IN_HPDHDMI_IN_HPD

220P_0402_50V7K~D

1

CV208

2

1

BS_I2C_DEV_ID2

BS_I2C_DEV_ID1

BS_I2C_DEV_ID0

BS_RESERVED_R

BS_SPI_R

BS_I2C_SRC_R

BS_I2C_ON_R

BS_EXTKEY_EN

BS_OCM_BOOT_SEL

BS_INTERFACE_SEL1

BS_INTERFACE_SEL0

BS_XTAL_TCLK_SEL

BS_OSC_SEL

HDMI_IN_AUD_CODEC

HDMI_SPI_CLKHDMI_SPI_CLK_R

RV25615_0402_ 5%~D RV25715_0402_ 5%~D

4.7K_0402_1%~D

12

RV260

DHMI_IN_NV_CLK_R DHMI_IN_NV_DAT_R

HDMI_CLK 26 HDMI_DAT 26

+HDMI_5V_OUT

100K_0402_5%~D

RV285

12

HDMI_IN_DET# 26

28 66Tuesday, August 14, 2012

0.1

5

4

3

2

1

D D

C C

TX_XTAL TX_TCLK

27MHZ_10PF_X3S027000BA1H-U~D

+1.2VS_A

0.1U_0603_25V7K~D RV300 240_0402_1%

CV216

2

1

4028_EDP_AUXN25 4028_EDP_AUXP25

4028_EDP_L0N25 4028_EDP_L0P25 4028_EDP_L1N25 4028_EDP_L1P25 4028_EDP_L2N25 4028_EDP_L2P25 4028_EDP_L3N25 4028_EDP_L3P25

+AVDD_3V3

10P_0402_50V8J~D

2

CV232

1

1 2

G1

YV2

10P_0402_50V8J~D

2

1

3 4

G2

12

+3VS

2.7K_0402_5%

RV303

47P_0402_50V8J~D

CV243

DP_4028_HPD

4028_EDP_AUXN 4028_EDP_AUXP

4028_EDP_L0N 4028_EDP_L0P 4028_EDP_L1N 4028_EDP_L1P 4028_EDP_L2N 4028_EDP_L2P 4028_EDP_L3N 4028_EDP_L3P

TX_XTAL

12

TX_TCLK

RESET

2

SPI_DI_4028 SPI_DO_4028

1

SPI_CLK_4028 SPI_CSN_4028

IRQ/BOOT7 I2C_SCL

12

RV3140_0402_5%~D

12

RV3170_0402_5%~D

12

RV3210_0402_5%~D

DP_4028_HPD25

CV233

UV2C

C11

DPTX_REXT

C12

DPTX_HPD_IN/GPIO_23

C10

DPTX_AUXN

D10

DPTX_AUXP

B6

DPTX_ML_L0N

C6

DPTX_ML_L0P

A7

DPTX_ML_L1N

B7

DPTX_ML_L1P

A8

DPTX_ML_L2N

B8

DPTX_ML_L2P

B9

DPTX_ML_L3N

C9

DPTX_ML_L3P

B4

TX_XTAL

C4

TX_TCLK

E6

RESETn

D13

SPI_DI/HOST_D1/GPO_19

C14

SPI_DO/HOST_D0/GPO_20

E12

SPI_CLK/HOST_CLK/GPIO_18

F10

SPI_CSn/HOST_CS/GPIO_17

G4

IR_IN/GPIO_6

D12

IRQ/BOOT7/GPIO_12

C3

VBUFC_RPLL

F3

TESTMODE0

G3

TESTMODE1

AUX_I2C_SCL/GPIO_15

AUX_I2C_SDA_GPIO_16

I2C_SCL/GPIO_24

I2C_SDA/GPIO_25

UART_TX/BOOT1/GPIO_13

UART_RX/GPIO_14

eDP

AUX_UART_TX/BOOT4/GPIO_21

AUX_UART_RX/GPIO_22

I2S_BCLK/GPIO_7

I2S_WCLK/GPIO_4

CLK_OUT/GPIO_5/BOOT0

SYS, Audio & DPTX

PWM0/GPIO_0/BOOT3

GPIO_1/BOOT2

GPIO_2/BOOT5

GPIO_3/BOOT6

STDP4028-AB_LFBGA164

I2S_0/GPIO_8

I2S_1/GPIO_9 I2S_2/GPIO_10 I2S_3/GPIO_11

NC1 NC2 NC3 NC4 NC5 NC6

C13 B14

B13 A13

C2

UART_TX

B1

UART_RX

B12

AUX_UART_TX

A12

AUX_UART_RX

D2 F5 F4 D3

C1

E4

E3

3D_VIDEO

F12 G12 D11 E11 B2 B3

E5

GPIO_0/BOOT3

D4

GPIO_1/BOOT2

G10

GPIO_2/BOOT5

F11

GPIO_3/BOOT6

EC_HDMI_CLK_R EC_HDMI_DAT_R

I2C_SCL I2C_SDA

RV299 0_0402_5%~D@ RV301 0_0402_5%~D@

T180PAD~D @

T181PAD~D @

12 12

+5VS

0.1U_0402_16V4Z~D

4.7K_0402_5%~D

CV228

1

RV302

2

1 2

UART_RX

+5VS

4.7K_0402_5%~D

@

CV242

+3VS

@

RV304

1

2

1 2

AUX_UART_RX

1 2

RV305 4.7K_0402_5%~D

1 2

RV308 4.7K_0402_5%~D

1 2

RV309 4.7K_0402_5%~D

1 2

RV310 4.7K_0402_5%~D

1 2

RV311 4.7K_0402_5%~D

1 2

RV312 4.7K_0402_5%~D

1 2

RV313 4.7K_0402_5%~D

1 2

RV315 4.7K_0402_5%~D

1 2

RV316 4.7K_0402_5%~D@

1 2

RV318 4.7K_0402_5%~D

1 2

RV319 4.7K_0402_5%~D

1 2

RV320 4.7K_0402_5%~D

1 2

RV322 4.7K_0402_5%~D@

1 2

RV323 4.7K_0402_5%~D

EC_HDMI_CLK 28

EC_HDMI_DAT 28

+1.2VS_A +VDD_RPLL_1V2

LV26

BLM18AG601SN1D_0603~D

+1.2VS_A

LV28

BLM18AG601SN1D_0603~D

VEGA STDP4028 DPTx BootStraps

UV2B

LVDS_6038_TZOUT0-2 8 LVDS_6038_TZOUT0+28

LVDS_6038_TZOUT1-2 8 LVDS_6038_TZOUT1+28

B B

LVDS_6038_TZOUT2-2 8 LVDS_6038_TZOUT2+28

LVDS_6038_TZCLK-28 LVDS_6038_TZCLK+28

LVDS_6038_TZOUT0LVDS_6038_TZOUT0+

LVDS_6038_TZOUT1LVDS_6038_TZOUT1+

LVDS_6038_TZOUT2LVDS_6038_TZOUT2+

LVDS_6038_TZCLKLVDS_6038_TZCLK+

P8

O0_LVRX_CH0N_VIDIN23

N8

O0_LVRX_CH0P_VIDIN22

N9

O0_LVRX_CH1N_VIDIN21

M9

O0_LVRX_CH1P_VIDIN20

M10

O0_LVRX_CH2N_VIDIN19

L10

O0_LVRX_CH2P_VIDIN18

N11

O0_LVRX_CLKN_VIDIN17

M11

O0_LVRX_CLKP_VIDIN16

P12

O0_LVRX_CH3N_VIDIN15

N12

O0_LVRX_CH3P_VIDIN14

P13

O0_LVRX_CH4N_VIDIN3

N13

O0_LVRX_CH4P_VIDIN2

M13

O1_LVRX_CH0N_VIDIN23

M14

O1_LVRX_CH0P_VIDIN22

L12

O1_LVRX_CH1N_VIDIN21

L13

O1_LVRX_CH1P_VIDIN20

K12

O1_LVRX_CH2N_VIDIN19

K11

O1_LVRX_CH2P_VIDIN18

J12

O1_LVRX_CLKN_VIDIN17

J13

O1_LVRX_CLKP_VIDIN16

H13

O1_LVRX_CH3N_VIDIN15

H14

O1_LVRX_CH3P_VIDIN14

G13

O1_LVRX_CH4N_VIDIN3

G14

O1_LVRX_CH4P_VIDIN2

O0_LVRX_CH5N_VIDIN_CLK

O0_LVRX_CH5P_VIDIN_DE

O0_LVRX_CH6N_VIDIN24 O0_LVRX_CH6P_VIDIN25

O0 & O1 LVDS Input

O1_LVRX_CH5N_VIDIN_CLK

O1_LVRX_CH5P_VIDIN_DE

O1_LVRX_CH6N_VIDIN24 O1_LVRX_CH6P_VIDIN25

STDP4028-AB_LFBGA164

M8 L9

L11 M12

J10 H11

K10 J11

LVDS_6038_TXOUT0-28 LVDS_6038_TXOUT0+28

LVDS_6038_TXOUT1-28 LVDS_6038_TXOUT1+28

LVDS_6038_TXOUT2-28 LVDS_6038_TXOUT2+28

LVDS_6038_TXCLK-28 LVDS_6038_TXCLK+28

LVDS_6038_TXOUT0-

LVDS_6038_TXOUT0+

LVDS_6038_TXOUT1-

LVDS_6038_TXOUT1+

LVDS_6038_TXOUT2-

LVDS_6038_TXOUT2+

LVDS_6038_TXCLKLVDS_6038_TXCLK+

UV2A

P2

E0_LVRX_CH0N_VIDIN13

N2

E0_LVRX_CH0P_VIDIN12

P3

E0_LVRX_CH1N_VIDIN11

N3

E0_LVRX_CH1P_VIDIN10

N4

E0_LVRX_CH2N_VIDIN9

M4

E0_LVRX_CH2P_VIDIN8

M5

E0_LVRX_CLKN_VIDIN7

L5

E0_LVRX_CLKP_VIDIN6

N6

E0_LVRX_CH3N_VIDIN5

M6

E0_LVRX_CH3P_VIDIN4

P7

E0_LVRX_CH4N_VIDIN1

N7

E0_LVRX_CH4P_VIDIN0

G1

E1_LVRX_CH0N_VIDIN13

G2

E1_LVRX_CH0P_VIDIN12

H1

E1_LVRX_CH1N_VIDIN11

H2

E1_LVRX_CH1P_VIDIN10

J2

E1_LVRX_CH2N_VIDIN9

J3

E1_LVRX_CH2P_VIDIN8

K3

E1_LVRX_CLKN_VIDIN7

K4

E1_LVRX_CLKP_VIDIN6

L2

E1_LVRX_CH3N_VIDIN5

L3

E1_LVRX_CH3P_VIDIN4

M1

E1_LVRX_CH4N_VIDIN1

M2

E1_LVRX_CH4P_VIDIN0

E0_LVRX_CH5N_VIDIN_VSYNC E0_LVRX_CH5P_VIDIN_HSYNC

LVDS

E1_LVRX_CH5N_VIDIN_VSYNC E1_LVRX_CH5P_VIDIN_HSYNC

+3VS

BLM18AG601SN1D_0603~D

12

1

2

12

1

2

3D_VIDEO AUX_UART_TX GPIO_3/BOOT6

I2C_SDA EC_HDMI_DAT_R EC_HDMI_CLK_R

UART_TX

AUX_UART_TX

GPIO_0/BOOT3

GPIO_1/BOOT2

GPIO_2/BOOT5

GPIO_3/BOOT6

IRQ/BOOT7

E0_LVRX_CH6N_VIDIN26 E0_LVRX_CH6P_VIDIN27

E0 & E1 LVDS Input

E1_LVRX_CH6N_VIDIN26 E1_LVRX_CH6P_VIDIN27

STDP4028-AB_LFBGA164

22U_0805_6.3VAM~D

1

CV217

2

+AVDD_LVRX_1V2

22U_0805_6.3VAM~D

1

CV229

2

LV25

0.1U_0402_25V6K~D

12

0.1U_0402_25V6K~D

CV218

1

2

0.1U_0402_25V6K~D

CV230

1

2

M7 L6

M3 L4

J5 H4

J4 K5

22U_0805_6.3VAM~D

1

2

+3VS

BLM18AG601SN1D_0603~D

CV219

+3VS

CV231

1

2

10K_0402_5%~D

12

RV306

+AVDD_LVRX_1V2

+AVDD_OUT_LV_33

0.1U_0402_25V6K~D CV210

1

CV209

2

22U_0805_6.3VAM~D

0.1U_0402_25V6K~D

CV234

1

2

SPI_CSN_4028 SPI_DI_4028

+1.2VS

+3VS

+1.2VS_A

+AVDD_3V3

+VDD_RPLL_1V2

0.1U_0402_25V6K~D CV211

1

2

LV27

12

+1.2VS_A

0.1U_0402_25V6K~D

CV235

CV236

1

2

UV2D

E7

PVDD1

E8

PVDD1

K6

PVDD1

K9

PVDD1

G11

PVDD21

G5

PVDD22

B11

DPTX_VDDA_1V2

C7

DPTX_VDDA_1V2

C8

DPTX_VDDA_1V2

D9

DPTX_VDDA_1V2

D6

VDDA_3V3

D5

VDD33_TX

A3

VDD_RPLL

L7

AVDD_LVRX_12

STDP4028-AB_LFBGA164

H12

AVDD_OUT_LVRX_33

H3

AVDD_OUT_LVRX_33

L8

AVDD_OUT_LVRX_33

N1

AVDD_OUT_LVRX_33

N14

AVDD_OUT_LVRX_33

0.1U_0402_25V6K~D

1

2

1

2

1

2

+AVDD_OUT_LV_33

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D CV213

0.1U_0402_25V6K~D

1

2

1

2

CV214

1

2

+AVDD_3V3

0.1U_0402_25V6K~D

CV221

1

2

0.1U_0402_25V6K~D CV238

1

2

2Mbit

VCC

RESET#

C D

CV212

1

2

22U_0805_6.3VAM~D

CV220

22U_0805_6.3VAM~D

CV237

UV3

1

S#

2

Q

3

W#

4

VSS

MX25L2006EM1I-12G_SOP8

PWR & GND

0.1U_0402_25V6K~D CV215

1

2

+1.2VS

22U_0805_6.3VAM~D

CV222

1

CV223

2

0.1U_0402_25V6K~D

CV239

CV240

1

2

0.1U_0402_16V4Z~D

8 7 6

SPI_CLK_4028

5

SPI_DO_4028

PVSS3 PVSS3

PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3 PVSS3

DPTX_VSSA DPTX_VSSA DPTX_VSSA DPTX_VSSA

VSS_RPLL

VSSA_TX

AVSS_LVRX_12

AVSS_OUT_LVRX

AVSS_OUT_LVRX AVSS_OUT_LVRX AVSS_OUT_LVRX AVSS_OUT_LVRX AVSS_OUT_LVRX AVSS_OUT_LVRX

1

2

1

2

CV244

0.1U_0402_25V6K~D CV224

0.1U_0402_25V6K~D CV241

1

2

A1 A14

F6 F7 F8 F9 G6 G7 G8 G9 H6 H7 H8 H9 J6 J7 J8 J9

D7 D8 E9 E10

A2

C5

K7

P1

F2 F13 H10 H5 K8 P14

0.1U_0402_25V6K~D

1

2

20mils

0.1U_0402_25V6K~D

CV225

0.1U_0402_25V6K~D

CV226

1

2

CV227

1

2

+3VS

10K_0402_5%~D

12

RV307

A A

Security Classification

2012/05/14 2013/05/13

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

5

4

3

2012/05/14 2013/05/13

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

LVDS to eDP-STDP4028

LA-9201P

1

29 66Tuesday, August 14, 2012

0.1

5

+3VS

1 2

RV327 2.2K_0402 _5%~D@

1 2

RV330 2.2K_0402 _5%~D@

VGA_DPD_AUXP/DDC

VGA_DPD_AUXN/DDC

PCH/GPU AUX&LANE SW for DPB

D D

GPU

1 2

VGA_DPD_P047 VGA_DPD_N047 VGA_DPD_P147 VGA_DPD_N147 VGA_DPD_P247 VGA_DPD_N247 VGA_DPD_P347 VGA_DPD_N347

CV247 0.1U_0402_10V6K~D

1 2

CV248 0.1U_0402_10V6K~D

1 2

CV249 0.1U_0402_10V6K~D

1 2

CV250 0.1U_0402_10V6K~D

1 2

CV251 0.1U_0402_10V6K~D

1 2

CV252 0.1U_0402_10V6K~D

1 2

CV253 0.1U_0402_10V6K~D

1 2

CV254 0.1U_0402_10V6K~D

VGA_DPD_SW_P0 VGA_DPD_SW_N0 VGA_DPD_SW_P1 VGA_DPD_SW_N1 VGA_DPD_SW_P2 VGA_DPD_SW_N2 VGA_DPD_SW_P3 VGA_DPD_SW_N3

UV21

44

IN1_D1n

45

IN1_D1p

47

IN1_D2n

48

IN1_D2p

1

IN1_D3n

2

IN1_D3p

4

IN1_D4n

5

IN1_D4p

4

+3VS

10U_0603_6.3V6M~D

CV245

2

1

2

6

VDD

31

VDD

25

PWDN_ASQ

CFG_HPD

DDCBUF

PRE_EMI

RTERM

28

40 34 7

DMC_PWDN

DMC_CFG_HPD

DMC_DDCBUF DMC_PRE_EMI

3

0.1U_0402_16V4Z~D

CV246

2

+3VS

1 2 1 2 1 2 1 2 1 2 1 2

12 12

PCH_DPD_CLK PCH_DPD_DAT DMC_PWDN DMC_CFG_HPD DMC_DDCBUF

DMC_PRE_EMI DMC_IN1_PEQ DMC_IN2_PEQ

DMC_PWDN

DMC_CFG_HPD

DMC_DDCBUF

DMC_PRE_EMI

DMC_IN1_PEQ

DMC_IN2_PEQ

RV30 2.2K_0402_5%~D RV31 2.2K_0402_5%~D RV324 4.7K_0402_5%~D@ RV325 4.7K_0402_5%~D@ RV326 4.7K_0402_5%~D RV328 4.7K_0402_5%~D@ RV329 4.7K_0402_5%~D RV331 4.7K_0402_5%~D

RV332 4.7K_0402_5%~D@ RV333 4.7K_0402_5%~D@ RV334 4.7K_0402_5%~D@ RV335 4.7K_0402_5%~D@ RV336 4.7K_0402_5%~D RV337 4.7K_0402_5%~D

1

1 2

CPU_DPD_DMC_P08 CPU_DPD_DMC_N08 CPU_DPD_DMC_P18 CPU_DPD_DMC_N18

CPU

C C

B B

CPU_DPD_DMC_P28 CPU_DPD_DMC_N28 CPU_DPD_DMC_P38 CPU_DPD_DMC_N38

VGA_DMC_HPD46

PCH_DMC_HPD15 VGA_DPD_AUXP/DDC47 VGA_DPD_AUXN/DDC47

PCH_DPD_CLK15

PCH_DPD_DAT15

MMST3904-7-F_SOT323-3~D

CV255 0.1U_0402 _16V4Z~D

1 2

CV256 0.1U_0402 _16V4Z~D

1 2

CV257 0.1U_0402 _16V4Z~D

1 2

CV258 0.1U_0402 _16V4Z~D

1 2

CV259 0.1U_0402 _10V7K~D

1 2

CV260 0.1U_0402 _10V7K~D

1 2

CV261 0.1U_0402 _10V7K~D

1 2

CV262 0.1U_0402 _10V7K~D

+3VS

C

DGPU_EDIDSEL#_R27 DGPU_SEL#27

E

3 1

10K_0402_5%~D

@

RV353

1 2

12 12

2

B

RV351 0_0402_5%~D

RV346 10K_0402_5%~D RV347 10K_0402_5%~D

QV21

@

DMC_SW_DETECT

DGPU_HPD_INT#19,27

RV350

@

200K_0402_5%

1 2

CPU_DPD_SW_P0 CPU_DPD_SW_N0 CPU_DPD_SW_P1 CPU_DPD_SW_N1 CPU_DPD_SW_P2 CPU_DPD_SW_N2 CPU_DPD_SW_P3 CPU_DPD_SW_N3

VGA_DMC_HPD_R PCH_DMC_HPD_R

DGPU_EDIDSEL#_R DGPU_SEL#

DMC_IN1_PEQ DMC_IN2_PEQ

2.2U_0603_6.3V6K~D

499_0402_1%~D

CV267

DGPU_HPD_INT#

12

RV348

1

2

CPU_DPD_SW_P0 CPU_DPD_SW_N0 CPU_DPD_SW_P1 CPU_DPD_SW_N1 CPU_DPD_SW_P2 CPU_DPD_SW_N2 CPU_DPD_SW_P3 CPU_DPD_SW_N3

PCH_DPD_CLK PCH_DPD_DAT

PCH_DMC_HPD DMC_SINK_HPD

200K_0402_5%

RV352

1 2

8

IN2_D1n

9

IN2_D1p

11

IN2_D2n

12

IN2_D2p

13

IN2_D3n

14

IN2_D3p

16

IN2_D4n

17

IN2_D4p

46

IN1_HPD

10

IN2_HPD

41

IN1_SCL

42

IN1_SDA

19

IN2_SCL

20

IN2_SDA

22

SW_DDC

21

SW_MAIN

3

IN1_PEQ

15

IN2_PEQ

23

CEXT

24

REXT

18

GND

43

GND

49

PAD

PS8271QFN48GTR-A1_QFN48_7X7

up@

1 2 1 2

RV634 0_0402_5 %~Den@

1 2

RV636 0_0402_5 %~Den@

1 2

RV638 0_0402_5 %~Den@

1 2

RV640 0_0402_5 %~Den@

1 2

RV642 0_0402_5 %~Den@

1 2

RV644 0_0402_5 %~Den@

1 2

RV646 0_0402_5 %~Den@ RV648 0_0402_5 %~Den@

1 2 1 2

RV650 0_0402_5 %~Den@ RV652 0_0402_5 %~Den@

1 2

RV675 0_0402_5 %~Den@

2

G

QV22

D

1 3

S

SSM3K7002F_SC59-3~D

DMC_SW_P0_R DMC_SW_N0_R DMC_SW_P1_R DMC_SW_N1_R DMC_SW_P2_R DMC_SW_N2_R DMC_SW_P3_R DMC_SW_N3_R

DMC_SW_SCL_R DMC_SW_SDA_R

MBK1608221YZF_2P

1 2

BAV99-7-F_SOT23-3

1

DV11

@

2

3

SEL0Y

1

LV29

+5VS

IN1

IN2

1 2 1 2

RV635 0_04 02_5%~De n@

1 2

RV637 0_04 02_5%~De n@

1 2

RV639 0_04 02_5%~De n@

1 2

RV641 0_04 02_5%~De n@

1 2

RV643 0_04 02_5%~De n@

1 2

RV645 0_04 02_5%~De n@

1 2

RV647 0_04 02_5%~De n@ RV649 0_04 02_5%~De n@

1 2 1 2

RV651 0_04 02_5%~De n@ RV653 0_04 02_5%~De n@

DMC_SINK_HPD

220P_0402_50V7K~D

CV269

1

2

36 35 33 32 30 29 27 26

39 38 37

DMC_SW_P0 DMC_SW_N0 DMC_SW_P1 DMC_SW_N1 DMC_SW_P2 DMC_SW_N2 DMC_SW_P3 DMC_SW_N3

DMC_SW_SCL DMC_SW_SDA

DMC_SW_P0 DMC_SW_N0 DMC_SW_P1 DMC_SW_N1 DMC_SW_P2 DMC_SW_N2 DMC_SW_P3 DMC_SW_N3

DMC_SW_DETECT DMC_SW_SCL DMC_SW_SDA

OUT_D1n OUT_D1p OUT_D2n OUT_D2p OUT_D3n OUT_D3p OUT_D4n OUT_D4p

OUT_HPD

OUT_SCL

OUT_SDA

+3VS

12

RV349 100K_0402_5%~D

DMC_OE#

1

D

2

G

QV23

SSM3K7002F_SC59-3~D

S

3

RV338 RV339 RV340 RV341 RV342 RV343 RV344 RV345

+HDMI_5V_OUT

RV366

1.5K_0402_5%

12

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

RV367

1.5K_0402_5%

12

0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D

DP_DMC_ML0P DP_DMC_ML0N DP_DMC_ML1P DP_DMC_ML1N DP_DMC_ML2P DP_DMC_ML2N DP_DMC_ML3P DP_DMC_ML3N

DP_DMC_HPD40

+3VS

1 2

RV61 4.7K_0402_5%~D

PS121 CFG0/ CFG1 SCLZ/SDAZ output voltage select; CFG1:0=00 LOW-level input voltage: <0.40V LOW-level output voltage: 0.60V PS121 PC0/PC1/PC2 Inputs equalization control, default inputs equalization setting at 12 dB 000: 12 dB, 001: 16 dB, 010: 10 dB, 011: 7 dB 100: 1.5 dB, 101: 4 dB, 110: 9 dB, 111: 7 dB

DP_DMC_ML0P DP_DMC_ML0N DP_DMC_ML1P DP_DMC_ML1N DP_DMC_ML2P DP_DMC_ML2N DP_DMC_ML3P DP_DMC_ML3N CPU_MXM_DMC_N1

DP_DMC_HPD

DMC_DDCBUF

DMC_OE#

CPU_MXM_DMC_AUXN CPU_MXM_DMC_AUXP

DMC_CFG1 DMC_CFG0

DMC_PC0 DMC_PC1

DMC_PC2

12

+3VS

Close to UV2 VCC pins

0.1U_0402_16V4Z~D

0.01U_0402_16V7K~D

1

CV263

2

+3VS

33

46

11

15

UV22

38

IN1p

39

IN1n

41

IN2p

42

IN2n

44

IN3p

45

IN3n

47

IN4p

48

IN4n

2

POW

30

HPD_SINK

26

I2C_CTL_EN#

32

NC/DDCBUF_EN#

25

NC/OE#

8

SDA

9

SCL

34

SDA_CTL/CFG1

35

SCL_CTL/CFG0

3

I2C_ADDR0/PC0

4

I2C_ADDR1/PC1

1

GND/PC2

12

6

RV62499_0402_1%~D

REXT

10

CV2682.2U_0402_ 6.3V6M~D

CEXT

21

VCC4

VCC540VCC6

VCC1

VCC2

VCC3

23 22 20 19 17 16 14 13

7

DMC_SINK_HPD

29 28

DMC_CFG1 DMC_CFG0 DMC_PC0 DMC_PC1 DMC_PC2 DMC_SW_SDA DMC_SW_SCL

DMC_CFG1 DMC_CFG0 DMC_PC0 DMC_PC1 DMC_PC2

CPU_MXM_DMC_P0 CPU_MXM_DMC_N0 CPU_MXM_DMC_P1

CPU_MXM_DMC_P2 CPU_MXM_DMC_N2 CPU_MXM_DMC_P3 CPU_MXM_DMC_N3

DMC_SW_SDA DMC_SW_SCL

OUT1p OUT1n OUT2p OUT2n OUT3p OUT3n OUT4p OUT4n

HPD

SDAZ SCLZ

GND7

GND424GND631GND5

GND3

GND15GND2

12

GND837GND9

GND10

PS121QFN48G_QFN48_7X7

36

27

18

12

RV3544.7K_0402_5%~D @

12

RV3554.7K_0402_5%~D @

12

RV3564.7K_0402_5%~D

12

RV3574.7K_0402_5%~D @

12

RV3584.7K_0402_5%~D

12

RV3592.2K_0402_5%~D

12

RV3602.2K_0402_5%~D

12

RV3614.7K_0402_5%~D @

12

RV3624.7K_0402_5%~D @

12

RV3634.7K_0402_5%~D @

12

RV3644.7K_0402_5%~D @

12

RV3654.7K_0402_5%~D @

43

49

2

CPU_MXM_DMC_P0 40 CPU_MXM_DMC_N0 40 CPU_MXM_DMC_P1 40 CPU_MXM_DMC_N1 40 CPU_MXM_DMC_P2 40 CPU_MXM_DMC_N2 40 CPU_MXM_DMC_P3 40 CPU_MXM_DMC_N3 40

+3VS

0.01U_0402_16V7K~D

0.1U_0402_16V4Z~D

1

CV264

2

CV266

CV265

2

A A

CPU_MXM_DMC_AUXN

CPU_MXM_DMC_AUXP

5

4

3

CPU_MXM_DMC_AUXN 40 CPU_MXM_DMC_AUXP 40

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

接接

DMC CONN

Compal Secret Data

2012/05/14 2013/05/13

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

DP SW for DMC

LA-9201P

1

30 66Wednesday, August 15, 2012

0.1

5

+3VS +3VS_CR

RR12

4

1 2

0_0805_5%~D

3

2

1

Need change to 8229

D D

PCIE_PTX_CARDRX_P418

PCIE_PTX_CARDRX_N418

CLK_PCIE_CD16

CLK_PCIE_CD#16

PCIE_PRX_CARDTX_P418

PCIE_PRX_CARDTX_N418

10U_0603_6.3V6M~D

Removed CR17

C C

Zdiff = 100 ohm

CR10

CR15

1 2

SD_CLK_R

22P_0402_50V8C~D

Reserved

1 2

CR7 0.1U_0402_10V7K~D

1 2

CR8 0.1U_0402_10V7K~D

+ODR_PWR

1

12

CR11

0.1U_0402_10V7K~D

2

SD_D1_R SD_D1

SD_D0_R SD_D0

1

CR13

2

1 2

RR3 47_0402_5%~D

1 2

RR4 47_0402_5%~D

1 2

RR5 47_0402_5%~D

1 2

RR6 47_0402_5%~D

1 2

RR7 47_0402_5%~D

CR6 4.7U_0603_6.3V6K~D

1 2

PCIE_PRX_CARDTX_P4_C

PCIE_PRX_CARDTX_N4_C

1 2

CR9 0.1U_0402_10V7K~D

DV33_18

0.1U_0402_10V7K~D

AV12

DV12

+3VS_CR

SD_CLK

SD_CMDSD_CMD_R

SD_D3SD_D3_R

1

HSIP

2

HSIN

3

REFCLKP

4

REFCLKN

5

AV12

6

HSOP

7

HSON

8

GND

9

DV12

10

Card1_3V3

11

3V3_IN

12

Card2_3V3

13

XD_CD#

14

DV33_18

15

GND

16

SP1

17

SP2

18

SP3

19

SP4

20

SD_D1

21

SD_D0

22

SD_CLK

23

SD_CMD

24

SD_D3

RTS5209-GR_LQFP48_7X7

UR1

RREF

3V3_IN

CLK_REQ#

PERST#

EEDO

EECS

EESK

GPIO/EEDI

MS_INS#

SD_CD#

SP15

SP14

SP13

SP12

SP11

SP10

SP9

SP8

SP7

SP6

SP5

DV12_S

GND

SD_D2

48

RREF

47

46

45

44

43

42

41

40

MS_INS#

39

SD_CD#

38

SP15_SDWP_XDD7

37

SP14_MSCLK_XDD6

36

35

34

33

SP10_MSD2_XDD2

32

31

30

29

28

SP5_MSBS_XDCLE

27

26

25

RR11

6.2K_0402_1%~D

SP12_MSD3_XDD4

SP9_MSD0_XDD1

SP7_MSD1_XDWP#

DV12_S

SD_D2 SD_D2_R

+3VS_CR

12

CDCLK_REQ# 16

PLT_RST# 6,15,32,33,40

1 2

RR2 47_0402_5%~D

1 2

CR16

SP14_MSCLK_XDD6_R

CR14

1 2

4.7U_0603_6.3V6K~D

0.1U_0402_10V7K~D

1 2

RR8 0_0402_5%~D

CR1

12

0.1U_0402_10V7K~D

1

CR12 22P_0402_50V8C~D

2

+ODR_PWR

12

RR1

For ver:ES2-B0

1

CR2

CR3

2

10K_0402_5%~D

0.1U_0402_10V7K~D

Place CR3 close to socket pin 11

Place CR4 close to socket pin 11

Place CR5 close to socket pin 4

Place CR6 close to socket pin 4

12

10U_0603_6.3V6M~D

CR4

CR5

2

0.1U_0402_10V7K~D

1

+ODR_PWR

JREAD1

SD_D2_R

SD_D3_R

SP14_MSCLK_XDD6_R SD_CMD_R

B B

Reserve for EMI please close to JREAD1

@

SP14_MSCLK_XDD6_R

A A

1 2

RR10 33_0402_5%

SD_CLK_R

1

CR18 22P_0402_50V8J~D@

2

Reserve for EMI please close to JREAD1

@

1 2

RR9 33_0402_5%

@

12

CR17

22P_0402_50V8J~D

SP12_MSD3_XDD4 MS_INS#

SP10_MSD2_XDD2

SP9_MSD0_XDD1 SP7_MSD1_XDWP# SD_CLK_R SP5_MSBS_XDCLE

SD_D0_R SD_D1_R SD_CD#

SP15_SDWP_XDD7

1

SD-DAT2

2

MS-VSS1

3

SD-CD/DAT3 MMC-RSV

4

MS-VCC

5

MS-SCLK

6

SD-CMD MMC-CMD

7

MS-DATA3

8

MS-INS

9

SD-VSS MMC-VSS1

10

MS-DATA2

11

SD-VDD MMC-VDD

12

MS-DATA0

13

MS-DATA1

14

SD-CLK MMC-CLK

15

MS-BS

16

MS-VSS2

17

SD-VSS MMC-VSS2

18

SD-DAT0 MMC-DAT

19

SD-DAT1

20

SD-CD

21

SD-GND

22

SD-WP(SW)

T-SOL_143-1300302601

CONN@

GND1 GND2

23 24

Security Classification

2011/06/02 2012/06/02

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2011/06/02 2012/06/02

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Card Reader RTS5209

LA-9201P

1

31 66Monday, August 20, 2012

0.1

5

4

3

2

1

+3VS

1 2

RE36 10K_0402_5%~D

1 2

RE38 10K_0402_5%~D

1 2

RE42 10K_0402_5%~D

1 2

RE43 2.2K_0402_5%~D

1 2

RE45 2.2K_0402_5%~D

+3VALW_EC

1 2

RE46 2.2K_0402_5%~D

1 2

D D

C C

B B

USBCHG_DET#41

A A

RE48 2.2K_0402_5%~D

1 2

RE51 10K_0402_5%~D

1 2

RE52 1K_0402_1%~D@

1 2

RE53 10K_0402_5%~D

1 2

RE54 4.7K_0402_5%~D

1 2

RE57 4.7K_0402_5%~D

1 2

RE58 10K_0402_5%~D RE59 10K_0402_5%~D RE60 10K_0402_5%~D@ RE69 10K_0402_5%~D

EC_ESB_CLK

12 1 2 1 2

1 2

RE61 0_0402_5%~ D

KSI[0..7]42

KSO[0..17]42

1 2

KSI0

1 2

KSI1

RE90 0_0402_5%~ D

1 2

KSI2

RE91 0_0402_5%~ D

1 2

KSI3

RE92 0_0402_5%~ D

1 2

KSI4

RE93 0_0402_5%~ D

1 2

KSI5

RE94 0_0402_5%~ D

1 2

KSI6

RE95 0_0402_5%~ D

1 2

KSI7

RE96 0_0402_5%~ D

1 2

KSO0

RE97 0_0402_5%~ D

1 2

KSO1

RE98 0_0402_5%~ D

1 2

KSO2

RE99 0_0402_5%~ D

1 2

KSO3

RE100 0_0402_ 5%~D

1 2

KSO4

RE101 0_0402_ 5%~D

1 2

KSO5

RE102 0_0402_ 5%~D

1 2

KSO6

RE103 0_0402_ 5%~D

1 2

KSO7

RE104 0_0402_ 5%~D

1 2

KSO8

RE105 0_0402_ 5%~D

1 2

KSO9

RE106 0_0402_ 5%~D

1 2

KSO10

RE107 0_0402_ 5%~D

1 2

KSO11

RE108 0_0402_ 5%~D

1 2

KSO12

RE109 0_0402_ 5%~D

1 2

KSO13

RE110 0_0402_ 5%~D

1 2

KSO14

RE111 0_0402_ 5%~D

1 2

KSO15 KSO15_EC

RE112 0_0402_ 5%~D

1 2

KSO16

RE113 0_0402_ 5%~D

1 2

KSO17

RE114 0_0402_ 5%~D RE115 0_0402_ 5%~D

H_PROCHOT#

1

1 2

RE89 0_0402_5%~D

1

D

2

H_PROCHOT#_EC

G

S

QE322

3

SSM3K7002F_SC59-3~D

DE83 BAT54CW_SOT323-3

3

2

BKOFF# EC_SCI# M_THERMAL# EC_SMB_CK2 EC_SMB_DA2

EC_SMB_CK1 EC_SMB_DA1

EC_MUTE# EC_SMI# DEPOP# EC_ESB_CLK EC_ESB_DAT LID_SW_IN# EN_WOL# EAPD#_R PCIE_WAKE#_EC

EC_ESB_CLK_R

KSI[0..7]

KSO[0..17]

RE85 10K_0402_5%~D

Check Voltage

12

RE87 100K_0402_5%~D

USBCHG_DET_PWR_EN#

RE88 150K_0402_1%~D

1 2

KSI0_EC KSI1_EC KSI2_EC KSI3_EC KSI4_EC KSI5_EC KSI6_EC KSI7_EC KSO0_EC KSO1_EC KSO2_EC KSO3_EC KSO4_EC KSO5_EC KSO6_EC KSO7_EC KSO8_EC KSO9_EC KSO10_EC KSO11_EC KSO12_EC KSO13_EC KSO14_EC

KSO16_EC KSO17_EC

VR_HOT# 61H_PROCHOT#6,63

1 2

+3VALW

1 2

RE37 0_0805_5%

+3VALW_EC +3VALW_EC

47K_0402_5%~D

RE55

1 2

EC_RST# RST#

0.1U_0402_16V4Z~D

CE43

1

2

EC_SMB_CK2_R28

EC_SMB_DA2_R28

47K_0402_5%~D

12

2

1

12

EC_SMB_CK156,63

EC_SMB_DA156,63

PM_SLP_S3#15,36 PM_SLP_S5#15,36

FOR NV

+3VALW_EC

USBCHG_DET_EC#

+3VLPVL

RE86 100K_0402_5%~D

1 2

13

D

2

G

S

USBCHG_DET_D 57

QE321 SSM3K7002FU_SC70-3~D

0.1U_0402_16V7K

1

CE35

2

0.1U_0402_16V7K

RE56

.1U_0402_16V7K~D

CE44

CLK_PCI_LPC

RE66

@

33_0402_5%~D

22P_0402_50V8J~D

1

@

CE45

2

Reserve for EMI please close to U36

1 2

RE75 0_0402_5%~D

1 2

RE76 0_0402_5%~D

EC_SMB_CK217,42,43,46

EC_SMB_DA217,42,43,46

1 2

RE77 0_0402_5%~D

1 2

RE78 0_0402_5%~D

EC_SMI#19

PS_ID56

SUSPWRDNACK15

SYSTEM_FAN_FB43

E51TXD_P80DATA39

E51RXD_P80CLK39

PCH_PWROK15

WLES ON/OFF LED#37

SG_AMD_BKL15,24

GC6_EVENT#46

DGPU_GC6_EN5 0

RE119 10K_0402_5%~D

接接

EC Pin

LPC_FRAME#17,40

LPC_AD317,40 LPC_AD217,40 LPC_AD117,40 LPC_AD017,40

CLK_PCI_LPC16

PLT_RST#6,15,3 1,33,40

1

CE31

2

0.1U_0402_16V7K

GATEA2019 KB_RST#19 SERIRQ17

EC_SCI#19

ACOFF63

0.1U_0402_16V7K

1

CE32

2

GATEA20 KB_RST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

CLK_PCI_LPC PLT_RST# EC_RST# EC_SCI# ACOFF

KSI0_EC KSI1_EC KSI2_EC KSI3_EC KSI4_EC KSI5_EC KSI6_EC KSI7_EC KSO0_EC KSO1_EC KSO2_EC KSO3_EC KSO4_EC KSO5_EC KSO6_EC KSO7_EC KSO8_EC KSO9_EC KSO10_EC KSO11_EC KSO12_EC KSO13_EC KSO14_EC KSO15_EC KSO16_EC KSO17_EC

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

PM_SLP_S3#_R

PM_SLP_S5#_R EC_SMI# PS_ID EC_ESB_CLK_R EC_ESB_DAT SUSPWRDNACK

SYSTEM_FAN_FB

E51TXD_P80DATA E51RXD_P80CLK PCH_PWROK WLES ON/OFF LED# SG_AMD_BKL

GC6_EVENT# DGPU_GC6_EN

12

PCH_PWROK

1

CE34

2

1000P_0402_50V7K

2

CE37

1

UE1

1

GATEA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ

4

LPC_FRAME#

5

LPC_AD3

7

LPC_AD2

8

LPC_AD1

10

LPC_AD0

12

CLK_PCI_EC

13

PCIRST#/GPIO05

37

EC_RST#

20

EC_SCII#/GPIO0E

38

GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

EC_SMB_CK1/GPIO44

78

EC_SMB_DA1/GPIO45

79

EC_SMB_CK2/GPIO46

80

EC_SMB_DA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

GPIO0A

17

GPIO0B

18

GPIO0C

19

GPIO0D

25

EC_INVT_PWM/GPIO11

28

FAN_SPEED1/GPIO14

29

EC_PME#/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

PCH_PWROK/GPIO18

34

SUSP_LED#/GPIO19

36

NUM_LED#/GPIO1A

122

XCLKI/GPIO5D

123

XCLKO/GPIO5E

LE3 FBMA-L11-160808-800LMT_060 3

+3VALW_EC +EC_VCCA

CE36

1000P_0402_50V7K

LPC & MISC

1 2

9

22

33

96

EC_VDD/VCC

PWM Output

RE44

@

0_0402_5%

1 2

67

111

125

EC_VDD0

EC_VDD/VCC

EC_VDD/AVCC

BATT_TEMP/AD0/GPIO38

AD Input

DA Output

PS2 Interface

Int. K/B Matrix

CPU1.5V_S3_GATE/GPXIOA00

SPI Device Interface

SPI Flash ROM

PECI_KB930/AD7/GPIO41

BATT_CHG_LED#/GPIO52

GPIO

SM Bus

BATT_LOW_LED#/GPIO55

EC_RSMRST#/GPXIOA03 EC_LID_OUT#/GPXIOA04

PROCHOT_IN/GPXIOA05

H_PROCHOT#_EC/GPXIOA06

VCOUT0_PH/GPXIOA07

GPO

GPIO

PBTN_OUT#/GPXIOA09

PCH_APWROK/GPXIOA10

SA_PGOOD/GPXIOA11

GPI

PECI_KB9012/GPXIOD07

GND/GND

AGND/AGND

GND/GND

GND0

11

24

35

69

94

113

ECAGND

1 2

1

0.1U_0402_16V7K CE33

ECAGND

2

1 2

RE47 0_0402_5%~D

Reserved for KB9012

21

GPIO0F

BEEP#/GPIO10

ACOFF/GPIO13

AD1/GPIO39

ADP_I/AD2/GPIO3A

AD3/GPIO3B AD4/GPIO42

IMON/AD5/GPIO43

DAC_BRIG/GPIO3C

EN_DFAN1/GPIO3D

IREF/GPIO3E

CHGVADJ/GPIO3F

EC_MUTE#/GPIO4A

USB_EN#/GPIO4B

CAP_INT#/GPIO4C

EAPD/GPIO4D

TP_CLK/GPIO4E

TP_DATA/GPIO4F

WOL_EN/GPXIOA01

ME_EN/GPXIOA02

VCIN0_PH/GPXIOD00

SPIDI/GPIO5B

SPIDO/GPIO5C

SPICLK/GPIO58

SPICS#/GPIO5A

ENBKL/AD6/GPIO40

FSTCHG/GPIO50

CAPS_LED#/GPIO53

PWR_LED#/GPIO54

SYSON/GPIO56 VR_ON/GPIO57

PM_SLP_S4#/GPIO59

BKOFF#/GPXIOA08

AC_IN/GPXIOD01

EC_ON/GPXIOD02

ON/OFF/GPXIOD03

LID_SW#/GPXIOD04

SUSP#/GPXIOD05

GPXIOD06

20mil

KB9012QF-A3_LQFP128_14X14

LE44 FBMA-L11-160808-800LMT_060 3

23 26

GPIO12

27

63 64 65 66 75 76

68 70 71 72

83 84 85 86 87 88

97 98 99 109

119 120 126 128

73 74 89 90 91 92 93 95 121 127

100 101 102 103 104 105 106 107 108

110 112 114 115 116 117 118

124

V18R

ECAGND 56

FOR NV

+3VLP

EN_TPLED# BEEP# SYSTEM_FAN_PWM

BATT_TEMP EAPD#_R ADP_I AD_BID0 USBCHG_DET_EC# ENBKL

RE68 0_0402_5%~D

M_THERMAL# EC_ENVDD LCD_TEST

EC_MUTE# IMVP_PWRGD LCD_BKL_EN EC_LID_OUT# TP_CLK TP_DATA

CPU1.5V_S3_GATE EN_WOL# HDA_SDO VCIN0_PH

PWRSHARE_EN_EC# PWRSHARE_OE# VPK_EN 3V_F347_ON

KB_DET#_EC PCIE_WAKE#_EC PCH_DPWROK BATT_CHG_LED# CAPS_LED# Power_LED_R# BATT_LOW_LED# SYSON IMVP_VR_ON PM_SLP_S4#_R

PCH_RSMRST# PCH_ENVDD VCIN1_PH H_PROCHOT#_EC VCOUT0_PH# BKOFF# PBTN_OUT# PCH_PWR_EN VPK_DET#

ACIN EC_ON ON/OFF LID_SW_IN# SUSP# USB_PWR_EN# EC_PECI

+V18R

12

VCIN0_PH 56

VPK_EN 42

RE79 0_0402_5%~ D RE82 0_0402_5%~ D

PCH_DPWROK 15

RE123 0_0402_ 5%~D

RE81 0_0402_5%~ D

PCH_ENVDD 15,24 VCIN1_PH 56

VCOUT0_PH# 57

VPK_DET# 42

CE47 100P_0 402_50V8J~D

1

4.7U_0805_10V4Z~D

1

2

CE51 47P_0402_50V8J@

CE48

2

HDMI_TOGGLE2 8

HDMI_IN_SELECT#24,25

HDMI_IN_CAB_DET#28

DGPU_PWR_EN46,49,50,62

DGPU_PWROK23,4 9

DGPU_HOLD_RST#46

HDMI_IN_OUT_DDC26

EN_TPLED# 37 BEEP# 34 SYSTEM_FAN_PWM 4 3

CE42 100P_0 402_50V8J~D

RE63 0_0402_5%~D@

ADP_I 56,63

ENBKL 24

M_THERMAL# 12,13 EC_ENVDD 25 LCD_TEST 25

EC_MUTE# 34 IMVP_PWRGD 6,15,61

LCD_BKL_EN 25 EC_LID_OUT# 17 TP_CLK 42

TP_DATA 42

CPU1.5V_S3_GATE 10 EN_WOL# 33

HDA_SDO 14

PWRSHARE_EN_EC# 41 PWRSHARE_OE# 41

3V_F347_ON 36

1 2 1 2

BATT_CHG_LED# 36 CAPS_LED# 37

1 2

BATT_LOW_LED# 36 SYSON 45,58,59 IMVP_VR_ON 61

1 2

PCH_RSMRST# 15

BKOFF# 25 PBTN_OUT# 6,15

PCH_PWR_EN 26,45

12

RE74 43_0402_1%

Please place RE74 close to EC with in 750mil

RE64 0_0402_5%~D

ODD_EJECT# 39

EC_ON 57

ON/OFF 44

LID_SW_IN# 17 ,36,37

SUSP# 10,45,58,60

USB_PWR_EN# 41,42

1 2

EC_ESB_CLK

RST#

EC_ESB_DAT

DEPOP#_EC

HDMI_IN_SELECT#

HDMI_IN_CAB_DET#

DGPU_PWR_EN

DGPU_PWROK

DGPU_HOLD_RST#

HDMI_IN_OUT_DDC

12

ECAGND

12 12

KB_DET# 42

PCIE_WAKE# 15,33,40

Power_LED# 37

PM_SLP_S4# 15

ACIN 1 5,36,56,63

H_PECI 6,19

UE2

1

ESB_CLK

2

GPIO00

3

RST#

4

ESB_DAT

5

GPIO01

6

GPIO02

7

GPIO03

8

GPIO04

9

GPIO05

10

GPIO06

11

GPIO07/CAS_CLK

12

GND

KC3810_QFN24_4X4

EC_ESB_CLK

RE40

@

33_0402_5%~D

22P_0402_50V8J~D

1 2

@

CE39

1

2

Reserve for EMI please close to U35

BATT_TEMP 56,63 PM_SLP_SUS# 15 EAPD# 34

DEPOP#_EC

GPIO08/CAS_DAT

GPIO10/ESB_RUN#

GPIO11/BaseAddOpt

0_0402_5%~D

1 2

10K_0402_5%~D

@

1 2

TEST_EN#

GPIO09

GPIO0A

GPIO0B

GPIO0C/PWM0

GPIO0D/PWM1

GPIO0E/PWM2

GPIO0F/PWM3

VCC

GND

25

RE62

DEPOP#

1

D

2

G

S

RE65

3

BOARD ID Table

Board ID

*

13

14

HDMI_IN_OUT_HPD_R

15

HDMI_SW_R

16

17

18

EC_INV_PWM

19

HDMI_IN_EN_R

20

21

22

23

24

TP_CLK

TP_DATA

DEPOP# 34

QE21

@

SSM3K7002F_SC59-3~D

Board ID

+3VALW_EC

RE67 100K_0402_5%~D

Ra

1 2

RE70 0_0402_5%

Rb

1 2

PCB Revision

0.1 (SSI)

0

0.2 (PT)

1

0.3 (ST)

2

0.4 (QT)

3

1.0 (MP)

4 5 6 7

RE120 0_04 02_5%~D

RE121 0_04 02_5%~D

HDMI_OUT_EN 26

1 2

RE122 0_0402_ 5%~D

VGA_AC_DET

EN_CAM

+3VALW_EC

0.1U_0402_16V4Z~D

60 mil

CE50

1

2

AD_BID0

1

CE46

0.1U_0402_16V4Z~D

2

8.2K +/- 5%

18K +/- 5%

33K +/- 5%

56K +/- 5%

100K +/- 5%

1 2

EC_INV_PWM 24

VGA_AC_DET 46

EN_CAM 25

Rb

+5VS

12

RE354.7K_0402_5 %~D

12

RE414.7K_0402_5 %~D

0

HDMI_IN_OUT_HPD 26

HDMI_SW 26

FOR HDMI

HDMI_IN_EN 28

GPU

要要

AC_BATT

Security Classification

2012/05/14 2013/05/13

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

5

4

3

2012/05/14 2013/05/13

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

EC ENE-KB9012QF,KC3810

LA-9201P

1

32 66Tuesday, August 21, 2012

0.1

5

+LAN_IO

12

RL7 0_0402_5%~D

12

D D

4.7K_0402_5%~D

RL10

RL11

RL15

@

PLT_RST#

12

PCIE_WAKE#

12

CLKREQ_LAN#_R

The pull-up resisters might not be necessory due to existence on PCH side.

4

12

PCIE_PRX_GLANTX_P1_C

12

PCIE_PRX_GLANTX_N1_C

PCIE_PTX_GLANRX_P1

PCIE_PTX_GLANRX_N1

CLK_PCIE_LAN

CLK_PCIE_LAN#

12

CLKREQ_LAN#_R

PLT_RST#

PCIE_WAKE#

RL13 30K_0402_5%

1 2

RL29

5.1K_0402_1%~D

RL28

PCIE_PRX_GLANTX_P118

PCIE_PRX_GLANTX_N118

PCIE_PTX_GLANRX_P118

PCIE_PTX_GLANRX_N118

CLK_PCIE_LAN16

CLK_PCIE_LAN#1 6

LANCLK_REQ#16

PLT_RST#6,15,31,32,40

PCIE_WAKE#15,32,40

4

12

GND2GND

0_0402_5%

OSC1OSC

YL1

3

CL51

25MHZ_10PF_7V25000014

CL52

2

1

15P_0402_50V8J~D

CL1 0.1U_ 0402_16V7K~D

CL4 0.1U_ 0402_16V7K~D

RL12 0_0402_5%~D

+LAN_IO

2

1

15P_0402_50V8J~D

3

UL1

30

TX_P

29

TX_N

35

RX_P

36

RX_N

33

REFCLK_P

32

REFCLK_N

4

CLKREQ#

2

PERST#

3

WAKE#

25

SMCLK

26

SMDATA

28

NC

27

TESTMODE

41

GND

XTLI XTLO

LAN_ACTIVITY# +RBIAS LAN_LINK#_R LAN_LED2#_R

8

XTLI

7

XTLO

5

ISOLAT#

38

LED_0

39

LED_1

23

LED_2

S IC E2201-BL3A-R QFN 40P E-LAN CTRL

AVDDL_REG

AVDDH_REG

DVDDL_REG

VDD33

AVDD33

AVDDL AVDDL AVDDL AVDDL

AVDDH

TRXP0 TRXN0 TRXP1 TRXN1 TRXP2 TRXN2 TRXP3 TRXN3

PPS

RBIAS

1 16

13 19 31 34 6

22 9

37

11

LAN_MDIP0

12

LAN_MDIN0

14

LAN_MDIP1

15

LAN_MDIN1

17

LAN_MDIP2

18

LAN_MDIN2

20

LAN_MDIP3

21

LAN_MDIN3

40

LX

24

10

W=40mils

+LAN_IO

+AVDDL

+AVDDH

+DVDDL

1 2

RL14

2.37K_0402_1%~D

2

1

C C

1U_0402_6.3V6K~D

+3VALW

RL18

10K_0402_5%~D

EN_WOL#32

B B

A A

B+_BIAS

1 2

13

D

2

G

S

W=40mils

CL20

RL17 470K_0402_5%~D

EN_WOL

QL2 SSM3K7002FU_SC70-3

+3VALW

1

2

QL1 FDC655BN_NL_SSOT6~D

D

6

2 1

RL19

+VDDCT_L

2

1

CL42

CL43

@

1

2

1000P_0402_50V7K~D

W=40mils

S

45

+LAN_IO_R

G

3

1 2

1.5M_0402_5%~D

LAN_MDIP3 LAN_MDIN3

LAN_MDIP2 LAN_MDIN2

LAN_MDIP1 LAN_MDIN1

LAN_MDIP0 LAN_MDIN0

TIMAG: S X'FORM_ IH-160 LAN , SP050006F00

BOTHHAND: S X'FORM_ GST5009-D LF LAN,SP050006B00

1

2

CL45

CL44

@

2

1

0.1U_0402_16V7K~D 1000P_0402_50V7K~D

1 2

RL16

0_0805_5%~D

1

CL36

0.1U_0402_25V6

2

TL1

1

TCT1

MCT1

2

TD1+

MX1+

3

TD1-

4

TCT2

MCT2

5

TD2+

MX2+

6

TD2-

7

TCT3

MCT3

8

TD3+

MX3+

9

TD3-

10

TCT4

11 12

MCT4

TD4+

MX4+

TD4-

350UH_GST5009-CLF

2

CL46

@

1

0.1U_0402_16V7K~D 1000P_0402_50V7K~D

MX1-

MX2-

MX3-

MX4-

+LAN_IO

1

CL21

2

24

RJ45_CT3

23

RJ45_MDI3+

22

RJ45_MDI3-

21

RJ45_CT2

20

RJ45_MDI2+

19

RJ45_MDI2-

18

RJ45_CT1

17

RJ45_MDI1+

16

RJ45_MDI1-

15

RJ45_CT0

14

RJ45_MDI0+

13

RJ45_MDI0-

2

1

CL48

CL47

@

1

2

0.1U_0402_16V7K~D 1000P_0402_50V7K~D

1

CL22

2

1000P_0402_50V7K~D

1

CL49

2

0.1U_0402_16V7K~D

1A

1

CL23

2

0.1U_0402_16V7K~D 1U_0402_6.3V6K~D

close to Pin 1

RL22

1 2

75_0402_1%~D

RL23

1 2

75_0402_1%~D

RL25

1 2

75_0402_1%~D

RL27

1 2

75_0402_1%~D

CL24

1

CL25

2

10U_0603_6.3V6M~D

2

CL40

1000P_1808_3KV7K~D

1

CL50

2

10U_0603_6.3V6M~D

1

2

1

CL41

2

0.1U_0402_16V7K~D

close to Pin 16

W=20milsW=20mils

close to Lan pin31

1

CL35

1U_0402_6.3V6K~D

2

1U_0402_6.3V6K~D

1

CL28

1

CL53

CL29

2

0.1U_0402_16V7K~D

1

CL54

2

1U_0402_6.3V6K~D

1

CL30

2

4.7U_0603_6.3V6K~D

0.1U_0402_16V7K~D

close to Lan pin34 close to Lan pin6

close to Lan pin13

+LAN_IO

LAN_LED2#_R

RL30

1K_0402_1%~D

1 2

+LAN_IO

LAN_LINK#_R

+LAN_IO

QL3 2N7002_SOT23

D

S

13

G

2

close to Lan pin19

1

CL31

2

RL26 330_0402_5%

CL38 470P_0402_50V7K

1 2

CL37 470P_0402_50V7K

RL21 130_04 02_1%~D

RL20 470_04 02_5%~D

1

CL32

2

0.1U_0402_16V7K~D

12

LAN_ACTIVITY#

RJ45_MDI3-

RJ45_MDI3+

RJ45_MDI1-

RJ45_MDI2-

RJ45_MDI2+

RJ45_MDI1+

RJ45_MDI0-

RJ45_MDI0+

12

LAN_LINK#

LAN_LED2#

RL24 0_0402_5%~D

12

+AVDDH+AVDDL +DVDDL

CL33

0.1U_0402_16V7K~D

2

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D

1

CL26

close to Lan pin9

OK

JLAN1

9

Yellow LED+

10

Yellow LED-

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

11

Green LED-

13

Orange LED-

12

Green-Orange LED+

SUYIN_100073HR013M25DZL

CONN@

1

CL34

2

0.1U_0402_16V7K~D

close to Lan pin22

14

GND

15

GND

W=20mils

1

CL27

CL39

2

1U_0402_6.3V6K~D

close to Lan pin37

1

2

0.1U_0402_16V7K~D

Security Classification

2012/05/14 2013/05/13

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2012/05/14 2013/05/13

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

GLAN AR8151 AL1A/ RJ45

LA-9201P

1

33 66Tu esday, August 14, 2012

0.1

A

+3VS

RA1 0_0805_5%~D

1 1

2 2

+3.3V_DVDD

FBMA-L11-201209-221LMA3 0T_0805

+3.3V_DVDD

1 2

0.1U_0402_10V6K~D

12

LA1

1 2

CA137 0.1U_0402 _10V6K~D

1 2

CA138 0.1U_0402 _10V6K~D

1 2

CA139 0.1U_0402 _10V6K~D

1 2

CA140 0.1U_0402 _10V6K~D

1 2

RA49 0_0402_5%~D

1 2

RA50 0_0402_5%~D

1 2

RA52 0_0402_5%~D

1 2

RA53 0_0402_5%~D

PCH_AZ_CODEC_SDIN014

RA14

CA104

2

CA105

1

PCH_AZ_CODEC_SDOUT14

PCH_AZ_CODEC_BITCLK14

PCH_AZ_CODEC_SYNC14

PCH_AZ_CODEC_RST#14

20K_0402_1%~D

12

10U_0805_10V4Z~D

1

2

1

CA17

2

10U_0805_10V4Z~D

+3.3V_DVDD

+5VS

+3.3V_DVDD

0.1U_0402_10V6K~D

2

CA18

1

CA10

2.2U_0402_6.3V6M~D

AGNDGND

+3.3V_DVDD

0.1U_0402_10V6K~D

CA27

1

3 3

2

HDMI_IN_AUDIO_CODEC28

Need double check this pin

4 4

0.1U_0402_10V6K~D

CA28

CA29

1

2

BEEP#32

HDA_SPKR14

CA30

1

2

1 2

CA38 0.1U_04 02_16V4Z~D

1 2

CA39 0.1U_04 02_16V4Z~D

1 2

CA36 0.1U_0402_10V6K~D

10U_0603_6.3V6M~D

1

2

+3.3V_AVDD

CA31

BEEP_C#

PCH_SPKR_C

1

2

B

Close to Pin39

0.1U_0402_10V6K~D

2

1

RA6

RA8 0_0402_5%~D

MIC2-VREFO-L LINE2-VREFO MIC2-VREFO-R

2

CA19

1

0.1U_0402_10V6K~D

CA59

4.7U_0805_25V6-K

2

12

CA100

CA99

1

10U_0805_10V4Z~D

0.1U_0402_10V6K~D

1

CA101

0.1U_0402_10V6K~D

CA11

1 2

1

2

Reserved Resistor(unknown)

2

CA102

2

1

0.1U_0402_10V6K~D

4.7U_0805_25V6-K

CA12

2

12

1

1 2

22_0402_5%

1 2

CA16 1U_0402_6.3V6K~D

1

CA20

100U_B3_6.3VM_R45M

+

2

0.1U_0402_10V6K~D

CA37

1 2

RA59

100K_0402_5%~D

1 2

RA61

100K_0402_5%~D

1 2

RA63

100K_0402_5%~D

CA22

1

2

1

2

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

CA15

CA35

2

1

10U_0805_10V4Z~D

CA23

1

2

23 39

11

25

22P_0402_50V8J~D

29 30

24 21 35 40 41 38

20 10

28 22 42

49

7

8 4 5 9 6

1

0_0402_5%~D

1 2

C

UA8

2

HVDD LDO-IN

DVDD DVDD-IO DVDD-IO-CP

SDATA-IN SDATA-OUT BCLK SYNC RESETB

MIC2-VREFO LINE2-VREFO MIC1-VREFO

CBP CBN JDREF LDO-CAP VREF VRP

CPVEE REGREF

CPVREF AVSS1 AVSS2

Thermal PAD

ALC3661-CG_MQFN48_6X6~D

Place under codec

1 2

RA26 0_0805_5%~D

1 2

RA29 0_0805_5%~D

1 2

RA32 0_0805_5%~D

1 2

RA33 0_0805_5%~D

PCBEEP

LINE1-R

LINE1-L

LINE2-IN-R/SLEEVE

LINE2-IN-L/RING2

MIC1-R

MIC1-L/MIC-CAP

MIC2-R

MIC2-L

SENSE A SENSE B

SURR-R

SURR-L

CEN

LFE

FRONT-R

FRONT-L

SPDIF-OUT

SPDIF-in

GPIO/DMIC-CLK

GPIO1/DMIC-DATA GPIO2/Combo-Jack1 GPIO3/Combo-Jack2

EAPD

46 45 32 31

37 36 48 47

34 33

27 26 19 18

44 43

15 16

12 13 17 3

14

GND AGND

RA60

PC_BEEP

RA62

@

10K_0402_5%~D

1 2

RA2 0_0402 _5%

1 2

RA3 0_0402 _5%

1 2

RA4 0_0402 _5%

1 2

PC_BEEP

CA103 0.1U_0402_10V6K~ D

SLEEVE RING2

MIC2-R MIC2-L

1 2

RA9 39.2K_04 02_1%

HP1_A_R HP1_A_L HP2_D_L HP2_D_R

RA119 0_0402_5% RA120 0_0402_5%

SPK_MUTE#35

1 2

CA13 10U_0805_10V4Z~D

MIC_B_PLUG#

INT-SPK-R 35 INT-SPK-L 35

I2S_DAT/SPDIF_IN 2 8

1 2 1 2

GPIO3

EAPD# 32

SPK_MUTE#

+3.3V_DVDD

HP_MUTE#

D

INT-SUB-SPK 3 5

1 2

RA11 10K_04 02_1%

1 2

RA12 5.1K_0 402_1%

DMIC_CLK 25 DMIC0 25

1

RA64 10K_0402_5%~D

1 2

DA7

RA65 10K_0402_5%~D

1 2

1

BAT54AW_SOT323-3~D

+3.3V_AVDD+3.3V_DVDD

HPOUT2-JD

HPOUT-JD

DA6 BAT54CW_SOT323-3

3

2

3

2

EC_MUTE#

DEPOP#

GPIO3

EAPD#

EC_MUTE# 32

DEPOP# 32

E

S1 (Out + In) : Front L/R + HP1 + MIC (auto-sense)

HP1_A_L_L

HP1_A_R_L

HP_MUTE#

Setting the Turn-Off Time: Ton (ms) = 0.02 x Cset (pF)

S2 (Out) :Center + HP2

S3 (Out) : Rear L/R +MIC

MIC2-L

MIC2-R

LINE_B_L_RR

LINE_B_R_RR

HP_MUTE#

F

LINE2-VREFO

RA76 18_0402_5%~D

1 2

HP1_A_L HP1_A_L_C

1 2

HP1_A_R

RA77 18_0402_5%~D

1 2

RA5 100_0402_1%

1 2

RA7 100_0402_1%

CA14

0.1U_0402_16V4Z~D

RA78 18_0402_5%~D

1 2

HP2_D_L

RA79 18_0402_5%~D

1 2

HP2_D_R

HP2_D_L_R

HP2_D_R_R

HP_MUTE#

CA21 22U_1206_6.3V6M~D

CA24 22U_1206_6.3V6M~D

Setting the Turn-Off Time: Ton (ms) = 0.02 x Cset (pF)

RA15 100_0402_1%

RA16 100_0402_1%

Setting the Turn-Off Time: Ton (ms) = 0.02 x Cset (pF)

1 2

RA54 100_0402_1%

1 2

RA55 100_0402_1%

1 2

RA57 0_0402_5%

HP1_A_L_L

HP1_A_R_L

UA2 MAX9892ERT+T_UCSP6~D

A1

INL

A3

INR

B1

/MUTE

B3

12

1 2

0.1U_0402_16V4Z~D

SET

HP2_D_L_R

HP2_D_R_R

12

CA25

0.1U_0402_16V4Z~D

MIC2-VREFO-L

LINE_B_L_R

LINE_B_R_R LINEIN_B_R_C

MIC2-VREFO-R

A1

A3

DEPOP#_R

CA40

B1

12

B3

0_0603_5%~D

1 2

LA3

0_0603_5%~D

+3.3V_AVDD

VDD

GND

A2

LA4

0_0603_5%~D

1 2

0_0603_5%~D

UA3 MAX9892ERT+T_UCSP6~D

A1

INL

A3

INR

B1

/MUTE

B3

SET

1 2

RA17 2.2K_0402_5%~D

RA80

75_0402_1%~D

1 2

75_0402_1%~D

UA7 MAX9892ERT+T_UCSP6~D

LINE_B_L_RR

LINE_B_R_RR

RA81

1 2

RA18 2.2K_0 402_5%~D

INL

INR /MUTE

SET

1 2

RA10 2.2K_0402_5%~D

LA2

1

CA61 100P_0402_50V8J~D

2

1

CA60 100P_0402_50V8J~D

2

B2

HP2_D_L1_JK

1

2

CA63

LA5

VDD

GND

A2

CA62

+3.3V_AVDD

VDD

GND

A2

+3.3V_AVDD

B2

100P_0402_50V8J~D

1

2

B2

0_0603_5%~D

1 2

0_0603_5%~D

RING2

HP1_A_R_C

100P_0402_50V8J~D

LA6

LA7

HP2_D_R1_JK

CA64

CA65

G

1 2

RA13 2.2K_0402_5%~D

SLEEVE

HPOUT-JD

HPOUT2-JD

1

AZ5125-02S.R7G_SOT23-3

Place close to Jack

1

AZ5125-02S.R7G_SOT23-3

100P_0402_50V8J~D

LINEIN_B_L_C

1

2

1

2

100P_0402_50V8J~D

normal close type

1

AZ5125-02S.R7G_SOT23-3

Place close to Jack

1

AZ5125-02S.R7G_SOT23-3

Place close to Jack

DA10

DA11

MIC_B_PLUG#

DA12

DA13

Combo Jack

OK

JHP1

3

6

1

2 4

5

SINGA_2SJ-E960-001F

CONN@

1

AZ5125-02S.R7G_SOT23-3

Place close to Jack

1

AZ5125-02S.R7G_SOT23-3

Place close to Jack

JHP2

6 5

4

3

2 1

SINGA_2SJ-0960-D06

CONN@

2

HP2_D_L1_JK

3

HP2_D_R1_JK

2

HPOUT2-JD

3

HPOUT-JD

JHP3

6 5

4

3

2 1

SINGA_2SJ-0960-D06

CONN@

2

LINEIN_B_L_C

3

LINEIN_B_R_C

2

MIC_B_PLUG#

3

DA8

DA9

H

2

RING2

3

SLEEVE

2

HP1_A_L_C

3

HP1_A_R_C

Security Classification

2012/05/14 2013/05/13

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

A

B

C

D

E

2012/05/14 2013/05/13

Compal Secret Data

Deciphered Date

F

Title

Size Document Number Rev

Custom

Date: Sheet of

G

Compal Electronics, Inc.

HD Audio ALC3661

LA-9201P

34 66Thursday, August 16, 2012

H

0.1

5

LA10 FBMA-L11-160808-121LMA30T_0805

1

2

INT-SPK-L34

INT-SPK-R34

1 2

CA67

0.1U_0402_25V6K~D

1 2

CA87 0.47U_0603_16V7K~D

1 2

CA88 0.47U_0603_16V7K~D

12

1U_0603_25V6K

SPK_CD_L

SPK_CD_R

B+

Close to LA9

CA66

10U_1206_25V6M

D D

Audio SPK

+PVDD

12

CA69

CA68

Close to UA2 Pin7,15,16,27,28

CA70

1U_0603_25V6K

RA82

1 2

240K_0402_1%

RA84

1 2

240K_0402_1%

1 2

RA117 0_0402_5%

12

TPA3113 for Speaker

+5VS

@

RA91 100K_0402_1%

1 2

RA93 100K_0402_1%

1 2

C C

@

RA92 100K_0402_1%

1 2

GIN1GIN0

RA94 100K_0402_1%

1 2

GAIN1 GAIN0

0

1

1 0

1 1

AV(inv)

20dB

26dB

32dB

36dB

INPUT IMPEDANCE

60Kohm

30Kohm

15Kohm

9Kohm

4

40mil

12

CA72

CA71

1U_0603_25V6K

12

RA83 10K_0402_5%

@

12

RA85 10K_0402_5%

@

+3VALW

SPK_MUTE#34,35

1 2

RA118 10_0402_5%~D

B+

CA73

1 2

CA79

1 2

0.027U_0402_16V6K

RA87 100K_0402_5%

@

RA88 0_0402_5%

RA90

100K_0402_5%

+AVCC

+PVDD

AMP_LEFT_C

1 2

0.027U_0402_16V6K

CA76

AMP_RIGHT_C

1 2

0.027U_0402_16V6K

CA81

GIN0

GIN1

EAPD_R

12

1 2

RA97 0_0402_5%

+AVCC

10U_0805_25V

1

CA141

2

UA9

7

AVCC

15

PVCCR

16

PVCCR

27

PVCCL

28

PVCCL

3

LINP

4

LINN

12

RINP

11

RINN

5

GAIN0

6

GAIN1

1

SD#

2

FAULT#

13

NC

29

GND

TPA3113D2PWPR_HTSSOP28

BSPL

OUTPL

OUTNL

BSNL

BSPR

OUTPR

OUTNR

BSNR

PBTL

PLIMIT

GVDD

PGND PGND AGND

3

CA74

BSPL

BSNL

BSPR

BSNR

PLIMIT

+GVDD

0.22U_0603_25V7K

1 2

CA75

0.22U_0603_25V7K

CA77

1 2

0.22U_0603_25V7K

1 2

CA82

0.22U_0603_25V7K

+GVDD

1U_0603_25V6K

CA85

12

OUTPL

OUTNL

OUTPR

OUTNR

12

1U_0603_25V6K

+GVDD

CA86

12

RA86 51K_0402_1%

RA89 10K_0402_1%

26

25

23

22

17

18

20

21

14

10

9

24 19 8

2

Int. Speaker Connector

LA9 HCB2012KF-121T50_0805

OUTPL SPK_L2+_CONN

OUTNL

OUTPR

OUTNR

1 2

5A/120ohm/100MHz

LA11 HCB2012KF-121T50_0805

1 2

5A/120ohm/100MHz

LA12 HCB2012KF-121T50_0805

1 2

5A/120ohm/100MHz

LA13 HCB2012KF-121T50_0805

1 2

5A/120ohm/100MHz

20mil

SPK_L1-_CONN

SPK_R2+_CONN

SPK_R1-_CONN

1

SPK_L2+_CONN 37

SPK_L1-_CONN 37

SPK_R2+_CONN 37

SPK_R1-_CONN 37

B+

RA109 0_1206_5%

1

2

CA123

10U_1206_25V6

UA10

14

PBTL

1

SD#

2

FAULT#

3

INPL

4

INNL

12

INPR

11

INNR

7

1

2

AVCC

8

AGND

9

GVDD

10

PLIMIT

5

GAIN0

6

GAIN1

1 2

1U_0603_25V6K

CA136

12

CA135

GAIN01

GAIN11

B+

SPK_MUTE#34,35

1 2

INT-SUB-SPK34

INT-SUB-SPK

Woofer Amp Table

B B

G1

0

1

GAIN(dB)G0

20

26

1

36

Input Impedance (Rl) (Kohm)

60

30

15320

9

RA105

@

GAIN01 GAIN11

RA107 0_0402_5%

12

CA118 1U_0603_16V6K~D

RA96 0_0402_5%

12

100K_0402_1%

1 2

B+

12

1 2

RA106

@

RA108 0_0402_5%

12

RA116

0_0402_5%

@

For 32dB design, RA24 populated and RA36 is depopulated.

1 2

CA133 0.1U_0402_25V6

1 2

CA134 0.1U_0402_25V6

B+

RA114 51K_0402_1%

RA115

10K_0402_5%

1 2

12

RA112 10K_0402_1%

RA95 0_0402_5%

RA113 10_0402_1%

10U_0603_6.3V6M

12

28

PVCC15PVCC16PVCC27PVCC

TPA3110D1

PGND

GND

PGND

24

29

19

BSPL

OUTPL

OUTNL

BSNL

BSNR

OUTNR

OUTPR

BSPR

NC

TPA3111D1PWPR_TSSOP28~D

CA124

26

25

23

22

21

20

18

17

13

1

2

CA126

CA125

10U_1206_25V6

1

CA129

0.47U_0402_6.3V6K

2

1

CA132

0.47U_0402_6.3V6K

2

1

2

CA128

CA127

10U_1206_25V6

1 2

RA110 10_0402_1%

1 2

RA111 10_0402_1%

12

10U_1206_25V6

Speaker amp impedance of JBL is 4 ohm.

1 2

LA14 FBM-11-160808-601-T_0603

12

CA130 330P_0402_50V7K~D

1 2

LA15 FBM-11-160808-601-T_0603

12

CA131 330P_0402_50V7K~D

2

CA41

1000P_0402_50V7K

1

2

CA42

1000P_0402_50V7K

1

W=40mil

SUB_L+ SUB_R-

JWFER1

1

2

3

G1

4

G2

ACES_50271-00201-001

CONN@

A A

Security Classification

2011/06/02 2012/06/02

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2011/06/02 2012/06/02

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Amp TPA6017/subwoofer/ Audio Jack

LA-9201P

1

35 66Th ursday, August 16, 2012

0.1

5

4

3

2

1

W=40mils

+3.3V_F347

0.1U_0402_16V4Z~D C7

JP1

GND1 GND2

+3.3V_F347

1 2

1K_0402_1%~D

1

2

3

4

5

6

7 8

1 2

R1 0_0 603_5%~D

1U_0805_10V7

0.1U_0402_16V4Z~D

C3

1

C4

2

R8

+3.3V_F347

C11 0.1U_0402_16V4Z~D

1

2

@

USB20_P618 USB20_N618

+3.3V_F347

@

C13 0.1U_0402_16V4Z~D

C12 0.1U_0402_16V4Z~D

1

2

+3.3V_F347_R

22P_0402_50V8J~D

0.1U_0402_16V4Z~D

C2

C1

2

1

2

place R1564 as close as U602

U1

6

VDD

USB20_P6 USB20_N6

@

C14 0.1U_0402_16V4Z~D

1

2

@

C15 0.1U_0402_16V4Z~D

C16 0.1U_0402_16V4Z~D

C17 0.1U_0402_16V4Z~D

1

2

4

D+

5

D-

7

REGIN

8

VBUS

9

RST#/C2CK

10

P3.0/C2D

18

P2.0

17

P2.1

16

P2.2

15

P2.3

14

P2.4

13

P2.5

12

P2.6

11

P2.7

C8051F347-GQ_LQFP32_7X7

@

C18 0.1U_0402_16V4Z~D

We are Green SA00003IR80 for Mariner

1

2

P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7

P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7

GND

2

SPI_MOCLK

1

SPI_MOSO

32

SPI_MOSI

31

SPI_MOCS#

30

I2C_DAT

29

I2C_CLK

28

C5 0.1U_040 2_16V4Z~D@

27

26

SLP_S3

25

BATT_CHG_LED

24

ACIN#

23

LID_SW_IN#_D

22

BATT_LOW_LED

21

SLP_S5

20

C8 0.1U_040 2_16V4Z~D@

19

C9 0.1U_040 2_16V4Z~D@

3

1 2

R4 0_0402_5%~D

1 2

1 2 1 2

SDMK0340L-7-F_SOD323-2~D

+3.3V_F347

SPI_MOCLK_R

I2C_DAT 37,42

I2C_CLK 37,42

1 2

R7 1K_0402_5%~D

12

D70

SPI_MOSI

SPI_MOCLK_R

1 2

R13 10K_0402_5%~D

1 2

R14 10K_0402_5%~D

1 2

R15 10K_0402_5%~D

+3.3V_F347

12

R910K_0402_5%

LID_SW_IN#

I2C_DAT

I2C_CLK

+3.3V_F347

SPI_MOCS#

0.1U_0402_16V4Z~D

C19

1

2

+3.3V_F347

LID_SW_IN# 17 ,32,37

5

R1015_0402_5%

6

R1215_0402_5%

1

7

3

8

22P_0402_50V8J~D

EN25Q80A-100HIP_SO8

1

C20

2

U2

DI

CLK

CS

HOLD

WP

VCC

12

+3.3V_F347

12

R24.7K_0402_5%~D

12

R34.7K_0402_5%~D

2

R11 15_0402_5%

SO

4

VSS

1 2

SPI_MOSO

D D

1 2

R5 0_0603 _5%~D

+5VALW

+5VS

C C

1 2

R6 0_0603 _5%~D@

+3.3V_F347

Cloase to JP1

1U_0805_10V7

C6

1

2

0.1U_0402_16V4Z

C10

1

2

CONN@

AMPHE_G846A06201EU

+3.3V_F347

12

R16

100K_0402_1%~D

SLP_S3

1

D

PM_SLP_S3#15,32

B B

ACIN15, 32,56,63

BATT_CHG_LED#32

2

G

2

G

2

G

Q1 SSM3K7002F_SC59-3~D

S

3

+3.3V_F347

12

R18

100K_0402_1%~D

ACIN#

1

D

Q4 SSM3K7002F_SC59-3~D

S

3

+3.3V_F347

12

R24

100K_0402_1%~D

BATT_CHG_LED

1

D

Q8 SSM3K7002F_SC59-3~D

S

3

PM_SLP_S5#15,32

2

G

2

G

+3.3V_F347

12

R17

100K_0402_1%~D

1

D

Q2 SSM3K7002F_SC59-3~D

S

3

+3.3V_F347

12

R21

100K_0402_1%~D

1

D

Q6 SSM3K7002F_SC59-3~D

S

3

SLP_S5

BATT_LOW_LED

+3VALW +3.3V_F347

B+_BIAS

+3VALW

12

R22

100K_0402_1%~D

1

D

2

3V_F347_ON32BATT_LOW_LED#32

100K_0402_1%~D

G

12

R25

Q7 SSM3K7002F_SC59-3~D

S

3

MAXIM - LED MAXIM - GPIO 0100 001b I2C EEPROM

J11

@

2

112

JUMP_43X118

Q3

SI3456DDV-T1-GE3_TSOP6~D

D

6

S

2 1

R20

100K_0402_1%~D

1 2

2

45

G

1

3

2

SSM3K7002F_SC59-3~D

1

D

G

Q5

S

3

0.1U_0402_25V6K~D

C21

SMBUS ADDRESSDEVICE 0100 000b

1010 000b

100K_0402_1%~D

12

R19

300K_0402_5%~D

0.1U_0402_25V6K~D

R23

1

2

1 2

4.7U_0603_6.3V6M~D

C22

1

2

+3.3V_F347 behavior

STATE

S0 S3 S4 S5

C23

BAT only

AC IN

ON ON ON ON

ON ON OFF OFF

AC mode battery full in S5:turn off ELC controller

A A

Security Classification

2012/05/14 2013/05/13

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

5

4

3

2012/05/14 2013/05/13

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

ELC (1)

LA-9201P

1

36 66Friday, August 17, 20 12

0.1

5

7313_INT#42

D D

+3.3V_F347

4.7K_0402_1%~D

12

R30

C C

B B

PCH_SATALED#14

+3.3V_F347

1 2

R26

4.7K_0402_1%~D

12

R27

4.7K_0402_1%~D

12

R28

4.7K_0402_1%~D

R31

2

G

12

R32

+5VS

D

S

4.7K_0402_1%~D

100K_0402_5%~D

12

1

3

R29

TP_LED_R_DRV#42 TP_LED_G_DRV#42 TP_LED_B_DRV#42

12

R34

SATA_LED_ACT

SSM3K7002F_SC59-3~D

Q12

7313_INT#

4.7K_0402_1%~D

12

R33

L/R Tron, Logo, Alien Head, TP

U3

22

INT#/O16

19

I2C_CLK36,42

I2C_DAT36,42

I2C_CLK I2C_DAT

AD0_0 AD0_1 AD0_2

TP_LED_R_DRV# TP_LED_G_DRV# TP_LED_B_DRV#

SCL

20

SDA

18

AD0

23

AD1

24

AD2

14

P12

15

P13

16

P14

17

OSC

GND9GND

MAX7313DATG+T_TQFN-EP24_4X4~D

Indicator, Power

U4

22

INT#/O16

I2C_CLK I2C_DAT

HDD_R_7313# HDD_G_7313# HDD_B_7313#

2

G

2

G

2

G

19

SCL

20

SDA

18

AD2_0 AD2_1 AD2_2

AD0

23

AD1

24

AD2

14

P12

15

P13

16

P14

17

OSC

GND9GND

MAX7313DATG+T_TQFN-EP24_4X4~D

HDD_B

1

D

Q9 SSM3K7002F_SC59-3~D

S

3

HDD_B_7313#

HDD_R

1

D

Q10 SSM3K7002F_SC59-3~D

S

3

HDD_R_7313#

HDD_G

1

D

Q14 SSM3K7002F_SC59-3~D

S

3

HDD_G_7313#

P10 P11

V+

P0 P1 P2 P3 P4 P5 P6 P7 P8 P9

Reference AD2 AD1 AD0 MAX7313

U605

U608

0 1 0

0 1 1

U? 1 0 0

A A

Tron Lights,TP A-panel,B-Panel Logo

Power Button, Media and Status LED Color

Button, Indicator Brightness

P10 P11

21

1 2 3 4 5 6 7 8 10 11 12 13 25

21

V+

1

P0

2

P1

3

P2

4

P3

5

P4

6

P5

7

P6

8

P7

10

P8

11

P9

12 13 25

4

+3.3V_F347

LTRON_LED_R_DRV# LTRON_LED_G_DRV# LTRON_LED_B_DRV# RTRON_LED_R_DRV# RTRON_LED_G_DRV# RTRON_LED_B_DRV# ALIEN_LED_R_DRV#_1 ALIEN_LED_G_DRV#_1 ALIEN_LED_B_DRV#_1 LOGO_LED_R_DRV# LOGO_LED_G_DRV# LOGO_LED_B_DRV#

+3.3V_F347

0.1U_0402_16V4Z

1

2

LED_R_7313#_1 LED_G_7313#_1 LED_B_7313#_1

PWR_R_7313# PWR_G_7313# PWR_B_7313#

LID_SW

3

ON/OFFBTN#

2

Lid Switch

(Hall Effect Switch)

+3VALW

0.1U_0402_16V4Z~D

1

2

0.1U_0402_16V4Z~D

C24

1

2

S-5711ACDL-M3T1S_SOT23-3

U6

C39

2

VDD

OUTPUT

GND

1

3

LID_SW_IN# SPK_L1-_CONN

1

C40 10P_0402_50V8J~D

2

5/26 CIS update ok.

LID_SW_IN#17,32,36

C25

+5VS

0.1U_0402_16V4Z

C26

1

2

LID_SW LOGO_LED_R_DRV# LOGO_LED_G_DRV# LOGO_LED_B_DRV#

ALIEN_LED_R_DRV#_1 ALIEN_LED_G_DRV#_1 ALIEN_LED_B_DRV#_1

20mil

JLOGO1

1

2

3

4

5

6

7

8

9

10

11

12

13

GND1

14

GND2

ACES_87213-1200G

CONN@

3

D72 PESD24VS2UT_SOT23-3~D

1

Place close to JLED1

Power_LED#32

+5VALW

100K_0402_5%~D

12

R35

LID_SW

1

D

2

G

Q13 SSM3K7002F_SC59-3~D

S

3

Power_LED#

0.1U_0402_16V4Z

1

2

LTRON_LED_G_DRV# LTRON_LED_B_DRV#

TRON LED Board (F/L) CONN

2

C31

0.1U_0402_16V4Z

+5VALW

+5VS

C27

Power LED

+5VALW

S

Q20

G

2

SI2301CDS-T1-GE3_SOT23-3

D

1 3

+LED_PWR

CAPS_LED#32

WLES ON/OFF LED#32

ON/OFFBTN#44

20mil 20mil

JTRONL

1

2

3

4

5

7

5

G1

6

8

6

G2

ACES_50224-00601-001

LED_R_7313#_1 LED_B_7313#_1 LED_G_7313#_1 CAPS_LED# WLES ON/OFF LED# HDD_R HDD_G HDD_B ON/OFFBTN# PWR_G_7313# PWR_R_7313# PWR_B_7313#

SPK_L1-_CONN35 SPK_L2+_CONN35 SPK_R1-_CONN35 SPK_R2+_CONN35

+LED_PWR

LED_R_7313#_1 LED_B_7313#_1 LED_G_7313#_1 PWR_G_7313# PWR_R_7313# PWR_B_7313#

RTRON_LED_R_DRV#LTRON_LED_R_DRV# RTRON_LED_G_DRV# RTRON_LED_B_DRV#

SPK_L2+_CONN SPK_R1-_CONN SPK_R2+_CONN +LED_PWR

1 2

@

1 2

@

C54 0.1U_0402_25 V6K~D

1 2

C55 0.1U_0402_25 V6K~D

@

1 2

C56 0.1U_0402_25 V6K~D

@

1 2

C57 0.1U_0402_25 V6K~D

@

1 2

@

C58 0.1U_0402_25 V6K~D C59 0.1U_0402_25 V6K~D

+5VS

0.1U_0402_16V4Z

C28

1

2

TRON LED Board (F/R) CONN

1

+5VS

1

2

1 2 3 4 5 6

ACES_50224-00601-001

INDICATOR/B +SPK

JLED1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

GND

22

GND

TYCO_2-1734820-0~D

CONN@

JTRONR

1 2 3 4

7

5

G1

8

6

G2

LOGO Board CONN

LTRON_LED_R_DRV# LTRON_LED_G_DRV# LTRON_LED_B_DRV#

SATA_LED_ACT

1

D

2

G

Q16 SSM3K7002F_SC59-3~D

S

3

EN_TPLED#32

B+_BIAS +5VS +5VS_TP_LED

300K_0402_5%~D

R36

1 2

EN_TPLED

SSM3K7002FU_SC70-3~D

13

D

2

G

Q15

S

C29

1

2

Q11

SI3456DDV-T1-GE3_TSOP6~D

D

6

0.1U_0402_16V4Z

S

2 1

G

3

0.1U_0402_25V6K~D

1.5M_0402_5%~D R37

1

12

2

45

C33

1U_0603_10V4Z~D

C32

1

2

Touchpad LED circuit

1 2

@

1 2

@

C60 0.1U_0402_25 V6K~D

1 2

C62 0.1U_0402_25 V6K~D

@

C64 0.1U_0402_25 V6K~D

LTRON_LED_R_DRV# LTRON_LED_G_DRV# LTRON_LED_B_DRV# RTRON_LED_R_DRV# RTRON_LED_G_DRV# RTRON_LED_B_DRV#

TRON LED Board (F/L) CONN

+5VS

0.1U_0402_16V4Z

C30

1

20mil

2

JTRONF

1

2

3

4

5

6

7

8

9

10

11

GND1

12

GND2

ACES_50224-01001-001

RTRON_LED_R_DRV# RTRON_LED_G_DRV# RTRON_LED_B_DRV#

LTRON_LED_R_DRV# LTRON_LED_G_DRV# LTRON_LED_B_DRV# RTRON_LED_R_DRV# RTRON_LED_G_DRV# RTRON_LED_B_DRV#

1 2

@

1 2

C61 0.1U_0402_25 V6K~D

@

1 2

C63 0.1U_0402_25 V6K~D

@

C65 0.1U_0402_25 V6K~D

1 2

@

1 2

@

C66 0.1U_0402_25 V6K~D

1 2

@

C67 0.1U_0402_25 V6K~D

1 2

C68 0.1U_0402_25 V6K~D

@

1 2

C69 0.1U_0402_25 V6K~D

@

1 2

C70 0.1U_0402_25 V6K~D

@

C71 0.1U_0402_25 V6K~D

Security Classification

2012/05/14 2013/05/13

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

5

4

3

2012/05/14 2013/05/13

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

ELC (2)

LA-9201P

1

37 66Monday, August 20, 2012

0.1

A

1 1

+3VS

0.1U_0402_16V4Z~D

C34

1

2

FFS_INT115 FFS_INT219,39

2 2

PCH_SMBDATA6,12,13,17,39,40,42

PCH_SMBCLK6,12,13,17,39,40,42

10U_0805_10V4Z~D

C35

1

2

FFS_INT1 FFS_INT2

PCH_SMBDATA PCH_SMBCLK

FFS_INT1 connect to PCH GPIO & EC discuss with BIOS to use which pin

3 3

B

Free Fall Sensor

UN4

LNG3DM

1

VDD_IO

14

VDD

11

INT 1

9

INT 2

7

SDO/SA0

6

SDA / SDI / SDO

4

SCL/SPC

8

CS

LNG3DMTR_LGA16_3X3~D

RES RES RES RES

GND GND

NC NC

10 13 15 16

5 12

2 3

C

D

+3VS

+5VS

E

Close to JHDD1

0.1U_0402_16V4Z~D

1

CN1

2

1 2

SATA_PTX_DRX_P014 SATA_PTX_DRX_N014

SATA_PRX_DTX_N014 SATA_PRX_DTX_P014

CN6 0.01U_0402_16V7K~D

1 2

CN7 0.01U_0402_16V7K~D

1 2

CN8 0.01U_0402_16V7K~D

1 2

CN9 0.01U_0402_16V7K~D

HDD_DET#19

FFS_INT2_CONN39

SATA_PTX_DRX_P1_C SATA_PTX_DRX_N1_C

SATA_PRX_DTX_N1_C SATA_PRX_DTX_P1_C

+3VS

+5VS

FFS_INT2_CONN

1000P_0402_50V7K~D

1

2

JHDD1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

G1

22

G2

23

G3

24

G4

ACES_50406-02071-001

CONN@

0.1U_0402_16V4Z~D

1

CN2

2

1U_0402_6.3V4Z~D

1

CN3

2

10U_0805_10V4Z~D

CN4

1

2

1

CN5

CN59 47P_0402_50V8J~D

2

4 4

Security Classification

2012/05/14 2013/05/13

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2012/05/14 2013/05/13

C

Compal Secret Data

Deciphered Date

Title

SATA HDD1 & FFS

Size Document Number Rev

B

Date: Sheet of

D

Date: Sheet of

SATA HDD1 & FFS

LA-9201P

0.1

38 66Thursday, August 16, 2012

E

38 66Thursday, August 16, 2012

A

B

C

D

E

21

13

D

2

G

S

+5VS

ODD_DA#_R

QN4 2N7002E-T1-E3_SOT23-3

12

RN28

@

100K_0402_5%~D

ODD_B_PRE0

ODD_B_PRE1

ODD_A_PRE1

ODD_A_PRE0

ODD_REXT_SATA

RN21 0_0402_5%@

RN22 0_0402_5%@

RN23 0_0402_5%@

RN24 2K_0402_5%@

1 2

RN25 5.1K_0402_1%@

ODD_DA#15

FFS_INT2_CONN 38,39

1 2

RN45 0_0402_5%~D

ODD_DETECT#19

FFS_INT2_CONN38,3 9

Pin 20: PARADE PS8250B: depop RN18, RN25

PERICOM PI3EQX6741ST: pop RN18, depop RN25

ASMEDIA ASM1466: pop RN18, depop RN25

+3VS

+5VS_ODD

SATA_PRX_DTX_P2_C SATA_PRX_DTX_N2_C

SATA_PTX_DRX_N2_C SATA_PTX_DRX_P2_C

FFS_INT2_CONN

+5VS

SATA ODD Conn.

JODD1

1

2

2 2

3

4

4 4

5

6

6 6

ODD_DA#_R

7

8

8 8

9

10

10 10

11

12

12 12

13

14

14 14

15

16

16 16

17

18

18 18

19

20

20 20

G1 G2 G3 G4

ACES_50559-02001-001

Pin 9: PARADE PS8250B: depop RN24.

PERICOM PI3EQX6741ST: depop RN24

ASMEDIA ASM1466: pop RN24 to pull down

21 22 23 24

ODD power

+5VS

B+_BIAS

1 1

ODD_EN#19

RN26

300K_0402_5%~D

2

G

1 2

13

D

S

1U_0402_6.3V6K~D

1

2

ODD_EN

QN1 SSM3K7002FU_SC70-3~D

QN2

SI3456DDV-T1-GE3_TSOP6~D

D

6

2

CN39

1

G

3

1 2

+5VS_ODD

S

45

1.5M_0402_5%~D

0.1U_0402_25V6K~D CN40

1

RN27

2

ODD Redriver

+3VS

1 2

RN13 0_0402_5%@

1 2

2 2

SATA_ODD_PTX_DRX_P214 SATA_ODD_PTX_DRX_N214

SATA_ODD_PRX_DTX_P214 SATA_ODD_PRX_DTX_N214

CN25 0.01U_0402_16V7K~D

1 2

CN26 0.01U_0402_16V7K~D

1 2

CN27 0.01U_0402_16V7K~D

1 2

CN28 0.01U_0402_16V7K~D

+3VS

1 2 1 2

RN14 4.7K_0402_1%~D RN15 4.7K_0402_1%~D

1 2

RN16 4.7K_0402_1%~D

@ @

@

SATA_PTX_DRX_P2_R SATA_PTX_DRX_N2_R

SATA_PRX_DTX_P2_R SATA_PRX_DTX_N2_R

ODD_B_PRE1 ODD_A_PRE1

UN2

7

EN

1

A_INp

2

A_INn

5

B_OUTp

4

B_OUTn

17

B_PRE1

19

A_PRE1

18

TEST

3

GND

13

GND

21

EPAD

PS8520BTQFN20GTR2_TQFN20_4X4

+5VS_ODD

1000P_0402_50V7K~D

CN35

1

2

Placea caps. near ODD CONN.

+3VS

6

VDD

16

VDD

10

NC

20

REXT

A_PRE0 B_PRE0

A_OUTp A_OUTn

B_INp B_INn

ODD_REXT_SATA

9

ODD_A_PRE0

8

ODD_B_PRE0

15

SATA_PTX_DRX_P2_RC

14

SATA_PTX_DRX_N2_RC SATA_PTX_DRX_N2_C

11

SATA_PRX_DTX_P2_R_C

12

SATA_PRX_DTX_N2_R_C

0.1U_0402_16V4Z~D

CN38

CN37

CN36

0.01U_0402_16V7K

1

2

1

2

FFS_INT219,38

0.1U_0402_25V6K

1

4.7K_0402_1%~D

CN34

CN33

12

2

RN17

1 2

CN29 0.01U_0402_16V7K~D

1 2

CN30 0.01U_0402_16V7K~D

1 2

CN31 0.01U_0402_16V7K~D

1 2

CN32 0.01U_0402_16V7K~D

FFS_INT2 FFS_INT2_CONN

SSM3K7002FU_SC70-3~D

4.7K_0402_1%~D

12

@

RN18

ODD_EJECT#32

+3VS

G

2

13

D

S

QN3

4.7K_0402_1%~D

12

@

DN1 SDM10U45-7_SOD523-2~D

4.7K_0402_1%~D

12

@

RN19

RN20

SATA_PTX_DRX_P2_C

SATA_PRX_DTX_P2_C SATA_PRX_DTX_N2_C

10U_0805_10V4Z~D

1U_0402_6.3V4Z~D

m-SATA CONN

+3VS

T62PAD~D @ T63PAD~D @

3 3

1 2

MSATA_PRX_DTX_P314 MSATA_PRX_DTX_N314

MSATA_PTX_DRX_N314 MSATA_PTX_DRX_P314

E51TXD_P80DATA32

E51RXD_P80CLK32

4 4

CN43 0.01U_0402_16V7K~D

1 2

CN44 0.01U_0402_16V7K~D

1 2

CN42 0.01U_0402_16V7K~D

1 2

CN41 0.01U_0402_16V7K~D

1 2

RN43 0_0402_5%~D

1 2

RN44 0_0402_5%~D

T61PAD~D @ T59PAD~D @

SATA_PRX_DTX_P3_R SATA_PRX_DTX_N3_R

SATA_PTX_DRX_N3_R

SATA_PTX_DRX_P3_R

T65PAD~D @ T64PAD~D @

EC_TX_DAT

EC_TX_DAT EC_RX_CLK

12

RN46

100K_0402_1%

+1.5VS

1000P_0402_50V7K~D

1

2

CN55

1

2

JMSATA1

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

GND153GND2

LCN_DAN08-52526-0100

CONN@

1U_0402_6.3V4Z~D

0.1U_0402_16V4Z~D

CN57

CN56

1

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

10U_0805_10V4Z~D

CN58

1

2

+3VS +1.5VS

PCH_SMBCLK PCH_SMBDATA

+3VS

1000P_0402_50V7K~D

CN51

1

2

PCH_SMBCLK 6, 12,13,17,38,40,42

PCH_SMBDATA 6,12,13 ,17,38,40,42

10U_0805_10V4Z~D

1U_0402_6.3V4Z~D

0.1U_0402_16V4Z~D

CN54

CN53

CN52

1

2

1

2

Placea caps. near JP2 CONN.

Security Classification

2012/05/14 2013/05/13

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

A

B

C

2012/05/14 2013/05/13

Compal Secret Data

Deciphered Date

D

Placea caps. near JP2 CONN.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

SATA ODD/mSATA

LA-9201P

E

39 66Thursday, August 16, 2012

0.1

A

B

C

D

E

+1.5VS

0.1U_0402_16V4Z~D

4.7U_0805_10V4Z~D

C37

C36

1

1 2 1 2 1 2

1 2

+3VS

1 2

1

2

BT_ON#_RBT_ON#

RE1181K_0402_1%~D

1 1

WLAN

PCIE_WAKE#15,32,33

PCIE_PTX_WLANRX_N114 PCIE_PTX_WLANRX_P114

2 2

PCIE_WAKE# COEX2 COEX1

MINI1CLK_REQ#16

CLK_PCIE_MINI1#16 CLK_PCIE_MINI116

PLT_RST#6,15,31,32,33,40

CLK_DEBUG16

PCIE_PRX_WLANTX_N114 PCIE_PRX_WLANTX_P114

BT_ON#15

RE12 0_0402_5%~D@ R38 0_0402_5%~D R39 0_0402_5%~D

MINI1CLK_REQ#

CLK_PCIE_MINI1# CLK_PCIE_MINI1

RE32 0_0402_5%~D

PCIE_PRX_WLANTX_N1 PCIE_PRX_WLANTX_P1

1 2 1 2

PCIE_PTX_WANRX_P1_C

C48 0.1U_0402_16V4Z~ D C49 0.1U_0402_16V4Z~ D

C38

1

12

2

1 3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

53

47P_0402_50V8J

C52

JMINI1

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

GND1

GND2

LCN_DAN08-52406-0500

CONN@

+3VS

0.1U_0402_16V4Z~D

4.7U_0805_10V4Z~D

CA106

1

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

32 34 36 38 40 42 44 46 48 50 52

WiGi_RADIO_DIS#_RPCIE_PTX_WANRX_N1_C

34 36 38 40 42 44 46 48 50 52

54

0.1U_0402_16V4Z~D

CA107

1

2

47P_0402_50V8J

CA108

1

12

C53

2

+3VS

+1.5VS

1 2

RE31 0_0402_5%~D

1 2

RE26 0_0402_5%~D

1 2

RE27 0_0402_5%~D

1 2

RE28 0_0402_5%~D

1 2

RE29 0_0402_5%~D

WL_OFF#

1 2

RE22 0_0402_5%~D

USB20_N4 USB20_P4

LPC_FRAME# 17,3 2

LPC_AD3 17,32 LPC_AD2 17,32 LPC_AD1 17,32 LPC_AD0 17,32

WL_OFF# 15 PLT_RST# 6,15,31,32,33,40

WiGi_RADIO_DIS# 19

USB20_N4 18 USB20_P4 18

Display Mini Card (DMC)

JDMC1

PCIE_WAKE# COEX2 COEX1

MINI2CLK_REQ#16

CLK_PCIE_MINI2#16 CLK_PCIE_MINI216

3 3

PCIE_PTX_WANRX_N214 PCIE_PTX_WANRX_P214

PCIE_PRX_WANTX_N214 PCIE_PRX_WANTX_P214

1 2 1 2

C50 0.1U_0402_16V4Z~ D C51 0.1U_0402_16V4Z~ D

DMC_PCH_DET#16

CPU_MXM_DMC_AUXN30 CPU_MXM_DMC_AUXP30

CPU_MXM_DMC_N230 CPU_MXM_DMC_P230

CPU_MXM_DMC_N030 CPU_MXM_DMC_P030

1 2

RE30 0_0402_5%~D@

1 2

R40 0_0402_5%~D

1 2

R41 0_0402_5%~D

MINI2CLK_REQ#

CLK_PCIE_MINI2# CLK_PCIE_MINI2

PCIE_PRX_WANTX_N2 PCIE_PRX_WANTX_P2

PCIE_PTX_WANRX_N2_C PCIE_PTX_WANRX_P2_C

+3VS_DMC

DMC_PCH_DET# CPU_MXM_DMC_AUXN CPU_MXM_DMC_AUXP

CPU_MXM_DMC_N2 CPU_MXM_DMC_P2

CPU_MXM_DMC_N0 CPU_MXM_DMC_P0

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

55

57

59

61

63

65

67

69

71

73

75

77

GND1

LOTES_AAA-PCI-112-K01

CONN@

GND2

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

64

66

68

70

72

74

76

78

+3VS_DMC

+1.5VS_DMC

DMC_RADIO_OFF# PLT_RST#

MINI2_SMBCLK MINI2_SMBDATA

USB20_N5 USB20_P5

DP_DMC_HPD

CPU_MXM_DMC_N3 CPU_MXM_DMC_P3

CPU_MXM_DMC_N1 CPU_MXM_DMC_P1

DMC_RADIO_OFF# 19

1 2

RE33 0_0402_5%~D@

1 2

RE34 0_0402_5%~D@

1M_0402_5%~D

1 2

CPU_MXM_DMC_N3 30 CPU_MXM_DMC_P3 30

CPU_MXM_DMC_N1 30 CPU_MXM_DMC_P1 30

USB20_N5 18

USB20_P5 18

R44

PCH_SMBCLK PCH_SMBDATA

DP_DMC_HPD 30

+3VS

PCH_SMBCLK 6, 12,13,17,38,39,42

PCH_SMBDATA 6,12,13,17 ,38,39,42

L2

BLM18PG330SN1D_2P~D

+3VS_DMC

12

1

2

+1.5VS

4.7U_0805_10V4Z~D

0.1U_0402_16V4Z~D

CA111

CA109

1

2

L1

BLM18AG601SN1D_0603~D

12

+1.5VS_DMC

4.7U_0805_10V4Z~D

1

2

0.1U_0402_16V4Z~D

CA112

1

2

CA113

CA110

1

2

4 4

Security Classification

2012/05/14 2013/05/13

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

A

B

C

2012/05/14 2013/05/13

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Mini Card -WLAN/DMC/BT

LA-9201P

E

40 66Thursday, August 16, 2012

0.1

5

1 2

RI1 0_0402_5%~D@

LI3

SW_USB20_N0

SW_USB20_P0

D D

USB3RN1_R_C USB3RN1_R

USB3RP1_R_C

4

1

DLW21SN900SQ2L_0805_4P~D

1 2

RI2 0_0402_5%~D@

1 2

RI3 0_0402_5%~D@

LI1

2

3

DLW21SN900HQ2L_0805_4P~D

1 2

RI4 0_0402_5%~D@

3

2

1

4

USB20_N0_CONN

USB20_P0_CONN

USB3RP1_R

3

2

1

4

Power share

UI1

PWRSHARE_OE#32

USB20_N01 8

USB20_P018

PWRSHARE_OE# USB20_N0 USB20_P0

+5VALW

0.1U_0402_16V4Z~D

PWRSHARE_SEL#

PWRSHARE_OE# PWRSHARE_SEL# PWRSHARE_EN

8

CB

7

TDM

6

TDP

5

VDD

CI1

2

1

Thermal Pad

SLG55584AVTR_TDFN8_2X2

1 2

RI9 10K_0402_5%~D

1 2

RI8 10K_0402_5%~D@

1 2

RI10 10K_0402_ 5%~D@

1 2

RI7 10K_0402_5%~D@

SELCDP

CEN

3

1

PWRSHARE_EN

2 3 4 9

SW_USB20_N0

SW_USB20_P0

PWRSHARE_SEL#

+5VALW

PWRSHARE_EN

PWRSHARE_EN_EC#32

1 2

RI86 0_0402_5%~D

1

DM

DP

+3VALW

12

RI82

10K_0402_5%

DI7

221

1SS355TE-17_SOD323-2

2

+5VALW

CI18

4.7U_0805_10V4Z 100K_0402_5%

RI81

1 2

13

D

2

G

S

+5VALW

1

2

PWRSHARE_EN_R#

SSM3K7002FU_SC70-3~D

QI1

1

CI16

0.1U_0402_16V7K

2

1

CI13

0.1U_0402_16V7K

2

UI2

1

GND

2

VIN VIN3VOUT

4

EN

2.0A

8

VOUT

7

VOUT

6 5

FLG

EPAD

9

AP2301MPG-13_MSOP8

+USB3_VCCA

80mil

1 2

RI80 0_0402_5%~D

1

CI15

0.1U_0402_16V7K

2

USB_OC0# 18

1 2

RI5 0_0402_5%~D@

LI2

USB3TN1_R_C USB3TN1_R

USB3TP1_R_C

+3VS

1 2

RI55 3.3K_0402_5%@

1 2

RI54 3.3K_0402_5%@

1 2

RI53 3.3K_0402_5%@

1 2

RI52 3.3K_0402_5%@

1 2

C C

B B

A A

RI42 4.7K_0402_5%~D@

1 2

RI43 4.7K_0402_5%~D@

1 2

RI44 4.7K_0402_5%~D@

1 2

RI41 4.7K_0402_5%~D@

1 2

RI19 4.7K_0402_5%~D

1 2

RI20 4.7K_0402_5%~D@

1 2

RI21 4.7K_0402_5%~D

1 2

RI22 4.7K_0402_5%~D

1 2

RI26 4.7K_0402_5%~D@

1 2

RI23 4.7K_0402_5%~D

1 2

RI24 4.7K_0402_5%~D

1 2

RI25 4.7K_0402_5%~D@

1 2

RI30 4.7K_0402_5%~D

1 2

RI27 4.7K_0402_5%~D

1 2

RI28 4.7K_0402_5%~D@

1 2

RI29 4.7K_0402_5%~D

1 2

RI87 4.7K_0402_5%~D@

1 2

RI31 4.7K_0402_5%~D@

1 2

RI36 4.7K_0402_5%~D@

1 2

RI40 4.7K_0402_5%~D@

1 2

RI35 4.7K_0402_5%~D@

1 2

RI32 4.7K_0402_5%~D@

1 2

RI33 4.7K_0402_5%~D@

1 2

RI34 4.7K_0402_5%~D@

1 2

RI39 4.7K_0402_5%~D@

1 2

RI37 4.7K_0402_5%~D@

1 2

RI38 4.7K_0402_5%~D@

1 2

RI84 4.7K_0402_5%~D@

1 2

RI46 4.7K_0402_5%~D@

1 2

RI47 4.7K_0402_5%~D@

1 2

RI48 4.7K_0402_5%~D@

1 2

RI45 4.7K_0402_5%~D@

1 2

RI49 0_0402_5%~D@

1 2

RI50 0_0402_5%~D@

1 2

RI85 0_0402_5%~D@

1 2

RI51 0_0402_5%~D@

USB20_P118

USB20_N11 8

2

3

DLW21SN900HQ2L_0805_4P~D

1 2

RI6 0_0402_5%~D@

USB20_P1

USB20_N1

RI17 0_0402_5%~D@

USB3TP2_R_C USB3TP2_R

USB3TN2_R_C

RI18 0_0402_5%~D@

RI15 0_0402_5%~D@

USB3RP2_R_C USB3RP2_R

USB3RN2_R_C

RI16 0_0402_5%~D@

5

1

4

USB3_P1_PIN6 USB3_P1_PIN18

USB3_P0_PIN6 USB3_P0_PIN18

USB3_CM_P0 USB3_CM_P1 USB3_ERD_P0 USB3_ERD_P1

USB3_OS2_P0 USB3_DE2_P0 USB3_EQ2_P0 USB3_OS1_P0 USB3_DE1_P0 USB3_EQ1_P0 USB3_OS2_P1 USB3_DE2_P1 USB3_EQ2_P1 USB3_OS1_P1 USB3_DE1_P1 USB3_EQ1_P1

USB3_CM_P0 USB3_CM_P1 USB3_ERD_P0 USB3_ERD_P1

USB3_P0_PIN6 USB3_P0_PIN18

USB3_P1_PIN6 USB3_P1_PIN18

1 2

RI13 0_0402_5%~D@

LI6

4

1

DLW21SN900HQ2L_0805_4P~D

RI14 0_0402_5%~D@

1 2

LI5

2

3

DLW21SN900HQ2L_0805_4P~D

1 2

LI4

2

3

DLW21SN900HQ2L_0805_4P~D

1 2

3

2

1 2

1

4

1

4

USB3TP1_R

Vendor pin

pin15

pin16

pin17

pin4

pin3

pin2

pin5

pin14

pin18

pin6

[Parade suggest] PS8710 AEQ0,BEQ0 adjust 7db, REXT use 3.3 K well get btter test result.

3

USB20_P1_CONN

2

USB20_N1_CONN

1

4

USB3TN2_R

1

4

USB3RN2_R

PS8710B (default)

AEQ1

ADE0

AEQ0

BEQ1

BDE0

BEQ0

PD

TEST

ADE1

BDE1

USB3RN118 USB3RP11 8

USB3TN118 USB3TP118

TI

OS2

DE2

EQ2

OS1

DE1

EQ1

EN_RXD

CM

USB3RN1 USB3RP1

USB3TN1 USB3TP1

SN65LVPE502 EN== 1:normal operation(default) 0:sleep mode CM== 0:normal operation(default) 1:Compliance test mode

PS8710 [A(B)_DE1, A(B)_DE0] == LL: 3.5dB de-emphasis LH: No de-emphasis HL: 7dB de-emphasis HH: 5dB with boost output swing [A(B)_EQ1, A(B)_EQ0] == LL: reserved LH: program EQ for channel loss up to 7dB HL: program EQ for channel loss up to 14.5dB HH: program EQ for channel loss up to 11.5dB TEST == L: Normal operation (default) H: Test mode enable

USB3RN218 USB3RP21 8

USB3TN218 USB3TP218

4

1 2

CI9 0.1U_0402_10V6K~D

1 2

CI8 0.1U_0402_10V6K~D

1 2

CI4 0.1U_0402_1 0V6K~D

1 2

CI5 0.1U_0402_1 0V6K~D

1 2

CI27 0.1U_0402_10V6K~D

1 2

CI28 0.1U_0402_10V6K~D

1 2

CI23 0.1U_0402_10V6K~D

1 2

CI24 0.1U_0402_10V6K~D

CI35

USB_PWR_EN#

USB_PWR_EN#32,42

USB3RN2 USB3RP2

USB3TN2 USB3TP2

4.7U_0805_10V4Z

CI7

0.01U_0402_16V7K~D

1 2 1 2

CI6

.1U_0402_16V7K~D

CI26

0.01U_0402_16V7K~D

1 2 1 2

CI25

.1U_0402_16V7K~D

+5VALW

1

2

+3VS

USB3RN1_L USB3RP1_L

USB3_OS2_P0 USB3_DE2_P0 USB3_EQ2_P0

USB3TN1_L USB3TP1_L

USB3_OS1_P0 USB3_DE1_P0 USB3_EQ1_P0

+3VS

1

CI36

0.1U_0402_16V7K

2

1

CI37

0.1U_0402_16V7K

2

UI3

1

VCC

13

VCC

11

TX2-

12

TX2+

15

OS2

16

DE2

17

EQ2

8

RX1-

9

RX1+

4

OS1

3

DE1

2

EQ1

25

PGND

PS8713BTQFN24GTR2-A0_TQFN24_4X4

PCB footprint and CIS symbol use TI (SN65LVPE502CPRGER) Compal P/N and value use Parade (PS8710B)

RX2-

RX2+

EN_RXD

TX1-

TX1+

GND GND GND GND

CM

NC NC

7 24

20

USB3RN1_R_C

19

USB3RP1_R_C

5

USB3_ERD_P0

14

USB3_CM_P0

23

USB3TN1_RC

22

USB3TP1_RC

6

USB3_P0_PIN6

10 18

USB3_P0_PIN18

21

For OPTION reserve

1 2

RI64 0_0402_5%~D@

1 2

RI65 0_0402_5%~D@

1 2

RI66 0_0402_5%~D@

1 2

RI67 0_0402_5%~D@

1 2

RI60 0_0402_5%~D@

1 2

RI61 0_0402_5%~D@

1 2

RI63 0_0402_5%~D@

1 2

RI62 0_0402_5%~D@

UI4

VCC

NC

VCC

NC

TX2-

RX2-

TX2+

RX2+

OS2

EN_RXD

DE2

CM

EQ2

RX1-

TX1-

TX1+

RX1+

OS1 DE1

GND

EQ1

GND GND GND

PGND

+USB3_VCCB

8

VOUT

7

VOUT

6 5

FLG

EPAD

AP2301MPG-13_MSOP8

3

USB3RN2_L USB3RP2_L

USB3_OS2_P1 USB3_DE2_P1 USB3_EQ2_P1

USB3TN2_L USB3TP2_L

USB3_OS1_P1 USB3_DE1_P1 USB3_EQ1_P1

1 2

4

USB3RN1 USB3RN1_RL USB3RP1

USB3TN1

USB3RN2 USB3RP2

USB3TN2

1

13

11 12

15 16 17

8 9

4 3 2

25

PS8713BTQFN24GTR2-A0_TQFN24_4X4

PCB footprint and CIS symbol use TI (SN65LVPE502CPRGER) Compal P/N and value use Parade (PS8710B)

2.0A

UI5

GND VIN VIN3VOUT EN

9

Power share USB CONN

+USB3_VCCA

RI56 4.99K_0402_1% RI57 0_0402_5%~D@

7 24

20 19

5 14

23 22

6 10 18 21

12

1 2

CI11 0.1 U_0402_10V6K~D

1 2

CI10 0.1 U_0402_10V6K~D

USB3RP1_RL

USB3TN1_RL USB3TP1_RLUSB3TP1

USB3RN2_RL USB3RP2_RL

USB3TN2_RL USB3TP2_RLUSB3TP2

RI77 4.99K_0402_1% RI76 0_0402_5%~D@

USB3RN2_R_C USB3RP2_R_C

USB3_ERD_P1 USB3_CM_P1

USB3TN2_RC USB3TP2_RC

USB3_P1_PIN6

USB3_P1_PIN18

12

1 2

CI29 0.1U_0402_10V6K~D

1 2

CI30 0.1U_0402_10V6K~D

USB3TN1_R_C USB3TP1_R_C

1 2

RI72 0_0402_5%~D@

1 2

RI73 0_0402_5%~D@

1 2

RI74 0_0402_5%~D@

1 2

RI75 0_0402_5%~D@

1 2

RI68 0_0402_5%~D@

1 2

RI69 0_0402_5%~D@

1 2

RI71 0_0402_5%~D@

1 2

RI70 0_0402_5%~D@

USB3TN2_R_C USB3TP2_R_C

USBCHG_DET#32

80mil

1 2

RI83 0_0402_5%~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

1

2

USB_OC1# 18

CI38

0.1U_0402_16V7K

Compal Secret Data

2012/05/14 2013/05/13

Compal Secret Data

Deciphered Date

USB20_N0_CONN USB20_P0_CONN

USB3RN1_R USB3RP1_R USB3TN1_R USB3TP1_R

PESD5V0U2BT_SOT23-3~D

2

3

DI8

1

USB3RN1_R

USB3RP1_R

USB3TN1_R

USB3TP1_R

USB3RN1_R_C USB3RP1_R_C

USB3TN1_R_C USB3TP1_R_C

USB3RN2_R_C USB3RP2_R_C

USB3TN2_R_C USB3TP2_R_C

+USB3_VCCB

USB3TP2_R

USB3TN2_R

USB20_P1_CONN

USB20_N1_CONN

USB3RP2_R

USB3RN2_R

2

3

DI10

PESD5V0U2BT_SOT23-3~D

1

DI11

1

USB3RN2_R USB3RN2_R

2

USB3RP2_R

4

USB3TN2_R

5

USB3TP2_R

3

8

IP4292CZ10-TBR_XSON10_2.5X1~D

2

OK

JUSB1

1

VBUS

2

D-

3

D+

5 6 8 9

10

1

2

4

5

3

8

IP4292CZ10-TBR_XSON10_2.5X1~D

GND

SSRX-

GND GND

SSRX+ SSTX-

GND GND

SSTX+ D1-DP

GND

TAITW_USB011-107BRL-TW

CONN@

DI9

(LEFT)

OK

JUSB2

9

SSTX+

1

VBUS

8

SSTX-

3

D+

7

GND

2

D-

6

SSRX+

4

GND

5

SSRX-

SINGA_2UB4008-500101F

CONN@

10

9

USB3RP2_R

7

USB3TN2_R

6

USB3TP2_R

10

GND

11

GND

12

GND

13

GND

Title

Size Document Number Rev

Custom

Date: Sheet of

14 13 12 11 4 7

10

9

7

6

USB3RN1_R

USB3RP1_R

USB3TN1_R

USB3TP1_R

CI32

220U_6.3V_M

CI20

220U_6.3V_M

+USB3_VCCB

1

+

2

1

2

Compal Electronics, Inc.

USB 3.0/2.0 x2 (left side)

LA-9201P

1

10U_0603_6.3V6M~D

CI34

+USB3_VCCA

1

+

2

10U_0603_6.3V6M~D

CI22

1

2

0.1

41 66Thursday, August 16, 2012

5

D D

1 2

RI89 0_0402_5%~D@

LI7

USB20_P218

USB20_N218

C C

B B

USB20_P2

USB20_N2

USB3TN5_R_C USB3TN5_R

USB3TP5_R_C

USB3RN5_R_C USB3RN5_R

USB3RP5_R_C

4

1

DLW21SN900HQ2L_0805_4P~D

1 2

RI90 0_0402_5%~D@

1 2

RI93 0_0402_5%~D@

LI9

2

3

DLW21SN900HQ2L_0805_4P~D

1 2

RI88 0_0402_5%~D@

1 2

RI92 0_0402_5%~D@

LI8

2

3

DLW21SN900HQ2L_0805_4P~D

1 2

RI91 0_0402_5%~D@

3

2

1

4

1

4

USB20_P2_CONN

USB20_N2_CONN

USB3TP5_R

USB3RP5_R

+3VS

4

USB3RN518 USB3RP518

USB3TN518 USB3TP518

USB3RN5 USB3RP5

USB3TN5 USB3TP5

4.7U_0805_10V4Z

USB_PWR_EN#3 2,41

1 2

RI128 3.3K_0402_5%@

1 2

RI122 3.3K_0402_5%@

1 2

RI116 4.7K_0402_5%~D@

1 2

RI102 4.7K_0402_5%~D@

1 2

RI103 4.7K_0402_5%~D

1 2

RI107 4.7K_0402_5%~D@

1 2

RI112 4.7K_0402_5%~D

1 2

RI125 4.7K_0402_5%~D

1 2

RI136 4.7K_0402_5%~D@

1 2

RI105 4.7K_0402_5%~D

CI41

0.01U_0402_16V7K~D

1 2 1 2

CI31

.1U_0402_16V7K~D

1 2

CI45 0.1U_0402_10V6K~D

1 2

CI43 0.1U_0402_10V6K~D

1 2

CI46 0.1U_0402_10V6K~D

1 2

CI48 0.1U_0402_10V6K~D

+5VALW

1

CI42

2

USB_PWR_EN#

CI40

0.1U_0402_16V7K

2

1

CI39

0.1U_0402_16V7K

2

USB3_P5_PIN6 USB3_P5_PIN18

USB3_CM_P5 USB3_ERD_P5

USB3_OS2_P5 USB3_DE2_P5 USB3_EQ2_P5 USB3_OS1_P5 USB3_DE1_P5 USB3_EQ1_P5

+3VS

USB3RN5_L USB3RP5_L

USB3_OS2_P5 USB3_DE2_P5 USB3_EQ2_P5

USB3TN5_L

USB3_OS1_P5 USB3_DE1_P5 USB3_EQ1_P5

3

UI6

1

VCC

13

VCC

11

TX2-

12

TX2+

15

OS2

16

EN_RXD

DE2

17

EQ2

8

RX1-

9

RX1+

4

OS1

3

DE1

2

EQ1

25

PGND

PS8713BTQFN24GTR2-A0_TQFN24_4X4

PCB footprint and CIS symbol use TI (SN65LVPE502CPRGER) Compal P/N and value use Parade (PS8710B)

2.0A

UI7

1

GND

2

4

VOUT VOUT

VIN VIN3VOUT

FLG

EN

EPAD

9

AP2301MPG-13_MSOP8

RX2+

8 7 6 5

NC NC

RX2-

CM

TX1-

TX1+

GND GND GND GND

7

RI96 4.99K_0402_1%

24

RI94 0_0402_5%~D@

20

USB3RN5_R_C

19

USB3RP5_R_C

5

USB3_ERD_P5

14

USB3_CM_P5

23

USB3TN5_RC

22

USB3TP5_RC

6

USB3_P5_PIN6

10 18

USB3_P5_PIN18

21

+USB3_VCCC

80mil

RI95 0_0402_5%~D

1 2

12

1 2

CI47 0.1U_0402_10V6K~D

1 2

CI49 0.1U_0402_10V6K~D

1

CI44

0.1U_0402_16V7K

2

PESD5V0U2BT_SOT23-3~D

2

3

USB_OC2# 18

USB3TP5_R

USB3TN5_R

USB20_P2_CONN

USB20_N2_CONN

USB3RP5_R

USB3RN5_R

DI12

2

1

50 pin FFC connector To MB(VPK) not Hot Key

JVPK1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

GND1

52

GND2

STARC_089B50-012000-G2-R

CI51

CONN@

USB3TN5_R_C USB3TP5_R_CUSB3TP5_L

TP_CLK

TP_DATA

2

3

PESD5V0U2BT_SOT23-3~D D71

1

Place close to JVPK1

+USB3_VCCC

(RIGHT)

JUSB3

9

SSTX+

1

VBUS

8

SSTX-

3

D+

7

GND

2

D-

6

SSRX+

4

GND

5

SSRX-

SINGA_2UB4008-500101F

CONN@

+5VS_TP_LED

TP_CLK32

TP_DATA32 PCH_SMBDATA6,12,13,17,38,39,40 PCH_SMBCLK6,12,13,17,38,39,40 TP_LED_R_DRV#37 TP_LED_G_DRV#37 TP_LED_B_DRV#37

+5VS

+3VS

EC_SMB_DA217,32,43,46

EC_SMB_CK217,32,43,46 USB20_P1218 USB20_N1218

+3.3V_F347

I2C_CLK36,37 I2C_DAT36,37 7313_INT#37

KB_DET#32

KSI[0..7]32

KSO[0..17]32

KSI[0..7]

KSO[0..17]

VPK_EN32 VPK_DET#32

OK

10

GND

11

GND

12

GND

13

GND

TP_CLK TP_DATA

TP_LED_R_DRV# TP_LED_G_DRV# TP_LED_B_DRV#

CI52

220U_6.3V_M

I2C_CLK I2C_DAT

KB_DET# KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17

+USB3_VCCC

1

+

2

10U_0603_6.3V6M~D

1

2

1 2

SN65LVPE502 EN== 1:normal operation(default)

Vendor pin

pin15

pin16

pin17

pin4

pin3

pin2

A A

pin5

pin14

pin18

pin6

PS8710B (default)

AEQ1

ADE0

AEQ0

BEQ1

BDE0

BEQ0

PD

TEST

ADE1

BDE1

TI

OS2

DE2

EQ2

OS1

DE1

EQ1

EN_RXD

CM

0:sleep mode CM== 0:normal operation(default) 1:Compliance test mode

PS8710 [A(B)_DE1, A(B)_DE0] == LL: 3.5dB de-emphasis LH: No de-emphasis HL: 7dB de-emphasis HH: 5dB with boost output swing [A(B)_EQ1, A(B)_EQ0] == LL: reserved LH: program EQ for channel loss up to 7dB HL: program EQ for channel loss up to 14.5dB HH: program EQ for channel loss up to 11.5dB

RI118 4.7K_0402_5%~D@

1 2

RI121 4.7K_0402_5%~D@

1 2

RI120 4.7K_0402_5%~D@

1 2

RI104 4.7K_0402_5%~D@

1 2

RI108 4.7K_0402_5%~D@

1 2

RI115 4.7K_0402_5%~D@

1 2

RI126 4.7K_0402_5%~D@

1 2

RI113 4.7K_0402_5%~D@

1 2

RI117 0_0402_5%~D@

1 2

RI124 0_0402_5%~D@

USB3RN5 USB3RN5_RL USB3RP5

USB3TN5

1 2

RI137 0_0402_5%~D@

1 2

RI139 0_0402_5%~D@

1 2

RI141 0_0402_5%~D@

1 2

RI143 0_0402_5%~D@

TEST ==

[Parade suggest] PS8710 AEQ0,BEQ0 adjust 7db,

L: Normal operation (default) H: Test mode enable

REXT use 3.3 K well get btter test result.

5

4

USB3_OS2_P5 USB3_DE2_P5 USB3_EQ2_P5 USB3_OS1_P5 USB3_DE1_P5 USB3_EQ1_P5

USB3_CM_P5 USB3_ERD_P5

USB3_P5_PIN6

USB3_P5_PIN18

1

1 2

RI138 0_0402_5%~D@

USB3RP5_RL

USB3TN5_RL USB3TP5_RLUSB3TP5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1 2

RI140 0_0402_5%~D@

1 2

RI142 0_0402_5%~D@

1 2

RI144 0_0402_5%~D@

2012/05/14 2013/05/13

USB3RN5_R_C USB3RP5_R_C

USB3TN5_R_C USB3TP5_R_C

Compal Secret Data

Deciphered Date

USB3RN5_R

USB3RP5_R

USB3TN5_R

USB3TP5_R

DI13

1

2

4

5

3

8

IP4292CZ10-TBR_XSON10_2.5X1~D

2

10

9

7

6

USB3RN5_R

USB3RP5_R

USB3TN5_R

USB3TP5_R

Title

USB & IO CONN

Size Document Number Rev

Custom

Date: Sheet of

USB & IO CONN

LA-9201P

42 66Thursday, August 16, 2012

1

42 66Thursday, August 16, 2012

0.1

A

B

C

D

E

System FAN Controller

+3VS

Diode circuit s used for skin temp sensor (placed between CPU and VGA). Place C45 close to Q17 as possible.

1 1

100P_0402_50V8J~D

@

C45

1

2

C

2

B

E

Q17

3 1

MMBT3904WT1G_SC70-3~D

Diode circuit s used for skin temp sensor

SENSOR_DIODE_N1

1 2

R46 0_0402_5%~D

1 2

R47 0_0402_5%~D

R48 4.7K_0402_5%~D

+3VS

REMOTE_P1SENSOR_DIODE_P1

1

C46

470P_0402_50V7K~D

2

REMOTE_N1

1 2

(placed between CPU and MXM). Place C1814 close to Q276 as possible.

Pull up resistor on thermtrip pin

4.7k

6.8k

2 2

10k 15k 22k 33k

SMBUS address

1111 1011 1001 1101 0011 0111

SYSTEM_FAN_PWM32

SYSTEM_FAN_FB32

SYSTEM_FAN_PWM

SYSTEM_FAN_FB

0.1U_0402_10V7K~D C44

1

2

U5

1

VDD

2

D+

3

ADM1032ARMZ-REEL_MSOP8

ALERT#

D-

THERM#4GND

SCLK

SDATA

8

7

6

5

EC_SMB_CK2

EC_SMB_DA2

EC_SMB_CK2 17,32,42,46

EC_SMB_DA2 17,32,42,46

Address:100_1100

+3VS

10K_0402_5%~D

R50

R49

1 2

D65

SDMK0340L-7-F_SOD323-2~D

+5VS

22U_0805_6.3VAM~D

C47

10K_0402_5%~D

R51

1 2

12

1

2

OK

JFAN1

6

GND2

5

GND1

4

3

2

1

ACES_50271-0040N-001

CONN@

+3VS

DDR FAN Controller

Diode circuit s used for skin temp sensor

0.1U_0402_10V7K~D C41

1

(placed around DIMM). Place C43 close to Q19as possible.

100P_0402_50V8J~D

C43

1

2

3 3

@

C

2

B

E

Q19

3 1

MMBT3904WT1G_SC70-3~D

SENSOR_DIODE_P2

SENSOR_DIODE_N2

1 2

R59 0_0402_5%~D

1 2

R60 0_0402_5%~D

R61 6.8K_0402_5%~D

+3VS

1 2

REMOTE_P2

1

C42

470P_0402_50V7K~D

2

REMOTE_N2

2

U7

1

VDD

2

D+

3

D-

THERM#4GND

ADM1032ARMZ-2REEL_MSOP8

SCLK

SDATA

ALERT#

8

7

6

5

EC_SMB_CK2

EC_SMB_DA2

Address:100_1101

4 4

Security Classification

2012/05/14 2013/05/13

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

2012/05/14 2013/05/13

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Thermal Sensor & FAN

LA-9201P

E

0.1

43 66Thursday, August 16, 2012

A

B

C

D

E

1 1

2 2

@

H1

@

H_2P8

1

H13

@

H_3P3

1

H27

@

H_3P0X2P5

1

@

H2

H_2P8

1

H14

@

H_3P3

1

H28

@

H_2P5X3P3

1

H3

H15

1

@

H_2P3

@

H_3P3

H5

H16

@

H_2P8

1

@

H_3P3

1

H29

@

H_2P5

H6

H17

1

H7

@

H_2P8

H18

@

H_3P3

1

H8

@

H_2P8

H19

@

H_3P8

1

H9

@

H_3P0

H20

@

H_3P8

1

H10

@

H_2P8

H21

@

H_2P8

1

H11

@

H_2P8

H22

@

H_3P8

1

H12

@

H_3P0

H23

@

H_3P8

1

H24

@

H_3P8

1

H25

@

H_3P8

1

H26

@

H_3P8

FD1

@

1

FIDUCIAL_C40M80

FD2

@

1

FIDUCIAL_C40M80

FD3

@

1

FIDUCIAL_C40M80

FD4

@

1

FIDUCIAL_C40M80

Fiducial Mark

+3VLP

ON/OFF switch

TOP Side

SMT1-05-A_4P

1

2

SW1

5

6

Power Button

3

4

ON/OFFBTN#

D26

ON/OFFBTN#

ON/OFFBTN#37

0.1U_0402_25V6K~D

CA122

1

DAN202UT106_SC70-3

2

3

R58

100K_0402_5%~D

1 2

ON/OFF 32

2

Bottom Side

3 3

SMT1-05-A_4P

1

2

SW2

3

4

5

6

Pop only for SSI debug

ZZZ1

4 4

Security Classification

PCB-MB

Security Classification

2012/05/14 2013/05/13

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2012/05/14 2013/05/13

C

Compal Secret Data

Deciphered Date

Title

KB & Power Button & IR

Size Document Number Rev

B

Date: Sheet of

D

Date: Sheet of

KB & Power Button & IR

LA-9201P

E

0.1

44 66Thursday, August 16, 2012

A

DC to DC

B

C

D

E

+5VALW to +5VS

1 1

1

2

B+_BIAS

102K_0402_ 1%

10U_0805_10V4Z~D

CZ1

1

2

1 2

RZ1

SUSP

10U_0805_10V4Z~D

5

QZ2B

+5VALW

CZ2

3

4

QZ1

SI4800BDY-T1-E3_SO8 ~D

8 7

5

4

+5VS_GATE +3V_PCH_GATE

2N7002DW-T/R7_SOT363-6

0.1U_0603_25V7K~D

1

CZ4

2

+5VS

1 2 36

0_0402_5%~D

@

RZ2

1 2

1U_0603_10V4Z~D

10U_0805_10V4Z~D

CZ3

CZ5

1

2

B+_BIAS

PCH_PWR_EN#

+3VALW to +3VS

+3VALW

10U_0805_10V4Z~D

RZ3

10U_0805_10V4Z~D

CZ7

CZ6

1

2

+3VS_GATE

SSM3K7002F_SC59-3~D

1

D

2

G

QZ4

S

3

2 2

B+_BIAS

1 2

102K_0402_ 1%

SUSP

QZ3

SI4800BDY-T1-E3_SO8 ~D

8 7

5

4

0.1U_0603_25V7K~D

1

2

0_0402_5%~D

12

CZ10

@

RZ4

+3VS

1 2 36

1U_0603_10V4Z~D

10U_0805_10V4Z~D

CZ8

1

2

CZ9

1

2

SUSP

2

G

+3VALW to +3V_PCH

10U_0805_10V4Z~D

CZ11

1

2

RZ5

1 2

102K_0402_ 1%

2

10U_0805_10V4Z~D

G

+3VALW

CZ12

D

S

1

3

SI4800BDY-T1-E3_SO8 ~D

QZ6

8 7

5

4

SSM3K7002F_SC59-3~D

QZ5

+1.05V To +1.05VS

+1.05V +1.05VS

UZ1

B+_BIAS

100K_0402_5%~D

12

RZ7

13

D

QZ7 SSM3K7002FU_ SC70-3~D

S

10U_0805_10V4Z~D

CZ19

1 2

RZ8

10K_0402_5 %~D

1

2

AO4728L_SO8~D

8 7 6 5

4

1

2

+3V_PCH

1 2 36

0.1U_0603_25V7K~D CZ15

1

2

1 2 3

0.1U_0603_25V7K~D 100K_0402_5%~D

CZ18

12

RZ9

10U_0805_10V4Z~D

1U_0603_10V4Z~D

CZ13

1

CZ14

2

0_0402_5%~D

12

@

RZ6

.1U_0402_16V7K~D

10U_0805_10V4Z~D

CZ17

1

CZ16

2

Discharge Circuit

+5VALW

12

RZ46

100K_0402_ 5%~D

SUSP

SSM3K7002F_SC59-3~D

1

D

2

G

@

CZ29

QZ16

S

3

RZ34

470_0603_5 %

2

QZ2A

470_0603_5 %

SUSP

+5VS

RZ43

1 2

2N7002DW-T/R7_SOT363-6

+5VS_D

61

+3VS

12

+3VS_D

3

QZ11B 2N7002DW-T/R7 _SOT363-6

5

4

SUSP

+1.35V

12

RZ37

470_0603_5 %

RZ42

2

G

QZ12

+3V_PCH

2

+1.5V_D

13

D

SUSP

S

SSM3K7002FU_SC70-3~D

12

+3V_D

61

3 3

SYSON#

470_0603_5 %

2N7002DW-T/R7 _SOT363-6

PCH_PWR_EN#

4 4

QZ11A

RZ40

470_0603_5 %

2

G

QZ10

+1.5VS

12

13

+1.5VS_D

D

S

SSM3K7002FU_SC70-3~D

RUN_ON_CPU1.5VS3#6,10

2011/11/22 change to +1.35V_CPU_VDDQ

220_0603_5%~D

12

RZ38

+1.5V_CPU_VDDQ_CHG

SSM3K7002FU_SC70-3~D

13

D

2

G

S

QZ13

SUSP

+0.675VS+1.35V_CPU_VDDQ

22_0603_5%~D

RZ39

2

G

470_0603_5 %

2

12

+DDR_CHG

SSM3K7002FU_SC70-3~D

13

D

S

RZ48

G

QZ14

+1.05VS

12

+1.05VS_D

1 6

+3VALW

RZ44

@

10K_0402_5 %~D

2

G

PCH_PWR_EN#

100K_0402_5%~D

12

RZ52

+5VALW

12

RZ49

100K_0402_ 5%~D

SSM3K7002F_SC59-3~D

1

D

S

3

QZ17

DMN66D0LDW-7_SOT363-6~D

D

QZ21A

S

PCH_PWR_EN26 ,32 SUSP#10,32 ,58,60

SYSON32,58,59

1 2

SYSON#

100K_0402_5%~D

0.1U_0603_25V7K~D

12

1

RZ50

@

CZ30

2

+5VALW

12

RZ45

100K_0402_ 5%~D

SSM3K7002F_SC59-3~D

1

D

2

G

0.1U_0603_25V7K~D

1

CZ28

2

QZ15

S

3

@

100K_0402_5%~D

0.1U_0603_25V7K~D

12

RZ47

1

2

Security Classification

2012/05/14 2013/05/13

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

A

B

C

2012/05/14 2013/05/13

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

DC/DC Interface

LA-9201P

E

45 66Thursday, August 16, 2012

0.1

5

4

3

2

1

PEG_CTX_GRX_N[0..15]5

PEG_CTX_GRX_P[0..15]5

PEG_CRX_GTX_N[0..15]5

PEG_CRX_GTX_P[0..15]5

D D

+1.05VS_VGA

LV30 BLM18PG181SN1D_2P

1 2

180ohms (ESR=0.2) Bead

C C

B B

1 2

RV391 10M_0402_5%

YV3

XTALIN XTAL_OUT

27MHZ_16PF_X5H027000FG1H CV308 22P_0402_50V8J

21

CV309 22P_0402_50V8J

9/20 For Crystal EA request

TO EC

DGPU_PWR_EN32,49,50,62

RV396

A A

CLK_REQ_VGA#16

RV400 0_0402_5%

10K_0402_5%

2

G

1 2

QV25

1 3

D

2N7002H 1N_SOT23-3

@

1 2

5

+3VS_VGA

RV397 10K_0402_5%

1 2

S

CLK_REQ_GPU# VGA_SMB_DA2

RV399

@

10K_0402_5%

1 2

PEG_CTX_GRX_N[0..15]

PEG_CTX_GRX_P[0..15]

PEG_CRX_GTX_N[0..15]

PEG_CRX_GTX_P[0..15]

Under GPU(below 150mils)

1

CV273

2

22U_0805_6.3V6M

4.7U_0402_6.3V6M

PEG_CRX_GTX_P0 PEG_CRX_GTX_N0 PEG_CRX_GTX_P1 PEG_CRX_GTX_N1 PEG_CRX_GTX_P2 PEG_CRX_GTX_N2 PEG_CRX_GTX_P3 PEG_CRX_GTX_N3 PEG_CRX_GTX_P4 PEG_CRX_GTX_N4 PEG_CRX_C_GTX_N4 PEG_CRX_GTX_P5 PEG_CRX_GTX_N5 PEG_CRX_GTX_P6 PEG_CRX_GTX_N6 PEG_CRX_GTX_P7 PEG_CRX_GTX_N7 PEG_CRX_GTX_P8 PEG_CRX_GTX_N8 PEG_CRX_GTX_P9 PEG_CRX_GTX_N9 PEG_CRX_GTX_P10 PEG_CRX_GTX_N10 PEG_CRX_GTX_P11 PEG_CRX_GTX_N11 PEG_CRX_GTX_P12 PEG_CRX_GTX_N12 PEG_CRX_GTX_P13 PEG_CRX_GTX_N13 PEG_CRX_GTX_P14 PEG_CRX_GTX_N14 PEG_CRX_GTX_P15 PEG_CRX_GTX_N15

1

2

CV272

CV274

2

0.1U_0402_10V7K

CV276 0.22U_0402_10V6K CV277 0.22U_0402_10V6K CV278 0.22U_0402_10V6K CV279 0.22U_0402_10V6K CV280 0.22U_0402_10V6K CV281 0.22U_0402_10V6K CV282 0.22U_0402_10V6K CV283 0.22U_0402_10V6K CV284 0.22U_0402_10V6K CV285 0.22U_0402_10V6K CV286 0.22U_0402_10V6K CV287 0.22U_0402_10V6K CV288 0.22U_0402_10V6K CV289 0.22U_0402_10V6K CV290 0.22U_0402_10V6K CV291 0.22U_0402_10V6K CV292 0.22U_0402_10V6K CV293 0.22U_0402_10V6K CV294 0.22U_0402_10V6K CV295 0.22U_0402_10V6K CV296 0.22U_0402_10V6K CV297 0.22U_0402_10V6K CV298 0.22U_0402_10V6K CV299 0.22U_0402_10V6K CV300 0.22U_0402_10V6K CV301 0.22U_0402_10V6K CV302 0.22U_0402_10V6K CV303 0.22U_0402_10V6K CV304 0.22U_0402_10V6K CV305 0.22U_0402_10V6K CV306 0.22U_0402_10V6K CV307 0.22U_0402_10V6K

Differential signal

4

0.1U_0402_10V7K

1

2

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

CLK_PCIE_VGA16 CLK_PCIE_VGA#16

150mA

+SP_PLLVDD

CV275

1 2

RV388 200_0402_1%

2.2K_0402_5%

VGA_SMB_CK2

RV390 2.49K_0402_1%

RV393

PEG_CTX_GRX_P0 PEG_CTX_GRX_N0 PEG_CTX_GRX_P1 PEG_CTX_GRX_N1 PEG_CTX_GRX_P2 PEG_CTX_GRX_N2 PEG_CTX_GRX_P3 PEG_CTX_GRX_N3 PEG_CTX_GRX_P4 PEG_CTX_GRX_N4 PEG_CTX_GRX_P5 PEG_CTX_GRX_N5 PEG_CTX_GRX_P6 PEG_CTX_GRX_N6 PEG_CTX_GRX_P7 PEG_CTX_GRX_N7 PEG_CTX_GRX_P8 PEG_CTX_GRX_N8 PEG_CTX_GRX_P9 PEG_CTX_GRX_N9 PEG_CTX_GRX_P10 PEG_CTX_GRX_N10 PEG_CTX_GRX_P11 PEG_CTX_GRX_N11 PEG_CTX_GRX_P12 PEG_CTX_GRX_N12 PEG_CTX_GRX_P13 PEG_CTX_GRX_N13 PEG_CTX_GRX_P14 PEG_CTX_GRX_N14 PEG_CTX_GRX_P15 PEG_CTX_GRX_N15

1 2

+3VS_VGA

RV394

2.2K_0402_5%

1 2

QV2A

2N7002DW-T/R7_SOT363-6

RV398 0_0402_5%

PEG_CRX_C_GTX_P0 PEG_CRX_C_GTX_N0 PEG_CRX_C_GTX_P1 PEG_CRX_C_GTX_N1 PEG_CRX_C_GTX_P2 PEG_CRX_C_GTX_N2 PEG_CRX_C_GTX_P3 PEG_CRX_C_GTX_N3 PEG_CRX_C_GTX_P4

PEG_CRX_C_GTX_P5 PEG_CRX_C_GTX_N5 PEG_CRX_C_GTX_P6 PEG_CRX_C_GTX_N6 PEG_CRX_C_GTX_P7 PEG_CRX_C_GTX_N7 PEG_CRX_C_GTX_P8 PEG_CRX_C_GTX_N8 PEG_CRX_C_GTX_P9 PEG_CRX_C_GTX_N9 PEG_CRX_C_GTX_P10 PEG_CRX_C_GTX_N10 PEG_CRX_C_GTX_P11 PEG_CRX_C_GTX_N11 PEG_CRX_C_GTX_P12 PEG_CRX_C_GTX_N12 PEG_CRX_C_GTX_P13 PEG_CRX_C_GTX_N13 PEG_CRX_C_GTX_P14 PEG_CRX_C_GTX_N14 PEG_CRX_C_GTX_P15 PEG_CRX_C_GTX_N15

CLK_PCIE_VGA CLK_PCIE_VGA# CLK_REQ_GPU#

PEX_TSTCLK_OUT PEX_TSTCLK_OUT#

PLTRST_VGA#

PEX_TERMP

+3VS_VGA

4

2N7002DW-T/R7_SOT363-6

1 2

RV395 0_0402_5%

2

61

1 2

@

5

@

QV2B

UV23A

AN12

PEX_RX0

AM12

PEX_RX0_N

AN14

PEX_RX1

AM14

PEX_RX1_N

AP14

PEX_RX2

AP15

PEX_RX2_N

AN15

PEX_RX3

AM15

PEX_RX3_N

AN17

PEX_RX4

AM17

PEX_RX4_N

AP17

PEX_RX5

AP18

PEX_RX5_N

AN18

PEX_RX6

AM18

PEX_RX6_N

AN20

PEX_RX7

AM20

PEX_RX7_N

AP20

PEX_RX8

AP21

PEX_RX8_N

AN21

PEX_RX9

AM21

PEX_RX9_N

AN23

PEX_RX10

AM23

PEX_RX10_N

AP23

PEX_RX11

AP24

PEX_RX11_N

AN24

PEX_RX12

AM24

PEX_RX12_N

AN26

PEX_RX13

AM26

PEX_RX13_N

AP26

PEX_RX14

AP27

PEX_RX14_N

AN27

PEX_RX15

AM27

PEX_RX15_N

AK14

PEX_TX0

AJ14

PEX_TX0_N

AH14

PEX_TX1

AG14

PEX_TX1_N

AK15

PEX_TX2

AJ15

PEX_TX2_N

AL16

PEX_TX3

AK16

PEX_TX3_N

AK17

PEX_TX4

AJ17

PEX_TX4_N

AH17

PEX_TX5

AG17

PEX_TX5_N

AK18

PEX_TX6

AJ18

PEX_TX6_N

AL19

PEX_TX7

AK19

PEX_TX7_N

AK20

PEX_TX8

AJ20

PEX_TX8_N

AH20

PEX_TX9

AG20

PEX_TX9_N

AK21

PEX_TX10

AJ21

PEX_TX10_N

AL22

PEX_TX11

AK22

PEX_TX11_N

AK23

PEX_TX12

AJ23

PEX_TX12_N

AH23

PEX_TX13

AG23

PEX_TX13_N

AK24

PEX_TX14

AJ24

PEX_TX14_N

AL25

PEX_TX15

AK25

PEX_TX15_N

AJ11

PEX_WAKE_N

AL13

PEX_REFCLK

AK13

PEX_REFCLK_N

AK12

PEX_CLKREQ_N

AJ26

PEX_TSTCLK_OUT

AK26

PEX_TSTCLK_OUT_N

AJ12

PEX_RST_N

AP29

PEX_TERMP

N13P-PES-A1_FCBGA908

14EGE@

3

Part 1 of 7

PCI EXPRESS

EC_SMB_CK2 17,32,42,43

VGA EC thermal sensor

EC_SMB_DA2 17,32,42,43

PU AT EC SIDE, +3VS AND 4.7K

3

GPIO

DACA_GREEN

DACA_HSYNC DACA_VSYNC

DACs

I2C

CLK

XTAL_OUTBUFF

DGPU_HOLD_RST#32

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8

GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21

DACA_RED

DACA_BLUE

DACA_VDD DACA_VREF DACA_RSET

I2CA_SCL

I2CA_SDA

I2CB_SCL

I2CB_SDA

I2CC_SCL

I2CC_SDA

I2CS_SCL I2CS_SDA

PLLVDD

SP_PLLVDD

VID_PLLVDD

XTAL_IN

XTAL_OUT

XTAL_SSIN

PCH_PLTRST#15

P6 M3 L6 P5 P7 L7 M7 N8 M1 M2 L1 M5 N3 M4 N4 P2 R8 M6 R1 P3 P4 P1

AK9 AL10 AL9

AM9 AN9

AG10 AP9 AP8

R4 R5

R7 R6

R2 R3

T4 T3

AD8

AE8

AD7

H3 H2

J4 H1

1 2

RV682 0_0402_5%@

DGPU_BL_PWM DGPU_ENVDD DGPU_BKL_EN STDBY_EN

OVERT#

VGA_AC_DET_R

GC6_EVENT#_R VGA_DPC_HPD NVVDD PSI

+DACA_VDD

VGA_CRT_CLK VGA_CRT_DATA

I2CB_SCL

I2CB_SDA

VGA_EDID_CLK VGA_EDID_DATA

VGA_SMB_CK2 VGA_SMB_DA2

78mA

+PLLVDD

71mA

41mA

XTALIN XTAL_OUT

XTALOUT XTALSSIN

1 2

RV378 10K_0402_5%

1 2

RV386 0_0402_5%@

1 2

Internal Thermal Sensor

TO EC

DGPU_HOLD_RST#

PCH_PLTRST#

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMP AL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMP AL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

FB_CLAMP 50

DGPU_BL_PWM 24 DGPU_ENVDD 24 DGPU_BKL_EN 24 STDBY_EN 62

NVVDD PWM_VID

VGA_DPC_HPD 23

NVVDD PSI 62 GPU_DPB_HPD 24 VGA_HDMI_DET 27 VGA_DMC_HPD 30

RV38910K_0402_5%

10K_0402_5%

+3VS_VGA

5

1

P

B

2

A

G

3

RV392

0.1U_0402_25V6K~D

O

TC7SH08FU_SSOP5~D

NVVDD PWM_VID 62

RV371 100K_0402_5%~D

1 2

MEM_VREF 51,52,53,54

Vendor recommand reserve PU/PD resistor

+3VS_VGA

RV383 10K_0402_5%

1 2

+SP_PLLVDD

12

CH147

1 2

4

UH6

2012/05/10 2013/12/31

DV14

RB751V-40_SOD323-2

+3VS_VGA

RH215 100K_0402_5%~D

@

1 2

12

RH196 100K_0402_5%~D

Compal Secret Data

2

12

to EC in

GC6_EVENT#32

PLTRST_VGA#

Deciphered Date

Under GPU Near GPU

TO EC

VGA_AC_DET 32

+PLLVDD

GC6

2

G

QV24

1 3

D

S

2N7002H 1N_SOT23-3

1

CV310

2

0.1U_0402_10V7K

22U_0805_6.3V6M

QV58 2N7002H 1N_SOT23-3

D

S

OVERT#

PLTRST_VGA#

VGA_EDID_CLK

VGA_EDID_DATA

VGA_CRT_DATA

VGA_CRT_CLK

I2CB_SCL

I2CB_SDA

GC6_EVENT#_RGC6_EVENT#

LV31

1 2

BLM18PG181SN1D_2P

1

30 ohms @100MHz (ESR=0.05)

CV311

2

Title

Size Document Number Rev

Date: Sheet of

13

H_THERMTRIP#

G

2

1 2

RV373 2.2K_0402_5%

1 2

RV374 2.2K_0402_5%

1 2

RV375 2.2K_0402_5%

1 2

RV376 2.2K_0402_5%

1 2

RV377 2.2K_0402_5%

1 2

RV379 2.2K_0402_5%

OVERT#

NVVDD PSI

DGPU_BKL_EN

DGPU_ENVDD

VGA_DPC_HPD

GPU_DPB_HPD

VGA_HDMI_DET

VGA_DMC_HPDVGA_AC_DETVGA_AC_DET_R

DGPU_BL_PWM

+3VS_VGA+3VS_VGA

RV387 10K_0402_5%

1 2

RV380 10K_0402_5%

1 2

RV683 10K_0402_1%

1 2

RV672 10K_0402_5%

1 2

RV671 10K_0402_5%

1 2

RV381 10K_0402_5%

1 2

RV382 10K_0402_5%

1 2

RV384 10K_0402_5%

1 2

RV385 10K_0402_5%

RV550 100K_0402_5%~D

+1.05VS_VGA

DGPU_HOLD_RST#

Compal Electronics, Inc.

N14P-PCIE/DAC/GPIO

LA-9201P

1

H_THERMTRIP# 6,19

+3VS_VGA

12

+3VS

RH32710K_0402_5%~D @

0.1

46 66Tuesday, August 21, 2012

5

D D

VGA_DPC_P023 VGA_DPC_N023 VGA_DPC_P123

TO MB DP

VGA_DPC_N123 VGA_DPC_P223 VGA_DPC_N223 VGA_DPC_P323 VGA_DPC_N323

4

UV23D

AM6 AN6

AP3 AN3 AN5 AM5

AL6

AK6

AJ6 AH6

AJ9 AH9

AP6

AP5 AM7

AL7 AN8 AM8

AK8

AL8

AK1

AJ1

AJ3

AJ2 AH3 AH4 AG5 AG4

IFPA_TXC IFPA_TXC_N IFPA_TXD0 IFPA_TXD0_N IFPA_TXD1 IFPA_TXD1_N IFPA_TXD2 IFPA_TXD2_N IFPA_TXD3 IFPA_TXD3_N

IFPB_TXC IFPB_TXC_N IFPB_TXD4 IFPB_TXD4_N IFPB_TXD5 IFPB_TXD5_N IFPB_TXD6 IFPB_TXD6_N IFPB_TXD7 IFPB_TXD7_N

IFPC_L0 IFPC_L0_N IFPC_L1 IFPC_L1_N IFPC_L2 IFPC_L2_N IFPC_L3 IFPC_L3_N

Part 4 of 7

3

NC NC NC NC NC NC NC NC NC NC NC

NC

NC NC NC

VDD_SENSE

GND_SENSE

P8 AC6 AJ28 AJ4 AJ5 AL11 C15 D19 D20 D23 D26 H31 T8 V32

L4

L5

VCCSENSE_VGA

VSSSENSE_VGA

2

VCCSENSE_VGA 62

VSSSENSE_VGA 62

trace width: 16mils differential voltage sensing. differential signal routing.

1

TEST

MXM_TX0P24 MXM_TX0N24

TO eDP

C C

GPU_HDMI_TXD2+27 GPU_HDMI_TXD2-27 GPU_HDMI_TXD1+27 GPU_HDMI_TXD1-27

TO MB HDMI

GPU_HDMI_TXD0+27 GPU_HDMI_TXD0-27 GPU_HDMI_TXC+27 GPU_HDMI_TXC-27

DMC TO HDMI

B B

Decive ID change to 0x1056

VGA_DPD_AUXP/DDC30 VGA_DPD_AUXN/DDC30

MXM_TX1P24 MXM_TX1N24 MXM_TX2P24 MXM_TX2N24 MXM_TX3P24 MXM_TX3N24

GPU_HDMI_TXD2+ GPU_HDMI_TXD2GPU_HDMI_TXD1+ GPU_HDMI_TXD1GPU_HDMI_TXD0+ GPU_HDMI_TXD0GPU_HDMI_TXC+ GPU_HDMI_TXC-

VGA_DPD_P030 VGA_DPD_N030 VGA_DPD_P130 VGA_DPD_N130 VGA_DPD_P230 VGA_DPD_N230 VGA_DPD_P330 VGA_DPD_N330

VGA_DPC_AUXP/DDC23 VGA_DPC_AUXN/DDC23

GPU_DPB_AUXP/DDC24 GPU_DPB_AUXN/DDC24

GPU_HDMI_SCLK27

GPU_HDMI_SDATA27

GPU_HDMI_SCLK GPU_HDMI_SDATA

VGA_DPD_AUXP/DDC VGA_DPD_AUXN/DDC

AM1

IFPD_L0

AM2

IFPD_L0_N

AM3

IFPD_L1

AM4

IFPD_L1_N

AL3

IFPD_L2

AL4

IFPD_L2_N

AK4

IFPD_L3

AK5

IFPD_L3_N

AD2

IFPE_L0

AD3

IFPE_L0_N

AD1

IFPE_L1

AC1

IFPE_L1_N

AC2

IFPE_L2

AC3

IFPE_L2_N

AC4

IFPE_L3

AC5

IFPE_L3_N

AE3

IFPF_L0

AE4

IFPF_L0_N

AF4

IFPF_L1

AF5

IFPF_L1_N

AD4

IFPF_L2

AD5

IFPF_L2_N

AG1

IFPF_L3

AF1

IFPF_L3_N

AG3

IFPC_AUX_I2CW_SCL

AG2

IFPC_AUX_I2CW_SDA_N

AK3

IFPD_AUX_I2CX_SCL

AK2

IFPD_AUX_I2CX_SDA_N

AB3

IFPE_AUX_I2CY_SCL

AB4

IFPE_AUX_I2CY_SDA_N

AF3

IFPF_AUX_I2CZ_SCL

AF2

IFPF_AUX_I2CZ_SDA_N

TESTMODE

JTAG_TCK

JTAG_TDO JTAG_TMS

JTAG_TRST_N

SERIAL

ROM_CS_N ROM_SCLK

LVDS/TMDS

GENERAL

BUFRST_N

MULTI_STRAP_REF0_GND

THERMDN

JTAG_TDI

ROM_SI

ROM_SO

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

THERMDP

CEC

AK11

AM10 AM11 AP12 AP11 AN11

H6 H4 H5 H7

L2

L3

J1

J2 J7 J6 J5 J3

K3 K4

TESTMODE0

TESTMODE1

1 2

RV403 10K_0402_5%

ROM_CS ROM_SCLK ROM_SI ROM_SO

RV404 10K_0402_5%

1 2

RV405 10K_0402_5%@

1 2

RV406 40.2K_0402_1%

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

TV1 TV2 TV3

ROM_CS 55 ROM_SCLK 55 ROM_SI 55 ROM_SO 55

12

STRAP0 55 STRAP1 55 STRAP2 55 STRAP3 55 STRAP4 55

12

10K_0402_5% RV401

+3VS_VGA

12

10K_0402_5% RV402

1 2

RV407 100K_0402_5%~D

1 2

RV408 100K_0402_5%~D

1 2

RV409 100K_0402_5%~D

1 2

RV410 100K_0402_5%~D

A A

+3VS_VGA

VGA_DPC_AUXP/DDC

VGA_DPC_AUXN/DDC

GPU_DPB_AUXP/DDC

GPU_DPB_AUXN/DDC

1 2

RV411 2.2K_0402_5%

1 2

RV412 2.2K_0402_5%

1 2

RV413 2.2K_0402_5%

1 2

RV414 2.2K_0402_5%

5

GPU_HDMI_SCLK

GPU_HDMI_SDATA

VGA_DPD_AUXP/DDC

VGA_DPD_AUXN/DDC

N13P-PES-A1_FCBGA908

14EGE@

Security Classification

2012/05/10 2013/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

4

3

2012/05/10 2013/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N14P-eDP/HDMI/DP/THM

LA-9201P

1

47 66Tuesday, August 21, 2012

0.1

5

4

3

2

1

UV23E

+1.35VS_VGA

D D

+1.35VS_VGA

1

CV344

2

1U_0402_6.3V6K

C C

1U_0402_6.3V6K

CALIBRATION PIN

FB_CAL_x_PD_VDDQ

FB_CAL_x_PU_GND

FB_CAL_xTERM_GND

For GDDR5 setting. Near GPU

1

CV321

2

4.7U_0603_6.3V6K

1

CV322

2

4.7U_0603_6.3V6K

1

CV323

CV324

2

4.7U_0603_6.3V6K

1

CV326

CV325

2

10U_0603_6.3V6M

4.7U_0603_6.3V6K

Under GPU(below 150mils)

1

2

1

CV345

CV346

2

1U_0402_6.3V6K

1

CV319

CV318

2

1U_0402_6.3V6K

CV347

2

1U_0402_6.3V6K

FB_VDDQ_SENSE65

GDDR5

40.2Ohm

60.4Ohm

AA27

FBVDDQ_0

AA30

FBVDDQ_1

2

CV327

CV328

1

10U_0603_6.3V6M

1

CV348

2

0.1U_0402_10V7K

2

CV329

CV313

1

22U_0805_6.3V6M

10U_0603_6.3V6M

1

CV349

CV350

2

0.1U_0402_10V7K

RV418 0_0402_5%

RV420 0_0402_5%

1

CV330

2

22U_0805_6.3V6M

1

CV351

2

0.1U_0402_10V7K

1 2

+1.35VS_VGA

1

CV331

22U_0805_6.3V6M

1

CV320

2

RV421 40.2_0402_1%

RV423 40.2_0402_1%

RV424 60.4_0402_1%

1

CV314

2

22U_0805_6.3V6M

1

CV352

2

0.1U_0402_10V7K

FB_VDDQ_SENSE_R

FB_VSS_SENSE

1 2

CV332

AB27

FBVDDQ_2

AB33

FBVDDQ_3

AC27

FBVDDQ_4

AD27

FBVDDQ_5

AE27

FBVDDQ_6

AF27

FBVDDQ_7

AG27

FBVDDQ_8

B13

FBVDDQ_9

B16

FBVDDQ_10

B19

FBVDDQ_11

E13

FBVDDQ_12

E16

FBVDDQ_13

E19

FBVDDQ_14

H10

FBVDDQ_15

H11

FBVDDQ_16

H12

FBVDDQ_17

H13

FBVDDQ_18

H14

FBVDDQ_19

H15

FBVDDQ_20

H16

FBVDDQ_21

H18

FBVDDQ_22

H19

FBVDDQ_23

H20

FBVDDQ_24

H21

FBVDDQ_25

H22

FBVDDQ_26

H23

FBVDDQ_27

H24

FBVDDQ_28

H8

FBVDDQ_29

H9

FBVDDQ_30

L27

FBVDDQ_31

M27

FBVDDQ_32

N27

FBVDDQ_33

P27

FBVDDQ_34

R27

FBVDDQ_35

T27

FBVDDQ_36

T30

FBVDDQ_37

T33

FBVDDQ_38

V27

FBVDDQ_39

W27

FBVDDQ_40

W30

FBVDDQ_41

W33

FBVDDQ_42

Y27

FBVDDQ_43

F1

FB_VDDQ_SENSE

F2

FB_GND_SENSE

J27

FB_CAL_PD_VDDQ

H27

FB_CAL_PU_GND

H25

FB_CAL_TERM_GND

Place near balls

Part 5 of 7

PEX_IOVDD_0 PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4 PEX_IOVDD_5

PEX_IOVDDQ_0 PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8

PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13

PEX_PLL_HVDD

PEX_SVDD_3V3

POWER

PEX_PLLVDD

IFPAB_PLLVDD

IFPAB_RSET

IFPA_IOVDD IFPB_IOVDD

IFPC_PLLVDD

IFPC_RSET

IFPC_IOVDD

IFPD_PLLVDD

IFPD_RSET

IFPD_IOVDD

IFPEF_PLVDD

IFPEF_RSET

IFPE_IOVDD IFPF_IOVDD

VDD33_0 VDD33_1 VDD33_2 VDD33_3

3300mA

AG19 AG21 AG22 AG24 AH21 AH25

AG13 AG15 AG16 AG18 AG25 AH15 AH18 AH26 AH27 AJ27 AK27 AL27 AM28 AN28

AH12

AG12

150mA

AG26

+VDD33

J8 K8 L8 M8

AH8

+IFPAB_PLLVDD

AJ8

AG8

+IFPAB_IOVDD

AG9

AF7

+IFPCD_PLLVDD

AF8

AF6

+IFPCD_IOVDD

AG7

+IFPCD_PLLVDD

AN2

AG6

+IFPCD_IOVDD

AB8

+IFPEF_PLLVDD

AD6

AC7

+IFPEF_IOVDD

AC8

+PEX_PLLHVDD

+PEX_PLLVDD

85mA

IFPC_RSET

IFPD_RSET

IFPEF_RSET

1

CV333

CV334

2

1U_0402_6.3V6K

22U_0805_6.3V6M

1U_0402_6.3V6K

1

CV317

CV316

2

22U_0805_6.3V6M

For N13P-GT/N13E-GE

1 2

RV415 0_0402_5%

+PEX_SVDD3V3

+VDD33

1 2

85mA

RV41710K_0402_5%

RV41910K_0402_5%

1

CV335

2

1U_0402_6.3V6K

1

CV342

2

22U_0805_6.3V6M

C/D

+3VS_VGA

B B

+1.05VS_VGA

LV32

MMZ1608R301AT_2P~D

1 2

4.7U_0603_6.3V6K~D

CV363

1

2

LV34

BLM18PG221SN1D_2P~D

1 2

1U_0402_6.3V6K~D

CV374

1

4.7U_0603_6.3V6K~D

1U_0603_10V6K~D

CV364

CV365

1

2

4.7U_0603_6.3V6K~D

CV375

1

2

1U_0402_6.3V6K~D

0.1U_0402_10V7K~D

CV376

CV377

1

+IFPCD_PLLVDD

0.1U_0402_10V7K~D

CV366

1

2

+IFPCD_IOVDD

0.1U_0402_10V7K~D

CV378

1

220mA

0.1U_0402_10V7K~D

CV367

1

2

176mA

0.1U_0402_10V7K~D

1

0.1U_0402_10V7K~D

CV368

0.1U_0402_10V7K~D

CV380

CV379

1

E/F

+3VS_VGA

LV33

MMZ1608R301AT_2P~D

1 2

4.7U_0603_6.3V6K~D

CV369

1

2

N13P-PES-A1_FCBGA908

14EGE@

1U_0603_10V6K~D

CV370

1

2

0.1U_0402_10V7K~D

CV371

200mA

+IFPEF_PLLVDD

0.1U_0402_10V7K~D

CV372

1

2

0.1U_0402_10V7K~D

CV373

1

2

1

2

1U_0402_6.3V6K

1

2

22U_0805_6.3V6M

210mA

Near GPU

1

CV315

4.7U_0603_6.3V6K

+1.05VS_VGA

CV343

1

CV336

2

4.7U_0603_6.3V6K

0.1U_0402_10V7K

2

CV337

2

1

10U_0603_6.3V6M

1

CV353

2

4.7U_0603_6.3V6K

Place near balls Place near GPU

1

2

0.1U_0402_10V7K

1

2

CV356

CV338

CV354

0.1U_0402_10V7K

2

1

10U_0603_6.3V6M

+3VS_VGA

4.7U_0603_6.3V6K

1

CV357

2

CV339

10U_0603_6.3V6M

1

CV355

2

1U_0402_6.3V6K

150mA

+PEX_PLLVDD

1

CV360

2

0.1U_0402_10V7K

Place near balls

IFPC_RSET

IFPD_RSET

IFPEF_RSET

1 2

1U_0603_10V6K

1 2

RV425

1K_0402_1%~D

RV426

1K_0402_1%~D

1 2

RV427

1K_0402_1%~D

+1.05VS_VGA

2

CV340

1

CV358

2

4.7U_0603_6.3V6K

1

CV361

2

CV341

1

10U_0603_6.3V6M

+3VS_VGA

0_0603_5%

12

RV416

1

CV359

2

0_0603_5%

1

CV362

2

4.7U_0805_25V6-K

RV422

N14M 120ohms @100MHz (ESR=0.18)

+1.05VS_VGA

12

2

A A

2

5

2

4

+1.05VS_VGA

1

2

LV35

BLM18PG221SN1D_2P~D

1 2

1U_0402_6.3V6K~D

CV381

1

2

4.7U_0603_6.3V6K~D

CV382

72mA

+IFPEF_IOVDD

1U_0603_10V6K~D

CV383

1

2

0.1U_0402_10V7K~D

CV385

CV384

1

2

Security Classification

2012/05/10 2013/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/05/10 2013/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

N14P-POWER

LA-9201P

1

48 66Tuesday, August 14, 2012

0.1

5

57890mA

V17 V18 V20 V22 W12 W14 W16 W19 W21 W23 Y13 Y15 Y17 Y18 Y20 Y22

U1 U2 U3 U4 U5 U6 U7 U8

V1 V2 V3 V4 V5 V6 V7 V8

W2 W3 W4 W5 W7 W8

Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8

AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8

+VGA_CORE

DGPU_PW R_EN32,46,49,5 0,62

GPU_PGOO D50,62,65

DGPU_PW R_EN32,46,49,5 0,62

+VGA_CORE

D D

C C

B B

A A

UV23G

AA12

VDD_0

AA14

VDD_1

AA16

VDD_2

AA19

VDD_3

AA21

VDD_4

AA23

VDD_5

AB13

VDD_6

AB15

VDD_7

AB17

VDD_8

AB18

VDD_9

AB20

VDD_10

AB22

VDD_11

AC12

VDD_12

AC14

VDD_13

AC16

VDD_14

AC19

VDD_15

AC21

VDD_16

AC23

VDD_17

M12

VDD_18

M14

VDD_19

M16

VDD_20

M19

VDD_21

M21

VDD_22

M23

VDD_23

N13

VDD_24

N15

VDD_25

N17

VDD_26

N18

VDD_27

N20

VDD_28

N22

VDD_29

P12

VDD_30

P14

VDD_31

P16

VDD_32

P19

VDD_33

P21

VDD_34

P23

VDD_35

R13

VDD_36

R15

VDD_37

R17

VDD_38

R18

VDD_39

R20

VDD_40

R22

VDD_41

T12

VDD_42

T14

VDD_43

T16

VDD_44

T19

VDD_45

T21

VDD_46

T23

VDD_47

U13

VDD_48

U15

VDD_49

U17

VDD_50

U18

VDD_51

U20

VDD_52

U22

VDD_53

V13

VDD_54

V15

VDD_55

N13P-PES-A 1_FCBGA90 8

14EGE@

Part 7 of 7

POWER

VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62 VDD_63 VDD_64 VDD_65 VDD_66 VDD_67 VDD_68 VDD_69 VDD_70 VDD_71

XVDD_1 XVDD_2 XVDD_3 XVDD_4 XVDD_5 XVDD_6 XVDD_7 XVDD_8

XVDD_9 XVDD_10 XVDD_11 XVDD_12 XVDD_13 XVDD_14 XVDD_15 XVDD_16

XVDD_17 XVDD_18 XVDD_19 XVDD_20 XVDD_21 XVDD_22

XVDD_23 XVDD_24 XVDD_25 XVDD_26 XVDD_27 XVDD_28 XVDD_29 XVDD_30

XVDD_31 XVDD_32 XVDD_33 XVDD_34 XVDD_35 XVDD_36 XVDD_37 XVDD_38

4

+3VALW

2

@

1 2

RV437 0_0 402_5%

1 2

RV438 0 _0402_5 %

470K_0402_5%~D

12

RV428

3_VGA_V TT_ON#

61

QV6A

2N7002DW-T/R7_SOT363-6

2

100P_0402_50V8J~D

1

CV391

2

B+_BIAS

100K_0402_5%~D

12

RV429

3

QV6B

5

4

+3VALW

470K_0402_5%~D

12

RV433

12

RV436 100K _0402_5 %~D

61

QV7A

2N7002DW-T/R7_SOT363-6

1.05V_VG A_VTT_ON#

2N7002DW-T/R7_SOT363-6

0.047U_0402_25V~D

1

CV390

2

+3VS

3.3V_RUN_G FX_EN

4.7M_0402_5%~D

12

RV431

5

3

QV26

SI3456DDV-T1 -GE3_TSOP 6~D

D

6

2 1

3

4

G

B+_BIAS

12

QV7B

2N7002DW-T/R7_SOT363-6

S

45

3

1

2

470K_0402_5%~D

1

2

220P_0402_25V8J

CV387

RV432

2.2M_0402_5%

12

RV435

+3VS_VGA

10U_0603_6.3V6M~D

39_0402_5%~D

12

CV386

RV430

@

SSM3K7002FU_SC70-3~D

+3.3V_RUN_GFX_CHG

QV27

@

13

D

S

+1.05VS_VGA

+1.05VS

SI4164DY-T1-GE 3_SO8~D

8 7

5

+1.05VS_ VGA +3VALW

RV599

S

+3VS_VGA

2

3_VGA_V TT_ON#

G

QV28

4

100P_0402_50V8J~D

1

2

12

1 2

1K_0402_1%~D

G

2

13

D

QV55 AO3414_ SOT23-3

2

UV23F

A2

GND_0

AA17

GND_1

AA18

GND_2

AA20

GND_3

AA22

GND_4

AB12

GND_5

AB14

GND_6

AB16

GND_7

AB19

GND_8

AB2

GND_9

AB21

GND_10

A33

GND_11

AB23

GND_12

AB28

GND_13

AB30

GND_14

AB32

GND_15

AB5

GND_16

AB7

GND_17

AC13

GND_18

AC15

GND_19

AC17

GND_20

AC18

GND_21

AA13

GND_22

AC20

GND_23

AC22

GND_24

AE2

GND_25

AE28

GND_26

AE30

GND_27

AE32

GND_28

AE33

GND_29

AE5

GND_30

AE7

GND_31

AH10

GND_32

AA15

GND_33

AH13

GND_34

+1.05VS_ VGA

1 2 36

CV389

RV548

10K_0402_5%

2

39_0402_5%~D

10U_0603_6.3V6M~D

12

RV434

CV388

1

2

@

SSM3K7002FU_SC70-3~D

+1.05V_PEX_VDD_CHG

QV29

13

D

2

1.05V_VG A_VTT_ON#

G

@

S

G

QV39 2N7002H 1 N_SOT23-3

D

1 3

DGPU_PW ROK 23 ,32

TO EC

RV549

1 2

10K_0402_5%

+3VS

AH16 AH19

AH2 AH22 AH24 AH28 AH29 AH30 AH32 AH33

AH5

AH7

AJ7

AK10

AK7

AL12 AL14 AL15 AL17 AL18

AL2 AL20 AL21 AL23 AL24 AL26 AL28 AL30 AL32 AL33

AL5

AM13 AM16 AM19 AM22 AM25

AN1 AN10 AN13 AN16 AN19 AN22 AN25 AN30 AN34

AN4

AN7

AP2 AP33

B10 B22 B25 B28 B31 B34

C10

C13

C19

C22

C25

C28

GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67 GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82 GND_83

B1

GND_84 GND_85 GND_86 GND_87 GND_88 GND_89 GND_90

B4

GND_91

B7

GND_92 GND_93 GND_94 GND_95 GND_96 GND_97 GND_98

C7

GND_99

Part 6 of 7

1

GND

GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 GND_120 GND_121 GND_122 GND_123 GND_124 GND_125 GND_126 GND_127 GND_128 GND_129 GND_130 GND_131 GND_132 GND_133 GND_134 GND_135 GND_136 GND_137 GND_138 GND_139 GND_140 GND_141 GND_142 GND_143 GND_144 GND_145 GND_146 GND_147 GND_148 GND_149 GND_150 GND_151 GND_152 GND_153 GND_154 GND_155 GND_156 GND_157 GND_158 GND_159 GND_160 GND_161 GND_162 GND_163 GND_164 GND_165 GND_166 GND_167 GND_168 GND_169 GND_170 GND_171 GND_172 GND_173 GND_174 GND_175 GND_176 GND_177 GND_178 GND_179 GND_180 GND_181 GND_182 GND_183 GND_184 GND_185 GND_186 GND_187 GND_188 GND_189 GND_190 GND_191 GND_192 GND_193 GND_194 GND_195 GND_196 GND_197 GND_198

GND_199 GND_OPT GND_OPT

D2 D31 D33 E10 E22 E25 E5 E7 F28 F7 G10 G13 G16 G19 G2 G22 G25 G28 G3 G30 G32 G33 G5 G7 K2 K28 K30 K32 K33 K5 K7 M13 M15 M17 M18 M20 M22 N12 N14 N16 N19 N2 N21 N23 N28 N30 N32 N33 N5 N7 P13 P15 P17 P18 P20 P22 R12 R14 R16 R19 R21 R23 T13 T15 T17 T18 T2 T20 T22 AG11 T28 T32 T5 T7 U12 U14 U16 U19 U21 U23 V12 V14 V16 V19 V21 V23 W13 W15 W17 W18 W20 W22 W28 Y12 Y14 Y16 Y19 Y21 Y23 AH11 C16 W32

Security Classification

2012/05/10 2013/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2012/05/10 2013/12/31

Compal Secret Data

Deciphered Date

N13P-PES-A 1_FCBGA90 8

Compal Electronics, Inc.

Title

Size Documen t Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

14EGE@

N14P-VGA CORE, GND

LA-9201P

1

0.1

49 66Tuesday, A ugust 14, 2012

5

4

3

2

1

FBC_D[0..63]

FBA_CKE_L 51

FBA_CKE_H 52

FBC_DBI0#53 FBC_DBI1#53 FBC_DBI2#53 FBC_DBI3#53 FBC_DBI4#54 FBC_DBI5#54 FBC_DBI6#54 FBC_DBI7#54

12

RV456 10K_0402_5%

FBC_D0 FBC_D1 FBC_D2 FBC_D3 FBC_D4 FBC_D5 FBC_D6 FBC_D7 FBC_D8

FBC_D9 FBC_D10 FBC_D11 FBC_D12 FBC_D13 FBC_D14 FBC_D15 FBC_D16 FBC_D17 FBC_D18 FBC_D19 FBC_D20 FBC_D21 FBC_D22 FBC_D23 FBC_D24 FBC_D25 FBC_D26 FBC_D27 FBC_D28 FBC_D29 FBC_D30 FBC_D31 FBC_D32 FBC_D33 FBC_D34 FBC_D35 FBC_D36 FBC_D37 FBC_D38 FBC_D39 FBC_D40 FBC_D41 FBC_D42 FBC_D43 FBC_D44 FBC_D45 FBC_D46 FBC_D47 FBC_D48 FBC_D49 FBC_D50 FBC_D51 FBC_D52 FBC_D53 FBC_D54 FBC_D55 FBC_D56 FBC_D57 FBC_D58 FBC_D59 FBC_D60 FBC_D61 FBC_D62 FBC_D63

FBC_DBI0# FBC_DBI1# FBC_DBI2# FBC_DBI3# FBC_DBI4# FBC_DBI5# FBC_DBI6# FBC_DBI7#

FBC_EDC0 FBC_EDC1 FBC_EDC2 FBC_EDC3 FBC_EDC4 FBC_EDC5 FBC_EDC6 FBC_EDC7

RV457 10K_0402_5%

UV23C

G9

FBB_D0

E9

FBB_D1

G8

FBB_D2

F9

FBB_D3

F11

FBB_D4

G11

FBB_D5

F12

FBB_D6

G12

FBB_D7

G6

FBB_D8

F5

FBB_D9

E6

FBB_D10

F6

FBB_D11

F4

FBB_D12

G4

FBB_D13

E2

FBB_D14

F3

FBB_D15

C2

FBB_D16

D4

FBB_D17

D3

FBB_D18

C1

FBB_D19

B3

FBB_D20

C4

FBB_D21

B5

FBB_D22

C5

FBB_D23

A11

FBB_D24

C11

FBB_D25

D11

FBB_D26

B11

FBB_D27

D8

FBB_D28

A8

FBB_D29

C8

FBB_D30

B8

FBB_D31

F24

FBB_D32

G23

FBB_D33

E24

FBB_D34

G24

FBB_D35

D21

FBB_D36

E21

FBB_D37

G21

FBB_D38

F21

FBB_D39

G27

FBB_D40

D27

FBB_D41

G26

FBB_D42

E27

FBB_D43

E29

FBB_D44

F29

FBB_D45

E30

FBB_D46

D30

FBB_D47

A32

FBB_D48

C31

FBB_D49

C32

FBB_D50

B32

FBB_D51

D29

FBB_D52

A29

FBB_D53

C29

FBB_D54

B29

FBB_D55

B21

FBB_D56

C23

FBB_D57

A21

FBB_D58

C21

FBB_D59

B24

FBB_D60

C24

FBB_D61

B26

FBB_D62

C26

FBB_D63

E11

FBB_DQM0

E3

FBB_DQM1

A3

FBB_DQM2

C9

FBB_DQM3

F23

FBB_DQM4

F27

FBB_DQM5

C30

FBB_DQM6

A24

FBB_DQM7

D10

FBB_DQS_WP0

D5

FBB_DQS_WP1

C3

FBB_DQS_WP2

B9

FBB_DQS_WP3

E23

FBB_DQS_WP4

E28

FBB_DQS_WP5

B30

FBB_DQS_WP6

A23

FBB_DQS_WP7

D9

FBB_DQS_RN0

E4

FBB_DQS_RN1

B2

FBB_DQS_RN2

A9

FBB_DQS_RN3

D22

FBB_DQS_RN4

D28

FBB_DQS_RN5

A30

FBB_DQS_RN6

B23

FBB_DQS_RN7

N13P-PES-A1_FCBGA908

14EGE@

Part 3 of 7

FBB_CMD_RFU0 FBB_CMD_RFU1

FBB_DEBUG0

FBB_DEBUG1

MEMORY INTERFACE B

FBB_WCK01_N

FBB_WCK23_N

FBB_WCK45_N

FBB_WCK67_N

FBB_WCKB01

FBB_WCKB01_N

FBB_WCKB23

FBB_WCKB23_N

FBB_WCKB45

FBB_WCKB45_N

FBB_WCKB67

FBB_WCKB67_N

FBB_PLL_AVDD

FBB_CMD0 FBB_CMD1 FBB_CMD2 FBB_CMD3 FBB_CMD4 FBB_CMD5 FBB_CMD6 FBB_CMD7 FBB_CMD8

FBB_CMD9 FBB_CMD10 FBB_CMD11 FBB_CMD12 FBB_CMD13 FBB_CMD14 FBB_CMD15 FBB_CMD16 FBB_CMD17 FBB_CMD18 FBB_CMD19 FBB_CMD20 FBB_CMD21 FBB_CMD22 FBB_CMD23 FBB_CMD24 FBB_CMD25 FBB_CMD26 FBB_CMD27 FBB_CMD28 FBB_CMD29 FBB_CMD30 FBB_CMD31

FBB_CLK0

FBB_CLK0_N

FBB_CLK1

FBB_CLK1_N

FBB_WCK01

FBB_WCK23

FBB_WCK45

FBB_WCK67

D13

FBC_CS#_L

E14

FBC_MA3_BA3_L

F14

FBC_MA2_BA0_L

A12

FBC_MA4_BA2_L

B12

FBC_MA5_BA1_L

C14

FBC_WE#_L

B14

FBC_MA7_MA8_L

G15

FBC_MA6_MA11_L

F15

FBC_ABI#_L

E15

FBC_MA12_RFU_L

D15

FBC_MA0_MA10_L

A14

FBC_MA1_MA9_L

D14

FBC_RAS#_L

A15

FBC_RST#_L

B15

FBC_CKE_L

C17

FBC_CAS#_L

D18

FBC_CS#_H

E18

FBC_MA3_BA3_H

F18

FBC_MA2_BA0_H

A20

FBC_MA4_BA2_H

B20

FBC_MA5_BA1_H

C18

FBC_WE#_H

B18

FBC_MA7_MA8_H

G18

FBC_MA6_MA11_H

G17

FBC_ABI#_H

F17

FBC_MA12_RFU_H

D16

FBC_MA0_MA10_H

A18

FBC_MA1_MA9_H

D17

FBC_RAS#_H

A17

FBC_RST#_H

B17

FBC_CKE_H

E17

FBC_CAS#_H

C12 C20

G14 G20

D12 E12 E20 F20

F8 E8 A5 A6 D24 D25 B27 C27

D6 D7 C6 B6 F26 E26 A26 A27

H17

FBC_CLK0 FBC_CLK0# FBC_CLK1 FBC_CLK1#

120mA

1 2 1 2

FBC_WCK0 FBC_WCK0_N FBC_WCK1 FBC_WCK1_N FBC_WCK2 FBC_WCK2_N FBC_WCK3 FBC_WCK3_N

1

2

0.1U_0402_10V7K

Place close to ball

@

RV45360.4_0402_1% RV45460.4_0402_1%

@

FBC_CLK0 53 FBC_CLK0# 53 FBC_CLK1 54 FBC_CLK1# 54

CV397

PU for X16 mod ePU for X16 mod e

FBC_CS#_L 53 FBC_MA3_BA3_L 53 FBC_MA2_BA0_L 53 FBC_MA4_BA2_L 53 FBC_MA5_BA1_L 53 FBC_WE#_L 53 FBC_MA7_MA8_L 53 FBC_MA6_MA11_L 53 FBC_ABI#_L 53 FBC_MA12_RFU_L 53 FBC_MA0_MA10_L 53 FBC_MA1_MA9_L 53 FBC_RAS#_L 53 FBC_RST#_L 53

FBC_CAS#_L 53 FBC_CS#_H 54 FBC_MA3_BA3_H 54 FBC_MA2_BA0_H 54 FBC_MA4_BA2_H 54 FBC_MA5_BA1_H 54 FBC_WE#_H 54 FBC_MA7_MA8_H 54 FBC_MA6_MA11_H 54 FBC_ABI#_H 54 FBC_MA12_RFU_H 54 FBC_MA0_MA10_H 54 FBC_MA1_MA9_H 54 FBC_RAS#_H 54 FBC_RST#_H 54

FBC_CAS#_H 54

+1.35VS_VGA

FBC_WCK0 53 FBC_WCK0_N 53 FBC_WCK1 53 FBC_WCK1_N 53 FBC_WCK2 54 FBC_WCK2_N 54 FBC_WCK3 54 FBC_WCK3_N 54

FBA_AVDD_1.05_3.3V

+1.35VS_VGA

12

+1.35VS_VGA

12

RV447 10K_0402_5%

RV449 10K_0402_5%

For N13P-GT/N13E-GE GC6 support

TO EC

DGPU_GC6_EN32

FB_CLAMP46

FB_CLAMP

GPU_PGOOD49,62,65

DGPU_PWR_EN32,46,49,62

RV458

1 2

0_0402_5%GC6@

1 2

RV464 0_0402_5%

FBC_CKE_L 53

FBC_CKE_H 54

+3VS

13

D

2

G

RV4611K_0402_1%

12

RV46210K_0402_5%

1 2

S

GC6@

RV466 0_0402_5%@

GDDR5 Mode H - Mirror Mode Mapping

DATA Bus

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

RAS#

RST#

CKE#

CAS#

FBVDDQ_PWR_EN 65

12

RV463 200K_0402_5%

GC6@

32..630..31

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

RAS#

RST#

CKE#

CAS#

QV32 2N7002_SOT23

GC6@

GC6_EN

Address

FBx_CMD0

FBx_CMD1

FBx_CMD2

FBx_CMD3

FBx_CMD4

FBx_CMD5

FBx_CMD6

FBx_CMD7

FBx_CMD8

FBx_CMD9

FBx_CMD10

FBx_CMD11

FBx_CMD12

FBx_CMD13

FBx_CMD14

FBx_CMD15

FBx_CMD16

FBx_CMD17

FBx_CMD18

FBx_CMD19

FBx_CMD20

FBx_CMD21

FBx_CMD22

FBx_CMD23

FBx_CMD24

FBx_CMD25

FBx_CMD26

FBx_CMD27

FBx_CMD28

FBx_CMD29

FBx_CMD30

FBx_CMD31

DV15

DAN202UT106_SC70-3

2

3

GC6@

1 2

RV465 0_0402_5%@

1

FBA_DBI0#51 FBA_DBI1#51 FBA_DBI2#51 FBA_DBI3#51 FBA_DBI4#52 FBA_DBI5#52 FBA_DBI6#52 FBA_DBI7#52

FBA_D[0..63]

FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8

FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

FBA_DBI0# FBA_DBI1# FBA_DBI2# FBA_DBI3# FBA_DBI4# FBA_DBI5# FBA_DBI6# FBA_DBI7#

FBA_EDC0 FBA_EDC1 FBA_EDC2 FBA_EDC3 FBA_EDC4 FBA_EDC5 FBA_EDC6 FBA_EDC7

UV23B

L28

FBA_D0

M29

FBA_D1

L29

FBA_D2

M28

FBA_D3

N31

FBA_D4

P29

FBA_D5

R29

FBA_D6

P28

FBA_D7

J28

FBA_D8

H29

FBA_D9

J29

FBA_D10

H28

FBA_D11

G29

FBA_D12

E31

FBA_D13

E32

FBA_D14

F30

FBA_D15

C34

FBA_D16

D32

FBA_D17

B33

FBA_D18

C33

FBA_D19

F33

FBA_D20

F32

FBA_D21

H33

FBA_D22

H32

FBA_D23

P34

FBA_D24

P32

FBA_D25

P31

FBA_D26

P33

FBA_D27

L31

FBA_D28

L34

FBA_D29

L32

FBA_D30

L33

FBA_D31

AG28

FBA_D32

AF29

FBA_D33

AG29

FBA_D34

AF28

FBA_D35

AD30

FBA_D36

AD29

FBA_D37

AC29

FBA_D38

AD28

FBA_D39

AJ29

FBA_D40

AK29

FBA_D41

AJ30

FBA_D42

AK28

FBA_D43

AM29

FBA_D44

AM31

FBA_D45

AN29

FBA_D46

AM30

FBA_D47

AN31

FBA_D48

AN32

FBA_D49

AP30

FBA_D50

AP32

FBA_D51

AM33

FBA_D52

AL31

FBA_D53

AK33

FBA_D54

AK32

FBA_D55

AD34

FBA_D56

AD32

FBA_D57

AC30

FBA_D58

AD33

FBA_D59

AF31

FBA_D60

AG34

FBA_D61

AG32

FBA_D62

AG33

FBA_D63

P30

FBA_DQM0

F31

FBA_DQM1

F34

FBA_DQM2

M32

FBA_DQM3

AD31

FBA_DQM4

AL29

FBA_DQM5

AM32

FBA_DQM6

AF34

FBA_DQM7

M31

FBA_DQS_WP0

G31

FBA_DQS_WP1

E33

FBA_DQS_WP2

M33

FBA_DQS_WP3

AE31

FBA_DQS_WP4

AK30

FBA_DQS_WP5

AN33

FBA_DQS_WP6

AF33

FBA_DQS_WP7

M30

FBA_DQS_RN0

H30

FBA_DQS_RN1

E34

FBA_DQS_RN2

M34

FBA_DQS_RN3

AF30

FBA_DQS_RN4

AK31

FBA_DQS_RN5

AM34

FBA_DQS_RN6

AF32

FBA_DQS_RN7

N13P-PES-A1_FCBGA908

14EGE@

Part 2 of 7

MEMORY INTERFACE

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8

FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31

FBA_CMD_RFU0 FBA_CMD_RFU1

A

FBA_DEBUG0 FBA_DEBUG1

FBA_CLK0

FBA_CLK0_N

FBA_CLK1

FBA_CLK1_N

FBA_WCK01

FBA_WCK01_N

FBA_WCK23

FBA_WCK23_N

FBA_WCK45

FBA_WCK45_N

FBA_WCK67

FBA_WCK67_N

FBA_WCKB01

FBA_WCKB01_N

FBA_WCKB23

FBA_WCKB23_N

FBA_WCKB45

FBA_WCKB45_N

FBA_WCKB67

FBA_WCKB67_N

FB_CLAMP

FB_DLL_AVDD

FBA_PLL_AVDD

U30

FBA_CS#_L

T31

FBA_MA3_BA3_L

U29

FBA_MA2_BA0_L

R34

FBA_MA4_BA2_L

R33

FBA_MA5_BA1_L

U32

FBA_WE#_L

U33

FBA_MA7_MA8_L

U28

FBA_MA6_MA11_L

V28

FBA_ABI#_L

V29

FBA_MA12_RFU_L

V30

FBA_MA0_MA10_L

U34

FBA_MA1_MA9_L

U31

FBA_RAS#_L

V34

FBA_RST#_L

V33

FBA_CKE_L

Y32

FBA_CAS#_L

AA31

FBA_CS#_H

AA29

FBA_MA3_BA3_H

AA28

FBA_MA2_BA0_H

AC34

FBA_MA4_BA2_H

AC33

FBA_MA5_BA1_H

AA32

FBA_WE#_H

AA33

FBA_MA7_MA8_H

Y28

FBA_MA6_MA11_H

Y29

FBA_ABI#_H

W31

FBA_MA12_RFU_H

Y30

FBA_MA0_MA10_H

AA34

FBA_MA1_MA9_H

Y31

FBA_RAS#_H

Y34

FBA_RST#_H

Y33

FBA_CKE_H

V31

FBA_CAS#_H

R32 AC32

R28 AC28

R30

FBA_CLK0

R31

FBA_CLK0#

AB31

FBA_CLK1

AC31

FBA_CLK1#

K31 L30 H34 J34 AG30 AG31 AJ34 AK34

J30 J31 J32 J33 AH31 AJ31 AJ32 AJ33

RV455 10K_0402_5%

E1

CV396 0.1U_0402_10V7K

50mA

K27

1 2 1 2

FBA_WCK0 FBA_WCK0_N FBA_WCK1 FBA_WCK1_N FBA_WCK2 FBA_WCK2_N FBA_WCK3 FBA_WCK3_N

1 2

@

RV45160.4_0402_1% RV45260.4_0402_1%

@

FBA_CLK0 51 FBA_CLK0# 51 FBA_CLK1 52 FBA_CLK1# 52

FB_CLAMP

12

+FB_PLLAVDD

Place close to ball

U27

FB_VREF

120mA

H26

1

CV398

2

0.1U_0402_10V7K

Place close to ball Place close to BGA

FBA_RST#_L FBA_RST#_H

12

RV459 10K_0402_5%

FBA_CS#_L 51 FBA_MA3_BA3_L 51 FBA_MA2_BA0_L 51 FBA_MA4_BA2_L 51 FBA_MA5_BA1_L 51 FBA_WE#_L 51 FBA_MA7_MA8_L 51 FBA_MA6_MA11_L 51 FBA_ABI#_L 51 FBA_MA12_RFU_L 51 FBA_MA0_MA10_L 51 FBA_MA1_MA9_L 51 FBA_RAS#_L 51 FBA_RST#_L 51

FBA_CAS#_L 51 FBA_CS#_H 52 FBA_MA3_BA3_H 52 FBA_MA2_BA0_H 52 FBA_MA4_BA2_H 52 FBA_MA5_BA1_H 52 FBA_WE#_H 52 FBA_MA7_MA8_H 52 FBA_MA6_MA11_H 52 FBA_ABI#_H 52 FBA_MA12_RFU_H 52 FBA_MA0_MA10_H 52 FBA_MA1_MA9_H 52 FBA_RAS#_H 52 FBA_RST#_H 52

FBA_CAS#_H 52

+1.35VS_VGA

FBA_WCK0 51 FBA_WCK0_N 51 FBA_WCK1 51 FBA_WCK1_N 51 FBA_WCK2 52 FBA_WCK2_N 52 FBA_WCK3 52 FBA_WCK3_N 52

FBA_AVDD_1.05_3.3V

1

CV399

CV400

2

22U_0805_6.3V6M

1U_0402_6.3V6K

12

RV460 10K_0402_5%

+1.35VS_VGA

12

+1.35VS_VGA

12

FBA_AVDD_1.05_3.3V

FBC_RST#_L FBC_RST#_H

RV446 10K_0402_5%

RV448 10K_0402_5%

FBC_EDC[3..0]53

FBC_EDC[7..4]54

FBA_D[0..63]51,52 FBC_D[0..63]53,54

30ohms (ESR=0.01) Bead P/N;SM010007W00

+1.05VS_VGA +FB_PLLAVDD

FBMA-L11-160808300LMA25T_2P

D D

+3VS_VGA

C C

B B

A A

1 2

LV36

+FB_PLLAVDD

+FB_PLLAVDD_3V

N14E

300mA

+FB_PLLAVDD

N14P

RV445

1 2

0_0402_5%

PGT@

RV450

1 2

0_0402_5%

EGE@

FBA_AVDD_1.05_3.3V

FBA_EDC[3..0]51

FBA_EDC[7..4]52

Security Classification

2012/05/10 2013/12/31

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMP AL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMP AL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

2012/05/10 2013/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

N14P-MEM Interface

LA-9201P

1

50 66Wednesday, August 15, 2012

0.1

5

4

3

2

1

Memory Partition A - Lower 32 bits

FBA_EDC0

FBA_D[0..31]50

FBA_EDC[3..0]50

D D

FBA_MA2_BA0_L50,51 FBA_MA5_BA1_L50,51 FBA_MA4_BA2_L50,51 FBA_MA3_BA3_L50,51

FBA_MA7_MA8_L50,51 FBA_MA1_MA9_L50,51 FBA_MA0_MA10_L50,51 FBA_MA6_MA11_L50,51 FBA_MA12_RFU_L50,51

Follow DG

FBA_CLK0

C C

FBA_CLK0#

B B

1 2

RV473 40.2_0402_1%

RV474 160_0402_1%

@

1 2

RV475 40.2_0402_1%

MEM_VREF46,52,53,54

1

2

0.01U_0402_25V7K

13

D

2

G

S

2N7002W-T/R7_SOT323-3

CV401

RV477

1 2

931_0402_1%

QV33

+1.35VS_VGA

RV476

549_0402_1%

RV478

1.33K_0402_1%

RV480

1 2

931_0402_1%

1.33K_0402_1%

FBA_CLK050,51 FBA_CLK0#50,51

FBA_CKE_L50,51

RV471

121_0402_1%

FBA_ABI#_L50,51 FBA_RAS#_L50,51 FBA_CS#_L50,51 FBA_CAS#_L50,51 FBA_WE#_L50,51

FBA_WCK0_N50,51 FBA_WCK050,51

FBA_WCK1_N50,51 FBA_WCK150,51

FBA_RST#_L50,51

12

820P_0402_25V7

+1.35VS_VGA

RV479

549_0402_1%

RV481

UV3 SIDE

FBA_DBI0#50

FBA_DBI2#50

12

+FBA_VREFC0

1

CV402

2

12

FBA_EDC2

FBA_DBI0#

FBA_DBI2#

FBA_CLK0 FBA_CLK0#

FBA_CKE_L

FBA_MA2_BA0_L FBA_MA5_BA1_L FBA_MA4_BA2_L FBA_MA3_BA3_L

FBA_MA7_MA8_L

FBA_MA1_MA9_L FBA_MA0_MA10_L FBA_MA6_MA11_L

FBA_MA12_RFU_L

12

RV467

1K_0402_1%

12

RV469

1K_0402_1%

FBA_ABI#_L

FBA_RAS#_L

FBA_CS#_L

FBA_CAS#_L

FBA_WE#_L

FBA_WCK0_N FBA_WCK0

FBA_WCK1_N FBA_WCK1

+FBA_VREFD_L

+FBA_VREFC0

FBA_RST#_L

16 mil

+1.35VS_VGA +1.35VS_VGA

+FBA_VREFD_L

1

CV403

2

820P_0402_25V7

UV25

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A 4

K10

BA1/A5 BA3/A 3

K11

BA2/A4 BA0/A 2

H10

BA3/A3 BA1/A 5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/N C

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE #

L3

CAS# RAS#

L12

WE# CS#

D5

WCK0 1# WCK23#

D4

WCK0 1 WCK23

P5

WCK2 3# WCK01#

P4

WCK2 3 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

2GS@

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9 DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15

DQ8 DQ16

DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23

DQ0 DQ24

DQ1 DQ25

DQ2 DQ26

DQ3 DQ27

DQ4 DQ28

DQ5 DQ29

DQ6 DQ30

DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

H5GQ1H24BFR-T2C_BGA170

A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7

FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23

+1.35VS_VGA

BYTE0

BYTE2

UV4 SIDE

FBA_MA4_BA2_L50,51 FBA_MA3_BA3_L50,51 FBA_MA2_BA0_L50,51 FBA_MA5_BA1_L50,51

FBA_MA0_MA10_L50,51 FBA_MA6_MA11_L50,51 FBA_MA7_MA8_L50,51 FBA_MA1_MA9_L50,51 FBA_MA12_RFU_L50,51

FBA_DBI3#50

FBA_DBI1#50

FBA_CLK050,51 FBA_CLK0#50,51

FBA_CKE_L50,51

+1.35VS_VGA

RV472

FBA_ABI#_L50,51 FBA_CAS#_L50,51 FBA_WE#_L50,51 FBA_RAS#_L50,51 FBA_CS#_L50,51

FBA_WCK1_N50,51 FBA_WCK150,51

FBA_WCK0_N50,51 FBA_WCK050,51

FBA_RST#_L50,51

12

121_0402_1%

FBA_EDC3

FBA_EDC1

FBA_DBI3#

FBA_DBI1#

FBA_CLK0 FBA_CLK0#

FBA_CKE_L

FBA_MA4_BA2_L FBA_MA3_BA3_L FBA_MA2_BA0_L FBA_MA5_BA1_L

FBA_MA0_MA10_L FBA_MA6_MA11_L

FBA_MA7_MA8_L FBA_MA1_MA9_L

FBA_MA12_RFU_L

12

RV468

1K_0402_1%

12

RV470

1K_0402_1%

FBA_ABI#_L

FBA_CAS#_L

FBA_WE#_L

FBA_RAS#_L

FBA_CS#_L

FBD_WCK1_N FBD_WCK1

FBD_WCK0_N FBD_WCK0

+FBA_VREFD_L

+FBA_VREFC0

FBA_RST#_L

UV26

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A 4

K10

BA1/A5 BA3/A 3

K11

BA2/A4 BA0/A 2

H10

BA3/A3 BA1/A 5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/N C

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE #

L3

CAS# RAS#

L12

WE# CS#

D5

WCK0 1# WCK23#

D4

WCK0 1 WCK23

P5

WCK2 3# WCK01#

P4

WCK2 3 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

2GS@

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

H5GQ1H24BFR-T2C_BGA170

A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31

FBA_D8

FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15

BYTE3

GDDR5 Mode H - Mirror Mode Mapping

BYTE1

Address

FBx_CMD0

FBx_CMD1

FBx_CMD2

FBx_CMD3

+1.35VS_VGA+1.35VS_VGA

FBx_CMD4

FBx_CMD5

FBx_CMD6

FBx_CMD7

FBx_CMD8

FBx_CMD9

FBx_CMD10

FBx_CMD11

FBx_CMD12

FBx_CMD13

FBx_CMD14

FBx_CMD15

FBx_CMD16

FBx_CMD17

FBx_CMD18

FBx_CMD19

FBx_CMD20

FBx_CMD21

FBx_CMD22

FBx_CMD23

FBx_CMD24

FBx_CMD25

FBx_CMD26

FBx_CMD27

FBx_CMD28

FBx_CMD29

FBx_CMD30

FBx_CMD31

DATA Bus

0..31 32..63

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

RAS#

RST#

CKE#

CAS#

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

RAS#

RST#

CKE#

CAS#

2

CV404

A A

1

1U_0603_25V6

10U_0603_6.3V6M

5

1

CV405

2

1

CV406

CV407

2

1U_0603_25V6

1

CV408

2

0.1U_0402_10V7K

1

CV409

2

0.1U_0402_10V7K

1

CV410

2

CV411

2

0.1U_0402_10V7K

4

2

CV412

1

1U_0603_25V6

10U_0603_6.3V6M

1

CV413

2

1

CV414

CV415

2

1U_0603_25V6

1

2

CV417

CV416

2

0.1U_0402_10V7K

3

1

2

CV419

CV418

2

0.1U_0402_10V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/05/10 2013/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

N14P-VRAM A Lower

LA-9201P

1

51 66Wednesday, August 15, 2012

0.1

5

4

3

2

1

Memory Partition A - Upper 32 bits

UV27

MF=0 MF=1 MF=0MF=1

A4

FBA_EDC4

FBA_D[63..32]50

FBA_EDC[7..4]50

D D

FBA_CLK150,52 FBA_CLK1#50,52

FBA_MA2_BA0_H50,52 FBA_MA5_BA1_H50,52 FBA_MA4_BA2_H50,52 FBA_MA3_BA3_H50,52

FBA_MA7_MA8_H50,52 FBA_MA1_MA9_H50,52 FBA_MA0_MA10_H50,52 FBA_MA6_MA11_H50,52 FBA_MA12_RFU_H50,52

Follow DG

FBA_CLK1

C C

FBA_CLK1#

B B

MEM_VREF46,51,53,54

A A

1 2

RV488 40.2_0402_1%

RV489 160_0402_1%

@

1 2

RV490 40.2_0402_1%

13

D

2

G

QV34

S

2N7002W-T/R7_SOT323-3

+1.35VS_VGA

UV5 SIDE

1

2

CV423

2

1

1U_0603_25V6

10U_0603_6.3V6M

1

2

0.01U_0402_25V7K

RV492

1 2

931_0402_1%

1 2

931_0402_1%

CV424

CV420

RV495

1U_0603_25V6

1

2

+1.35VS_VGA

RV491

549_0402_1%

RV493

1.33K_0402_1%

+1.35VS_VGA

RV494

549_0402_1%

RV496

1.33K_0402_1%

1

CV425

CV426

2

1U_0603_25V6

FBA_ABI#_H50,52 FBA_RAS#_H50,52 FBA_CS#_H50,52 FBA_CAS#_H50,52 FBA_WE#_H50,52

FBA_WCK2_N50,52 FBA_WCK250,52

FBA_WCK3_N50,52 FBA_WCK350,52

FBA_RST#_H50,52

1U_0603_25V6

FBA_CKE_H50,52

12

1

2

RV487

CV427

FBA_DBI4#50

FBA_DBI6#50

12

121_0402_1%

+FBA_VREFC1

1

CV421

2

820P_0402_25V7

+FBA_VREFD_H

1

2

0.1U_0402_10V7K

16 mil

CV428

FBA_EDC6

FBA_DBI4#

FBA_DBI6#

FBA_CLK1

FBA_CLK1#

FBA_CKE_H

FBA_MA2_BA0_H FBA_MA5_BA1_H FBA_MA4_BA2_H FBA_MA3_BA3_H

FBA_MA7_MA8_H

FBA_MA1_MA9_H FBA_MA0_MA10_H FBA_MA6_MA11_H

FBA_MA12_RFU_H

12

RV483

1K_0402_1%

12

RV485

1K_0402_1%

FBA_ABI#_H

FBA_RAS#_H

FBA_CS#_H

FBA_CAS#_H

FBA_WE#_H

FBA_WCK2_N FBA_WCK2

FBA_WCK3_N FBA_WCK3

+FBA_VREFD_H

+FBA_VREFC1

FBA_RST#_H

+1.35VS_VGA

1

CV422

2

820P_0402_25V7

1

CV429

2

0.1U_0402_10V7K

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A 4

K10

BA1/A5 BA3/A 3

K11

BA2/A4 BA0/A 2

H10

BA3/A3 BA1/A 5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/N C

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE #

L3

CAS# RAS#

L12

WE# CS#

D5

WCK0 1# WCK23#

D4

WCK0 1 WCK23

P5

WCK2 3# WCK01#

P4

WCK2 3 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

2GS@

1

CV430

2

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15

DQ8 DQ16

DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23

DQ0 DQ24

DQ1 DQ25

DQ2 DQ26

DQ3 DQ27

DQ4 DQ28

DQ5 DQ29

DQ6 DQ30

DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

H5GQ1H24AFR-T2L_BGA170

A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39

FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55

+1.35VS_VGA

BYTE4

FBA_DBI7#50

FBA_DBI5#50

FBA_CLK150,52 FBA_CLK1#50,52

FBA_CKE_H50,52

FBA_MA4_BA2_H50,52 FBA_MA3_BA3_H50,52 FBA_MA2_BA0_H50,52

BYTE6

FBA_MA5_BA1_H50,52

FBA_MA0_MA10_H50,52 FBA_MA6_MA11_H50,52 FBA_MA7_MA8_H50,52 FBA_MA1_MA9_H50,52 FBA_MA12_RFU_H50,52

FBA_ABI#_H50,52 FBA_CAS#_H50,52 FBA_WE#_H50,52 FBA_RAS#_H50,52 FBA_CS#_H50,52

FBA_RST#_H50,52

FBA_WCK3_N50,52 FBA_WCK350,52

FBA_WCK2_N50,52 FBA_WCK250,52

+1.35VS_VGA

12

RV486

121_0402_1%

UV6 SIDE

2

CV431

2

1

1U_0603_25V6

10U_0603_6.3V6M

CV433

CV432

2

1U_0603_25V6

1

2

CV435

CV434

2

1U_0603_25V6

0.1U_0402_10V7K

1

CV436

2

0.1U_0402_10V7K

FBA_EDC7

FBA_EDC5

FBA_DBI7#

FBA_DBI5#

FBA_CLK1

FBA_CLK1#

FBA_CKE_H

FBA_MA4_BA2_H FBA_MA3_BA3_H FBA_MA2_BA0_H FBA_MA5_BA1_H

FBA_MA0_MA10_H FBA_MA6_MA11_H

FBA_MA7_MA8_H FBA_MA1_MA9_H

FBA_MA12_RFU_H

12

RV482

1K_0402_1%

12

RV484

1K_0402_1%

FBA_ABI#_H

FBA_CAS#_H

FBA_WE#_H

FBA_RAS#_H

FBA_CS#_H

FBA_WCK3_N FBA_WCK3

FBA_WCK2_N FBA_WCK2

+FBA_VREFD_H

+FBA_VREFC1

FBA_RST#_H

+1.35VS_VGA

1

CV438

CV437

2

0.1U_0402_10V7K

UV28

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A 4

K10

BA1/A5 BA3/A 3

K11

BA2/A4 BA0/A 2

H10

BA3/A3 BA1/A 5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/N C

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE #

L3

CAS# RAS#

L12

WE# CS#

D5

WCK0 1# WCK23#

D4

WCK0 1 WCK23

P5

WCK2 3# WCK01#

P4

WCK2 3 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

2GS@

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

H5GQ1H24AFR-T2L_BGA170

A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47

+1.35VS_VGA

BYTE7

BYTE5

GDDR5 Mode H - Mirror Mode Mapping

Address

FBx_CMD0

FBx_CMD1

FBx_CMD2

FBx_CMD3

FBx_CMD4

FBx_CMD5

FBx_CMD6

FBx_CMD7

FBx_CMD8

FBx_CMD9

FBx_CMD10

FBx_CMD11

FBx_CMD12

FBx_CMD13

FBx_CMD14

FBx_CMD15

FBx_CMD16

FBx_CMD17

FBx_CMD18

FBx_CMD19

FBx_CMD20

FBx_CMD21

FBx_CMD22

FBx_CMD23

FBx_CMD24

FBx_CMD25

FBx_CMD26

FBx_CMD27

FBx_CMD28

FBx_CMD29

FBx_CMD30

FBx_CMD31

0..31

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

RAS#

RST#

CKE#

CAS#

DATA Bus

32..63

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

RAS#

RST#

CKE#

CAS#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/05/10 2013/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

N14P-VRAM A Upper

LA-9201P

1

52 66Tuesday, August 14, 2012

0.1

5

4

3

2

1

Memory Partition C - Lower 32 bits

G12

G10

G11

G14

CV449

UV30

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS# CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD VDD

L11

VDD

P11

VDD VDD

L14

VDD

170-BALL

SGRAM GDDR5

2GS@

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

H5GQ1H24AFR-T2L_BGA170

A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

FBC_D24 FBC_D25 FBC_D26 FBC_D27 FBC_D28 FBC_D29 FBC_D30 FBC_D31

FBC_D8

FBC_D9 FBC_D10 FBC_D11 FBC_D12 FBC_D13 FBC_D14 FBC_D15

+1.35VS_VGA

BYTE3

BYTE1

GDDR5 Mode H - Mirror Mode Mapping

Address

FBx_CMD0

FBx_CMD1

FBx_CMD2

FBx_CMD3

FBx_CMD4

FBx_CMD5

FBx_CMD6

FBx_CMD7

FBx_CMD8

FBx_CMD9

FBx_CMD10

FBx_CMD11

FBx_CMD12

FBx_CMD13

FBx_CMD14

FBx_CMD15

FBx_CMD16

FBx_CMD17

FBx_CMD18

FBx_CMD19

FBx_CMD20

FBx_CMD21

FBx_CMD22

FBx_CMD23

FBx_CMD24

FBx_CMD25

FBx_CMD26

FBx_CMD27

FBx_CMD28

FBx_CMD29

FBx_CMD30

FBx_CMD31

0..31

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

RAS#

RST#

CKE#

CAS#

DATA Bus

32..63

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

RAS#

RST#

CKE#

CAS#

UV29

FBC_D[0..31]50

FBC_EDC[3..0]50

D D

FBC_MA2_BA0_L50,53 FBC_MA5_BA1_L50,53 FBC_MA4_BA2_L50,53 FBC_MA3_BA3_L50,53

FBC_MA7_MA8_L50,53 FBC_MA1_MA9_L50,53 FBC_MA0_MA10_L50,53 FBC_MA6_MA11_L50,53 FBC_MA12_RFU_L50,53

Follow DG

FBC_CLK0

C C

FBC_CLK0#

B B

MEM_VREF46,51,52,54

A A

1 2

RV503 40.2_0402_1%

RV504 160_0402_1%

@

1 2

RV505 40.2_0402_1%

2

G

+1.35VS_VGA

UV7 SIDE

1

2

CV450

2

1

1U_0603_25V6

10U_0603_6.3V6M

1

2

0.01U_0402_25V7K

13

D

QV35

S

2N7002W-T/R7_SOT323-3

CV451

1U_0603_25V6

CV439

RV507

1 2

931_0402_1%

RV510

1 2

931_0402_1%

1

CV452

2

1U_0603_25V6

FBC_ABI#_L50,53 FBC_RAS#_L50,53 FBC_CS#_L50,53 FBC_CAS#_L50,53 FBC_WE#_L50,53

FBC_WCK0_N50,53 FBC_WCK050,53

FBC_WCK1_N50,53 FBC_WCK150,53

FBC_RST#_L50,53

549_0402_1%

1.33K_0402_1%

RV509

549_0402_1%

RV511

1.33K_0402_1%

1

CV453

2

1U_0603_25V6

+1.35VS_VGA

RV506

RV508

+1.35VS_VGA

1

2

FBC_CLK050,53 FBC_CLK0#50,53

FBC_CKE_L50,53

12

CV454

RV501

121_0402_1%

12

1

2

0.1U_0402_10V7K

FBC_DBI0#50

FBC_DBI2#50

12

+FBC_VREFC0

1

2

820P_0402_25V7

+FBC_VREFD_L

1

CV441

2

820P_0402_25V7

CV455

0.1U_0402_10V7K

FBC_EDC0

FBC_EDC2

FBC_DBI0#

FBC_DBI2#

FBC_CLK0 FBC_CLK0#

FBC_CKE_L

FBC_MA2_BA0_L FBC_MA5_BA1_L

FBC_MA4_BA2_L

FBC_MA3_BA3_L

FBC_MA7_MA8_L

FBC_MA1_MA9_L FBC_MA0_MA10_L FBC_MA6_MA11_L

FBC_MA12_RFU_L

12

RV497

1K_0402_1%

12

RV499

1K_0402_1%

FBC_ABI#_L

FBC_RAS#_L

FBC_CS#_L

FBC_CAS#_L

FBC_WE#_L

FBC_WCK0_N FBC_WCK0

FBC_WCK1_N FBC_WCK1

+FBC_VREFD_L

+FBC_VREFC0

FBC_RST#_L

CV440

+1.35VS_VGA

1

CV456

2

0.1U_0402_10V7K

CV457

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

2GS@

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

H5GQ1H24AFR-T2L_BGA170

A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

FBC_D0 FBC_D1 FBC_D2 FBC_D3 FBC_D4 FBC_D5 FBC_D6 FBC_D7

FBC_D16 FBC_D17 FBC_D18 FBC_D19 FBC_D20 FBC_D21 FBC_D22 FBC_D23

+1.35VS_VGA

BYTE0

BYTE2

+1.35VS_VGA

2

1

10U_0603_6.3V6M

UV8 SIDE

CV442

1U_0603_25V6

FBC_EDC3

FBC_EDC1

FBC_DBI3#50

FBC_DBI1#50

FBC_CLK050,53 FBC_CLK0#50,53

FBC_CKE_L50,53

FBC_MA4_BA2_L50,53 FBC_MA3_BA3_L50,53 FBC_MA2_BA0_L50,53 FBC_MA5_BA1_L50,53

FBC_MA0_MA10_L50,53 FBC_MA6_MA11_L50,53 FBC_MA7_MA8_L50,53 FBC_MA1_MA9_L50,53 FBC_MA12_RFU_L50,53

+1.35VS_VGA

12

RV502

121_0402_1%

FBC_ABI#_L50,53 FBC_CAS#_L50,53 FBC_WE#_L50,53 FBC_RAS#_L50,53 FBC_CS#_L50,53

FBC_WCK1_N50,53 FBC_WCK150,53

FBC_WCK0_N50,53 FBC_WCK050,53

FBC_RST#_L50,53

1

CV443

2

1

CV444

CV445

2

1U_0603_25V6

1

2

CV447

CV446

2

0.1U_0402_10V7K

FBC_DBI3#

FBC_DBI1#

FBC_CLK0 FBC_CLK0#

FBC_CKE_L

FBC_MA4_BA2_L

FBC_MA3_BA3_L FBC_MA2_BA0_L FBC_MA5_BA1_L

FBC_MA0_MA10_L FBC_MA6_MA11_L

FBC_MA7_MA8_L FBC_MA1_MA9_L

FBC_MA12_RFU_L

12

RV498

1K_0402_1%

12

RV500

1K_0402_1%

FBC_ABI#_L

FBC_CAS#_L

FBC_WE#_L

FBC_RAS#_L

FBC_CS#_L

FBC_WCK1_N FBC_WCK1

FBC_WCK0_N FBC_WCK0

+FBC_VREFD_L

+FBC_VREFC0

FBC_RST#_L

+1.35VS_VGA

1

CV448

2

0.1U_0402_10V7K

1

2

Security Classification

2012/05/10 2013/12/31

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMP AL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMP AL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

2012/05/10 2013/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

N14P-VRAM C Lower

LA-9201P

1

53 66Tuesday, August 14, 2012

0.1

5

4

3

2

1

Memory Partition C - Upper 32 bits

UV31

MF=0 MF=1 MF=0MF=1

A4

FBC_EDC4

FBC_D[63..32]50

D D

C C

B B

MEM_VREF46,51,52,53

A A

FBC_EDC[7..4]50

Follow DG

FBC_CLK1

FBC_CLK1#

RV518 40.2_0402_1%

1 2

RV520 40.2_0402_1%

+1.35VS_VGA

1 2

RV519 160_0402_1%

@

1 2

2

G

2

CV469

1

10U_0603_6.3V6M

13

1

CV458

2

0.01U_0402_25V7K

549_0402_1%

RV522

1 2

931_0402_1%

1.33K_0402_1%

549_0402_1%

RV525

1 2

931_0402_1%

D

QV36

S

2N7002W-T/R7_SOT323-3

1.33K_0402_1%

UV9 SIDE

1

2

1U_0603_25V6

CV471

CV470

2

1U_0603_25V6

RV521

RV523

RV524

RV526

1

2

1U_0603_25V6

FBC_MA2_BA0_H50,54 FBC_MA5_BA1_H50,54 FBC_MA4_BA2_H50,54 FBC_MA3_BA3_H50,54

FBC_MA7_MA8_H50,54 FBC_MA1_MA9_H50,54 FBC_MA0_MA10_H50,54 FBC_MA6_MA11_H50,54 FBC_MA12_RFU_H50,54

FBC_ABI#_H50,54 FBC_RAS#_H50,54 FBC_CS#_H50,54 FBC_CAS#_H50,54 FBC_WE#_H50,54

FBC_WCK2_N50,54 FBC_WCK250,54

FBC_WCK3_N50,54 FBC_WCK350,54

FBC_RST#_H50,54

+1.35VS_VGA

12

+1.35VS_VGA

12

CV472

1U_0603_25V6

FBC_CLK150,54 FBC_CLK1#50,54

FBC_CKE_H50,54

820P_0402_25V7

1

CV473

2

12

RV515

121_0402_1%

+FBC_VREFC1

1

CV459

2

+FBC_VREFD_H

1

CV460

2

1

CV474

2

0.1U_0402_10V7K

FBC_DBI4#50

FBC_DBI6#50

0.1U_0402_10V7K

FBC_EDC6

FBC_DBI4#

FBC_DBI6#

FBC_CLK1

FBC_CLK1#

FBC_CKE_H

FBC_MA2_BA0_H FBC_MA5_BA1_H

FBC_MA4_BA2_H

FBC_MA3_BA3_H

FBC_MA7_MA8_H

FBC_MA1_MA9_H FBC_MA0_MA10_H FBC_MA6_MA11_H

FBC_MA12_RFU_H

12

RV512

1K_0402_1%

12

RV514

1K_0402_1%

FBC_ABI#_H

FBC_RAS#_H

FBC_CS#_H

FBC_CAS#_H

FBC_WE#_H

FBC_WCK2_N FBC_WCK2

FBC_WCK3_N FBC_WCK3

+FBC_VREFD_H

+FBC_VREFC1

FBC_RST#_H

+1.35VS_VGA

1

CV475

2

0.1U_0402_10V7K

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

2GS@

CV476

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

H5GQ1H24AFR-T2L_BGA170

A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

FBC_D32 FBC_D33 FBC_D34 FBC_D35 FBC_D36 FBC_D37 FBC_D38 FBC_D39

FBC_D48 FBC_D49 FBC_D50 FBC_D51 FBC_D52 FBC_D53 FBC_D54 FBC_D55

+1.35VS_VGA

2

1

10U_0603_6.3V6M

BYTE4

BYTE6

UV10 SIDE

CV461

1U_0603_25V6

FBC_EDC7

FBC_EDC5

FBC_DBI7#50

FBC_DBI5#50

FBC_CLK150,54 FBC_CLK1#50,54

FBC_CKE_H50,54

FBC_MA4_BA2_H50,54 FBC_MA3_BA3_H50,54 FBC_MA2_BA0_H50,54 FBC_MA5_BA1_H50,54

FBC_MA0_MA10_H50,54 FBC_MA6_MA11_H50,54 FBC_MA7_MA8_H50,54 FBC_MA1_MA9_H50,54 FBC_MA12_RFU_H50,54

+1.35VS_VGA

12

RV517

121_0402_1%

FBC_ABI#_H50,54 FBC_CAS#_H50,54 FBC_WE#_H50,54 FBC_RAS#_H50,54 FBC_CS#_H50,54

FBC_WCK3_N50,54 FBC_WCK350,54

FBC_WCK2_N50,54 FBC_WCK250,54

FBC_RST#_H50,54

1

CV462

2

CV463

2

1U_0603_25V6

1

CV464

2

1U_0603_25V6

1

CV465

2

0.1U_0402_10V7K

FBC_DBI7#

FBC_DBI5#

FBC_CLK1

FBC_CLK1#

FBC_CKE_H

FBC_MA4_BA2_H

FBC_MA3_BA3_H FBC_MA2_BA0_H FBC_MA5_BA1_H

FBC_MA0_MA10_H FBC_MA6_MA11_H

FBC_MA7_MA8_H FBC_MA1_MA9_H

FBC_MA12_RFU_H

12

RV513

1K_0402_1%

12

RV516

1K_0402_1%

FBC_ABI#_H

FBC_CAS#_H

FBC_WE#_H

FBC_RAS#_H

FBC_CS#_H

FBC_WCK3_N FBC_WCK3

FBC_WCK2_N FBC_WCK2

+FBC_VREFD_H

+FBC_VREFC1

FBC_RST#_H

+1.35VS_VGA

1

CV467

CV466

2

0.1U_0402_10V7K

UV32

MF=0 MF=1 MF=0MF=1

A4

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

2GS@

1

CV468

2

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

H5GQ1H24AFR-T2L_BGA170

A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

FBC_D56 FBC_D57 FBC_D58 FBC_D59 FBC_D60 FBC_D61 FBC_D62 FBC_D63

FBC_D40 FBC_D41 FBC_D42 FBC_D43 FBC_D44 FBC_D45 FBC_D46 FBC_D47

+1.35VS_VGA

BYTE7

BYTE5

GDDR5 Mode H - Mirror Mode Mapping

Address

FBx_CMD0

FBx_CMD1

FBx_CMD2

FBx_CMD3

FBx_CMD4

FBx_CMD5

FBx_CMD6

FBx_CMD7

FBx_CMD8

FBx_CMD9

FBx_CMD10

FBx_CMD11

FBx_CMD12

FBx_CMD13

FBx_CMD14

FBx_CMD15

FBx_CMD16

FBx_CMD17

FBx_CMD18

FBx_CMD19

FBx_CMD20

FBx_CMD21

FBx_CMD22

FBx_CMD23

FBx_CMD24

FBx_CMD25

FBx_CMD26

FBx_CMD27

FBx_CMD28

FBx_CMD29

FBx_CMD30

FBx_CMD31

0..31

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

RAS#

RST#

CKE#

CAS#

DATA Bus

32..63

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

RAS#

RST#

CKE#

CAS#

Security Classification

2012/05/10 2013/12/31

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMP AL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMP AL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

2012/05/10 2013/12/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

N14P-VRAM C Upper

LA-9201P

1

54 66Tuesday, August 14, 2012

0.1

5

4

+3VS_VGA

3

2

1

RV527

45.3K_0402_1%

D D

STRAP047 STRAP147 STRAP247 STRAP347 STRAP447

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

GEGT@

1 2

RV532

@

45.3K_0402_1%

1 2

RV528

34.8K_0402_1%

@

1 2

RV533

4.99K_0402_1%

GEGT@

1 2

RV529 10K_0402_1%

@

1 2

RV534 20K_0402_1%

GE@

1 2

RV530 15K_0402_1%

GEGT@

1 2

RV535

4.99K_0402_1%

@

1 2

RV531 20K_0402_1%

@

1 2

RV536

45.3K_0402_1%

GEGT@

1 2

RV534

24.9K_0402_1%

GT@

SD03424928L

11/07 Follow NV request change to 45K for GTGE

N14E-GE(ver.ES) SA00005W30L Samsung SA00005B70L N14P-GT(ver.ES) SA00005W20L Hynix SA00004GD1L

C C

+3VS_VGA

GPU

FB Memory gDDR5

ROM_SO ROM_SCLK ROM_SI STRAP1

STRAP0

STRAP2

STRAP4STRAP3

RV537

4.99K_0402_1%

@

1 2

ROM_SI47,55 ROM_SO47 ROM_SCLK47,55

B B

ROM_SI ROM_SO ROM_SCLK

X76

RV540

45.3K_0402_1%

GE@

1 2

RV538 10K_0402_1%

GEGT@

1 2

RV541 10K_0402_1%

@

1 2

RV539

4.99K_0402_1%

GE@

1 2

RV542 15K_0402_1%

GT@

1 2

N14P-GT

N14E-GE

Samsung 900MHz

Hynix 900MHz

Samsung 900MHz

Hynix

128Mx16

H5GQ2H24AER-T2C

128Mx16

K4G20325FD-FC04

128Mx16

PU 10K

PD 15K

PD 25K

PD 45KPU 5K

PU 45K

PD 5K

PD 25K

PD 20K

PU 15K

PD 45K

900MHz

RV540

128Mx16

X76

24.9K_0402_1%

GT@

SD03424928L

+3VS_VGA+3VS_VGA+3VS_VGA

12

@

RV543

10K_0402_5%

ROM_CS47 ROM_SI47,55

A A

ROM_CS ROM_SI ROM_SI_R

1 2

RV544 33_0402_5%~D@

EEPROM

UV33

1

CS#

2

SO

3

WP#

4

GND

@

VCC

HOLD#

SCK

8 7 6 5

SI

ROM_SCLK_R ROM_SI_R

0.1U_0402_16V4Z~D

CV477

1

@

2

RV547 33_0402_5%~D@

1 2 1 2

RV546 33_0402_5%~D@

ROM_SCLK ROM_SI

ROM_SCLK 47,55 ROM_SI 47,55

XXX1

Samsung

S2G@ X7644731L01

XXX2

Hynix

H2G@

X7644731L02

Security Classification

2012/05/10 2013/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2012/05/10 2013/12/31

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N14P_MISC

LA-9201P

55 66Friday, August 17, 2012

1

55 66Friday, August 17, 2012

0.1

A

PL1

C8B BPH 853025_2P

ADPIN

@

PJPDC1

1

2

3

4

5

6

1 1

7

ACES_88299-0710-001

PSID

12

PC1

1000P_0402_50V7K

BLM18BD102SN1D_0603~D

1 2

PC2

100P_0402_50V8J

PL2

12

VIN

12

PC3

1000P_0402_50V7K

PC4

ACIN15,32,36,63

BATT++BATT+

PL3

SMB3025500YA_2P

BATT+

1 2

12

2 2

3 3

12

PC6

100P_0402_50V8J

ACES_50293-0117N-001

SMART

SMARTSMART Battery:

Battery:

Battery:Battery:

11.BATT+

11.BATT+11.BATT+

10.BATT+

10.BATT+10.BATT+

09.BATT+

09.BATT+09.BATT+

08.CLK_SMB

08.CLK_SMB08.CLK_SMB

07.DAT_SMB

07.DAT_SMB07.DAT_SMB

06.BATT_PRS

06.BATT_PRS06.BATT_PRS

05.SYS_PRES

05.SYS_PRES05.SYS_PRES

04.BAT_ALERT

04.BAT_ALERT04.BAT_ALERT

03.GND

03.GND03.GND

02.GND

02.GND02.GND

01.GND

01.GND01.GND

PC7

0.01U_0402_25V7K

11 10

9 8 7 6 5 4 3 2 1

PBATT1

@

11 10 9 8 7 6 5 4 3 2 1

CLK_SMB DAT_SMB BATT_PRS SYS_PRES

BATT++

12

PC8

1000P_0402_50V7K

@

JRTC1

ACES_50271-00201-001

G1 G2

PC9

100P_0402_50V8J

1 2

1

PD3 PESD24VS2UT_SOT23-3

2

3

PR19 0_0402_5%

1 2

1 2 3 4

JRTC1

+3VLP

1

PD4

2

3

PESD24VS2UT_SOT23-3

PR15

100_0402_5%

1 2

PR18

100_0402_5%

1 2

PR20

100_0402_5%

1 2

PD5

2

3

BAS40CW_SOT323-3

1

B

Erp lot6 Circuit

100P_0402_50V8J

12

@

+3VALW

@

2

PR1

200K_0402_1%

PC5

0.1U_0402_25V6

PR16

10K_0402_1%

1 2

EC_SMB_CK1 32,63

EC_SMB_DA1 32,63

+RTC_CELL

VIN

PR7

1M_0402_1%

1 2

61

PQ1A

@

BATT_TEMP 32,63

1 2

DMN66D0LDW-7 2N SOT363-6

@

5

@

PR10

1M_0402_1%

C

PR4

1 3

D

G

12

PR5

3

PQ1B

4

2

3.3K_1206_5%~D

DMN66D0LDW-7 2N SOT363-6

3

@

1

PD1 SM24_SOT23

PR6

1 2

100K_0402_1%

PR9

15K_0402_1%

1 2

PSID-1

2

C

2

PQ2

B

MMST3904-7-F_SOT323~D

E

3 1

33_0402_5%

1 2

PSID-3

S

PQ7 FDV301N_NL_SOT23-3~D

PSID-2

B+

12

100K_0402_1%

PC10

0.22U_0603_25V7K

VSB_N_001

2

TP0610K-T1-E3_SOT23-3

PQ3

100K_0402_1%

POK57

ADP_I32,63

+5VALW

PR14

PR17

1 2

0_0402_5%

1 2

VSB_N_002

12

PR12

PR13

100K_0402_1%

1 2

VSB_N_003

13

D

2

G

PC12

.1U_0402_16V7K

PQ4 2N7002KW_SOT323-3

S

13

D

+3VALW

PR3

2.2K_0402_5%

1 2

12

PR8

10K_0402_1%

B+_BIAS

PC11

0.1U_0402_25V6

PS_ID 32

12

+5VALW

CPU thermal protection at 93 +/- 3 degree C

+3VLP+3VALW

PR23 681K_0402_1%

1 2

VCIN0_PH32

VCIN1_PH32

PR24

12.1K_0402_1%

PR25

@

12.1K_0402_1%

1 2

12

PC13

PR26

499K_0402_1%

4 4

Security Classification

2012/01/17 2013/01/16

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2012/01/17 2013/01/16

1 2

@

.1U_0402_16V7K

1 2

Compal Secret Data

Deciphered Date

C

100K_0402_1%_TSM0B104F4251RZ

ECAGND32

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PWR-DCIN / BATT CONN / OTP

LA-XXXXP

PH1

56 66Friday, August 10, 2012

D

56 66Friday, August 10, 2012

0.1

A

1 1

B

13.7K_0402_1%~D

PR100

1 2

PC113

0.1U_0402_25V6

1 2

20K_0402_1%

1 2

@

PR102

+3VLP

PR103

1 2

0_0603_5%~D

C

@

PC115

0.1U_0402_25V6

1 2

PR101

30.9K_0402_1%

12

PC114

1U_0603_10V5K

20K_0402_1%

1 2

12

PR104

D

E

B++

1UH_NRS4018T1R0NDGJ_3.2A_30%

B+

2 2

+3VALWP

PL103

1 2

PC101

150U_B2_6.3VM_R35M

12

PC107

PC110

PC106

PC105

0.1U_0402_25V6 2200P_0402_50V7K

3.3UH +-20% PCMB063T-3R3MS 6.5A

1

+

2

PL101

@

10U_0805_25V6K

12

PQ101

3 5

241

MDV1528URH 1N PDFN33-8

12

PR109

4.7_1206_5% PQ103

SNUB_3V

12

PC116

680P_0603_50V7K

3 5

241

MDV1525URH 1N PDFN33-8

PC112

0.1U_0603_25V7K

1 2

POK56

PR108

2.2_0603_5%

1 2

PR105

1 2

100K_0402_1%~D

3V_EN

UG_3V

BST_3V

SW2

LG_3V

B++

PU100

6

7

10

9

8

FB_3V

3

4

5

CS2

EN2

PGOOD

DRVH2

VBST2

SW2

VFB2

VREG3

TPS51225CRUKR_QFN20_3X3

DRVL211VIN12VREG5

13

12

PC117

0.1U_0603_25V7K

2

20

5V_EN

PC118

1U_0603_10V5K

FB_5V

VFB1

EN1

12

1

CS1

DRVH1

VBST1

DRVL1

15

PR106

PAD

VO1

VCLK

SW1

PR114

1 2

100K_0402_1%~D

12

21

14

19

16

UG_5V

17

BST_5V

18

SW1

LG_5V

1 2

0_0603_5%~D

PR107

2.2_0603_5%

1 2

PC111

0.1U_0603_25V7K

1 2

3 5

241

3 5

241

VL

PC103

0.1U_0402_25V6

PQ102

MDV1528URH 1N PDFN33-8

3.3UH +-20% PCMB063T-3R3MS 6.5A

PR110

4.7_1206_5%

PQ104

MDV1525URH 1N PDFN33-8

PC119

680P_0603_50V7K

12

PC108

PC109

2200P_0402_50V7K

10U_0805_25V6K

PL102

12

SNUB_5V

12

PC104

@

10U_0805_25V6K

12

1

+

PC102

2

150U_B2_6.3VM_R35M

+5VALWP

3 3

3VALWP

3V_EN

TDC 5.95A Peak Current 8.5A

5V_EN

OCP current 10.2A TYP MAX H/S Rds(on): 22mohm , 30mohm L/S Rds(on):10.8mohm ,13.6mohm

4 4

A

EC_ON32

USBCHG_DET_D32

VIN

PD102

2

3

BAS40CW_SOT323-3

VCOUT0_PH#32

PD101

@

LL4148_LL34-2

B

1

12

2.2K_0402_5%

1 2

0_0402_5%

1 2

PR115

@

1M_0402_1%

1 2

PR113

PR117

1 2

PR111 0_0402_5%

1 2

PR112 0_0402_5%

12

PR116

@

PC120

402K_0402_1%

PJP100

+3VALWP

4.7U_0603_6.3V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

1 2

PAD-OPEN 4x4m PJP102

1 2

PAD-OPEN 4x4m

2012/01/17 2013/01/16

+3VALW

+5VALWP

Compal Secret Data

Deciphered Date

PJP101

1 2

PAD-OPEN 4x4m PJP103

1 2

PAD-OPEN 4x4m

D

+5VALW

5VALWP TDC 5.96A Peak Current 8.51A OCP current 10.2A TYP MAX H/S Rds(on):22mohm , 30mohm L/S Rds(on):10.8mohm , 13.6mohm

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PWR-3VALWP/5VALWP

LA-XXXXP

E

57 66Friday, August 10, 2012

0.1

5

PJP200

B+

D D

+1.35VP

C C

@

2

JUMP_43X118

1

+

2

1

1UH_PCMC063T-1R0MN_11A_20%

PC201 330U_2.5V_M

1.35V_B+

12

PC202

PL201

1 2

12

4.7U_0805_25V6-K

12

PC203

PC204

4.7U_0805_25V6-K

4.7_1206_5%

680P_0603_50V7K

0.1U_0402_25V6

12

PR202

SNUB_1.35V

12

PC212

SYSON32,45,59

1.35VP TDC 7.64A Peak Current 10.92A OCP current 13.2A

12

4

PC205

2200P_0402_50V7K

PR206

0_0402_5%~D

1 2

3

VLDOIN_1.35V

PR200

1 2

2.2_0603_5%

PC206

0.22U_0603_10V7K

1 2

PQ201

3 5

241

MDV1528URH 1N PDFN33-8

PR203

5.1_0603_5%

1 2

PQ203

MDV1525URH 1N PDFN33-8

3 5

241

+5VALW

1 2

12

@

1U_0402_6.3VX5R

PC215

SUSP#10,32,45,60

PR208

0_0402_5%~D

1 2

BOOT_1.35V

DH_1.35V

SW_1.35V

DL_1.35V

PR201

13.3K_0402_1%

1 2

12

PC210 1U_0603_10V6K

PC213 1U_0603_10V6K

@

CS_1.35V

VDDP_1.35V

VDD_1.35V

VDDP_1.35V

1.35V_B+

S5_1.35V

S3_1.35V

12

PC216

0.1U_0402_10V7K

15

LGATE

14

PGND

13

CS

12

VDDP

11

VDD

1M_0402_1%

1 2

16

PHASE

RT8207MZQW_W QFN20_3X3

PGOOD

10

PR205

18

17

BOOT

UGATE

S5

TON

8

9

19

VLDOIN

S3

7

2

20

PU200

VTT

PAD

VTTGND

VTTSNS

GND

VTTREF

VDDQ

FB

6

@

PJP201

PAD-OPEN1x1m

21

1

2

3

4

5

1.35V_FB

1 2

12

+1.35VP

VTTREF_1.35V

+1.35VP

PC211 220P_0402_50V8J~D

1 2

PR204

7.68K_0402_1%

PR207 10K_0402_1%

12

PC214 .1U_0402_16V7K

@

1

0.675Volt +/- 5% TDC 0.7A Peak Current 1A OCP Current 1.2A

12

PC207

10U_0805_6.3V6M

+1.35VP

PC208

10U_0805_6.3V6M

PC209

0.033U_0402_16V7~D

+0.675VSP

TYP MAX H/S Rds(on) :22mohm , 30mohm

B B

L/S Rds(on) :10.8mohm ,13.6mohm

+0.675VS

@

PJP202

12

PAD-OPEN1x1m

+0.675VSP

PJP203

+1.35V +1.35VP

2 1

PAD-OPEN 1x2m~D@

PJP204

2 1

PAD-OPEN 1x2m~D@

A A

Security Classification

2012/01/17 2013/01/16

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

2012/01/17 2013/01/16

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PWR-1.35VP/0.675VSP

LA-XXXXP

1

0.1

58 66Friday, August 10, 2012

5

4

3

+1.05VP_B+

2

PJP300

2 1

PAD-OPEN 1x2m~D@

1

B+

+3VS

12

D D

PR302

1 2

PR303

0_0402_5%~D

SYSON32,45,58

C C

1 2

0.22U_0402_16V7K

120K_0402_1%

12

PC307

@

TRIP_+1.05VP

EN_+1.05VP

FB_+1.05VP

RF_+1.05VP

12

PR305

470K_0402_1%

PR300 10K_0402_1%

1 2

PU300

1

PGOOD

2

TRIP

3

EN

4

VFB

5

TST

TPS51212DSCR_SON10_3X3

PR306

4.99K_0402_1%

PC306

PR301

10

9

8

7

6

11

BST_+1.05VP

UG_+1.05VP

SW_+1.05VP

+1.05VP_5V

LG_+1.05VP

VBST

DRVH

SW

V5IN

DRVL

TP

12

1 2

2.2_0603_5%

PC308

1 2

1U_0603_10V6K

.1U_0603_25V7K

12

+5VALW

MDV1525URH 1N PDFN33-8

PQ303

PQ301 MDV1528URH 1N PDFN33-8884_POWER33-8-5

3 5

241

1UH_PCMC063T-1R0MN_11A_20%

12

PR304

4.7_1206_5%

SNB_1.05VP

12

PC309

3 5

241

1000P_0402_50V7K

PC303

PC302

0.1U_0402_25V6

2200P_0402_50V7K

PL301

1 2

PC305

PC304

4.7U_0805_25V6-K

+1.05VP

1

+

PC301 220U_B2_2.5VM_R15M

2

PR307 10K_0402_1%

1 2

PJP301

B B

+1.05V +1.05VP

@

1 2

PAD-OPEN 4x4m

PJP302

@

1 2

PAD-OPEN 4x4m

+1.05VP TDC 7.315A Peak Current 10.45A OCP current 12.54A TYP MAX H/S Rds(on) :22mohm ,30mohm L/S Rds(on) :10.8mohm , 13.6mohm

A A

Security Classification

2012/01/17 2013/01/16

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

2012/01/17 2013/01/16

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PWR-+1.05VSP

LA-XXXXP

0.1

59 66Friday, August 10, 2012

1

59 66Friday, August 10, 2012

A

1 1

B

C

D

PR400

12

10K_0402_5%

+3VS

+1.5VSP TDC 1.13A Peak Current 1.62A OCP current 2.1A

PU400

PJP400

+3VALW

2 2

SUSP#10,32,45,58

2 1

PAD-OPEN 1x2m~D@

12

0_0402_5%

1 2

PR403

PC400 22U_0805_6.3VAM

EN_1.5VSP

1.5VSP_VIN

12

PC401

0.1U_0402_25V6

PR404

@

47K_0402_5%

12

10

9

8

5

PC406

.1U_0402_16V7K

@

4

PVIN

SVIN

EN

LX

PG

LX

FB

TP

NC

7

11

1

SYN470DBC_DFN10_3X3

2

3

6

1.5VSP_LX

1.5VSP_FB

1UH_NRS4018T1R0NDGJ_3.2A_30%

12

PR401

@

SNUB_1.5VSP

12

PC407

@

PL401

1 2

30.1K_0402_1%

4.7_0603_5%

20K_0402_1%

PR402

PR405

+1.5VSP

12

PC402

22P_0402_50V8J

12

PC403

12

22U_0805_6.3VAM

12

PC404

22U_0805_6.3VAM

PC405

47P_0402_50V8J

680P_0402_50V7K

3 3

PJP401

+1.5VS

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

2 1

PAD-OPEN 1x2m~D@

+1.5VSP

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PWR-1.5VSP

LA-7902P

D

60 66Friday, August 10, 2012

0.1

5

4

3

2

1

PC507

2200P_0402_50V7K~D

12

1 2

12

PL502

12

PL503

12

1

CPU_B+

PL504

12

PC530

12

1

+

2

+VCC_CORE

PR515

1 2

10_0402_1%

ISUMN

B+

+VCC_CORE

12

PR544 10_0402_1%

ISUMN

1

+

PC531

100U_25V_M

PC532

2

100U_25V_M

+VCC_CORE

12

PR556 10_0402_1%

ISUMN

61 66Friday, August 10, 2012

1

+

2

100U_25V_M

0.1

+5VS

UGATE

BOOT

PHASE

LGATE

12

PC501

PR502

2.2_0603_5%

1

2

8

5

BOOT3

1 2

12

UGATE2

PHASE2

BOOT2

LGATE2

BOOT1

2.2_0603_5%

LGATE1

UGATE3

CPU_PHASE3

LGATE3

2.2_0603_5%

UGATE1

PHASE1

PR550

PR534

12

1 2

PC522

0.22U_0603_16V7K

12

1 2

PC542

0.22U_0603_16V7K

PQ505

@

PQ507

PQ509

@

4

PQ511

4

12

+VCCIO_OUT

D D

PR505 0_0402_5%

VIDSOUT10

VIDALERT_N10

VIDSCLK10

IMVP_VR_ON32

PR519 1.91K_0402_1%

+3VS

IMVP_PWRGD6,15,32

PC500

1 2

0.01U_0402_50V7K

PR521

100K_0402_1%

C C

VR_HOT#32

+1.05VS

B B

ISEN3

ISEN2

ISEN1

A A

12

PR527

@

1 2

0_0402_5%

1800P_0402_50V8F~D

PR542

@

1 2

154K_0402_1%

PC539

0.22U_0402_6.3V6K

12

PC540

0.22U_0402_6.3V6K

12

PC544

0.22U_0402_6.3V6K

12

@

1 2

PC547

12

PC510

47P_0402_50V8J~D

39P_0402_50V8J

PC519

12

PR539

909_0402_1%

1 2

PC526

4700P_0402_50V7K~D

ISUMN

12

.1U_0402_16V7K

56P_0402_50V8

1 2

PR506 0_0402_5%

1 2

PR508 0_0402_5%

1 2

PR522

0_0402_5%~D

1 2

PR524

1 2

0_0402_5%~D

PR525

1 2

3.83K_0402_1%

@

PC517

12

PR532

130K_0402_1%

PC523

@

22P_0402_50V8J~D

PC525

@

12

PR500 110_0402_1%~D

12

PR503 75_0402_5%@

12

PR504 54.9_0402_1%

PR511 0_0402_5%

VCC_PGOOD

VR_HOT#1

470K_0402_5%_ TSM0B474J4702RE

12

VCCSENSE10

1 2

PR528

27.4K_0402_1%

FBCOMP

10_0402_1%

PR543 2K_0402_1%

1 2

PC527 330P_0402_50V7K~D

1 2

VSSSENSE10

12

VR_ON

IMON

NTC

12

PH500

12

FB2/VSEN

PR533

12

PR537

2.94K_0402_1%

PC541

@

1 2

330P_0402_50V7K

PC546

1 2

0.01U_0402_50V7K

SDA

ALERT#

1

SCLK

2 3 4 5 6 7

COMP

8

FB

33

PR529

@

1 2

0_0402_5%

PC520

390P_0402_50V7K

12

@

PR507

49.9K_0402_1%~D

1 2

PR509

34K_0402_1%

1 2

PR512

24.9K_0402_1%

1 2

32

SCLK VR_ON PGOOD IMON VR_HOT# NTC COMP FB

PAD

PR531

0_0402_5%

@

1 2

PR540

0_0402_5%

1 2

12

PC545

0.082U_0402_16V7K

BOOT2 UGATE2

PHASE2

25

26

27

28

30

31

29

SDA

BOOT2

PROG2

PROG3

ALERT#

FB2/VSEN9ISEN310ISEN211ISEN112RTN13ISUMN14ISUMP15VDD

10KB_0402_5%_ERTJ0ER103J

PHASE2

UGATE2

LGATE2

SLOPE/PROG1

VDDP

PWM3

LGATE1 PHASE1 UGATE1

BOOT1

PU500

16

ISL95812HRZ-T_QFN32_4x4

12

PC521

12

4700P_0402_50V7K~D

PR545

1 2

1.5K_0402_1%

PR548

0_0402_5%

1 2

ISUMN

1 2

PWM3

1U_0603_10V6K

24 23 22 21 20 19 18 17

VIN

12

PR535

549 +-1% 0402

PC528

0.1U_0402_10V6K~D

1 2

PC529

0.1U_0603_25V7K~D

1 2

PC538

0.033U_0603_25V7M~D

1 2

PR549

11K_0402_1%

1 2

PH501

2.61K_0402_1%

1 2

PR501

LGATE1

12

PC502

0_0402_5%~D

+5VS

PC509

1 2

LGATE2

PWM3

PHASE1

UGATE1

BOOT1

PR526

0_0402_5%~D

1 2

PC511

0.22U_0603_25V7K

PR530

1_0603_1%

1 2

PC518

1U_0603_10V6K

PR551

1 2

VCORE_VDDP

0.22U_0603_16V7K

1U_0603_10V6K

PU501

6

VCC

7

FCCM

3

PWM

4

GND

9

TP

ISL6208BCRZ-T_QFN8_2X2

PR520 0_0402_5%~D

@

PR523

0_0402_5%~D

CPU_B+

+5VS

ISUMP

Local sense put on HW site

DELL CONFIDENTIAL/PROPRIETARY

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

PQ501

@

PQ503

5

4

123

5

4

213

MDU1516URH 1N POWERDFN56-8

MDU1511RH 1N POWERDFN56-8

PQ502

4

PQ504

4

5

12

PC503

PC505

10U_0805_25V6K

123

MDU1516URH 1N POWERDFN56-8

5

213

12

PC508

SNB_CPU_P3

680P_0603_50V7K

12

PR513

4.7_1206_5%

MDU1511RH 1N POWERDFN56-8

VCC_core (Base on PDDG rev 0.8) TDC 27A Peak Current 85A DC Load line -1.5mV/A Icc_Dyn_VID1 60A OCP current 105A DCR 0.98m ohm

123

PC533

MDU1516URH 1N POWERDFN56-8

MDU1511RH 1N POWERDFN56-8

12

10U_0805_25V6K

PR554

CPU_B+

12

PC512

PC513

10U_0805_25V6K

PR541

4.7_1206_5%

CPU_B+

PC534

12

SNB_CPU_P1

12

4.7_1206_5%

12

SNB_CPU_P2

12

10U_0805_25V6K

PC543

3.65K_0603_1%

PC524

680P_0603_50V7K

ISUMP

12

PC535

10U_0805_25V6K

PR552

3.65K_0603_1%

1 2

680P_0603_50V7K

ISUMP

Title

Size Document Number Rev

Date: Sheet of

5

4

MDU1516URH 1N POWERDFN56-8

123

5

4

213

MDU1511RH 1N POWERDFN56-8

5

PQ510

4

123

MDU1516URH 1N POWERDFN56-8

5

213

PQ512

4

MDU1511RH 1N POWERDFN56-8

2

PQ506

PQ508

4

5

4

5

213

123

MDU1516URH 1N POWERDFN56-8

5

213

MDU1511RH 1N POWERDFN56-8

12

PC506

10U_0805_25V6K

0.22UH_FDUE0640-H-R22M=P3_25A_20%~D

PR514

1 2

3.65K_0603_1%

ISUMP

12

PC514

10U_0805_25V6K

PR536

1 2

ISEN2

V1N

V3N

PC536

0.1U_0402_25V6K~D

ISEN1

V2N

V3N

Compal Electronics, Inc.

12

PC504

10U_0805_25V6K

0.1U_0402_25V6K~D

PL501

PR510

10K_0603_1%

ISEN3

PR516

@

1_0402_5%

1 2

V1N

PR518

@

1_0402_5%

1 2

V2N

FBMA-L11-453215-800LMA90T_1812

12

PC515

PC516

0.1U_0402_25V6K~D 2200P_0402_50V7K~D

0.22UH_FDUE0640-H-R22M=P3_25A_20%~D

PR538

10K_0603_1%

1 2

PR546

@

1_0402_5%

PR547

@

1_0402_5%

12

PC537

2200P_0402_50V7K~D

0.22UH_FDUE0640-H-R22M=P3_25A_20%~D

PR553

10K_0603_1%

1 2

PR555

@

1_0402_5%

PR557

@

10K_0402_1%

+VCC_CORE

LA-XXXXP

+3VS

47

B+

FBMA-L11-453215-800LMA90T_18 12

PL600

1 2

12

PC600

PC601

10U_0805_25V6K

GPU_B+

12

PC602

10U_0805_25V6K

PC603

12

PC604

10U_0805_25V6K

12

PC605

10U_0805_25V6K

12

PC606

PC607

10U_0805_25V6K

PC608

10U_0805_25V6K

12

PC609

PC610

10U_0805_25V6K

12

PC611

10U_0805_25V6K

12

PC626

.01U_0402_16V7K

VSSSENSE_VGA

47

+VGA_CORE

TDC=45A Peak Current=58A OCP=70A TYP MAX L/S Rds(on):2.7mohm ,3.3mohm

1U_0402_6.3V6K

12

PC613

STDBY_EN46

12

@

VCCSENSE_VGA

@

PR620 0_0402_5%~D

@

2

G

PR631 10K_0402_1%~D@

GPU_B+

PR622

0_0402_5%~D

1 2

PR624

100_0402_1%~D

1 2

PR627

0_0402_5%~D

1 2

PR629

100_0402_1%~D

1 2

GPU_REFIN

12

PR623 3K_0402_1%~D

13

D

S

PQ610

GPU_FBRTN

PR621

0_0402_5%~D

1 2

2N7002KW_SOT323-3

12

1 2

PR628

0_0402_5%~D

15.8K_0402_1%~D

1 2

@

1 2

PR616

12

12K_0402_1%~D

PR618 0_0402_5%~D

GPU_FBRTN

PR650

499K_0402_1%

12

PC620

@

.01U_0402_16V7K

@

1 2

0_0402_5%~D

1 2

PR630

1 2

PR632

1 2

47P_0402_50V8J

PC624

0_0402_5%~D

2200P_0402_50V7K

33P_0402_50V8J~D

PR611

PC616

PC631

@

PC623

.01U_0402_16V7K@

12

PR606 14K_0402_1%~D

12

PR609 0_0402_5%~D

PR612

0_0402_5%~D

1 2

PC617

12

@

.01U_0402_16V7K

GPU_REFIN

GPU_VREF

GPU_TON

GPU_FBRTN

GPU_FB

GPU_COMP

1 2

PHASE3

PR638

10K_0402_1%

PR613

12K_0402_1%~D

1 2

PU600

7

REFIN

8

VREF

9

TON

10

RGND

11

VSNS

12

SS

GND

25

PR646

1 2

10K_0402_1%

U2_PHASE2

12

PR600 0_0402_5%~D

@

12

PR602 0_0402_5%~D

@

47P_0402_50V8J~D

GPU_PSI

GPU_REFADJ

6

13

GPU_TSNS/ISEN3

GPU_EN

GPU_VID

5

REFADJ

TSNS/ISEN3

14

GPU_TALERT/ISEN2

U2_UGATE1U2_UGATE2

4

3

2

EN

PSI

VID

UGATE1

TALERT/ISEN2

PGOOD

VCC/ISNE1

17

16

15

GPU_PGOOD1

GPU_DSBL/ISEN1

PR639

PC627

@

PR648

1 2

10K_0402_1%

U2_PHASE1

PR610

0_0402_5%~D

1 2

PR607

0_0402_5%~D

1 2

12

PC614

@

U2_BOOT1

1

BOOT1

GND/PWM3

BOOT218UGATE2

U2_BOOT2

+3VS

12

24

PHASE1

23

LGATE1

22

21

PVCC

20

LAGTE2

19

PHASE2

RT8813AGQW_W QFN24_4X4

GPU_PGOOD49,50,65

PR619

0_0402_5%~D

10K_0402_1%~D

1 2

.01U_0402_16V7K

NVVDD PWM_VID 46

+3VS

12

PR614

@

10K_0402_1%~D

12

PC618

47P_0402_50V8J~D

U2_PHASE1

U2_LGATE1

U2_PWM3

U2_LGATE2

U2_PHASE2

2.2_0603_1%~D

.1U_0603_25V7K

+5VS

U2_PWM3

0_0402_5%~D

NVVDD PSI 46

0_0402_5%~D

1 2

2.2_0603_1%~D

1 2

12

+5VS

PR643

PC629

PR641

1K_0402_1%~D

1 2

PR642

U2_BOOT1

U2_UGATE1

U2_PHASE1

PR615

U2_BOOT2

PR625

PC622

.1U_0603_25V7K

12

PR601

2.2_0603_1%~D

1 2

U2_LGATE1

U2_UGATE2

U2_PHASE2

+5VS

PU601

8

VCC

1

EN

5

PWM

6

GND

TP

RT9610BZQW W DFN8 MOSFET DRIVER ET88

9

12

PC612

.1U_0603_25V7K

PR649

DGPU_PWR_EN 32,46,49,50

PR617

2.2_0603_1%~D

1 2

U2_LGATE2

UGATE

BOOT

PHASE

LGATE

1 2

12

2.2_0603_1%~D

1 2

3

UG3

4

2

7

LG3

.1U_0603_25V7K

PR633

PHASE3

GPU_B+

5

PQ601

4

MDU1516URH 1N POWERDFN56-8

123

4

MDU1511RH 1N POWERDFN56-8

4

MDU1511RH 1N POWERDFN56-8

5

PQ608

5

PQ603

PR608

321

MDU1511RH 1N POWERDFN56-8

GPU_B+

5

PQ604

123

MDU1516URH 1N POWERDFN56-8

5

PQ606

PR626

321

MDU1511RH 1N POWERDFN56-8

GPU_B+

5

PQ607

4

123

5

PQ609

4

321

MDU1511RH 1N POWERDFN56-8

321

5

PQ602

4

321

10K_0402_1%

PC619

5

PQ605

4

321

12

PC625

.1U_0603_25V7K

4

PL601

0.22UH_FDUE0640-H- R22M=P3_25A_20%~D

12

4.7_1206_5%

PC615

0.22UH_FDUE0640-H- R22M=P3_25A_20%~D

12

4.7_1206_5%

PC621

MDU1516URH 1N POWERDFN56-8

0.22UH_FDUE0640-H- R22M=P3_25A_20%~D

PR640

MDU1511RH 1N POWERDFN56-8

12

680P_0603_50V7K

PL602

12

680P_0603_50V7K

PL603

12

4.7_1206_5%

PC628

680P_0603_50V7K

+VGA_CORE

Compal Electronics, Inc.

Title

Size Docume nt Number Rev

Date: Sheet of

Compal Electronics, Inc.

+VGA_CORE

LA-XXXXP

62 66Friday, August 10, 2012

0.1

A

VIN

PQ702 SI7149DP

1 2

4

PQ718A

Back_G1

13

DMN66D0LDW-7 2N SOT363-6

PC729

2

G

3

PQ707

2

PQ709

DDTC115EUA-7-F_SOT323

ACIN15,32,36,56

13

PQ713

12

13

D

PQ715 SSM3K7002FU_SC70-3

S

1 3

5

DDTC115EUA-7-F_SOT323

5

12

1 1

3.3_1210_5%

PR701

12

3.3_1210_5%

PR706

1 2

PC701

2.2U_0805_25V6K

2

2 2

ACIN

PR723

1 2

10K_0402_5%

ACOFF

BATT_TEMP

3 3

BATT_TEMP32,56,63

PDTA144EU PNP_SOT323

12

PR704

200K_0402_1%

2

V1

61

PQ710A

DMN66D0LDW-7 2N SOT363-6

PR720

47K_0402_5%

1 2

2

61

2

H_PROCHOT#6,32

1U_0603_25V6K

@

P2

12

PR707 150K_0402_1%

3

4

ACIN

100_0402_1%

ADP_I32,56

.1U_0402_16V7K

@

12

PQ710B

DMN66D0LDW-7 2N SOT363-6

PR717

PR721

PR729

PC732

1 2 3

12

PC702

0.1U_0603_25V7K

VDDP_LDO

12

100K_0402_1%

12

158K_0402_1%

1 2

PR702

200K_0402_1%

BATT_TEMP32,56,63

+5VALW

12

PC717

0.1U_0402_10V7K

12

PR730

4.7K_0402_5%

@

ISL8731_REF

12

33K_0402_1%~D

PR735

12

PC733

PR736

0.01U_0402_25V7K

16.9K_0402_1%~D

@

PQ703SI7149DP

4

Back_G2

@

5

12

PC710

@

0.1U_0402_10V7K

1000P_0402_50V7K

PC714

1 2

EC_SMB_CK132,56

EC_SMB_DA132,56

PC735

0.01U_0402_25V7K

12

PC734

@

0.01U_0402_25V7K

5

PC703

3

4

PR719

49.9K_0402_1%

12

Iada=0~9.23A(180W)

P3

ADP_I = 19.9*Iadapter*Rsense

1 2

5600P_0402_25V7K~D

VIN

PQ716B

1U_0603_25V6K

DMN66D0LDW-7 2N SOT363-6

VIN

PR715

1 2

PR722

0_0402_5%

PR724

0_0402_5%

12

@

PR738

33K_0402_1%~D

ISL8731_ICREF

12

@

PR739

33K_0402_1%~D

PR703

0.01_2512_1%~D

1

2

PR712

10_1206_1%

1 2

PC712

210K_0402_1%

12

ISL8731_EAJ

@

B

12

ACSETIN

ISL8731_REF

12

PC728

0.1U_0402_10V7K

4

3

DCIN

CSIN

CSIP

12

PR708

10_0402_5%

1 2

PC708

0.1U_0402_25V6K~D

ISL8731_ICREF

PU700

22

DCIN

2

ACIN

13

ACOK

11

VDDSMB

10

SCL

9

SDA

14

NC

8

VICM

6

FBO

5

EAI

4

EAO

3

VREF

7

CE

12

GND

29

TP

ISL88731CHRTZ-T_QFN28_5X5~D

0.047U_0603_25V7M

ISL8731_CSIP

1

28

CSSP

ICREF

PC713

1 2

ISL8731_CSIN

27

ICOUT

CSSN

BOOT

VDDP

UGATE

PHASE

LGATE

PGND CSOP

CSON

VFB

NC

C

D

B+

PQ704SI7149DP

1 2 3

CHG_B+

4

Dis_G

12

PR710

47K_0402_1%

1 2

13

PQ711

PQ701

5

4

123

PQ714

3 5

241

DDTC115EUA-7-F_SOT323

MDU1516URH 1N POWERDFN56-8

5.6UH_FDVE1040-H-5R6M-P3_9.2A_20%~D

MDV1525URH 1N PDFN33-8

PL702

1 2

12

4.7_1206_5%

PR728

SNUB_CHG

12

PC719

680P_0402_50V7K

1 2

0.1U_0402_25V6K~D PR713

4.7_0603_5%

PR716

0_0603_5%

1 2

PR734

100_0402_5%

PL701

PC709 1U_0603_10V6K

12

BST_CHGA

BATT+

12

PC705

PC704

4.7U_0805_25V6-K

0.1U_0603_25V7K

1U_0603_10V6K

PC706

PC715

1 2

PC716

1 2

DL_CHG

12

0.1U_0603_25V7K

PC707

2200P_0402_50V7K~D

1UH_NRS4018T1R0NDGJ_3.2A_30%

12

PR709

10_0402_5%

PC711

1 2

26

25

BST

21

VDDP_LDO

24

DH_CHG

23

LX_CHG

20

19 18

17

15

VFB

16

5

200K_0402_1%

1 2

2

VDDP_LDO

CHG

12

10_0402_5%

PR731

0.22U_0603_25V7K

PR705

100K_0402_1%

PR711

1 2

10K_0402_5%

ACOFF32,63

PR725

0.01_1206_1%

1

2

PC726

1 2

PR714

VIN

V1

61

2

4

3

12

0_0402_5%

PR732

PC731

1 2

0.1U_0402_25V6K~D

3

5

PQ717B

4

DMN66D0LDW-7 2N SOT363-6

PQ717A

DMN66D0LDW-7 2N SOT363-6

BATT+

12

PC721

PC720

10U_0805_25V5K~D

@

PC722

10U_0805_25V5K~D

12

PC723

@

10U_0805_25V5K~D

For DT Mode

VIN

12

4 4

ACOFF

5

PR737

3.3K_1206_5%~D

3

PQ718B

4

DMN66D0LDW-7 2N SOT363-6

A

BATT_TEMP32,56,63

V1

@

61

2

PQ716A

DMN66D0LDW-7 2N SOT363-6

B

Security Classification

2012/01/17 2013/01/16

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/01/17 2013/01/16

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PWR-Charger

LA-XXXXP

D

0.1

63 66Friday, August 10, 2012

5

Based on PDDG rev 0.7 Table 5-1.

4

3

2

1

+VCC_CORE+VCC_CORE

D D

1

PC900 10U_0805_4VAM

2

1

PC909 10U_0805_4VAM

2

1

PC901 10U_0805_4VAM

2

1

PC910 10U_0805_4VAM

2

1

PC902 10U_0805_4VAM

2

1

PC911 10U_0805_4VAM

2

1

PC903 10U_0805_4VAM

2

1

PC912 10U_0805_4VAM

2

1

PC904 10U_0805_4VAM

2

1

PC913 10U_0805_4VAM

2

1

PC914 10U_0805_4VAM

2

1

+

PC905

2

330U 2.5V Y D2 LESR9M EEFS H1.9

1

+

PC906

2

330U 2.5V Y D2 LESR9M EEFS H1.9

1

+

PC907

2

330U 2.5V Y D2 LESR9M EEFS H1.9

1

+

PC908

2

330U 2.5V Y D2 LESR9M EEFS H1.9

1

+

PC915

2

330U 2.5V Y D2 LESR9M EEFS H1.9

+VCC_CORE

1

PC917 22U_0805_6.3VAM

2

1

PC918 22U_0805_6.3VAM

2

1

PC919 22U_0805_6.3VAM

2

1

PC920 22U_0805_6.3VAM

2

1

PC921 22U_0805_6.3VAM

2

+VGA_CORE

C C

1

PC922 22U_0805_6.3VAM

2

1

PC935 22U_0805_6.3VAM

2

1

PC923 22U_0805_6.3VAM

2

1

PC936 22U_0805_6.3VAM

2

1

PC924 22U_0805_6.3VAM

2

1

PC937 22U_0805_6.3VAM

2

1

PC925 22U_0805_6.3VAM

2

1

PC938 22U_0805_6.3VAM

2

1

PC926 22U_0805_6.3VAM

2

1

PC939 22U_0805_6.3VAM

2

.1U_0402_16V7K

12

PC927

.1U_0402_16V7K

12

PC928

12

PC929

.1U_0402_16V7K

@

12

PC930

.1U_0402_16V7K

@

12

PC931

12

PC932

.1U_0402_16V7K

@

12

PC933

PC934

+GPU_CORE

4.7U_0805_6.3V6K~D

47U_0805_6.3V6M~D

1

PC940 22U_0805_6.3VAM

2

B B

A A

1

PC941 22U_0805_6.3VAM

2

1

PC942 22U_0805_6.3VAM

2

1

PC943 22U_0805_6.3VAM

2

12

1

PC944

2

4.7U_0603_6.3V6K~D

PC954

12

4.7U_0805_6.3V6K~D

22U_0805_6.3VAM

PC945

4.7U_0603_6.3V6K~D

PC955

12

PC946

4.7U_0603_6.3V6K~D

@

PC956

12

PC947

4.7U_0603_6.3V6K~D

PC957

12

4.7U_0805_6.3V6K~D

12

PC948

4.7U_0603_6.3V6K~D

PC958

12

4.7U_0805_6.3V6K~D

12

PC949

PC950

4.7U_0603_6.3V6K~D

@

PC960

PC959

12

4.7U_0603_6.3V6K~D

PC951

12

4.7U_0603_6.3V6K~D

PC961

12

4.7U_0603_6.3V6K~D

@

PC952

PC953

12

4.7U_0603_6.3V6K~D

@

PC963

PC962

12

4.7U_0603_6.3V6K~D

@

PC964

12

1

PC965

+

2

1

+

2

PC966

470U_D2_2VM_R4.5M~D

1

+

2

PC967

470U_D2_2VM_R4.5M~D

1

+

2

PC968

1

+

2

PC969

PC970

470U_D2_2VM_R4.5M~D

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR DECOUPLING

LA-XXXXP

1

64 66Friday, August 10, 2012

0.1

5

4

3

2

1

PR1000

10K_0402_5%

1 2

D D

1 2

PR1004 0_0402_5%

0_0402_5%

PR1009

@

12

FBVDDQ_PWR_EN50

GPU_PGOOD49,50,62

12

EN_+1.35VDGPUP

12

PC1011

.1U_0402_16V7K~D

@

PR1003 47.5K_04 02_1%~D

FB_+1.35VDGPUP

TRIP_+1.35VDGPUP

12

PR1006

470K_0402_1%

+3VS

PU1000

1

2

3

4

5

VBST

PGOOD

TRIP

DRVH

EN

VFB

RF

TPS51212DSCR_SON10_ 3X3

SW

V5IN

DRVL

TP

10

9

8

7

6

11

2.2_0603_5%

BST_+1.35VDGPUP

DH_+1.35VDGPUP

LX_+1.35VDGPUP

+1.35VDGPUP_5V

DL_+1.35VDGPUPRF_+1.35VDGPUP

1 2

PR1002

PC1008

0.1U_0603_25V7K~D

1 2

+5VALW

12

PC1013

4.7U_0805_10V6K

5

PQ1001

4

123

5

PQ1003

4

213

MDU1516URH 1N POWERDFN56-8

+1.35VDGPUP_B+

12

PC1004

PC1003

2200P_0402_50V7K~D

0.68UH_PCMC063T-R68 MN_15.5A_20%

1 2

12

PR1005

4.7_1206_5%

@

SNUB_+1.35VDGPUP

12

PC1014

680P_0402_50V7K~D

@

0.1U_0603_25V7K~D

PL1001

PC1005

4.7U_0805_25V6K~D

12

PC1006

4.7U_0805_25V6K~D

PR1010 0_0402_5%

@

12

PC1007

@

4.7U_0805_25V6K~D

PC1001

220U_D2_2VY_R15M

PJP1000

2

112

JUMP_43X79@

B+

+1.35VDGPUP

1

+

PC1012

2

220U_D2_2VY_R15M

@

2

PJP1001

JUMP_43X118@

PJP1002

JUMP_43X118@

112

+1.35VS_VGA+1.35VDGPUP

+1.35VDGPUP (for VRAM) TDC 14.72 A Peak Current 21.03 A

PR1007

1 2

C C

9.31K_0402_1%~D

12

PR1008 10K_0402_1%

MDU1511RH 1N POWERDFN56-8

PR1011 10_0402_1%

12

FB_VDDQ_SENSE 48

OCP current TDC

B B

A A

Security Classification

2011/01/31 2012/01/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2011/01/31 2012/01/31

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PWR-+1.35VSDGPUP

Size Document Num ber Rev

C

LA-XXXXP

Date: Sheet of

1

65 66Friday, August 10, 2012

0.1

5

Request

RequestRequest

Item

Item Issue Description

ItemItem

Page# Title

Page#Page#

Title

TitleTitle

Date

DateDate

Owner

OwnerOwner

4

Version Change List ( P. I. R. List )

Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )

Issue DescriptionDate

Issue DescriptionIssue Description

3

Page 1

Page 1Page 1

2

Solution Description

Solution Description Rev.

Solution DescriptionSolution Description

1

Rev.Page#

Rev.Rev.

D D

1 56 7/24 PD5 pin1 change from +RTC_BATT to +RTC_CELL

2

3

57

56

Power

7/24

63

4

5

C C

6

7

57 Power Compal7/30 For OTP

64 Power 7/30 Compal Update Memo

Power

Power Compal

7/24

7/2456 For De-rating

Compal

Compal7/24

Compal

HW and Power has the same part

Shortage issue

Adapter protect function56

PC111、PC112 change from SE042104M80 to SE042104K8L

PQ1,PQ710,PQ716,PQ717,PQ718 change from SB00000O600 to SB00000DH0L

PR23 change from 340K ohm to 681K ohm

PR530 change size from 0402 to 0603

Del PD100.Add PR117

Change SGA0000420L to SGA0000268L PC905,PC906,PC907,PC908,PC915

8

62 Power 7/30 Compal For VGA CORE

Change PU600 from UP1642 to RT8831A Change PU601 from UP1909 to RT9610B

9

62 Power 8/1 Compal For VGA CORE

Change PR638,PR646,PR648 from 2k to 10k

Unpop PR632,PC623 Add PC624 47pF

Unpop PR628,PC631 Add PR630,PR620 o ohm

Change PR650 from 68.1k to 499k

B B

Change PC616 from 0.01uF to 2.2nF

Add PR649 10k ohm

10

58 Power 8/3 Compal For 1.35V output voltage and Dfx request

Change PR204 from 8.06k to 7.65k

Change PJP203,PJP204 size from 4x4m to 1x2m

11

14

15

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PWR_PIR

LA-9201P

1

66 66Friday, August 10, 2012

0.2

Compal LA-9201P Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual