Compal LA-8681P PAWGE, G480, G485 Schematic

A

1 1

B

C

D

E

Compal Confidential

2 2

PAWGE Schematics Document

AMD APU Zacate-FT1 + FCH Hudson-M3L + GPU RobsonXT

3 3

2011-11-21

REV:1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/06/30 2012/06/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

LA8681P

1 48Tuesday, November 29, 2011

E

1.0

A

Compal confidential

File Name : PAWGE

B

C

D

E

QIWG5

LS7981P CardReader/B LS7982P USB/B LS7983P PWR/B

1 1

LVDS Conn.

page 22

CRT Conn.

page 24

AMD Brazos APU

FT1

Memory BUS(DDRIII)

Single Channel

1.5V DDRIII 1333

200pin DDRII-SO-DIMM X2

BANK 0, 1, 2, 3

page 8,9

BGA 413-Ball

AMDRosbon XT_M2

VRAM 64*16

DDR3*4

page 15 ~ 21

2 2

HDMI Conn.

page 23

x4 PCI-E GPP GEN2

4 * x1 PCI-E 1.0

WLAN &WiMax

page 29

GIGA LAN

RTL8111/8105

page 25,26

3 3

PCI Express Mini card Slot 1

WLAN/WiMAX

page 29

USB(WiMAX)

PCI-E(WLAN)

SPI ROM

page 11

19mm x 19mm

page 5,6,7

x4 UMI Gen. 2

Hudson M3L

BGA 656-Ball 23mm x 23mm

page 10,11,12,13,14

LPC BUS

EC

ENE KB9012

page 30

10*USB2.0

2*SATA serial

Int.KBD

page 32

AZALIA

2Channel Speaker

page 22

page 28

Internal MIC

Audio Jacks

Stereo HeadPhone Output Microphone Input

Audio Codec

CX20671

page 27

CMOS Camera

BlueTooth CONN

USB PORT 2.0 x2(Left)

USB PORT 3.0 x2(Right)

WLAN/WiMAX

Card Reader

Realtek RTS5178 SD/MMC

Daoughter board

page 27

page 33

page 34

QIWG6

LS7981P CardReader/B LS7982P USB/B LS7983P PWR/B LS7984P LED/B LS7985P ODD/B

Touch Pad

page 32

SATA3.0 HDD CONN

page 28

Thermal Sensor

4 4

A

B

EMC1403

page 29

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/06/30 2012/06/30

SATA ODD CONN

Compal Secret Data

Deciphered Date

page 28

D

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

Compal Electronics, Inc.

Block Diagrams

LA8681P

2 48Tuesday, November 29, 2011

E

1.0

A

Voltage Rails

Power Plane Description

VIN

B+

+APU_CORE

1 1

2 2

+APU_CORE_NB 1.0V switched power rail ON OFF

+1.5V

+0.75VS 0.75VS switched power rail for DDR terminator

+1.0VS

+1.1VS 1.1VS switched power rail ON OFF OFF

+1.8VS 1.8V switched power rail

+3VALW

+3V_LAN 3.3V power rail for LAN ON ON(WOL) OFF

+3VS

+5VALW

+5VS

+VSB VSB always on power rail ON ON*

+RTCVCC RTC power

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

EC SM Bus1 address

Device

Smart Battery

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU (0.7-1.2V)

1.5V power rail for CPU VDDIO and DDRIII

1.0V switched power rail for NB VDDC & VGA

3.3V always on power rail

3.3V switched power rail

5V always on power rail

5V switched power rail

EC SM Bus2 address

Address Address

0001-011xb

HEX

Device

EMC1412-2 (dGPU)

EMC1403-2(DDR,WLAN)

SB-TSI

B

S1 S3 S5

N/A N/A N/A

ON OFF

ON

ON OFF OFF

ON

1111-100xb

1001-101xb

1001-100xb

N/AN/AN/A

OFF

ON

OFF

ON ON*

OFF

ON ON*

OFF

OFFON

ONON

ON ON*ON+1.1VALW 1.1V always on power rail

HEX

F8H15H

9AH

98H

C

FCH Hudson-M3L USB Port List

USB1.1

Port0

Port1

USB2.0

Port0

Port1

Port2

Port3

Port4

Port5

Port6

Port7

Port8

Port9

Port10

Port11

Port12

Port13

NC

Right USB

Mini-PCIE

USB Camera

NC

CardReader

BT

NC

Left USB1 Left USB2

NC

Brazos PCIE Port List

PCIE0

APUFCH

PCIE1

PCIE2

PCIE3

PCIE0

PCIE1

PCIE2

PCIE3

GPU PCIE x4

LAN

WLAN

NC

D

FCH Hudson-M3L SATA Port List

SATA0

SATA1

SATA2

SATA3

SATA4

SATA5

BOM Structure

UMA@ : UMA only PX@ : DIS muxluss PX 4.0

Robson@ : Robson GPU GIGA@ : RTL8111 1000 8105@ : RTL8105 10/100

E

HDD

ODD

NC

DIMM@ : DIMM select

SM Bus Controller 0

Device Address

APU SIC/SID (FCH_SMB3)

H_THERMTRIP# (FCH_ALERT#)

(FCH_SMB1 ~ FCH_SMB4, SMB_AL ERT#)

HEX

CMOS@ : USB camera BT@ : BT function ME@ : ME components X76@, H1G@, H512@, S1G@, S512@ : VRAM 45@ : 45 Level HDMI@ : HDMI function

non HDMI@ : HDMI function

AN@ : Apple + Nokia ear phone combo

3 3

SM Bus Controller 1

Device Address HEX

DDR DIMM1 (FCH_SMB0)

DDR DIMM2 (FCH_SMB0)

WLAN (FCH_SMB0 )

1001-000xb

1001-001xb

(FCH_SMB0)

90

92

A@ : Apple ear phone PCB@ : PCB PN 14@ : 14" 15@ : 15" BBH@ : BBH nonBBH@@ : nonBBH@

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/06/30 2012/06/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Notes List

LA8681P

3 48Tuesday, November 29, 2011

E

1.0

5

Power-Up/Down Sequence

1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred.

2. VDDR3 should ramp-up before or simultaneously with VDDC.

3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before

D D

DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10.

4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and VDD_CT have ramped up.

5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to ramp-up (or vice versa).)

4

3

2

1

Without BACO option :

PXS_RST# : Low -> Reset dGPU ; High ->Normal operation PXS_PWREN : Low -> dGPU Power OFF ; High -> dGPU Power ON

BACO option :

PXS_RST# : High ->Normal operation (dGPU is not reset on BACO mode) PXS_PWREN : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)

dGPU Power Pins Max current

PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT, DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD, DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI, DPLL_PVDD, MPV18, and SPV18

DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and

Voltage

1.8V

1.0V

PX 3.0

OFF

BACO Mode

ON

1679mA

575mA

SPV10

VDDR3(3.3VGS)

Note: Do not drive any IOs before VDDR3 is ramped up.

PCIE_VDDC

VDDR3 , and A2VDD

BIF_VDDC (current consumption = 55mA@1.0V, in

PCIE_VDDC(1.0V)

BACO mode) BIF_VDDC=VGA_CORE When GPU enable

C C

VDDR1(1.5VGS)

BIF_VDDC=1.0V When BACO

VDDR1

VDDC/VDDCI

1.0V

3.3V

Same as VDDC

1.5V

1.12V

OFF

ON

ON Same as PCIE_VDDC

OFF

2A

190mA

70mA

2.8A

12.9A

VDDC/VDDCI(1.12V)

VDD_CT(1.8V)

iGPU

PERSTb

REFCLK

B B

Straps Reset

Straps Valid

PXS_RST# PE_EN

dGPU

BIF_VDDC

PXS_PWREN

+3.3VALW

+1.0V

MOS

Regulator

+3.3VGS

1

+1.0VGS

2

PX_mode

+1.5V

BACO Switch

SI4800

+1.5VGS

3

Global ASIC Reset

+B

+1.8V

T4+16clock

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

2010/06/30 2012/07/14

3

Compal Secret Data

Deciphered Date

SI4800

2

+1.8VGS

5

Compal Electronics, Inc.

Title

Size Document Numbe r Rev

B

Date: Sheet of

Compal Electronics, Inc.

Regulator

dGPU Block Diagram

LA8681P

4

1

+VGA_CORE

PWRGOOD

4 48Tuesday, November 29, 2011

1.0

AAAU6

PCB@AAAU6

PCB@ BBBU22

PCB 0R3 LA-8681P REV0 M/B

+1.8VS

D D

+3VS

5

AAAU22

EM1200GBB22GV

R404 1K_0402_5%R404 1K _0402_5%

1 2

R399 1K_0402_5%R399 1K _0402_5%

1 2

R400 1K_0402_5%R400 1K _0402_5%

1 2

R405 300_0402_5%

R401 300_0402_5%R401 300_0402_5%

R402 510_0402_1%R402 510_0402_1%

R403 1K_0402_5%R403 1K _0402_5%

R510 4.7K_0402_5%R510 4.7K_0402_5%

R511 4.7K_0402_5%R511 4.7K_0402_5%

R410 1K_0402_5%R410 1K _0402_5%

R411 1K_0402_5%R411 1K _0402_5%

1 2

12

E1200@AAAU22

E1200@

APU_DBREQ#

APU_SVC

APU_SVD

APU_RST#

APU_PWRGD

TEST_25_L

TEST36

EDID_CLK

EDID_DATA

APU_PROCHOT#

APU_ALERT#_R

E1800@BBBU22

E1800@

EM1800GBB22GV

TO EC

C C

B B

APU_THERMTRIP#

If FCH internal pull-up disable d, level-shifte r coul Need BIOS to dis able internal p ull-up!!

A A

R425

1K_0402_5%

1 2

E

3 1

MMBT3904_NL_SOT23-3

1 2

R427 0_0402_5%@R427 0_0402_5%@

+3VS

B

12

2

R424

R424 10K_0402_5%

10K_0402_5%

Q79

C

APU_PWRGD<10,44>

C1022

@C1022

@

100P_0402_50V8J

d be deleted.

1

2

H_THERMTRIP# <12>

4

C508 0.1U_0402_16V7KHDMI@C508 0.1U_0402_16V7KHDMI@

HDMI_TX2P<23>

HDMI_TX2N<23>

HDMI_TX1P<23>

HDMI_TX1N<23>

HDMI_TX0P<23>

HDMI_TX0N<23>

HDMI_CLKP<23>

HDMI_CLKN<23>

EC_SMB_CK2<16,29,30> EC_SMB_DA2<16,29,30>

H_PROCHOT#<10,30,37>

APU_VDDNB_RUN_FB _H<44> APU_VDD0_RUN_FB_H<44>

APU_VDD0_RUN_FB_L<44>

1 2

C509 0.1U_0402_16V7K

1 2

HDMI@

C510 0.1U_0402_16V7KHDMI@C510 0.1U_0402_16V7KHDMI@

1 2

C511 0.1U_0402_16V7K

1 2

HDMI@

C512 0.1U_0402_16V7KHDMI@C512 0.1U_0402_16V7KHDMI@

1 2

C513 0.1U_0402_16V7K

1 2

HDMI@

C514 0.1U_0402_16V7KHDMI@C514 0.1U_0402_16V7KHDMI@

1 2

C515 0.1U_0402_16V7K

1 2

HDMI@

LVDS_A2<22> LVDS_A2#<22>

LVDS_A1<22> LVDS_A1#<22>

LVDS_A0<22> LVDS_A0#<22>

LVDS_ACLK<22> LVDS_ACLK#<22>

APU_CLK<10> APU_CLK#<10>

APU_DISP_CLK<10> APU_DISP_CLK#<10>

APU_SVC<44>

APU_SVD<44>

R809 0_0402_5%R809 0_0402_5%

1 2

R810 0_0402_5%R810 0_0402_5%

1 2

APU_RST#<10>

R808 0_0402_5%R808 0_0402_5%

1 2

T77PADT77PAD

HDMI_TX2P_C HDMI_TX2N_C

HDMI_TX1P_C HDMI_TX1N_C

HDMI_TX0P_C HDMI_TX0N_C

HDMI_CLKP_C HDMI_CLKN_C

EC_SMB_CK2_R EC_SMB_DA2_R

APU_PROCHOT# APU_THERMTRIP# APU_ALERT#_R

APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ#

3

U22B

A8

TDP1_TXP0

B8

TDP1_TXN0

B9

TDP1_TXP1

A9

TDP1_TXN1

D10

TDP1_TXP2

C10

TDP1_TXN2

A10

TDP1_TXP3

B10

TDP1_TXN3

B5

LTDP0_TXP0

A5

LTDP0_TXN0

D6

LTDP0_TXP1

C6

LTDP0_TXN1

A6

LTDP0_TXP2

B6

LTDP0_TXN2

D8

LTDP0_TXP3

C8

LTDP0_TXN3

V2

CLKIN_H

V1

CLKIN_L

D2

DISP_CLKIN_H

D1

DISP_CLKIN_L

J1

SVC

J2

SVD

P3

SIC

P4

SID

T3

RESET_L

T4

PWROK

U1

PROCHOT_L

U2

THERMTRIP_L

T2

ALERT_L

N2

TDI

N1

TDO

P1

TCK

P2

TMS

M4

TRST_L

M3

DBRDY

M1

DBREQ_L

F4

VDDCR_NB_SENSE

G1

VDDCR_CPU_SENSE

F3

VDDIO_MEM_S_SENSE

F1

VSS_SENSE

B4

RSVD_1

W11

RSVD_2

V5

RSVD_3

S IC E SERIES EME450GBB22GVA 1.65G BGA

DISPLAYPORT 1

DISPLAYPORT 0

CLK

SER

JTAG CTRL

DP MISC

VGA DAC

TEST

DP_ZVSS

DP_BLON

DP_DIGON

DP_VARY_BL

TDP1_AUXP

TDP1_AUXN

TDP1_HPD

LTDP0_AUXP LTDP0_AUXN

LTDP0_HPD

DAC_RED

DAC_REDB

DAC_GREEN

DAC_GREENB

DAC_BLUE

DAC_BLUEB

DAC_HSYNC DAC_VSYNC

DAC_SCL DAC_SDA

DAC_ZVSS

TEST4 TEST5

TEST6 TEST14 TEST15 TEST16 TEST17 TEST18 TEST19

TEST25_H

TEST25_L

TEST28_H

TEST28_L

TEST31

TEST33_H

TEST33_L

TEST34_H

TEST34_L

TEST35 TEST36 TEST37

TEST38

DMAACTIVE_L

2

H3

G2 H2 H1

B2 C2

C1

A3 B3

D3

C12 D13 A12 B12 A13 B13

E1 E2

F2 D4

D12

R1 R2 R6 T5 E4 K4 L1 L2 M2 K1 K2 L5 M5 M21 J18 J19 U15 T15 H4 N5 R5

K3 T1

DP_ZVSS

LTDP0_HPD

DAC_ZVSS

TEST15

TEST18 TEST19 TEST25_H TEST_25_L TEST28_H TEST28_L TEST31 TEST33_H TEST33_L

TEST35 TEST36 TEST37

R398 150_0402_1%R398 150_0402_1%

1 2

EDID_CLK EDID_DATA

R406 100K_0402_5%R406 100K_0402_5%

1 2

R407 150_0402_1%R407 150_0402_1%

1 2

R408 150_0402_1%R408 150_0402_1%

1 2

R409 150_0402_1%R409 150_0402_1%

1 2

R413 499_0402_1%R413 499_0402_1%

1 2

T66

PAD

T67

PAD

T68

PAD

R415 1K_0402_5%@R415 1K_0402_5%@

T69

PAD

T95

PAD

R416 1K_0402_5%R416 1K _0402_5% R417 1K_0402_5%R417 1K _0402_5% R419 510_0402_1%R419 510_0402_1%

T71

PAD

T72

PAD

T73

PAD

C516 0.1U_0402_16V4ZC516 0.1U_0402_16V4Z

Delete Test point for layout limitation 20100818

C517 0.1U_0402_16V4ZC517 0.1U_0402_16V4Z

T76

PAD

HDMI function en able R958 mount di sable R422 moun t

R423 1K_0402_5%R423 1K _0402_5%

1 2

APU_ENBKL <22> APU_ENVDD <22> APU_BLPWM <22>

HDMI_CLK <23>

HDMI_DATA <23>

HDMI_DET <23>

EDID_CLK <22> EDID_DATA <22>

DAC_RED <24>

DAC_GRN <24>

DAC_BLU <24>

CRT_HSYNC <24> CRT_VSYNC <24>

CRT_DDC_CLK <24> CRT_DDC_DATA <24>

AMD check list update 20101110

1 2

1 2 1 2 1 2

1 2 1 2

non HDMI@

R422 1K_0402_5%

1 2

R958 1K_0402_5%HDMI@R958 1K_0402_5%HDMI@

1 2

ALLOW_STOP# <10>

+1.8VS

R420 51_0402_1%R420 51_0402_1%

1 2

R421 51_0402_1%R421 51_0402_1%

1 2

+1.8VS

1

AMD Debug

check the connect need or not

JHDT1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

SAMTE_ASP-136446-07-B

@

APU_TCK

2

APU_TMS

4

APU_TDI

6

APU_TDO

8

APU_PWRGD

10

APU_RST#

12

APU_DBRDY

14

APU_DBREQ#

16

J108_PLLTST0

18

J108_PLLTST1

20

Please be noted about TEST_18 and TEST_19

R843 1K_0402_5%R843 1K _0402_5%

R844 1K_0402_5%R844 1K _0402_5%

R845 1K_0402_5%R845 1K _0402_5%

R851 0_0402_5%@R851 0_0402_5%@

R852 0_0402_5%@R852 0_0402_5%@

12

1 2

need to pop for HDT debug 20101012

TEST19

TEST18

+1.8VS

R842

1 2

1K_0402_5%

APU_TRST#

need to pop for HDT debug 20101012

@

R846 0_0402_5%

1 2

R847 10K_0402_5%@R847 10K_0402_5%@

R848 10K_0402_5%@R848 10K_0402_5%@

R849 10K_0402_5%@R849 10K_0402_5%@

12

+1.8VS +1.8VS

APU_TRST#_R

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/06/30 2012/06/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

FT1 CTRL/DP/CRT

LA8681P

5 48Wednesday, November 30, 2011

1

1.0

A

U22E

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6

4 4

3 3

2 2

DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_A_BS0<8,9> DDR_A_BS1<8,9> DDR_A_BS2<8,9>

DDR_A_DQS0<8,9>

DDR_A_DQS#0<8,9>

DDR_A_DQS1<8,9>

DDR_A_DQS#1<8,9>

DDR_A_DQS2<8,9>

DDR_A_DQS#2<8,9>

DDR_A_DQS3<8,9>

DDR_A_DQS#3<8,9>

DDR_A_DQS4<8,9>

DDR_A_DQS#4<8,9>

DDR_A_DQS5<8,9>

DDR_A_DQS#5<8,9>

DDR_A_DQS6<8,9>

DDR_A_DQS#6<8,9>

DDR_A_DQS7<8,9>

DDR_A_DQS#7<8,9>

DDR_A_CLK0<8> DDR_A_CLK#0<8> DDR_A_CLK1<8> DDR_A_CLK#1<8> DDR_B_CLK2<9> DDR_B_CLK#2<9> DDR_B_CLK3<9> DDR_B_CLK#3<9>

DDR_RST#<8,9>

DDR_EVENT#<8,9>

DDR_CKE0<8,9> DDR_CKE1<8,9>

DDR_A_ODT0<8> DDR_A_ODT1<8> DDR_B_ODT0<9> DDR_B_ODT1<9>

DDR_CS0_DIMMA#<8> DDR_CS1_DIMMA#<8> DDR_CS0_DIMMB#<9> DDR_CS1_DIMMB#<9>

DDR_A_RAS#< 8,9> DDR_A_CAS#< 8,9> DDR_A_WE#<8,9>

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1

DDR_A_DQS#1

DDR_A_DQS2

DDR_A_DQS#2

DDR_A_DQS3

DDR_A_DQS#3

DDR_A_DQS4

DDR_A_DQS#4

DDR_A_DQS5

DDR_A_DQS#5

DDR_A_DQS6

DDR_A_DQS#6

DDR_A_DQS7

DDR_A_DQS#7

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1 DDR_B_CLK2 DDR_B_CLK#2 DDR_B_CLK3 DDR_B_CLK#3

DDR_RST# DDR_EVENT#

DDR_CKE0 DDR_CKE1

DDR_A_ODT0 DDR_A_ODT1 DDR_B_ODT0 DDR_B_ODT1

DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMB# DDR_CS1_DIMMB#

DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

U22E

R17

M_ADD0

H19

M_ADD1

J17

M_ADD2

H18

M_ADD3

H17

M_ADD4

G17

M_ADD5

H15

M_ADD6

G18

M_ADD7

F19

M_ADD8

E19

M_ADD9

T19

M_ADD10

F17

M_ADD11

E18

M_ADD12

W17

M_ADD13

E16

M_ADD14

G15

M_ADD15

R18

M_BANK0

T18

M_BANK1

F16

M_BANK2

D15

M_DM0

B19

M_DM1

D21

M_DM2

H22

M_DM3

P23

M_DM4

V23

M_DM5

AB20

M_DM6

AA16

M_DM7

A16

M_DQS_H0

B16

M_DQS_L0

B20

M_DQS_H1

A20

M_DQS_L1

E23

M_DQS_H2

E22

M_DQS_L2

J22

M_DQS_H3

J23

M_DQS_L3

R22

M_DQS_H4

P22

M_DQS_L4

W22

M_DQS_H5

V22

M_DQS_L5

AC20

M_DQS_H6

AC21

M_DQS_L6

AB16

M_DQS_H7

AC16

M_DQS_L7

M17

M_CLK_H0

M16

M_CLK_L0

M19

M_CLK_H1

M18

M_CLK_L1

N18

M_CLK_H2

N19

M_CLK_L2

L18

M_CLK_H3

L17

M_CLK_L3

L23

M_RESET_L

N17

M_EVENT_L

F15

M_CKE0

E15

M_CKE1

W19

M0_ODT0

V15

M0_ODT1

U19

M1_ODT0

W15

M1_ODT1

T17

M0_CS_L0

W16

M0_CS_L1

U17

M1_CS_L0

V16

M1_CS_L1

U18

M_RAS_L

V19

M_CAS_L

V17

M_WE_L

S IC E SERIES EME450GBB22GVA 1.65G BGA

DDR SYSTEM MEMORY

B

M_DATA0 M_DATA1 M_DATA2 M_DATA3 M_DATA4 M_DATA5 M_DATA6 M_DATA7

M_DATA8

M_DATA9 M_DATA10 M_DATA11 M_DATA12 M_DATA13 M_DATA14 M_DATA15

M_DATA16 M_DATA17 M_DATA18 M_DATA19 M_DATA20 M_DATA21 M_DATA22 M_DATA23

M_DATA24 M_DATA25 M_DATA26 M_DATA27 M_DATA28 M_DATA29 M_DATA30 M_DATA31

M_DATA32 M_DATA33 M_DATA34 M_DATA35 M_DATA36 M_DATA37 M_DATA38 M_DATA39

M_DATA40 M_DATA41 M_DATA42 M_DATA43 M_DATA44 M_DATA45 M_DATA46 M_DATA47

M_DATA48 M_DATA49 M_DATA50 M_DATA51 M_DATA52 M_DATA53 M_DATA54 M_DATA55

M_DATA56 M_DATA57 M_DATA58 M_DATA59 M_DATA60 M_DATA61 M_DATA62 M_DATA63

M_VREF

M_ZVDDIO_MEM_S

B14 A15 A17 D18 A14 C14 C16 D16

C18 A19 B21 D20 A18 B18 A21 C20

C23 D23 F23 F22 C22 D22 F20 F21

H21 H23 K22 K21 G23 H20 K20 K23

N23 P21 T20 T23 M20 P20 R23 T22

V20 V21 Y23 Y22 T21 U23 W23 Y21

Y20 AB22 AC19 AA18 AA23 AA20 AB19 Y18

AC17 Y16 AB14 AC14 AC18 AB18 AB15 AC15

M23

M_ZVDDIO_MEM_S

M22

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7

DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15

DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23

DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31

DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39

DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47

DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55

DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

+MEM_VREF

R437

39.2_0402_1%

C

DDR_A_D[0..63]

DDR_A_MA[0..15]

DDR_A_DM[0..7]

PCIE_CRX_GTX_P0<15> PCIE_CRX_GTX_N0<15>

PCIE_CRX_GTX_P1<15> PCIE_CRX_GTX_N1<15>

PCIE_CRX_GTX_P2<15> PCIE_CRX_GTX_N2<15>

PCIE_CRX_GTX_P3<15> PCIE_CRX_GTX_N3<15>

+1.05VS

UMI_RX0P<10> UMI_RX0N<1 0>

UMI_RX1P<10> UMI_RX1N<1 0>

UMI_RX2P<10> UMI_RX2N<1 0>

UMI_RX3P<10> UMI_RX3N<1 0>

12

R435 2K_0402_1%R435 2K_0402_1%

Less than 1"

+1.5V_APU

1 2

DDR_A_D[0..63] <8,9>

DDR_A_MA[0..15] <8,9>

DDR_A_DM[0..7] <8,9>

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1

PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3

P_ZVDD_10

U22A

AA6

P_GPP_RXP0

Y6

P_GPP_RXN0

AB4

P_GPP_RXP1

AC4

P_GPP_RXN1

AA1

P_GPP_RXP2

AA2

P_GPP_RXN2

Y4

P_GPP_RXP3

Y3

P_GPP_RXN3

Y14

P_ZVDD_10

AA12

P_UMI_RXP0

Y12

P_UMI_RXN0

AA10

P_UMI_RXP1

Y10

P_UMI_RXN1

AB10

P_UMI_RXP2

AC10

P_UMI_RXN2

AC7

P_UMI_RXP3

AB7

P_UMI_RXN3

S IC E SERIES EME450GBB22GVA 1.65G BGA

PCIE I/F

UMI I/F

P_GPP_TXP0 P_GPP_TXN0

P_GPP_TXP1 P_GPP_TXN1

P_GPP_TXP2 P_GPP_TXN2

P_GPP_TXP3 P_GPP_TXN3

P_ZVSS

P_UMI_TXP0 P_UMI_TXN0

P_UMI_TXP1 P_UMI_TXN1

P_UMI_TXP2 P_UMI_TXN2

P_UMI_TXP3 P_UMI_TXN3

D

PCIE_CTX_C_GRX_P0

AB6

PCIE_CTX_C_GRX_N0

AC6

PCIE_CTX_C_GRX_P1

AB3

PCIE_CTX_C_GRX_N1

AC3

PCIE_CTX_C_GRX_P2

Y1

PCIE_CTX_C_GRX_N2

Y2

PCIE_CTX_C_GRX_P3

V3

PCIE_CTX_C_GRX_N3

V4

P_ZVSS

AA14

UMI_TX0P_C

AB12

UMI_TX0N_C

AC12

UMI_TX1P_C

AC11

UMI_TX1N_C

AB11

UMI_TX2P_C

AA8

UMI_TX2N_C

Y8

UMI_TX3P_C

AB8

UMI_TX3N_C

AC8

C518 0.1U_0402_16V7KC518 0.1U_0402_16V7K

1 2

C519 0.1U_0402_16V7KC519 0.1U_0402_16V7K

1 2

C520 0.1U_0402_16V7KC520 0.1U_0402_16V7K

1 2

C521 0.1U_0402_16V7KC521 0.1U_0402_16V7K

1 2

C522 0.1U_0402_16V7KC522 0.1U_0402_16V7K

1 2

C523 0.1U_0402_16V7KC523 0.1U_0402_16V7K

1 2

C524 0.1U_0402_16V7KC524 0.1U_0402_16V7K

1 2

C525 0.1U_0402_16V7KC525 0.1U_0402_16V7K

1 2

R436 1.27K_0402_1%R436 1.27K_0402_1%

1 2

Less than 1"

C526 0.1U_0 402_16V7KC526 0.1U_0402_16V7K

1 2

C527 0.1U_0 402_16V7KC527 0.1U_0402_16V7K

1 2

C528 0.1U_0 402_16V7KC528 0.1U_0402_16V7K

1 2

C529 0.1U_0402_16V7KC52 9 0.1U_0402_16V7K

1 2

C530 0.1U_0 402_16V7KC530 0.1U_0402_16V7K

1 2

C531 0.1U_0 402_16V7KC531 0.1U_0402_16V7K

1 2

C532 0.1U_0 402_16V7KC532 0.1U_0402_16V7K

1 2

C533 0.1U_0 402_16V7KC533 0.1U_0402_16V7K

1 2

E

PCIE_CTX_GRX_P0 <15> PCIE_CTX_GRX_N0 <15>

PCIE_CTX_GRX_P1 <15> PCIE_CTX_GRX_N1 <15>

PCIE_CTX_GRX_P2 <15> PCIE_CTX_GRX_N2 <15>

PCIE_CTX_GRX_P3 <15> PCIE_CTX_GRX_N3 <15>

UMI_TX0P <10> UMI_TX0N <10>

UMI_TX1P <10> UMI_TX1N <10>

UMI_TX2P <10> UMI_TX2N <10>

UMI_TX3P <10> UMI_TX3N <10>

+1.5V_APU

R444

1 2

1K_0402_5%

1 1

DDR_EVENT#

A

R438

1K_0402_1%

R439

1K_0402_1%

1 2

1

C534

1000P_0402_50V7K

2

1 2

Place within 1000 mils to APU 20100526

B

C535

+MEM_VREF

1

0.1U_0402_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/06/30 2012/0630

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

FT1 DDRIII/UMI/PCIE

LA8681P

E

6 48Wednesday, November 30, 2011

1.0

5

4

3

2

1

U22C

+APU_CORE

D D

1

C550

2

1

C559

2

+APU_CORE_NB

C C

C582

C591

B B

1

C551

2

1U_0402_6.3V6K

1

C560

2

0.1U_0402_16V7K

1

C583

2

1U_0402_6.3V6K

1

C592

2

0.1U_0402_16V7K

1

C553

C552

1U_0402_6.3V6K

C561

0.1U_0402_16V7K

C584

1U_0402_6.3V6K

C593

0.1U_0402_16V7K

C553

2

1U_0402_6.3V6K

1

C562

2

0.1U_0402_16V7K

1

C585

2

1U_0402_6.3V6K

1

C594

2

0.1U_0402_16V7K

1

C554

2

1U_0402_6.3V6K

1

C563

2

0.1U_0402_16V7K

1

C586

2

1U_0402_6.3V6K

1

2

0.1U_0402_16V7K

1

C555

2

180P_0402_50V8J

0.1U_0402_16V7K

1U_0402_6.3V6K

180P_0402_50V8J

1

C588

C587

2

180P_0402_50V8J

+APU_CORE_NB

+1.5V_APU

180P_0402_50V8J

+1.5V_APU

11A

E5

VDDCR_CPU_1

E6

VDDCR_CPU_2

F5

VDDCR_CPU_3

F7

VDDCR_CPU_4

G6

VDDCR_CPU_5

G8

VDDCR_CPU_6

H5

VDDCR_CPU_7

H7

VDDCR_CPU_8

J6

VDDCR_CPU_9

J8

VDDCR_CPU_10

L7

VDDCR_CPU_11

M6

VDDCR_CPU_12

M8

VDDCR_CPU_13

N7

VDDCR_CPU_14

R8

VDDCR_CPU_15

10A

E8

VDDCR_NB_1

E11

VDDCR_NB_2

E13

VDDCR_NB_3

F9

VDDCR_NB_4

F12

VDDCR_NB_5

G11

VDDCR_NB_6

G13

VDDCR_NB_7

H9

VDDCR_NB_8

H12

VDDCR_NB_9

K11

VDDCR_NB_10

K13

VDDCR_NB_11

L10

VDDCR_NB_12

L12

VDDCR_NB_13

L14

VDDCR_NB_14

M11

VDDCR_NB_15

M12

VDDCR_NB_16

M13

VDDCR_NB_17

N10

VDDCR_NB_18

N12

VDDCR_NB_19

N14

VDDCR_NB_20

P11

VDDCR_NB_21

P13

VDDCR_NB_22

2A

G16

VDDIO_MEM_S_1

G19

VDDIO_MEM_S_2

E17

VDDIO_MEM_S_3

J16

VDDIO_MEM_S_4

L16

VDDIO_MEM_S_5

L19

VDDIO_MEM_S_6

N16

VDDIO_MEM_S_7

R16

VDDIO_MEM_S_8

R19

VDDIO_MEM_S_9

W18

VDDIO_MEM_S_10

U16

VDDIO_MEM_S_11

S IC E SERIES EME450GBB22GVA 1.65G BGA

1

C589

2

1

C595

2

1

C590

2

10U_0603_6.3V6M

1U_0402_6.3V6K

10U_0603_6.3V6M

1

C596

2

1

C597

2

1U_0402_6.3V6K

TSense/PLL/DP/PCIE/IO

VDD_18_1 VDD_18_2 VDD_18_3 VDD_18_4 VDD_18_5 VDD_18_6

CPU CORE

VDD_18_7

DAC

VDD_18_DAC

GPU AND NB CORE

POWER

DIS PLL

VDDPL_10

PCIE/IO/DDR3 Phy

VDD_10_1 VDD_10_2 VDD_10_3 VDD_10_4

DDR3

DP Phy/IO

1

C598

2

1U_0402_6.3V6K

VDD_33

2A

+VDD_18

U8 W8 U6 U9 W6 T7 V7

0.15A

+VDD_18_DAC

W9

0.2A

+VDDL_10

U11

place C564 close APU ball

5.5A

+VDD_10

U13 W13 V12 T12

0.5A

A4

1

C537

C545

2

180P_0402_50V8J

1

C557

C556

2

180P_0402_50V8J

1

C565

C564

2

180P_0402_50V8J

1

C569

C1102

2

180P_0402_50V8J

1

C580

C581

2

0.1U_0402_16V7K

1

C546

C538

2

1U_0402_6.3V6K

0.1U_0402_16V7K

Change from SM010014520 to SD002000080 20100816

1

C558

2

10U_0603_6.3V6M

1U_0402_6.3V6K

1

C566

C567

2

1U_0402_6.3V6K

0.1U_0402_16V7K

1

C571

C570

2

0.1U_0402_16V7K

+3VS

1U_0402_6.3V6K

1

C547

2

1U_0402_6.3V6K

L30

FBMA-L11-201209-221LMA30T_0805

10U_0603_6.3V6M

1

C572

2

1U_0402_6.3V6K

1

C548

C549

2

1U_0402_6.3V6K

+1.0VS has been raised to +1.05VS for AMD design guide 45339_R1.02 update 20101004

1U_0402_6.3V6K

10U_0603_6.3V6M

+1.8VS

12

FBMA-L11-201209-221LMA30T_0805

1

C574

C573

2

10U_0603_6.3V6M

+1.8VS

L29

12

FBMA-L11-201209-221LMA30T_0805

Change from SM010014520 to SD002000080 20100816

+1.05VS

L31

12

L32

12

FBMA-L11-201209-221LMA30T_0805

Change from SM010014520 to SD002000080 20100816

U22D

A7

VSS_1

B7

VSS_2

B11

VSS_3

B17

VSS_4

B22

VSS_5

C4

VSS_6

D5

VSS_7

D7

VSS_8

D9

VSS_9

D11

VSS_10

D14

VSS_11

B15

VSS_12

D17

VSS_13

D19

VSS_14

E7

VSS_15

E9

VSS_16

E12

VSS_17

E20

VSS_18

F8

VSS_19

F11

VSS_20

F13

VSS_21

G4

VSS_22

G5

VSS_23

G7

VSS_24

G9

VSS_25

G12

VSS_26

G20

VSS_27

G22

VSS_28

H6

VSS_29

H11

VSS_30

H13

VSS_31

J4

VSS_32

J5

VSS_33

J7

VSS_34

J20

VSS_35

K10

VSS_36

K14

VSS_37

L4

VSS_38

L6

VSS_39

L8

VSS_40

L11

VSS_41

L13

VSS_42

L20

VSS_43

L22

VSS_44

M7

VSS_45

N4

VSS_46

N6

VSS_47

N8

VSS_48

N11

VSS_49

S IC E SERIES EME450GBB22GVA 1.65G BGA

GND

VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97

VSSBG_DAC

N13 N20 N22 P10 P14 R4 R7 R20 T6 T9 T11 T13 U4 U5 U7 U12 U20 U22 V8 V9 V11 V13 W1 W2 W4 W5 W7 W12 W20 Y5 Y7 Y9 Y11 Y13 Y15 Y17 Y19 AA4 AA22 AB2 AB5 AB9 AB13 AB17 AB21 AC5 AC9 AC13 A11

1

C599

2

1

C600

2

0.1U_0402_16V7K

1

C602

C601

0.1U_0402_16V7K

C602

2

0.1U_0402_16V7K

1

C603

2

180P_0402_50V8J

+1.5V_APU +1.5V

J15

@ J 15

@

2

112

JUMP_43X79

By case (Along split)

+1.5V_APU

A A

@

C622

Near CPU Socket

5

POWER

1

C608

1

2

4

1

+

C623

@

2

330U_2.5V_M

22U_0805_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2010/06/30 2012/06/30

Compal Secret Data

Deciphered Date

2

C608

2

0.1U_0402_16V7K

1

C610

C609

2

0.1U_0402_16V7K

Title

Size Document Number Rev

C

Date: Sheet of

1

C611

2

1

C612

C613

2

180P_0402_50V8J

Compal Electronics, Inc.

P07-FT1 PWR/VSS

LA8681P

1

C615

C614

2

180P_0402_50V8J

1.0

7 48Tuesday, November 29, 2011

1.0

5

+1.5V

JDIMM1

ME@JDIMM1

+VREF_DQ

1

C626

2

D D

DDR_A_DQS#1<6,9> DDR_A_DQS1<6,9>

DDR_A_DQS#2<6,9> DDR_A_DQS2<6,9>

C C

DDR_CS1_DIMMA#<6>

B B

A A

+3VS

DDR_A_DQS#4<6,9> DDR_A_DQS4<6,9>

DDR_A_DQS#6<6,9> DDR_A_DQS6<6,9>

C646

1

C627

2

0.1U_0402_16V4Z

DDR_CKE0<6,9>

DDR_A_BS2<6,9>

DDR_A_CLK0<6> DDR_A_CLK#0<6>

DDR_A_BS0<6,9>

DDR_A_WE#<6,9>

DDR_A_CAS#<6,9>

1

C647

2

2.2U_0603_6.3V4Z

5

1000P_0402_50V7K

0.1U_0402_16V4Z

DDR_A_D0 DDR_A_D1

DDR_A_DM0

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

DDR_A_MA10

DDR_A_MA13

DDR_A_D32 DDR_A_D33

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_DM7

DDR_A_D58 DDR_A_D59

R445 10K_0402_5%R445 10K_0402_5%

1 2

12

R446

10K_0402_5%

1 3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

73 75 77 79 81 83 85 87 89 91 93 95 97 99

101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205 207

ME@

VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS

CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST

VREF_CA VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT

GND1 BOSS1

LCN_DAN06-K4406-0103

VSS DQ4 DQ5 VSS

DQS0#

DQS0

VSS DQ6 DQ7

VSS DQ12 DQ13

VSS

DM1

RESET#

VSS DQ14 DQ15

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS

DQS3#

DQS3

VSS DQ30 DQ31

VSS

CKE1

VDD

CK1

CK1#

VDD

BA1 RAS#

VDD

ODT0

VDD ODT1

VDD

VSS DQ36 DQ37

VSS

DM4

VSS DQ38 DQ39

VSS DQ44 DQ45

VSS

DQS5#

DQS5

VSS DQ46 DQ47

VSS DQ52 DQ53

VSS

DM6

VSS DQ54 DQ55

VSS DQ60 DQ61

VSS

DQS7#

DQS7

VSS DQ62 DQ63

VSS

EVENT#

SDA

SCL

VTT

GND2

BOSS2

4

+1.5V

2

DDR_A_D4

4

DDR_A_D5

6 8 10 12 14

DDR_A_D6

16

DDR_A_D7

18 20

DDR_A_D12

22

DDR_A_D13

24 26

DDR_A_DM1

28 30 32

DDR_A_D14

34

DDR_A_D15

36 38

DDR_A_D20

40

DDR_A_D21

42 44

DDR_A_DM2

46 48

DDR_A_D22

50

DDR_A_D23

52 54

DDR_A_D28

56

DDR_A_D29

58 60 62 64 66

DDR_A_D30

68

DDR_A_D31

70 72

74 76

DDR_A_MA15

78

A15 A14

A11

A7

A6 A4

A2 A0

S0#

NC

DDR_A_MA14

80 82

DDR_A_MA11

84

DDR_A_MA7

86 88

DDR_A_MA6

90

DDR_A_MA4

92 94

DDR_A_MA2

96

DDR_A_MA0

98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206 208

DDR_A_D36 DDR_A_D37

DDR_A_DM4

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_DM6

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_D62 DDR_A_D63

4

DDR_A_DQS#0 <6,9> DDR_A_DQS0 <6,9>

DDR_RST# <6,9>

DDR_A_DQS#3 <6,9> DDR_A_DQS3 <6,9>

DDR_CKE1 <6,9>

DDR_A_CLK1 <6> DDR_A_CLK#1 <6>

DDR_A_BS1 <6,9> DDR_A_RAS# <6,9>

DDR_CS0_DIMMA# <6> DDR_A_ODT0 <6>

DDR_A_ODT1 <6>

C645

DDR_A_DQS#5 <6,9> DDR_A_DQS5 <6,9>

DDR_A_DQS#7 <6,9> DDR_A_DQS7 <6,9>

DDR_EVENT# <6,9>

FCH_SMDAT0 <9,12,29>

+0.75VS

DDR3 SO-DIMM A Reverse Type

FCH_SMCLK0 <9,12,29>

1

2

1

C644

2

1000P_0402_50V7K

0.1U_0402_16V4Z

3

DDR_A_D[0..63]

DDR_A_MA[0..15]

DDR_A_DM[0..7]

+1.5V

2

C628

1

0.1U_0402_16V4Z

+VREF_CA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/06/30 2012/06/30

0.1U_0402_16V4Z

2

C629

1

DDR_A_D[0..63] <6,9>

DDR_A_MA[0..15] <6,9>

DDR_A_DM[0..7] <6,9>

0.1U_0402_16V4Z

2

C630

1

0.1U_0402_16V4Z

Compal Secret Data

Deciphered Date

2

C631

1

2

C632

1

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

+1.5V

+VREF_DQ

2

C633

1

CRB 0.1u X1 4.7u X1

+0.75VS

1

C642

Place near JDIMM1

2

C641

2

1

0.1U_0402_16V4Z

4.7U_0603_6.3V6K

Title

Size Document Number Rev

Custom

Date: Sheet of

1

R440

R440 1K_0402_1%

1K_0402_1%

1 2

R442

R442 1K_0402_1%

1K_0402_1%

1 2

+VREF_CA

Combine to one?

CRB 100U X2

+1.5V

1

+

C643

2

SF000002Y00

Compal Electronics, Inc.

DDR3 SODIMM-I Socket

LA8681P

1

+1.5V

1 2

220U_6.3V_M

20100729

R441

R441 1K_0402_1%

1K_0402_1%

R443

R443 1K_0402_1%

1K_0402_1%

8 48Wednesday, November 30, 2011

1.0

5

4

3

2

1

DQ4 DQ5

DQ6 DQ7

DM1

DM2

A15 A14

A11

CK1

BA1

S0#

NC2

DM4

DM6

SDA SCL

+1.5V

2

DDR_A_D4

4

DDR_A_D5

6 8 10 12 14

DDR_A_D6

16

DDR_A_D7

18 20

DDR_A_D12

22

DDR_A_D13

24 26

DDR_A_DM1

28 30 32

DDR_A_D14

34

DDR_A_D15

36 38

DDR_A_D20

40

DDR_A_D21

42 44

DDR_A_DM2

46 48

DDR_A_D22

50

DDR_A_D23

52 54

DDR_A_D28

56

DDR_A_D29

58 60 62 64 66

DDR_A_D30

68

DDR_A_D31

70 72

74 76

DDR_A_MA15

78

DDR_A_MA14

80 82

DDR_A_MA11

84

DDR_A_MA7

86

A7

88

DDR_A_MA6

90

A6 A4

A2 A0

G2

DDR_A_MA4

92 94

DDR_A_MA2

96

DDR_A_MA0

98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_A_D36 DDR_A_D37

DDR_A_DM4

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_DM6

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_D62 DDR_A_D63

4

DDR_A_DQS#0 <6,8> DDR_A_DQS0 <6,8>

DDR_RST# <6,8>

DDR_A_DQS#3 <6,8> DDR_A_DQS3 <6,8>

DDR_CKE1 <6,8>

DDR_B_CLK3 <6> DDR_B_CLK#3 <6>

DDR_A_BS1 <6,8> DDR_A_RAS# <6,8>

DDR_CS0_DIMMB# <6>

DDR_B_ODT1 <6>

DIMM@

DDR_A_DQS#5 <6,8> DDR_A_DQS5 <6,8>

DDR_A_DQS#7 <6,8> DDR_A_DQS7 <6,8>

DDR_EVENT# <6,8>

FCH_SMDAT0 <8,12,29>

+0.75VS

DDR3 SO-DIMM B Reverse Type

FCH_SMCLK0 <8,12,29>

DDR_A_D[0..63]

DDR_A_MA[0..15]

DDR_A_DM[0..7]

+1.5V

0.1U_0402_16V4Z

2

DIMM@

DIMM@ 1

0.1U_0402_16V4Z

+VREF_CA

1

2

0.1U_0402_16V4Z

1

DIMM@

C666

C665

C666

2

1000P_0402_50V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

C651

C650

DIMM@

DIMM@ 1

0.1U_0402_16V4Z

2010/06/30 2012/06/30

DDR_A_D[0..63] <6,8>

DDR_A_MA[0..15] <6,8>

DDR_A_DM[0..7] <6,8>

0.1U_0402_16V4Z

2

DIMM@

DIMM@ 1

Compal Secret Data

C652

Deciphered Date

DIMM@

DIMM@ 1

C653

0.1U_0402_16V4Z

2

C654

DIMM@

DIMM@ 1

0.1U_0402_16V4Z

2

C655

DIMM@

DIMM@ 1

2

CRB 0.1u X1 4,7uX1

+0.75VS

1

2

C664

C663

2

DIMM@

Place near JDIMM2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

1

DIMM@

0.1U_0402_16V4Z

4.7U_0603_6.3V6K

DDR3 SODIMM-II Socket

LA8681P

9 48Wednesday, November 30, 2011

1

1.0

+1.5V

JDIMM2

E@

M

+VREF_DQ

1

DIMM@

C649

DIMM@ C648

DIMM@

D D

C C

B B

For DRAM strap pin reservation 20100817

+3VS

A A

C648

2

0.1U_0402_16V4Z

DDR_A_DQS#1<6,8> DDR_A_DQS1<6,8>

DDR_A_DQS#2<6,8> DDR_A_DQS2<6,8>

DDR_CKE0<6,8>

DDR_A_BS2<6,8>

DDR_B_CLK2<6> DDR_B_CLK#2<6>

DDR_A_BS0<6,8>

DDR_A_WE#<6,8>

DDR_A_CAS#<6,8> DDR_B_ODT0 <6>

DDR_CS1_DIMMB#<6>

DDR_A_DQS#4<6,8> DDR_A_DQS4<6,8>

DDR_A_DQS#6<6,8> DDR_A_DQS6<6,8>

DIMM@

R961 10K_0402_5%

1 2

1

C667

2.2U_0603_6.3V4Z

DIMM@

2

CRB only one 4.7k

5

1

2

1000P_0402_50V7K

1

C668

2

0.1U_0402_16V4Z

DDR_A_D0 DDR_A_D1

DDR_A_DM0

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

DDR_A_MA10

DDR_A_MA13

DDR_A_D32 DDR_A_D33

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5

DDR_A_D42 DDR_A_D43

DDR_A_D48

DDR_A_D49

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_DM7

DDR_A_D58 DDR_A_D59

DIMM@

R962

10K_0402_5%

1 2

For DRAM strap pin reservation 20100817

11 13 15 17 19 21 23 25 27

33 35

39 41

45 47 49 51 53 55 57 59

63

67 69

73 75 77 79 81 83 85 87 89 91 93 95 97

99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205

M

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS129RESET# VSS1131VSS12 DQ10 DQ11 VSS1337VSS14 DQ16 DQ17 VSS1543VSS16 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS2261DQS#3 DM3 VSS2365VSS24 DQ26 DQ27 VSS2571VSS26

CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST

VREF_CA VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1

G1

LCN_DAN06-K4806-0103

VSS3

DQS#0

DQS0 VSS6

VSS8 DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VSS28

DQ36 DQ37

VSS30

VSS31

DQ38 DQ39

VSS33

DQ44

DQ45 VSS35 DQS#5

DQS5 VSS38

DQ46

DQ47 VSS40

DQ52

DQ53 VSS42

VSS43

DQ54

DQ55 VSS45

DQ60

DQ61 VSS47 DQS#7

DQS7 VSS50

DQ62

DQ63 VSS52

EVENT#

VTT2

A

C146 150P_0402_50V8JC146 150P_0402_50V8J

+VDDAN_11_PCIE

PCIE_FTX_C_DRX_N0<25> PCIE_FTX_C_DRX_P1<29> PCIE_FTX_C_DRX_N1<29>

PCIE_FRX_DTX_P0<25> PCIE_FRX_DTX_N0<25> PCIE_FRX_DTX_P1<29> PCIE_FRX_DTX_N1<29>

+1.1VS_CKVDD

CLK_PCIE_VGA<15> CLK_PCIE_VGA#<15>

CLK_PCIE_WLAN<29> CLK_PCIE_WLAN#<29>

CLK_PCIE_LAN<25> CLK_PCIE_LAN#<25>

1

2

1 2

UMI_RX0P<6> UMI_RX0N<6> UMI_RX1P<6> UMI_RX1N<6> UMI_RX2P<6> UMI_RX2N<6> UMI_RX3P<6> UMI_RX3N<6>

UMI_TX0P<6> UMI_TX0N<6 > UMI_TX1P<6> UMI_TX1N<6 > UMI_TX2P<6> UMI_TX2N<6 > UMI_TX3P<6> UMI_TX3N<6 >

C158

22P_0402_50V8J

20M_0402_5%

C159

22P_0402_50V8J

PLT_RST#

C147 0.1U_0402_16V7KC147 0.1U_0402_16V7K C148 0.1U_0402_16V7KC148 0.1U_0402_16V7K C149 0.1U_0402_16V7KC149 0.1U_0402_16V7K C150 0.1U_0402_16V7KC150 0.1U_0402_16V7K C151 0.1U_0402_16V7KC151 0.1U_0402_16V7K C152 0.1U_0402_16V7KC152 0.1U_0402_16V7K C153 0.1U_0402_16V7KC153 0.1U_0402_16V7K C154 0.1U_0402_16V7KC154 0.1U_0402_16V7K

R94 590_0402_1%R94 590_0402_1% R88 2K_0402_1%R88 2K_0402_1%

C718 0.1U_0402_16V7KC718 0.1U_0402_16V7K C720 0.1U_0402_16V7KC720 0.1U_0402_16V7K C721 0.1U_0402_16V7KC721 0.1U_0402_16V7K C719 0.1U_0402_16V7KC719 0.1U_0402_16V7K

R95 2K_0402_1%R95 2K_0402_1%

R98 0_0402_5%R98 0_0402_5% R99 0_0402_5%R99 0_0402_5%

R102 0_0402_5%R102 0_0402_5% R103 0_0402_5%R103 0_0402_5%

R100 0_0402_5%R100 0_0402_5% R101 0_0402_5%R101 0_0402_5%

1 2

12

R107

1 2

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2

1 2

C146 place close to FCH

1 1

LAN

WLAN

2 2

VGA

WLAN

3 3

25M_X1

25M_X2

4 4

C157

22P_0402_50V8J

LAN

1 2

R106 1M_0402_5%R106 1M_0402_5%

3

2

25MHZ_20PF_FSX3M-25.M20FDO

1

2

OSC

NC

Y4

A

4

NC

1

OSC

22P_0402_50V8J

C155

B

T101T101

APU_DISP_CLK<5>

APU_DISP_CLK#<5>

B

APU_PCIE_RST#_C

PCIE_FTX_DRX_P0 PCIE_FTX_DRX_N0 PCIE_FTX_DRX_P1 PCIE_FTX_DRX_N1

APU_CLK<5>

APU_CLK#<5>

CLK_PCIE_VGA_R CLK_PCIE_VGA#_R

CLK_PCIE_WLAN_R CLK_PCIE_WLAN#_R

CLK_PCIE_LAN_R CLK_PCIE_LAN#_R

22_0402_5%

R559

1 2

32K_X1

32K_X2

R557 33_0402_5%R557 33_0402_5%

1 2

1 2 1 2 1 2 1 2

1 2 1 2

Y1

32.768KHZ_12.5PF_CM31532768DZFT

1 2

A_RST#

UMI_RXP0_C UMI_RXN0_C UMI_RXP1_C UMI_RXN1_C UMI_RXP2_C UMI_RXN2_C UMI_RXP3_C UMI_RXN3_C

PCIE_CALRP PCIE_CALRN

@

CLK_CALRN

25M_X1

25M_X2

C

U2A

HUDSON-2

AE2

PCIE_RST#

AD5

A_RST#

AE30

UMI_TX0P

AE32

UMI_TX0N

AD33

UMI_TX1P

AD31

UMI_TX1N

AD28

UMI_TX2P

AD29

UMI_TX2N

AC30

UMI_TX3P

AC32

UMI_TX3N

AB33

UMI_RX0P

AB31

UMI_RX0N

AB28

UMI_RX1P

AB29

UMI_RX1N

Y33

UMI_RX2P

Y31

UMI_RX2N

Y28

UMI_RX3P

Y29

UMI_RX3N

AF29

PCIE_CALRP

AF31

PCIE_CALRN

V33

GPP_TX0P

V31

GPP_TX0N

W30

GPP_TX1P

W32

GPP_TX1N

AB26

GPP_TX2P

AB27

GPP_TX2N

AA24

GPP_TX3P

AA23

GPP_TX3N

AA27

GPP_RX0P

AA26

GPP_RX0N

W27

GPP_RX1P

V27

GPP_RX1N

V26

GPP_RX2P

W26

GPP_RX2N

W24

GPP_RX3P

W23

GPP_RX3N

F27

CLK_CALRN

G30

PCIE_RCLKP

G28

PCIE_RCLKN

R26

DISP_CLKP

T26

DISP_CLKN

H33

DISP2_CLKP

H31

DISP2_CLKN

T24

APU_CLKP

T23

APU_CLKN

J30

SLT_GFX_CLKP

K29

SLT_GFX_CLKN

H27

GPP_CLK0P

H28

GPP_CLK0N

J27

GPP_CLK1P

K26

GPP_CLK1N

F33

GPP_CLK2P

F31

GPP_CLK2N

E33

GPP_CLK3P

E31

GPP_CLK3N

M23

GPP_CLK4P

M24

GPP_CLK4N

M27

GPP_CLK5P

M26

GPP_CLK5N

N25

GPP_CLK6P

N26

GPP_CLK6N

R23

GPP_CLK7P

R24

GPP_CLK7N

N27

GPP_CLK8P

R27

GPP_CLK8N

J26

14M_25M_48M_OSC

C31

25M_X1

C33

25M_X2

S IC 218-0755091 A13 HUDSON-M3L FCBGA 656P C38

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HUDSON-2

PCI CLKS

PCICLK4/14M_OSC/GPO39

PCI EXPRESS INTERFACES

PCI INTERFACE

REQ2#/CLK_REQ8#/GPIO41 REQ3#/CLK_REQ5#/GPIO42

GNT2#/SD_LED/GPO45

GNT3#/CLK_REQ7#/GPIO46

CLOCK GENERATOR

LPCAPUS5 PLUS

LDRQ1#/CLK_REQ6#/GPIO49

2011/10/12 2013/10/12

C

PCICLK0 PCICLK1/GPO36 PCICLK2/GPO37 PCICLK3/GPO38

PCIRST#

AD0/GPIO0 AD1/GPIO1 AD2/GPIO2 AD3/GPIO3 AD4/GPIO4 AD5/GPIO5 AD6/GPIO6 AD7/GPIO7 AD8/GPIO8

AD9/GPIO9 AD10/GPIO10 AD11/GPIO11 AD12/GPIO12 AD13/GPIO13 AD14/GPIO14 AD15/GPIO15 AD16/GPIO16 AD17/GPIO17 AD18/GPIO18 AD19/GPIO19 AD20/GPIO20 AD21/GPIO21 AD22/GPIO22 AD23/GPIO23 AD24/GPIO24 AD25/GPIO25 AD26/GPIO26 AD27/GPIO27 AD28/GPIO28 AD29/GPIO29 AD30/GPIO30 AD31/GPIO31

CBE0# CBE1# CBE2# CBE3#

FRAME#

DEVSEL#

IRDY#

TRDY#

PAR STOP# PERR# SERR# REQ0#

REQ1#/GPIO40

GNT0#

GNT1#/GPO44

CLKRUN#

LOCK#

INTE#/GPIO32

INTF#/GPIO33 INTG#/GPIO34 INTH#/GPIO35

LPCCLK0

LPCCLK1

LAD0 LAD1 LAD2 LAD3

LFRAME#

LDRQ0#

SERIRQ/GPIO48

DMA_ACTIVE#

PROCHOT#

APU_PG

LDT_STP#

APU_RST#

S5_CORE_EN

RTCCLK

INTRUDER_ALERT#

VDDBT_RTC_G

32K_X1

32K_X2

AF3 AF1 AF5 AG2 AF6

AB5

AJ3 AL5 AG4 AL6 AH3 AJ5 AL1 AN5 AN6 AJ1 AL8 AL3 AM7 AJ6 AK7 AN8 AG9 AM11 AJ10 AL12 AK11 AN12 AG12 AE12 AC12 AE13 AF13 AH13 AH14 AD15 AC15 AE16 AN3 AJ8 AN10 AD12 AG10 AK9 AL10 AF10 AE10 AH1 AM9 AH8 AG15 AG13 AF15 AM17 AD16 AD13 AD21 AK17 AD19 AH9

AF18 AE18 AC16 AD18

B25

D25 D27 C28 A26 A29 A31 B27 AE27 AE19

G25 E28 E26 G26 F26

H7 F1 F3 E6

G2

G4

Compal Secret Data

APU_PCIE_RST#_C

Module design have reserve GPIO44,45 for VGA power enable and reset

R558 22_0402_5%R558 22_0402_5%

1 2

APU_PROCHOT#_R

32K_X1

32K_X2

Deciphered Date

D

PCI_CLK1 <14>

PCI_CLK3 <14> PCI_CLK4 <14>

APU_PCIE_RST #: Reset PCIE device on APU

MC74VHC1G08DFT2G SC70 5P

R692

@R692

@

1 2

33_0402_5%

C790

150P_0402_50V8J

12

1

@

2

@

R693

8.2K_0402_5%

R692/ C790 close to FCH

PCI_AD23 <14> PCI_AD24 <14> PCI_AD25 <14> PCI_AD26 <14> PCI_AD27 <14>

T14T14

T99T99

LPC_CLK1 <14> LPC_AD0 <29,30> LPC_AD1 <29,30> LPC_AD2 <29,30> LPC_AD3 <29,30> LPC_FRAME# <29,30>

SERIRQ <30>

R15 0_0402_5%@R15 0_0402_5%@

1 2

APU_PWRGD <5,44>

APU_RST# <5>

T100T100

RTC_CLK <14,30>

CLK_PCI_EC <14,30>

1U_0402_6.3V6K

D

@

1 2

R670

0_0402_5%

change to 510 Ohm

W=20mils

1

C156

2

1 2

R105 510_0402_5%R105 510_0402_5%

Size Document Number Rev

Custom

Date: Sheet of

Title

2

1

1 2

0_0402_5%

E

+3VALW

C789

@C789

@

1 2

0.1U_0402_16V4Z

5

P

B

4

Y

A

G

U43

3

@

R695

@R695

@

CLK_PCI_DB <29>

ALLOW_STOP# <5> H_PROCHOT# <5,30,37>

+RTCBATT

12

CLRP1 SHORT PADS

SHORT PADS

@CLRP1

@

1 2

R866

R866 0_0402_5%

0_0402_5%

APU_PCIE_RST# <15,29>

PLT_RST# <25,30>PCIE_FTX_C_DRX_P0<25>

for Clear CMOS

Compal Electronics, Inc.

FCH PCIE/CLK/PCI/LPC/RTC

LA8681P

E

0.1

10 48Wednesday, November 30, 2011

0.1

A

B

C

D

E

4MB SPI ROM & Non-share ROM.

+3VALW

1 2

SPI_WP#_R

3.3K_0402_5%

SPI_HOLD#

U4

1

CS#

2

SO/SIO1

3 4

HOLD# WP# GND

SI/SIO0

W25Q32BVSSIG SOIC 8

VCC

SCLK

+3VALW

8

SPI_HOLD#

7

SPI_CLK_FCH

6

SPI_SI

5

GBE_PHY_INTR

0.1U_0402_16V4Z

0.1U_0402_16V4Z C165

C165

1 2

R110

0_0402_5%

1 2 1 2

33_0402_5%

R119

R110 place close to FCH

R121 10K_0402_5%R121 10K_0402_5%

1 2

R112

U2B

1 1

HDD

ODD

SATA_FTX_C_DRX_P0<28> SATA_FTX_C_DRX_N0<28>

SATA_FRX_C_DTX_N0<28> SATA_FRX_C_DTX_P0<28>

SATA_FTX_C_DRX_P1<28> SATA_FTX_C_DRX_N1<28>

SATA_FRX_C_DTX_N1<28> SATA_FRX_C_DTX_P1<28>

FCH-M3L NC pin

2 2

SATA_CALRP

R1281K_0402_1% R1281K_0402_1%

12

SATA_CALRN

R130931_0402_1% R130931_0402_1%

+AVDD_SATA

+3VS

3 3

BT_DISABLE#<29>

4 4

12

R13310K_0402_5% @ R13310K_0402_5% @

1 2

BT_ON#<28>

WL_OFF#<29>

ODD_EN<28>

1 2

R146 10K_0402_5%R146 10K_0402_5%

1 2

R149 10K_0402_5%R149 10K_0402_5%

1 2

R151 10K_0402_5%R151 10K_0402_5%

T48T48

U2B

AK19

SATA_TX0P

AM19

SATA_TX0N

AL20

SATA_RX0N

AN20

SATA_RX0P

AN22

SATA_TX1P

AL22

SATA_TX1N

AH20

SATA_RX1N

AJ20

SATA_RX1P

AJ22

SATA_TX2P

AH22

SATA_TX2N

AM23

SATA_RX2N

AK23

SATA_RX2P

AH24

SATA_TX3P

AJ24

SATA_TX3N

AN24

SATA_RX3N

AL24

SATA_RX3P

AL26

SATA_TX4P

AN26

SATA_TX4N

AJ26

SATA_RX4N

AH26

SATA_RX4P

AN29

SATA_TX5P

AL28

SATA_TX5N

AK27

SATA_RX5N

AM27

SATA_RX5P

AL29

NC6

AN31

NC7

AL31

NC8

AL33

NC9

AH33

NC10

AH31

NC11

AJ33

NC12

AJ31

NC13

AF28

SATA_CALRP

AF27

SATA_CALRN

AD22

SATA_ACT#/GPIO67

AF21

SATA_X1

AG21

SATA_X2

AH16

FANOUT0/GPIO52

AM15

FANOUT1/GPIO53

AJ16

FANOUT2/GPIO54

AK15

FANIN0/GPIO56

AN16

FANIN1/GPIO57

AL16

FANIN2/GPIO58

K6

TEMPIN0/GPIO171

K5

TEMPIN1/GPIO172

K3

TEMPIN2/GPIO173

M6

TEMPIN3/TALERT#/GPIO174

HUDSON-2

SERIAL ATA

HW MONITOR

SD_CLK/SCLK_2/GPIO73

SD_CMD/SLOAD_2/GPIO74

SD_DATA0/SDATI_2/GPIO77

SD_DATA1/SDATO_2/GPIO78

SD CARDGBE LANSPI ROMVGA DACVGA MAINLINK

SD_DATA2/GPIO79 SD_DATA3/GPIO80

GBE_RXCTL/RXDV

GBE_TXCTL/TXEN

GBE_PHY_RST#

GBE_PHY_INTR

SPI_DI/GPIO164

SPI_DO/GPIO163

SPI_CLK/GPIO162

SPI_CS1#/GPIO165

ROM_RST#/SPI_WP#/GPIO161

VGA_HSYNC/GPO68 VGA_VSYNC/GPO69

VGA_DDC_SDA/GPO70

VGA_DDC_SCL/GPO71

VGA_DAC_RSET

AUX_VGA_CH_P AUX_VGA_CH_N

ML_VGA_HPD/GPIO229

VIN2/SDATI_1/GPIO177

VIN3/SDATO_1/GPIO178

VIN4/SLOAD_1/GPIO179

VIN5/SCLK_1/GPIO180

VIN6/GBE_STAT3/GPIO181

VIN7/GBE_LED3/GPIO182

SD_CD/GPIO75 SD_WP/GPIO76

GBE_COL GBE_CRS

GBE_MDCK

GBE_MDIO

GBE_RXCLK

GBE_RXD3 GBE_RXD2 GBE_RXD1 GBE_RXD0

GBE_RXERR

GBE_TXCLK

GBE_TXD3 GBE_TXD2 GBE_TXD1 GBE_TXD0

GBE_PHY_PD

VGA_RED

VGA_GREEN

VGA_BLUE

AUXCAL

ML_VGA_L0P ML_VGA_L0N ML_VGA_L1P ML_VGA_L1N ML_VGA_L2P ML_VGA_L2N ML_VGA_L3P ML_VGA_L3N

VIN0/GPIO175

VIN1/GPIO176

NC1 NC2 NC3 NC4 NC5

AL14 AN14 AJ12 AH12 AK13 AM13 AH15 AJ14

AC4 AD3 AD9 W10 AB8 AH7 AF7 AE7 AD7 AG8 AD1 AB7 AF9 AG6 AE8 AD8 AB9 AC2 AA7

GBE_PHY_INTR

W9

SPI_SO_R

V6

SPI_SI_R

V5

SPI_CLK_FCH_R

V3

SPI_SB_CS0#_R

T6

SPI_WP#

V1

L30

L32

M29

M28 N30

M33 N32

K31

V28 V29

U28

T31 T33 T29 T28 R32 R30 P29 P28

C29

N2

M3

L2

N4

P1

P3

M1

M5

AG16 AH10 A28 G27 L4

FCH-M3L NC pin

1 2

R137 10K_0402_5%R137 10K_0402_5%

1 2

R138 10K_0402_5%R138 10K_0402_5%

1 2

R139 10K_0402_5%R139 10K_0402_5%

1 2

R148 10K_0402_5%R148 10K_0402_5%

Need to enable i nternal pull down to lea ve unconnected

R115

0_0402_5%

SPI_SB_CS0#_R SPI_SO_R SPI_SO_L

SPI_WP#

0_0402_5%

1 2 1 2

33_0402_5%

R117

R117 R116

R116

0_0402_5%

1 2

R112

R108 10K_0402_5%R108 10K_0402_5%

SPI_SB_CS0#

SPI_WP#_R

SPI_CLK_FCH

33_0402_5%

22P_0402_50V8J

SPI_CLK_FCH_R SPI_SI_R

R111

@

C160

@

+3VALW

12

S IC 218-0755091 A13 HUDSON-M3L FCBGA 656P C38

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/10/12 2013/10/12

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

FCH SATA/SPI/VGA/HWM/SD

LA8681P

11 48Wednesday, November 30, 2011

E

0.1

A

1 1

+3VALW

For FCH internal debug use

R179 2.2K_0402_5%@R179 2.2K_0402_5%@

1 2

R181 2.2K_0402_5%@R181 2.2K_0402_5%@

1 2

R183 2.2K_0402_5%@R183 2.2K_0402_5%@

2 2

+3VALW

3 3

+3VS

4 4

1 2

R883 10K_0402_5%@R883 10K_0402_ 5%@

1 2

R624 10K_0402_5%R624 10K_0402_5%

1 2

R625 10K_0402_5%R625 10K_0402_5%

1 2

R174 10K_0402_5%R174 10K_0402_5%

1 2

R618 10K_0402_5%@R618 10K_0402_ 5%@

1 2

R649 10K_0402_5%@R649 10K_0402_ 5%@

1 2

R620 10K_0402_5%@R620 10K_0402_ 5%@

1 2

R163 10K_0402_5%@R163 10K_0402_ 5%@

1 2

R164 10K_0402_5%@R164 10K_0402_ 5%@

1 2

R169 100K_0402_5%@R169 100K_0402_5%@

1 2

R170 10K_0402_5%@R170 10K_0402_ 5%@

1 2

R171 2.2K_0402_5%R171 2.2K_0402_5%

1 2

R172 2.2K_0402_5%R172 2.2K_0402_5%

1 2

R175 10K_0402_5%R175 10K_0402_5%

1 2

R173 8.2K_0402_5%R173 8.2K_0402_5%

1 2

R176 8.2K_0402_5%R176 8.2K_0402_5%

1 2

R166 10K_0402_5%R166 10K_0402_5%

1 2

R168 10K_0402_5%R168 10K_0402_5%

1 2

R177 2.2K_0402_5%R177 2.2K_0402_5%

1 2

R178 10K_0402_5%@R178 10K_0402_5%@

1 2

R180 10K_0402_5%@R180 10K_0402_5%@

1 2

R182 10K_0402_5%PX@R182 10K_0402_5%PX@

1 2

ODD_DA#_FCH

ODD_DETECT#

H_THERMTRIP#

EC_LID_OUT#

FCH_PCIE_WAKE#

FCH_SMCLK0

FCH_SMDAT0

WD_PWRGD

WLAN_CLKREQ#

LAN_CLKREQ#

FCH_SMCLK1

FCH_SMDATA1

EC_RSMRST#

HDA_BITCLK

HDA_SDIN0

PEG_CLKREQ#_R

A

TEST0

TEST1

TEST2

USB_OC7#

USB_OC2#

USB_OC1#

USB_OC0#

USB_OC5#

USB_OC3#

PEG_CLKREQ#<16>

HDA_BITCLK_AUDIO<27> HDA_SDOUT_AUDIO<27>

HDA_SDIN0<27>

HDA_SYNC_AUDIO<27>

HDA_RST_AUDIO#<27>

PXS_RST#<15> PXS_PWREN<17,43>

VGA_GATE#<30>

+3VALW+3VALW

12

UMA@

12

PX@

R684

R685

10K_0402_5%

GPIO189 GPIO190

12

PX@

R682

R683

10K_0402_5%

B

PCIE_RST2 : Reset PCIE device on Hudson 3

EC_LID_OUT#<30>

PM_SLP_S3#<30> PM_SLP_S5#<30> PBTN_OUT#<30>

FCH_PWRGD<30,44>

GATEA20<30>

KBRST#<30> EC_SCI#<30> EC_SMI#<30>

R155 10K_0402_5%@R155 10K_0402_5%@

1 2

FCH_PCIE_WAKE#<25,29>

H_THERMTRIP#<5>

EC_RSMRST#<30>

LAN_CLKREQ#<25>

FCH_SPKR<27> FCH_SMCLK0<8,9,29> FCH_SMDAT0<8,9,29>

WLAN_CLKREQ#<29>

VGA_PWRGD<15,17,43>

R156 0_0402_5%@R156 0_0402_5%@

ODD_DA#_FCH<28>

R159 33_0402_5%R159 33_0402_5% R160 33_0402_5%R160 33_0402_5%

R161 33_0402_5%R161 33_0402_5% R162 33_0402_5%R162 33_0402_5%

2

G

BOARD Config.

12

ODD_DETECT#<28>

USB_OC2#<32> USB_OC1#<33> USB_OC0#<34>

1 2 1 2

12 12

13

D

PX@

Q112

2N7002K_SOT23-3

S

GPIO189 GPIO190

0 0

1 1

B

FCH_PWRGD

TEST0 TEST1 TEST2

SYS_RESET#

WD_PWRGD

FCH_SMCLK0 FCH_SMDAT0 FCH_SMCLK1 FCH_SMDATA1

PEG_CLKREQ#_R

USB_OC7#

USB_OC5#

USB_OC3# USB_OC2# USB_OC1# USB_OC0#

R960_0402_5% PX@ R960_0402_5% PX@ R970_0402_5% PX@ R970_0402_5% PX@

10

01

T17T17

HDA_BITCLK HDA_SDOUT HDA_SDIN0

HDA_SYNC HDA_RST#

T61T61 T19T19

GPIO189 GPIO190

Function

PX4 Full

PX4 low

UMA Low

UMA Full

C

U2D

HUDSON-2

AB6

PCIE_RST2#/PCI_PME#/GEVENT4#

R2

RI#/GEVENT22#

W7

SPI_CS3#/GBE_STAT1/GEVENT21#

T3

SLP_S3#

W2

SLP_S5#

J4

PWR_BTN#

N7

PWR_GOOD

T9

TEST0

T10

TEST1/TMS

V9

TEST2

AE22

GA20IN/GEVENT0#

AG19

KBRST#/GEVENT1#

R9

LPC_PME#/GEVENT3#

C26

LPC_SMI#/GEVENT23#

T5

LPC_PD#/GEVENT5#

U4

SYS_RESET#/GEVENT19#

K1

WAKE#/GEVENT8#

V7

IR_RX1/GEVENT20#

R10

THRMTRIP#/SMBALERT#/GEVEN T2#

AF19

WD_PWRGD

U2

RSMRST#

AG24

CLK_REQ4#/SATA_IS0#/GPIO64

AE24

CLK_REQ3#/SATA_IS1#/GPIO63

AE26

SMARTVOLT1/SATA_IS2#/GPIO50

AF22

CLK_REQ0#/SATA_IS3#/GPIO60

AH17

SATA_IS4#/FANOUT3/GPIO55

AG18

SATA_IS5#/FANIN3/GPIO59

AF24

SPKR/GPIO66

AD26

SCL0/GPIO43

AD25

SDA0/GPIO47

T7

SCL1/GPIO227

R7

SDA1/GPIO228

AG25

CLK_REQ2#/FANIN4/GPIO62

AG22

CLK_REQ1#/FANOUT4/GPIO61

J2

IR_LED#/LLB#/GPIO184

AG26

SMARTVOLT2/SHUTDOWN #/GPIO51

V8

DDR3_RST#/GEVENT7#/VGA_PD

W8

GBE_LED0/GPIO183

Y6

SPI_HOLD#/GBE_LED1/GEVENT9#

V10

GBE_LED2/GEVENT10#

AA8

GBE_STAT0/GEVENT11#

AF25

CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#

M7

BLINK/USB_OC7#/GEVENT18#

R8

USB_OC6#/IR_TX1/GEVENT6#

T1

USB_OC5#/IR_TX0/GEVENT17#

P6

USB_OC4#/IR_RX0/GEVENT16#

F5

USB_OC3#/AC_PRES/TDO/GEVENT15#

P5

USB_OC2#/TCK/GEVENT14#

J7

USB_OC1#/TDI/GEVENT13#

T8

USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT1 2#

AB3

AZ_BITCLK

AB1

AZ_SDOUT

AA2

AZ_SDIN0/GPIO167

Y5

AZ_SDIN1/GPIO168

Y3

AZ_SDIN2/GPIO169

Y1

AZ_SDIN3/GPIO170

AD6

AZ_SYNC

AE4

AZ_RST#

K19

PS2_DAT/SDA4/GPIO187

J19

PS2_CLK/CEC/SCL4/GPIO188

J21

SPI_CS2#/GBE_STAT2/GPIO166

D21

PS2KB_DAT/GPIO189

C20

PS2KB_CLK/GPIO190

D23

PS2M_DAT/GPIO191

C22

PS2M_CLK/GPIO192

F21

KSO_0/GPIO209

E20

KSO_1/GPIO210

F20

KSO_2/GPIO211

A22

KSO_3/GPIO212

E18

KSO_4/GPIO213

A20

KSO_5/GPIO214

J18

KSO_6/GPIO215

H18

KSO_7/GPIO216

G18

KSO_8/GPIO217

B21

KSO_9/GPIO218

K18

KSO_10/GPIO219

D19

KSO_11/GPIO220

A18

KSO_12/GPIO221

C18

KSO_13/GPIO222

B19

KSO_14/GPIO223

B17

KSO_15/GPIO224

A24

KSO_16/GPIO225

D17

KSO_17/GPIO226

S IC 218-0755091 A13 HUDSON-M3L FCBGA 656P C38

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

HUDSON-2

EMBEDDED CTRL

2011/10/12 2013/10/12

USBCLK/14M_25M_48M_OSC

USB MISCUSB 1.1USB 2.0USB 3.0

USB_FSD1P/GPIO186

USB_FSD0P/GPIO185

USB OC GPIO ACPI / WAKE UP EVENTSHD AUDIO

SCL3_LV/GPIO195

SDA3_LV/GPIO196 EC_PWM0/EC_TIMER 0/GPIO197 EC_PWM1/EC_TIMER 1/GPIO198

EC_PWM2/EC_TIMER 2/WOL_EN/GPIO199

EC_PWM3/EC_TIMER 3/GPIO200

Compal Secret Data

Deciphered Date

USB_RCOMP

USB_FSD1N

USB_FSD0N

USB_HSD13P USB_HSD13N

USB_HSD12P USB_HSD12N

USB_HSD11P USB_HSD11N

USB_HSD10P USB_HSD10N

USB_HSD9P USB_HSD9N

USB_HSD8P USB_HSD8N

USB_HSD7P USB_HSD7N

USB_HSD6P USB_HSD6N

USB_HSD5P USB_HSD5N

USB_HSD4P USB_HSD4N

USB_HSD3P USB_HSD3N

USB_HSD2P USB_HSD2N

USB_HSD1P USB_HSD1N

USB_HSD0P USB_HSD0N

USBSS_CALRP USBSS_CALRN

USB_SS_TX3P USB_SS_TX3N

USB_SS_RX3P USB_SS_RX3N

USB_SS_TX2P USB_SS_TX2N

USB_SS_RX2P USB_SS_RX2N

USB_SS_TX1P USB_SS_TX1N

USB_SS_RX1P USB_SS_RX1N

USB_SS_TX0P USB_SS_TX0N

USB_SS_RX0P USB_SS_RX0N

SCL2/GPIO193 SDA2/GPIO194

KSI_0/GPIO201 KSI_1/GPIO202 KSI_2/GPIO203 KSI_3/GPIO204 KSI_4/GPIO205 KSI_5/GPIO206 KSI_6/GPIO207 KSI_7/GPIO208

D

G8

B9

H1 H3

H6 H5

H10 G10

K10 J12

G12 F12

K12 K13

B11 D11

E10 F10

C10 A10

H9 G9

A8 C8

F8 E8

C6 A6

C5 A5

C1 C3

E1 E3

C16 A16

A14 C14

C12 A12

D15 B15

E14 F14

F15 G15

H13 G13

J16 H16

J15 K15

H19 G19 G22 G21 E22 H22 J22 H21

K21 K22 F22 F24 E24 B23 C24 F18

D

USB_RCOMP

R154 11.8K_0402_1%R154 11.8K_0402_1%

1 2

FCH-M3L NC pin

USB30_P11 <34> USB30_N11 <34 >

USB30_P10 <34> USB30_N10 <34 >

FCH-M3L NC pin

USB20_P6 <28> USB20_N6 <28>

USB20_P5 <32> USB20_N5 <32>

FCH-M3L NC pin

USB20_P3 <22> USB20_N3 <22>

USB20_P2 <29> USB20_N2 <29>

USB20_P1 <32> USB20_N1 <32>

USB20_P0 <33>

USBSS_CALRP USBSS_CALRN

USB20_N0 <33>

R864 1K_0402_1%R864 1K _0402_1%

1 2

R865 1K_0402_1%R865 1K _0402_1%

1 2

FCH-M3L NC pin

USB30_FTX_DRX_P1 USB30_FTX_DRX_N1

USB30_FRX_DTX_P1 USB30_FRX_DTX_N1

USB30_FTX_DRX_P0 USB30_FTX_DRX_N0

USB30_FRX_DTX_P0 USB30_FRX_DTX_N0

R165 10K_0402_5%R165 10K_0402_5%

1 2

R167 10K_0402_5%R167 10K_0402_5%

1 2

R227 10K_0402_5%R227 10K_0402_5%

1 2

R228 10K_0402_5%R228 10K_0402_5%

1 2

EC_PWM2

Title

Size Document Number Rev

Custom

Date: Sheet of

E

LP2

LP1

BT

CR

CMOS

WLAN

RP2

RP1

+FCH_VDD_11_SSUSB_S

USB30_FTX_DRX_P1 <34> USB30_FTX_DRX_N1 <34>

USB30_FRX_DTX_P1 <34> USB30_FRX_DTX_N1 <34>

USB30_FTX_DRX_P0 <34> USB30_FTX_DRX_N0 <34>

USB30_FRX_DTX_P0 <34> USB30_FRX_DTX_N0 <34>

EC_PWM2 <14>

strap pin

Compal Electronics, Inc.

FCH-ACPI/USB/HDA/GPIO

LA8681P

E

Root

12 48Wednesday, November 30, 2011

LP2

LP1

0.1

A

B

C

D

E

+3VS

1 1

del +VDDPL_33_MLDAC power plane

L4

1 2

MBK1608221YZF_2P

220 ohm

+VDDPL_33_SYS

C181

2.2U_0402_6.3V6M

C181

2.2U_0402_6.3V6M

C182

1

2

0.1U_0402_16V7K

1

2

+3VS

1 2

R185 0_0603_5%R185 0_0603_5%

C176

1

2

+VDDPL_33_SYS

22U_0603_6.3V6M

0.1U_0402_16V7K

C178

1

2

+VDDIO_33_PCIGP

0.1U_0402_16V7K

C187

C179

1

2

demo board connect to GND

VDDPL_33_SSUSB_S F

or Hudson3 USB3.0 only

For Hudson2, connect to GND

LDO_CAP: Internally generated 1.8V

upply for the RGB outputs

s

del +FCH_VDDAN_33_DAC power plane

2 2

+3VALW

+VDDAN_33_USB

3 3

+3VS

4 4

L6

1 2

MBK1608221YZF_2P

20 ohm

2

L7

1 2

MBK1608221YZF_2P

220 ohm

L10

1 2

MBK1608221YZF_2P

220 ohm

L12

1 2

MBK1608221YZF_2P

220 ohm

+VDDPL_33_SSUSB_S

C198

2.2U_0402_6.3V6M

C198

2.2U_0402_6.3V6M

1

2

+VDDPL_33_USB_S

C210

2.2U_0402_6.3V6M

C210

2.2U_0402_6.3V6M

1

2

+VDDPL_33_PCIE

+VDDPL_33_SATA

A

C200

0.1U_0402_16V7K

C200

0.1U_0402_16V7K

1

2

C211

0.1U_0402_16V7K

C211

0.1U_0402_16V7K

1

2

C218

2.2U_0402_6.3V6M

C218

2.2U_0402_6.3V6M

1

2

C227

2.2U_0402_6.3V6M

C227

2.2U_0402_6.3V6M

1

2

demo board connect to GND

+3VALW

FBMA-L11-201209-221LMA30T_0805

+1.1VALW

MBK1608221YZF_2P

+1.1VALW

MBK1608221YZF_2P

L15

+1.1VALW

FBMA-L11-201209-221LMA30T_0805

L15

42 ohm/4A

+VDDPL_33_USB_S

+VDDPL_33_PCIE

+VDDPL_33_SATA

L8

1 2

220 ohm/2A

L11

1 2

220 ohm

L13

1 2

220 ohm

+FCH_VDD_11_SSUSB_S

40mils

12

R199

1 2

0_0603_5%

R201

1 2

0_0603_5%

B

10U_0603_6.3V6M

C212

1

2

C219

2.2U_0402_6.3V6M

C219

2.2U_0402_6.3V6M

1

2

C223

10U_0603_6.3V6M

C223

10U_0603_6.3V6M

1

2

+VDDPL_33_SSUSB_S

@

1 2

C194 2.2U_0603_6.3V4Z

1 2

R196 0_0402_5%R196 0_0402_5%

+VDDAN_33_USB

10U_0603_6.3V6M

C213

C214

1U_0402_6.3V6K

C214

1U_0402_6.3V6K

C215

1U_0402_6.3V6K

C215

1

2

C220

0.1U_0402_16V7K

C220

0.1U_0402_16V7K

C234

1

2

Add C234 follow AMD reccommandation 10/28

C224

0.1U_0402_16V7K

C224

0.1U_0402_16V7K

1

2

C229

1

2

C237

1

2

1U_0402_6.3V6K

1

2

+VDDAN_11_USB_S+VDDAN_11_USB_S

0.1U_0402_16V7K@C234

0.1U_0402_16V7K

1

@

2

+VDDCR_11V_USB

C225

0.1U_0402_16V7K

C225

0.1U_0402_16V7K

1

2

+VDDAN_11_SSUSB

1U_0402_6.3V6K

C230

0.1U_0402_16V7K

C230

0.1U_0402_16V7K

1

2

+VDDCR_11_SSUSB

C238

1U_0402_6.3V6K

C238

1U_0402_6.3V6K

10U_0603_6.3V6M

1

2

C216

1

2

C231

0.1U_0402_16V7K

C231

0.1U_0402_16V7K

1

2

C239

1

2

U2C

HUDSON-2

102mA

AB17

VDDIO_33_PCIGP_1

AB18

VDDIO_33_PCIGP_2

AE9

VDDIO_33_PCIGP_3

AD10

VDDIO_33_PCIGP_4

AG7

VDDIO_33_PCIGP_5

AC13

VDDIO_33_PCIGP_6

AB12

VDDIO_33_PCIGP_7

AB13

VDDIO_33_PCIGP_8

AB14

VDDIO_33_PCIGP_9

AB16

VDDIO_33_PCIGP_10

47mA

H24

VDDPL_33_SYS

20mA

V22

VDDPL_33_DAC

12mA

U22

VDDPL_33_ML

3

0mA

T22

VDDAN_33_DAC

11mA

L18

VDDPL_33_SSUSB_S

14mA

D7

VDDPL_33_USB_S

11mA

AH29

VDDPL_33_PCIE

12mA

AG28

VDDPL_33_SATA

M31

LDO_CAP

7mA

V21

VDDPL_11_DAC

226mA

Y22

VDDAN_11_ML_1

V23

VDDAN_11_ML_2

V24

VDDAN_11_ML_3

V25

VDDAN_11_ML_4

AB10

VDDIO_33_GBE_S

AB11

VDDCR_11_GBE_S_1

AA11

VDDCR_11_GBE_S_2

AA9

VDDIO_GBE_S_1

AA10

VDDIO_GBE_S_2

470mA

G7

VDDAN_33_USB_S_1

H8

0.1U_0402_16V7K

VDDAN_33_USB_S_2

J8

VDDAN_33_USB_S_3

K8

VDDAN_33_USB_S_4

K9

VDDAN_33_USB_S_5

M9

VDDAN_33_USB_S_6

M10

VDDAN_33_USB_S_7

N9

VDDAN_33_USB_S_8

N10

VDDAN_33_USB_S_9

M12

VDDAN_33_USB_S_10

N12

VDDAN_33_USB_S_11

M11

VDDAN_33_USB_S_12

140mA

U12

VDDAN_11_USB_S_1

U13

VDDAN_11_USB_S_2

42mA

T12

VDDCR_11_USB_S_1

T13

VDDCR_11_USB_S_2

282mA

P16

VDDAN_11_SSUSB_S_1

M14

VDDAN_11_SSUSB_S_2

N14

VDDAN_11_SSUSB_S_3

P13

VDDAN_11_SSUSB_S_4

P14

VDDAN_11_SSUSB_S_5

424mA

N16

VDDCR_11_SSUSB_S_1

N17

VDDCR_11_SSUSB_S_2

P17

VDDCR_11_SSUSB_S_3

M17

VDDCR_11_SSUSB_S_4

S IC 218-0755091 A13 HUDSON-M3L FCBGA 656P C38

0.1U_0402_16V7K

C240

0.1U_0402_16V7K

C240

0.1U_0402_16V7K

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HUDSON-2

PCI/GPIO I/O

USB SS USB MAIN LINKGBE LAN

POWER

C

VDDCR_11_1 VDDCR_11_2 VDDCR_11_3 VDDCR_11_4 VDDCR_11_5 VDDCR_11_6 VDDCR_11_7 VDDCR_11_8

CORE S0

VDDCR_11_9

VDDAN_11_CLK_1 VDDAN_11_CLK_2 VDDAN_11_CLK_3 VDDAN_11_CLK_4 VDDAN_11_CLK_5 VDDAN_11_CLK_6

CLKGEN I/OPCI EXPRESSSERIAL ATA3.3V_S5 I/O

VDDAN_11_CLK_7 VDDAN_11_CLK_8

VDDAN_11_PCIE_1 VDDAN_11_PCIE_2 VDDAN_11_PCIE_3 VDDAN_11_PCIE_4 VDDAN_11_PCIE_5 VDDAN_11_PCIE_6 VDDAN_11_PCIE_7 VDDAN_11_PCIE_8

VDDAN_11_SATA_1 VDDAN_11_SATA_4 VDDAN_11_SATA_2 VDDAN_11_SATA_3 VDDAN_11_SATA_5 VDDAN_11_SATA_6 VDDAN_11_SATA_7 VDDAN_11_SATA_8 VDDAN_11_SATA_9

VDDAN_11_SATA_10

VDDIO_33_S_1 VDDIO_33_S_2 VDDIO_33_S_3 VDDIO_33_S_4 VDDIO_33_S_5 VDDIO_33_S_6 VDDIO_33_S_7 VDDIO_33_S_8

VDDXL_33_S

VDDCR_11_S_1 VDDCR_11_S_2

VDDPL_11_SYS_S

VDDAN_33_HWM _S

VDDIO_AZ_S

2011/10/12 2013/10/12

1007mA

C183

T14 T17

1 T20 U16 U18

2 V14

V17 V20 Y17

40mA

3

H26 J25

C189

K24 L22

1 M22 N21 N22

2 P22

1088mA

AB24 Y21 AE25

C195

AD24 AB23

1 AA22 AF26 AG27

2

1337mA

AA21 Y20 AB21

C203

AB22 AC22

1 AC21 AA20 AA18

2 AB20

AC19

59mA

N18 L19

C207

M18 V12

1 V13 Y12 Y13

2 W11

5mA

G24

C217

1

2

187mA

N20 M20

C221

1

2

70mA

J24

C226

1

2

12mA

M8

C232

1

@

2

26mA

AA4

Compal Secret Data

Deciphered Date

+VCC_VDDCR_11

0.1U_0402_16V7K

+1.1VS_CKVDD

0.1U_0402_16V7K

+VDDAN_11_PCIE

0.1U_0402_16V7K

+VDDIO_33_S

1U_0402_6.3V6K

2.2U_0402_6.3V6M

1U_0402_6.3V6K

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M@C232

2.2U_0402_6.3V6M

@

C184

0.1U_0402_16V7K

C184

0.1U_0402_16V7K

C185

1U_0402_6.3V6K

C185

1U_0402_6.3V6K

C186

1

2

C190

1

2

C196

1

2

C204

1

2

C208

1

2

+VDDXL_3.3V

+VDDCR_1.1V

C222

1

2

+VDDPL_11_SYS_S

C228

1

2

+VDDAN_33_HWM

C233

1

2

C186

1

2

+1.1VS_CKVDD

C192

0.1U_0402_16V7K

C191

1U_0402_6.3V6K

C191

1U_0402_6.3V6K

1

2

+VDDAN_11_PCIE

C197

22U_0603_6.3V6M

C197

22U_0603_6.3V6M

1U_0402_6.3V6K

1

2

+AVDD_SATA

C206

C205

1U_0402_6.3V6K

C205

1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K@C233

0.1U_0402_16V7K

+VDDIO_AZ

1

2

C209

2.2U_0402_6.3V6M

C209

2.2U_0402_6.3V6M

1

2

C236 2.2U_0402_6.3V6MC 236 2.2U_0402_6.3V6M

1 2

D

C177

10U_0603_6.3V6M

C177

10U_0603_6.3V6M

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

22U_0603_6.3V6M

R187 0_0603_5%R187 0_0603_5%

C193

22U_0603_6.3V6M

C193

22U_0603_6.3V6M

1

2

1 2

R195 0_0402_5%R195 0_0402_5%

L9

1 2

MBK1608221YZF_2P

220 ohm

1 2

R197 0_0603_5%R197 0_0603_5%

L14

1 2

MBK1608221YZF_2P

220 ohm

1 2

R198 0_0402_5%R198 0_0402_5%

1 2

R200 0_0402_5%R200 0_0402_5%

1 2

R184 0_0805_5%R184 0_0805_5%

42ohm @ 100MHz

1 2

42ohm @ 100MHz

1 2

R191 0_0805_5%R191 0_0805_5%

42ohm @ 100MHz

1 2

R194 0_0805_5%R194 0_0805_5%

+1.1VS

+3VALW

+VDDXL_3.3V Tie to +3.3V_S5 rail if USB3 Wa ke is supported; ot herwise, tie to +3.3V_S0 rail. Hudson-2 designs : Tie to +3.3V_ S0 rail.

+1.1VALW

+3VALW

AMD reply: VDDAN_33_HWM_S: Please connect it to +3.3V_S5 directly if HWM is not used.

+3VS

VDDIO_AZ_S should be tied to +3.3/1.5V_S5 rail if Wake on Ring is supported

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

FCH PWR

LA8681P

13 48Tuesday, November 29, 2011

E

0.1

5

4

3

2

1

U2E

HUDSON-2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSAN_HWM

VSSXL

VSSPL_SYS

HUDSON-2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

GROUND

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSPL_DAC

VSSAN_DAC

VSSANQ_DAC

VSSIO_DAC

EFUSE

T25 T27 U6 U14 U17 U20 U21 U30 U32 V11 V16 V18 W4 W6 W25 W28 Y14 Y16 Y18 AA6 AA12 AA13 AA14 AA16 AA17 AA25 AA28 AA30 AA32 AB25 AC6 AC18 AC28 AD27 AE6 AE15 AE21 AE28 AF8 AF12 AF16 AF33 AG30 AG32 AH5 AH11 AH18 AH19 AH21 AH23 AH25 AH27 AJ18 AJ28 AJ29 AK21 AK25 AL18 AM21 AM25 AN1 AN18 AN28 AN33

T21 L28 K33 N28

R6

A3

A33

B7

B13

D D

C C

B B

D13

E12 E16 E29

F11 F13 F16 F17 F19 F23 F25 F29

G16 G32 H12 H15 H29

K16 K27 K28

L12 L13 L15 L16

L21 M13 M16 M21 M25

N11 N13 N23 N24

P12

P18

P20

P21

P31

P33

R11 R25 R28

T11

T16

T18

K25

H25

J10 J13 J28 J32

D9

E5

F7 F9

G6

J6 J9

K7

L6

N6

R4

N8

STRAP PINS

PCI_CLK1

ALLOW

PULL

PCIE GEN2

HIGH

DEFAULT

FORCE

PULL

PCIE GEN1

LOW

PCI_CLK1<10>

PCI_CLK3<10>

PCI_CLK4<10>

CLK_PCI_EC<10,30>

LPC_CLK1<10>

EC_PWM2<12>

RTC_CLK<10,30 >

PCI_CLK3

USE DEBUG STRAPS

IGNORE DEBUG STRAP

DEFAULT

12

@

PCI_CLK4 LPC_CLK0_EC

NON_FUSION CLOCK MODE

FUSION CLOCK MODE

DEFAULT

R202 1 0K_0402_5%R202 10K_0402_5%

12

@

R214 1 0K_0402_5%@R214 1 0K_0402_5%

12

R203 1 0K_0402_5%@R203 1 0K_0402_5%

R215 1 0K_0402_5%R215 10K_0402_5%

EC ENABLED

EC DISABLED

DEFAULT

R204 1 0K_0402_5%@R204 1 0K_0402_5%

12

@

R216 1 0K_0402_5%R216 10K_0402_5%

12

EC_PWM2

CLKGEN ENABLED

DEFAULT

CLKGEN DISABLE

R205 1 0K_0402_5%@R205 1 0K_0402_5%

R206 1 0K_0402_5%R206 10K_0402_5%

12

@

R217 1 0K_0402_5%R217 10K_0402_5%

12

@

R218 1 0K_0402_5%@R218 1 0K_0402_5%

12

@

LPC ROM

SPI ROM

DEFAULT

+3VALW+3VALW+3VALW+3VALW+3VS+3 VS+3VS

R208 1 0K_0402_5%R208 10K_0402_5%

R207 1 0K_0402_5%@R207 1 0K_0402_5%

12

R219 2 .2K_0402_5%R219 2.2K_0402_5%

R220 2 .2K_0402_5%@R220 2 .2K_0402_5%

12

@

RTC_CLKLPC_CLK1

S5 PLUS MODE DISABLED

DEFAULT

S5 PLUS MODE ENABLED

DEBUG STRAPS

FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]

PCI_AD27 PCI_AD26

PULL HIGH

PULL LOW

PCI_AD27<10>

PCI_AD26<10>

PCI_AD25<10>

PCI_AD24<10>

PCI_AD23<10>

USE PCI PLL

DEFAULT

BYPASS PCI PLL

DISABLE ILA AUTORUN

DEFAULT

ENABLE ILA AUTORUN

R209 2.2K_040 2_5%@R209 2.2K_040 2_5%

12

@

R210 2.2K_040 2_5%@R210 2.2K_040 2_5%

12

@

PCI_AD25 PCI_AD24

USE FC PLL

BYPASS FC PLL

@

R211 2.2K_040 2_5%@R211 2.2K_040 2_5%

12

USE DEFAULT PCIE STRAPS

DEFAULT

USE EEPROM PCIE STRAPS

@

12

R212 2.2K_040 2_5%@R212 2.2K_040 2_5%

PCI_AD23

DISABLE PCI MEM BOOT

DEFAULTDEFAULT

ENABLE PCI MEM BOOT

12

@

R213 2.2K_040 2_5%@R213 2.2K_040 2_5%

S IC 218-0755091 A13 HUDSON-M3L FCBGA 656P C38

A A

S IC 218-0755091 A13 HUDSON-M3L FCBGA 656P C38

5

Security Classification

2011/10/12 2013/10/12

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

2011/10/12 2013/10/12

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Numbe r Rev

B

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

FCH-VSS/Strap

LA8681P

14 48Wednesday, November 30, 2011

1

0.1

5

PCIE_CTX_GRX_P[3..0]<6>

PCIE_CTX_GRX_N[3..0]<6>

PCIE_CTX_GRX_P[3..0]

PCIE_CTX_GRX_N[3..0]

U6A

PX@

4

PCIE_CRX_GTX_P[3..0]

PCIE_CRX_GTX_N[3..0]

3

PCIE_CRX_GTX_P[3..0] <6>

PCIE_CRX_GTX_N[3..0] <6>

2

1

LVDS Interface

PCIE_CTX_GRX_P0

D D

C C

B B

CLK_PCIE_VGA<10> CLK_PCIE_VGA#<10>

VGA_PWRGD<12,17,43>

A A

PCIE_CTX_GRX_N0

PCIE_CTX_GRX_P1 PCIE_CTX_GRX_N1

PCIE_CTX_GRX_P2 PCIE_CTX_GRX_N2

PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3

CLK_PCIE_VGA CLK_PCIE_VGA#

R222 0_04 02_5%

R224

PX@R2 24

PX@

10K_0402_5%

GPU_RST#

5

@

12

PX@

R226

R226 100K_0402_5%

100K_0402_5%

AA38

Y37

Y35

W36

W38

V37

V35 U36

U38

T37

T35

R36

R38 P37

P35 N36

N38 M37

M35

L36

L38 K37

K35 J36

J38 H37

H35 G36

G38

F37

F35

E37

AB35 AA36

AH16

AA30

PCIE_RX0P PCIE_RX0N

PCIE_RX1P PCIE_RX1N

PCIE_RX2P PCIE_RX2N

PCIE_RX3P PCIE_RX3N

PCIE_RX4P PCIE_RX4N

PCIE_RX5P PCIE_RX5N

PCIE_RX6P PCIE_RX6N

PCIE_RX7P PCIE_RX7N

PCIE_RX8P PCIE_RX8N

PCIE_RX9P PCIE_RX9N

PCIE_RX10P PCIE_RX10N

PCIE_RX11P PCIE_RX11N

PCIE_RX12P PCIE_RX12N

PCIE_RX13P PCIE_RX13N

PCIE_RX14P PCIE_RX14N

PCIE_RX15P PCIE_RX15N

CLOCK

PCIE_REFCLKP PCIE_REFCLKN

PWRGOOD

PERSTB

ROBSON XT M2

PCI EXPRESS INTERFACE

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

PCIE_TX8P PCIE_TX8N

PCIE_TX9P PCIE_TX9N

PCIE_TX10P

PCIE_TX10N

PCIE_TX11P

PCIE_TX11N

PCIE_TX12P

PCIE_TX12N

PCIE_TX13P

PCIE_TX13N

PCIE_TX14P

PCIE_TX14N

PCIE_TX15P

PCIE_TX15N

CALIBRATION

PCIE_CALRP

PCIE_CALRN

4

PCIE_CRX_C_GTX_P0

Y33

PCIE_CRX_C_GTX_N0

Y32

PCIE_CRX_C_GTX_P1

W33

PCIE_CRX_C_GTX_N1 PCIE_CRX_GTX_N1

W32

PCIE_CRX_C_GTX_P2

U33

PCIE_CRX_C_GTX_N2

U32

PCIE_CRX_C_GTX_P3

U30

PCIE_CRX_C_GTX_N3 PCIE_CRX_GTX_N3

U29

T33 T32

T30 T29

P33 P32

P30 P29

N33 N32

N30 N29

L33 L32

L30 L29

K33 K32

J33 J32

K30 K29

H33 H32

Y30

Y29

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

1 2

R2231.27K_0402_1% PX@ R2231.27K_0402_1% PX@

R2252K_0402_1% PX@ R2252K_0402_1% PX@

+1.0VGS

2011/10/12 2013/10/12

3

C2410.1U_0402_16V7K PX@C2410.1U_0402_16V7K PX@

12

C2420.1U_0402_16V7K PX@C2420.1U_0402_16V7K PX@

12

C2430.1U_0402_16V7K

12

C2440.1U_0402_16V7K PX@C2440.1U_0402_16V7K PX@

12

C2450.1U_0402_16V7K

12

C2460.1U_0402_16V7K PX@C2460.1U_0402_16V7K PX@

12

C2470.1U_0402_16V7K

12

C2480.1U_0402_16V7K PX@C2480.1U_0402_16V7K PX@

12

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0

PX@

PCIE_CRX_GTX_P1

PX@

PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2

PX@

PCIE_CRX_GTX_P3

Compal Secret Data

Deciphered Date

U6G

PX@

U6G

PX@

LVDS CONTROL

TXCLK_UP_DPF3P

TXCLK_UN_DPF3N

TXOUT_U0P_DPF2P TXOUT_U0N_D PF2N

TXOUT_U1P_DPF1P TXOUT_U1N_D PF1N

TXOUT_U2P_DPF0P TXOUT_U2N_D PF0N

TXOUT_U3P TXOUT_U3N

LVTMDP

TXCLK_LP_DPE3P

TXCLK_LN_DPE3N

TXOUT_L0P_DPE2P

TXOUT_L0N_DPE2N

TXOUT_L1P_DPE1P

TXOUT_L1N_DPE1N

TXOUT_L2P_DPE0P

TXOUT_L2N_DPE0N

TXOUT_L3P

TXOUT_L3N

ROBSON XT M2

R221 0_0402_5%@R221 0_0402_5%@

PXS_RST#<12>

APU_PCIE_RST#<10,29>

2

1

Title

Size Document Numbe r Rev

B

Date: Sheet of

12

+3VGS

5

U7

P

B

4

Y

A

G

PX@

3

MC74VHC1G08DFT2G SC70 5P

Compal Electronics, Inc.

ATI_RobsonXT_M2_PCIE/LVDS

GPU_RST#

LA8681P

1

VARY_BL

DIGON

15 48Wednesday, November 30, 2011

AK27 AJ27

AK35 AL36

AJ38 AK37

AH35 AJ36

AG38 AH37

AF35 AG36

AP34 AR34

AW37 AU35

AR37 AU39

AP35 AR35

AN36 AP37

0.1

Compal LA-8681P PAWGE, G480, G485 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual