COMPAL LA-8681P Schematics

A

1 1

B

C

D

E

Compal Confidential

2 2

PAWGE Schematics Document

AMD APU Zacate-FT1 + FCH Hudson-M3L + GPU RobsonXT

3 3

2011-11-21

REV:1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/06/30 2012/06/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

LA8681P

1 48Tuesday, November 29, 2011

E

1.0

A

Compal confidential

File Name : PAWGE

B

C

D

E

QIWG5

LS7981P CardReader/B LS7982P USB/B LS7983P PWR/B

1 1

LVDS Conn.

page 22

CRT Conn.

page 24

AMD Brazos APU

FT1

Memory BUS(DDRIII)

Single Channel

1.5V DDRIII 1333

200pin DDRII-SO-DIMM X2

BANK 0, 1, 2, 3

page 8,9

BGA 413-Ball

AMDRosbon XT_M2

VRAM 64*16

DDR3*4

page 15 ~ 21

2 2

HDMI Conn.

page 23

x4 PCI-E GPP GEN2

4 * x1 PCI-E 1.0

WLAN &WiMax

page 29

GIGA LAN

RTL8111/8105

page 25,26

3 3

PCI Express Mini card Slot 1

WLAN/WiMAX

page 29

USB(WiMAX)

PCI-E(WLAN)

SPI ROM

page 11

19mm x 19mm

page 5,6,7

x4 UMI Gen. 2

Hudson M3L

BGA 656-Ball 23mm x 23mm

page 10,11,12,13,14

LPC BUS

EC

ENE KB9012

page 30

10*USB2.0

2*SATA serial

Int.KBD

page 32

AZALIA

2Channel Speaker

page 22

page 28

Internal MIC

Audio Jacks

Stereo HeadPhone Output Microphone Input

Audio Codec

CX20671

page 27

CMOS Camera

BlueTooth CONN

USB PORT 2.0 x2(Left)

USB PORT 3.0 x2(Right)

WLAN/WiMAX

Card Reader

Realtek RTS5178 SD/MMC

Daoughter board

page 27

page 33

page 34

QIWG6

LS7981P CardReader/B LS7982P USB/B LS7983P PWR/B LS7984P LED/B LS7985P ODD/B

Touch Pad

page 32

SATA3.0 HDD CONN

page 28

Thermal Sensor

4 4

A

B

EMC1403

page 29

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/06/30 2012/06/30

SATA ODD CONN

Compal Secret Data

Deciphered Date

page 28

D

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

Compal Electronics, Inc.

Block Diagrams

LA8681P

2 48Tuesday, November 29, 2011

E

1.0

A

Voltage Rails

Power Plane Description

VIN

B+

+APU_CORE

1 1

2 2

+APU_CORE_NB 1.0V switched power rail ON OFF

+1.5V

+0.75VS 0.75VS switched power rail for DDR terminator

+1.0VS

+1.1VS 1.1VS switched power rail ON OFF OFF

+1.8VS 1.8V switched power rail

+3VALW

+3V_LAN 3.3V power rail for LAN ON ON(WOL) OFF

+3VS

+5VALW

+5VS

+VSB VSB always on power rail ON ON*

+RTCVCC RTC power

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

EC SM Bus1 address

Device

Smart Battery

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU (0.7-1.2V)

1.5V power rail for CPU VDDIO and DDRIII

1.0V switched power rail for NB VDDC & VGA

3.3V always on power rail

3.3V switched power rail

5V always on power rail

5V switched power rail

EC SM Bus2 address

Address Address

0001-011xb

HEX

Device

EMC1412-2 (dGPU)

EMC1403-2(DDR,WLAN)

SB-TSI

B

S1 S3 S5

N/A N/A N/A

ON OFF

ON

ON OFF OFF

ON

1111-100xb

1001-101xb

1001-100xb

N/AN/AN/A

OFF

ON

OFF

ON ON*

OFF

ON ON*

OFF

OFFON

ONON

ON ON*ON+1.1VALW 1.1V always on power rail

HEX

F8H15H

9AH

98H

C

FCH Hudson-M3L USB Port List

USB1.1

Port0

Port1

USB2.0

Port0

Port1

Port2

Port3

Port4

Port5

Port6

Port7

Port8

Port9

Port10

Port11

Port12

Port13

NC

Right USB

Mini-PCIE

USB Camera

NC

CardReader

BT

NC

Left USB1 Left USB2

NC

D

Brazos PCIE Port List

PCIE0

APUFCH

PCIE1

PCIE2

PCIE3

PCIE0

PCIE1

PCIE2

PCIE3

GPU PCIE x4

LAN

WLAN

NC

FCH Hudson-M3L SATA Port List

SATA0

SATA1

SATA2

SATA3

SATA4

SATA5

HDD

ODD

NC

BOM Structure

UMA@ : UMA only PX@ : DIS muxluss PX 4.0

Robson@ : Robson GPU GIGA@ : RTL8111 1000 8105@ : RTL8105 10/100

E

DIMM@ : DIMM select

SM Bus Controller 0

Device Address

APU SIC/SID (FCH_SMB3)

H_THERMTRIP# (FCH_ALERT#)

(FCH_SMB1 ~ FCH_SMB4, SMB_AL ERT#)

HEX

CMOS@ : USB camera BT@ : BT function ME@ : ME components X76@, H1G@, H512@, S1G@, S512@ : VRAM 45@ : 45 Level HDMI@ : HDMI function

non HDMI@ : HDMI function

AN@ : Apple + Nokia ear phone combo

3 3

SM Bus Controller 1

Device Address HEX

DDR DIMM1 (FCH_SMB0)

DDR DIMM2 (FCH_SMB0)

WLAN (FCH_SMB0 )

1001-000xb

1001-001xb

(FCH_SMB0)

90

92

A@ : Apple ear phone PCB@ : PCB PN 14@ : 14" 15@ : 15" BBH@ : BBH nonBBH@@ : nonBBH@

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/06/30 2012/06/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Notes List

LA8681P

3 48Tuesday, November 29, 2011

E

1.0

5

Power-Up/Down Sequence

1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred.

2. VDDR3 should ramp-up before or simultaneously with VDDC.

3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before

D D

DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10.

4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and VDD_CT have ramped up.

5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to ramp-up (or vice versa).)

4

3

2

1

Without BACO option :

PXS_RST# : Low -> Reset dGPU ; High ->Normal operation PXS_PWREN : Low -> dGPU Power OFF ; High -> dGPU Power ON

BACO option :

PXS_RST# : High ->Normal operation (dGPU is not reset on BACO mode) PXS_PWREN : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)

dGPU Power Pins Max current

PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT, DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD, DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI, DPLL_PVDD, MPV18, and SPV18

DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and

Voltage

1.8V

1.0V

PX 3.0

OFF

BACO Mode

ON

1679mA

575mA

SPV10

VDDR3(3.3VGS)

Note: Do not drive any IOs before VDDR3 is ramped up.

PCIE_VDDC

VDDR3 , and A2VDD

BIF_VDDC (current consumption = 55mA@1.0V, in

PCIE_VDDC(1.0V)

BACO mode) BIF_VDDC=VGA_CORE When GPU enable

C C

VDDR1(1.5VGS)

BIF_VDDC=1.0V When BACO

VDDR1

VDDC/VDDCI

1.0V

3.3V

Same as VDDC

1.5V

1.12V

OFF

ON

ON Same as PCIE_VDDC

OFF

2A

190mA

70mA

2.8A

12.9A

VDDC/VDDCI(1.12V)

VDD_CT(1.8V)

iGPU

PERSTb

REFCLK

B B

Straps Reset

Straps Valid

PXS_RST# PE_EN

dGPU

BIF_VDDC

PXS_PWREN

+3.3VALW

+1.0V

MOS

Regulator

+3.3VGS

1

+1.0VGS

2

PX_mode

+1.5V

BACO Switch

SI4800

+1.5VGS

3

Global ASIC Reset

+B

+1.8V

T4+16clock

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

2010/06/30 2012/07/14

3

Compal Secret Data

Deciphered Date

SI4800

2

+1.8VGS

5

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

Compal Electronics, Inc.

Regulator

dGPU Block Diagram

LA8681P

4

1

+VGA_CORE

PWRGOOD

4 48Tuesday, November 29, 2011

1.0

AAAU6

PCB@AAAU6

PCB@ BBBU22

PCB 0R3 LA-8681P REV0 M/B

+1.8VS

D D

+3VS

5

AAAU22

EM1200GBB22GV

R404 1K_0402_5%R404 1K _0402_5%

1 2

R399 1K_0402_5%R399 1K _0402_5%

1 2

R400 1K_0402_5%R400 1K _0402_5%

1 2

R405 300_0402_5%

R401 300_0402_5%R401 300_0402_5%

R402 510_0402_1%R402 510_0402_1%

R403 1K_0402_5%R403 1K _0402_5%

R510 4.7K_0402_5%R510 4.7K_0402_5%

R511 4.7K_0402_5%R511 4.7K_0402_5%

R410 1K_0402_5%R410 1K _0402_5%

R411 1K_0402_5%R411 1K _0402_5%

1 2

12

E1200@AAAU22

E1200@

APU_DBREQ#

APU_SVC

APU_SVD

APU_RST#

APU_PWRGD

TEST_25_L

TEST36

EDID_CLK

EDID_DATA

APU_PROCHOT#

APU_ALERT#_R

E1800@BBBU22

E1800@

EM1800GBB22GV

TO EC

C C

B B

APU_THERMTRIP#

If FCH internal pull-up disable d, level-shifte r could be delet ed. Need BIOS to di sable internal p ull-up!!

A A

R425

1K_0402_5%

1 2

E

3 1

MMBT3904_NL_SOT23-3

1 2

R427 0_0402_5%@R427 0_0402_5%@

+3VS

B

12

2

R424

R424 10K_0402_5%

10K_0402_5%

Q79

C

APU_PWRGD<10,44>

C1022

@C1022

@

100P_0402_50V8J

1

2

H_THERMTRIP# <12>

4

C508 0.1U_0402_16V7KHDMI@C508 0.1U_0402_16V7KHDMI@

HDMI_TX2P<23>

HDMI_TX2N<23>

HDMI_TX1P<23>

HDMI_TX1N<23>

HDMI_TX0P<23>

HDMI_TX0N<23>

HDMI_CLKP<23>

HDMI_CLKN<23>

EC_SMB_CK2<16,29,30> EC_SMB_DA2<16,29,30>

H_PROCHOT#<10,30,37>

APU_VDDNB_RUN_FB_ H<44> APU_VDD0_RUN_FB_H<44>

APU_VDD0_RUN_FB_L<44>

1 2

C509 0.1U_0402_16V7K

1 2

HDMI@

C510 0.1U_0402_16V7KHDMI@C510 0.1U_0402_16V7KHDMI@

1 2

C511 0.1U_0402_16V7K

1 2

HDMI@

C512 0.1U_0402_16V7KHDMI@C512 0.1U_0402_16V7KHDMI@

1 2

C513 0.1U_0402_16V7K

1 2

HDMI@

C514 0.1U_0402_16V7KHDMI@C514 0.1U_0402_16V7KHDMI@

1 2

C515 0.1U_0402_16V7K

1 2

HDMI@

LVDS_A2<22> LVDS_A2#<22>

LVDS_A1<22> LVDS_A1#<22>

LVDS_A0<22> LVDS_A0#<22>

LVDS_ACLK<22> LVDS_ACLK#<22>

APU_CLK<10> APU_CLK#<10>

APU_DISP_CLK<10> APU_DISP_CLK#<10>

APU_SVC<44>

APU_SVD<44>

R809 0_0402_5%R809 0_0402_5%

1 2

R810 0_0402_5%R810 0_0402_5%

1 2

APU_RST#<10>

R808 0_0402_5%R808 0_0402_5%

1 2

T77PADT77PAD

HDMI_TX2P_C HDMI_TX2N_C

HDMI_TX1P_C HDMI_TX1N_C

HDMI_TX0P_C HDMI_TX0N_C

HDMI_CLKP_C HDMI_CLKN_C

EC_SMB_CK2_R EC_SMB_DA2_R

APU_PROCHOT# APU_THERMTRIP# APU_ALERT#_R

APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ#

3

U22B

A8

TDP1_TXP0

B8

TDP1_TXN0

B9

TDP1_TXP1

A9

TDP1_TXN1

D10

TDP1_TXP2

C10

TDP1_TXN2

A10

TDP1_TXP3

B10

TDP1_TXN3

B5

LTDP0_TXP0

A5

LTDP0_TXN0

D6

LTDP0_TXP1

C6

LTDP0_TXN1

A6

LTDP0_TXP2

B6

LTDP0_TXN2

D8

LTDP0_TXP3

C8

LTDP0_TXN3

V2

CLKIN_H

V1

CLKIN_L

D2

DISP_CLKIN_H

D1

DISP_CLKIN_L

J1

SVC

J2

SVD

P3

SIC

P4

SID

T3

RESET_L

T4

PWROK

U1

PROCHOT_L

U2

THERMTRIP_L

T2

ALERT_L

N2

TDI

N1

TDO

P1

TCK

P2

TMS

M4

TRST_L

M3

DBRDY

M1

DBREQ_L

F4

VDDCR_NB_SENSE

G1

VDDCR_CPU_SENSE

F3

VDDIO_MEM_S_SENSE

F1

VSS_SENSE

B4

RSVD_1

W11

RSVD_2

V5

RSVD_3

S IC E SERIES EME450GBB22GVA 1.65G BGA

DISPLAYPORT 1

DISPLAYPORT 0

CLK

SER

JTAG CTRL

DP MISC

VGA DAC

TEST

DP_ZVSS

DP_BLON

DP_DIGON

DP_VARY_BL

TDP1_AUXP

TDP1_AUXN

TDP1_HPD

LTDP0_AUXP LTDP0_AUXN

LTDP0_HPD

DAC_RED

DAC_REDB

DAC_GREEN

DAC_GREENB

DAC_BLUE

DAC_BLUEB

DAC_HSYNC DAC_VSYNC

DAC_SCL DAC_SDA

DAC_ZVSS

TEST4 TEST5

TEST6 TEST14 TEST15 TEST16 TEST17 TEST18 TEST19

TEST25_H

TEST25_L

TEST28_H

TEST28_L

TEST31

TEST33_H

TEST33_L

TEST34_H

TEST34_L

TEST35 TEST36 TEST37

TEST38

DMAACTIVE_L

2

H3

G2 H2 H1

B2 C2

C1

A3 B3

D3

C12 D13 A12 B12 A13 B13

E1 E2

F2 D4

D12

R1 R2 R6 T5 E4 K4 L1 L2 M2 K1 K2 L5 M5 M21 J18 J19 U15 T15 H4 N5 R5

K3 T1

DP_ZVSS

LTDP0_HPD

DAC_ZVSS

TEST15

TEST18 TEST19 TEST25_H TEST_25_L TEST28_H TEST28_L TEST31 TEST33_H TEST33_L

TEST35 TEST36 TEST37

R398 150_0402_1%R398 150_0402_1%

EDID_CLK EDID_DATA

R406 100K_0402_5%R406 100K_0402_5%

R407 150_0402_1%R407 150_0402_1%

1 2

R408 150_0402_1%R408 150_0402_1%

1 2

R409 150_0402_1%R409 150_0402_1%

1 2

R413 499_0402_1%R413 499_0402_1%

T66

PAD

T67

PAD

T68

PAD

T69

PAD

T95

PAD

T71

PAD

T72

PAD

T73

PAD

Delete Test point for layout limitation 20100818

T76

PAD

HDMI function e nable R958 mount d isable R422 moun t

R423 1K_0402_5%R423 1K _0402_5%

1 2

APU_ENBKL <22> APU_ENVDD <22> APU_BLPWM <22>

HDMI_CLK <23>

HDMI_DATA <23>

HDMI_DET <23>

EDID_CLK <22>

1 2

1 2 1 2 1 2

non HDMI@

1 2

EDID_DATA <22>

DAC_RED <24>

DAC_GRN <24>

DAC_BLU <24>

CRT_HSYNC <24> CRT_VSYNC <24>

CRT_DDC_CLK <24> CRT_DDC_DATA <24>

AMD check list update 20101110

ALLOW_STOP# <10>

+1.8VS

1 2

R415 1K_0402_5%@R415 1K_0402_5%@

R416 1K_0402_5%R416 1K _0402_5% R417 1K_0402_5%R417 1K _0402_5% R419 510_0402_1%R419 510_0402_1%

C516 0.1U_0402_16V4ZC516 0.1U_0402_16V4Z

1 2

C517 0.1U_0402_16V4ZC517 0.1U_0402_16V4Z

1 2

R422 1K_0402_5%

R958 1K_0402_5%HDMI@R958 1K_0402_5%HDMI@

R420 51_0402_1%R420 51_0402_1%

1 2

R421 51_0402_1%R421 51_0402_1%

1 2

+1.8VS

1

AMD Debug

check the connect need or not

JHDT1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

SAMTE_ASP-136446-07-B

@

APU_TCK

2

APU_TMS

4

APU_TDI

6

APU_TDO

8

APU_PWRGD

10

APU_RST#

12

APU_DBRDY

14

APU_DBREQ#

16

J108_PLLTST0

18

J108_PLLTST1

20

Please be noted about TEST_18 and TEST_19

R843 1K_0402_5%R843 1K _0402_5%

R844 1K_0402_5%R844 1K _0402_5%

R845 1K_0402_5%R845 1K _0402_5%

R851 0_0402_5%@R851 0_0402_5%@

R852 0_0402_5%@R852 0_0402_5%@

12

1 2

need to pop for HDT debug 20101012

TEST19

TEST18

+1.8VS

R842

1 2

1K_0402_5%

APU_TRST#

need to pop for HDT debug 20101012

@

R846 0_0402_5%

1 2

R847 10K_0402_5%@R847 10K_0402_5%@

R848 10K_0402_5%@R848 10K_0402_5%@

R849 10K_0402_5%@R849 10K_0402_5%@

12

+1.8VS +1.8VS

APU_TRST#_R

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/06/30 2012/06/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

FT1 CTRL/DP/CRT

LA8681P

5 48Wednesday, November 30, 2011

1

1.0

A

U22E

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6

4 4

3 3

2 2

DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_A_BS0<8,9> DDR_A_BS1<8,9> DDR_A_BS2<8,9>

DDR_A_DQS0<8,9>

DDR_A_DQS#0<8,9>

DDR_A_DQS1<8,9>

DDR_A_DQS#1<8,9>

DDR_A_DQS2<8,9>

DDR_A_DQS#2<8,9>

DDR_A_DQS3<8,9>

DDR_A_DQS#3<8,9>

DDR_A_DQS4<8,9>

DDR_A_DQS#4<8,9>

DDR_A_DQS5<8,9>

DDR_A_DQS#5<8,9>

DDR_A_DQS6<8,9>

DDR_A_DQS#6<8,9>

DDR_A_DQS7<8,9>

DDR_A_DQS#7<8,9>

DDR_A_CLK0<8> DDR_A_CLK#0<8> DDR_A_CLK1<8> DDR_A_CLK#1<8> DDR_B_CLK2<9> DDR_B_CLK#2<9> DDR_B_CLK3<9> DDR_B_CLK#3<9>

DDR_RST#<8,9>

DDR_EVENT#<8,9>

DDR_CKE0<8,9> DDR_CKE1<8,9>

DDR_A_ODT0<8> DDR_A_ODT1<8> DDR_B_ODT0<9> DDR_B_ODT1<9>

DDR_CS0_DIMMA#<8> DDR_CS1_DIMMA#<8> DDR_CS0_DIMMB#<9> DDR_CS1_DIMMB#<9>

DDR_A_RAS#< 8,9> DDR_A_CAS#< 8,9> DDR_A_WE#<8,9>

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1

DDR_A_DQS#1

DDR_A_DQS2

DDR_A_DQS#2

DDR_A_DQS3

DDR_A_DQS#3

DDR_A_DQS4

DDR_A_DQS#4

DDR_A_DQS5

DDR_A_DQS#5

DDR_A_DQS6

DDR_A_DQS#6

DDR_A_DQS7

DDR_A_DQS#7

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1 DDR_B_CLK2 DDR_B_CLK#2 DDR_B_CLK3 DDR_B_CLK#3

DDR_RST# DDR_EVENT#

DDR_CKE0 DDR_CKE1

DDR_A_ODT0 DDR_A_ODT1 DDR_B_ODT0 DDR_B_ODT1

DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMB# DDR_CS1_DIMMB#

DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

U22E

R17

M_ADD0

H19

M_ADD1

J17

M_ADD2

H18

M_ADD3

H17

M_ADD4

G17

M_ADD5

H15

M_ADD6

G18

M_ADD7

F19

M_ADD8

E19

M_ADD9

T19

M_ADD10

F17

M_ADD11

E18

M_ADD12

W17

M_ADD13

E16

M_ADD14

G15

M_ADD15

R18

M_BANK0

T18

M_BANK1

F16

M_BANK2

D15

M_DM0

B19

M_DM1

D21

M_DM2

H22

M_DM3

P23

M_DM4

V23

M_DM5

AB20

M_DM6

AA16

M_DM7

A16

M_DQS_H0

B16

M_DQS_L0

B20

M_DQS_H1

A20

M_DQS_L1

E23

M_DQS_H2

E22

M_DQS_L2

J22

M_DQS_H3

J23

M_DQS_L3

R22

M_DQS_H4

P22

M_DQS_L4

W22

M_DQS_H5

V22

M_DQS_L5

AC20

M_DQS_H6

AC21

M_DQS_L6

AB16

M_DQS_H7

AC16

M_DQS_L7

M17

M_CLK_H0

M16

M_CLK_L0

M19

M_CLK_H1

M18

M_CLK_L1

N18

M_CLK_H2

N19

M_CLK_L2

L18

M_CLK_H3

L17

M_CLK_L3

L23

M_RESET_L

N17

M_EVENT_L

F15

M_CKE0

E15

M_CKE1

W19

M0_ODT0

V15

M0_ODT1

U19

M1_ODT0

W15

M1_ODT1

T17

M0_CS_L0

W16

M0_CS_L1

U17

M1_CS_L0

V16

M1_CS_L1

U18

M_RAS_L

V19

M_CAS_L

V17

M_WE_L

S IC E SERIES EME450GBB22GVA 1.65G BGA

DDR SYSTEM MEMORY

B

M_DATA0 M_DATA1 M_DATA2 M_DATA3 M_DATA4 M_DATA5 M_DATA6 M_DATA7

M_DATA8

M_DATA9 M_DATA10 M_DATA11 M_DATA12 M_DATA13 M_DATA14 M_DATA15

M_DATA16 M_DATA17 M_DATA18 M_DATA19 M_DATA20 M_DATA21 M_DATA22 M_DATA23

M_DATA24 M_DATA25 M_DATA26 M_DATA27 M_DATA28 M_DATA29 M_DATA30 M_DATA31

M_DATA32 M_DATA33 M_DATA34 M_DATA35 M_DATA36 M_DATA37 M_DATA38 M_DATA39

M_DATA40 M_DATA41 M_DATA42 M_DATA43 M_DATA44 M_DATA45 M_DATA46 M_DATA47

M_DATA48 M_DATA49 M_DATA50 M_DATA51 M_DATA52 M_DATA53 M_DATA54 M_DATA55

M_DATA56 M_DATA57 M_DATA58 M_DATA59 M_DATA60 M_DATA61 M_DATA62 M_DATA63

M_VREF

M_ZVDDIO_MEM_S

B14 A15 A17 D18 A14 C14 C16 D16

C18 A19 B21 D20 A18 B18 A21 C20

C23 D23 F23 F22 C22 D22 F20 F21

H21 H23 K22 K21 G23 H20 K20 K23

N23 P21 T20 T23 M20 P20 R23 T22

V20 V21 Y23 Y22 T21 U23 W23 Y21

Y20 AB22 AC19 AA18 AA23 AA20 AB19 Y18

AC17 Y16 AB14 AC14 AC18 AB18 AB15 AC15

M23

M_ZVDDIO_MEM_S

M22

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7

DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15

DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23

DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31

DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39

DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47

DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55

DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

+MEM_VREF

R437

39.2_0402_1%

C

DDR_A_D[0..63]

DDR_A_MA[0..15]

DDR_A_DM[0..7]

PCIE_CRX_GTX_P0<15> PCIE_CRX_GTX_N0<15>

PCIE_CRX_GTX_P1<15> PCIE_CRX_GTX_N1<15>

PCIE_CRX_GTX_P2<15> PCIE_CRX_GTX_N2<15>

PCIE_CRX_GTX_P3<15> PCIE_CRX_GTX_N3<15>

+1.05VS

UMI_RX0P<10> UMI_RX0N<1 0>

UMI_RX1P<10> UMI_RX1N<1 0>

UMI_RX2P<10> UMI_RX2N<1 0>

UMI_RX3P<10> UMI_RX3N<1 0>

12

R435 2K_0402_1%R435 2K_0402_1%

Less than 1"

+1.5V_APU

1 2

DDR_A_D[0..63] <8,9>

DDR_A_MA[0..15] <8,9>

DDR_A_DM[0..7] <8,9>

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1

PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3

P_ZVDD_10

U22A

AA6

P_GPP_RXP0

Y6

P_GPP_RXN0

AB4

P_GPP_RXP1

AC4

P_GPP_RXN1

AA1

P_GPP_RXP2

AA2

P_GPP_RXN2

Y4

P_GPP_RXP3

Y3

P_GPP_RXN3

Y14

P_ZVDD_10

AA12

P_UMI_RXP0

Y12

P_UMI_RXN0

AA10

P_UMI_RXP1

Y10

P_UMI_RXN1

AB10

P_UMI_RXP2

AC10

P_UMI_RXN2

AC7

P_UMI_RXP3

AB7

P_UMI_RXN3

S IC E SERIES EME450GBB22GVA 1.65G BGA

PCIE I/F

UMI I/F

P_GPP_TXP0 P_GPP_TXN0

P_GPP_TXP1 P_GPP_TXN1

P_GPP_TXP2 P_GPP_TXN2

P_GPP_TXP3 P_GPP_TXN3

P_ZVSS

P_UMI_TXP0 P_UMI_TXN0

P_UMI_TXP1 P_UMI_TXN1

P_UMI_TXP2 P_UMI_TXN2

P_UMI_TXP3 P_UMI_TXN3

D

PCIE_CTX_C_GRX_P0

AB6

PCIE_CTX_C_GRX_N0

AC6

PCIE_CTX_C_GRX_P1

AB3

PCIE_CTX_C_GRX_N1

AC3

PCIE_CTX_C_GRX_P2

Y1

PCIE_CTX_C_GRX_N2

Y2

PCIE_CTX_C_GRX_P3

V3

PCIE_CTX_C_GRX_N3

V4

P_ZVSS

AA14

UMI_TX0P_C

AB12

UMI_TX0N_C

AC12

UMI_TX1P_C

AC11

UMI_TX1N_C

AB11

UMI_TX2P_C

AA8

UMI_TX2N_C

Y8

UMI_TX3P_C

AB8

UMI_TX3N_C

AC8

C518 0.1U_0402_16V7KC518 0.1U_0402_16V7K

1 2

C519 0.1U_0402_16V7KC519 0.1U_0402_16V7K

1 2

C520 0.1U_0402_16V7KC520 0.1U_0402_16V7K

1 2

C521 0.1U_0402_16V7KC521 0.1U_0402_16V7K

1 2

C522 0.1U_0402_16V7KC522 0.1U_0402_16V7K

1 2

C523 0.1U_0402_16V7KC523 0.1U_0402_16V7K

1 2

C524 0.1U_0402_16V7KC524 0.1U_0402_16V7K

1 2

C525 0.1U_0402_16V7KC525 0.1U_0402_16V7K

1 2

R436 1.27K_0402_1%R436 1.27K_0402_1%

1 2

Less than 1"

C526 0.1U_0 402_16V7KC526 0.1U_0402_16V7K

1 2

C527 0.1U_0 402_16V7KC527 0.1U_0402_16V7K

1 2

C528 0.1U_0 402_16V7KC528 0.1U_0402_16V7K

1 2

C529 0.1U_0402_16V7KC52 9 0.1U_0402_16V7K

1 2

C530 0.1U_0 402_16V7KC530 0.1U_0402_16V7K

1 2

C531 0.1U_0 402_16V7KC531 0.1U_0402_16V7K

1 2

C532 0.1U_0 402_16V7KC532 0.1U_0402_16V7K

1 2

C533 0.1U_0 402_16V7KC533 0.1U_0402_16V7K

1 2

E

PCIE_CTX_GRX_P0 <15> PCIE_CTX_GRX_N0 <15>

PCIE_CTX_GRX_P1 <15> PCIE_CTX_GRX_N1 <15>

PCIE_CTX_GRX_P2 <15> PCIE_CTX_GRX_N2 <15>

PCIE_CTX_GRX_P3 <15> PCIE_CTX_GRX_N3 <15>

UMI_TX0P <10> UMI_TX0N <10>

UMI_TX1P <10> UMI_TX1N <10>

UMI_TX2P <10> UMI_TX2N <10>

UMI_TX3P <10> UMI_TX3N <10>

+1.5V_APU

R444

1 2

1K_0402_5%

1 1

DDR_EVENT#

A

R438

1K_0402_1%

R439

1K_0402_1%

1 2

1

C534

1000P_0402_50V7K

2

1 2

Place within 1000 mils to APU 20100526

+MEM_VREF

1

C535

0.1U_0402_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/06/30 2012/0630

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

FT1 DDRIII/UMI/PCIE

LA8681P

E

6 48Wednesday, November 30, 2011

1.0

5

4

3

2

1

U22C

+APU_CORE

D D

1

C550

2

1

C559

2

+APU_CORE_NB

C C

C582

C591

B B

1

C551

2

1U_0402_6.3V6K

1

C560

2

0.1U_0402_16V7K

1

C583

2

1U_0402_6.3V6K

1

C592

2

0.1U_0402_16V7K

1

C553

C552

1U_0402_6.3V6K

C561

0.1U_0402_16V7K

C584

1U_0402_6.3V6K

C593

0.1U_0402_16V7K

C553

2

1U_0402_6.3V6K

1

C562

2

0.1U_0402_16V7K

1

C585

2

1U_0402_6.3V6K

1

C594

2

0.1U_0402_16V7K

1

C554

2

1U_0402_6.3V6K

1

C563

2

0.1U_0402_16V7K

1

C586

2

1U_0402_6.3V6K

1

2

0.1U_0402_16V7K

1

C555

2

180P_0402_50V8J

0.1U_0402_16V7K

1U_0402_6.3V6K

180P_0402_50V8J

1

C588

C587

2

180P_0402_50V8J

+APU_CORE_NB

+1.5V_APU

180P_0402_50V8J

+1.5V_APU

11A

E5

VDDCR_CPU_1

E6

VDDCR_CPU_2

F5

VDDCR_CPU_3

F7

VDDCR_CPU_4

G6

VDDCR_CPU_5

G8

VDDCR_CPU_6

H5

VDDCR_CPU_7

H7

VDDCR_CPU_8

J6

VDDCR_CPU_9

J8

VDDCR_CPU_10

L7

VDDCR_CPU_11

M6

VDDCR_CPU_12

M8

VDDCR_CPU_13

N7

VDDCR_CPU_14

R8

VDDCR_CPU_15

10A

E8

VDDCR_NB_1

E11

VDDCR_NB_2

E13

VDDCR_NB_3

F9

VDDCR_NB_4

F12

VDDCR_NB_5

G11

VDDCR_NB_6

G13

VDDCR_NB_7

H9

VDDCR_NB_8

H12

VDDCR_NB_9

K11

VDDCR_NB_10

K13

VDDCR_NB_11

L10

VDDCR_NB_12

L12

VDDCR_NB_13

L14

VDDCR_NB_14

M11

VDDCR_NB_15

M12

VDDCR_NB_16

M13

VDDCR_NB_17

N10

VDDCR_NB_18

N12

VDDCR_NB_19

N14

VDDCR_NB_20

P11

VDDCR_NB_21

P13

VDDCR_NB_22

2A

G16

VDDIO_MEM_S_1

G19

VDDIO_MEM_S_2

E17

VDDIO_MEM_S_3

J16

VDDIO_MEM_S_4

L16

VDDIO_MEM_S_5

L19

VDDIO_MEM_S_6

N16

VDDIO_MEM_S_7

R16

VDDIO_MEM_S_8

R19

VDDIO_MEM_S_9

W18

VDDIO_MEM_S_10

U16

VDDIO_MEM_S_11

S IC E SERIES EME450GBB22GVA 1.65G BGA

1

C589

2

1

C595

2

1

C590

2

10U_0603_6.3V6M

1U_0402_6.3V6K

10U_0603_6.3V6M

1

C596

2

1

C597

2

1U_0402_6.3V6K

TSense/PLL/DP/PCIE/IO

VDD_18_1 VDD_18_2 VDD_18_3 VDD_18_4 VDD_18_5 VDD_18_6

CPU CORE

VDD_18_7

DAC

VDD_18_DAC

GPU AND NB CORE

POWER

DIS PLL

VDDPL_10

PCIE/IO/DDR3 Phy

VDD_10_1 VDD_10_2 VDD_10_3 VDD_10_4

DDR3

DP Phy/IO

1

C598

2

1U_0402_6.3V6K

VDD_33

2A

+VDD_18

U8 W8 U6 U9 W6 T7 V7

0.15A

+VDD_18_DAC

W9

0.2A

+VDDL_10

U11

place C564 close APU ball

5.5A

+VDD_10

U13 W13 V12 T12

0.5A

A4

1

C537

C545

2

180P_0402_50V8J

1

C557

C556

2

180P_0402_50V8J

1

C565

C564

2

180P_0402_50V8J

1

C569

C1102

2

180P_0402_50V8J

1

C580

C581

2

0.1U_0402_16V7K

1

C546

C538

2

1U_0402_6.3V6K

0.1U_0402_16V7K

Change from SM010014520 to SD002000080 20100816

1

C558

2

10U_0603_6.3V6M

1U_0402_6.3V6K

1

C566

C567

2

1U_0402_6.3V6K

0.1U_0402_16V7K

1

C571

C570

2

0.1U_0402_16V7K

+3VS

1U_0402_6.3V6K

1

C547

2

1U_0402_6.3V6K

L30

FBMA-L11-201209-221LMA30T_0805

10U_0603_6.3V6M

1

C572

2

1U_0402_6.3V6K

1

C548

C549

2

1U_0402_6.3V6K

+1.0VS has been raised to +1.05VS for AMD design guide 45339_R1.02 update 20101004

1U_0402_6.3V6K

10U_0603_6.3V6M

+1.8VS

12

FBMA-L11-201209-221LMA30T_0805

1

C574

C573

2

10U_0603_6.3V6M

+1.8VS

L29

12

FBMA-L11-201209-221LMA30T_0805

Change from SM010014520 to SD002000080 20100816

+1.05VS

L31

12

L32

12

FBMA-L11-201209-221LMA30T_0805

Change from SM010014520 to SD002000080 20100816

U22D

A7

VSS_1

B7

VSS_2

B11

VSS_3

B17

VSS_4

B22

VSS_5

C4

VSS_6

D5

VSS_7

D7

VSS_8

D9

VSS_9

D11

VSS_10

D14

VSS_11

B15

VSS_12

D17

VSS_13

D19

VSS_14

E7

VSS_15

E9

VSS_16

E12

VSS_17

E20

VSS_18

F8

VSS_19

F11

VSS_20

F13

VSS_21

G4

VSS_22

G5

VSS_23

G7

VSS_24

G9

VSS_25

G12

VSS_26

G20

VSS_27

G22

VSS_28

H6

VSS_29

H11

VSS_30

H13

VSS_31

J4

VSS_32

J5

VSS_33

J7

VSS_34

J20

VSS_35

K10

VSS_36

K14

VSS_37

L4

VSS_38

L6

VSS_39

L8

VSS_40

L11

VSS_41

L13

VSS_42

L20

VSS_43

L22

VSS_44

M7

VSS_45

N4

VSS_46

N6

VSS_47

N8

VSS_48

N11

VSS_49

S IC E SERIES EME450GBB22GVA 1.65G BGA

GND

VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97

VSSBG_DAC

N13 N20 N22 P10 P14 R4 R7 R20 T6 T9 T11 T13 U4 U5 U7 U12 U20 U22 V8 V9 V11 V13 W1 W2 W4 W5 W7 W12 W20 Y5 Y7 Y9 Y11 Y13 Y15 Y17 Y19 AA4 AA22 AB2 AB5 AB9 AB13 AB17 AB21 AC5 AC9 AC13 A11

1

C599

2

1

C600

2

0.1U_0402_16V7K

1

C602

C601

0.1U_0402_16V7K

C602

2

0.1U_0402_16V7K

1

C603

2

180P_0402_50V8J

+1.5V_APU +1.5V

J15

@ J 15

@

2

112

JUMP_43X79

By case (Along split)

+1.5V_APU

A A

@

C622

Near CPU Socket

5

POWER

1

C608

1

2

4

1

+

C623

@

2

330U_2.5V_M

22U_0805_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2010/06/30 2012/06/30

Compal Secret Data

Deciphered Date

2

C608

2

0.1U_0402_16V7K

1

C610

C609

2

0.1U_0402_16V7K

Title

Size Document Number Rev

C

Date: Sheet of

1

C611

2

1

C612

C613

2

180P_0402_50V8J

Compal Electronics, Inc.

P07-FT1 PWR/VSS

LA8681P

1

C615

C614

2

180P_0402_50V8J

1.0

7 48Tuesday, November 29, 2011

1.0

5

+1.5V

JDIMM1

ME@JDIMM1

+VREF_DQ

1

C626

2

D D

DDR_A_DQS#1<6,9> DDR_A_DQS1<6,9>

DDR_A_DQS#2<6,9> DDR_A_DQS2<6,9>

C C

DDR_CS1_DIMMA#<6>

B B

A A

+3VS

DDR_A_DQS#4<6,9> DDR_A_DQS4<6,9>

DDR_A_DQS#6<6,9> DDR_A_DQS6<6,9>

C646

1

C627

2

0.1U_0402_16V4Z

DDR_CKE0<6,9>

DDR_A_BS2<6,9>

DDR_A_CLK0<6> DDR_A_CLK#0<6>

DDR_A_BS0<6,9>

DDR_A_WE#<6,9>

DDR_A_CAS#<6,9>

1

C647

2

2.2U_0603_6.3V4Z

5

1000P_0402_50V7K

0.1U_0402_16V4Z

DDR_A_D0 DDR_A_D1

DDR_A_DM0

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

DDR_A_MA10

DDR_A_MA13

DDR_A_D32 DDR_A_D33

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_DM7

DDR_A_D58 DDR_A_D59

R445 10K_0402_5%R445 10K_0402_5%

1 2

12

R446

10K_0402_5%

1 3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

73 75 77 79 81 83 85 87 89 91 93 95 97 99

101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205 207

ME@

VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS

CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST

VREF_CA VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT

GND1 BOSS1

LCN_DAN06-K4406-0103

VSS DQ4 DQ5 VSS

DQS0#

DQS0

VSS DQ6 DQ7

VSS DQ12 DQ13

VSS

DM1

RESET#

VSS DQ14 DQ15

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS

DQS3#

DQS3

VSS DQ30 DQ31

VSS

CKE1

VDD

CK1

CK1#

VDD

BA1 RAS#

VDD

ODT0

VDD ODT1

VDD

VSS DQ36 DQ37

VSS

DM4

VSS DQ38 DQ39

VSS DQ44 DQ45

VSS

DQS5#

DQS5

VSS DQ46 DQ47

VSS DQ52 DQ53

VSS

DM6

VSS DQ54 DQ55

VSS DQ60 DQ61

VSS

DQS7#

DQS7

VSS DQ62 DQ63

VSS

EVENT#

SDA

SCL

VTT

GND2

BOSS2

4

+1.5V

2

DDR_A_D4

4

DDR_A_D5

6 8 10 12 14

DDR_A_D6

16

DDR_A_D7

18 20

DDR_A_D12

22

DDR_A_D13

24 26

DDR_A_DM1

28 30 32

DDR_A_D14

34

DDR_A_D15

36 38

DDR_A_D20

40

DDR_A_D21

42 44

DDR_A_DM2

46 48

DDR_A_D22

50

DDR_A_D23

52 54

DDR_A_D28

56

DDR_A_D29

58 60 62 64 66

DDR_A_D30

68

DDR_A_D31

70 72

74 76

DDR_A_MA15

78

A15 A14

A11

A7

A6 A4

A2 A0

S0#

NC

DDR_A_MA14

80 82

DDR_A_MA11

84

DDR_A_MA7

86 88

DDR_A_MA6

90

DDR_A_MA4

92 94

DDR_A_MA2

96

DDR_A_MA0

98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206 208

DDR_A_D36 DDR_A_D37

DDR_A_DM4

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_DM6

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_D62 DDR_A_D63

4

DDR_A_DQS#0 <6,9> DDR_A_DQS0 <6,9>

DDR_RST# <6,9>

DDR_A_DQS#3 <6,9> DDR_A_DQS3 <6,9>

DDR_CKE1 <6,9>

DDR_A_CLK1 <6> DDR_A_CLK#1 <6>

DDR_A_BS1 <6,9> DDR_A_RAS# <6,9>

DDR_CS0_DIMMA# <6> DDR_A_ODT0 <6>

DDR_A_ODT1 <6>

C645

DDR_A_DQS#5 <6,9> DDR_A_DQS5 <6,9>

DDR_A_DQS#7 <6,9> DDR_A_DQS7 <6,9>

DDR_EVENT# <6,9>

FCH_SMDAT0 <9,12,29>

+0.75VS

DDR3 SO-DIMM A Reverse Type

FCH_SMCLK0 <9,12,29>

1

2

1

C644

2

1000P_0402_50V7K

0.1U_0402_16V4Z

3

DDR_A_D[0..63]

DDR_A_MA[0..15]

DDR_A_DM[0..7]

+1.5V

2

C628

1

0.1U_0402_16V4Z

+VREF_CA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/06/30 2012/06/30

0.1U_0402_16V4Z

2

C629

1

DDR_A_D[0..63] <6,9>

DDR_A_MA[0..15] <6,9>

DDR_A_DM[0..7] <6,9>

0.1U_0402_16V4Z

2

C630

1

0.1U_0402_16V4Z

Compal Secret Data

Deciphered Date

2

C631

1

2

C632

1

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

+1.5V

+VREF_DQ

2

C633

1

CRB 0.1u X1 4.7u X1

+0.75VS

1

C642

Place near JDIMM1

2

C641

2

1

0.1U_0402_16V4Z

4.7U_0603_6.3V6K

Title

Size Document Number Rev

Custom

Date: Sheet of

1

R440

R440 1K_0402_1%

1K_0402_1%

1 2

R442

R442 1K_0402_1%

1K_0402_1%

1 2

+VREF_CA

Combine to one?

CRB 100U X2

+1.5V

1

+

C643

2

SF000002Y00

Compal Electronics, Inc.

DDR3 SODIMM-I Socket

LA8681P

1

220U_6.3V_M

+1.5V

1 2

20100729

R441

R441 1K_0402_1%

1K_0402_1%

R443

R443 1K_0402_1%

1K_0402_1%

8 48Wednesday, November 30, 2011

1.0

5

4

3

2

1

DQ4 DQ5

DQ6 DQ7

DM1

DM2

A15 A14

A11

CK1

BA1

S0#

NC2

DM4

DM6

SDA SCL

+1.5V

2

DDR_A_D4

4

DDR_A_D5

6 8 10 12 14

DDR_A_D6

16

DDR_A_D7

18 20

DDR_A_D12

22

DDR_A_D13

24 26

DDR_A_DM1

28 30 32

DDR_A_D14

34

DDR_A_D15

36 38

DDR_A_D20

40

DDR_A_D21

42 44

DDR_A_DM2

46 48

DDR_A_D22

50

DDR_A_D23

52 54

DDR_A_D28

56

DDR_A_D29

58 60 62 64 66

DDR_A_D30

68

DDR_A_D31

70 72

74 76

DDR_A_MA15

78

DDR_A_MA14

80 82

DDR_A_MA11

84

DDR_A_MA7

86

A7

88

DDR_A_MA6

90

A6 A4

A2 A0

G2

DDR_A_MA4

92 94

DDR_A_MA2

96

DDR_A_MA0

98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_A_D36 DDR_A_D37

DDR_A_DM4

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_DM6

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_D62 DDR_A_D63

4

DDR_A_DQS#0 <6,8> DDR_A_DQS0 <6,8>

DDR_RST# <6,8>

DDR_A_DQS#3 <6,8> DDR_A_DQS3 <6,8>

DDR_CKE1 <6,8>

DDR_B_CLK3 <6> DDR_B_CLK#3 <6>

DDR_A_BS1 <6,8> DDR_A_RAS# <6,8>

DDR_CS0_DIMMB# <6>

DDR_B_ODT1 <6>

DIMM@

DDR_A_DQS#5 <6,8> DDR_A_DQS5 <6,8>

DDR_A_DQS#7 <6,8> DDR_A_DQS7 <6,8>

DDR_EVENT# <6,8>

FCH_SMDAT0 <8,12,29>

+0.75VS

DDR3 SO-DIMM B Reverse Type

FCH_SMCLK0 <8,12,29>

DDR_A_D[0..63]

DDR_A_MA[0..15]

DDR_A_DM[0..7]

+1.5V

0.1U_0402_16V4Z

2

DIMM@

DIMM@ 1

0.1U_0402_16V4Z

+VREF_CA

1

2

0.1U_0402_16V4Z

1

DIMM@

C666

C665

C666

2

1000P_0402_50V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

C651

C650

DIMM@

DIMM@ 1

0.1U_0402_16V4Z

2010/06/30 2012/06/30

DDR_A_D[0..63] <6,8>

DDR_A_MA[0..15] <6,8>

DDR_A_DM[0..7] <6,8>

0.1U_0402_16V4Z

2

DIMM@

DIMM@ 1

Compal Secret Data

C652

Deciphered Date

DIMM@

DIMM@ 1

C653

0.1U_0402_16V4Z

2

C654

DIMM@

DIMM@ 1

0.1U_0402_16V4Z

2

C655

DIMM@

DIMM@ 1

2

CRB 0.1u X1 4,7uX1

+0.75VS

1

2

C664

C663

2

DIMM@

Place near JDIMM2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

1

DIMM@

0.1U_0402_16V4Z

4.7U_0603_6.3V6K

DDR3 SODIMM-II Socket

LA8681P

9 48Wednesday, November 30, 2011

1

1.0

+1.5V

JDIMM2

ME@

+VREF_DQ

1

DIMM@

C649

DIMM@ C648

DIMM@

D D

C C

B B

For DRAM strap pin reservation 20100817

+3VS

A A

C648

2

0.1U_0402_16V4Z

DDR_A_DQS#1<6,8> DDR_A_DQS1<6,8>

DDR_A_DQS#2<6,8> DDR_A_DQS2<6,8>

DDR_CKE0<6,8>

DDR_A_BS2<6,8>

DDR_B_CLK2<6> DDR_B_CLK#2<6>

DDR_A_BS0<6,8>

DDR_A_WE#<6,8>

DDR_A_CAS#<6,8> DDR_B_ODT0 <6>

DDR_CS1_DIMMB#<6>

DDR_A_DQS#4<6,8> DDR_A_DQS4<6,8>

DDR_A_DQS#6<6,8> DDR_A_DQS6<6,8>

DIMM@

R961 10K_0402_5%

1 2

1

C667

2.2U_0603_6.3V4Z

DIMM@

2

CRB only one 4.7k

5

1

2

1000P_0402_50V7K

1

C668

2

0.1U_0402_16V4Z

DDR_A_D0 DDR_A_D1

DDR_A_DM0

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

DDR_A_MA10

DDR_A_MA13

DDR_A_D32 DDR_A_D33

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5

DDR_A_D42 DDR_A_D43

DDR_A_D48

DDR_A_D49

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_DM7

DDR_A_D58 DDR_A_D59

DIMM@

R962

10K_0402_5%

1 2

For DRAM strap pin reservation 20100817

11 13 15 17 19 21 23 25 27

33 35

39 41

45 47 49 51 53 55 57 59

63

67 69

73 75 77 79 81 83 85 87 89 91 93 95 97

99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205

ME@

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS129RESET# VSS1131VSS12 DQ10 DQ11 VSS1337VSS14 DQ16 DQ17 VSS1543VSS16 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS2261DQS#3 DM3 VSS2365VSS24 DQ26 DQ27 VSS2571VSS26

CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST

VREF_CA VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1

G1

LCN_DAN06-K4806-0103

VSS3

DQS#0

DQS0 VSS6

VSS8 DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VSS28

DQ36 DQ37

VSS30

VSS31

DQ38 DQ39

VSS33

DQ44

DQ45 VSS35 DQS#5

DQS5 VSS38

DQ46

DQ47 VSS40

DQ52

DQ53 VSS42

VSS43

DQ54

DQ55 VSS45

DQ60

DQ61 VSS47 DQS#7

DQS7 VSS50

DQ62

DQ63 VSS52

EVENT#

VTT2

A

C146 150P_0402_50V8JC146 150P_0402_50V8J

+VDDAN_11_PCIE

PCIE_FTX_C_DRX_N0<25> PCIE_FTX_C_DRX_P1<29> PCIE_FTX_C_DRX_N1<29>

PCIE_FRX_DTX_P0<25> PCIE_FRX_DTX_N0<25> PCIE_FRX_DTX_P1<29> PCIE_FRX_DTX_N1<29>

+1.1VS_CKVDD

CLK_PCIE_VGA<15> CLK_PCIE_VGA#<15>

CLK_PCIE_WLAN<29> CLK_PCIE_WLAN#<29>

CLK_PCIE_LAN<25> CLK_PCIE_LAN#<25>

1

2

1 2

UMI_RX0P<6> UMI_RX0N<6> UMI_RX1P<6> UMI_RX1N<6> UMI_RX2P<6> UMI_RX2N<6> UMI_RX3P<6> UMI_RX3N<6>

UMI_TX0P<6> UMI_TX0N<6 > UMI_TX1P<6> UMI_TX1N<6 > UMI_TX2P<6> UMI_TX2N<6 > UMI_TX3P<6> UMI_TX3N<6 >

C158

22P_0402_50V8J

20M_0402_5%

C159

22P_0402_50V8J

PLT_RST#

C147 0.1U_0402_16V7KC147 0.1U_0402_16V7K C148 0.1U_0402_16V7KC148 0.1U_0402_16V7K C149 0.1U_0402_16V7KC149 0.1U_0402_16V7K C150 0.1U_0402_16V7KC150 0.1U_0402_16V7K C151 0.1U_0402_16V7KC151 0.1U_0402_16V7K C152 0.1U_0402_16V7KC152 0.1U_0402_16V7K C153 0.1U_0402_16V7KC153 0.1U_0402_16V7K C154 0.1U_0402_16V7KC154 0.1U_0402_16V7K

R94 590_0402_1%R94 590_0402_1% R88 2K_0402_1%R88 2K_0402_1%

C718 0.1U_0402_16V7KC718 0.1U_0402_16V7K C720 0.1U_0402_16V7KC720 0.1U_0402_16V7K C721 0.1U_0402_16V7KC721 0.1U_0402_16V7K C719 0.1U_0402_16V7KC719 0.1U_0402_16V7K

R95 2K_0402_1%R95 2K_0402_1%

R98 0_0402_5%R98 0_0402_5% R99 0_0402_5%R99 0_0402_5%

R102 0_0402_5%R102 0_0402_5% R103 0_0402_5%R103 0_0402_5%

R100 0_0402_5%R100 0_0402_5% R101 0_0402_5%R101 0_0402_5%

1 2

12

R107

1 2

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2

1 2

C146 place close to FCH

1 1

LAN

WLAN

2 2

VGA

WLAN

3 3

25M_X1

25M_X2

4 4

C157

22P_0402_50V8J

LAN

1 2

R106 1M_0402_5%R106 1M_0402_5%

3

2

25MHZ_20PF_FSX3M-25.M20FDO

1

2

OSC

NC

Y4

A

4

NC

1

OSC

22P_0402_50V8J

C155

B

T101T101

APU_DISP_CLK<5>

APU_DISP_CLK#<5>

B

APU_PCIE_RST#_C

PCIE_FTX_DRX_P0 PCIE_FTX_DRX_N0 PCIE_FTX_DRX_P1 PCIE_FTX_DRX_N1

APU_CLK<5>

APU_CLK#<5>

CLK_PCIE_VGA_R CLK_PCIE_VGA#_R

CLK_PCIE_WLAN_R CLK_PCIE_WLAN#_R

CLK_PCIE_LAN_R CLK_PCIE_LAN#_R

22_0402_5%

R559

1 2

32K_X1

32K_X2

R557 33_0402_5%R557 33_0402_5%

1 2

1 2 1 2 1 2 1 2

1 2 1 2

Y1

32.768KHZ_12.5PF_CM31532768DZFT

1 2

A_RST#

UMI_RXP0_C UMI_RXN0_C UMI_RXP1_C UMI_RXN1_C UMI_RXP2_C UMI_RXN2_C UMI_RXP3_C UMI_RXN3_C

PCIE_CALRP PCIE_CALRN

@

CLK_CALRN

25M_X1

25M_X2

C

U2A

HUDSON-2

AE2

PCIE_RST#

AD5

A_RST#

AE30

UMI_TX0P

AE32

UMI_TX0N

AD33

UMI_TX1P

AD31

UMI_TX1N

AD28

UMI_TX2P

AD29

UMI_TX2N

AC30

UMI_TX3P

AC32

UMI_TX3N

AB33

UMI_RX0P

AB31

UMI_RX0N

AB28

UMI_RX1P

AB29

UMI_RX1N

Y33

UMI_RX2P

Y31

UMI_RX2N

Y28

UMI_RX3P

Y29

UMI_RX3N

AF29

PCIE_CALRP

AF31

PCIE_CALRN

V33

GPP_TX0P

V31

GPP_TX0N

W30

GPP_TX1P

W32

GPP_TX1N

AB26

GPP_TX2P

AB27

GPP_TX2N

AA24

GPP_TX3P

AA23

GPP_TX3N

AA27

GPP_RX0P

AA26

GPP_RX0N

W27

GPP_RX1P

V27

GPP_RX1N

V26

GPP_RX2P

W26

GPP_RX2N

W24

GPP_RX3P

W23

GPP_RX3N

F27

CLK_CALRN

G30

PCIE_RCLKP

G28

PCIE_RCLKN

R26

DISP_CLKP

T26

DISP_CLKN

H33

DISP2_CLKP

H31

DISP2_CLKN

T24

APU_CLKP

T23

APU_CLKN

J30

SLT_GFX_CLKP

K29

SLT_GFX_CLKN

H27

GPP_CLK0P

H28

GPP_CLK0N

J27

GPP_CLK1P

K26

GPP_CLK1N

F33

GPP_CLK2P

F31

GPP_CLK2N

E33

GPP_CLK3P

E31

GPP_CLK3N

M23

GPP_CLK4P

M24

GPP_CLK4N

M27

GPP_CLK5P

M26

GPP_CLK5N

N25

GPP_CLK6P

N26

GPP_CLK6N

R23

GPP_CLK7P

R24

GPP_CLK7N

N27

GPP_CLK8P

R27

GPP_CLK8N

J26

14M_25M_48M_OSC

C31

25M_X1

C33

25M_X2

S IC 218-0755091 A13 HUDSON-M3L FCBGA 656P C38

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HUDSON-2

PCICLK1/GPO36 PCICLK2/GPO37

PCI CLKS

PCI EXPRESS INTERFACES

PCI INTERFACE

CLOCK GENERATOR

LPCAPUS5 PLUS

C

PCICLK3/GPO38

PCICLK4/14M_OSC/GPO39

AD10/GPIO10 AD11/GPIO11 AD12/GPIO12 AD13/GPIO13 AD14/GPIO14 AD15/GPIO15 AD16/GPIO16 AD17/GPIO17 AD18/GPIO18 AD19/GPIO19 AD20/GPIO20 AD21/GPIO21 AD22/GPIO22 AD23/GPIO23 AD24/GPIO24 AD25/GPIO25 AD26/GPIO26 AD27/GPIO27 AD28/GPIO28 AD29/GPIO29 AD30/GPIO30 AD31/GPIO31

REQ1#/GPIO40 REQ2#/CLK_REQ8#/GPIO41 REQ3#/CLK_REQ5#/GPIO42

GNT1#/GPO44

GNT2#/SD_LED/GPO45

GNT3#/CLK_REQ7#/GPIO46

INTE#/GPIO32

INTF#/GPIO33 INTG#/GPIO34 INTH#/GPIO35

LDRQ1#/CLK_REQ6#/GPIO49

SERIRQ/GPIO48

DMA_ACTIVE#

S5_CORE_EN

INTRUDER_ALERT#

VDDBT_RTC_G

2011/10/12 2013/10/12

PCICLK0

PCIRST#

AD0/GPIO0 AD1/GPIO1 AD2/GPIO2 AD3/GPIO3 AD4/GPIO4 AD5/GPIO5 AD6/GPIO6 AD7/GPIO7 AD8/GPIO8 AD9/GPIO9

CBE0# CBE1# CBE2# CBE3#

FRAME#

DEVSEL#

IRDY#

TRDY#

PAR STOP# PERR# SERR# REQ0#

GNT0#

CLKRUN#

LOCK#

LPCCLK0

LPCCLK1

LAD0 LAD1 LAD2 LAD3

LFRAME#

LDRQ0#

PROCHOT#

APU_PG

LDT_STP#

APU_RST#

RTCCLK

32K_X1

32K_X2

Compal Secret Data

AF3 AF1 AF5 AG2 AF6

AB5

AJ3 AL5 AG4 AL6 AH3 AJ5 AL1 AN5 AN6 AJ1 AL8 AL3 AM7 AJ6 AK7 AN8 AG9 AM11 AJ10 AL12 AK11 AN12 AG12 AE12 AC12 AE13 AF13 AH13 AH14 AD15 AC15 AE16 AN3 AJ8 AN10 AD12 AG10 AK9 AL10 AF10 AE10 AH1 AM9 AH8 AG15 AG13 AF15 AM17 AD16 AD13 AD21 AK17 AD19 AH9

AF18 AE18 AC16 AD18

B25

D25 D27 C28 A26 A29 A31 B27 AE27 AE19

G25 E28 E26 G26 F26

H7 F1 F3 E6

G2

G4

APU_PCIE_RST#_C

Module design have reserve GPIO44,45 for VGA power enable and reset

R558 22_0402_5%R558 22_0402_5%

1 2

APU_PROCHOT#_R

32K_X1

32K_X2

Deciphered Date

D

PCI_CLK1 <14>

PCI_CLK3 <14> PCI_CLK4 <14>

APU_PCIE_RST #: Reset PCIE device on APU

MC74VHC1G08DFT2G SC70 5P

R692

@R692

@

1 2

33_0402_5%

C790

150P_0402_50V8J

12

1

@

2

@

R693

8.2K_0402_5%

R692/ C790 close to FCH

PCI_AD23 <14> PCI_AD24 <14> PCI_AD25 <14> PCI_AD26 <14> PCI_AD27 <14>

T14T14

T99T99

LPC_CLK1 <14> LPC_AD0 <29,30> LPC_AD1 <29,30> LPC_AD2 <29,30> LPC_AD3 <29,30> LPC_FRAME# <29,30>

SERIRQ <30>

R15 0_0402_5%@R15 0_0402_5%@

1 2

APU_PWRGD <5,44>

APU_RST# <5>

T100T100

RTC_CLK <14,30>

CLK_PCI_EC <14,30>

1U_0402_6.3V6K

D

@

1 2

R670

0_0402_5%

change to 510 Ohm

W=20mils

1

C156

2

1 2

R105 510_0402_5%R105 510_0402_5%

Size Document Number Rev

Custom

Date: Sheet of

Title

+3VALW

2

1

1 2

0_0402_5%

E

C789

@C789

@

1 2

0.1U_0402_16V4Z

5

P

B

4

Y

A

G

U43

3

@

R695

@R695

@

CLK_PCI_DB <29>

ALLOW_STOP# <5> H_PROCHOT# <5,30,37>

+RTCBATT

12

CLRP1 SHORT PADS

SHORT PADS

@CLRP1

@

1 2

R866

R866 0_0402_5%

0_0402_5%

APU_PCIE_RST# <15,29>

PLT_RST# <25,30>PCIE_FTX_C_DRX_P0<25>

for Clear CMOS

Compal Electronics, Inc.

FCH PCIE/CLK/PCI/LPC/RTC

LA8681P

E

0.1

10 48Wednesday, November 30, 2011

0.1

A

B

C

D

E

4MB SPI ROM & Non-share ROM.

+3VALW

1 2

SPI_WP#_R

3.3K_0402_5%

SPI_HOLD#

U4

1

CS#

2

SO/SIO1

3 4

HOLD# WP# GND

SI/SIO0

W25Q32BVSSIG SOIC 8

VCC

SCLK

+3VALW

8

SPI_HOLD#

7

SPI_CLK_FCH

6

SPI_SI

5

GBE_PHY_INTR

0.1U_0402_16V4Z

0.1U_0402_16V4Z C165

C165

1 2

R110

0_0402_5%

1 2 1 2

33_0402_5%

R119

R110 place close to FCH

R121 10K_0402_5%R121 10K_0402_5%

1 2

R112

U2B

1 1

HDD

ODD

SATA_FTX_C_DRX_P0<28> SATA_FTX_C_DRX_N0<28>

SATA_FRX_C_DTX_N0<28> SATA_FRX_C_DTX_P0<28>

SATA_FTX_C_DRX_P1<28> SATA_FTX_C_DRX_N1<28>

SATA_FRX_C_DTX_N1<28> SATA_FRX_C_DTX_P1<28>

FCH-M3L NC pin

2 2

SATA_CALRP

R1281K_0402_1% R1281K_0402_1%

12

SATA_CALRN

R130931_0402_1% R130931_0402_1%

+AVDD_SATA

+3VS

3 3

BT_DISABLE#<29>

4 4

12

R13310K_0402_5% @ R13310K_0402_5% @

1 2

BT_ON#<28>

WL_OFF#<29>

ODD_EN<28>

1 2

R146 10K_0402_5%R146 10K_0402_5%

1 2

R149 10K_0402_5%R149 10K_0402_5%

1 2

R151 10K_0402_5%R151 10K_0402_5%

T48T48

U2B

AK19

SATA_TX0P

AM19

SATA_TX0N

AL20

SATA_RX0N

AN20

SATA_RX0P

AN22

SATA_TX1P

AL22

SATA_TX1N

AH20

SATA_RX1N

AJ20

SATA_RX1P

AJ22

SATA_TX2P

AH22

SATA_TX2N

AM23

SATA_RX2N

AK23

SATA_RX2P

AH24

SATA_TX3P

AJ24

SATA_TX3N

AN24

SATA_RX3N

AL24

SATA_RX3P

AL26

SATA_TX4P

AN26

SATA_TX4N

AJ26

SATA_RX4N

AH26

SATA_RX4P

AN29

SATA_TX5P

AL28

SATA_TX5N

AK27

SATA_RX5N

AM27

SATA_RX5P

AL29

NC6

AN31

NC7

AL31

NC8

AL33

NC9

AH33

NC10

AH31

NC11

AJ33

NC12

AJ31

NC13

AF28

SATA_CALRP

AF27

SATA_CALRN

AD22

SATA_ACT#/GPIO67

AF21

SATA_X1

AG21

SATA_X2

AH16

FANOUT0/GPIO52

AM15

FANOUT1/GPIO53

AJ16

FANOUT2/GPIO54

AK15

FANIN0/GPIO56

AN16

FANIN1/GPIO57

AL16

FANIN2/GPIO58

K6

TEMPIN0/GPIO171

K5

TEMPIN1/GPIO172

K3

TEMPIN2/GPIO173

M6

TEMPIN3/TALERT#/GPIO174

HUDSON-2

SERIAL ATA

HW MONITOR

SD_CLK/SCLK_2/GPIO73

SD_CMD/SLOAD_2/GPIO74

SD_DATA0/SDATI_2/GPIO77

SD_DATA1/SDATO_2/GPIO78

SD CARDGBE LANSPI ROMVGA DACVGA MAINLINK

SD_DATA2/GPIO79 SD_DATA3/GPIO80

GBE_RXCTL/RXDV

GBE_TXCTL/TXEN

GBE_PHY_RST#

GBE_PHY_INTR

SPI_DI/GPIO164

SPI_DO/GPIO163

SPI_CLK/GPIO162

SPI_CS1#/GPIO165

ROM_RST#/SPI_WP#/GPIO161

VGA_HSYNC/GPO68 VGA_VSYNC/GPO69

VGA_DDC_SDA/GPO70

VGA_DDC_SCL/GPO71

VGA_DAC_RSET

AUX_VGA_CH_P AUX_VGA_CH_N

ML_VGA_HPD/GPIO229

VIN2/SDATI_1/GPIO177

VIN3/SDATO_1/GPIO178

VIN4/SLOAD_1/GPIO179

VIN5/SCLK_1/GPIO180

VIN6/GBE_STAT3/GPIO181

VIN7/GBE_LED3/GPIO182

SD_CD/GPIO75 SD_WP/GPIO76

GBE_RXCLK

GBE_RXERR

GBE_TXCLK

GBE_PHY_PD

VGA_GREEN

ML_VGA_L0P ML_VGA_L0N ML_VGA_L1P ML_VGA_L1N ML_VGA_L2P ML_VGA_L2N ML_VGA_L3P ML_VGA_L3N

VIN0/GPIO175

VIN1/GPIO176

GBE_COL GBE_CRS

GBE_MDCK

GBE_MDIO

GBE_RXD3 GBE_RXD2 GBE_RXD1 GBE_RXD0

GBE_TXD3 GBE_TXD2 GBE_TXD1 GBE_TXD0

VGA_RED

VGA_BLUE

AUXCAL

NC1 NC2 NC3 NC4 NC5

AL14 AN14 AJ12 AH12 AK13 AM13 AH15 AJ14

AC4 AD3 AD9 W10 AB8 AH7 AF7 AE7 AD7 AG8 AD1 AB7 AF9 AG6 AE8 AD8 AB9 AC2 AA7

GBE_PHY_INTR

W9

SPI_SO_R

V6

SPI_SI_R

V5

SPI_CLK_FCH_R

V3

SPI_SB_CS0#_R

T6

SPI_WP#

V1

L30

L32

M29

M28 N30

M33 N32

K31

V28 V29

U28

T31 T33 T29 T28 R32 R30 P29 P28

C29

N2

M3

L2

N4

P1

P3

M1

M5

AG16 AH10 A28 G27 L4

FCH-M3L NC pin

1 2

R137 10K_0402_5%R137 10K_0402_5%

1 2

R138 10K_0402_5%R138 10K_0402_5%

1 2

R139 10K_0402_5%R139 10K_0402_5%

1 2

R148 10K_0402_5%R148 10K_0402_5%

Need to enable internal pull down to le ave unconnected

R115

0_0402_5%

SPI_SB_CS0#_R SPI_SO_R SPI_SO_L

SPI_WP#

0_0402_5%

1 2 1 2

33_0402_5%

R117

R117 R116

R116

0_0402_5%

1 2

R112

R108 10K_0402_5%R108 10K_0402_5%

SPI_SB_CS0#

SPI_WP#_R

SPI_CLK_FCH

33_0402_5%

22P_0402_50V8J

SPI_CLK_FCH_R SPI_SI_R

R111

@

C160

@

+3VALW

12

S IC 218-0755091 A13 HUDSON-M3L FCBGA 656P C38

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/10/12 2013/10/12

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

FCH SATA/SPI/VGA/HWM/SD

LA8681P

11 48Wednesday, November 30, 2011

E

0.1

A

1 1

+3VALW

For FCH internal debug use

R179 2.2K_0402_5%@R179 2.2K_0402_5%@

1 2

R181 2.2K_0402_5%@R181 2.2K_0402_5%@

1 2

R183 2.2K_0402_5%@R183 2.2K_0402_5%@

2 2

+3VALW

3 3

+3VS

4 4

1 2

R883 10K_0402_5%@R883 10K_0402_ 5%@

1 2

R624 10K_0402_5%R624 10K_0402_5%

1 2

R625 10K_0402_5%R625 10K_0402_5%

1 2

R174 10K_0402_5%R174 10K_0402_5%

1 2

R618 10K_0402_5%@R618 10K_0402_ 5%@

1 2

R649 10K_0402_5%@R649 10K_0402_ 5%@

1 2

R620 10K_0402_5%@R620 10K_0402_ 5%@

1 2

R163 10K_0402_5%@R163 10K_0402_ 5%@

1 2

R164 10K_0402_5%@R164 10K_0402_ 5%@

1 2

R169 100K_0402_5%@R169 100K_0402_5%@

1 2

R170 10K_0402_5%@R170 10K_0402_ 5%@

1 2

R171 2.2K_0402_5%R171 2.2K_0402_5%

1 2

R172 2.2K_0402_5%R172 2.2K_0402_5%

1 2

R175 10K_0402_5%R175 10K_0402_5%

1 2

R173 8.2K_0402_5%R173 8.2K_0402_5%

1 2

R176 8.2K_0402_5%R176 8.2K_0402_5%

1 2

R166 10K_0402_5%R166 10K_0402_5%

1 2

R168 10K_0402_5%R168 10K_0402_5%

1 2

R177 2.2K_0402_5%R177 2.2K_0402_5%

1 2

R178 10K_0402_5%@R178 10K_0402_5%@

1 2

R180 10K_0402_5%@R180 10K_0402_5%@

1 2

R182 10K_0402_5%PX@R182 10K_0402_5%PX@

1 2

ODD_DA#_FCH

ODD_DETECT#

H_THERMTRIP#

EC_LID_OUT#

FCH_PCIE_WAKE#

FCH_SMCLK0

FCH_SMDAT0

WD_PWRGD

WLAN_CLKREQ#

LAN_CLKREQ#

FCH_SMCLK1

FCH_SMDATA1

EC_RSMRST#

HDA_BITCLK

HDA_SDIN0

PEG_CLKREQ#_R

A

TEST0

TEST1

TEST2

USB_OC7#

USB_OC2#

USB_OC1#

USB_OC0#

USB_OC5#

USB_OC3#

PEG_CLKREQ#<16>

HDA_BITCLK_AUDIO<27> HDA_SDOUT_AUDIO<27>

HDA_SDIN0<27>

HDA_SYNC_AUDIO<27>

HDA_RST_AUDIO#<27>

PXS_RST#<15> PXS_PWREN<17,43>

VGA_GATE#<30>

+3VALW+3VALW

12

UMA@

12

PX@

R684

R685

10K_0402_5%

GPIO189 GPIO190

12

PX@

R682

R683

10K_0402_5%

B

PCIE_RST2 : Reset PCIE device on Hudson 3

EC_LID_OUT#<30>

PM_SLP_S3#<30> PM_SLP_S5#<30> PBTN_OUT#<30>

FCH_PWRGD<30,44>

GATEA20<30>

KBRST#<30> EC_SCI#<30> EC_SMI#<30>

R155 10K_0402_5%@R155 10K_0402_5%@

1 2

FCH_PCIE_WAKE#<25,29>

H_THERMTRIP#<5>

EC_RSMRST#<30>

LAN_CLKREQ#<25>

FCH_SPKR<27> FCH_SMCLK0<8,9,29> FCH_SMDAT0<8,9,29>

WLAN_CLKREQ#<29>

VGA_PWRGD<15,17,43>

R156 0_0402_5%@R156 0_0402_5%@

ODD_DA#_FCH<28>

ODD_DETECT#<28>

USB_OC2#<32> USB_OC1#<33> USB_OC0#<34>

R159 33_0402_5%R159 33_0402_5% R160 33_0402_5%R160 33_0402_5%

R161 33_0402_5%R161 33_0402_5% R162 33_0402_5%R162 33_0402_5%

2

G

BOARD Config.

GPIO189 GPIO190

1 2 1 2

13

D

S

0 0

12

12 12

PX@

Q112

2N7002K_SOT23-3

FCH_PWRGD

1 1

B

TEST0 TEST1 TEST2

SYS_RESET#

WD_PWRGD

FCH_SMCLK0 FCH_SMDAT0 FCH_SMCLK1 FCH_SMDATA1

PEG_CLKREQ#_R

USB_OC7#

USB_OC5#

USB_OC3# USB_OC2# USB_OC1# USB_OC0#

R960_0402_5% PX@ R960_0402_5% PX@ R970_0402_5% PX@ R970_0402_5% PX@

10

01

T17T17

HDA_BITCLK HDA_SDOUT HDA_SDIN0

HDA_SYNC HDA_RST#

T61T61 T19T19

GPIO189 GPIO190

Function

PX4 Full

PX4 low

UMA Low

UMA Full

C

U2D

HUDSON-2

AB6

PCIE_RST2#/PCI_PME#/GEVENT4#

R2

RI#/GEVENT22#

W7

SPI_CS3#/GBE_STAT1/GEVENT21#

T3

SLP_S3#

W2

SLP_S5#

J4

PWR_BTN#

N7

PWR_GOOD

T9

TEST0

T10

TEST1/TMS

V9

TEST2

AE22

GA20IN/GEVENT0#

AG19

KBRST#/GEVENT1#

R9

LPC_PME#/GEVENT3#

C26

LPC_SMI#/GEVENT23#

T5

LPC_PD#/GEVENT5#

U4

SYS_RESET#/GEVENT19#

K1

WAKE#/GEVENT8#

V7

IR_RX1/GEVENT20#

R10

THRMTRIP#/SMBALERT#/GEVEN T2#

AF19

WD_PWRGD

U2

RSMRST#

AG24

CLK_REQ4#/SATA_IS0#/GPIO64

AE24

CLK_REQ3#/SATA_IS1#/GPIO63

AE26

SMARTVOLT1/SATA_IS2#/GPIO50

AF22

CLK_REQ0#/SATA_IS3#/GPIO60

AH17

SATA_IS4#/FANOUT3/GPIO55

AG18

SATA_IS5#/FANIN3/GPIO59

AF24

SPKR/GPIO66

AD26

SCL0/GPIO43

AD25

SDA0/GPIO47

T7

SCL1/GPIO227

R7

SDA1/GPIO228

AG25

CLK_REQ2#/FANIN4/GPIO62

AG22

CLK_REQ1#/FANOUT4/GPIO61

J2

IR_LED#/LLB#/GPIO184

AG26

SMARTVOLT2/SHUTDOWN #/GPIO51

V8

DDR3_RST#/GEVENT7#/VGA_PD

W8

GBE_LED0/GPIO183

Y6

SPI_HOLD#/GBE_LED1/GEVENT9#

V10

GBE_LED2/GEVENT10#

AA8

GBE_STAT0/GEVENT11#

AF25

CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#

M7

BLINK/USB_OC7#/GEVENT18#

R8

USB_OC6#/IR_TX1/GEVENT6#

T1

USB_OC5#/IR_TX0/GEVENT17#

P6

USB_OC4#/IR_RX0/GEVENT16#

F5

USB_OC3#/AC_PRES/TDO/GEVENT15#

P5

USB_OC2#/TCK/GEVENT14#

J7

USB_OC1#/TDI/GEVENT13#

T8

USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12 #

AB3

AZ_BITCLK

AB1

AZ_SDOUT

AA2

AZ_SDIN0/GPIO167

Y5

AZ_SDIN1/GPIO168

Y3

AZ_SDIN2/GPIO169

Y1

AZ_SDIN3/GPIO170

AD6

AZ_SYNC

AE4

AZ_RST#

K19

PS2_DAT/SDA4/GPIO187

J19

PS2_CLK/CEC/SCL4/GPIO188

J21

SPI_CS2#/GBE_STAT2/GPIO166

D21

PS2KB_DAT/GPIO189

C20

PS2KB_CLK/GPIO190

D23

PS2M_DAT/GPIO191

C22

PS2M_CLK/GPIO192

F21

KSO_0/GPIO209

E20

KSO_1/GPIO210

F20

KSO_2/GPIO211

A22

KSO_3/GPIO212

E18

KSO_4/GPIO213

A20

KSO_5/GPIO214

J18

KSO_6/GPIO215

H18

KSO_7/GPIO216

G18

KSO_8/GPIO217

B21

KSO_9/GPIO218

K18

KSO_10/GPIO219

D19

KSO_11/GPIO220

A18

KSO_12/GPIO221

C18

KSO_13/GPIO222

B19

KSO_14/GPIO223

B17

KSO_15/GPIO224

A24

KSO_16/GPIO225

D17

KSO_17/GPIO226

S IC 218-0755091 A13 HUDSON-M3L FCBGA 656P C38

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

HUDSON-2

EMBEDDED CTRL

2011/10/12 2013/10/12

USBCLK/14M_25M_48M_OSC

USB MISCUSB 1.1USB 2.0USB 3.0

USB_FSD1P/GPIO186

USB_FSD0P/GPIO185

USB OC GPIO ACPI / WAKE UP EVENTSHD AUDIO

SCL3_LV/GPIO195

SDA3_LV/GPIO196 EC_PWM0/EC_TIMER 0/GPIO197 EC_PWM1/EC_TIMER 1/GPIO198

EC_PWM2/EC_TIMER 2/WOL_EN/GPIO199

EC_PWM3/EC_TIMER 3/GPIO200

Compal Secret Data

Deciphered Date

USB_RCOMP

USB_FSD1N

USB_FSD0N

USB_HSD13P USB_HSD13N

USB_HSD12P USB_HSD12N

USB_HSD11P USB_HSD11N

USB_HSD10P USB_HSD10N

USB_HSD9P USB_HSD9N

USB_HSD8P USB_HSD8N

USB_HSD7P USB_HSD7N

USB_HSD6P USB_HSD6N

USB_HSD5P USB_HSD5N

USB_HSD4P USB_HSD4N

USB_HSD3P USB_HSD3N

USB_HSD2P USB_HSD2N

USB_HSD1P USB_HSD1N

USB_HSD0P USB_HSD0N

USBSS_CALRP USBSS_CALRN

USB_SS_TX3P USB_SS_TX3N

USB_SS_RX3P USB_SS_RX3N

USB_SS_TX2P USB_SS_TX2N

USB_SS_RX2P USB_SS_RX2N

USB_SS_TX1P USB_SS_TX1N

USB_SS_RX1P USB_SS_RX1N

USB_SS_TX0P USB_SS_TX0N

USB_SS_RX0P USB_SS_RX0N

SCL2/GPIO193 SDA2/GPIO194

KSI_0/GPIO201 KSI_1/GPIO202 KSI_2/GPIO203 KSI_3/GPIO204 KSI_4/GPIO205 KSI_5/GPIO206 KSI_6/GPIO207 KSI_7/GPIO208

D

G8

B9

H1 H3

H6 H5

H10 G10

K10 J12

G12 F12

K12 K13

B11 D11

E10 F10

C10 A10

H9 G9

A8 C8

F8 E8

C6 A6

C5 A5

C1 C3

E1 E3

C16 A16

A14 C14

C12 A12

D15 B15

E14 F14

F15 G15

H13 G13

J16 H16

J15 K15

H19 G19 G22 G21 E22 H22 J22 H21

K21 K22 F22 F24 E24 B23 C24 F18

D

USB_RCOMP

R154 11.8K_0402_1%R154 11.8K_0402_1%

1 2

FCH-M3L NC pin

USB30_P11 <34> USB30_N11 <34>

USB30_P10 <34> USB30_N10 <34>

FCH-M3L NC pin

USB20_P6 <28> USB20_N6 <28>

USB20_P5 <32> USB20_N5 <32>

FCH-M3L NC pin

USB20_P3 <22> USB20_N3 <22>

USB20_P2 <29> USB20_N2 <29>

USB20_P1 <32> USB20_N1 <32>

USB20_P0 <33>

USBSS_CALRP USBSS_CALRN

USB20_N0 <33>

R864 1K_0402_1%R864 1K _0402_1%

1 2

R865 1K_0402_1%R865 1K _0402_1%

1 2

FCH-M3L NC pin

USB30_FTX_DRX_P1 USB30_FTX_DRX_N1

USB30_FRX_DTX_P1 USB30_FRX_DTX_N1

USB30_FTX_DRX_P0 USB30_FTX_DRX_N0

USB30_FRX_DTX_P0 USB30_FRX_DTX_N0

R165 10K_0402_5%R165 10K_0402_5%

1 2

R167 10K_0402_5%R167 10K_0402_5%

1 2

R227 10K_0402_5%R227 10K_0402_5%

1 2

R228 10K_0402_5%R228 10K_0402_5%

1 2

EC_PWM2

Title

Size Document Number Rev

Custom

Date: Sheet of

E

LP2

LP1

BT

CR

CMOS

WLAN

RP2

RP1

+FCH_VDD_11_SSUSB_S

USB30_FTX_DRX_P1 <34> USB30_FTX_DRX_N1 <34>

USB30_FRX_DTX_P1 <34> USB30_FRX_DTX_N1 <34>

USB30_FTX_DRX_P0 <34> USB30_FTX_DRX_N0 <34>

USB30_FRX_DTX_P0 <34> USB30_FRX_DTX_N0 <34>

EC_PWM2 <14>

strap pin

Compal Electronics, Inc.

FCH-ACPI/USB/HDA/GPIO

LA8681P

E

Root

12 48Wednesday, November 30, 2011

LP2

LP1

0.1

A

B

C

D

E

+3VS

1 1

del +VDDPL_33_MLDAC power plane

L4

1 2

MBK1608221YZF_2P

220 ohm

+VDDPL_33_SYS

C181

2.2U_0402_6.3V6M

C181

2.2U_0402_6.3V6M

C182

1

2

0.1U_0402_16V7K

1

2

+3VS

1 2

R185 0_0603_5%R185 0_0603_5%

C176

1

2

+VDDPL_33_SYS

22U_0603_6.3V6M

0.1U_0402_16V7K

C178

1

2

+VDDIO_33_PCIGP

0.1U_0402_16V7K

C187

C179

1

2

demo board connect to GND

VDDPL_33_SSUSB_S For Hudson3 USB3.0 only For Hudson2, connect to GND

LDO_CAP: Internally generated 1.8V supply for the RGB outputs

del +FCH_VDDAN_33_DAC power plane

2 2

+3VALW

+VDDAN_33_USB

3 3

+3VS

4 4

L6

1 2

MBK1608221YZF_2P

220 ohm

L7

1 2

MBK1608221YZF_2P

220 ohm

L10

1 2

MBK1608221YZF_2P

220 ohm

L12

1 2

MBK1608221YZF_2P

220 ohm

+VDDPL_33_SSUSB_S

C198

2.2U_0402_6.3V6M

C198

2.2U_0402_6.3V6M

1

2

+VDDPL_33_USB_S

C210

2.2U_0402_6.3V6M

C210

2.2U_0402_6.3V6M

1

2

+VDDPL_33_PCIE

+VDDPL_33_SATA

A

C200

0.1U_0402_16V7K

C200

0.1U_0402_16V7K

1

2

C211

0.1U_0402_16V7K

C211

0.1U_0402_16V7K

1

2

C218

2.2U_0402_6.3V6M

C218

2.2U_0402_6.3V6M

1

2

C227

2.2U_0402_6.3V6M

C227

2.2U_0402_6.3V6M

1

2

demo board connect to GND

+3VALW

FBMA-L11-201209-221LMA30T_0805

+1.1VALW

MBK1608221YZF_2P

+1.1VALW

MBK1608221YZF_2P

L15

+1.1VALW

FBMA-L11-201209-221LMA30T_0805

L15

42 ohm/4A

+VDDPL_33_USB_S

+VDDPL_33_PCIE

+VDDPL_33_SATA

L8

1 2

220 ohm/2A

L11

1 2

220 ohm

L13

1 2

220 ohm

+FCH_VDD_11_SSUSB_S

40mils

12

R199

1 2

0_0603_5%

R201

1 2

0_0603_5%

B

10U_0603_6.3V6M

C212

1

2

C219

2.2U_0402_6.3V6M

C219

2.2U_0402_6.3V6M

1

2

C223

10U_0603_6.3V6M

C223

10U_0603_6.3V6M

1

2

+VDDPL_33_SSUSB_S

@

1 2

C194 2.2U_0603_6.3V4Z

1 2

R196 0_0402_5%R196 0_0402_5%

+VDDAN_33_USB

10U_0603_6.3V6M

C213

C214

1U_0402_6.3V6K

C214

1U_0402_6.3V6K

C215

1U_0402_6.3V6K

C215

1

2

C220

0.1U_0402_16V7K

C220

0.1U_0402_16V7K

C234

1

2

Add C234 follow AMD reccommandation 10/28

C224

0.1U_0402_16V7K

C224

0.1U_0402_16V7K

1

2

C229

1

2

C237

1

2

1U_0402_6.3V6K

1

2

+VDDAN_11_USB_S+VDDAN_11_USB_S

0.1U_0402_16V7K@C234

0.1U_0402_16V7K

1

@

2

+VDDCR_11V_USB

C225

0.1U_0402_16V7K

C225

0.1U_0402_16V7K

1

2

+VDDAN_11_SSUSB

1U_0402_6.3V6K

C230

0.1U_0402_16V7K

C230

0.1U_0402_16V7K

1

2

+VDDCR_11_SSUSB

C238

1U_0402_6.3V6K

C238

1U_0402_6.3V6K

10U_0603_6.3V6M

1

2

C216

1

2

C231

0.1U_0402_16V7K

C231

0.1U_0402_16V7K

1

2

C239

1

2

U2C

HUDSON-2

102mA

AB17

VDDIO_33_PCIGP_1

AB18

VDDIO_33_PCIGP_2

AE9

VDDIO_33_PCIGP_3

AD10

VDDIO_33_PCIGP_4

AG7

VDDIO_33_PCIGP_5

AC13

VDDIO_33_PCIGP_6

AB12

VDDIO_33_PCIGP_7

AB13

VDDIO_33_PCIGP_8

AB14

VDDIO_33_PCIGP_9

AB16

VDDIO_33_PCIGP_10

47mA

H24

VDDPL_33_SYS

20mA

V22

VDDPL_33_DAC

12mA

U22

VDDPL_33_ML

30mA

T22

VDDAN_33_DAC

11mA

L18

VDDPL_33_SSUSB_S

14mA

D7

VDDPL_33_USB_S

11mA

AH29

VDDPL_33_PCIE

12mA

AG28

VDDPL_33_SATA

M31

LDO_CAP

7mA

V21

VDDPL_11_DAC

226mA

Y22

VDDAN_11_ML_1

V23

VDDAN_11_ML_2

V24

VDDAN_11_ML_3

V25

VDDAN_11_ML_4

AB10

VDDIO_33_GBE_S

AB11

VDDCR_11_GBE_S_1

AA11

VDDCR_11_GBE_S_2

AA9

VDDIO_GBE_S_1

AA10

VDDIO_GBE_S_2

470mA

G7

VDDAN_33_USB_S_1

H8

0.1U_0402_16V7K

VDDAN_33_USB_S_2

J8

VDDAN_33_USB_S_3

K8

VDDAN_33_USB_S_4

K9

VDDAN_33_USB_S_5

M9

VDDAN_33_USB_S_6

M10

VDDAN_33_USB_S_7

N9

VDDAN_33_USB_S_8

N10

VDDAN_33_USB_S_9

M12

VDDAN_33_USB_S_10

N12

VDDAN_33_USB_S_11

M11

VDDAN_33_USB_S_12

140mA

U12

VDDAN_11_USB_S_1

U13

VDDAN_11_USB_S_2

42mA

T12

VDDCR_11_USB_S_1

T13

VDDCR_11_USB_S_2

282mA

P16

VDDAN_11_SSUSB_S_1

M14

VDDAN_11_SSUSB_S_2

N14

VDDAN_11_SSUSB_S_3

P13

VDDAN_11_SSUSB_S_4

P14

VDDAN_11_SSUSB_S_5

424mA

N16

VDDCR_11_SSUSB_S_1

N17

VDDCR_11_SSUSB_S_2

P17

VDDCR_11_SSUSB_S_3

M17

VDDCR_11_SSUSB_S_4

S IC 218-0755091 A13 HUDSON-M3L FCBGA 656P C38

0.1U_0402_16V7K

C240

0.1U_0402_16V7K

C240

0.1U_0402_16V7K

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HUDSON-2

PCI/GPIO I/O

USB SS USB MAIN LINKGBE LAN

POWER

C

VDDCR_11_1 VDDCR_11_2 VDDCR_11_3 VDDCR_11_4 VDDCR_11_5 VDDCR_11_6 VDDCR_11_7 VDDCR_11_8

CORE S0

VDDCR_11_9

VDDAN_11_CLK_1 VDDAN_11_CLK_2 VDDAN_11_CLK_3 VDDAN_11_CLK_4 VDDAN_11_CLK_5 VDDAN_11_CLK_6

CLKGEN I/OPCI EXPRESSSERIAL ATA3.3V_S5 I/O

VDDAN_11_CLK_7 VDDAN_11_CLK_8

VDDAN_11_PCIE_1 VDDAN_11_PCIE_2 VDDAN_11_PCIE_3 VDDAN_11_PCIE_4 VDDAN_11_PCIE_5 VDDAN_11_PCIE_6 VDDAN_11_PCIE_7 VDDAN_11_PCIE_8

VDDAN_11_SATA_1 VDDAN_11_SATA_4 VDDAN_11_SATA_2 VDDAN_11_SATA_3 VDDAN_11_SATA_5 VDDAN_11_SATA_6 VDDAN_11_SATA_7 VDDAN_11_SATA_8 VDDAN_11_SATA_9

VDDAN_11_SATA_10

VDDIO_33_S_1 VDDIO_33_S_2 VDDIO_33_S_3 VDDIO_33_S_4 VDDIO_33_S_5 VDDIO_33_S_6 VDDIO_33_S_7 VDDIO_33_S_8

VDDXL_33_S

VDDCR_11_S_1 VDDCR_11_S_2

VDDPL_11_SYS_S

VDDAN_33_HWM _S

VDDIO_AZ_S

2011/10/12 2013/10/12

1007mA

C183

T14 T17

1 T20 U16 U18

2 V14

V17 V20 Y17

340mA

H26 J25

C189

K24 L22

1 M22 N21 N22

2 P22

1088mA

AB24 Y21 AE25

C195

AD24 AB23

1 AA22 AF26 AG27

2

1337mA

AA21 Y20 AB21

C203

AB22 AC22

1 AC21 AA20 AA18

2 AB20

AC19

59mA

N18 L19

C207

M18 V12

1 V13 Y12 Y13

2 W11

5mA

G24

C217

1

2

187mA

N20 M20

C221

1

2

70mA

J24

C226

1

2

12mA

M8

C232

1

@

2

26mA

AA4

Compal Secret Data

Deciphered Date

+VCC_VDDCR_11

0.1U_0402_16V7K

+1.1VS_CKVDD

0.1U_0402_16V7K

+VDDAN_11_PCIE

0.1U_0402_16V7K

+VDDIO_33_S

1U_0402_6.3V6K

2.2U_0402_6.3V6M

1U_0402_6.3V6K

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M@C232

2.2U_0402_6.3V6M

@

C184

0.1U_0402_16V7K

C184

0.1U_0402_16V7K

C185

1U_0402_6.3V6K

C185

1U_0402_6.3V6K

C186

1

2

C190

1

2

C196

1

2

C204

1

2

C208

1

2

+VDDXL_3.3V

+VDDCR_1.1V

C222

1

2

+VDDPL_11_SYS_S

C228

1

2

+VDDAN_33_HWM

C233

1

2

C186

1

2

+1.1VS_CKVDD

C192

0.1U_0402_16V7K

C191

1U_0402_6.3V6K

C191

1U_0402_6.3V6K

1

2

+VDDAN_11_PCIE

C197

22U_0603_6.3V6M

C197

22U_0603_6.3V6M

1U_0402_6.3V6K

1

2

+AVDD_SATA

C206

C205

1U_0402_6.3V6K

C205

1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K@C233

0.1U_0402_16V7K

+VDDIO_AZ

1

2

C209

2.2U_0402_6.3V6M

C209

2.2U_0402_6.3V6M

1

2

C236 2.2U_0402_6.3V6MC 236 2.2U_0402_6.3V6M

1 2

D

C177

10U_0603_6.3V6M

C177

10U_0603_6.3V6M

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

22U_0603_6.3V6M

R187 0_0603_5%R187 0_0603_5%

C193

22U_0603_6.3V6M

C193

22U_0603_6.3V6M

1

2

1 2

R195 0_0402_5%R195 0_0402_5%

L9

1 2

MBK1608221YZF_2P

220 ohm

1 2

R197 0_0603_5%R197 0_0603_5%

L14

1 2

MBK1608221YZF_2P

220 ohm

1 2

R198 0_0402_5%R198 0_0402_5%

1 2

R200 0_0402_5%R200 0_0402_5%

1 2

R184 0_0805_5%R184 0_0805_5%

42ohm @ 100MHz

1 2

42ohm @ 100MHz

1 2

R191 0_0805_5%R191 0_0805_5%

42ohm @ 100MHz

1 2

R194 0_0805_5%R194 0_0805_5%

+1.1VS

+3VALW

+VDDXL_3.3V Tie to +3.3V_S5 rail if USB3 Wa ke is supported; o therwise, tie to +3.3V_S0 rail. Hudson-2 design s: Tie to +3.3V_ S0 rail.

+1.1VALW

+3VALW

AMD reply: VDDAN_33_HWM_S: Please connect it to +3.3V_S5 directly if HWM is not used.

+3VS

VDDIO_AZ_S should be tied to +3.3/1.5V_S5 rail if Wake on Ring is supported

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

FCH PWR

LA8681P

13 48Tuesday, November 29, 2011

E

0.1

5

4

3

2

1

U2E

HUDSON-2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSAN_HWM

VSSXL

VSSPL_SYS

HUDSON-2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

GROUND

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSPL_DAC

VSSAN_DAC

VSSANQ_DAC

VSSIO_DAC

EFUSE

T25 T27 U6 U14 U17 U20 U21 U30 U32 V11 V16 V18 W4 W6 W25 W28 Y14 Y16 Y18 AA6 AA12 AA13 AA14 AA16 AA17 AA25 AA28 AA30 AA32 AB25 AC6 AC18 AC28 AD27 AE6 AE15 AE21 AE28 AF8 AF12 AF16 AF33 AG30 AG32 AH5 AH11 AH18 AH19 AH21 AH23 AH25 AH27 AJ18 AJ28 AJ29 AK21 AK25 AL18 AM21 AM25 AN1 AN18 AN28 AN33

T21 L28 K33 N28

R6

A3

A33

B7

B13

D D

C C

B B

D13

E12 E16 E29

F11 F13 F16 F17 F19 F23 F25 F29

G16 G32 H12 H15 H29

K16 K27 K28

L12 L13 L15 L16

L21 M13 M16 M21 M25

N11 N13 N23 N24

P12

P18

P20

P21

P31

P33

R11 R25 R28

T11

T16

T18

K25

H25

J10 J13 J28 J32

D9

E5

F7 F9

G6

J6 J9

K7

L6

N6

R4

N8

STRAP PINS

PCI_CLK1

ALLOW

PULL

PCIE GEN2

HIGH

DEFAULT

FORCE

PULL

PCIE GEN1

LOW

PCI_CLK1<10>

PCI_CLK3<10>

PCI_CLK4<10>

CLK_PCI_EC<10,30>

LPC_CLK1<10>

EC_PWM2<12>

RTC_CLK<10,30 >

PCI_CLK3

USE DEBUG STRAPS

IGNORE DEBUG STRAP

DEFAULT

12

@

PCI_CLK4 LPC_CLK0_EC

NON_FUSION CLOCK MODE

FUSION CLOCK MODE

DEFAULT

R202 1 0K_0402_5%R202 10K_0402_5%

12

@

R214 1 0K_0402_5%@R214 1 0K_0402_5%

12

R203 1 0K_0402_5%@R203 1 0K_0402_5%

R215 1 0K_0402_5%R215 10K_0402_5%

EC ENABLED

EC DISABLED

DEFAULT

R204 1 0K_0402_5%@R204 1 0K_0402_5%

12

@

R216 1 0K_0402_5%R216 10K_0402_5%

12

EC_PWM2

CLKGEN ENABLED

DEFAULT

CLKGEN DISABLE

R205 1 0K_0402_5%@R205 1 0K_0402_5%

R206 1 0K_0402_5%R206 10K_0402_5%

12

@

R217 1 0K_0402_5%R217 10K_0402_5%

12

@

R218 1 0K_0402_5%@R218 1 0K_0402_5%

12

@

LPC ROM

SPI ROM

DEFAULT

+3VALW+3VALW+3VALW+3VALW+3VS+3 VS+3VS

R208 1 0K_0402_5%R208 10K_0402_5%

R207 1 0K_0402_5%@R207 1 0K_0402_5%

12

R219 2 .2K_0402_5%R219 2.2K_0402_5%

R220 2 .2K_0402_5%@R220 2 .2K_0402_5%

12

@

RTC_CLKLPC_CLK1

S5 PLUS MODE DISABLED

DEFAULT

S5 PLUS MODE ENABLED

DEBUG STRAPS

FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]

PCI_AD27 PCI_AD26

PULL HIGH

PULL LOW

PCI_AD27<10>

PCI_AD26<10>

PCI_AD25<10>

PCI_AD24<10>

PCI_AD23<10>

USE PCI PLL

DEFAULT

BYPASS PCI PLL

DISABLE ILA AUTORUN

DEFAULT

ENABLE ILA AUTORUN

R209 2.2K_040 2_5%@R209 2.2K_040 2_5%

12

@

R210 2.2K_040 2_5%@R210 2.2K_040 2_5%

12

@

PCI_AD25 PCI_AD24

USE FC PLL

BYPASS FC PLL

@

R211 2.2K_040 2_5%@R211 2.2K_040 2_5%

12

USE DEFAULT PCIE STRAPS

DEFAULT

USE EEPROM PCIE STRAPS

@

12

R212 2.2K_040 2_5%@R212 2.2K_040 2_5%

PCI_AD23

DISABLE PCI MEM BOOT

DEFAULTDEFAULT

ENABLE PCI MEM BOOT

12

@

R213 2.2K_040 2_5%@R213 2.2K_040 2_5%

S IC 218-0755091 A13 HUDSON-M3L FCBGA 656P C38

A A

S IC 218-0755091 A13 HUDSON-M3L FCBGA 656P C38

5

Security Classification

2011/10/12 2013/10/12

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

2011/10/12 2013/10/12

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

FCH-VSS/Strap

LA8681P

14 48Wednesday, November 30, 2011

1

0.1

5

PCIE_CTX_GRX_P[3..0]<6>

PCIE_CTX_GRX_N[3..0]<6>

PCIE_CTX_GRX_P[3..0]

PCIE_CTX_GRX_N[3..0]

U6A

PX@

4

PCIE_CRX_GTX_P[3..0]

PCIE_CRX_GTX_N[3..0]

3

PCIE_CRX_GTX_P[3..0] <6>

PCIE_CRX_GTX_N[3..0] <6>

2

1

LVDS Interface

PCIE_CTX_GRX_P0

D D

C C

B B

CLK_PCIE_VGA<10> CLK_PCIE_VGA#<10>

VGA_PWRGD<12,17,43>

A A

PCIE_CTX_GRX_N0

PCIE_CTX_GRX_P1 PCIE_CTX_GRX_N1

PCIE_CTX_GRX_P2 PCIE_CTX_GRX_N2

PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3

CLK_PCIE_VGA CLK_PCIE_VGA#

R222 0_04 02_5%

R224

PX@R22 4

PX@

10K_0402_5%

GPU_RST#

5

@

12

PX@

R226

R226 100K_0402_5%

100K_0402_5%

AA38

Y37

Y35

W36

W38

V37

V35 U36

U38

T37

T35

R36

R38 P37

P35 N36

N38 M37

M35

L36

L38 K37

K35 J36

J38 H37

H35 G36

G38

F37

F35

E37

AB35 AA36

AH16

AA30

PCIE_RX0P PCIE_RX0N

PCIE_RX1P PCIE_RX1N

PCIE_RX2P PCIE_RX2N

PCIE_RX3P PCIE_RX3N

PCIE_RX4P PCIE_RX4N

PCIE_RX5P PCIE_RX5N

PCIE_RX6P PCIE_RX6N

PCIE_RX7P PCIE_RX7N

PCIE_RX8P PCIE_RX8N

PCIE_RX9P PCIE_RX9N

PCIE_RX10P PCIE_RX10N

PCIE_RX11P PCIE_RX11N

PCIE_RX12P PCIE_RX12N

PCIE_RX13P PCIE_RX13N

PCIE_RX14P PCIE_RX14N

PCIE_RX15P PCIE_RX15N

CLOCK

PCIE_REFCLKP PCIE_REFCLKN

PWRGOOD

PERSTB

ROBSON XT M2

PCI EXPRESS INTERFACE

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

PCIE_TX8P PCIE_TX8N

PCIE_TX9P PCIE_TX9N

PCIE_TX10P

PCIE_TX10N

PCIE_TX11P

PCIE_TX11N

PCIE_TX12P

PCIE_TX12N

PCIE_TX13P

PCIE_TX13N

PCIE_TX14P

PCIE_TX14N

PCIE_TX15P

PCIE_TX15N

CALIBRATION

PCIE_CALRP

PCIE_CALRN

4

PCIE_CRX_C_GTX_P0

Y33

PCIE_CRX_C_GTX_N0

Y32

PCIE_CRX_C_GTX_P1

W33

PCIE_CRX_C_GTX_N1 PCIE_CRX_GTX_N1

W32

PCIE_CRX_C_GTX_P2

U33

PCIE_CRX_C_GTX_N2

U32

PCIE_CRX_C_GTX_P3

U30

PCIE_CRX_C_GTX_N3 PCIE_CRX_GTX_N3

U29

T33 T32

T30 T29

P33 P32

P30 P29

N33 N32

N30 N29

L33 L32

L30 L29

K33 K32

J33 J32

K30 K29

H33 H32

Y30

Y29

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

1 2

R2231.27K_0402_1% PX@ R2231.27K_0402_1% PX@

R2252K_0402_1% PX@ R2252K_0402_1% PX@

+1.0VGS

2011/10/12 2013/10/12

3

C2410.1U_0402_16V7K PX@C2410.1U_0402_16V7K PX@

12

C2420.1U_0402_16V7K PX@C2420.1U_0402_16V7K PX@

12

C2430.1U_0402_16V7K

12

C2440.1U_0402_16V7K PX@C2440.1U_0402_16V7K PX@

12

C2450.1U_0402_16V7K

12

C2460.1U_0402_16V7K PX@C2460.1U_0402_16V7K PX@

12

C2470.1U_0402_16V7K

12

C2480.1U_0402_16V7K PX@C2480.1U_0402_16V7K PX@

12

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0

PX@

PCIE_CRX_GTX_P1

PX@

PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2

PX@

PCIE_CRX_GTX_P3

Compal Secret Data

Deciphered Date

U6G

PX@

U6G

PX@

LVDS CONTROL

TXCLK_UP_DPF3P

TXCLK_UN_DPF3N

TXOUT_U0P_DPF2P TXOUT_U0N_DPF2 N

TXOUT_U1P_DPF1P TXOUT_U1N_DPF1 N

TXOUT_U2P_DPF0P TXOUT_U2N_DPF0 N

TXOUT_U3P TXOUT_U3N

LVTMDP

TXCLK_LP_DPE3P

TXCLK_LN_DPE3N

TXOUT_L0P_DPE2P

TXOUT_L0N_DPE2N

TXOUT_L1P_DPE1P

TXOUT_L1N_DPE1N

TXOUT_L2P_DPE0P

TXOUT_L2N_DPE0N

TXOUT_L3P

TXOUT_L3N

ROBSON XT M2

R221 0_0402_5%@R221 0_0402_5%@

PXS_RST#<12>

APU_PCIE_RST#<10,29>

2

1

Title

Size Document Number Rev

B

Date: Sheet of

12

+3VGS

5

U7

P

B

4

Y

A

G

PX@

3

MC74VHC1G08DFT2G SC70 5P

Compal Electronics, Inc.

ATI_RobsonXT_M2_PCIE/LVDS

GPU_RST#

LA8681P

1

VARY_BL

DIGON

15 48Wednesday, November 30, 2011

AK27 AJ27

AK35 AL36

AJ38 AK37

AH35 AJ36

AG38 AH37

AF35 AG36

AP34 AR34

AW37 AU35

AR37 AU39

AP35 AR35

AN36 AP37

0.1

5

D D

VRAM_ID0<20> VRAM_ID1<20> VRAM_ID2<20>

L18

PX@L18

PX@

12

L19

PX@L19

PX@

12

27MHZ_16PF_X5H027000FG1H

C291

PX@ C 291

PX@

18P_0402_50V8J

STRAPS

1 2 1 2 1 2

R1.0

1 2

1 2 1 2

1 2 1 2 1 2

1 2

75mA

1

C280

C281

2

PX@ C280

PX@

PX@ C281

PX@

1U_0402_6.3V6K

10U_0603_6.3V6M

125mA

1

C284

C285

2

PX@ C284

PX@

PX@ C285

PX@

1U_0402_6.3V6K

10U_0603_6.3V6M

R254

PX@

1M_0402_5%

Y2

PX@Y2

PX@

2 1

R22910K_0402_5% @ R22910K_0402_5% @ R23010K_0402_5% PX@ R23010K_0402_5% PX@ R23110K_0402_5% PX@ R23110K_0402_5% PX@

R23210K_0402_5% @ R23210K_0402_5% @

R23410K_0402_5% @ R23410K_0402_5% @ R23610K_0402_5% @ R23610K_0402_5% @

R23710K_0402_5% PX@ R23710K_0402_5% PX@ R23910K_0402_5% @ R23910K_0402_5% @ R24010K_0402_5% @ R24010K_0402_5% @

R24210K_0402_5% @ R24210K_0402_5% @ R24310K_0402_5% @ R24310K_0402_5% @ R24410K_0402_5% @ R24410K_0402_5% @

R24510K_0402_5% @ R24510K_0402_5% @

1

2

0.1U_0402_16V7K

1

2

0.1U_0402_16V7K

XTALINXTALOUT

C292

18P_0402_50V8J

5

GPU_GPIO0 GPU_GPIO1 GPU_GPIO2

GPU_GPIO5

GPU_GPIO8 GPU_GPIO9

GPU_GPIO11 GPU_GPIO12 GPU_GPIO13

GPIO24_TRSTB

GPIO25_TDI GPIO27_TMS

GPIO26_TCK

+DPLL_PVDD

1

C282

2

PX@ C282

PX@

+DPLL_VDDC

1

C287

2

PX@ C287

PX@

PX@C292

PX@

ACIN<30,38>

XTALIN Voltage Swing: 1.8 V

+1.8VGS

RB751V_SOD323

RB751V_SOD323 D2

@D2

@

GPU_VID0<43>

GPU_VID1<43>

PEG_CLKREQ#<12>

+1.8VGS

PX@

R248 499_0402_1%

PX@

R249 249_0402_1%

12

C279 0.1U_0402_16V7K

PX@

L20

1 2

BLM15BD121SN1D_0402

21

T49T49

T50T50

R241 10K_0402_5%@R241 10K_0402_5%@

1 2

T51T51

T52T52

12

T58T58

(1.8V@20mA TSVDD)

1

C288

2

10U_0603_6.3V6M

PX@ C288

PX@

+3VGS

C C

+3VGS

B B

+1.8VGS

BLM15BD121SN1D_0402

+1.0VGS

BLM15BD121SN1D_0402

A A

4

GPU_GPIO0 GPU_GPIO1 GPU_GPIO2 VGA_SMB_DA2 VGA_SMB_CK2 GPU_GPIO5 GPU_GPIO_6

R02

GPU_GPIO8 GPU_GPIO9

GPU_GPIO11 GPU_GPIO12 GPU_GPIO13

GPU_VID0 GPIO_16

GPU_VID1 GPIO21_BBEN

PEG_CLKREQ# GPIO24_TRSTB GPIO25_TDI GPIO26_TCK GPIO27_TMS GPIO28_TDO

0.60 V level, Please VREFG Divider ans cap close to ASIC

+VREFG_GPU

+DPLL_PVDD

+DPLL_VDDC

XTALIN XTALOUT

TS_FDO

+TSVDD

1

C290

C289

2

1U_0402_6.3V6K

0.1U_0402_16V4Z

PX@ C290

PX@

PX@ C289

PX@

4

U6B

AR8

DVPCNTL_MVP_0

AU8

DVPCNTL_MVP_1

AP8

DVPCNTL_0

AW8

DVPCNTL_1

AR3

DVPCNTL_2

AR1

DVPCLK

AU1

DVPDATA_0

AU3

DVPDATA_1

AW3

DVPDATA_2

AP6

DVPDATA_3

AW5

DVPDATA_4

AU5

DVPDATA_5

AR6

DVPDATA_6

AW6

DVPDATA_7

AU6

DVPDATA_8

AT7

DVPDATA_9

AV7

DVPDATA_10

AN7

DVPDATA_11

AV9

DVPDATA_12

AT9

DVPDATA_13

AR10

DVPDATA_14

AW10

DVPDATA_15

AU10

DVPDATA_16

AP10

DVPDATA_17

AV11

DVPDATA_18

AT11

DVPDATA_19

AR12

DVPDATA_20

AW12

DVPDATA_21

AU12

DVPDATA_22

AP12

DVPDATA_23

AJ21

SWAPLOCKA

AK21

SWAPLOCKB

AK26

SCL

AJ26

SDA

GENERAL PURPOSE I/O

AH20

GPIO_0

AH18

GPIO_1

AN16

GPIO_2

AH23

GPIO_3_SMBDATA

AJ23

GPIO_4_SMBCLK

AH17

GPIO_5_AC_BATT

AJ17

GPIO_6

AK17

GPIO_7_BLON

AJ13

GPIO_8_ROMSO

AH15

GPIO_9_ROMSI

AJ16

GPIO_10_ROMSCK

AK16

GPIO_11

AL16

GPIO_12

AM16

GPIO_13

AM14

GPIO_14_HPD2

AM13

GPIO_15_PWRCNTL_0

AK14

GPIO_16

AG30

GPIO_17_THERMAL_INT

AN14

GPIO_18_HPD3

AM17

GPIO_19_CTF

AL13

GPIO_20_PWRCNTL_1

AJ14

GPIO_21_BB_EN

AK13

GPIO_22_ROMCSB

AN13

GPIO_23_CLKREQB

AM23

JTAG_TRSTB

AN23

JTAG_TDI

AK23

JTAG_TCK

AL24

JTAG_TMS

AM24

JTAG_TDO

AJ19

GENERICA

AK19

GENERICB

AJ20

GENERICC

AK20

GENERICD

AJ24

GENERICE_HPD4

AH26

GENERICF_HPD5

AH24

GENERICG_HPD6

AK24

HPD1

AH13

VREFG

AM32

DPLL_PVDD

AN32

DPLL_PVSS

AN31

DPLL_VDDC

AV33

XTALIN

AU34

XTALOUT

AW34

XO_IN

AW35

XO_IN2

AF29

DPLUS

AG29

DMINUS

AK32

TS_FDO

AL31

TS_A/NC

AJ32

TSVDD

AJ33

TSVSS

ROBSON XT M2

MUTI GFX

I2C

PLL/CLOCK

THERMAL

PX@

TXCAP_DPA3P

TXCAM_DPA3N

TX0P_DPA2P

TX0M_DPA2N

DPA

TX1P_DPA1P

TX1M_DPA1N

TX2P_DPA0P

TX2M_DPA0N

TXCBP_DPB3P

TXCBM_DPB3N

TX3P_DPB2P

TX3M_DPB2N

DPB

TX4P_DPB1P

TX4M_DPB1N

TX5P_DPB0P

TX5M_DPB0N

TXCCP_DPC3P

TXCCM_DPC3N

TX0P_DPC2P

TX0M_DPC2N

DPC

TX1P_DPC1P

TX1M_DPC1N

TX2P_DPC0P

TX2M_DPC0N

TXCDP_DPD3P

TXCDM_DPD3N

TX3P_DPD2P

TX3M_DPD2N

DPD

TX4P_DPD1P

TX4M_DPD1N

TX5P_DPD0P

TX5M_DPD0N

DAC1

HSYNC VSYNC

AVSSQ

VDD1DI

VSS1DI

R2/NC

R2B/NC

G2/NC

G2B/NC

B2/NC

B2B/NC

COMP/NC

DAC2

H2SYNC/GENLK_CLK

V2SYNC/GENLK_VSYNC

VDD2DI/NC

VSS2DI/NC

A2VDD/NC

A2VDDQ/NC

A2VSSQ/TSVSSQ

R2SET/NC

DDC/AUX

DDC1CLK

DDC1DATA

AUX1P

AUX1N

DDC2CLK

DDC2DATA

AUX2P

AUX2N

DDCCLK_AUX3P

DDCDATA_AUX3N

DDCCLK_AUX4P

DDCDATA_AUX4N

DDCCLK_AUX5P

DDCDATA_AUX5N

DDC6CLK

DDC6DATA

DDCCLK_AUX7P

DDCDATA_AUX7N

RSET

AVDD

C/NC Y/NC

3

AU24 AV23

AT25 AR24

AU26 AV25

AT27 AR26

AR30 AT29

AV31 AU30

AR32 AT31

AT33 AU32

AU14 AV13

AT15 AR14

AU16 AV15

AT17 AR16

AU20 AT19

AT21 AR20

AU22 AV21

AT23 AR22

AD39

R

AD37

RB

AE36

G

AD35

GB

AF37

B

AE38

BB

AC36 AC38

R238 499_0402_1%PX@R238 499_0402_1%PX@

AB34

+AVDD

AD34 AE34

+VDD1DI

AC33 AC34

AC30 AC31

AD30 AD31

AF30 AF31

AC32 AD32 AF32

AD29 AC29

AG31 AG32

AG33

AD33

AF33

R330

AA29

AM26 AN26

AM27 AL27

AM19 AL19

AN20 AM20

AL30 AM30

AL29 AM29

AN21 AM21

AJ30 AJ31

AK30 AK29

1 2

(1.8V@65mA AVDD)

GENLK_CLK GENLK_VSYNC

+VDD2DI

+A2VDD

+A2VDDQ

Robson@R330

Robson@

1 2

12

@

R250

R250 10K_0402_5%

10K_0402_5%

715_0402_1%

3

+3VGS+3VGS

12

@

R265

R265 10K_0402_5%

10K_0402_5%

1

C1033

2

PX@ C1033

PX@

0.1U_0402_16V7K

(1.8V@100mA VDD1DI)

0.1U_0402_16V7K

Issued Date

+VDD2DI

+A2VDD

C434

Robson@

C437

Robson@

C430

Robson@

T53T53 T54T54

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

1 2

L16

PX@L16

PX@

BLM15BD121SN1D_0402

1

C274

C273

2

PX@ C274

PX@

PX@ C273

PX@

1U_0402_6.3V6K

10U_0603_6.3V6M

1 2

BLM15BD121SN1D_0402

1

C278

C277

C276

2

PX@ C278

PX@

PX@ C277

PX@

PX@ C276

PX@

1U_0402_6.3V6K

10U_0603_6.3V6M

Robson@L28

C435

Robson@

0.1U_0402_10V6K

C395

Robson@

0.1U_0402_10V6K

130mA

C438

Robson@

0.1U_0402_10V6K

1

C429

Robson@

2

1U_0402_6.3V4Z

1

C380

Robson@

2

1U_0402_6.3V4Z

1

C436

Robson@

2

1U_0402_6.3V4Z

Robson@

1 2

BLM15BD121SN1D_0402

1

2

10U_0603_6.3V6M

Robson@L41

Robson@

1 2

BLM15BD121SN1D_0402

1

2

10U_0603_6.3V6M

Robson@L27

Robson@

1 2

BLM15BD121SN1D_0402

1

2

10U_0603_6.3V6M

Compal Secret Data

2mA

1

2

100mA

1

2

1

2

2011/10/12 2013/10/12

+1.8VGS

L17

PX@L17

PX@

L28

L41

L27

Deciphered Date

2

CONFIGURATION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

STRAPS

GPIO0 PCIE FULL TX OUTPUT SWINGTX_PWRS_ENB

GPIO1TX_DEEMPH _EN PCIE TR ANSMITTER DE-EMPHASIS

RSVD

BIOS_ROM_EN

VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE STR APS

RSVD

AMD RESERVED CONFIGURATION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL RESISTOR. IF THESE GPIOS ARE USED, THEY MUST KEEP "LOW" AND NOT CONFLICT DURING RESET

GPIO21 GPIO2

GPIO2

GPIO8

GPIO9 VGA ENABLEDBIF_VGA DIS

GPIO21

GPIO_22_ROMCSB

GPIO[13:11]ROMIDCFG(2:0)

H2SYNC

GENERICC

HSYNCAUD [1]

VSYNCAUD[0]

H2SYNC GENERICC

TX_PWRS_ENB

TX_DEEMPH_EN

+1.8VGS

+3VGS

R246

10K_0402_5%

+1.8VGS

+3VGS

+1.8VGS+A2VDDQ

2

VGA_SMB_CK2

VGA_SMB_DA2

DESCRIPTION OF DEFAULT SETT INGSPIN

Advertises PCIE speed when compliance test

RESERVED

ENABLE EXTERNAL BIOS ROM

SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT

AUD[1] AUD[0] 0 0 No audio function 0 1 Audio for DisplayPort and HDMI if dongle is detected 1 0 Audio for DisplayPort only 1 1 Audio for both DisplayPort and HDMI

GPIO8

Transmitter Power Saving Enable

GPIO0

0: 50% Tx output swing for mobile mode 1: full Tx output swing (Default setting for Desktop)

PCI Express Transmitter De-emphasis Enable

GPIO1

0: Tx de-emphasis diabled for mobile mode 1: Tx de-emphasis enabled (Defailt setting for desktop)

Internal VGA Thermal Sensor

12

R247

R247 10K_0402_5%

10K_0402_5%

PX@

DMN66D0LDW-7_SOT363-6

+3VGS

2

61

5

Q17A

4

PX@

Q17B

DMN66D0LDW-7_SOT363-6

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet of

Compal Electronics, Inc.

ATI_RobsonXT_M2_Main_MSIC

1

RECOMMEN DED SETTINGS 0= DO N OT INSTALL RESISTOR 1 = I NSTALL 10K RESISTOR X = DESIGN DEPENDANT NA = NOT APPLICABLE

0: 50% swing 1: Full swing

0: disable 1: enable

0: 2.5GT/s 1: 5GT/s

0: disable 1: enable

EC_SMB_CK2 <5,29,30>

3

LA8681P

1

EC_SMB_DA2 <5,29,30>

RECOMMENDED SETTINGS

X

0

X

XXX

0

11

16 48Wednesday, November 30, 2011

0.1

5

4

3

2

1

+3VGS

1

5

2

B

1

A

3

PX_MODE <43>

C293

@ C293

@

2

0.1U_0402_16V7K

0.1U_0402_16V7K U9

U9

PX@

P

4

Y

G

VGA_PWRGD<12,15,43>

PX@

R259

+3VGS

D D

PX_EN<18>

C C

1 2

10K_0402_5%

13

D

Q24

2

2N7002K_SOT23-3

G

PX@

S

+3VGS

12

@

R261

20K_0402_5%

PXS_PWREN RUNPWROK

PX@

1 2

R880

0_0402_5%

1U_0603_10V6K

1

@

C297

2

+3VGS

C296

0.1U_0402_16V7K

1 2

5

2

P

B

Y

1

A

G

3

MC74VHC1G08DFT2G SC70 5P

@C296

@

U10

PX_MODE

4

PX@

+1.8VS TO +1.8VGS

+1.8VS +1.8VGS

PX@

1

C375

10U_0603_6.3V6M

B B

+VSB

PXS_PWREN#

2

R279

20K_0402_5%

PX@R279

PX@

2

G

R370

1 2

47K_0402_5%

13

D

Q32

2N7002K_SOT23-3

S

U13 AO4430L_SO8

AO4430L_SO8

8 7 6 5

PX@R370

PX@

J4

@J4

@

2 1

2MM

PX@U13

PX@

4

1

C357

0.1U_0603_25V7K

2

1

PX@

C398

1 2 3

PX@C357

PX@

C398 10U_0603_6.3V6M

10U_0603_6.3V6M

2

PXS_PWREN#

1 2

R281

@ R 281

@

0_0402_5%

1

PX@

C399

C399 1U_0603_10V6K

1U_0603_10V6K

2

G

12

R269

@R269

@

470_0603_5%

Q33

@

Q33

@

13

D

S

2N7002K_SOT23-3

+5VALW

PXS_PWREN

10U_0603_6.3V6M

R270

1 2

51K_0402_5%

PX@

R257

10K_0402_5%

PX@

5

PX@

C423

2

G

12

34

PX@

Q68B

Q68B DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

+3.3VS TO +3.3VGS

+3VS +3VGS

1

2

PX@

R271

20K_0402_5%

13

D

Q30

PX@

Q30

PX@

2N7002K_SOT23-3

S

J2

2 1

2MM

3 1

AP2301GN-HF_SOT23-3

2

1

C304

0.1U_0603_25V7K

2

@J2

@

Q27

10K_0402_5%

PX@Q27

PX@

PX@C304

PX@

R256

PX@

2

+5VS+5VS

PXS_PWREN#

12

VDDC_ON#

6

PX@

Q68A

Q68A DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

1

PX@

C302

C302 10U_0603_6.3V6M

10U_0603_6.3V6M

2

1 2

R272

@ R 272

@

0_0402_5%

1.0V_ON#

1

PX@

C303

C303 1U_0603_10V6K

1U_0603_10V6K

2

G

12

R268

@ R268

@

470_0603_5%

Q29

@

Q29

@

13

D

S

2N7002K_SOT23-3

+1.0VGS

1.0V_ON#

+VGA_CORE

VDDC_ON#

Q18

PX@

AO3414_SOT23-3

D

S

D

S

123

G

Q22

PX@

AO3414_SOT23-3

D

S

D

S

123

G

PXS_PWREN<12, 43>

Q19

PX@

AO3414_SOT23-3

D

S

D

S

123

G

Q23

PX@

AO3414_SOT23-3

D

S

D

S

123

G

100K_0402_5%

DTC124EKAT146_SC59-3

PXS_PWREN

55mA@1.0V, in BACO mode

+BIF_VDDC

+3VALW

12

R263

PX@R263

PX@

PXS_PWREN#

Q26

1

OUT

2

IN

GND

PX@

3

1

C294

22U_0805_6.3V6MPX@

2

+1.5V

2 1

2MM

U12

PX@U12

+1.5VS TO +1.5VGS

+3VALW

12

PX@

R273

100K_0402_5%

34

PX@

A A

PX_MODE

PX@ R276

PX@

100K_0402_5%

R276

12

5

PX@

Q69B

5

DMN66D0LDW-7_SOT363-6

PX_MODE#

10U_0603_6.3V6M

1

C305

PX@

2

+VSB

PX@

R275

R275 20K_0402_5%

20K_0402_5%

6

PX@

Q69A

2

DMN66D0LDW-7_SOT363-6

1

8 7 6 5

R278

1 2

43K_0402_5%

PX@

AO4430L_SO8

J9

@J9

@

4

R280

R280 0_0402_5%

0_0402_5%

@

1 2

1 2 3

+1.5VGS

1

PX@

C306

C306 10U_0603_6.3V6M

10U_0603_6.3V6M

2

PX_MODE#

1

PX@

C308

0.1U_0603_25V7K

2

4

1

2

R282

@ R282

@

1 2

0_0402_5%

2N7002K_SOT23-3

PX@

C307

C307 1U_0603_10V6K

1U_0603_10V6K

2

G

Q31

@

Q31

@

12

@

R274

R274 470_0603_5%

470_0603_5%

13

D

S

PX@

C376

10U_0603_6.3V6M

+VSB

PXS_PWREN#

+1.05VS +1.0VGS

1

2

PX@R309

PX@

2

G

R862

1 2

39K_0402_5%

13

D

Q34

2N7002K_SOT23-3

S

3

R309

20K_0402_5%

J7

@J7

@

2 1

2MM

U14

PX@U14

PX@

AO4430L_SO8

8 7 6 5

4

PX@R862

PX@

1

C358

0.1U_0603_25V7K

PX@

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

1

PX@

C419

1 2 3

PX@C358

PX@

C419 10U_0603_6.3V6M

10U_0603_6.3V6M

2

PXS_PWREN#

2011/10/12 2013/10/12

1 2

R310

@ R 310

@

0_0402_5%

1

2

Compal Secret Data

PX@

C421

C421 1U_0603_10V6K

1U_0603_10V6K

2

G

Deciphered Date

12

13

D

S

R277

@R277

@

470_0603_5%

Q38

@

Q38

@

2N7002K_SOT23-3

2

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet of

Compal Electronics, Inc.

ATI_RobsonXT_M2_BACO POWER

LA8681P

1

17 48Wednesday, November 30, 2011

0.1

+1.05VS TO +1.0VGS

5

D D

+1.8VGS

R284

1 2

0_0402_5%

PX@

+1.0VGS

R286

1 2

0_0402_5%

+1.8VGS

+1.0VGS

0_0402_5%

PX@

R289

1 2

0_0402_5%

PX@

R291

1 2

0_0402_5%

PX@

C C

B B

A A

+DPCD_VDD10

1

C319

C318

@ C319

@

@ C318

@

2

1U_0402_6.3V6K

10U_0603_6.3V6M

150mA

1

C322

C321

@ C322

@

@ C321

@

2

10U_0603_6.3V6M

1

C324

C325

@ C324

@

@ C325

@

2

10U_0603_6.3V6M

C320

@ C320

@

0.1U_0402_16V7K

1

2

1U_0402_6.3V6K

+DPEF_VDD10

1

2

1U_0402_6.3V6K

C313

@

+DPCD_VDD10

1

2

1

C323

@ C323

@

2

0.1U_0402_16V7K

1

C326

@ C326

@

2

0.1U_0402_16V7K

1

C314

@

2

10U_0603_6.3V6M

+DPEF_VDD10

1U_0402_6.3V6K

1

@

2

C310

0.1U_0402_16V7K

+DPEF_VDD10

+DPCD_VDD18

1

2

+DPCD_VDD18

+DPCD_VDD10

+DPEF_VDD18

+DPEF_VDD10

+DPCD_VDD18

+DPCD_VDD10

+DPEF_VDD18

20mA

R287150_0402_1% PX@ R287150_0402_1% PX@

12

R292150_0402_1% PX@ R292150_0402_1% PX@

12

AP20 AP21

AP13 AT13

AN17 AP16

AP17 AW14 AW16

AP22

AP23

AP14

AP15

AN19

AP18

AP19 AW20 AW22

AW18

AH34

AJ34

AL33

AM33

AN34

AP39

AR39

AU37

AF34

AG34

AK33

AK34

AF39

AH39

AK39

AL34

AM34

AM39

ROBSON XT M2

PX@

4

U6H

DP C/D POWER

DPCD/DPC_VDD18#1 DPCD/DPC_VDD18#2

DPCD/DPC_VDD10#1 DPCD/DPC_VDD10#2

DP/DPC_VSSR#1 DP/DPC_VSSR#2 DP/DPC_VSSR#3 DP/DPC_VSSR#4 DP/DPC_VSSR#5

DPCD/DPD_VDD18#1 DPCD/DPD_VDD18#2

DPCD/DPD_VDD10#1 DPCD/DPD_VDD10#2

DP/DPD_VSSR#1 DP/DPD_VSSR#2 DP/DPD_VSSR#3 DP/DPD_VSSR#4 DP/DPD_VSSR#5

DPCD_CALR

DP E/F POWER

DPEF/DPE_VDD18#1 DPEF/DPE_VDD18#2

DPEF/DPE_VDD10#1 DPEF/DPE_VDD10#2

DP/DPE_VSSR#1 DP/DPE_VSSR#2 DP/DPE_VSSR#3 DP/DPE_VSSR#4

DPEF/DPF_VDD18#1 DPEF/DPF_VDD18#2

DPEF/DPF_VDD10#1 DPEF/DPF_VDD10#2

DP/DPF_VSSR#1 DP/DPF_VSSR#2 DP/DPF_VSSR#3 DP/DPF_VSSR#4 DP/DPF_VSSR#5

DPEF_CALR

DP A/B POWER

DPAB/DPA_VDD18#1 DPAB/DPA_VDD18#2

DPAB/DPA_VDD10#1 DPAB/DPA_VDD10#2

DP/DPA_VSSR#1 DP/DPA_VSSR#2 DP/DPA_VSSR#3 DP/DPA_VSSR#4 DP/DPA_VSSR#5

DPAB/DPB_VDD18#1 DPAB/DPB_VDD18#2

DPAB/DPB_VDD10#1 DPAB/DPB_VDD10#2

DP/DPB_VSSR#1 DP/DPB_VSSR#2 DP/DPB_VSSR#3 DP/DPB_VSSR#4 DP/DPB_VSSR#5

DPAB_CALR

DP PLL POWER

DPAB_VDD18/DPA_PVDD

DP_VSSR/DPA_PVSS

DPAB_VDD18/DPB_PVDD

DP_VSSR/DPB_PVSS

DPCD_VDD18/DPC_PVDD

DP_VSSR/DPC_PVSS

DPCD_VDD18/DPD_PVDD

DP_VSSR/DPD_PVSS

DPEF_VDD18/DPE_PVDD

DP_VSSR/DPE_PVSS

DPEF_VDD18/DPF_PVDD

DP_VSSR/DPF_PVSS

1.8V@300mA DPAB_VDD18)

+DPAB_VDD18

1

C311

2

@

130mA

AN24 AP24

110mA

AP31 AP32

AN27 AP27 AP28 AW24 AW26

AP25 AP26

AN33 AP33

AN29 AP29 AP30 AW30 AW32

AW28

20mA

AU28 AV27

20mA

AV29 AR28

AU18 AV17

AV19 AR18

AM37 AN38

AL38 AM35

0.1U_0402_16V7K

(1.0V@220mA DPAB_VDD10)

+DPAB_VDD10

1

C315

@

2

0.1U_0402_16V7K

+DPAB_VDD18

130mA

+DPAB_VDD10

110mA

R288 150_0402_1%PX@R288 150_0402_1%PX@

1 2

+DPAB_VDD18

+DPCD_VDD18

+DPEF_VDD18

3

R283

1 2

0_0402_5%

PX@

R285

1 2

0_0402_5%

PX@

+1.8VGS

+1.0VGS

+DPAB_VDD18

1

C312

C309

2

@

+DPAB_VDD10

1U_0402_6.3V6K

10U_0603_6.3V6M

1

C317

C316

@

2

1U_0402_6.3V6K

10U_0603_6.3V6M

2

AB39

E39 F34 F39 G33 G34 H31 H34 H39

J31

J34 K31 K34 K39 L31 L34 M34 M39 N31 N34 P31 P34 P39 R34 T31 T34 T39 U31 U34 V34 V39

W31 W34

Y34 Y39

F15 F17 F19 F21 F23 F25 F27 F29 F31 F33

F7

F9 G2 G6 H9

J2

J27

J6

J8

K14

K7

L11 L17

L2

L22 L24

L6

M17 M22 M24 N16 N18

N2

N21 N23 N26

N6

R15 R17

R2

R20 R22 R24 R27

R6

T11 T13 T16 T18 T21 T23 T26 U15 U17

U2

U20 U22 U24 U27

U6

V11 V16 V18 V21 V23 V26 W2 W6 Y15 Y17 Y20 Y22 Y24 Y27 U13 V13

U6F

PCIE_VSS#1 PCIE_VSS#2 PCIE_VSS#3 PCIE_VSS#4 PCIE_VSS#5 PCIE_VSS#6 PCIE_VSS#7 PCIE_VSS#8 PCIE_VSS#9 PCIE_VSS#10 PCIE_VSS#11 PCIE_VSS#12 PCIE_VSS#13 PCIE_VSS#14 PCIE_VSS#15 PCIE_VSS#16 PCIE_VSS#17 PCIE_VSS#18 PCIE_VSS#19 PCIE_VSS#20 PCIE_VSS#21 PCIE_VSS#22 PCIE_VSS#23 PCIE_VSS#24 PCIE_VSS#25 PCIE_VSS#26 PCIE_VSS#27 PCIE_VSS#28 PCIE_VSS#29 PCIE_VSS#30 PCIE_VSS#31 PCIE_VSS#32 PCIE_VSS#33 PCIE_VSS#34 PCIE_VSS#35

GND#100 GND#101 GND#102 GND#103 GND#104 GND#105 GND#106 GND#107 GND#108 GND#109 GND#110 GND#111 GND#112 GND#113 GND#114 GND#115 GND#116 GND#117 GND#118 GND#119 GND#120 GND#121 GND#122 GND#123 GND#124 GND#125 GND#126 GND#127 GND#128 GND#129 GND#130 GND#131 GND#132 GND#133 GND#134 GND#135 GND#136 GND#137 GND#138 GND#139 GND#140 GND#141 GND#142 GND#143 GND#144 GND#145 GND#146 GND#147 GND#148 GND#149 GND#150 GND#151 GND#153 GND#154 GND#155 GND#156 GND#157 GND#158 GND#159 GND#160 GND#161 GND#163 GND#164 GND#165 GND#166 GND#167 GND#168 GND#169 GND#170 GND#171 GND#172 GND#173 GND#174 GND#175 GND#152 GND#162

ROBSON XT M2

PX@

GND

GND#1 GND#2 GND#3 GND#4 GND#5 GND#6 GND#7 GND#8

GND#9 GND#10 GND#11 GND#12 GND#13 GND#14 GND#15 GND#16 GND#17 GND#18 GND#19 GND#20 GND#21 GND#22 GND#23 GND#24 GND#25 GND#26 GND#27 GND#28 GND#29 GND#30 GND#31 GND#32 GND#33 GND#34 GND#35 GND#36 GND#37 GND#38 GND#39 GND#40 GND#41 GND#42 GND#43 GND#44 GND#45 GND#46 GND#47 GND#48 GND#49 GND#50 GND#51 GND#52 GND#53 GND#54 GND#55 GND#56 GND#57 GND#58 GND#59 GND#60

GND/PX_EN#61

GND#62 GND#63 GND#64 GND#65 GND#66 GND#67 GND#68 GND#69 GND#70 GND#71 GND#72 GND#73 GND#74 GND#75 GND#76 GND#77 GND#78 GND#79 GND#80 GND#81 GND#82 GND#83 GND#84 GND#85 GND#86 GND#87 GND#88 GND#89 GND#90 GND#91 GND#92 GND#93 GND#94 GND#95 GND#96 GND#97 GND#98

VSS_MECH#1 VSS_MECH#2 VSS_MECH#3

A3 A37 AA16 AA18 AA2 AA21 AA23 AA26 AA28 AA6 AB12 AB15 AB17 AB20 AB22 AB24 AB27 AC11 AC13 AC16 AC18 AC2 AC21 AC23 AC26 AC28 AC6 AD15 AD17 AD20 AD22 AD24 AD27 AD9 AE2 AE6 AF10 AF16 AF18 AF21 AG17 AG2 AG20 AG22 AG6 AG9 AH21 AJ10 AJ11 AJ2 AJ28 AJ6 AK11 AK31 AK7 AL11 AL14 AL17 AL2 AL20 AL21 AL23 AL26 AL32 AL6 AL8 AM11 AM31 AM9 AN11 AN2 AN30 AN6 AN8 AP11 AP7 AP9 AR5 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B7 B9 C1 C39 E35 E5 F11 F13

A39 AW1 AW39

MECH#1 MECH#2 MECH#3

12

R290

4.7K_0402_5%

PX@

1

PX_EN <17>

T55 PADT55 PAD T56 PADT56 PAD T57 PADT57 PAD

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2011/10/12 2013/10/12

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet of

Compal Electronics, Inc.

ATI_RobsonXT_M2_PWR_GND

LA8681P

1

18 48Wednesday, November 30, 2011

0.1

5

4

3

2

1

+1.5VGS

D D

VDDR1 CRB Design

0.1u 6 6 1u 10 5 10u 6 5

VDD_CT CRB Design

0.1u 1 1 1u 3 3 10u 1 1

VDDR3 CRB Design

C C

1u 3 3 10u 1 1

VDDR4 CRB Design

0.1u 1 1 1u 1 1

MPV18 CRB Design

0.1u 2 1 1u 2 1 10u 1 1

SPV18 CRB Design

0.1u 1 1 1u 1 1 10u 1 1

SPV10 CRB Design

0.1u 1 1 1u 1 1 10u 1 1

B B

1

C336

C337

+

@

2

PX@ C337

PX@

10U_0603_6.3V6M

220U_B2_2.5VM_R35

1

C338

2

PX@ C338

PX@

10U_0603_6.3V6M

1

C339

C327

C328

2

PX@ C339

PX@

PX@ C327

PX@

PX@ C328

PX@

10U_0603_6.3V6M

+1.8VGS +VDDC_CT

+3VGS

1

C391

C390

2

PX@ C391

PX@

PX@ C390

PX@

1U_0402_6.3V6K

10U_0603_6.3V6M

1 2

BLM15BD121SN1D_0402

+1.0VGS

1 2

MCK1608471YZF 0603

For DDR3/GDDR5, MVDDQ = 1.5V

1

C340

C341

2

PX@ C340

PX@

PX@ C341

PX@

1U_0402_6.3V6K

PX@ L22

PX@

1 2

BLM15BD121SN1D_0402

1

C393

C392

2

PX@ C393

PX@

PX@ C392

PX@

1U_0402_6.3V6K

+1.8VGS

+1.8VGS+1.8VGS

L25

PX@L25

PX@

L26

PX@L26

PX@

1

C342

C329

C343

2

PX@ C342

PX@

PX@ C329

PX@

PX@ C343

PX@

1U_0402_6.3V6K

L22

(1.8V@110mA VDD_CT)

1

C370

2

PX@ C370

PX@

1U_0402_6.3V6K

10U_0603_6.3V6M

L23

PX@ L23

PX@

1 2

BLM15BD121SN1D_0402

(M97, Broadway and Madison: 1.8V@150mA MPV18)

L24

PX@L24

PX@

1 2

MCK1608471YZF 0603

1

C406

C407

2

PX@ C406

PX@

PX@ C407

PX@

1U_0402_6.3V6K

10U_0603_6.3V6M

1

C420

C424

2

PX@ C420

PX@

PX@ C424

PX@

1U_0402_6.3V6K

10U_0603_6.3V6M

1

C344

2

PX@ C344

PX@

0.1U_0402_16V7K

1

C371

C372

2

PX@ C371

PX@

PX@ C372

PX@

1U_0402_6.3V6K

1

C408

2

PX@ C408

PX@

0.1U_0402_16V7K

1

C426

2

PX@ C426

PX@

0.1U_0402_16V7K

1

C347

C346

C345

2

PX@ C347

PX@

PX@ C346

PX@

PX@ C345

PX@

0.1U_0402_16V7K

1

C374

C373

2

PX@ C374

PX@

PX@ C373

PX@

1U_0402_6.3V6K

0.1U_0402_16V7K

1

C397

C396

2

PX@ C397

PX@

PX@ C396

PX@

1U_0402_6.3V6K

0.1U_0402_16V7K

1

C403

C405

C404

2

PX@ C403

PX@

PX@ C405

PX@

PX@ C404

PX@

1U_0402_6.3V6K

0.1U_0402_16V7K

10U_0603_6.3V6M

(1.8V@75mA SPV18)

(120mA SPV10)

VCCSENSE_VGA<43>

VSSSENSE_VGA<43>

1

2

0.1U_0402_16V7K

+VDDR4

+MPV18

1

C348

2

PX@ C348

PX@

+SPV18

+SPV10

AD11

AG10

AG26 AG27

AG23 AG24

AG13 AG15

AD12

AG11

AM10

AN10

AG28

AH29

AF26 AF27

AF23 AF24

AF13 AF15

AF11 AF12

AF28

AC7

AF7

AJ7

AK8

AL9 G11 G14 G17 G20 G23 G26 G29 H10

K11

K13

L12

L16

L21

L23

L26

M11 N11

R11 U11

Y11

M20 M21

V12 U12

AN9

U6E

VDDR1#1 VDDR1#2 VDDR1#3 VDDR1#4 VDDR1#5 VDDR1#6 VDDR1#7 VDDR1#8 VDDR1#9 VDDR1#10 VDDR1#11 VDDR1#12 VDDR1#13 VDDR1#14 VDDR1#15

J7

VDDR1#16

J9

VDDR1#17 VDDR1#18 VDDR1#19

K8

VDDR1#20 VDDR1#21 VDDR1#22 VDDR1#23 VDDR1#24 VDDR1#25

L7

VDDR1#26 VDDR1#27 VDDR1#28

P7

VDDR1#29 VDDR1#30 VDDR1#31

U7

VDDR1#32 VDDR1#33

Y7

VDDR1#34

VDD_CT#1 VDD_CT#2 VDD_CT#3 VDD_CT#4

VDDR3#1 VDDR3#2 VDDR3#3 VDDR3#4

VDDR4#4 VDDR4#5 VDDR4#7 VDDR4#8

VDDR4#1 VDDR4#2 VDDR4#3 VDDR4#6

NC_VDDRHA NC_VSSRHA

NC_VDDRHB NC_VSSRHB

H7

MPV18#1

H8

MPV18#2

SPV18

SPV10

SPVSS

FB_VDDC

FB_VDDCI

FB_GND

ROBSON XT M2

PX@

MEM I/O

LEVEL

LEVEL TRANSLATION

TRANSLATION

I/O

PLL

VOLTAGE

VOLTAGE SENESE

SENESE

PCIE

PCIE_VDDR#1 PCIE_VDDR#2 PCIE_VDDR#3 PCIE_VDDR#4 PCIE_VDDR#5 PCIE_VDDR#6 PCIE_VDDR#7 PCIE_VDDR#8

PCIE_VDDR/PCIE_PVDD

PCIE_VDDC#1 PCIE_VDDC#2 PCIE_VDDC#3 PCIE_VDDC#4 PCIE_VDDC#5 PCIE_VDDC#6 PCIE_VDDC#7 PCIE_VDDC#8

PCIE_VDDC#9 PCIE_VDDC#10 PCIE_VDDC#11 PCIE_VDDC#12

VDDC#1

CORE

VDDC#2 VDDC#3 VDDC#4 VDDC#5 VDDC#6 VDDC#7 VDDC#8

VDDC#9 VDDC#10 VDDC#11 VDDC#12 VDDC#13 VDDC#14 VDDC#15

POWER

VDDC#16 VDDC#17 VDDC#18 VDDC#19 VDDC#20 VDDC#21 VDDC#22 VDDC#23 VDDC#24 VDDC#25 VDDC#26 VDDC#27 VDDC#28 VDDC#29 VDDC#30 VDDC#31 VDDC#32

VDDC/BIF_VDDC#33

VDDC#34 VDDC#35 VDDC#36 VDDC#37 VDDC#38 VDDC#39 VDDC#40 VDDC#41

VDDC/BIF_VDDC#42

VDDC#43 VDDC#44 VDDC#45 VDDC#46 VDDC#47 VDDC#48 VDDC#49 VDDC#50 VDDC#51 VDDC#52 VDDC#53 VDDC#54 VDDC#55 VDDC#56 VDDC#57 VDDC#58

VDDCI#1 VDDCI#2 VDDCI#3 VDDCI#4 VDDCI#5 VDDCI#6 VDDCI#7 VDDCI#8

VDDCI#9 VDDCI#10 VDDCI#11 VDDCI#12 VDDCI#13 VDDCI#14 VDDCI#15

ISOLATED

VDDCI#16

CORE I/O

VDDCI#17 VDDCI#18 VDDCI#19 VDDCI#20 VDDCI#21 VDDCI#22

AA31 AA32 AA33 AA34 V28 W29 W30 Y31 AB37

G30 G31 H29 H30 J29 J30 L28 M28 N28 R28 T28 U28

AA15 AA17 AA20 AA22 AA24 AA27 AB16 AB18 AB21 AB23 AB26 AB28 AC17 AC20 AC22 AC24 AC27 AD18 AD21 AD23 AD26 AF17 AF20 AF22 AG16 AG18 AG21 AH22 AH27 AH28 M26 N24 N27 R18 R21 R23 R26 T17 T20 T22 T24 T27 U16 U18 U21 U23 U26 V17 V20 V22 V24 V27 Y16 Y18 Y21 Y23 Y26 Y28

AA13 AB13 AC12 AC15 AD13 AD16 M15 M16 M18 M23 N13 N15 N17 N20 N22 R12 R13 R16 T12 T15 V15 Y13

(1.8V@504mA PCIE_VDDR)

+PCIE_VDDR

1

C332

C330

C331

C333

2

PX@ C332

PX@

PX@ C330

PX@

PX@ C331

PX@

PX@ C333

PX@

1U_0402_6.3V6K

0.1U_0402_16V7K

1U_0402_6.3V6K

0.1U_0402_16V7K

(1.0V@1920mA PCIE_VDDC)

1

C349

2

PX@ C349

PX@

1U_0402_6.3V6K

1

C355

2

PX@ C355

PX@

1U_0402_6.3V6K

1

C401

2

PX@ C401

PX@

1U_0402_6.3V6K

(GDDR3/DDR3 1.12V@4A VDDCI)

(GDDR5 1.12V@16A VDDCI)

1

C409

2

PX@ C409

PX@

1U_0402_6.3V6K

VDDCI and VDDC should have seperate regulators with a merge option on PCB For Madison, Park, Capilano, Robson, Seymour and Whistler, VDDCI and VDDC can share one common regulator

1

C350

C352

C351

2

PX@ C350

PX@

PX@ C352

PX@

PX@ C351

PX@

1U_0402_6.3V6K

1

C356

2

PX@ C356

PX@

1U_0402_6.3V6K

1

C378

C377

2

PX@ C378

PX@

PX@ C377

PX@

1U_0402_6.3V6K

+BIF_VDDC

For non-BACO designs, connect BIF_VDDC to VDDC. For BACO designs - see BACO reference schematics

1

C402

2

PX@ C402

PX@

1U_0402_6.3V6K

1

C410

C412

C411

2

PX@ C410

PX@

PX@ C412

PX@

PX@ C411

PX@

1U_0402_6.3V6K

1

C334

2

PX@ C334

PX@

1

C353

2

@ C353

@

1

C359

2

PX@ C359

PX@

1

C379

2

PX@ C379

PX@

1

C413

2

PX@ C413

PX@

MBK1608121YZF_0603

1

C335

2

PX@ C335

PX@

10U_0603_6.3V6M

+1.0VGS

1

C354

2

PX@ C354

PX@

10U_0603_6.3V6M

1

C360

2

PX@ C360

PX@

1U_0402_6.3V6K

1

C414

2

PX@ C414

PX@

1U_0402_6.3V6K

1

C361

2

PX@ C361

PX@

1

C381

2

PX@ C381

PX@

1

C415

2

PX@ C415

PX@

PX@ L21

PX@

1

C362

2

PX@ C362

PX@

1U_0402_6.3V6K

1

C382

2

PX@ C382

PX@

1U_0402_6.3V6K

1

C416

2

PX@ C416

PX@

1U_0402_6.3V6K

+1.8VGS

L21

12

PCIE_VDDR CRB Design

0.1u 2 2 1u 3 3 10u 1 1

PCIE_VDDC CRB Design 1u 7 5 (1@) 10u 1 1

+VGA_CORE

VDDC CRB Design 1u 30 25

1

C366

C364

C363

C365

2

PX@ C366

PX@

PX@ C364

PX@

PX@ C363

PX@

PX@ C365

PX@

1U_0402_6.3V6K

1

C383

2

PX@ C383

PX@

1U_0402_6.3V6K

1

C417

2

PX@ C417

PX@

1U_0402_6.3V6K

1

C386

C385

C384

2

PX@ C386

PX@

PX@ C385

PX@

PX@ C384

PX@

1U_0402_6.3V6K

1

C418

2

PX@ C418

PX@

1U_0402_6.3V6K

1

C369

C367

C368

2

PX@ C367

PX@

PX@ C368

PX@

1U_0402_6.3V6K

+VGA_CORE

1

C387

C388

2

PX@ C387

PX@

PX@ C388

PX@

1U_0402_6.3V6K

+VGA_CORE

1

C400

2

PX@ C400

PX@

22U_0603_6.3V6M

10U_0603_6.3V6M

+VGA_CORE

1

C422

2

PX@ C422

PX@

22U_0603_6.3V6M

10U_0603_6.3V6M

10u 10 1 22u 0 1

2

PX@ C369

PX@

1

C389

2

PX@ C389

PX@

1

C394

2

PX@ C394

PX@

VDDCI CRB Design 1u 10 9 10u 3 2 22u 0 1

1

C425

2

PX@ C425

PX@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2011/10/12 2013/10/12

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet of

Compal Electronics, Inc.

ATI_RobsonXT_M2_Power

LA8681P

1

19 48Wednesday, November 30, 2011

0.1

5

U6C

DDR2

DDR2 GDDR3/GDDR5

GDDR3/GDDR5 DDR3

DDR3

C37

DQA0_0/DQA_0

C35

DQA0_1/DQA_1

A35

DQA0_2/DQA_2

E34

DQA0_3/DQA_3

G32

DQA0_4/DQA_4

D33

DQA0_5/DQA_5

F32

DQA0_6/DQA_6

E32

DQA0_7/DQA_7

D31

DQA0_8/DQA_8

F30

DQA0_9/DQA_9

C30

DQA0_10/DQA_10

A30

DQA0_11/DQA_11

F28

DQA0_12/DQA_12

AG12

AH12

C28 A28 E28 D27 F26 C26 A26 F24 C24 A24 E24 C22 A22 F22 D21 A20 F20 D19 E18 C18 A18 F18 D17 A16 F16 D15 E14 F14 D13 F12 A12 D11 F10 A10 C10 G13 H13

J13 H11 G10

G8 K9

K10

G9 A8 C8 E8 A6 C6 E6 A5

L18

L20

L27 N12

M12 M27

DQA0_13/DQA_13 DQA0_14/DQA_14 DQA0_15/DQA_15 DQA0_16/DQA_16 DQA0_17/DQA_17 DQA0_18/DQA_18 DQA0_19/DQA_19 DQA0_20/DQA_20 DQA0_21/DQA_21 DQA0_22/DQA_22 DQA0_23/DQA_23 DQA0_24/DQA_24 DQA0_25/DQA_25 DQA0_26/DQA_26 DQA0_27/DQA_27 DQA0_28/DQA_28 DQA0_29/DQA_29 DQA0_30/DQA_30 DQA0_31/DQA_31 DQA1_0/DQA_32 DQA1_1/DQA_33 DQA1_2/DQA_34 DQA1_3/DQA_35 DQA1_4/DQA_36 DQA1_5/DQA_37 DQA1_6/DQA_38 DQA1_7/DQA_39 DQA1_8/DQA_40 DQA1_9/DQA_41 DQA1_10/DQA_42 DQA1_11/DQA_43 DQA1_12/DQA_44 DQA1_13/DQA_45 DQA1_14/DQA_46 DQA1_15/DQA_47 DQA1_16/DQA_48 DQA1_17/DQA_49 DQA1_18/DQA_50 DQA1_19/DQA_51 DQA1_20/DQA_52 DQA1_21/DQA_53 DQA1_22/DQA_54 DQA1_23/DQA_55 DQA1_24/DQA_56 DQA1_25/DQA_57 DQA1_26/DQA_58 DQA1_27/DQA_59 DQA1_28/DQA_60 DQA1_29/DQA_61 DQA1_30/DQA_62 DQA1_31/DQA_63

MVREFDA MVREFSA

MEM_CALRN0 MEM_CALRN1 MEM_CALRN2

MEM_CALRP1 MEM_CALRP0 MEM_CALRP2

D D

C C

+1.5VGS

R299 240_0402_1%@R 299 240_0402_1%@

1 2

R300 240_0402_1%PX@R300 240_0402_1%PX@

1 2

R301 240_0402_1%@R 301 240_0402_1%@

1 2

R304 240_0402_1%PX@R304 240_0402_1%PX@

1 2

R302 240_0402_1%@R 302 240_0402_1%@

1 2

R305 240_0402_1%@R 305 240_0402_1%@

1 2

DDR2

DDR2 GDDR5/GDDR3

GDDR5/GDDR3 DDR3

DDR3

MAA0_0/MAA_0 MAA0_1/MAA_1 MAA0_2/MAA_2 MAA0_3/MAA_3 MAA0_4/MAA_4 MAA0_5/MAA_5 MAA0_6/MAA_6 MAA0_7/MAA_7 MAA1_0/MAA_8

MAA1_1/MAA_9 MAA1_2/MAA_10 MAA1_3/MAA_11 MAA1_4/MAA_12

MAA1_5/MAA_13_BA2 MAA1_6/MAA_14_BA0

MAA1_7/MAA_A15_BA1

WCKA0_0/DQMA_0

WCKA0B_0/DQMA_1

WCKA0_1/DQMA_2

WCKA0B_1/DQMA_3

WCKA1_0/DQMA_4

WCKA1B_0/DQMA_5

WCKA1_1/DQMA_6

WCKA1B_1/DQMA_7

MEMORY INTERFACE A

GDDR5/DDR2/GDDR3

EDCA0_0/QSA_0/RDQSA_0 EDCA0_1/QSA_1/RDQSA_1 EDCA0_2/QSA_2/RDQSA_2 EDCA0_3/QSA_3/RDQSA_3 EDCA1_0/QSA_4/RDQSA_4 EDCA1_1/QSA_5/RDQSA_5 EDCA1_2/QSA_6/RDQSA_6 EDCA1_3/QSA_7/RDQSA_7

DDBIA0_0/QSA_0B/WDQSA_0 DDBIA0_1/QSA_1B/WDQSA_1 DDBIA0_2/QSA_2B/WDQSA_2 DDBIA0_3/QSA_3B/WDQSA_3 DDBIA1_0/QSA_4B/WDQSA_4 DDBIA1_1/QSA_5B/WDQSA_5 DDBIA1_2/QSA_6B/WDQSA_6 DDBIA1_3/QSA_7B/WDQSA_7

ADBIA0/ODTA0

ADBIA1/ODTA1

CLKA0

CLKA0B

CLKA1

CLKA1B

RASA0B RASA1B

CASA0B CASA1B

CSA0B_0 CSA0B_1

CSA1B_0 CSA1B_1

CKEA0 CKEA1

WEA0B WEA1B

MAA0_8 MAA1_8

GDDR5

G24 J23 H24 J24 H26 J26 H21 G21 H19 H20 L13 G16 J16 H16 J17 H17

A32 C32 D23 E22 C14 A14 E10 D9

C34 D29 D25 E20 E16 E12 J10 D7

A34 E30 E26 C20 C16 C12 J11 F8

J21 G19

H27 G27

J14 H14

K23 K19

K20 K17

K24 K27

M13 K16

K21 J20

K26 L15

H23 J19

4

+1.8VGS

R293 10K_0402_5%X76@R293 10K_0402_5%X76@

1 2

R294 10K_0402_5%X76@R294 10K_0402_5%X76@

1 2

R295 10K_0402_5%X76@R295 10K_0402_5%X76@

1 2

R296 10K_0402_5%X76@R296 10K_0402_5%X76@

1 2

R297 10K_0402_5%X76@R297 10K_0402_5%X76@

1 2

R298 10K_0402_5%X76@R298 10K_0402_5%X76@

1 2

Vendor VRAM_ID0 VRAM_ID1 VRAM_ID2

64MX16 (512MB)

128M16 (1GB)

K4W1G1646G-BC11

Samsung 1Gb PN:SA00004GS40

H5TQ1G63DFR-11C

Hynix 1Gb PN:SA000041S30

K4W2G1646C-HC11

Samsung 256MB PN:SA000047Q10

H5TQ2G63BFR-11C/H5TQ2G63DFR-11C

Hynix 256MB PN:SA00003YO10/ SA00003YO70

3

VRAM_ID0

VRAM_ID1

VRAM_ID2

R293

R296

1 0 0

R295

R294

0 0

R293

R294

1

R296

0

1 1

R295

0

1 1

R298

R297

R303

VRAM_ID0 <16>

VRAM_ID1 <16>

VRAM_ID2 <16>

PX@

1 2

5.11K_0402_1%

MDB0 MDB1 MDB2 MDB3 MDB4 MDB5 MDB6 MDB7 MDB8 MDB9 MDB10 MDB11 MDB12 MDB13 MDB14 MDB15 MDB16 MDB17 MDB18 MDB19 MDB20 MDB21 MDB22 MDB23 MDB24 MDB25 MDB26 MDB27 MDB28 MDB29 MDB30 MDB31 MDB32 MDB33 MDB34 MDB35 MDB36 MDB37 MDB38 MDB39 MDB40 MDB41 MDB42 MDB43 MDB44 MDB45 MDB46 MDB47 MDB48 MDB49 MDB50 MDB51 MDB52 MDB53 MDB54 MDB55 MDB56 MDB57 MDB58 MDB59 MDB60 MDB61 MDB62 MDB63

+VDD_MEM15_REFDB +VDD_MEM15_REFSB

TESTEN

AA12

AD28

AK10

AL10

2

C5 C3

E3 E1 F1 F3

F5 G4 H5 H6

J4

K6

K5

L4 M6 M1 M3 M5 N4

P6

P5 R4

T6

T1 U4

V6

V1

V3

Y6

Y1

Y3

Y5

AA4 AB6 AB1 AB3 AD6 AD1 AD3 AD5 AF1 AF3 AF6 AG4 AH5 AH6

AJ4 AK3 AF8 AF9 AG8 AG7 AK9

AL7 AM8 AM7 AK1

AL4 AM6 AM1 AN4 AP3 AP1 AP5

Y12

U6D

DDR2

DDR2 GDDR3/GDDR5

GDDR3/GDDR5 DDR3

DDR3

DQB0_0/DQB_0 DQB0_1/DQB_1 DQB0_2/DQB_2 DQB0_3/DQB_3 DQB0_4/DQB_4 DQB0_5/DQB_5 DQB0_6/DQB_6 DQB0_7/DQB_7 DQB0_8/DQB_8 DQB0_9/DQB_9 DQB0_10/DQB_10 DQB0_11/DQB_11 DQB0_12/DQB_12 DQB0_13/DQB_13 DQB0_14/DQB_14 DQB0_15/DQB_15 DQB0_16/DQB_16 DQB0_17/DQB_17 DQB0_18/DQB_18 DQB0_19/DQB_19 DQB0_20/DQB_20 DQB0_21/DQB_21 DQB0_22/DQB_22 DQB0_23/DQB_23 DQB0_24/DQB_24 DQB0_25/DQB_25 DQB0_26/DQB_26 DQB0_27/DQB_27 DQB0_28/DQB_28 DQB0_29/DQB_29 DQB0_30/DQB_30 DQB0_31/DQB_31 DQB1_0/DQB_32 DQB1_1/DQB_33 DQB1_2/DQB_34 DQB1_3/DQB_35 DQB1_4/DQB_36 DQB1_5/DQB_37 DQB1_6/DQB_38 DQB1_7/DQB_39 DQB1_8/DQB_40 DQB1_9/DQB_41 DQB1_10/DQB_42 DQB1_11/DQB_43 DQB1_12/DQB_44 DQB1_13/DQB_45 DQB1_14/DQB_46 DQB1_15/DQB_47 DQB1_16/DQB_48 DQB1_17/DQB_49 DQB1_18/DQB_50 DQB1_19/DQB_51 DQB1_20/DQB_52 DQB1_21/DQB_53 DQB1_22/DQB_54 DQB1_23/DQB_55 DQB1_24/DQB_56 DQB1_25/DQB_57 DQB1_26/DQB_58 DQB1_27/DQB_59 DQB1_28/DQB_60 DQB1_29/DQB_61 DQB1_30/DQB_62 DQB1_31/DQB_63

MVREFDB MVREFSB

TESTEN

CLKTESTA CLKTESTB

DDR2

DDR2 GDDR5/GDDR3

GDDR5/GDDR3 DDR3

DDR3

MAB0_0/MAB_0 MAB0_1/MAB_1 MAB0_2/MAB_2 MAB0_3/MAB_3 MAB0_4/MAB_4 MAB0_5/MAB_5 MAB0_6/MAB_6 MAB0_7/MAB_7 MAB1_0/MAB_8

MAB1_1/MAB_9 MAB1_2/MAB_10 MAB1_3/MAB_11 MAB1_4/MAB_12

MAB1_5/BA2 MAB1_6/BA0 MAB1_7/BA1

WCKB0_0/DQMB_0

WCKB0B_0/DQMB_1

WCKB0_1/DQMB_2

WCKB0B_1/DQMB_3

WCKB1_0/DQMB_4

WCKB1B_0/DQMB_5

WCKB1_1/DQMB_6

WCKB1B_1/DQMB_7

GDDR5/DDR2/GDDR3

MEMORY INTERFACE B

EDCB0_0/QSB_0/RDQSB_0 EDCB0_1/QSB_1/RDQSB_1 EDCB0_2/QSB_2/RDQSB_2 EDCB0_3/QSB_3/RDQSB_3 EDCB1_0/QSB_4/RDQSB_4 EDCB1_1/QSB_5/RDQSB_5 EDCB1_2/QSB_6/RDQSB_6 EDCB1_3/QSB_7/RDQSB_7

DDBIB0_0/QSB_0B/WDQSB_0 DDBIB0_1/QSB_1B/WDQSB_1 DDBIB0_2/QSB_2B/WDQSB_2 DDBIB0_3/QSB_3B/WDQSB_3 DDBIB1_0/QSB_4B/WDQSB_4 DDBIB1_1/QSB_5B/WDQSB_5 DDBIB1_2/QSB_6B/WDQSB_6 DDBIB1_3/QSB_7B/WDQSB_7

ADBIB0/ODTB0

ADBIB1/ODTB1

CLKB0

CLKB0B

CLKB1

CLKB1B

RASB0B RASB1B

CASB0B CASB1B

CSB0B_0 CSB0B_1

CSB1B_0 CSB1B_1

CKEB0 CKEB1

WEB0B WEB1B

MAB0_8 MAB1_8

GDDR5

DRAM_RST

P8 T9 P9 N7 N8 N9 U9 U8 Y9 W9 AC8 AC9 AA7 AA8 Y8 AA9

H3 H1 T3 T5 AE4 AF5 AK6 AK5

F6 K3 P3 V5 AB5 AH1 AJ9 AM5

G7 K1 P1 W4 AC4 AH3 AJ8 AM3

T7 W7

L9 L8

AD8 AD7

T10 Y10

W10 AA10

P10 L10

AD10 AC10

U10 AA11

N10 AB11

T8 W8

AH11

MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 B_BA2 B_BA0 B_BA1

DQMB#0 DQMB#1 DQMB#2 DQMB#3 DQMB#4 DQMB#5 DQMB#6 DQMB#7

QSB0 QSB1 QSB2 QSB3 QSB4 QSB5 QSB6 QSB7

QSB#0 QSB#1 QSB#2 QSB#3 QSB#4 QSB#5 QSB#6 QSB#7

ODTB0 ODTB1

CLKB0 CLKB0#

CLKB1 CLKB1#

RASB0# RASB1#

CASB0# CASB1#

CSB0#_0

CSB1#_0

CKEB0 CKEB1

WEB0# WEB1#

MAB13 MAB14

DRAM_RST#_R

1

MDB[0..63]<21>

MDB[0..63]

MAB[12..0]

B_BA[2..0]

ODTB0 <21> ODTB1 <21>

CLKB0 <21> CLKB0# <21>

CLKB1 <21> CLKB1# <21>

RASB0# <21> RASB1# <21>

CASB0# <21> CASB1# <21>

CSB0#_0 <21>

CSB1#_0 <21>

CKEB0 <21> CKEB1 <21>

WEB0# <21> WEB1# <21>

MAB13 <21> MAB14 <21>

DQMB#[7..0] <21>

QSB[7..0] <21>

QSB#[7..0] <21>

MAB[12..0] <21>

B_BA[2..0] <21>

ROBSON XT M2

PX@

B B

A A

R299

R300

R301

R302

R304

R305

Rosbon M2

@

POP

@

POP

@

5

This basic topology should be used for DRAM_RST for DDR3/GDDR5.These Capacitors and Resistor values are an example only. The Series R and || Cap values will depend on the DRAM load and will have to be calculated for different Memory ,DRAM Load and board to pass Reset Signal Spec. Place all these components very close to GPU (Within 25mm) and keep all component close to each Other (within 5mm) except Rser2

+1.5VGS

12

R308

4.7K_0402_5%

@

R313

DRAM_RST#<21>

4

1 2

51.1_0402_1%

PX@

C431

120P_0402_50V9

12

DRAM_RST#_R

R314

1 2

10_0402_5%

PX@

R317

4.99K_0402_1%

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

0.1U_0402_16V7K

2011/10/12 2013/10/12

51.1_0402_1%

C427

R306

12

@

12

@

Compal Secret Data

12

@

C428

0.1U_0402_16V7K

12

@

R307

51.1_0402_1%

Deciphered Date

ROBSON XT M2

PX@

route 50ohms single-ended/100o hms diff and keep short Debug only, for clock observation, if not needed, DNI 5mil 5mil

+1.5VGS +1.5VGS

12

R311

40.2_0402_1%

PX@

+VDD_MEM15_REFDB

12

C432

0.1U_0402_16V7K

R318

100_0402_1%

PX@

2

0.1U_0402_16V7K

PX@

Title

Size Document Number Rev

C

Date: Sheet of

12

R312

40.2_0402_1%

PX@

+VDD_MEM15_REFSB

12

C433

0.1U_0402_16V7K

LA8681P

1

0.1U_0402_16V7K

PX@

20 48Wednesday, November 30, 2011

R319

100_0402_1%

PX@

Compal Electronics, Inc.

ATI_RobsonXT_M2_MEM IF

0.1

5

U17

VREFC_A1_B VREFD_Q1_B

D D

MDB[0..63]<20>

MAB[14..0]<20>

DQMB#[7..0]<20>

QSB[7..0]<20>

QSB#[7..0]<20>

C C

CLKB0

R344 56_0402_1%

CLKB0#

R345 56_0402_1%

CLKB1

1 2

R350 56_0402_1%

CLKB1#

1 2

R351 56_0402_1%

PX@

1 2

PX@

1 2

PX@

MDB[0..63]

MAB[14..0]

DQMB#[7..0]

QSB[7..0]

QSB#[7..0]

12

C481

0.01U_0402_16V7K

PX@

C482

0.01U_0402_16V7K

PX@

B_BA0<20> B_BA1<20> B_BA2<20>

CLKB0<20> CLKB0#<20> CKEB0< 20>

ODTB0<20> CSB0#_0<20> RASB0#<20> CASB0#<20> WEB0#<20>

QSB2 QSB3 QSB4 QSB0 QSB1

DQMB#2 DQMB#3 DQMB#4 DQMB#0 DQMB#1

QSB#2 QSB#3 QSB#4 QSB#0 QSB#1

DRAM_RST#<20>

12

R346

240_0402_1%

PX@

U17

M8 H1

MAB0 MAB0 MAB0 MAB0

N3

MAB1 MAB1 MAB1 MAB1

P7

MAB2 MAB2 MAB2 MAB2

P3

MAB3 MAB3 MAB3 MAB3

N2

MAB4 MAB4 MAB4 MAB4

P8

MAB5 MAB5 MAB5 MAB5

P2

MAB6 MAB6 MAB6 MAB6

R8

MAB7 MAB7 MAB7 MAB7

R2

MAB8 MAB8 MAB8 MAB8

T8

MAB9 MAB9 MAB9 MAB9

R3

MAB10 MAB10 MAB10 MAB10

L7

MAB11 MAB11 MAB11 MAB11

R7

MAB12 MAB12 MAB12 MAB12

N7

MAB13 MAB13 MAB13 MAB13

T3

MAB14 MAB14 MAB14 MAB14

T7 M7

M2 N8 M3

J7 K7 K9

K1

L2

J3 K3

L3

F3 C7

E7 D3

G3 B7

T2

L8

J1

L1

J9

L9

H5TQ1G63DFR-11C

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

BA0 BA1 BA2

CK CK CKE/CKE0

ODT/ODT0 CS/CS0 RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET

ZQ/ZQ0

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

4

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

X76@

3

U18

MDB19

E3

MDB20

F7

MDB22

F2

MDB16

F8

MDB23

H3

MDB17

H8

MDB21

G2

MDB18

H7

MDB0

D7

MDB4

C3

MDB1

C8

MDB6

C2

MDB3

A7

MDB7

A2

MDB2

B8

MDB5

A3

+1.5VGS

B2 D9 G7 K2 K8 N1 N9 R1 R9

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

VREFC_A2_B VREFD_Q2_B

B_BA0 B_BA0 B_BA0 B_BA1 B_BA1 B_BA1 B_BA2 B_BA2 B_BA2

CLKB0 CLKB0# CKEB0 CKEB1

ODTB0 ODTB1 CSB0#_0 CSB1#_0 RASB0# RASB1# CASB0# CASB1# WEB0# WEB1#

DRAM_RST# DRAM_RST# DRAM_RST#

12

R347

240_0402_1%

PX@

U18

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

H5TQ1G63DFR-11C

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

X76@

MDB26

E3

MDB30

F7

MDB24

F2

MDB29

F8

MDB27

H3

MDB28

H8

MDB25

G2

MDB31

H7

MDB15

D7

MDB10

C3

MDB14

C8

MDB11

C2

MDB12

A7

MDB9

A2

MDB13

B8

MDB8

A3

+1.5VGS

B2 D9 G7 K2 K8 N1 N9 R1 R9

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

R348

240_0402_1%

PX@

CLKB1<20> CLKB1#<20> CKEB1< 20>

ODTB1<20> CSB1#_0<20> RASB1#<20> CASB1#<20> WEB1#<20>

VREFC_A3_B VREFD_Q3_B

QSB5

DQMB#5

QSB#5

12

U19

M8 H1

N3

P7 P3

N2

P8

P2 R8 R2

T8 R3

L7 R7 N7

T3

T7 M7

M2 N8 M3

J7

K7

K9

K1

L2

J3

K3

L3

F3 C7

E7 D3

G3

B7

T2

L8

J1

L1

J9

L9

H5TQ1G63DFR-11C

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

BA0 BA1 BA2

CK CK CKE/CKE0

ODT/ODT0 CS/CS0 RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET

ZQ/ZQ0

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

2

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

1

U20

CLKB1 CLKB1#

QSB6 QSB7

DQMB#6 DQMB#7

QSB#6 QSB#7

U20

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

H5TQ1G63DFR-11C

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

X76@

MDB55

E3

MDB50

F7

MDB54

F2

MDB51

F8

MDB53

H3

MDB49

H8

MDB52

G2

MDB48

H7

MDB56

D7

MDB59

C3

MDB63

C8

MDB62

C2

MDB57

A7

MDB61

A2

MDB58

B8

MDB60

A3

+1.5VGS

B2 D9 G7 K2 K8 N1 N9 R1 R9

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

MDB33

E3

MDB37

F7

MDB35

F2

MDB39

F8

MDB32

H3

MDB36

H8

MDB34

G2

MDB38

H7

MDB44

D7

MDB41

C3

MDB47

C8

MDB43

C2

MDB45

A7

MDB40

A2

MDB46

B8

MDB42

A3

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

X76@

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

240_0402_1%

R349

PX@

VREFC_A4_B VREFD_Q4_B

12

B B

+1.5VGS

1

C491

A A

2

PX@ C491

PX@

0.1U_0402_16V7K

1

C492

C493

2

PX@ C492

PX@

PX@ C493

PX@

0.1U_0402_16V7K

5

1

C495

C494

2

PX@ C495

PX@

PX@ C494

PX@

0.1U_0402_16V7K

1

C497

C496

2

PX@ C497

PX@

PX@ C496

PX@

0.1U_0402_16V7K

+1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS

4.99K_0402_1%

1

C498

2

PX@ C498

PX@

0.1U_0402_16V7K

12

R352

PX@

VREFD_Q1_B VREFD_Q2_B

12

1

R360

PX@

C483

2

PX@ C483

PX@

0.1U_0402_16V7K

1

C500

C499

2

PX@ C500

PX@

PX@ C499

PX@

0.1U_0402_16V7K

C502

C501

2

PX@ C502

PX@

PX@ C501

PX@

0.1U_0402_16V7K

4

R353

4.99K_0402_1%

PX@

R361

4.99K_0402_1%

PX@

1

C503

2

PX@ C503

PX@

0.1U_0402_16V7K

12

1

C484

2

PX@ C484

PX@

0.1U_0402_16V7K

4.99K_0402_1%

VREFC_A1_B VREFC_A2_B

4.99K_0402_1%

+1.5VGS

1

C504

2

PX@ C504

PX@

10U_0603_6.3V6M

12

R354

PX@

12

1

R362

PX@

C485

2

PX@ C485

PX@

0.1U_0402_16V7K

1

C505

2

PX@ C505

PX@

10U_0603_6.3V6M

1

C507

C506

2

PX@ C507

PX@

PX@ C506

PX@

10U_0603_6.3V6M

12

R355

4.99K_0402_1%

PX@

12

1

R364

4.99K_0402_1%

PX@

3

C486

2

PX@ C486

PX@

0.1U_0402_16V7K

+1.5VGS +1.5VGS

1

C1048

C1049

2

PX@ C1048

PX@

PX@ C1049

PX@

1U_0402_6.3V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

R356

4.99K_0402_1%

PX@

VREFC_A3_B

12

1

R365

4.99K_0402_1%

PX@

1

C1050

2

PX@ C1050

PX@

1U_0402_6.3V6K

C487

2

PX@ C487

PX@

0.1U_0402_16V7K

1

C1052

2

PX@ C1052

PX@

1U_0402_6.3V6K

1

C1053

2

PX@ C1053

PX@

1U_0402_6.3V6K

Compal Secret Data

C1051

2

PX@ C1051

PX@

1U_0402_6.3V6K

2011/10/12 2013/10/12

R357

4.99K_0402_1%

PX@

R366

4.99K_0402_1%

PX@

1

C1054

2

PX@ C1054

PX@

1U_0402_6.3V6K

Deciphered Date

12

0.1U_0402_16V7K

1

C1056

C1055

2

PX@ C1056

PX@

PX@ C1055

PX@

1U_0402_6.3V6K

2

VREFD_Q3_B

1

C488

2

PX@ C488

PX@

C1057

PX@ C1057

PX@

1U_0402_6.3V6K

12

R358

4.99K_0402_1%

PX@

12

R367

4.99K_0402_1%

PX@

0.1U_0402_16V7K

1

2

1

C1058

2

PX@ C1058

PX@

1U_0402_6.3V6K

1

C1062

C1059

2

PX@ C1062

PX@

PX@ C1059

PX@

1U_0402_6.3V6K

12

R359

4.99K_0402_1%

PX@

VREFC_A4_B

1

C489

2

PX@ C489

PX@

R363

4.99K_0402_1%

PX@

1

C1060

C1063

2

PX@ C1060

PX@

PX@ C1063

PX@

1U_0402_6.3V6K

Title

Size Document Number Rev

C 0.1

Date: Sheet of

1U_0402_6.3V6K

Compal Electronics, Inc.

ATI_RobsonXT_M2_VRAM_B

VREFD_Q4_B

12

1

C490

2

PX@ C490

PX@

0.1U_0402_16V7K

1

C1064

2

PX@ C1064

PX@

1U_0402_6.3V6K

1

C1065

2

PX@ C1065

PX@

1U_0402_6.3V6K

LA8681P

1

C1061

2

PX@ C1061

PX@

1

C1067

C1066

2

PX@ C1067

PX@

PX@ C1066

PX@

1U_0402_6.3V6K

21 48Wednesday, November 30, 2011

5

4

3

2

1

LCD POWER CIRCUIT

D D

APU_ENVDD<5>

C C

B B

A A

2N7002K_SOT23-3

R389 0_0402_5%R389 0_0402_5%

1 2

EC_INVT_PWM<30>

APU_BLPWM<5>

APU_ENBKL<5>

+3VS

5

+LCDVDD

12

R381

R381 150_0603_1%

150_0603_1%

13

D

Q35

2

G

S

2

12

R390

@R390

100K_0402_5%

R983 0_0402_5%R983 0_0402_5%

1 2

R396

100K_0402_5%

CMOS_ON#<30>

@

R697 0_0402_5%R697 0_0402_5%

1 2

R392 0_0402_5%

1 2

@

12

+5VALW

12

R382

R382 100K_0402_5%

100K_0402_5%

R383

1 2

220K_0402_5%

1

OUT

IN

GND

Q37

DTC124EKAT146_SC59-3

3

BKOFF#<30>

R698 0_0402_5%R698 0_0402_5%

R1007 10K_0402_5%R1007 10K_0402_5%

1 2

CMOS Camera

Q39

AP2301GN-HF_SOT23-3

3 1

CMOS@

2

C1091

1 2

0.1U_0402_16V4Z

CMOS@

R987

R987 10K_0402_5%

10K_0402_5%

CMOS@

1 2

1

2

1 2

+3VS

2

C1069

0.1U_0402_16V4Z

FBMA-L11-201209-221LMA30T_0805

INVTPWM

R395

R395 100K_0402_5%

100K_0402_5%

1 2

ENBKL <30>

+CMOS_PW

12

1

2

4

W=60mils

1

C1068

31

4.7U_0603_6.3V6K

2

Q36

Q36 AP2301GN-HF_SOT23-3

AP2301GN-HF_SOT23-3

+LCDVDD

L74

1 2

4.7U_0603_6.3V6K

1 2

R984 0_0402_5%R984 0_0402_5%

21

RB751V_SOD323

RB751V_SOD323 D4

@D4

@

1

C1090

0.1U_0402_16V4Z

CMOS@

R986

R986 0_0603_5%

0_0603_5%

CMOS@

10U_0603_6.3V6M

10U_0603_6.3V6M C1092

C1092

CMOS@

2

+3VS_CMOS

W=60mils

+LCDVDD_CONN

1

C1070

2

R982

@R982

@

1 2

10K_0402_5%

DISPOFF#

1

C1071

0.1U_0402_16V4Z

2

+3VS

LVDS_ACLK<5> LVDS_ACLK#<5>

LVDS_A2<5> LVDS_A2#<5> LVDS_A1<5> LVDS_A1#<5> LVDS_A0<5> LVDS_A0#<5>

EDID_DATA<5>

C544

@

2

EDID_CLK<5>

1

+LCDVDD_CONN

2

+3VS_CMOS

+3VS

680P_0402_50V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/10/12 2013/10/12

Compal Secret Data

Deciphered Date

B++LEDVDD

R822

1 2

0_0805_5%

1

@

C543

680P_0402_50V7K

1 2 3 4 5

DISPOFF# INVTPWM

(60 MIL)

+3VS

USB20_P3<12> USB20_N3<12>

USB20_P3

USB20_N3

Title

Size Document Number Rev

B

Date: Sheet of

6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

ACES_88341-3001

Compal Electronics, Inc.

C542

4.7U_0805_25V6-K

2

JLVDS1

1

31

2

G1

32

3

G2

33

4

G3

34

5

G4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

ME@

LVDS/CAMERA

LA8681P

0.1

22 48Wednesday, November 30, 2011

1

0.1

5

4

3

2

1

EMI request

L75

@L75

HDMI_CLKP<5>

D D

C C

HDMI_CLKN<5>

HDMI_TX0P<5>

HDMI_TX0N<5>

HDMI_TX1P<5>

HDMI_TX1N<5>

HDMI_TX2P<5>

HDMI_TX2N<5>

R988 0_0402_5%HDMI@R988 0_0402_5%HDMI@

R989 0_0402_5%HDMI@R989 0_0402_5%HDMI@

R412 0_0402_5%HDMI@R412 0_0402_5%HDMI@

R991 0_0402_5%HDMI@R991 0_0402_5%HDMI@

R414 0_0402_5%HDMI@R414 0_0402_5%HDMI@

R993 0_0402_5%HDMI@R993 0_0402_5%HDMI@

R994 0_0402_5%HDMI@R994 0_0402_5%HDMI@

R995 0_0402_5%HDMI@R995 0_0402_5%HDMI@

1 2

HDMI_CLK+_CONN

HDMI_CLK-_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX2-_CONN

HDMI_CLKP

HDMI_CLKN

HDMI_TX0P

HDMI_TX0N

HDMI_TX1P

HDMI_TX1N

HDMI_TX2P

HDMI_TX2N

@

1

4

WCM-2012-900T_4P

L33

@L33

@

1

4

WCM-2012-900T_4P

L34

@L34

@

1

4

WCM-2012-900T_4P

L35

@L35

@

1

4

WCM-2012-900T_4P

2

3

2

3

2

3

2

3

HDMI_CLK+_CONN

HDMI_CLK-_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX2-_CONN

C1025 10P_0402_50V8J@ C1025 10P_0402_50V8J@

1 2

C1026 10P_0402_50V8J@ C1026 10P_0402_50V8J@

1 2

C1027 10P_0402_50V8J@ C1027 10P_0402_50V8J@

1 2

C1028 10P_0402_50V8J@ C1028 10P_0402_50V8J@

1 2

C1029 10P_0402_50V8J@ C1029 10P_0402_50V8J@

1 2

C1030 10P_0402_50V8J@ C1030 10P_0402_50V8J@

1 2

C1031 10P_0402_50V8J@ C1031 10P_0402_50V8J@

1 2

C1032 10P_0402_50V8J@ C1032 10P_0402_50V8J@

1 2

3

HDMI_CLK<5>

HDMI_DATA<5>

HDMI_DET<5>

HDMIDAT_R

HDMICLK_R

2

D5 PJDLC05_SOT23-3

PJDLC05_SOT23-3

1

+5VS

@D5

@

3

2

ESD

R451

HDMI@R451

HDMI@

0_0402_5%

12

R452

HDMI@R452

HDMI@

0_0402_5%

12

R450

HDMI@R450

HDMI@

0_0402_5%

12

HDMI@

R974

R974 100K_0402_5%

100K_0402_5%

12

ESD

HDMI_HPD

1

@

D8

D8 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

HDMICLK_R

HDMIDAT_R

HDMI_HPD

1.1A_6V_SMD1812P110TF

HDMI@

R430

2K_0402_5%

1 2

+5VS_HDMI_F

21

HDMI@

F1

+5VS_HDMI

HDMI@

R431

R431 2K_0402_5%

2K_0402_5%

HDMI_CLK-_CONN

HDMI_CLK+_CONN HDMI_TX0-_CONN

HDMI_TX0+_CONN HDMI_TX1-_CONN

HDMI_TX1+_CONN HDMI_TX2-_CONN

HDMI_TX2+_CONN

HDMI_HPD

HDMIDAT_R HDMICLK_R

R429

@R429

@

0_0805_5%

RB491D_SC59-3

HDMI@

D7

C1093

1

0.1U_0402_16V4Z

HDMI@

2

19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

21

+5VS

JHDMI1

HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKCK_shield CK+ D0D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+

SUYIN_100042GR019M23DZL

ME@

GND GND GND GND

20 21 22 23

HDMI@

HDMI_CLK+_CONN

HDMI_CLK-_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX2-_CONN

B B

NEAR CONNECTOR

A A

HDMI@

R418 499_0402_1%

HDMI@

R252 499_0402_1%

HDMI@

R253 499_0402_1%

HDMI@

R255 499_0402_1%

HDMI@

R258 499_0402_1%

HDMI@

R260 499_0402_1%

HDMI@

R262 499_0402_1%

HDMI@

R264 499_0402_1%

+5VS

12

@

R970

R970 100K_0402_5%

100K_0402_5%

2

G

13

D

Q42

Q42 2N7002K_SOT23-3

2N7002K_SOT23-3

HDMI@

S

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/10/12 2013/10/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HDMI Connector

LA8681P

23 48Wednesday, November 30, 2011

1

0.1

A

1 1

2 2

3 3

4 4

DAC_RED<5 >

DAC_GRN<5>

DAC_BLU<5>

CRT_HSYNC< 5>

CRT_VSYNC<5>

CRT_DDC _DATA<5>

CRT_DDC _CLK<5>

DAC_RED

DAC_GRN

DAC_BLU

12

C1108

0.1U_040 2_16V4Z

C1109

0.1U_040 2_16V4Z

12

R975

R975 150_040 2_1%

150_040 2_1%

R976

R976 150_040 2_1%

150_040 2_1%

+CRT_VC C

1

2

1

5

P

A2Y

G

3

+CRT_VC C

1

2

1

5

P

A2Y

G

3

R104 0_ 0402_5%R104 0_0402_5%

1 2

R109 0_ 0402_5%R109 0_0402_5%

1 2

12

R977

R977 150_040 2_1%

150_040 2_1%

R978

1 2

1K_0402 _5%

4

OE#

U23

U23 SN74AHC T1G125DCKR_S C70-5

SN74AHC T1G125DCKR_S C70-5

R979

1 2

1K_0402 _5%

4

OE#

U24

U24 SN74AHC T1G125DCKR_S C70-5

SN74AHC T1G125DCKR_S C70-5

1

2

10P_040 2_50V8J

CRT_HSYNC _1

CRT_VSYNC _1

R980

4.7K_040 2_5%

100P_04 02_50V8J

B

C1094

+CRT_VC C

12

@

C1112

FCM1608 CF-121T03 0603

1 2

FCM1608 CF-121T03 0603

1 2

FCM1608 CF-121T03 0603

1 2

1

C1103

C1104

C1104 10P_040 2_50V8J

10P_040 2_50V8J

2

10P_040 2_50V8J

1 2

L39

FCM1608 CF-121T03 0603

1 2

L40

FCM1608 CF-121T03 0603

12

R981

4.7K_040 2_5%

CRT_DDC _DATA_R

CRT_DDC _CLK_R

1

@

C1121

C1121 68P_040 2_50V8K

68P_040 2_50V8K

2

L36

L37

L38

1

C1105

2

10P_040 2_50V8J

1

C1106

2

10P_040 2_50V8J

1

@

C1120

C1120 10P_040 2_50V8J

10P_040 2_50V8J

2

1

@

C1110

C1110 10P_040 2_50V8J

10P_040 2_50V8J

2

RED

GREEN

BLUE

1

C1107

C1107 10P_040 2_50V8J

10P_040 2_50V8J

2

JVGA_HS

JVGA_VS

C

+5VS

D

BLUE

CRT_DDC _DATA_R

CRT_DDC _CLK_R

D2107

6

5

4

AZC099-0 4S.R7G_SOT23-6

D2108

6

5

4

AZC099-0 4S.R7G_SOT23-6

+5VS

@D2107

@

I/O4

VDD

I/O3

I/O4

VDD

I/O3

RED

CRT_DDC _DATA_R GREEN

JVGA_HS BLUE

JVGA_VS

CRT_DDC _CLK_R

@D2108

@

D14

2 1

RB491D_ SC59-3

I/O2

GND

I/O1

I/O2

GND

I/O1

+CRT_VC C

GREEN

3

2

RED

1

JVGA_HS

3

2

JVGA_VS

1

F2

21

1.1A_6V_ SMD1812P110T F

1

C1122

100P_04 02_50V8J

2

E

1

C568

0.1U_040 2_16V4Z

2

JCRT1

6

11

1 7

12

2 8

G

13

G

3 9

14

4 10 15

5

CONTE_8 0431-5K1-152

ME@

16 17

Security Class ification

2011/10/ 12 2013/10/ 12

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/10/ 12 2013/10/ 12

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Numb er Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

CRT Connector

Custom

LA8681P

0.1

24 48Wednesd ay, November 30, 201 1

E

5

D D

R569 10K_0402_5%

R569 10K_0402_5% R577 1K_0402_5%

R577 1K_0402_5%

1 2

+LAN_VDDREG

PCIE_PRX_C_DTX_P0

PCIE_PRX_C_DTX_N0

LAN_XTALI

LAN_XTALO

PCIE_WAKE#_R

ISOLATEB

12

ENSWREG

1 2

R575 2.49K_0402_1%R575 2.49K_0402_1%

22

23

17 18

16

25

19 20

43

44

28

26

14 15 38

33

34 35

46

24 49

25MHZ_20PF_FSX3M-25.M20FDO

1

2

27P_0402_50V8J

C1126 0.1U_0402_16V7KC1126 0.1U_0402_16V7K

PCIE_FRX_DTX_P0<10>

PCIE_FRX_DTX_N0<10>

PCIE_FTX_C_DRX_P0<10>

PCIE_FTX_C_DRX_N0<10>

LAN_CLKREQ#<12>

PLT_RST#<10,30>

CLK_PCIE_LAN<10>

C C

CLK_PCIE_LAN#<10>

Pin 16 and Pin 28 are OD pins

LAN_WAKE#< 30>

FCH_PCIE_WAKE#<12,29>

+3V_LAN

12

R570

R570 10K_0402_5%

10K_0402_5%

@

LAN_CLKREQ#

B B

1 2

C1127 0.1U_0402_16V7KC1127 0.1U_0402_16V7K

1 2

R1370 0_0402_5%R1370 0_0402_5%

1 2

R1369@0_0402_5%R1369@0_0402_5%

1 2

GIGA@

GIGA@ GIGA@

+3V_LAN

GIGA@

4

U44

8105@U44

8105@

RTL8105E-VL-CGT

U41

HSOP

HSON

HSIP HSIN

CLKREQB

PERSTB

REFCLK_P REFCLK_N

CKXTAL1

CKXTAL2

LANWAK EB

ISOLATEB

NC/SMBCLK NC/SMBDATA GPO/SMBALERT

ENSWR EG

VDDREG VDDREG

RSET

GND PGND

RTL8111F-CGT_QFN48_6x6

GIGA@

SA00004Y700

Y6

4

NC

OSC

1

OSC

NC

R02

C1134

LED3/EEDO LED1/EESK

NC/MDIP2 NC/MDIN2 NC/MDIP3 NC/MDIN3

DVDD10 DVDD10 DVDD10

DVDD33 DVDD33

AVDD33 AVDD33 AVDD33 AVDD33

EVDD10

AVDD10 AVDD10 AVDD10 AVDD10

REGOUT

3

2

LED0

EECS

EEDI

MDIP0 MDIN0 MDIP1 MDIN1

LAN_XTALI

LAN_XTALO

1

C1135

2

31

LAN_LINK#

37

LAN_ACTIVITY#

40

R571 10K_0402 _5%R571 10K_0402 _5%

30

R573 10K_0402 _5%R573 10K_0402 _5%

32

MDI0+

1

MDI0-

2

MDI1+

4

MDI1-

5

MDI2+

7

MDI2-

8

MDI3+

10

MDI3-

11

13

+LAN_VDD10

29 41

27

+3V_LAN

39

12

+3V_LAN

42 47 48

21

+LAN_EVDD10

3

+LAN_VDD10

6 9 45

+LAN_REGOUT

36

27P_0402_50V8J

LAN_LINK# <26> LAN_ACTIVITY# <26>

12 12

MDI0+ <26> MDI0- <26> MDI1+ <26> MDI1- <26> MDI2+ <26> MDI2- <26> MDI3+ <26> MDI3- <26>

3

+LAN_REGOUT

Layout Note: L39 must be within 200mil to Pin36, C700,C738 must be within 200mil to LL1 +LAN_REGOUT: Width =60mil

+LAN_VDD10

1K_0402_1%

15K_0402_5%

L76

1 2

2.2UH +-5% NLC252018T-2R2J-N

4.7U_0603_6.3V6K

12

L480_0603_5% L480_0603_5%

1U_0402_6.3V4Z

Close to Pin 21

12

L770_0603_5% L770_0603_5%

4.7U_0603_6.3V6K

X5R

+3VS

12

R576

R578

+LAN_VDD10

12

C1125

X5R

12

C732

12

C1131

H: Enable internal Regular L: Disable

+LAN_EVDD10

C695

0.1U_0402_16V4Z

1 2

+LAN_VDDREG+ 3V_LAN

0.1U_0402_16V4Z

1 2

ENSWREGISOLATEB

C738

0.1U_0402_16V4Z

1 2

C1132

+3V_LAN

2

R572

R572 0_0402_5%

0_0402_5%

R574

R574 0_0402_5%

0_0402_5%

@

1

Layout Notice : Place as close chip as possible.

+3VALW

J3

JUMP_43X79

AO3413_SOT23

S

R145

Q150

@

LAN_PWR_ON#<30>

12

10K_0402_5%

11/08 Increase for LAN S5 power saving

Rising time (10%~90%)1mS <Rising time <100mS

Close to Pin 12,27,39,42,47,48

+3V_LAN

1 2

C7450.1U_0402_16V4Z C7450.1U_0402_16V4Z

1 2

C11280.1U_0402_16V4Z C11280.1U_0402_16V4Z

1 2

C7420.1U_0402_16V4Z C7420.1U_0402_16V4Z

1 2

GIGA@

Close to Pin 3,6,9,13,29,41,45

GIGA@

1 2

C11290.1U_0402_16V4Z

C7310.1U_0402_16V4Z

C11300.1U_0402_16V4Z

+LAN_VDD10

C7370.1U_0402_16V4Z C7370.1U_0402_16V4Z

C11330.1U_0402_16V4Z C11330.1U_0402_16V4Z

C6940.1U_0402_16V4Z C6940.1U_0402_16V4Z

C7430.1U_0402_16V4Z

C7410.1U_0402_16V4Z

C7390.1U_0402_16V4Z

C7400.1U_0402_16V4Z

+3V_LAN

2

112

@

D

13

G

@

2

C1021

0.1U_0402_16V7K

1

@

Layout Notice : Place as close chip as possible.

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECTRONICS, INC. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

LAN-RTL8111F/8105E

LA-7984P

Wednesday, November 30, 2011

LA-7984P

1

25 48

0.1

5

MDI3-

MDI3+

GND

6677889

5

91010

6677889

RCLAMP3304N.TCT_SLP262 6P10-10

112233445

D69

@

5

91010

112233445

@

MDI2-

MDI2+

MDI1-

MDI1+

RCLAMP3304N.TCT_SLP262 6P10-10

RCLAMP3304N.TCT_SLP262 6P10-10 D68

D68

@

MDI0-

MDI0+

LAN_ACTIVITY#<25>

D D

11

Place Close to T2

C C

11

GND

Place Close to T1

B B

4

1

C1136

0.01U_0402_16V7K

2

3

T2

MDI3+<25> MDI3-<25>

MDI2+<25> MDI2-<25>

MDI3+ MDI3-

MDI2+ MDI2-

MDI0+<25> MDI0-<25>

MDI1+<25> MDI1-<25>

MDI0+ MDI0-

MDI1+ MDI1-

1

TD+

2 3 4 5 6 7

1 2 3 4 5 6 7

TX+

TD-

TX-

CT

NC

CT

RD+

RX+

RD-8RX-

BOTHHAND_NS0013L F

GIGA@

R02

T1

TD+

TX+

TD-

TX-

CT

NC

CT

RD+

RX+

RD-8RX-

BOTHHAND_NS0013L F

2

MDO3+

16

MDO3-

15

MCT3

14 13 12

MCT2

11

MDO2+

10

MDO2-

9

MCT0

MCT1

MDO0+ MDO0-

MDO1+ MDO1-

16 15 14 13 12 11 10 9

1 2

R1374 75_0603_5%

GIGA@

1 2

R1375 75_0603_5%

GIGA@

R1376

1 2

75_0603_5%

R1377

1 2

75_0603_5%

1

1 2

C973

1000P_1206_2KV7K

Reserve gas tube for EMI go rural solution

Place Close to T1,T2

JRJ1

LAN_LINK#<25>

LAN_LINK#

LAN_ACTIVITY#

R1449 510_0402_5%R1449 510_0402_5%

12

C1137

@C1137

@

470P_0402_50V7K

1

2

Overclocking mode stick

R1448 510_0402_5%R1448 510_0402_5%

12

@

C1138

470P_0402_50V7K

1

2

+3V_LAN

MDO0+

MDO0-

MDO1+

MDO2+

MDO2-

MDO1-

MDO3+

MDO3-

+3V_LAN

JRJ1

9

Green LED-

10

Green LED+

1

PR1+

2

PR1-

3

PR2+

4

PR3+

5

PR3-

6

PR2-

7

PR4+

8

PR4-

11

Yellow LED-

12

Yellow LED+

SANTA_130452-D ME@

MCT3

MCT2

MCT1

MCT0

DL1

@

14

G2

13

G1

@

DL2

@

1 2

LSE-200NX3216TRLF_1206-2

DL3

@

1 2

LSE-200NX3216TRLF_1206-2

DL4

@

1 2

LSE-200NX3216TRLF_1206-2

Reserve for EMI go rural solution

A A

Security Classification

2011/06/15 2012/07/11

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

LAN_Transformer

LA-7984P

26 48Wednesday, November 30, 2011

1

0.1

5

CX20671 High Definition Audio Codec SoC With Integrated Class-D Stereo Amplifier. An integrated 5 V to 3.3 V Low-dropout voltage regulator (LDO).

An integrated 3.3 V to 1.8V Low-dropout voltage regulator (LDO).

D D

+3VS

1

C981

C982

2

4.7U_0603_6.3V6K

R839 0 _0402_5%R839 0_0402_ 5%

+3VS

+3VALW

C C

1 2

R840 0_0402_ 5%@R840 0 _0402_5%@

1 2

HDA_RST_AUD IO#<12>

HDA_SYNC_A UDIO<12>

HDA_SDIN0<12>

HDA_SDOUT_A UDIO<12>

HDA_BITCLK_ AUDIO<12>

CX_GPIO0<32>

EAPD<30 >

EC_MUTE#<3 0>

EAPD active low 0=power down ex AMP 1=power up ex AMP

4.7U_0603_6.3V6K

1

C993

C992

2

1U_0603_10V4Z

@

R841 33_0402_5 %R841 33_0402 _5%

1 2

Internal SPEAKER

Short GND and GNDA on GND1 & GND2 on layout

B B

R853

@R853

@

1 2

0_0402_ 5%

R861

@R861

@

1 2

R863

@R863

@

0_0402_ 5%

1 2

R867

@R867

@

0_0402_ 5%

1 2

0_0402_ 5%

GND GNDA

PC Beep

EC Beep

ICH Beep

A A

FCH_SPKR<1 2>

C1009

C1010

5

1 2

0.1U_040 2_16V4Z

PC_BEEP 1 P C_BEEP

1 2

0.1U_040 2_16V4Z

1 2

33_0402 _5%

12

@

R859

R859 10K_040 2_5%

10K_040 2_5%

R858

BEEP#<30>

C978

0.1U_0402_16V4Z

1 2

4

1

C979

2

4.7U_0603_6.3V6K

1

C997

2

HDA_RST_AUD IO#

HDA_BITCLK_ AUDIO HDA_SYNC_A UDIO

HDA_SDOUT_A UDIO

PC_BEEP

R10030_04 02_5% @ R10030_04 02_5% @

12

R8500_0402 _5% R8500_0402 _5%

SPK_L2+ SPK_L1-

SPK_R2+ SPK_R1-

MIC1

1 2

WM-64PC Y_2P

45@

4

1

C980

2

@

0.1U_0402_16V4Z

10 mils

1

C998

2

U45

0.1U_0402_16V4Z

10U_0603_6.3V6M

@

9

RESET#

5

BIT_CLK

8

SYNC

6

SDATA_IN

4

SDATA_OUT

10

PC_BEEP

CX_GPIO0

38

GPIO0/EAPD#

37

GPIO1/SPK_MUTE#

40

DMIC_CLK

1

DMIC_1/2

11

LEFT+

13

LEFT-

16

RIGHT+

14

RIGHT-

Place colose to Codec chip

GNDA

1

2

C1017

C1018

0.1U_0402_16V4Z

@

1

C984

C983

2

1U_0603_10V4Z

0.1U_0402_16V4Z

7

2

18

29

3

VDD_IO

FILT_1.8

VAUX_3.3

DVDD_3.3

GND

CX20671 -21Z_QFN40_6 X6

41

+MICBIASC

12

R860

2.2K_04 02_5%

C1012 2.2U_0 603_6.3V4 ZC10 12 2.2U _0603_6.3 V4Z

1 2

FILT_1.65

C985

27

28

26

AVDD_5V

AVDD_3.3

1

C986

2

4.7U_0603_6.3V6K

LPWR_5.0

RPWR_5.0

AVDD_HP

CLASS-D_REF

SENSE_A

PORTB_R PORTB_L

B_BIAS

C_BIAS PORTC_R PORTC_L

PORTA_R PORTA_L

AVEE

FLY_P

FLY_N

AVDD_3.3 pinis output of

1

internal LDO. NOT connect to external supply.

2

0.1U_0402_16V4Z

1

C995

C994

@

2

4.7U_0603_6.3V6K

12 15 17

36

35 34 33

32 31 30

23 22

24

NC

25

NC

39

NC

21 19 20

C1005 1U_060 3_10V4ZC1005 1U_ 0603_10V4 Z

MIC_INR

MIC_INL

0.1U_0402_16V4Z

SENSE_A

1 2

+MICBIASB

+MICBIASC

3

+LDO_OUT_3 .3V

+5VS

C996

1

C1002

2

0.1U_0402_16V4Z

R1001 0_0402 _5%R1001 0_04 02_5%

1 2

1

C1006

@

2

SPK_R1SPK_R2+ SPK_L1SPK_L2+

wide 30MIL

3

2

22P_0402_50V8J

Layout Note:Path from +5VS to LPWR_5.0 RPWR_5.0 must be very low resistance (<0.01 ohms)

+5VS

1

C999

2

0.1U_0402_16V4Z

Please bypass caps very close to device.

C1003

C1003 C1004

C1004

MIC_INR

MIC_INL

1

C1007

2

0.1U_0402_16V4Z

L70 FBMA-L11-1 60808-121L MT_0603L70 FBMA-L11-160808-1 21LMT_0603

1 2

L71 FBMA-L11-1 60808-121L MT_0603L71 FBMA-L11-160808-1 21LMT_0603

1 2

L72 FBMA-L11-1 60808-121L MT_0603L72 FBMA-L11-160808-1 21LMT_0603

1 2

L73 FBMA-L11-1 60808-121L MT_0603L73 FBMA-L11-160808-1 21LMT_0603

1 2

1

C1000

C1001

@

2

0.1U_0402_16V4Z

4.7U_0603_6.3V6K

2.2U_060 3_6.3V4Z @

1 2 1 2

2.2U_060 3_6.3V4Z

2

4.7U_0603_6.3V6K

R1002 100_0402_ 1%R1002 100_0402_ 1%

SENSE_A

R999 2K_040 2_5%

EXT_MIC

R996 5.11K _0402_1%R996 5.11K _0402_1%

1 2

R997 20K_0 402_1%R9 97 20K_0402_ 1%

1 2

R998 39.2K _0402_1%R998 39.2K _0402_1%

1 2

AN@

12

R1000 & R700 for App & Nokia combo ear phone un-pop

EXT_MIC <32>

Internal MIC

R1005 15_040 2_5%R1005 15_ 0402_5%

1 2

R1006 15_040 2_5%R1006 15_ 0402_5%

1 2

Changed from 5.1ohm to 15ohm for "zi zi"noise.

4.7U_0603_6.3V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MIC_JD

Q107

LBSS138 LT1G_SOT-23-3

PLUG_IN_ R

Combo Jack detect (normal close)

13

D

2

G

S

CX_GPIO0

@

C1013

2011/10/12 2013/10/12

HP_OUTR <32> HP_OUTL <32>

33K_040 2_5%

R854

1 2

12

C1008

C1008 1U_0402 _6.3V6K

1U_0402 _6.3V6K

R857 47 K_0402_5 %

1 2

@

C1011

0.1U_040 2_16V4Z

@

1

@

2

close to Codec

1

C1014

C1015

2

220P_0402_50V7K

@

Compal Secret Data

Deciphered Date

2

C1016

@

1

2

220P_0402_50V7K

Headphone

EXT_MICEXT_MIC

SPK_R1-_ CONN SPK_R2+_ CONN SPK_L1-_ CONN SPK_L2+_ CONN

TVNST52302A B0 C/C SOT523

1

C988

C987

2

@

22P_0402_50V8J

+MICBIASB

R1000 4.7K_0402_5 %

External MIC

1

2

PLUG_IN<32 >

@ D41

@

1

C989

2

@

22P_0402_50V8J

AN@

D41

1

HDA_RST_AUD IO#

HDA_SYNC_A UDIO

HDA_SDOUT_A UDIO

R838

1 2

0_0402_ 5%

@

1

C991

2

@

22P_0402_50V8J

+3VS

MIC_JD PLUG_IN_ R

12

+5VS

2

3

2

3

1

Date: Sheet of

EMI

HDA_BITCLK_ AUDIO

Sense resistors must be connected same power that is used for VAUX_3.3

Port B Port A

12

R855

R855 10K_040 2_5%

10K_040 2_5%

R856

20K_040 2_5%

D42

@D4 2

@

TVNST52302A B0 C/C SOT523

Title

Size Docu ment Number Rev

Custom

PLUG_IN_ R

13

D

Q108

2

G

2N7002_ SOT23

G

2N7002_ SOT23

S

JSPK1

1

2

3

4

5

GND1

6

GND2

ACES_88 231-04001

ME@

Compal Electronics, Inc.

CX20671 Codec

LA8681P

1

R837

@R837

@

4.7K_04 02_5%

HDA_RST_AUD IO#

C990

@C990

@

100P_04 02_50V8J

ESD Reserve

27 48Wednesday, N ovember 30, 2011

+3VS

12

1

2

0.1

A

B

C

D

E

F

G

H

HDD CONN

JHDD1

1

GND

2

RX+

3

RX-

4

GND

5

TX-

6

TX+

7

GND

8

3.3V

9

3.3V

10

3.3V

11

GND

12

GND

13

GND

14

5V

15

5V

16

5V

17

GND

18

Reserved

19

GND

20

12V 12V 12V

ME@

JODD1

1 2 3 4 5 6 7 8 9

10

11 12

ACES_87056-01001-001

ME@

GND GND

1 2 3 4 5 6 7 8 9 10

GND GND

21 22

SUYIN_127043FB022G278ZR

23 24

S

SATA_FTX_DRX_P0 SATA_FTX_DRX_N0

SATA_FRX_DTX_N0 SATA_FRX_DTX_P0

+3VS

+5VS_HDD

1

@

C620

0.1U_0402_16V4Z

2

SATA_FTX_DRX_P1_15 SATA_FTX_DRX_N1_15

SATA_FRX_DTX_N1_15 SATA_FRX_DTX_P1_15

ODD_DETECT# +5V_ODD

ODD_DA#_R

C161 0.01U_0402_16V7KC161 0.01U_0402_16V7K

SATA_FTX_C_DRX_P0<11> SATA_FTX_C_DRX_N0<11>

SATA_FRX_C_DTX_N0<11>

1 1

+5VS_HDD +3VS

2 2

ODD CONN 15''

SATA_FTX_C_DRX_P1<11> SATA_FTX_C_DRX_N1<11>

SATA_FRX_C_DTX_N1<11> SATA_FRX_C_DTX_P1<11>

3 3

SATA_FRX_C_DTX_P0<11>

+5VS +5VS_HDD

1

C1076

C1076 1000P_0402_50V7K

1000P_0402_50V7K

2

J10

@ J10

@

112

JUMP_43X79

1

C616

0.1U_0402_16V4Z

2

ODD_DETECT#<12> ODD_DA#<30>

2

1

C617

C617 1U_0603_10V6K

1U_0603_10V6K

2

ODD_DA#_FCH<12>

1 2

C162 0.01U_0402_16V7KC162 0.01U_0402_16V7K

1 2

C1075 0.01U_0402_16V7KC 1075 0.01U_0 402_16V7K

1 2

C1074 0.01U_0402_16V7KC 1074 0.01U_0 402_16V7K

1 2

1

C1079

C1079 10U_0603_6.3V6M

10U_0603_6.3V6M

2

C969 0.01U_0402_16V7K

1 2

C968 0.01U_0402_16V7K

1 2

C934 0.01U_0402_16V7K15@C934 0.01U_0402_ 16V7K15@

1 2

C935 0.01U_0402_16V7K

1 2

R819 0_0402_5%@ R819 0_0402_5%@

1 2

R873 0_0402_5%@R873 0_0402_5%@

1 2

R820 0_0402_5%

1 2

R821 10K_0402_5%

+3VS

1 2

1 3

+3VS

15@

@

Q46 2N7002_SOT23@

@

D

G

2

ODD CONN 14''

JODD2

ME@JODD2

SATA_FTX_C_DRX_P1 SATA_FTX_C_DRX_N1

SATA_FRX_C_DTX_N1 SATA_FRX_C_DTX_P1

14@

C967 0.01U_0402_16V7K

1 2

C966 0.01U_0402_16V7K

1 2

14@

C965 0.01U_0402_16V7K14@C965 0.01U_0402_ 16V7K14@

1 2

C964 0.01U_0402_16V7K

1 2

14@

SATA_FTX_DRX_P1_14 SATA_FTX_DRX_N1_14

SATA_FRX_DTX_N1_14 SATA_FRX_DTX_P1_14

ODD_DETECT# +5V_ODD

ODD_DA#_R

1 2 3 4 5 6 7

8

9 10 11 12 13

ME@

GND RX+ RXGND TXTX+ GND

DP +5V +5V MD

GND1

GND

GND2

GND

TYCO_2-1759838-8~D

14 15

BT MODULE CONN

BT@

R814

R814 100K_0402_5%

100K_0402_5%

BT_ON#<11>

1 2

ODD_EN<11>

+3VS

BT@

C929

0.1U_0402_16V4Z

1 2

D

S

D

S

13

G

2

USB20_P6<12> USB20_N6<12>

BT_ACTIVE<29>

2

IN

+3VS_BT_R

Q81

Q81 PMV65XP_SOT23-3~D

PMV65XP_SOT23-3~D

BT@

short J12, no zero power ODD function

+5VS

12

@

R817

R817 10K_0402_5%

10K_0402_5%

1

OUT

GND

Q83

Q83 DTC124EKAT146_SC59-3

DTC124EKAT146_SC59-3

3

@

+3VS_BT

0_0603_5%

0_0603_5% R815

BT@R815

BT@

12

BTON_LED:NC

@

R818

1 2

100K_0402_5%

30mils

1

2

ACES_87213-0600G

ME@

J12

@ J12

@

112

JUMP_43X79

S

G

2

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z C930

C930

BT@

JBT1

1

2

3

4

5

7

5

G1

6

8

6

G2

2

D

13

Q82

Q82 PMV65XP_SOT23-3~D

PMV65XP_SOT23-3~D

@

C937

0.01U_0402_16V7K

+5V_ODD

1

2

C936

C936 10U_0603_6.3V6M

10U_0603_6.3V6M

1

C932

0.1U_0402_16V4Z

2

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2011/10/12 2013/10/12

E

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

F

Date: Sheet of

Compal Electronics, Inc.

HDD/ODD/BT

LA8681P

G

LA8681P

0.1

28 48Wednesday, November 30, 2011

H

0.1

A

B

C

D

E

Mini-Express Card for WLAN/WiMAX(Half)

+3VS_WLAN+3VS

J5

2

3.3V

GND

1.5V NC NC NC NC NC

GND

NC

PERST#

+3.3Vaux

GND

+1.5V

SMB_CLK

SMB_DATA

GND

USB_D-

USB_D+

GND

LED_WWAN#

LED_WLAN# LED_WPAN#

+1.5V

GND

+3.3V

GND

LPC_FRAME# <10,30> LPC_AD3 <10,30> LPC_AD2 <10,30> LPC_AD1 <10,30>

LPC_AD0 <10,30>

CLK_PCI_DB <10>

112

JUMP_43X79

@

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

54

PCI_RST#_R CLK_PCI_DB

100_0402_1%

R490

R491

100_0402_1%

1 2 1 2 1 2 1 2 1 2 1 2

+3VS_WLAN

WLAN_WAKE#

R492

R492 100K_0402_5%

100K_0402_5%

1 2

JWLN1

1

WAKE#

3

NC

5

NC

7

CLKREQ#

9

GND

11

REFCLK-

13

REFCLK+

15

GND

17

NC

19

NC

21

GND

23

PERn0

25

PERp0

27

GND

29

GND

31

PETn0

33

PETp0

35

GND

37

NC

39

NC

41

NC

43

NC

45

NC

47

NC

49

NC

51

NC

53

GND

TAITW_PFPET0-AFGLBG1ZZ4N0

ME@

LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 APU_PCIE_RST#

R480 0_0402_5%R480 0_0402_5%

FCH_PCIE_WAKE#<12,25>

1 1

BT_DISABLE#<11>

2 2

R525 0_0402_5%R525 0_0402_5%

1 2

BT_ACTIVE<28>

WLAN_CLKREQ#<12>

CLK_PCIE_WLAN#<10>

CLK_PCIE_WLAN<10>

PCIE_FRX_DTX_N1<10> PCIE_FRX_DTX_P1<10>

PCIE_FTX_C_DRX_N1<10> PCIE_FTX_C_DRX_P1<10>

EC_TX_P80_DATA<30,31> EC_RX_P80_CLK<30,31>

1 2

R481 0_0402_5%@R481 0_0402_5%@

1 2

1 2 1 2

For EC to detect debug card insert.

Reserve for SW mini-pcie debug card. Series resistors closed to KBC side.

LPC_FRAME#_R LPC_AD3_R LPC_AD2_R LPC_AD1_R LPC_AD0_R PCI_RST#_R CLK_PCI_DB

R493 0_0402_5%@R493 0_0402_5%@ R494 0_0402_5%@R494 0_0402_5%@ R495 0_0402_5%@R495 0_0402_5%@ R496 0_0402_5%@R496 0_0402_5%@ R497 0_0402_5%@R497 0_0402_5%@ R498 0_0402_5%@R498 0_0402_5%@

1

J6

1

JUMP_43X79

@

2

+1.5VS_WLAN

R484 0_0402_5%@R484 0_0402_5%@

1 2

R485 0_0402_5%R485 0_0402_5%

1 2

R486 0_0402_5%@R486 0_0402_5%@

1 2

R487 0_0402_5%@R487 0_0402_5%@

1 2

LPC_FRAME#_R LPC_AD3_R LPC_AD2_R LPC_AD1_R LPC_AD0_R

+3VS_WLAN+1.5VS

1

C1081

0.1U_0402_16V4Z

2

WL_OFF# <11>

APU_PCIE_RST# <10,15> +3VALW +3VS_WLAN

FCH_SMCLK0 <8, 9,12>

FCH_SMDAT0 <8,9,12>

USB20_N2 <12> USB20_P2 <12>

1

@

C1023

4.7U_0603_6.3V6K

2

+1.5VS

1

@

C1036

0.1U_0402_16V4Z

2

1

@

C1037

0.1U_0402_16V4Z

2

3 3

4 4

Close U33

C782

2200P_0402_50V7K

C784

2200P_0402_50V7K

REMOTE1+

1

2

REMOTE1-

REMOTE2+

1

@

2

REMOTE2-

0.1U_0402_16V4Z

+3VS

2

C785

1

Fintek thermal sensor placed near by VRAM

REMOTE1+

REMOTE1-

REMOTE2+

REMOTE2-

1

2

3

4

5

U33

VDD

DP1

DN1

DP2

DN2

EMC1403-2-AIZL-TR_MSOP10

SMCLK

SMDATA

ALERT#

THERM#

GND

Address 1001_101xb

Change from SA000029210 to SA000046C00 for main source

A

B

+3VS

12

R674

R674 10K_0402_5%

10K_0402_5%

@

10

9

8

7

6

EC_SMB_CK2 <5,16,30>

EC_SMB_DA2 <5,16,30>

REMOTE1+

C783

100P_0402_50V8J

REMOTE1-

REMOTE2+

C786

100P_0402_50V8J

REMOTE2-

REMOTE1,2+/-: Trace width/spa ce:10/10 mil Trace length:<8 "

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

1

@

2

1

@

2

Close to DDR

C

Q72

2

B

MMST3904-7-F_SOT323-3

E

3 1

Under WLAN

C

Q73

@

Q73

@

2

B

MMST3904-7-F_SOT323-3

E

3 1

Compal Secret Data

2011/10/12 2013/10/12

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Mini PCIE/Thermal IC

LA8681P

E

29 48Wednesday, November 30, 2011

0.1

L45

+3VALW +EC_AVCC

+3VALW

+3VS

12

R512

R512 10K_0402_5%

10K_0402_5%

@

+3VALW

+3VS

1

@

C1123

C1123 100P_0402_50V8J

100P_0402_50V8J

2

1 2

FBM-11-160808-601-T_0603

1 2

R502 47K_0402_5%R502 47K_0402_5%

R507 47K_0402_5%@ R507 47K_0402_5%@

R508 47K_0402_5%@ R508 47K_0402_5%@

EC_FAN_PWM

R518

R519

R523

2.2K_0402_5%

C1042

0.1U_0402_16V4Z

1 2

L46 FBM-11-160808-601-T_0603L46 FBM-11-160808-601-T_0603

@

12

C1116 22P_0402_50V8J

C1117

0.1U_0402_16V4Z

1 2

R524

2.2K_0402_5%

EC_SMB_CK2

EC_SMB_DA2

1

@

C1124

C1124 100P_0402_50V8J

100P_0402_50V8J

2

EC_SMB_CK1

EC_SMB_DA1

2.2K_0402_5%

2.2K_0402_5% R516

2

1

ECAGND

2

1

1000P_0402_50V7K

2

@

12

R501 10_ 0402_5%

KSO[0..17]<32>

KSI[0..7]< 32>

KSO1

KSO2

C1113

EC_SMB_CK2 < 5,16,29> EC_SMB_DA2 < 5,16,29>

RTC_CLK<10,14>

KSO[0..17]

KSI[0..7]

EC_TX_P80_DATA<29,31> EC_RX_P80_CLK<29,31>

EC_FAN_PWM<31>

C1038

0.1U_0402_16V4Z

C1038

0.1U_0402_16V4Z

1

2

GATEA20<12> KBRST#<12>

LPC_FRAME#<10,29>

LPC_AD3<10,29> LPC_AD2<10,29> LPC_AD1<10,29> LPC_AD0<10,29>

CLK_PCI_EC<10,14>

PLT_RST#<10,25>

EC_SCI#<12>

BATT_LEN#<37>

EC_SMB_CK1<37,38> EC_SMB_DA1<37,38>

PM_SLP_S3#<12> PM_SLP_S5#<12>

EC_SMI#<12> CMOS_ON#<22>

ODD_DA#<28>

EC_INVT_PWM<22>

EC_TACH<31>

FCH_PWRGD<12,44>

C1040

0.1U_0402_16V4Z

C1040

0.1U_0402_16V4Z

C1039

0.1U_0402_16V4Z

C1039

0.1U_0402_16V4Z

1

2

SERIRQ<10>

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17

EC_SMB_CK2 EC_SMB_DA2

EC_SMI#

EC_PME# EC_TX_P80_DATA EC_RX_P80_CLK

T98T98

1 2

R513 0_0402_5%R513 0_0402_5%

100K_0402_5%

+3VALW

C1041

0.1U_0402_16V4Z

C1041

0.1U_0402_16V4Z

1

2

LPC_AD3 LPC_AD2 LPC_AD1 BATT_TEMP LPC_AD0

EC_RST# EC_SCI#

EC_SMB_CK1 EC_SMB_DA1

XCLKI XCLKO

R516

1 2

10

12 13 37 20 38

55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82

77 78 79 80

14 15 16 17 18 19 25 28 29 30 31 32 34 36

122 123

12

POP for susclk implemented 20100810

C1096

1000P_0402_50V7K

C1096

1000P_0402_50V7K

C1095

1000P_0402_50V7K

C1095

1000P_0402_50V7K

1

2

1

GATEA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ

4

LPC_FRAME#

5

LPC_AD3

7

LPC_AD2

8

LPC_AD1

LPC & MISC

LPC_AD0

CLK_PCI_EC PCIRST#/GPIO05 EC_RST# EC_SCII#/GPIO0E GPIO1D

KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 KSO6/GPIO26 KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49

EC_SMB_CK1/GPIO44 EC_SMB_DA1/GPIO45 EC_SMB_CK2/GPIO46 EC_SMB_DA2/GPIO47

6

PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 GPIO0A GPIO0B GPIO0C GPIO0D EC_INVT_PWM/GPIO11 FAN_SPEED1/GPIO14 EC_PME#/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 PCH_PWROK/GPIO18 SUSP_LED#/GPIO19 NUM_LED#/GPIO1A

XCLKI/GPIO5D XCLKO/GPIO5E

C1119

C1119 20P_0402_50V8

20P_0402_50V8

1

2

Int. K/B

Int. K/B Matrix

Matrix

SM Bus

9

PS2 Interface

+EC_AVCC

+3VLP

22

33

96

111

125

EC_VDD0

EC_VDD/VCC

PWM Output

AD Input

DA Output

CPU1.5V_S3_GATE/GPXIOA00

SPI Device Interface

SPI Flash ROM

GPIO

H_PROCHOT#_EC/GPXIOA06

GPO

GPIO

GPI

GND/GND

GND0

11

24

35

94

113

67

GPIO0F

BEEP#/GPIO10

EC_VDD/AVCC

BATT_CHG_LED#/GPIO52

BATT_LOW_LED#/GPIO55

EC_RSMRST#/GPXIOA03 EC_LID_OUT#/GPXIOA04

PROCHOT_IN/GPXIOA05

VCOUT0_PH/GPXIOA07

PBTN_OUT#/GPXIOA09

PCH_APWROK/GPXIOA10

PECI_KB9012/GPXIOD07

AGND/AGND

69

ECAGND

GPIO12

ACOFF/GPIO13

BATT_TEMP/GPIO38

GPIO39

ADP_I/GPIO3A

GPIO3B GPIO42

IMON/GPIO43

DAC_BRIG/GPIO3C EN_DFAN1/GPIO3D

IREF/GPIO3E

CHGVADJ/GPIO3F

EC_MUTE#/GPIO4A

USB_EN#/GPIO4B

CAP_INT#/GPIO4C

EAPD/GPIO4D

TP_CLK/GPIO4E

TP_DATA/GPIO4F

WOL_EN/GPXIOA01

HDA_SDO/GPXIOA02

VCIN0_PH/GPXIOD00

SPIDI/GPIO5B

SPIDO/GPIO5C

SPICLK/GPIO58

SPICS#/GPIO5A

ENBKL/GPIO40

PECI_KB930/GPIO41

FSTCHG/GPIO50

CAPS_LED#/GPIO53

PWR_LED#/GPIO54

SYSON/GPIO56 VR_ON/GPIO57

PM_SLP_S4#/GPIO59

BKOFF#/GPXIOA08

SA_PGOOD/GPXIOA11

AC_IN/GPXIOD01

EC_ON/GPXIOD02

ON/OFF/GPXIOD03

LID_SW#/GPXIOD04

SUSP#/GPXIOD05

GPXIOD06

V18R

KB9012QF A3 LQFP 128P_14X14

U31

21 23 26 27

63 64 65 66 75 76

68 70 71 72

83 84 85 86 87 88

97 98 99 109

119 120 126 128

73 74 89 90

CAPS_LED#

91 92 93

SYSON

95 121 127

100

EC_LID_OUT#

101

Turbo_V

102

H_PROCHOT#_EC

103 104 105 106 107 108

110 112 114 115 116 117 118

V18R

124

BEEP#

ACOFF

BRDID

T59T59

USB_ON# INT#

TP_CLK TP_DATA

T60T60

ENBKL RST#

VSB_ON_R

BKOFF# PBTN_OUT#

ACIN EC_ON

LID_SW# SUSP#

1

2

C1118

4.7U_0603_6.3V6K

BEEP# <27> NOVO# <32 > ACOFF <38>

BATT_TEMP < 37>

ADP_I <37,38>

EC_MUTE#

EC_MUTE# <27>

EAPD <27>

TP_CLK <32>

TP_DATA <32>

VGATE <44>

NTC_V <37>

ENBKL <22>

LAN_PWR_ON# <25>

BATT_CHG_LED# <32>

CAPS_LED# <32> PWR_LED# <32>

BATT_LOW_LED# <32>

SYSON <35,40>

VR_ON <44>

EC_RSMRST# <12>

EC_LID_OUT# <12>

Turbo_V <37>

BKOFF# <22>

PBTN_OUT# <12>

VGA_GATE# <12>

ACIN <16,38> EC_ON <32,39> ON/OFF <32> LID_SW# <32>

SUSP# <35,40,41,43>

R503 10K_0402_5%R503 10K_0402_5%

USB_ON# <32,33,34>

MAINPWON <37,39>

1 2

+3VALW

11/08 Increase for LAN S5 power saving

R1450

@R1450

@

0_0402_5%

12

@

R757

0_0402_5%

H_PROCHOT#_EC

12

VSB_ON <3 7>

2

G

13

D

S

PROCHOT <37>

Q109

2N7002H_SOT23-3

LAN_WAKE#<25>

TP_CLK

R499 4.7K_0402_5%R499 4.7K_0402_5%

TP_DATA

BATT_TEMP

ACIN

USB_ON#

BRDID

1 2

R500 4.7K_0402_5%R500 4.7K_0402_5%

1 2

C1114 100P_0402_50V8JC1114 100P_0402_50V8J

1 2

C1115 100P_0402_50V8JC1115 100P_0402_50V8J

R504 10K_0402_5%R504 10K_0402_5%

1 2

Ra

R505 100K_0402_5%R505 100K_0402_5%

1 2

R506 33K_0402_5%R506 33K_0402_5%

1 2

Rb

ID BRD I D R a Rb Vab

x

+3VALW

1 2

EC_TACH

SUSP#

R517

R517 10K_0402_5%

10K_0402_5%

0

8.2K

18K

33K

+3VS

1

@

C1043

C1043 1000P_0402_50V7K

1000P_0402_50V7K

2

EC_PME#

JCAP1

1

2

3

4

5

6

7

8

9

GND1

10

GND2

ACES_50521-0084N-P01

ME@

R10 MP0

R03 PVT

1

R02 DVT

2

3

H_PROCHOT# <5,10,37>

1 2

R520 0_0402_5%R520 0_0402_5%

RST#

+3VS

EC_SMB_DA2 EC_SMB_CK2

INT#

+5VS

100K

For Cap sensor function

+5VS

+5VALW

+3VALW

0V

0.25V

0.5V

0.82VR01 EVT

12

R509

R509 10K_0402_5%

10K_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/10/12 2013/10/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

KB9012/Cap sensor

LA8681P

30 48Wednesday, November 30, 2011

0.1

5

4

3

2

1

D D

FAN CONN

EC DEBUG PORT

+5VS

JFAN1

1

C1082

C1082 10U_060 3_6.3V6M

10U_060 3_6.3V6M

2

C C

EC_TACH<30>

EC_FAN_ PWM<30>

2

3

4

5

G5

6

G6

ACES_85 205-04001

ME@

H1

H1 HOLEA

HOLEA

1

H_3P8

H2

H2 HOLEA

HOLEA

1

H_3P8

H3

H3 HOLEA

HOLEA

1

H_3P8

EC_TX_P 80_DATA<29,30> EC_RX_P 80_CLK<2 9,30>

VGA_L VGA_RCPU

+3VALW

H4

H4 HOLEA

HOLEA

1

H_3P3

H5

H5 HOLEA

HOLEA

1

H_3P3

BA

H10

H6 HOLEA

HOLEA

B B

1

H_2P8

HOLEA

1

H_2P8

HOLEA

1

H_2P8

H8

H7

H6

H10

H9

HOLEA

1

H_2P8

2P8 * 9 pcd

H11

H11 HOLEA

HOLEA

1

H_2P8

H12

H12 HOLEA

HOLEA

1

H_2P8

JECDP1

1

2

3

4

ACES_85 205-0400

ME@

H13

H14

HOLEA

1

H_2P8

D

FD1FD1

FD4FD4

FD3FD3

FD2FD2

1

M/B

橢橢橢

L R

H15

H15 HOLEA

HOLEA

1

H_3P0X4 P0N

1

H16

H16 HOLEA

HOLEA

1

H_3P0X4 P0N

1

M/B

橢橢

H17

H17 HOLEA

HOLEA

1

H_3P0N

E

A A

Security Class ification

2011/10/ 12 2013/10/ 12

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/10/ 12 2013/10/ 12

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Numb er Rev

B

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

FAN/SCREW/EC Debug

LA8681P

31 48Wednesd ay, November 30, 201 1

1

0.1

ON/OFF switch

Power Button

TOP Side

Bottom Side

EC_ON<30, 39>

SW3 SMT1-05_4P

SMT1-05_4P

1

2

ON/OFFBTN#

@SW3

@

5

6

J13

1 2

SHORT PADS

3

4

1

DAN202UT106_SC70-3

@

R641

R641 10K_0402_5%

10K_0402_5%

1 2

R720

1 2

0_0402_5%

D24

@D24

@

+3VLP +3VALW

R701

R701 100K_0402_5%

100K_0402_5%

1 2

3

2

13

D

@

2

G

Q106

G

Q106 2N7002_SOT23-3

2N7002_SOT23-3

S

R535 100K_0402_5%

100K_0402_5%

1 2

KSI[0..7]

KSO[0..17]

KSO2 KSO1

@R535

@

ON/OFF <30>

51_ON# <36>

KSO15

KSO6

KSO8

KSO13

KSO12

KSO11

KSO10

KSO3

KSO4

KSI0

KSO0

C940 100P_0402_50V8J@C940 100P_0402_50V8J@

1 2

C942 100P_0402_50V8J@C942 100P_0402_50V8J@

1 2

C944 100P_0402_50V8J@C944 100P_0402_50V8J@

1 2

C946 100P_0402_50V8J@C946 100P_0402_50V8J@

1 2

C948 100P_0402_50V8J@C948 100P_0402_50V8J@

1 2

C950 100P_0402_50V8J@C950 100P_0402_50V8J@

1 2

C952 100P_0402_50V8J@C952 100P_0402_50V8J@

1 2

C954 100P_0402_50V8J@C954 100P_0402_50V8J@

1 2

C956 100P_0402_50V8J@C956 100P_0402_50V8J@

1 2

C958 100P_0402_50V8J@C958 100P_0402_50V8J@

1 2

C960 100P_0402_50V8J@C960 100P_0402_50V8J@

1 2

C962 100P_0402_50V8J@C962 100P_0402_50V8J@

1 2

KSI[0..7] <30>

KSO[0..17] <30>

CONN PIN define need double check

INT_KBD Conn.

KSO16

C938 100P_0402_50V8J@C938 100P_0402_50V8J@

1 2

KSO17

C939 100P_0402_50V8J@C939 100P_0402_50V8J@

1 2

C941 100P_0402_50V8J@C941 100P_0402_50V8J@

1 2

KSO7

C943 100P_0402_50V8J@C943 100P_0402_50V8J@

1 2

KSI2

C945 100P_0402_50V8J@C945 100P_0402_50V8J@

1 2

KSO5

C947 100P_0402_50V8J@C947 100P_0402_50V8J@

1 2

KSI3

C949 100P_0402_50V8J@C949 100P_0402_50V8J@

1 2

KSO14

C951 100P_0402_50V8J@C951 100P_0402_50V8J@

1 2

KSI7

C953 100P_0402_50V8J@C953 100P_0402_50V8J@

1 2

KSI6

C955 100P_0402_50V8J@C955 100P_0402_50V8J@

1 2

KSI5

C957 100P_0402_50V8J@C957 100P_0402_50V8J@

1 2

KSI4

C959 100P_0402_50V8J@C959 100P_0402_50V8J@

1 2

KSO9

C961 100P_0402_50V8J@C961 100P_0402_50V8J@

1 2

KSI1

C963 100P_0402_50V8J@C963 100P_0402_50V8J@

1 2

Reserve for ESD.

KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6

KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15 KSO16 KSO17

JKB1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

ACES_88514-3001

ME@

FOR 14"

JKB2

26

GND2

25

GND1

KSI1

24

KSI7

23

KSI6

22

KSO9

21

KSI4

20

KSI5

19

KSO0

18

KSI2

17

KSI3

16

KSO5

15

KSO1

14

KSI0

13

KSO2

12

KSO4

11

KSO7

10

KSO8

9

KSO6

8

KSO3

7

KSO12

6

KSO13

5

KSO14

4

KSO11

3

KSO10

2

KSO15

31

GND

32

GND

1

ACES_88514-2401

ME@

Power Button Board Conn. 8pin

R532

@R532

@

100K_0402_5%

NOVO#<30>

ON/OFF

51_ON#

NOVO#

R725

0_0402_5%

1 2

R722 0_0402_5%

0_0402_5%

@R722

@

FOR 14"

White

PWR_LED#<30>

BATT_LOW_LED#

BATT_LOW_LED#<30>

BATT_CHG_LED#

BATT_CHG_LED#<30>

CAPS_LED#<30>

+3VALW

PWR_LED#

Orange

BATT_LOW_LED#

2nd source SC500005910 S LED LTST-C191KFKT-5A 0603 ORANGE

R615

0_0402_5%

0.1U_0402_16V4Z

White

BATT_CHG_LED#

White

CAPS_LED#

12

1

14@

C716

2

+VCC_LID

Lid Switch

S-5711ACDL-M3T1S_SOT23-3

L R

SW4 SMT1-05_4P

SMT1-05_4P

5

6

4

3

R628 0_0402_5%

0_0402_5%

14@SW4

14@

R629 0_0402_5%

0_0402_5%

2

SW_L

1

+3VALW+3VLP

R642

R642 100K_0402_5%

100K_0402_5%

1 2

19-213A-T1D-CP2Q2HY-3T_WHITE

LED2

HT-191UD5_AMBER

LED5

19-213A-T1D-CP2Q2HY-3T_WHITE

2

OUTPUT

1

nonBBH@R628

nonBBH@

12

14@R629

14@

12

D26

2

3

DAN202UT106_SC70-3

14@

LED1

R644

21

12

300_0402_5%

14@LED2

14@

R764

12

21

470_0402_5%

14@LED5

14@

R765

21

12

300_0402_5%

14@

LED6

VDD

GND

U37

TP_2

TP_3 SW_R

21

R616

1 2

100K_0402_5%

3

14@U37

14@

R8

300_0402_5%

LID_SW#

2

14@

C717

C717 10P_0402_50V8J

10P_0402_50V8J

1

4

3

12

5

1

14@R 644

14@

14@R 764

14@

14@R 765

14@

14@R8

14@

6

NOVO_BTN#

+5VALW

+3VALW

+5VALW

+5VS

SW5 SMT1-05_4P

SMT1-05_4P

2

1

LID_SW# <30>

14@SW5

14@

R626 0_0402_5%

0_0402_5%

R627 0_0402_5%

0_0402_5%

nonBBH@R626

nonBBH@

12

14@R627

14@

12

+5VALW

JPWRB1

ME@

1

NOVO_BTN# ON/OFFBTN#

2

3

D25 PJSOT24C 3P C/A SOT-23

PJSOT24C 3P C/A SOT-23

1

IO board USB port

0.1U_0402_16V4Z

C1020

12

USB20_P1 USB20_P5 USB20_P5_R

1

2

3

5

3

G1

4

6

4

G2

E-T_7182K-F04N-00R

@D25

@

+5VALW +USB_VCCB

U42

1

GND

VOUT

2

VOUT7VIN

VIN3VOUT

@L47

@

4

EN

G547I2P81U_MSOP8

2

USB20_P1_R

3

FLG

EMI request

USB_ON#<30,33,34>

L47

1

4

WCM-2012-900T_4P

+USB_VCCA

8

6 5

USB20_N5USB20_N1_R USB20_N5_RUSB20_N1

@

1

C1019

C1019 1000P_0402_50V7K

1000P_0402_50V7K

2

L57

@L57

@

1

4

WCM-2012-900T_4P

USB_OC2# <12>

J14

@J14

@

2 1

2MM

check U40 !

2

3

+USB_VCCB

+5VS

check BOM structure

AN@

R894 0_0402_5%

R895 0_0402_5%

A@

12

C734

220U_6.3V_M

6.3Φ * 5.9 SF000001500

CR_GND

+USB_VCCB

1

+

2

Card Reader/Audio Jack SB CONN

HP_OUTR<27> HP_OUTL<27>

EXT_MIC<27> PLUG_IN<27>

+3VS

1

C733

C733 470P_0402_50V7K

470P_0402_50V7K

2

USB20_N1<12> USB20_P1<12>

USB20_N5<12> USB20_P5<12>

CX_GPIO0<27>

+MICBIASB

R687 0_0402_5%R687 0_0402_5%

12

R686 0_0402_5%R686 0_0402_5%

12

R534 0_0402_5%R534 0_0402_5%

12

R533 0_0402_5%R533 0_0402_5%

12

R690 0_0402_5%AN@R 690 0_0402_5%AN@

12

R689 0_0402_5%AN@R 689 0_0402_5%AN@

12

R699 0_0402_5%A@R699 0_0402_5%A@

12

0_0402_5%A@

12

R691

USB20_N1_R USB20_P1_R

CR_GND USB20_N5_R USB20_P5_R

JCR1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

GND

18

GND

ACES_51524-0160N-001

ME@

reserve for EMI, which follow GIWG5/6

pin 6 5 4 3 2 1

FOR 15"

LED B/D Conn

+5VALW +3VALW

+5VS

LID_SW#

PWR_LED# BATT_LOW_LED# BATT_CHG_LED# CAPS_LED# SW_R SW_L

TP_1

TP_2

JLED1

1

2

3

4

5

6

7

8

9

10

11

12

13

GND

14

GND

ACES_88058-120N

ME@

14 VDD CLK DAT L R GND

15 VDD CLK DAT GND L R

BB-H VDD CLK DAT GND NC NC

BB-L VDD CLK DAT GND L R

TP_CLK<30> TP_DATA<30>

100P_0402_50V8J

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

1

@

C697

C698

C698 100P_0402_50V8J

100P_0402_50V8J

2

PSOT24C_SOT23-3

Compal Secret Data

2011/10/12 2013/10/12

Compal Secret Data

3

@

D15

Deciphered Date

1

R889 0_0402_5%

+5VS

nonBBH@

R890 0_0402_5%

+3VS

BBH@

C696 0.1U_0402_16V4ZC696 0.1U_0402_16V4Z

2

15@

R643

R643 0_0402_5%

0_0402_5%

R619

R619 0_0402_5%

0_0402_5%

14@

12

TP_3

TP_1

To TP/B Conn.

JTP1

8

GND

7

GND

6

TP_CLK TP_DATA TP_3 TP_2

TP_1

0.1U_0402_10V6K

@

6

5

4

3

2

1

ACES_88058-060N

ME@

1

C541

C540

@

2

0.1U_0402_10V6K

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet of

Compal Electronics, Inc.

KBD/PWR/CR/LED/TP Conn.

LA8681P

32 48Wednesday, November 30, 2011

0.1

A

B

C

D

E

1 1

C976

0.1U_0402_16V4Z

12

@

2 2

+5VALW +USB_VCCA

USB_ON#<30,32,34>

@

U40

1

GND

VOUT

2

VOUT

VIN VIN3VOUT

4

FLG

EN

G547I2P81U_MSOP8

8 7 6 5

@

1

C977

C977 1000P_0402_50V7K

1000P_0402_50V7K

2

USB_OC1# <12>

Right Ext.USB FFC Conn.

ME@

ACES_88058-060N

1

2

3

4

5

6

7

GND

8

GND

JUSB4

USB20_P0<12>

USB20_N0<12>

W=80mils

R836 0_0402_5%R836 0_0402_5% R835 0_0402_5%R835 0_0402_5%

12 12

3

USB20_P0_R

USB20_N0_R

2

WCM-2012-900T_ 4P

USB20_P0 USB20_P0_R

USB20_N0 USB20_N0_R

3 3

Update to SM070001S00 for EMI request

WCM-2012-900T_ 4P

4

1

L69

3

2

D40PJDLC05_SOT23-3 @D40PJDLC05_SOT23-3 @

+USB_VCCA

1

C974

220U_6.3V_M

6.3Φ * 5.9 SF000001500

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

1

+

C975

C975 470P_0402_50V7K

470P_0402_50V7K

2

Compal Secret Data

2011/10/12 2013/10/12

C

Compal Secret Data

1

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

USB cable port

LA8681P

33 48Wednesday, November 30, 2011

E

0.1

5

4

3

2

1

For EMI/ESD request

D23

@

U3RXDN1 U3RXDN1

U3RXDP1

D D

0.1U_0402_16V7K

C C

USB30_N10<12>

USB30_P10<12>

USB30_FTX_DRX_P0<12>

USB30_FTX_DRX_N0<12>

USB30_FRX_DTX_P0<12>

USB30_FRX_DTX_N0<12>

+USB3_VCCA +USB3_VCCA

B B

A A

U3TXDP1

U3TXDN1 U2DP1

U2DN1 U3RXDP1

U3RXDN1

+5VALW +USB3_VCCA

C692

1 2

USB_ON#<30,32,33>

C847

C849

1 2

4

0.1U_0402_16V7K

W=80mils

U39

GND VIN VIN3VOUT EN

G547I2P81U_MSOP8

VOUT VOUT

FLG

8 7 6 5

2A/Active Low

U3TXDP1_L

U3TXDN1_L

USB_OC0# <12>

@

1

C1024

C1024 1000P_0402_50V7K

1000P_0402_50V7K

2

USB30_N11<12>

USB30_P11<12>

USB30_FTX_DRX_P1<12>

USB30_FTX_DRX_N1<12>

USB30_FRX_DTX_P1<12>

USB30_FRX_DTX_N1<12>

LP1

W=80mils W=80mils

JUSB2

9

SSTX+

1

VBUS

8

SSTX-

3

D+

7

GND

2

D-

6

SSRX+

4

GND

5

SSRX-

TAITW_PUBAU1-09FNLSC NN4H0

ME@

GND GND GND GND

10 11 12 13

U3TXDP2

U3TXDN2 U2DP2

U2DN2 U3RXDP2

U3RXDN2

C848

C850

LP2

+USB3_VCCA

1

C749

C748

1

+

2

470P_0402_50V7K

220U_6.3V_M

1 2

JUSB3

9

SSTX+

1

VBUS

8

SSTX-

3

D+

7

GND

2

D-

6

SSRX+

4

GND

5

SSRX-

TAITW_PUBAU1-09FNLSC NN4H0

ME@

U3TXDP2_L

0.1U_0402_16V7K

U3TXDN2_L

0.1U_0402_16V7K

10

GND

11

GND

12

GND

13

GND

U3TXDN1

U3TXDP1

YSCLAMP0524P_SLP2510P8-10-9

U3RXDN2

U3RXDP2

U3TXDP2

YSCLAMP0524P_SLP2510P8-10-9

U3TXDN1_L U3TXDN1

USB30_FRX_DTX_N0 U3RXDN1

USB30_FRX_DTX_P0 U3RXDP1

USB30_N10

USB30_P10

U3TXDN1_L

USB30_FRX_DTX_N0

USB30_P10

USB30_N10

@

10

9

8

7

6 5

6

@

10

9

8

7

6 5

6

WCM-2012-900T_ 4P

1

4

L49

WCM-2012-900T_ 4P

1

4

L50

WCM-2012-900T_ 4P

1

4

L51

R544

1 2

R545

1 2

R546

1 2

R547

1 2

R550

1 2

R551

1 2

@L49

@

@L50

@

D29

1

2

4

3

8

1

2

4

3

8

1

U3RXDP1

2

U3TXDN1

4

U3TXDP1

5

3

U3RXDN2

1

U3RXDP2

2

U3TXDN2U3T XDN2

4

U3TXDP2

5

3

2

3

2

3

2

3

U3TXDN1

0_0402_5%

U3TXDP1U3TXDP1_L

0_0402_5%

U3RXDN1

0_0402_5%

U3RXDP1USB30_FRX_DTX_P0

0_0402_5%

U2DP1

0_0402_5%

U2DN1

0_0402_5%

U2DP1

U2DP2

U3TXDP1U3TXD P1_L

U2DN1

U2DP1

USB30_FRX_DTX_N1

D22

@

3

I/O2

2

GND

1

I/O1

AZC099-04S.R7G_SOT23- 6

D30

@

3

I/O2

2

GND

1

I/O1

AZC099-04S.R7G_SOT23- 6

U3TXDN2_L U3TXDN2

U3TXDP2_L U3TXDP2

USB30_FRX_DTX_N1 U3RXDN2

USB30_FRX_DTX_P1 U3RXDP2

USB30_N11 U2DN2

U3TXDN2_L

USB30_P11

USB30_N11

1 2

6

I/O4

5

VDD

4

I/O3

6

I/O4

5

VDD

4

I/O3

WCM-2012-900T_ 4P

1

4

L53

@L53

@

WCM-2012-900T_ 4P

1

4

L54

@L54

@

WCM-2012-900T_ 4P

1

4

L55

@

U3TXDN2

R631

0_0402_5%

U3TXDP2U3TXDP2_L

R632

0_0402_5%

U3RXDN2

R633

0_0402_5%

U3RXDP2USB30_FR X_DTX_P1

R634

0_0402_5%

U2DP2

R635

0_0402_5%

U2DN2

R636

0_0402_5%

U2DN1

U2DN2

2

3

2

3

2

3

2

3

2

3

2

3

+5VALW

U2DP2USB30_P11

Security Classification

2011/10/12 2013/10/12

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

2011/10/12 2013/10/12

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Left USB3.0

LA8681P

34 48Wednesday, November 30, 2011

1

0.1

A

B

C

D

E

+3VALW TO +3VS+5VALW TO +5VS

U35

U34

+5VALW

DMN3030LSS-13_SOP8L-8

8

1

C702

C702 10U_0603_6.3V6M

1 1

10U_0603_6.3V6M

2

+VSB

2

G

+1.1VALW to +1.1VS

SUSP

1

2

+VSB

2

G

2 2

7

5

R584

R584 20K_0402_5%

20K_0402_5%

5VS_GATE

10K_0402_5%

13

D

Q59

Q59 2N7002K_SOT23-3

2N7002K_SOT23-3

S

+1.1VALW +1.1VS

C712

C712 10U_0603_6.3V6M

10U_0603_6.3V6M

12

75K_0402_5%

75K_0402_5% R594

R594

1.1VS_GATE 1.1VS_GATE_R

13

D

Q65

2N7002K_SOT23-3

S

U34

+5VS

1 2

1

36

C703

C703 10U_0603_6.3V6M

10U_0603_6.3V6M

1

C1

0.1U_0402_25V6

2

U36

1 2 36

4

1

C4

0.1U_0402_25V6

2

1

C713

C713 10U_0603_6.3V6M

10U_0603_6.3V6M

2

1

2

4

5VS_GATE_R 3VS_GATE_R

R587

12

DMN3030LSS-13_SOP8L-8

8 7

5

R669

1 2

160K_0402_1%

1

C708

@C708

@

0.1U_0603_25V7K

2

C715

@C715

@

0.1U_0603_25V7K

1

C704

C704 1U_0603_10V6K

1U_0603_10V6K

2

1

C714

C714 1U_0603_10V6K

1U_0603_10V6K

2

12

R582

R582 470_0603_5%

470_0603_5%

@

13

D

S

12

13

D

S

SUSP

2

G

Q56

Q56 2N7002_SOT23

2N7002_SOT23

@

R590

R590 470_0603_5%

470_0603_5%

@

SUSP

2

G

Q62

@

Q62

@

2N7002_SOT23

SUSP

1

C705

C705 10U_0603_6.3V6M

10U_0603_6.3V6M

2

+VSB

12

R585

R585 47K_0402_5%

47K_0402_5%

3VS_GATE

13

D

2

G

2N7002K_SOT23-3

S

+3VALW

DMN3030LSS-13_SOP8L-8

8 7

5

Q60

U35

+3VS

1 2

1

36

C706

C706 10U_0603_6.3V6M

10U_0603_6.3V6M

1

C2

0.1U_0402_25V6

2

SUSP

2

DTC124EKAT146_SC59-3

4

R668

1 2

43K_0402_5%

SUSP<42>

SUSP#<30,40,41,43> SYSON<30,40>

1

C707

C707 1U_0603_10V6K

1U_0603_10V6K

2

1

C709

@C709

@

0.1U_0603_25V7K

2

R591

R591 220K_0402_5%

220K_0402_5%

1 2

Q63

2

IN

+5VALW+RTCBATT

12

1

3

12

13

D

S

@

R592

R592 100K_0402_5%

100K_0402_5%

OUT

GND

R583

R583 470_0603_5%

470_0603_5%

@

SUSP

2

G

Q57

Q57 2N7002_SOT23

2N7002_SOT23

@

+1.5V to +1.5VS

C699

10U_0603_6.3V6M

+5VALW

12

100K_0402_5%

100K_0402_5% R586

R586

1.5VS_GATE 1.5VS_GATE_R

13

D

SUSP#SUSP

D

2

G

S

+1.5V

1

AP2301GN-HF_SOT23-3

2

R588

22K_0402_1%

1 2

Q61

Q61 2N7002K_SOT23-3

2N7002K_SOT23-3

SYSON#

SYSON

Q55

3 1

2

1

C3

0.1U_0402_25V6

2

R593

100K_0402_5%

2

IN

+5VALW

@

12

1

OUT

GND

3

+1.5VS

1

C700

C700 10U_0603_6.3V6M

10U_0603_6.3V6M

2

1

C711

0.1U_0603_25V7K

2

Q64

Q64 DTC124EKAT146_SC59-3

DTC124EKAT146_SC59-3

@

@C711

@

1

C701

C701 1U_0603_10V6K

1U_0603_10V6K

2

12

R581

R581 470_0603_5%

470_0603_5%

@

13

D

Q58

S

2N7002_SOT23

@

SUSP

2

G

3 3

+1.5V +0.75VS

12

R597

R597 470_0603_5%

470_0603_5%

@

13

D

SYSON# SUSP

2

G

Q66

S

2N7002_SOT23

@

4 4

12

R598

R598 470_0603_5%

470_0603_5%

@

13

D

2

G

Q67

S

2N7002_SOT23

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2011/10/12 2013/10/12

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

DC Interface

LA8681P

35 48Wednesday, November 30, 2011

E

0.1

5

4

3

2

1

2

12

PQ104

@PQ104

@

2

VIN

12

100P_0402_50V8J

PC103

PC104

1000P_0402_50V7K

VIN

@PD103

@

PD103

1 2

LL4148_LL34-2

51ON-1

12

PR118

PR119

@

68_1206_5%

13

@

68_1206_5%

VS

12

PC113

0.1U_0603_25V7K

DC030006J00

PL101

PF101

7A_24VDC_429007.WRML

4

3

2

D D

2

1

4602-Q04C-09R 4P P2.5

4602-Q04C-09R 4P P2.5 JDCIN1

JDCIN1

ME@

APDIN1APDIN

21

12

PC101

SMB3025500YA_2P

12

1000P_0402_50V7K

PL101

1 2

100P_0402_50V8J

PC102

Unpop for KB9012

PD104

@PD104

@

LL4148_LL34-2

CHGRTCP

LL4148_LL34-2

PR120

@PR120

@

200_0603_5%

1 2

PR124

@PR124

@

22K_0402_1%

1 2

12

@PR123

@

PR123

100K_0402_1%

C C

+3VLP

BATT+

51_ON#<32>

1 2

51ON-2

PC112

@ PC112

@

PJ101

PJ101 JUMP_43X39@

JUMP_43X39@

0.22U_0603_25V7K

51ON-3

112

TP0610K-T1-E3_SOT23-3

PR127

0_0402_5%

1 2

B B

PC114

@ PC114

@

3.3V

12

@PU102

@

APL5156-33DI-TRL_SOT89-3

3

VOUT

10U_0603_6.3V6M

PU102

VIN

GND

1

PR127

RTCVREF

CHGRTCIN

2

12

PR128

@

200_0603_5%

12

PC115

@ PC115

@

1U_0805_25V6K

+CHGRTC

JRTC2

- +

MAXEL_ML1220T10@

PR131

560_0603_5%

1 2

12

PR132

560_0603_5%

1 2

PD109

RB751V-40_SOD323-2

12

1 2

PD108

RB751V-40_SOD323-2

+RTCBATT

RTCVREF

PR131

RTC Battery

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/10/12 2013/10/12

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PWR DCIN

1

0.1

36 48Wednesday, November 30, 2011

0.1

5

4

3

2

1

JBATT1

VMB2

JBATT1

1

2

3

4

5

6

7

8

D D

GND

9

GND

TYCO_1775789-1

@

EC_SMCA

EC_SMDA

12

PR201

100_0402_1%

PR201

100_0402_1%

PF201

PF201 12A_65V_451012MRL

12A_65V_451012MRL

12

PR202

100_0402_1%

PR202

100_0402_1%

21

VMB

SMB3025500YA_2P

1 2

12

PC201

PC201 1000P_0402_50V7K

1000P_0402_50V7K

PL201

BATT+

12

PC202

0.01U_0402_25V7K

ADP_I need to write Charge Options Register (0x12H)=> bit6=1

0: IOUT is the 20x current amplifier output <default @ POR> 1: IOUT is the 40x current amplifier output

EC_SMB_CK1 < 30,38>

PH1 under CPU botten side :

EC_SMB_DA1 < 30,38>

CPU thermal protection at 93 +-3 degree C Recovery at 56 +-3 degree C

1 2

PR203

JBATT2

1

2

3

4

5

6

7

8

GND

9

GND

TYCO_1775789-1

C C

TYCO_1775789-1

@

PR203

6.49K_0402_1%

1 2

PR204

PR204 10K_0402_5%

10K_0402_5%

+3VALW

BATT_TEMP < 30>

A/D

VL

12

PC203

0.1U_0603_16V7K

H_PROCHOT#<5,10,30>

PROCHOT<30>

+3VS

PR208

1 2

PQ201

13

D

ADP_OCP_1

2

G

SSM3K7002FU_SC70-3

S

PR212

PR212 0_0402_5%@

0_0402_5%@

1 2

100K_0402_1%

1

2

3

4

OTP_N_003

PR213 0_0402_5%PR213 0_0402_5%

PU201

VCC

TMSNS1

GND

RHYST1

OT1

TMSNS2

RHYST2

OT2

G718TM1U_SOT23-8

MAINPWON <30,39>

12

8

7

6

5

For KB930 --> Keep PU201 circuit (Vth = 0.825V)

For KB9012 (Red square) --> Remove PU201 circuit, but keep PR206 PH201, PR205, PR211,PQ201,PR208,PR212

PR228

PR228 0_0402_5%

0_0402_5%

@

1 2

47K_0402_1%

PR229

+3VLP

12

+3VLP+3VLP

12

PR206

@

12.7K_0402_1%

OTP_N_002

ADP_OCP_2

ADP_I<30,38>

PR210

1 2

5.11K_0402_1%

PR205

402_0402_1%

Turbo_V_2

PR230

47K_0402_1%

PR231

@

0_0402_5%

1 2

PR227

0_0402_5%

@

1 2

12

NTC_V_2

PR211

1 2

10K_0402_1%

PR209

10K_0402_1%

12

PH201

100K_0402_1%_NCP15WF104F03RC

12

PR207

21.5K_0402_1%

12

<30>

Turbo_V

B B

VMB2

PR217

PR217 768K_0402_1%

768K_0402_1%

PR219

10K_0402_1%

1 2

PR221

PR221 221K_0402_1%

221K_0402_1%

1 2

A A

5

12

PC204

3

2

PR223

PR223 10K_0402_1%

10K_0402_1%

PR225

PR225 10K_0402_1%

10K_0402_1%

@

0.01U_0402_25V7K

P2

+

-

10M_0402_5%

8

P

O

G

LM393DG_SO8

4

12

PR218

1 2

1

PU202A

2VREF_8205

RTCVREF

BATT_LEN#<30>

PR214

PR214 100K_0402_1%

100K_0402_1%

1 2

PR226

100K_0402_1%

+3VLP

1 2

+3VALW+3VLP

1 2

13

2

G

2

G

PR215

PR215 100K_0402_1%

100K_0402_1%

PQ202

D

2N7002KW_SOT323-3

S

PQ203

13

D

2N7002KW_SOT323-3

S

4

BATT_OUT <38>

100K_0402_1%

SPOK<39,41>

VSB_ON<30>

TP0610K-T1-E3_SOT23-3

B+

VL

PR222

PR224

1 2

1K_0402_5%

1 2

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

22K_0402_1%

13

D

2

G

2N7002W-T/R7_SOT323-3

G

2N7002W-T/R7_SOT323-3

S

PC207

1U_0402_6.3V6K

2011/10/12 2013/10/12

PR220

1 2

PQ204

12

PR216

PC205

100K_0402_1%

0.22U_0603_25V7K

Compal Secret Data

Deciphered Date

PQ205

2

13

2

12

PC206

0.1U_0603_25V7K

+VSBP

Title

Size Document Number Rev

Custom

Date: Sheet of

<30>

NTC_V

PJ201

PJ201 JUMP_43X39@

JUMP_43X39@

112

2

+VSB

Compal Electronics, Inc.

PWR-BATTERY CONN/OTP

1

0.1

37 48Wednesday, November 30, 2011

0.1

5

PQ301

PQ301 AO4407A_SO8

AO4407A_SO8

DTA144EUA_SC70-3

47K_0402_5%

13

2

PQ307A

PACIN

PQ311

DTC115EUA_SC70-3

PR321

1 2

10K_0402_5%

8 7

5

PQ304

2

1 3

PQ305

DTC115EUA_SC70-3

PR318

47K_0402_1%

1 2

ACOFF-1

2

12

PR325

PR325 0_0402_5%

0_0402_5%

PQ313

13

D

2

G

S

4

2N7002KW_SOT323-3

VIN

D D

C C

B B

12

PR301

61

2N7002KDW -2N_SOT363-6

2

PACIN

ACON

ACOFF<30>

BATT_OUT<37>

P2

1 2 36

12

PC301

PR303

0.1U_0603_25V7K

P2-1

12

P2-2

34

PQ307B

5

13

AO4423L SO8

1 2 3 6

200K_0402_1%

12

PR307

PR307 20K_0402_1%

20K_0402_1%

13

D

2N7002KW_S OT323-3

G

PR308

S

150K_0402_1%

1 2

64.9K_0603_1%

2N7002KDW-2N_SOT363-6

PQ302

PQ308

2

PR317

4

5600P_0402_25V7K

PR314

EC_SMB_DA1<30 ,37>

EC_SMB_CK1<30 ,37>

4

P3

8 7

5

1UH_PCMB061H-1R0M S_7A_20%

1 2

PC304

BATT_OUT <37>

VIN

12

PR315

10K_0402_5%

390K_0603_1%

@

12

@

PC323

0.1U_0603_25V7K

+3VALW

SH00000AA00

1 2

PL301

1 2

PC302

10U_0805_25V6K

+3VALW

PR316

10K_0402_5%

1 2

ADP_I<30, 37>

@

1 2

100P_0603_50V8

PR323

1 2

316K_0402_1%

PC312

ACPRN<39>

39.2K_0402_1%

12

PR302

0.01_1206_1%

1

2

1 2

PC315

10U_0805_25V6K

PR309

@

PR312

@PR3 12

@

6

7

8

9

10

PR326

PR326 100K_0402_1%

100K_0402_1%

1 2

12

4.7M_0603_1%

5

ACOK

ACDET

IOUT

SDA

BQ24727RGRR_VQFN20_ 3P5X3P5

SA000051W00

SCL

ILIM

11

0.1U_0603_25V7K

ACP

PR313

6.8_0603_5%

B+

4

3

+3VALW

100K_0402_1%

4

CMPIN

PU301

SRN12BM

12

PR327

PC320

12

ACN

PC308

1 2

12

PC310

0.1U_0603_25V7K

PR310

10K_0603_1%

@

2

3

CMPOUT

SRP

12

14

13

PR328

10_0603_5%

12

PC321

0.1U_0603_25V7K

ACP

GND

3

PC309

12

0.1U_0603_25V7K

12

1

ACN

TP

VCC

PHASE

HIDRV

BTST

REGN

LODRV

15

12

21

20

19

18

BST_CHG

17

PD303

16

RB751V-40_SOD323-2

12

PC318

PC318 1U_0603_25V6K

1U_0603_25V6K

@

PC322

0.1U_0603_25V7K

P2

PR319

10_1206_5%

BQ24727VCC

DH_CHG

12

DL_CHG

1 2

PC313

1 2

1U_0603_25V6K

PR324

2.2_0603_5%

1 2

PC303

LX_CHG

0.047U_0603_25V7M

BQ24727VDD

4.7U_0805_25V6-K

PC314

2

B+

PQ303

AO4407A_SO8

1 2 3 6

PL302

PD301

ACOFF-1

1 2

1SS355_SOD323-2

1 2

CHGCHG

4

PD302

PD302 1SS355_SOD323-2

1SS355_SOD323-2

0.01_1206_1%

1

2

SRP

DISCHG_G

PC307

1 2

PC305

4.7U_0805_25V6-K

12

PC307

1 2

PC306

2200P_0402_50V7K

4.7U_0805_25V6-K

6

578

4

123

6

578

4

123

PR304

47K_0402_1%

1 2

PR305

PR305 10K_0402_1%

10K_0402_1%

1 2

DISCHG_G-1

PQ306

13

DTC115EUA_SC70-3

2

PQ310

AO4466L_SO8

4.7U_LF919AS-4R7M- P3_5.2A_20%

1 2

12

PQ312

PR322

4.7_1206_5%

AO4466L_SO8

4.7_1206_5%

6251_SN

12

PC319

680P_0603_50V7K

PC311

PR320

0.1U_0603_25V7K

1

8 7

5

PR306

PR306 200K_0402_1%

200K_0402_1%

1 2

PQ309

2N7002W- T/R7_SOT323-3

13

D

2

12

G

S

4

3

SRN

VIN

PACIN

PC316

BATT+

12

PC317

10U_0805_25V6K

BQ24727VDD

PR337

10K_0402_1%

4

10K_0402_1%

1 2

PACIN

12

PR339

12K_0402_1%

ACIN <16,30>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Deciphered Date

2013/10/122011/10/12

2

Compal Electronics, Inc.

Title

Size D ocument Number Rev

Date: Sheet of

Compal Electronics, Inc.

CHARGER

38 48Wednesday, November 30, 2011

1

0.1

12

PR335

47K_0402_1%

ACPRN <39>

PQ316

DTC115EUA_SC70-3

A A

5

DTC115EUA_SC70-3

12

PR336

PR336 10K_0402_1%

10K_0402_1%

13

2

5

Note: Use TPS51125 IC can remove RTC refernece LDO Use TPS51427 IC must keep RTC refernece LDO

4

3

2

1

2VREF_8205

+3VALW P +3VAL W

D D

PR401

13K_040 2_1%

1 2

PR403

RT8205_B+

PJ401

B+

PC405

C C

B B

PJ401

2

112

JUMP_43 X118@

12

0.1U_0603_25V7K

PC402

0.1U_0603_25V7K

PC404

PC403

4.7U_0805_25V6-K

12

PC402

+3VALWP

For KB9012

EC_ON<30,32>

MAINPWON<30,37>

PR418

PR418 10K_040 2_5%

10K_040 2_5%

PR413

PR413 0_0402_ 5%

0_0402_ 5%

12

PC406

4.7U_0805_25V6-K

4.7U_0805_25V6-K 2200P_0402_50V7K

2200P_0402_50V7K

4.7UH +-20 % PCMC063T-4R7M N 5.5A

1

+

PC415

PC415 150U_B2 _6.3VM_R45M

150U_B2 _6.3VM_R45M

2

2N7002K DW-2N_SOT3 63-6

VL

AO4466L _SO8

PL401

1 2

PQ405A

PQ401

PR409

4.7_1206_5%

PC418

680P_0603_50V7K

61

100K_04 02_1%

6

578

4

123

12

578

PQ403

PQ403 AO4712_ SO8

AO4712_ SO8

12

3 6

241

2

PR414

12

Typ: 175mA

34

5

+3VLP

12

PC411

4.7U_0805_10V6K

1 2

2.2_0603 _5%

PC412

0.1U_060 3_25V7K

PR411

499K_04 02_1%

1 2

B+

ENTRIP2EN TRIP1

PR412

PQ405B

PQ405B 2N7002K DW-2N_SOT3 63-6

2N7002K DW-2N_SOT3 63-6

PR407

100K_0402_1%

12

PR403

20K_040 2_1%

1 2

PR405

130K_04 02_1%

1 2

25

7

8

BST_3V

9

UG_3V

10

LX_3V

11

LG_3V

12

PC420

1U_0603_10V6K

2VREF_8205

PU401

P PAD

VO2

VREG3

BOOT2

UGATE2

PHASE2

LGATE2

12

PC401

1U_0603_10V6K

ENTRIP2

5

6

FB2

ENTRIP2

VFB=2.0V

SKIPSEL

EN

14

13

RT8205_ B+

+5VALW P +5VAL W

PR402

30K_040 2_1%

1 2

PR404

19.6K_04 02_1%

1 2

PR406

66.5K_04 02_1%

ENTRIP1

1 2

2

3

1

4

FB1

REF

TONSEL

15

ENTRIP1

24

VO1

23

PGOOD

BOOT1

UGATE1

PHASE1

LGATE1

NC18VREG5

VIN16GND

17

12

PC421

12

4.7U_0805_10V6K

PC422

0.1U_0603_25V7K

BST_5V

22

UG_5V

21

LX_5V

20

LG_5V

19

RT8205E GQW_W QFN24_4X4

VL

Typ: 175mA

12

PC407

4.7U_0805_25V6-K

PR408

2.2_0603 _5%

1 2

RT8205_ B+

12

PC408

PC409

4.7U_0805_25V6-K

4.7U_0805_25V6-K 2200P_0402_50V7K

2200P_0402_50V7K

SPOK <37,41>

PC413

0.1U_060 3_25V7K

1 2

12

PC410

0.1U_0603_25V7K

678

PQ402

35241

5

PQ404TPC8A03-H_SO8 PQ404TPC8A03-H_SO8

4

+3.3VALWP OCP(min)=5.81A +5VALWP OCP(min)=8.44A

PJ402

2

112

JUMP_43 X118@

PJ403

2

112

JUMP_43 X118

@

TPC8065-H_SO8

PL402

12

PR410

12

PC419

PL402

1 2

4.7_1206_5%

680P_0603_50V7K

4.7UH_PC MB104E-4R7MS_ 10A_20%

786

123

+5VALWP

1

+

PC417

PC417 150U_B2 _6.3VM_R45M

150U_B2 _6.3VM_R45M

2

13

PR415

200K_04 02_1%

ACPRN<38 >

A A

200K_04 02_1%

EC_ON<30,32>

12

@

2

@

5

2

G

13

D

VS

S

PQ407

2N7002W-T/R7_SOT323-3

PQ408

DTC115E UA_SC70-3

@

1 2

PR416

100K_04 02_1%

@

12

PR417

40.2K_0402_1%

@

For KB9012

PQ406

4

PQ406 DTC115E UA_SC70-3

DTC115E UA_SC70-3

Security Class ification

2011/10/ 12 2013/10/ 12

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/10/ 12 2013/10/ 12

3

Compal Secret Data

Deciphered Date

2

Title

Size Document Numb er Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

3VALWP/5VALWP

39 48Wednesd ay, November 30, 201 1

1

0.1

2

PC423

4.7U_0603_6.3V6M

A

1 1

PR501

0_0402_5%

SYSON<30,35>

2 2

1 2

PR502

@

12

PC501

1 2

47K_0402_5%

.1U_0402_16V7K

12

PR507

1 2

11.5K_0402_1%

PR508

PR508 10K_0402_1%

10K_0402_1%

100K_0402_1%

PR505

PR506

1 2

470K_0402_1%

12

B

PU501

1

VBST

PGOOD

2

TRIP

DRVH

3

EN

4

5

SW

V5IN

VFB

DRVL

RF

TP

TPS51212DSCR_SON10_3X 3

VFB=0.7V

C

1.5V_B+

678

PQ501

PQ501 TPC8065-H_SO8

TPC8065-H_SO8

PC506

PR503

0_0603_5%

BST_1.5V

DH_1.5V

LX_1.5V

DL_1.5V

1 2

12

10

9

8

7

6

11

0.22U_0603_16V7K

BST_1.5V-1

+5VALW

PC508

1U_0603_10V6K

PC506

1 2

35241

786

5

PQ502

4

TPC8A03-H_SO8

123

PC502

1UH_PCMC063T-1R0M N_11A_20%

12

PR504

4.7_1206_5%

12

PC509

1000P_0603_50V7K

12

10U_0805_25V6K

1 2

12

PC503

PC504

0.1U_0402_25V6

10U_0805_25V6K

PL501

0.1U_0402_25V6

PJ501

2

JUMP_43X118@

12

PC505

2200P_0402_50V7K

1

+

PC507

PC507 220U_6.3V_M

220U_6.3V_M

2

+1.5VP

D

112

B+

+1.5VP

+1.5VP OCP(min)=15.6A

2

PJ502

JUMP_43X118@

PJ503

JUMP_43X118@

112

+1.5V

PU502

PJ505

+5VALW

3 3

2

112

JUMP_43X118@

SUSP#<30,35,41,43>

4 4

A

1.8VSP_VIN

12

PC510

22U_0603_6.3V6K

PR511

1 2

47K_0402_5%

EN_1.8VSP

PR512

PR512 1M_0402_5%

1M_0402_5%

12

PC515

1 2

4

10

PVIN

PG

9

PVIN

8

SVIN

5

EN

TP

NC

7

11

SY8033BDBC_DFN10_3X3

0.1U_0402_10V7K

1.8VSP_LX

2

LX

3

LX

6

FB

NC

1

B

FB=0.6Volt

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PL503

1UH_PH041H-1R0MS_3. 8A_20%

1 2

12

PR510

20K_0402_1%

PR509

4.7_1206_5%

12

PC512

680P_0603_50V7K

1.8VSP_FB

PR513

10K_0402_1%

12

PC511

68P_0402_50V8J

PC513

22U_0603_6.3V6K

12

Compal Secret Data

2011/10/12 2013/10/12

Compal Secret Data

12

PC514

22U_0603_6.3V6K

Deciphered Date

C

+1.8VSP

PJ504

2

112

JUMP_43X118@

+1.8VS+1.8VSP

1.8VSP max current=4A

Title

Size D ocument Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PWR-+1.5VP/+1.8VSP

40 48Wednesday, November 30, 2011

D

40 48Wednesday, November 30, 2011

0.1

5

D D

SPOK<37,39>

+5VALW

C C

PR601

1 2

0_0402_5%

JUMP_43X118@

PR602

1M_0402_5%

PJ601

2

4

@PC602

@

12

PC602

1 2

112

0.1U_0402_10V7K

1.1V_LX 1.1V_LX

12

PC601

22U_0603_6.3V6K

PU601

PU601 SY8809DFC_DFN8_2X2

SY8809DFC_DFN8_2X2

1

EN

FB

2

IN

PG

3

LX

4

GND

8

7

6

5

10K_0402_1%

PR605

12

3

PL603

1UH_PCMC063T-1R0MN_11A_20%

1 2

PR603

4.7_1206_5%

PC603

PR604

8.25K_0402_1%

680P_0603_50V7K

1 2

PC604

@

1 2

68P_0402_50V8J

2

1

+1.1VALWP

12

PC605

22U_0603_6.3V6K

12

PC606

22U_0603_6.3V6K

PC627

22U_0805_6.3V6M

@

PJ602

2

JUMP_43X118

@

+1.1VALW+1.1VALWP

112

PJ603

2

112

JUMP_43X118

@

PC614

4.7U_0805_25V6-K

B+

+1.05VSP

1

12

+

PC618

PC619

2

1U_0603_10V6K

220U_D2_4VY_R15M

PJ604

2

JUMP_43X118

@

Title

Size Document Number Rev

C

Date: Sheet of

Compal Electronics, Inc.

PWR +1.1VALWP/+1.0VSP

+1.05VS+1.05VSP

112

0.1

41 48Wednesday, November 30, 2011

1

41 48Wednesday, November 30, 2011

0.1

123

+1.2VSP_B+

PQ603

PQ603 TPC8065-H_SO8

TPC8065-H_SO8

@

TPC8A03-H_SO8

@

12

PC612

PC611

0.1U_0402_25V6

0.1U_0402_25V6 2200P_0402_50V7K

2200P_0402_50V7K

PL602

1UH_PCMC063T-1R0MN_11A_20%

1 2

12

PR614

4.7_1206_5%

12

PC620

680P_0603_50V7K

2011/10/12 2013/10/12

12

PC613

4.7U_0805_25V6-K

Compal Secret Data

Deciphered Date

678

B B

PU602

1

PR615

5.1K_0402_1%

2

3

4

5

PGOOD

TRIP

EN

VFB

RF

TPS51212DSCR_SON10_3X3

12

4

PR610

TRIP_+1.0VSP

1 2

75K_0402_1%

PR611

SUSP#<30,35,40,43>

A A

1 2

160K_0402_1%

5

12

PR612

@

47K_0402_1%

EN_+1.0VSP

FB_+1.0VSP

RF_+1.0VSP

12

PC616

0.1U_0402_16V7K

PR616

PR616 10K_0402_1%

10K_0402_1%

1 2

12

PR613

470K_0402_1%

VBST

DRVH

V5IN

DRVL

BST_+1.0VSP

10

UG_+1.0VSP

9

SW_+1.0VSP

8

SW

+1.0VSP_5V

7

LG_+1.0VSP

6

11

TP

PR609

1 2

0_0603_5%

0.1U_0603_25V7K

12

PC617

PC617 1U_0603_6.3V6M

1U_0603_6.3V6M

PC615

1 2

+5VALW

35241

786

5

PQ604

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

5

4

3

2

1

D D

PQ701

PQ701 2N7002W -T/R7_SOT32 3-3

2N7002W -T/R7_SOT32 3-3

PR701

49.9K_04 02_1%

C C

B B

SUSP<35>

1 2

PC701

0.1U_0402_10V7K

13

D

2

G

S

12

S

+1.5V

1

2

4.7U_080 5_6.3V6K

1 2

PJ701

PJ701 JUMP_43 X118

JUMP_43 X118

@

PC702

PR702

1K_0402 _1%

PR703

PU701

1

VIN

2

12

PC704

PC705

.1U_0402_16V7K

1K_0402_1%

3

4

12

10U_0603_6.3V6M

GND

VREF

VOUT

APL5336 KAI-TRL_SOP8P8

+0.75VSP

PC706

8

NC

7

NC

6

VCNTL

5

NC

9

TP

10U_0603_6.3V6M

12

+3VALW

PC703

1U_0603 _10V6K

PJ702

2

112

JUMP_43 X118@

+0.75VS+0.75 VSP

A A

Security Class ification

2011/10/ 12 2013/10/ 12

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/10/ 12 2013/10/ 12

3

Compal Secret Data

Deciphered Date

Title

Size Document Numb er Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PWR +0.75VSP

42 48Wednesd ay, November 30, 201 1

1

0.1

A

B

C

D

VCCSENSE_VGA<19>

1 1

10P_0402_25V8J

1 2

PC801

PR805

11.8K_0402_1%

PR809

7.68K_0402_1%

PR810

1 2

PC818

0.1U_0402_16V7K

10P_0402_25V8J

+3VS

PR811

PC801

1 2

PR807

5.11K_0402_1%

1 2

1 2 12

97.6K_0402_1%

12

10K_0402_1%

PR801

0_0402_5%

1 2

PR814

PR814 0_0402_5%

0_0402_5%

1 2

@

GPU_VID0

GPU_VID1

1 2

PR804

100K_0402_1%

0_0402_5%

1 2

GPU_VID0<16>

GPU_VID1<16>

VRON_VGA

PR812

12

VSSSENSE_VGA<19>

2 2

VGA_PWRGD<12,15,17>

SUSP#<30,35,40,41>

PR820 10k_0402_5%

10k_0402_5%

1 2

PR821

PR821 10k_0402_5%

10k_0402_5%

1 2

PR813 33K_0402_5%PR813 33K_0402_5%

PX_MODE<17>

3 3

@ PR820

+3VS

@

PC806

PU801

1

GSNS

2

V3

3

V2

4

V1

5

V0

PR822

PR822 10k_0402_5%

10k_0402_5%

1 2

PR823

PR823 10k_0402_5%

10k_0402_5%

1 2

12

21

12

PR802

PR802 0_0402_5%

0_0402_5%

1 2

PC807

19

18

20

4700P_0402_25V7K

PAD

VSNS

SLEW

TPS51518RUKR_QFN20_3X3

VID08PGOOD

VREF

7

6

PC817

0.1U_0402_10V7K

PXS_PWREN<12,17>

PR803

41.2K_0402_1%

TRIP

VID19EN

17

GND

10

PXS_PWREN

DRVL

DRVH

5

4

16

MODE

15

V5IN

14

13

12

SW

11

BST

12

PR808

2.2_0603_5%

+5VALW

PC808

1U_0603_10V6K

UGATE2_VGA

BOOT2_2_VGABOOT2_VGA

12

LGATE2_VGA

PC816

0.1U_0603_25V7K

1 2

4

Seymour

GPU_VID1

GPU_VID0

Core Voltage Level

1

0

PD801

@ PD 801

@

RB751V-40_SOD323-2

1 2

PR816

@ PR 816

@

40.2K_0402_1%

1 2

1

0

1

0

@

PC822

0.1U_0603_25V7K

PR815

0_0402_5%

12

+5VALW

12

PR818

PR818 20K_0402_1%

20K_0402_1%

0.9V

1.0V

1.05V

1.12V

7

8

12

PC819

PC819 1U_0402_6.3V6K

1U_0402_6.3V6K

PU802

POK

EN

+5VALW

6

VIN

VOUT

VCNTL

VOUT

FB

VIN

GND

APL5912-KAC-TRL_SO8

1

5

4

3

2

9

PQ801

123

TPCA8065-H_SOP-ADV8-5

PQ802

123 5

TPCA8057-H 1N PPAK56-8

+1.5V

1

PJ804

1

JUMP_43X79

2

12

1.15K_0402_1%

4.53K_0402_1%

VGA_CORE_B+

4

@

PC820

4.7U_0805_6.3V6K

12

PR817

12

PR819

12

PC803

PC802

0.1U_0402_25V6

0.1U_0402_25V6 2200P_0402_50V7K

2200P_0402_50V7K

0.36UH_PCMC104T-R36MN1R17_30A_20%

1 2

12

PR806

4.7_1206_5%

PQ803

12

PC815

680P_0603_50V7K

123 5

TPCA8057-H 1N PPAK56-8

@

+VGA_COREP +VGA_CORE

+VGA_PCIEP +1.0VGS

12

PC823

22U_0603_6.3V6K

PC821

0.01U_0402_25V7K

PL801

12

PC804

4.7U_0805_25V6-K

+VGA_PCIEP

PC805

1

2

PJ801

@ PJ 801

@

2

JUMP_43X118

4.7U_0805_25V6-K

1

+

PC809

PC810

2

@

470U_D2_2VM_R4.5M

+VGA_COREP Iocp=32.5A

PJ802

2

JUMP_43X118@

PJ803

2

JUMP_43X118@

PJ805

2

JUMP_43X79

@

PC811

2

112

PR819 4.53K

112

470U_D2_2VM_R4.5M

112

1.0VVGA_PCIE

B+

+VGA_COREP

1

PC812

PC813

PC814

2

10U_0603_6.3V6M

1.1 V

PC814

2

10U_0603_6.3V6M

3K

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

2011/10/12 2013/10/12

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PWR-VGA_CORE/VGA_PCIE

Size Document Number Rev

Date: Sheet of

D

43 48Wednesday, November 30, 2011

0.1

A

1 1

+5VS +3VS

12

PR915

@PR915

PR914

105K_0402_1%

2 2

VGATE<30>

VR_ON<30>

PR924

21.5K_0402_1%

1 2

12

FCH_PWRGD<12,30>

APU_PWRGD<5,10>

3 3

APU_SVD<5> APU_SVC<5>

@

10K_0402_1%

PR917 100K_0402_5%@PR917 100K_0402_5%@

PR919 100K_0402_5%PR919 100K_0402_5%

PR925

95.3K_0402_1%

12

+APU_CORE

APU_VDD0_RUN_FB_H<5>

APU_VDD0_RUN_FB_L<5>

10_0402_5%

PR912

PR912 0_0402_5%

0_0402_5%

PR921

0_0402_5%

PR927

PR932

+5VS

CPU_B+

12

PR913

@PR913

@

105K_0402_1%

12

PR916

@PR916

@

105K_0402_1%

ISL6265_PWROK

12

0_0402_5%

12

PR938

12

0_0402_5%

1 2

10_0402_5%

0.1U_0603_25V7K

PR923

PR928

0_0402_5%

PR929

0_0402_5%

PR930

B

PR902

2_0603_5%

1 2

PC907

0.1U_0603_16V7K

1 2

PR906

2_0603_5%

PC911

PU901

1

OFS/VFIXEN

2

PGOOD

3

PWROK

4

SVD

5

12

SVC

6

ENABLE

7

RBIAS

8

OCSET

9

VDIFF0

10

FB0

11

COMP0

12

VW0

VSEN1

ISP0 ISN0

1 2

VSEN0

12

RTN0

12

+1.5VS

C

PC901

33P_0402_50V8J

12

PR901

44.2K_0402_1%

PC906

1000P_0402_50V7K

12

46

47

48

VIN

VCC

ISN0

ISP0

15

14

13

22K_0402_1%

43

44

45

FB_NB

FSET_NB

VSEN_NB

COMP_NB

ISL6265CHRTZ-T_TQFN48_6X6

RTN117VSEN0

RTN0

VSEN1

16

18

VSEN1

12

PR931

PR931 0_0402_5%

0_0402_5%

PC902

1000P_0402_50V7K

12

PR904

12

PR908

0_0402_5%

12

PR909

PR909 0_0402_5%

0_0402_5%

27.4K_0402_1%

40

41

42

RTN_NB

PGND_NB

OCSET_NB

VDIFF1

COMP121ISP1

FB1

19

20

12

PR907

@ PR907

@

10_0402_5%

1 2

APU_VDD0_RUN_FB_L

12

PR911

12

37

38

39

LGATE_NB

PHASE_NB

UGATE_NB

VW1

ISN1

22

23

24

ISN0

ISP0

+APU_CORE_NB

PR910

@PR910

@

1 2

10_0402_5%

BOOT_NB

BOOT0

UGATE0

PHASE0

PGND0

LGATE0

PVCC

LGATE1

PGND1

PHASE1

UGATE1

BOOT1

TP

49

UGATE_NB

PHASE_NB

2.2_0603_1%

BOOT_NB

1 2

LGATE_NB

APU_VDDNB_RUN_FB_ H <5>

PHASE_NB

LGATE_NB

PHASE_NB

UGATE_NB

BOOT_NB

36

BOOT0

35

UGATE0

34

PHASE0

33

32

LGATE0

31

30

29

28

27

26

25

PR903

0.22U_0603_25V7K

UGATE0

PHASE0

BOOT0

+5VS

12

PC918

PC918 1U_0603_16V6K

1U_0603_16V6K

1 2

PC908

4

0_0603_5%

1 2

PR918

2.2_0603_5%

1 2

0.22U_0603_25V7K

578

5

PR939

PC915

3 6

241

786

1 2

LGATE0

PQ901

PQ901 AO4466L_SO8

AO4466L_SO8

PQ902

AO4712L_SO8

123

4

5

D

CPU_B+

12

PC904

PC905

4.7U_0805_25V6-K

12

@

12

@

123

123 5

PL902

3.3UH_PCMB104E-3R3MS_11A_2 0%

1 2

PR905

4.7_1206_5%

PC910

PC910 680P_0603_50V7K

680P_0603_50V7K

PQ903

PC912

4.7U_0805_25V6-K

S TR AON7518 1N DFN

PQ904

TPCA8059-H_SOP-ADVANCE8-5

E

PL901

HCB2012KF-121T50_0805

12

PC924

+APU_CORE_NB

1

+

PC909

PC909 220U_D2_4VM

220U_D2_4VM

2

CPU_B+

12

PC914

PC913

4.7U_0805_25V6-K

12

@

PR920

4.7_1206_5%

12

PC916

@PC916

@

680P_0603_50V7K

B+

1

+

2

220U_25V_M

PL903

0.36UH_ETQP4LR36WFC_24A _20%

1

2

PR922

9.31K_0402_1%

1 2

PC917

12

0.1U_0603_16V7K

12

PR926

5.11K_0402_1%

ISP0

+VDDNBP Iocp~15A

+CPU_CORE Iocp~15A

4

3

+APU_CORE

ISN0

DIFF_0

PC919

PR933

2200P_0402_25V7K

255_0402_1%

12

4 4

PR934

1K_0402_5%

FB_0

12

54.9K_0402_1%

12

@ PR937

@

A

PC920

180P_0402_50V8J

PR935

PR937

36.5K_0402_1%

VW0

COMP0

12

PC922

12

1200P_0402_50V7K

12

PC921

1000P_0402_50V7K

PR936

6.81K_0402_1%

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/06/30 2012/06/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

+CPU_CORE/VDDNBP

44 48Wednesday, November 30, 2011

E

0.1

5

4

3

2

1

+CPU_CORE +CPU_CORE_NB

D D

+APU_CORE

12

PC1001

10U_0603_6.3V6K

12

PC1002

10U_0603_6.3V6K

12

PC1003

10U_0603_6.3V6K

12

PC1004

10U_0603_6.3V6K

12

PC1005

10U_0603_6.3V6K

+APU_CORE_NB

12

PC1007

PC1006

10U_0603_6.3V6K

PC1007

10U_0603_6.3V6K

12

PC1008

10U_0603_6.3V6K

12

PC1009

10U_0603_6.3V6K

1

+

C C

2

12

PC1010

10U_0603_6.3V6K

PC1017

330U_D2_2V5M_R9M

12

PC1011

10U_0603_6.3V6K

1

+

PC1018

2

330U_D2_2V5M_R9M

12

PC1012

10U_0603_6.3V6K

1

+

PC1019

2

330U_D2_2V5M_R9M

12

PC1013

10U_0603_6.3V6K

1

+

PC1020

2

330U_D2_2V5M_R9M

@

12

PC1014

10U_0603_6.3V6K

12

PC1015

10U_0603_6.3V6K

1

+

PC1022

2

220U_D2_4VM

12

PC1016

10U_0603_6.3V6K

+1.05VS +1.8VS

1

12

+

PC1023

2

B B

PC1024

330U_D2_2VM_R7M

10U_0603_6.3V6K

1

2

12

+

PC1025

PC1026

330U_D2_2VM_R7M

10U_0603_6.3V6K

A A

Security Class ification

2011/10/ 12 2013/10/ 12

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/10/ 12 2013/10/ 12

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Numb er Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PWR - PROCESSOR DECOUPLING

45 48Tuesday, November 29, 20 11

1

0.1

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1

for PWR

Reason for change PG# Modify List Date PhaseItem

1

D D

2

0402 0

歐歐歐歐歐歐歐歐

(CPU CORE/VDDNBP)...VR_ON

增增增增增增增增

PR938

3

APU_CORE_NB....PC1021

拿拿拿拿拿拿拿拿

4

5

6

7

8

C C

9

10

11

12

13

14

B B

15

16

17

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/10/12 2013/10/12

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size D ocument Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PIR (PWR)

46 48Tuesday, November 29, 2011

1

0.1

5

4

3

2

1

QAWGE Power Sequence (AC mode)

EC -> PWR

D D

PWR -> PWR

Switch -> EC

EC -> FCH

FCH -> EC

EC -> FCH

FCH -> EC

EC -> PWR

C C

DIS sequence

B B

EC -> PWR

PWR -> EC

EC -> FCH

FCH -> APU

FCH -> EC

FCH -> Device

FCH -> APU

EC_ON

+3VALW +5VALW

SPOK

+1.1VALW

ON/OFFBTN#

EC_RSMRST#

RTC_CLK

PBTN_OUT#

PM_SLP_S5# PM_SLP_S3#

SYSON

1.5V

SUSP#

+1.8VS

+1.5VS

+1.05VS

+5VS

+3VS

+1.1VS

+0.75VS

PXS_PWREN

+3VGS

+1.0VGS

+1.5VGS

+VGA_CORE

+1.8VGS

CLK_PCIE_VGA

PXS_RST#

VR_ON

+APU_CORE

+APU_CORE_NB

VGATE

FCH_PWRGD

APU_CLK DISP_CLK

APU_PWRGD

KB_RST#

A_RST# (PLT_RST#)

APU_RST#

T1

T2

T3

T13

1ms< T1 < 100ms : +3VALW rising time, for LAN chip request

+3VALW need rampe up before +1.1VALW or at the same time.

T2 < 50ms : EC_RSMRST# rising time

+3VALW need rampe up before EC_RSMRST# de-assertion at least 10ms +1.1VALW need rampe up before EC_RSMRST# de-assertion

T3 > 16ms : EC_RSMRST# de-assert to start RTCCLK

T13 > 200ns : PBTN_OUT# to SLP_S3#/S5# de-assertion

+3VS need rampe up before +1.1VS or at the same time.

The time delay between PXS_PWREN assertion and PXS_RST# de-assertion must be more than 100ms.

CLK_PCIE_VGA should be 100us earlier than PXS_RST# de-assert.

T11

T7

T9

T11< 32ms : FCH_POK assertion to clock out

98ms< T7< 150ms : FCH_POK assertion to APU_PWRGD

KB_RST# should be de-asserted before FCH_POK

101ms< T9< 113ms : FCH_POK assertion to A_RST# de-assertion

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2011/10/12 2013/10/12

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PWR - PROCESSOR DECOUPLING

Size Document Number Rev

Date: Sheet of

1

47 47Tuesday, November 29, 2011

0.1

COMPAL LA-8681P Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual