COMPAL LA-8671P Schematics

A

B

C

D

E

Compal Confidential

1 1

Model Name : File Name : LA-8671P

2 2

Compal Confidential

TN-Note Schematic Document

3 3

REV:1A_1004A

4 4

Security Classification

2012-10-04

AMY WEN

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

2012/08/252010/08/25

D

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Cover Page

LA-8671P_SDV

Thursday, October 04, 2012

E

1A

1

1A

50

A

B

C

D

E

Compal Confidential

Model Name : File Name :

ZZZ

DAZ0RP00201

1 1

2 2

U5009

U5006

DDR2@

ELIPDA 8G

SA000058U20

UD1

UD2

DDR2@

ELIPDA 8G

SA000058U20

R267

R5049

DDR2@

10K_0402_5%

SD028100280

LVDS Conn.

mHDMI Conn.

mDP Conn.

2-Ch. SPK Conn.

TN-Note

Block Diagram

U5008

U5007

DDR2@

ELIPDA 8G

SA000058U20

UD3

UD4

DDR2@

ELIPDA 8G

SA000058U20

R1944

R5066

DDR2@

10K_0402_5%

SD028100280

P. 23

P. 24

P. 25

P. 28

DMIC

UCPU1

CPU2@

1.8G

SA00005L5H0

UCPU1

CPU6@

1.4G

SA00005UH60

ZZZ1

X76E4G@

ELPIDA_4G

X7639839L07

ZZZ4

X76E2G@

ELPIDA_2G

X7639839L10

Audio Codec

ALC3202

Combo Jack Conn.

P. 29

Card Reader

RTS5229

P. 22

CPU3@

SA00005K6I0

X76H4G@

HYNIX_4G

X7639839L08

X76H2G@

HYNIX_2G

X7639839L11

P. 28

1X

UCPU1

1.7G

ZZZ2

ZZZ5

UCPU1

CPU4@

1.8G

SA00005L9F0

ZZZ3

X76S4G@

SAMSUNG_4G

X7639839L09

LVDS

HDMI

DP

HDA

PCI-E

BIOS ROM

(8M+4M)

UCPU1

CPU5@

1.9G

SA00005K5E0

SPI

SA00005L5H0 S IC AV8063801058401 SR0N9 L1 1.8G A39!

CPU2@

SA00005K6I0 S IC AV8063801058002 SR0N8 L1 1.7G A39!

CPU3@

SA00005L9F0 S IC AV8063801057801 SR0N7 L1 1.8G A39!CPU4@

CPU5@ SA00005K5E0 S IC AV8063801057605 SR0N6 L1 1.9G A39!

CPU6@ SA00005UH60 S IC AV8062701313000 SR0U3 J1 1.4G A39!

Intel

Ivy Bridge

BGA

Single Channel

DDR3-1333(1.5V)

P. 04~09

FDI

DMI

USB3.0

Intel

USB2.0

Panther Point

SATA

P. 12~20

LPC

P. 12

TPM

P. 36

USB 2.0

Sub-board

1. PWR Board (LS-8671P)

2. HDD Board (LS-8672P)

3. P-Sensor1 Board (LS-8673P)

4. P-Sensor2 Board (LS-8674P)

DDR3 Chip x8

P. 10~11

USB 3.0 Conn. - L

USB 3.0 Conn. - R

Sensor Hub

STM32F103CBU6TR LSM303DLHCTR

Touch Panel (LVDS Conn.)

P. 21

P. 26

P. 27

ALS (PWR/B Conn.)

CM3218

Accelerometer & eCompass

Gyro

L3GD20TR

P. 23

PWR/B

P. 37

P. 21

EC

3 3

LAN

RTL8111F

RJ45 Conn.

P. 30

P. 31

mini PCI-E Half Card Conn.

WLAN & BT

P. 32

(WLAN)

USB(BT)

1X

Thermal Sensor

Fintek 75303M

ENE KB9012

APS

LIS34ALTR

P. 33

P. 34

P. 33

Click Pad

P. 35

Track Point

Int.KBD

P. 35

DMIC

(WWAN)

(mSATA)

Camera & DMIC (LVDS Conn.)

mini PCI-E Full Card Conn.

WWAN/mSATA

P. 32

P. 23

SIM Conn.

P. 32

PCH_GPIO

4 4

PCH_GPIO

AMY WEN

A

P-Sensor2 Conn.

B

P-Sensor2/B (Left)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HDD BTB Conn.

Compal Secret Data

Deciphered Date

D

2012/08/252010/08/25

P. 36

P-Sensor1 Conn.

HDD/B

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

TN-Note Block Diagram

LA-8671P_SDV

Thursday, October 04, 2012

E

1ACustom

502

A

B

C

D

E

Voltage Rails

Full ON

SIGNAL

SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS

H H H

L

L L

ON

HH

ON

H

ON

EC SM Bus2 address

Address Address

0001-011xb

0001-0010b

1010-100x b

1010-000x b

HEX

16H

12H

A8 H

A0 H

Device

Thermal sensor

PCH (SML1DATA / GPIO75)

ON ON

ON

OFF

1001-101x b

1001-0110 b

OFF

HEX

9AH

96H

STATE

1 1

Power plane

+5VALW

+B

State

S0

S3

M3

2 2

S4/S5 - AC

S4/S5 - BATT ONLY

S4/S5 - NO AC & BATT

O

X

+3VALW

+1.5V

O

X

X X X

+3VM

+1.05VM

O

O O

O

OOOO

X X

X

+5VS

+3VS

+1.8VS

+1.5VS

+1.05VS

+VCC_GFXCORE_AXG

+CPU_CORE

+VCCSA

+0.75VS

X

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

EC SM Bus1 address

Device

Smart Battery

Charger

SM Bus Controller

Device Address HEX

Security Rom

DDR DIMM0

BOM Structure

SDV FVT SIT SVT SOVP

@ : No Stuff

3 3

ME@ : ME components

CPUx@ : CPU SKU

DDRx@ : RAM SKU

SBA@ : SBA

V V

VV

V

NOSBA@ : NO SBA

ID4@ : Intel Deep S4

AOAC@ : AOAC

TPM@ : TPM

4 4

Short@ : 0ohm short pad

V

V V

V

SM Bus Controller 0

Device Address

No-use

HEX

No-use

Sensor HUB

Device Address HEX

ALS

APS

Gyroscope

e-Compass

0100-100x b

0011-001x b

0110-101xb

0011-110x b

48h

32h

6Ah

3Ch

BOARD ID Table

Board ID

0 1 2 3 4 5 6 7

1

2

3

4 3

PCB Revision

0.1

0.2

0.3

0.4

0.5

USB2.0USB3.0 NOTE

0

USB3.0/2.0 Conn

1 *

USB3.0/2.0 Conn

2

Sensor Hub

4

USB Camera

5

6

7

8

9 *

10

11

12

13

X

Touch Panel

WWAN

WLAN

Finger Printer**

Bluetooth**

* Debug Port

** Not Use

AMY WEN

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2011/05/16 2013/05/16

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

LA-8671P

E

3 50Thursday, October 04, 2012

1A

A

1 1

UCPU1A

DMI_CRX_PTX_N0[14] DMI_CRX_PTX_N1[14] DMI_CRX_PTX_N2[14] DMI_CRX_PTX_N3[14]

DMI_CRX_PTX_P0[14] DMI_CRX_PTX_P1[14] DMI_CRX_PTX_P2[14] DMI_CRX_PTX_P3[14]

DMI_CTX_PRX_N0[14] DMI_CTX_PRX_N1[14] DMI_CTX_PRX_N2[14] DMI_CTX_PRX_N3[14]

DMI_CTX_PRX_P0[14] DMI_CTX_PRX_P1[14] DMI_CTX_PRX_P2[14] DMI_CTX_PRX_P3[14]

FDI_CTX_PRX_N0[1 4]

+1.05VS

FDI_CTX_PRX_N1[1 4] FDI_CTX_PRX_N2[1 4] FDI_CTX_PRX_N3[1 4] FDI_CTX_PRX_N4[1 4] FDI_CTX_PRX_N5[1 4] FDI_CTX_PRX_N6[1 4] FDI_CTX_PRX_N7[1 4]

FDI_CTX_PRX_P0[14] FDI_CTX_PRX_P1[14] FDI_CTX_PRX_P2[14] FDI_CTX_PRX_P3[14] FDI_CTX_PRX_P4[14] FDI_CTX_PRX_P5[14] FDI_CTX_PRX_P6[14] FDI_CTX_PRX_P7[14]

FDI_FSYNC0[14] FDI_FSYNC1[14]

FDI_INT[14]

FDI_LSYNC0[14] FDI_LSYNC1[14]

1 2

R7 24.9_0402_1%R7 24.9_0402_1%

2 2

3 3

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_FSYNC0 FDI_FSYNC1

FDI_INT

FDI_LSYNC0 FDI_LSYNC1

+EDP_COM

M2

DMI_RX#[0]

P6

DMI_RX#[1]

P1

DMI_RX#[2]

P10

DMI_RX#[3]

N3

DMI_RX[0]

P7

DMI_RX[1]

P3

DMI_RX[2]

P11

DMI_RX[3]

K1

DMI_TX#[0]

M8

DMI_TX#[1]

N4

DMI_TX#[2]

R2

DMI_TX#[3]

K3

DMI_TX[0]

M7

DMI_TX[1]

P4

DMI_TX[2]

T3

DMI_TX[3]

U7

FDI0_TX#[0]

W11

FDI0_TX#[1]

W1

FDI0_TX#[2]

AA6

FDI0_TX#[3]

W6

FDI1_TX#[0]

V4

FDI1_TX#[1]

Y2

FDI1_TX#[2]

AC9

FDI1_TX#[3]

U6

FDI0_TX[0]

W10

FDI0_TX[1]

W3

FDI0_TX[2]

AA7

FDI0_TX[3]

W7

FDI1_TX[0]

T4

FDI1_TX[1]

AA3

FDI1_TX[2]

AC8

FDI1_TX[3]

AA11

FDI0_FSYNC

AC12

FDI1_FSYNC

U11

FDI_INT

AA10

FDI0_LSYNC

AG8

FDI1_LSYNC

AF3

eDP_COMPIO

AD2

eDP_ICOMPO

AG11

eDP_HPD#

AG4

eDP_AUX#

AF4

eDP_AUX

AC3

eDP_TX#[0]

AC4

eDP_TX#[1]

AE11

eDP_TX#[2]

AE7

eDP_TX#[3]

AC1

eDP_TX[0]

AA4

eDP_TX[1]

AE10

eDP_TX[2]

AE6

eDP_TX[3]

IVY-BRIDGE_BGA1023

CPU1@

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0] PEG_RX#[1]

DMI Intel(R) FDI

eDP

PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PCI EXPRESS -- GRAPHICS

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

B

+1.05VS

12

R6

24.9_0402_1%

G3 G1 G4

H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7

K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6

G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4

F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4

PEG_COMP

PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms PEG_ICOMPO signals should be routed with - max length = 500 mils

- typical impedance = 14.5 mohms

PEG Static Lane Reversal - CFG 2 is for the 16x

CFG2

C

1: Normal Opera tion; Lane # defi nition matches socket pin map definition

*

0:Lane Reversed

D

UCPU1I

BG17

VSS[181]

BG21

VSS[182]

BG24

VSS[183]

BG28

VSS[184]

BG37

VSS[185]

BG41

VSS[186]

BG45

VSS[187]

BG49

VSS[188]

BG53

VSS[189]

BG9

VSS[190]

C29

VSS[191]

C35

VSS[192]

C40

VSS[193]

D10

VSS[194]

D14

VSS[195]

D18

VSS[196]

D22

VSS[197]

D26

VSS[198]

D29

VSS[199]

D35

VSS[200]

D4

VSS[201]

D40

VSS[202]

D43

VSS[203]

D46

VSS[204]

D50

VSS[205]

D54

VSS[206]

D58

VSS[207]

D6

VSS[208]

E25

VSS[209]

E29

VSS[210]

E3

VSS[211]

E35

VSS[212]

E40

VSS[213]

F13

VSS[214]

F15

VSS[215]

F19

VSS[216]

F29

VSS[217]

F35

VSS[218]

F40

VSS[219]

F55

VSS[220]

G51

VSS[221]

G6

VSS[222]

G61

VSS[223]

H10

VSS[224]

H14

VSS[225]

H17

VSS[226]

H21

VSS[227]

H4

VSS[228]

H53

VSS[229]

H58

VSS[230]

J1

VSS[231]

J49

VSS[232]

J55

VSS[233]

K11

VSS[234]

K21

VSS[235]

K51

VSS[236]

K8

VSS[237]

L16

VSS[238]

L20

VSS[239]

L22

VSS[240]

L26

VSS[241]

L30

VSS[242]

L34

VSS[243]

L38

VSS[244]

L43

VSS[245]

L48

VSS[246]

L61

VSS[247]

M11

VSS[248]

M15

VSS[249]

IVY-BRIDGE_BGA1023

CPU1@

VSS

VSS_NCTF_10 VSS_NCTF_11

NCTF

VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14

VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301]

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9

E

M4 M58 M6 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P14 P16 P18 P21 P58 P59 P9 R17 R20 R4 R46 T1 T47 T50 T51 T52 T53 T55 T56 U13 U8 V20 V61 W13 W15 W18 W21 W46 W8 Y4 Y47 Y58 Y59 G48

A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61

T90 @PADT90 @PAD T91 @PADT91 @PAD

T95 @PADT95 @PAD T96 @PADT96 @PAD T97 @PADT97 @PAD

T103 @PADT103 @PAD T98 @PADT98 @PAD

4 4

Security Classif ication

AMY WEN

Security Classif ication

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/05/16 2013/05/16

Compal Secret Data

Deciphered D ate

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(1/6) DMI,FDI,PEG

LA-8671P_SDV

E

4 50Thursday, October 04, 2012

1.0

5

PROC_DETECT (Processor Detect): pulled to

D D

C C

B B

H_CPUPWRGD[17]

PM_DRAM_PWRGD[14]

RUN_ON_CPU1.5VS3#[9]

ground on the processor package. There is no connection to the processor silicon for this signal. System board designers may use this signal to determine if the processor is present

H_PROCHOT#[34]

R14

R14 0_0402_5%

0_0402_5%

1 2

short@

1

C5236

@

100P_0402_ 50V8J

+3VS

100P_0402_ 50V8J

ESD C Reserve

0.1U_0402_ 16V4Z

@

R31

R31 10K_0402_5 %

10K_0402_5 %

1 2

2

@

12

C33

1

2

1 2

R532 0_0 402_5%R532 0_0 402_5%

RUN_ON_CPU 1.5VS3#

R13

62_0402_5 %

R28

R28 10K_0402_5 %

10K_0402_5 %

1 2

+3VALW

U1

@

5

P

B

4

PM_SYS_PWRGD_BUF

O

A

G

74AHC1G09GW _TSSOP5

3

2N7002K_SOT 23-3

+1.05VS

1 2

H_THERMTRIP#[17]

H_PM_SYNC[14]

+1.5V_CPU_VDDQ

12

R33@

R33@ 39_0402_5 %

39_0402_5 %

13

D

2

G

Q4

S

@

4

UCPU1B

H_SNB_IVB#[17]

12

R11 @ 10K_0402_5 %R11 @ 10K _0402_5%

T1 @PAD~D T1 @PAD~D

H_PECI[17,34] H_DRAMRST# [6]

1 2

12

R30

R30 200_0402_ 5%

200_0402_ 5%

H_CATERR#

R15

H_PROCHOT#_R

56_0402_5 %

H_THERMTRIP#

H_CPUPW RGD_R

R29

VDDPWRGOOD_R XDP_BPM#0

130_0402_ 1%

BUF_CPU_RST#

F49

C57

C49

A48

C45

D45

C48

B46

BE45

D44

C38

0.1U_0402_ 16V4Z

@

PROC_SELECT#

PROC_DETECT#

CATERR#

PECI

PROCHOT#

THERMTRIP#

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPWROK

RESET#

IVY-BRIDGE_BGA1023

CPU1@

75_0402_5 %

R34

43_0402_5 %

1 2

12

+1.05VS

R32

SN74LVC1G07D CKR_SC70-5

MISC THERMAL PWR MANAGEMENT

Buffered reset to CPU

0.1U_0402_ 16V4Z

12

BUFO_CPU_RST#

3

J3

CLK_CPU_DMI_R

BCLK

H2

CLK_CPU_DMI#_R

AG3

R9 1K_0402_5%R9 1K_0402_5%

AG1

R10 1K_0402_ 5%R10 1K_0402_ 5%

AT30

H_DRAMRST#

BF44

SM_RCOMP0

BE43

SM_RCOMP1

BG43

SM_RCOMP2

DDR3 Compensation Signals

N53

XDP_PRDY#

N55

XDP_PREQ#

L56

XDP_TCK

TCK

L55

XDP_TMS

TMS

J58

XDP_TRST#

M60

XDP_TDI

TDI

L59

XDP_TDO

TDO

K58

DBR#

G58 E55

XDP_BPM#1

E59

XDP_BPM#2

G55

XDP_BPM#3

G59

XDP_BPM#4

H60

XDP_BPM#5

J59

XDP_BPM#6

J61

XDP_BPM#7

12 12

+3VS

12

PCH_PLTRST# [16,36]

1 2 1 2 1 2

R27

R27 1K_0402_5%

1K_0402_5%

XDP_DBRESET#

DDR3

C34

CLOCKS

JTAG & BPM

U3

4

DPLL_REF_CLK

DPLL_REF_CLK#

SM_DRAMRST#

MISC

+3VS

12

5

Y

3

BCLK#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PRDY#

PREQ#

TRST#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

1

P

NC

2

PCH_PLTRST#

A

G

2

1 2

R833_04 02_5% R833_04 02_5%

1 2

R1233 _0402_5% R123 3_0402_5%

+1.05VS

R16140_0402_ 1% R16140_0402_1 % R1725.5_0402_1 % R1725.5 _0402_1% R18200_0402_ 1% R18200_0402_1 %

+1.05VS

C5237

0.1U_0402_ 16V4Z

@

ESD R532, C39 Reserve

C82

@ C82

@

100P_0402_ 50V8J

ESD C Reserve

XDP_DBRESET# [12,14]

PBTN_OUT#[12,14,34]

+1.05VS

PCH_PLTRST# XDP_DBRESET#

12

CLK_CPU_DMI [13] CLK_CPU_DMI# [13]

1

2

H_CPUPWRGD

XDP_CFG0[7] SYS_PWROK[14] CLK_XDP_CLK[13] CLK_XDP_CLK#[13]

1 2

R55 1K_0402_ 1%

XDP_TDO XDP_TRST# XDP_TDI XDP_TMS

XDP_TCK

PU/PD for JTAG signals

XDP_TMS

R20 51_0402_5 %R20 51_0402_5 %

XDP_TDI

R21 51_0402_5 %R21 51_0402_5 %

XDP_TDO

R22 51_0402_5 %R22 51_0402_5 %

XDP_TCK

R24 51_0402_5 %R24 51_0402_5 %

XDP_TRST#

R25 51_0402_5 %R25 51_0402_5 %

XDP_PREQ# XDP_PRDY#

@

1 2

R52 1K_0402_1%

@

1 2

R531 0_0402_5%

@

1 2

R54 1K_0402_1%

@

1 2

R397 0_0402_5%

@

1 2

R389 0_0402_5%

@

1 2

R400 0_0402_5%

@

1

12 12 12

12 12

CLK_XDP_CLK_ R CLK_XDP_CLK# _R

+1.05VS

JDB1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

G1

28

G2

ACES_88717-26 01

ME@

A A

Security Classification

AMY WEN

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/05/16 2013/05/16

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(2/6) PM,XDP,CLK

LA-8671P_SDV

1

5 50Thursday, October 04, 201 2

1.0

5

UCPU1C

D D

DDR_A_D[0..63][10,11]

C C

B B

A A

DDR_A_BS0[10,11] DDR_A_BS1[10,11] DDR_A_BS2[10,11]

DDR_A_CAS#[10,11] DDR_A_RAS#[10,11] DDR_A_WE#[10,11]

H_DRAMRST#[5]

DRAMRST_CNTRL_PCH[13,9]

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

H_DRAMRST#

UCPU1C

AG6

SA_DQ[0]

AJ6

SA_DQ[1]

AP11

SA_DQ[2]

AL6

SA_DQ[3]

AJ10

SA_DQ[4]

AJ8

SA_DQ[5]

AL8

SA_DQ[6]

AL7

SA_DQ[7]

AR11

SA_DQ[8]

AP6

SA_DQ[9]

AU6

SA_DQ[10]

AV9

SA_DQ[11]

AR6

SA_DQ[12]

AP8

SA_DQ[13]

AT13

SA_DQ[14]

AU13

SA_DQ[15]

BC7

SA_DQ[16]

BB7

SA_DQ[17]

BA13

SA_DQ[18]

BB11

SA_DQ[19]

BA7

SA_DQ[20]

BA9

SA_DQ[21]

BB9

SA_DQ[22]

AY13

SA_DQ[23]

AV14

SA_DQ[24]

AR14

SA_DQ[25]

AY17

SA_DQ[26]

AR19

SA_DQ[27]

BA14

SA_DQ[28]

AU14

SA_DQ[29]

BB14

SA_DQ[30]

BB17

SA_DQ[31]

BA45

SA_DQ[32]

AR43

SA_DQ[33]

AW48

SA_DQ[34]

BC48

SA_DQ[35]

BC45

SA_DQ[36]

AR45

SA_DQ[37]

AT48

SA_DQ[38]

AY48

SA_DQ[39]

BA49

SA_DQ[40]

AV49

SA_DQ[41]

BB51

SA_DQ[42]

AY53

SA_DQ[43]

BB49

SA_DQ[44]

AU49

SA_DQ[45]

BA53

SA_DQ[46]

BB55

SA_DQ[47]

BA55

SA_DQ[48]

AV56

SA_DQ[49]

AP50

SA_DQ[50]

AP53

SA_DQ[51]

AV54

SA_DQ[52]

AT54

SA_DQ[53]

AP56

SA_DQ[54]

AP52

SA_DQ[55]

AN57

SA_DQ[56]

AN53

SA_DQ[57]

AG56

SA_DQ[58]

AG53

SA_DQ[59]

AN55

SA_DQ[60]

AN52

SA_DQ[61]

AG55

SA_DQ[62]

AK56

SA_DQ[63]

BD37

SA_BS[0]

BF36

SA_BS[1]

BA28

SA_BS[2]

BE39

SA_CAS#

BD39

SA_RAS#

AT41

SA_WE#

IVY-BRIDGE_BGA1023

CPU1@

R39

4.99K_0402_1%

1 2

DRAMRST_CNTRL_PCH

R36@

0_0402_5%

1 2

D

S

D

S

123

G

BSS138_NL_SOT23-3

DDR SYSTEM MEMORY A

DDR3_DRAMRST#_R

Q5

1K_0402_5%

SA_CK[0]

SA_CK#[0]

SA_CKE[0]

SA_CK[1]

SA_CK#[1]

SA_CKE[1]

SA_CS#[0] SA_CS#[1]

SA_ODT[0] SA_ODT[1]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

+1.5V

R37

12

4

AU36 AV36 AY26

AT40 AU40 BB26

BB40 BC41

AY40 BA41

AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55

AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54

BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26

R38

R38 1K_0402_5%

1K_0402_5%

1 2

M_CLK_DDR0 M_CLK_DDR#0 DDR_CKE0_DIMMA

M_CLK_DDR1 M_CLK_DDR#1 DDR_CKE1_DIMMA

DDR_CS0_DIMMA# DDR_CS1_DIMMA#

M_ODT0 M_ODT1

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

M_CLK_DDR0 [10] M_CLK_DDR#0 [10] DDR_CKE0_DIMMA [10]

M_CLK_DDR1 [10,11] M_CLK_DDR#1 [10,11] DDR_CKE1_DIMMA [10,11]

DDR_CS0_DIMMA# [10] DDR_CS1_DIMMA# [10,11]

M_ODT0 [10] M_ODT1 [10,11]

DDR_A_DQS#[0..7] [10,11]

DDR_A_DQS[0..7] [10,11]

DDR_A_MA[0..15] [10,11]

DDR3_DRAMRST# [10,11]

3

2

UCPU1D

AL4

SB_DQ[0]

AL1

SB_DQ[1]

AN3

SB_DQ[2]

AR4

SB_DQ[3]

AK4

SB_DQ[4]

AK3

SB_DQ[5]

AN4

SB_DQ[6]

AR1

SB_DQ[7]

AU4

SB_DQ[8]

AT2

SB_DQ[9]

AV4

SB_DQ[10]

BA4

SB_DQ[11]

AU3

SB_DQ[12]

AR3

SB_DQ[13]

AY2

SB_DQ[14]

BA3

SB_DQ[15]

BE9

SB_DQ[16]

BD9

SB_DQ[17]

BD13

SB_DQ[18]

BF12

SB_DQ[19]

BF8

SB_DQ[20]

BD10

SB_DQ[21]

BD14

SB_DQ[22]

BE13

SB_DQ[23]

BF16

SB_DQ[24]

BE17

SB_DQ[25]

BE18

SB_DQ[26]

BE21

SB_DQ[27]

BE14

SB_DQ[28]

BG14

SB_DQ[29]

BG18

SB_DQ[30]

BF19

SB_DQ[31]

BD50

SB_DQ[32]

BF48

SB_DQ[33]

BD53

SB_DQ[34]

BF52

SB_DQ[35]

BD49

SB_DQ[36]

BE49

SB_DQ[37]

BD54

SB_DQ[38]

BE53

SB_DQ[39]

BF56

SB_DQ[40]

BE57

SB_DQ[41]

BC59

SB_DQ[42]

AY60

SB_DQ[43]

BE54

SB_DQ[44]

BG54

SB_DQ[45]

BA58

SB_DQ[46]

AW59

SB_DQ[47]

AW58

SB_DQ[48]

AU58

SB_DQ[49]

AN61

SB_DQ[50]

AN59

SB_DQ[51]

AU59

SB_DQ[52]

AU61

SB_DQ[53]

AN58

SB_DQ[54]

AR58

SB_DQ[55]

AK58

SB_DQ[56]

AL58

SB_DQ[57]

AG58

SB_DQ[58]

AG59

SB_DQ[59]

AM60

SB_DQ[60]

AL59

SB_DQ[61]

AF61

SB_DQ[62]

AH60

SB_DQ[63]

BG39

SB_BS[0]

BD42

SB_BS[1]

AT22

SB_BS[2]

AV43

SB_CAS#

BF40

SB_RAS#

BD45

SB_WE#

IVY-BRIDGE_BGA1023

CPU1@

1

BA34

SB_CK[0]

AY34

SB_CK#[0]

AR22

SB_CKE[0]

BA36

SB_CK[1]

BB36

SB_CK#[1]

BF27

SB_CKE[1]

BE41

SB_CS#[0]

BE47

SB_CS#[1]

AT43

SB_ODT[0]

BG47

SB_ODT[1]

AL3

SB_DQS#[0]

AV3

SB_DQS#[1]

BG11

SB_DQS#[2]

BD17

SB_DQS#[3]

BG51

SB_DQS#[4]

BA59

SB_DQS#[5]

AT60

SB_DQS#[6]

AK59

SB_DQS#[7]

AM2

SB_DQS[0]

AV1

SB_DQS[1]

BE11

SB_DQS[2]

BD18

SB_DQS[3]

BE51

SB_DQS[4]

BA61

SB_DQS[5]

AR59

SB_DQS[6]

AK61

SB_DQS[7]

DDR SYSTEM MEMORY B

BF32

SB_MA[0]

BE33

SB_MA[1]

BD33

SB_MA[2]

AU30

SB_MA[3]

BD30

SB_MA[4]

AV30

SB_MA[5]

BG30

SB_MA[6]

BD29

SB_MA[7]

BE30

SB_MA[8]

BE28

SB_MA[9]

BD43

SB_MA[10]

AT28

SB_MA[11]

AV28

SB_MA[12]

BD46

SB_MA[13]

AT26

SB_MA[14]

AU22

SB_MA[15]

AMY WEN

5

12

C35

0.047U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/05/16 2013/05/16

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(3/6) DDRIII

LA-8671P_SDV

1

1.0

6 50Thursday, October 04, 2012

1.0

5

4

3

2

1

CFG Straps for Processor

UCPU1E

D D

XDP_CFG0[5]

+CPU_CORE

+VCC_GFXCORE_AXG

C C

B B

R43

49.9_0402_1%

R44

49.9_0402_1%

R45

49.9_0402_1%

R46

49.9_0402_1%

12

R91

R91 100_0402_1%~D

100_0402_1%~D

@

1 2

12

R89

R89 100_0402_1%~D

100_0402_1%~D

@

1 2

12

XDP_CFG0

CFG2

CFG4 CFG5 CFG6 CFG7

VCC_VAL_SENSE VSS_VAL_SENSE

VCC_AXG_VAL_SENSE VSS_AXG_VAL_SENSE

T20 @

PAD~D

UCPU1E

B50

CFG[0]

C51

CFG[1]

B54

CFG[2]

D53

CFG[3]

A51

CFG[4]

C53

CFG[5]

C55

CFG[6]

H49

CFG[7]

A55

CFG[8]

H51

CFG[9]

K49

CFG[10]

K53

CFG[11]

F53

CFG[12]

G53

CFG[13]

L51

CFG[14]

F51

CFG[15]

D52

CFG[16]

L53

CFG[17]

H43

VCC_VAL_SENSE

K43

VSS_VAL_SENSE

H45

VAXG_VAL_SENSE

K45

VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

H48

RSVD6

K48

RSVD7

BA19

RSVD8

AV19

RSVD9

AT21

RSVD10

BB21

RSVD11

BB19

RSVD12

AY21

RSVD13

BA22

RSVD14

AY22

RSVD15

AU19

RSVD16

AU21

RSVD17

BD21

RSVD18

BD22

RSVD19

BD25

RSVD20

BD26

RSVD21

BG22

RSVD22

BE22

RSVD23

BG26

RSVD24

BE26

RSVD25

BF23

RSVD26

BE24

RSVD27

IVY-BRIDGE_BGA1023

CPU1@

RESERVED

BCLK_ITP

BCLK_ITP#

RSVD30 RSVD31 RSVD32 RSVD33

RSVD34 RSVD35 RSVD36 RSVD37 RSVD38

RSVD39 RSVD40

RSVD41 RSVD42 RSVD43 RSVD44

RSVD45

DC_TEST_A4 DC_TEST_C4 DC_TEST_D3

DC_TEST_D1 DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61 DC_TEST_D61

DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58

DC_TEST_BG4 DC_TEST_BG3 DC_TEST_BE3 DC_TEST_BG1 DC_TEST_BE1 DC_TEST_BD1

N59 N58

N42 L42 L45 L47

M13 M14 U14 W14 P13

AT49 K24

AH2 AG13 AM14 AM15

N50

A4 C4 D3 D1 A58 A59 C59 A61 C61 D61 BD61 BE61 BE59 BG61 BG59 BG58 BG4 BG3 BE3 BG1 BE1 BD1

PEG Static Lane Reversal - CFG2 is for the 16x

Display Port Presence Strap

PCIE Port Bifurcation Straps

CFG[6:5]

CFG2

12

R41

@R41

@

1K_0402_1%~D

1:(Default) Nor mal Operation; Lan e #

*

CFG2

definition matc hes socket pin map definition 0:Lane Reversed

CFG4

12

R42@

R42@ 1K_0402_1%~D

1K_0402_1%~D

1 : Disabled; N o Physical Display Port

*

CFG4

attached to Emb edded Display Port

0 : Enabled; An external Display Port device is connected to th e Embedded Display Port

CFG6

CFG5

12

R49@

1K_0402_1%~D

11: (Default) x 16 - Device 1 func tions 1 and 2 disab led

*

10: x8, x8 - De vice 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; funct ion 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

R50@

R50@ 1K_0402_1%~D

1K_0402_1%~D

CFG7

12

R51@

R51@ 1K_0402_1%~D

1K_0402_1%~D

PEG DEFER TRAINING

1: (Default) PE G Train immediatel y

*

CFG7

following xxRES ETB de assertion

0: PEG Wait for BIOS for training

A A

AMY WEN

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/05/16 2013/05/16

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(4/6) RSVD,CFG

LA-8671P_SDV

1

7 50Thursday, October 04, 2012

1.0

5

D D

CPU_CORE GFX_CORE VCCP1.05

VGA_CORE

All Capacitor place on Power side.

C C

B B

A A

4

UCPU1F

+CPU_CORE

A26

VCC[1]

A29

VCC[2]

A31

VCC[3]

A34

VCC[4]

A35

VCC[5]

A38

VCC[6]

A39

VCC[7]

A42

VCC[8]

C26

VCC[9]

C27

VCC[10]

C32

VCC[11]

C34

VCC[12]

C37

VCC[13]

C39

VCC[14]

C42

VCC[15]

D27

VCC[16]

D32

VCC[17]

D34

VCC[18]

D37

VCC[19]

D39

VCC[20]

D42

VCC[21]

E26

VCC[22]

E28

VCC[23]

E32

VCC[24]

E34

VCC[25]

E37

VCC[26]

E38

VCC[27]

F25

VCC[28]

F26

VCC[29]

F28

VCC[30]

F32

VCC[31]

F34

VCC[32]

F37

VCC[33]

F38

VCC[34]

F42

VCC[35]

G42

VCC[36]

H25

VCC[37]

H26

VCC[38]

H28

VCC[39]

H29

VCC[40]

H32

VCC[41]

H34

VCC[42]

H35

VCC[43]

H37

VCC[44]

H38

VCC[45]

H40

VCC[46]

J25

VCC[47]

J26

VCC[48]

J28

VCC[49]

J29

VCC[50]

J32

VCC[51]

J34

VCC[52]

J35

VCC[53]

J37

VCC[54]

J38

VCC[55]

J40

VCC[56]

J42

VCC[57]

K26

VCC[58]

K27

VCC[59]

K29

VCC[60]

K32

VCC[61]

K34

VCC[62]

K35

VCC[63]

K37

VCC[64]

K39

VCC[66]

K42

VCC[67]

L25

VCC[68]

L28

VCC[69]

L33

VCC[70]

L36

VCC[71]

L40

VCC[72]

N26

VCC[73]

N30

VCC[74]

N34

VCC[75]

N38

VCC[76]

IVY-BRIDGE_BGA1023

CPU1@

3

POWER

CORE SUPPLY

VCCIO[1] VCCIO[3] VCCIO[4] VCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8]

VCCIO[9] VCCIO[10] VCCIO[11] VCCIO[12] VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16] VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20] VCCIO[21] VCCIO[22] VCCIO[23] VCCIO[24] VCCIO[25] VCCIO[26] VCCIO[27] VCCIO[28] VCCIO[29]

VCCIO[30] VCCIO[31] VCCIO[32]

PEG IO AND DDR IO

VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49]

VCCIO50

VCCIO51

VCCIO_SEL

VCCPQE[1] VCCPQE[2]

RAILS

VIDALERT#

VIDSCLK

VIDSOUT

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID QUIET

AF46 AG48 AG50 AG51 AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48

AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15

W16 W17

BC22

AM25 AN22

A44 B43 C44

F43 G43

AN16 AN17

VCCSENSE_R VSSSENSE_R

H_VCCP_SEL

1 2

C106

C106 1U_0402_6.3V6K

1U_0402_6.3V6K

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

1 2

R617 10_0402_1%R617 10_0402_1%

VSS_SENSE_VCCIO

2

+1.05VS

Chief river VCC IO_SEL pull-H

+1.05VS

+3VS

12

R5157

R5157 10K_0402_5%

10K_0402_5%

R58

43_0402_5%

1 2

R59 0_0402_5%

short@

R60 0_0402_5%

short@

R62 0_0402_5%

R62 0_0402_5% R63 0_0402_5%

R63 0_0402_5%

12

short@

12

short@

+1.05VS

1 2

R618 10_0402_1%R618 10_0402_1%

VCCIO_SENSE [46] VSS_SENSE_VCCIO [46]

12 12

+1.05VS

130_0402_1%~D

1 2

R79

100_0402_1%~D

@

1

+1.05VS

12

R56

+CPU_CORE

12

R57

R57 75_0402_5%

75_0402_5%

R61

R61 100_0402_1%~D

100_0402_1%~D

R64

R64 100_0402_1%~D

100_0402_1%~D

Place the PU resistors close to CPU

VR_SVID_ALRT# [47] VR_SVID_CLK [47] VR_SVID_DAT [47]

Place the PU resistors close to CPU

VCCSENSE [ 47] VSSSENSE [47]

Place the PU resistors close to VR

AMY WEN

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/05/16 2013/05/16

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(5/6) PWR,BYPASS

LA-8671P_SDV

8 50Thursday, October 04, 2012

1

1.0

5

4

3

2

1

+1.5V

1 2

PAD-OPEN 4x4m

12

RUN_ON_CPU1.5VS3#

13

D

S

AA46 AB47 AB50 AB51 AB52 AB53 AB55 AB56 AB58 AB59 AC61 AD47 AD48 AD50 AD51 AD52 AD53 AD55 AD56 AD58 AD59 AE46

W50 W51 W52 W53 W55 W56 W61

BC1 BC4

W20

1 2

R650_0402_5% R650_0402_5%

UCPU1G

VAXG[1] VAXG[2] VAXG[3] VAXG[4] VAXG[5] VAXG[6] VAXG[7] VAXG[8] VAXG[9] VAXG[10] VAXG[11] VAXG[12] VAXG[13] VAXG[14] VAXG[15] VAXG[16] VAXG[17] VAXG[18] VAXG[19] VAXG[20] VAXG[21] VAXG[22]

N45

VAXG[23]

P47

VAXG[24]

P48

VAXG[25]

P50

VAXG[26]

P51

VAXG[27]

P52

VAXG[28]

P53

VAXG[29]

P55

VAXG[30]

P56

VAXG[31]

P61

VAXG[32]

T48

VAXG[33]

T58

VAXG[34]

T59

VAXG[35]

T61

VAXG[36]

U46

VAXG[37]

V47

VAXG[38]

V48

VAXG[39]

V50

VAXG[40]

V51

VAXG[41]

V52

VAXG[42]

V53

VAXG[43]

V55

VAXG[44]

V56

VAXG[45]

V58

VAXG[46]

V59

VAXG[47] VAXG[48] VAXG[49] VAXG[50] VAXG[51] VAXG[52] VAXG[53] VAXG[54]

Y48

VAXG[55]

Y61

VAXG[56]

F45

VAXG_SENSE

G45

VSSAXG_SENSE

BB3

VCCPLL[1] VCCPLL[2] VCCPLL[3]

L17

VCCSA[1]

L21

VCCSA[2]

N16

VCCSA[3]

N20

VCCSA[4]

N22

VCCSA[5]

P17

VCCSA[6]

P20

VCCSA[7]

R16

VCCSA[8]

R18

VCCSA[9]

R21

VCCSA[10]

U15

VCCSA[11]

V16

VCCSA[12]

V17

VCCSA[13]

V18

VCCSA[14]

V21

VCCSA[15] VCCSA[16]

IVY-BRIDGE_BGA1023

CPU1@

+VSB

12

13

D

2

G

S

RUN_ON_CPU1.5VS3# [5]

POWER

GRAPHICS

SENSE

LINES

SENSE

LINES

1.8V RAIL

SA RAIL

SUSP[39,46]

+3VALW

R67

D D

@

12

R71 0_0402_5%

SUSP#[ 34,39,42,44,46]

R71 0_0402_5%

1 2

@

R70

0_0402_5% R70

0_0402_5%

CPU1.5V_S3_GATE[34]

100K_0402_5% @

Q6

2N7002K_SOT23-3

R67

2

G

@

+VCC_GFXCORE_AXG

C C

+VCC_GFXCORE_AXG

B B

VCC_AXG_SENSE[47]

VSS_AXG_SENSE[47]

+1.8VS

+VCCSA

C158

330U_D2_2VM_R9M~D

A A

VCC_AXG_SENSE VSS_AXG_SENSE

22U_0805_6.3V6M@C633

22U_0805_6.3V6M

@

10U_0603_6.3V6M~D

12

+

R620

R620 100_0402_1%~D

100_0402_1%~D

1 2

R619 100_0402_1%~DR619 100_0402_1%~D

10U_0603_6.3V6M~D

C633

12

10U_0603_6.3V6M~D

12

C162

1 2

R88

100_0402_1%~D

@

1U_0402_6.3V6K~D

12

C153

12

C161

C164

1U_0402_6.3V6K

C164

1U_0402_6.3V6K

12

C155

C154

10U_0603_6.3V6M~D

12

C165

1U_0402_6.3V6K

C165

1U_0402_6.3V6K

12

10U_0603_6.3V6M~D

12

C163

C160

C159

C167

1U_0402_6.3V6K

C167

1U_0402_6.3V6K

C166

1U_0402_6.3V6K

C166

1U_0402_6.3V6K

C168

1U_0402_6.3V6K

C168

1U_0402_6.3V6K

12

R68

R68 82K_0402_5%

82K_0402_5%

RUN_ON_CPU1.5VS3

Q8

Q8 2N7002K_SOT23-3

2N7002K_SOT23-3

SA_DIMM_VREFDQ SB_DIMM_VREFDQ

VREF

DDR3 - 1.5V RAILS

QUIET RAILS

VSS_SENSE_VDDQ

SENSE LINES

VCCSA VID

lines

VCCSA VID

lines

PAD-OPEN 4x4m

8 7 6 5

AO4430L_SO8

VDDQ_SENSE

VCCSA_SENSE

VCCSA_VID[0] VCCSA_VID[1]

AMY WEN

5

4

+1.5V_CPU_VDDQ

J1@

U7

1

S

D

2

S

D

3

S

D

G4D

R175

R175 15K_0402_1%

15K_0402_1%

1 2

12

R69

R69 330K_0402_5%

330K_0402_5%

@

Follw G-Series

AY43

SM_VREF

VDDQ[1] VDDQ[2] VDDQ[3] VDDQ[4] VDDQ[5] VDDQ[6] VDDQ[7] VDDQ[8]

VDDQ[9] VDDQ[10] VDDQ[11] VDDQ[12] VDDQ[13] VDDQ[14] VDDQ[15] VDDQ[16] VDDQ[17] VDDQ[18] VDDQ[19] VDDQ[20] VDDQ[21] VDDQ[22] VDDQ[23] VDDQ[24] VDDQ[25] VDDQ[26]

VCCDQ[1] VCCDQ[2]

+V_SM_VREF_CNT +V_SM_VREF

BE7

+V_DDR_REFA_R

BG7

+V_DDR_REFB_R

AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

AM28 AN26

BC43 BA43

U10

D48

VCCSA_VID0

D49

VCCSA_VID1

12

C108

0.047U_0603_25V7K

R173@

1K_0402_1%~D

12

1 2

C149

C149 1U_0402_6.3V6K

1U_0402_6.3V6K

220_0402_5%

2N7002K_SOT23-3

12

10U_0603_6.3V6M

C129

12

C140

1U_0402_6.3V6K

C140

1U_0402_6.3V6K

C139

1U_0402_6.3V6K

C139

1U_0402_6.3V6K

12

R66

13

D

Q7

S

+V_SM_VREF should have 20 mil trace width

12

R129@

R129@ 1K_0402_1%~D

1K_0402_1%~D

10U_0603_6.3V6M

C130

12

C141

1U_0402_6.3V6K

C141

1U_0402_6.3V6K

12

+1.5V_CPU_VDDQ

R99 0_0402_5%

1 2

short@

1 2

short@

R100 0_0402_5%

C131

C142

12

2

G

0.1U_0402_16V4Z

1U_0402_6.3V6K

C143

12

C107@

0.1U_0402_10V6K

RUN_ON_CPU1.5VS3#

+1.5V_CPU_VDDQ

12

R98

R98 1K_0402_1%~D

1K_0402_1%~D

12

C115

12

R92

R92 1K_0402_1%~D

1K_0402_1%~D

10U_0603_6.3V6M

12

1U_0402_6.3V6K

12

3

C135

C144

1U_0402_6.3V6K

C144

1U_0402_6.3V6K

R78@

0_0402_5%~D

H_VCCSA_VID0 [45] H_VCCSA_VID1 [45]

C137

C133

C134

12

C146

1U_0402_6.3V6K

C146

1U_0402_6.3V6K12C147

1U_0402_6.3V6K

C147

1U_0402_6.3V6K

C148

1U_0402_6.3V6K

C148

1U_0402_6.3V6K

12

+1.5V_CPU_VDDQ +1.5V

C150 0.1U_0402_10V7K~DC150 0.1U_0402_10V7K~D

C151 0.1U_0402_10V7K~DC151 0.1U_0402_10V7K~D

C152 0.1U_0402_10V7K~DC152 0.1U_0402_10V7K~D

C157 0.1U_0402_10V7K~DC157 0.1U_0402_10V7K~D

+VCCSA_SENSE [45]

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

C136

12

C145

12

1U_0402_6.3V6K

12

M3 Support

12

R72 0_0402_5%@R72 0_0402_5%@

D

S

D

S

123

Q11

Q11 AO3414_SOT23-3

AO3414_SOT23-3

G

@

RUN_ON_CPU1.5VS3

+1.5V_CPU_VDDQ

12

+

C132

C132 330U_D2_2VM_R9M

330U_D2_2VM_R9M

VID[0]

000

111

ULVVID[1] 2011 2012

0.90 V

YesNoYes

0.85 V

01

2011/05/16 2013/05/16

Yes

0.775 V

0.75 V

Compal Secret Data

Deciphered Date

2

Yes Yes YesNo

+V_DDR_REFA_R

+1.5V

12

R73@

R73@ 1K_0402_1%~D

1K_0402_1%~D

12

R75@

R75@ 1K_0402_1%~D

1K_0402_1%~D

1 2

R86 0_0402_5%@R86 0_0402_5%@

Q2204

Q2204 BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

D

S

D

S

13

G

2

DRAMRST_CNTRL_PCH

UCPU1H

A13

VSS[1]

A17

VSS[2]

A21

VSS[3]

A25

VSS[4]

A28

VSS[5]

A33

VSS[6]

A37

VSS[7]

A40

VSS[8]

A45

VSS[9]

A49

VSS[10]

A53

VSS[11]

A9

VSS[12]

AA1

VSS[13]

AA13

VSS[14]

AA50

VSS[15]

AA51

VSS[16]

AA52

VSS[17]

AA53

VSS[18]

AA55

VSS[19]

AA56

VSS[20]

AA8

VSS[21]

AB16

VSS[22]

AB18

VSS[23]

AB21

VSS[24]

AB48

VSS[25]

AB61

VSS[26]

AC10

VSS[27]

AC14

VSS[28]

AC46

VSS[29]

AC6

VSS[30]

AD17

VSS[31]

AD20

VSS[32]

AD4

VSS[33]

AD61

VSS[34]

AE13

VSS[35]

AE8

VSS[36]

AF1

VSS[37]

AF17

VSS[38]

AF21

VSS[39]

AF47

VSS[40]

AF48

VSS[41]

AF50

VSS[42]

AF51

VSS[43]

AF52

VSS[44]

AF53

VSS[45]

AF55

VSS[46]

AF56

VSS[47]

AF58

VSS[48]

AF59

VSS[49]

AG10

VSS[50]

AG14

VSS[51]

AG18

VSS[52]

AG47

VSS[53]

AG52

VSS[54]

AG61

VSS[55]

AG7

VSS[56]

AH4

VSS[57]

AH58

VSS[58]

AJ13

VSS[59]

AJ16

VSS[60]

AJ20

VSS[61]

AJ22

VSS[62]

AJ26

VSS[63]

AJ30

VSS[64]

AJ34

VSS[65]

AJ38

VSS[66]

AJ42

VSS[67]

AJ45

VSS[68]

AJ48

VSS[69]

AJ7

VSS[70]

AK1

VSS[71]

AK52

VSS[72]

AL10

VSS[73]

AL13

VSS[74]

AL17

VSS[75]

AL21

VSS[76]

AL25

VSS[77]

AL28

VSS[78]

AL33

VSS[79]

AL36

VSS[80]

AL40

VSS[81]

AL43

VSS[82]

AL47

VSS[83]

AL61

VSS[84]

AM13

VSS[85]

AM20

VSS[86]

AM22

VSS[87]

AM26

VSS[88]

AM30

VSS[89]

AM34

VSS[90]

IVY-BRIDGE_BGA1023

CPU1@

Title

Size Document Number Rev

Custom

LA-8671P_SDV

Date: Sheet of

+VREF0

DRAMRST_CNTRL_PCH [13,6]

VSS

Compal Electronics, Inc.

PROCESSOR(6/6) PWR,VSS

1

VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]

VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180]

AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13

9 50Thursday, October 04, 2012

1.0

5

4

3

2

1

DDR_A_ MA[0..15][11 ,6]

DDR_A_ DQS#[0..7 ][11,6]

DDR_A_ DQS[0..7][11,6]

DDR_A_ D[0..63][11,6]

D D

C C

DDR_A_ MA[0..15]

DDR_A_ DQS#[0..7 ]

DDR_A_ DQS[0..7]

DDR_A_ D[0..63]

+VREF0 +VRE F1

1

C5239

C5241

2

0.1U_0402_16V4Z

DDR_A_ BS0[11,6] DDR_A_ BS1[11,6] DDR_A_ BS2[11,6]

M_CLK_D DR0[6]

M_CLK_D DR#0[6 ]

DDR_CK E0_DIMMA[6]

DDR_CS 0_DIMMA#[6]

DDR_A_ RAS#[11,6] DDR_A_ CAS#[11,6]

DDR_A_ WE#[11,6 ]

DDR3_D RAMRST#[11 ,6]

+VREF0 +VREF 1

U5006

DQL0

VREFCA

DQL1

VREFDQ

DQL2 DQL3

A0

DQL4

A1 A2

DQL5

A3

DQL6

A4

DQL7 A5 A6 A7

DQU0

A8

DQU1

A9

DQU2

A10/AP

DQU3

A11

DQU4

A12/BC

DQU5 DQU6

A13

DQU7

A14

BA0

VDD

BA1

VDD VDD

BA2

VDD VDD VDD

CK

VDD

CK

VDD

CKE

VDD

VDDQ

ODT CS

VDDQ

RAS

VDDQ

CAS

VDDQ

WE

VDDQ VDDQ VDDQ

DQSL

VDDQ

DQSU

VDDQ

VSS

DML

VSS

DMU

VSS VSS

DQSL

VSS

DQSU

VSS VSS VSS VSS

RESET

VSS VSS

ZQ

VSS

NC

VSSQ

NC

VSSQ VSSQ

NC

VSSQ

NC

VSSQ VSSQ

NC

VSSQ VSSQ VSSQ

96-BALL

96-BALL SDRAM DD R3L

SDRAM DD R3L

H5TC4G6 3MFR-PBA _FBGA 96

DDR1@

E4

DDR_A_ D6

F8

DDR_A_ D1

F3

DDR_A_ D2

F9

DDR_A_ D5

H4

DDR_A_ D3

H9

DDR_A_ D4

G3

DDR_A_ D7

H8

DDR_A_ D0

D8

DDR_A_ D12

C4

DDR_A_ D15

C9

DDR_A_ D13

C3

DDR_A_ D10

A8

DDR_A_ D9

A3

DDR_A_ D11

B9

DDR_A_ D8

A4

DDR_A_ D14

B3

+1.5V +1.5V+1.5V

D10 G8 K3 K9 N2 N10 R2 R10

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

B2 B10 D2 D9 E3 E9 F10 G2 G10

1

C5242

C5243

2

0.1U_0402_16V4Z

DDR_A_ DQS2

DDR_A_ DQS#2 DDR_A_ DQS#3

M9 H2

N4

DDR_A_ MA0

P8

DDR_A_ MA1

1

2

0.1U_0402_16V4Z

M_ODT0[6]

DDR_A_ MA2 DDR_A_ MA3 DDR_A_ MA4 DDR_A_ MA5 DDR_A_ MA6 DDR_A_ MA7 DDR_A_ MA8 DDR_A_ MA9 DDR_A_ MA10 DDR_A_ MA11 DDR_A_ MA12 DDR_A_ MA13

DDR_A_ BS0 DDR_A_ BS1 DDR_A_ BS2

M_CLK_D DR0

M_CLK_D DR#0

DDR_CK E0_DIMMA

M_ODT0

DDR_CS 0_DIMMA#

DDR_A_ RAS# DDR_A_ CAS#

DDR_A_ WE#

DDR_A_ DQS0 DDR_A_ DQS1

DDR_A_ DQS#0 DDR_A_ DQS#1

DDR3_D RAMRST#

1 2

DDR_A_ MA15

P4

N3

P9

P3 R9 R3

T9 R4

L8 R8 N8

T4

T8

M3 N9 M4

J8

K8 K10

K2

L3

J4

K4

L4

F4 C8

E8 D4

G4

B8

T3

L9

R5197240_0402_1% R5 197240_04 02_1%

J2

L2 J10 L10

M8

DDR_A_ MA0 DDR_A_ MA1 DDR_A_ MA2 DDR_A_ MA3 DDR_A_ MA4 DDR_A_ MA5 DDR_A_ MA6 DDR_A_ MA7 DDR_A_ MA8 DDR_A_ MA9 DDR_A_ MA10 DDR_A_ MA11 DDR_A_ MA12 DDR_A_ MA13 DDR_A_ MA14

DDR_A_ BS0 DDR_A_ BS1 DDR_A_ BS2

M_CLK_D DR0 M_CLK_D DR#0 DDR_CK E0_DIMMA

M_ODT0 DDR_CS 0_DIMMA# DDR_A_ RAS# DDR_A_ CAS# DDR_A_ WE#

DDR3_D RAMRST#

1 2

240_04 02_1%

DDR_A_ MA15

M9 H2

N4

P8 P4

N3

P9

P3 R9 R3

T9 R4

L8 R8 N8

T4

T8

M3 N9 M4

J8

K8

K10

K2

L3

J4

K4

L4

F4 C8

E8 D4

G4

B8

T3

L9

R5196

J2

L2 J10 L10

M8

U5009

DQL0

VREFCA

DQL1

VREFDQ

DQL2 DQL3

A0

DQL4

A1 A2

DQL5

A3

DQL6

A4

DQL7 A5 A6 A7

DQU0

A8

DQU1

A9

DQU2

A10/AP

DQU3

A11

DQU4

A12/BC

DQU5 DQU6

A13

DQU7

A14

BA0

VDD

BA1

VDD VDD

BA2

VDD VDD VDD

CK

VDD

CK

VDD

CKE

VDD

VDDQ

ODT CS

VDDQ

RAS

VDDQ

CAS

VDDQ

WE

VDDQ VDDQ VDDQ

DQSL

VDDQ

DQSU

VDDQ

VSS

DML

VSS

DMU

VSS VSS

DQSL

VSS

DQSU

VSS VSS VSS VSS

RESET

VSS VSS

ZQ

VSS

NC

VSSQ

NC

VSSQ VSSQ

NC

VSSQ

NC

VSSQ VSSQ

NC

VSSQ VSSQ VSSQ

96-BALL

96-BALL SDRAM DD R3L

SDRAM DD R3L

H5TC4G6 3MFR-PBA _FBGA 96

DDR1@

E4

DDR_A_ D23

F8

DDR_A_ D16

F3

DDR_A_ D18

F9

DDR_A_ D17

H4

DDR_A_ D19

H9

DDR_A_ D20

G3

DDR_A_ D22

H8

DDR_A_ D21

D8

DDR_A_ D25

C4

DDR_A_ D31

C9

DDR_A_ D28

C3

DDR_A_ D26

A8

DDR_A_ D29

A3

DDR_A_ D27

B9

DDR_A_ D24

A4

DDR_A_ D30

B3

+1.5V

D10 G8 K3 K9 N2 N10 R2 R10

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

B2 B10 D2 D9 E3 E9 F10 G2 G10

+VREF0

+VREF1 +VREF0 +VREF 1

1

C5240

C5244

2

0.1U_0402_16V4Z

DDR_A_ DQS4 DDR_A_ DQS5

DDR_A_ DQS#4 DDR_A_ DQS#5

DDR3_D RAMRST#

U5008

DQL0

VREFCA

DQL1

VREFDQ

DQL2 DQL3

A0

DQL4

A1 A2

DQL5

A3

DQL6

A4

DQL7 A5 A6 A7

DQU0

A8

DQU1

A9

DQU2

A10/AP

DQU3

A11

DQU4

A12/BC

DQU5 DQU6

A13

DQU7

A14

BA0

VDD

BA1

VDD VDD

BA2

VDD VDD VDD

CK

VDD

CK

VDD

CKE

VDD

VDDQ

ODT CS

VDDQ

RAS

VDDQ

CAS

VDDQ

WE

VDDQ VDDQ VDDQ

DQSL

VDDQ

DQSU

VDDQ

VSS

DML

VSS

DMU

VSS VSS

DQSL

VSS

DQSU

VSS VSS VSS VSS

RESET

VSS VSS

ZQ

VSS

NC

VSSQ

NC

VSSQ VSSQ

NC

VSSQ

NC

VSSQ VSSQ

NC

VSSQ VSSQ VSSQ

96-BALL

96-BALL SDRAM DD R3L

SDRAM DD R3L

H5TC4G6 3MFR-PBA _FBGA 96

DDR1@

E4

DDR_A_ D38

F8

DDR_A_ D32

F3

DDR_A_ D34

F9

DDR_A_ D37

H4

DDR_A_ D35

H9

DDR_A_ D36

G3

DDR_A_ D39

H8

DDR_A_ D33

D8

DDR_A_ D41

C4

DDR_A_ D43

C9

DDR_A_ D40

C3

DDR_A_ D47

A8

DDR_A_ D45

A3

DDR_A_ D46

B9

DDR_A_ D44

A4

DDR_A_ D42

B3 D10 G8 K3 K9 N2 N10 R2 R10

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

B2 B10 D2 D9 E3 E9 F10 G2 G10

M9 H2

N4

DDR_A_ MA0

P8

DDR_A_ MA1

P4

DDR_A_ MA2

N3

DDR_A_ MA3

P9

DDR_A_ MA4

P3

DDR_A_ MA5

R9

DDR_A_ MA6

R3

DDR_A_ MA7

T9

DDR_A_ MA8

R4

DDR_A_ MA9

L8

DDR_A_ MA10

R8

DDR_A_ MA11

N8

DDR_A_ MA12

T4

DDR_A_ MA13

T8

DDR_A_ MA14

M3

DDR_A_ BS0

N9

DDR_A_ BS1

M4

DDR_A_ BS2

J8

M_CLK_D DR0

K8

M_CLK_D DR#0

K10

DDR_CK E0_DIMMA

K2

M_ODT0

L3

DDR_CS 0_DIMMA#

J4

DDR_A_ RAS#

K4

DDR_A_ CAS#

L4

DDR_A_ WE#

F4

C8

E8

D4

G4

B8

T3

1 2

L9

R5198

240_04 02_1%

J2

L2 J10 L10

M8

DDR_A_ MA15 DDR_A_ MA15

U5007

M9

H2

N4

DDR_A_ MA0

P8

DDR_A_ MA1

1

C5246

C5245

2

0.1U_0402_16V4Z

DDR_A_ MA2 DDR_A_ MA3 DDR_A_ MA4 DDR_A_ MA5 DDR_A_ MA6 DDR_A_ MA7 DDR_A_ MA8 DDR_A_ MA9 DDR_A_ MA10 DDR_A_ MA11 DDR_A_ MA12 DDR_A_ MA13 DDR_A_ MA14DDR_A_ MA14

DDR_A_ BS0 DDR_A_ BS1 DDR_A_ BS2

M_CLK_D DR0 M_CLK_D DR#0 DDR_CK E0_DIMMA

M_ODT0 DDR_CS 0_DIMMA# DDR_A_ RAS# DDR_A_ CAS# DDR_A_ WE#

DDR_A_ DQS6DDR_A_ DQS3 DDR_A_ DQS7

DDR_A_ DQS#6 DDR_A_ DQS#7

DDR3_D RAMRST#

1 2

240_04 02_1%

P4 N3 P9 P3 R9 R3 T9 R4 L8 R8 N8 T4 T8

M3 N9

M4

J8 K8

K10

K2 L3

J4

K4

L4

F4 C8

E8 D4

G4

B8

T3

L9

R5199

J2

L2 J10 L10

M8

H5TC4G6 3MFR-PBA _FBGA 96

DDR1@

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14

BA0 BA1 BA2

CK CK CKE

ODT CS RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET

ZQ

NC NC NC NC

NC

96-BALL

96-BALL SDRAM DD R3L

SDRAM DD R3L

E4

DDR_A_ D51

DQL0

F8

DDR_A_ D49

DQL1

F3

DDR_A_ D50

DQL2

F9

DDR_A_ D53

DQL3

H4

DDR_A_ D55

DQL4

H9

DDR_A_ D48

DQL5

G3

DDR_A_ D54

DQL6

H8

DDR_A_ D52

DQL7

D8

DDR_A_ D56

DQU0

C4

DDR_A_ D63

DQU1

C9

DDR_A_ D60

DQU2

C3

DDR_A_ D58

DQU3

A8

DDR_A_ D61

DQU4

A3

DDR_A_ D59

DQU5

B9

DDR_A_ D57

DQU6

A4

DDR_A_ D62

DQU7

B3

VDD

D10

VDD

G8

VDD

K3

VDD

K9

VDD

N2

VDD

N10

VDD

R2

VDD

R10

VDD

A2

VDDQ

A9

VDDQ

C2

VDDQ

C10

VDDQ

D3

VDDQ

E10

VDDQ

F2

VDDQ

H3

VDDQ

H10

VDDQ

A10

VSS

B4

VSS

E2

VSS

G9

VSS

J3

VSS

J9

VSS

M2

VSS

M10

VSS

P2

VSS

P10

VSS

T2

VSS

T10

VSS

B2

VSSQ

B10

VSSQ

D2

VSSQ

D9

VSSQ

E3

VSSQ

E9

VSSQ

F10

VSSQ

G2

VSSQ

G10

VSSQ

B B

SA00001LV10

+3VS

@

C5247

@

U5010

1

A0

2

A1

3

1K_0402_5%~D

12

A2

4

R5201

1

2

@

10U_0603_6.3V6M

5

C5255

1

2

VSS

CAT24C 02WI-G T3A_S O8

10U_0603_6.3V6M

C5258

1

2

R5200

@

+1.5V

10U_0603_6.3V6M

C5254

C5253

1

2

A A

1 2

8

0.1U_040 2_16V4 Z~D

VCC

7

WP

6

SMB_CLK _S3 SMB_DAT A_S3

0.1U_0402_16V7K

0.1U_0402_16V7K C5260

C5260

0.1U_0402_16V7K

0.1U_0402_16V7K C5261

C5261

1

2

SMB_CLK _S3 [13,21,32,35] SMB_DAT A_S3 [13,21,32,35]

0.1U_0402_16V7K

0.1U_0402_16V7K C5263

C5263

C5262

1

2

1

@

+

C5257

C5257 220U_D2 _2VY_R1 5M

220U_D2 _2VY_R1 5M

SGA00004L00

2

M_ODT1[11,6]

DDR_CS 1_DIMMA#[11,6]

DDR_CK E1_DIMMA[11,6]

4

M_ODT1 M_ODT0 DDR_A_ RAS# DDR_CK E0_DIMMA

DDR_CS 0_DIMMA# DDR_A_ WE# DDR_CS 1_DIMMA# DDR_A_ CAS#

DDR_A_ MA12 DDR_A_ BS0 DDR_A_ MA10 DDR_CK E1_DIMMA

DDR_A_ MA11 DDR_A_ MA13 DDR_A_ MA9 DDR_A_ MA14

DDR_A_ MA3 DDR_A_ MA1 DDR_A_ BS2 DDR_A_ MA15

DDR_A_ MA7 DDR_A_ MA4 DDR_A_ MA8 DDR_A_ MA6

DDR_A_ MA0 DDR_A_ BS1 DDR_A_ MA5 DDR_A_ MA2

1 2

R5214 36_0 402_5%R5214 36_0 402_5%

1 2

R5215 36_0 402_5%R5215 36_0 402_5%

1 2

R5216 36_0 402_5%R5216 36_0 402_5%

1 2

R5217 36_0 402_5%R5217 36_0 402_5%

1 2

R5218 36_0 402_5%R5218 36_0 402_5%

1 2

R5219 36_0 402_5%R5219 36_0 402_5%

1 2

R5220 36_0 402_5%R5220 36_0 402_5%

1 2

R5221 36_0 402_5%R5221 36_0 402_5%

1 2

R5222 36_0 402_5%R5222 36_0 402_5%

1 2

R5227 36_0 402_5%R5227 36_0 402_5%

1 2

R5228 36_0 402_5%R5228 36_0 402_5%

1 2

R5231 36_0 402_5%R5231 36_0 402_5%

1 2

R5232 36_0 402_5%R5232 36_0 402_5%

1 2

R5233 36_0 402_5%R5233 36_0 402_5%

1 2

R5234 36_0 402_5%R5234 36_0 402_5%

1 2

R5235 36_0 402_5%R5235 36_0 402_5%

1 2

R5236 36_0 402_5%R5236 36_0 402_5%

1 2

R5237 36_0 402_5%R5237 36_0 402_5%

1 2

R5238 36_0 402_5%R5238 36_0 402_5%

1 2

R5239 36_0 402_5%R5239 36_0 402_5%

1 2

R5240 36_0 402_5%R5240 36_0 402_5%

1 2

R5242 36_0 402_5%R5242 36_0 402_5%

1 2

R5243 36_0 402_5%R5243 36_0 402_5%

1 2

R5244 36_0 402_5%R5244 36_0 402_5%

1 2

R5245 36_0 402_5%R5245 36_0 402_5%

1 2

R5246 36_0 402_5%R5246 36_0 402_5%

1 2

R5247 36_0 402_5%R5247 36_0 402_5%

1 2

R5248 36_0 402_5%R5248 36_0 402_5%

SCL

5

SDA

10U_0603_6.3V6M

C5259

C5256

1

2

+0.75VS

C5251

1U_0402_6.3V6K

C5251

1U_0402_6.3V6K

C5250

1U_0402_6.3V6K

C5250

1U_0402_6.3V6K

C5248

1U_0402_6.3V6K

C5248

1U_0402_6.3V6K

C5249

1U_0402_6.3V6K

C5249

1U_0402_6.3V6K

1

2

M_CLK_D DR0

1

C5252

C5252 2P_040 2_50V8 C

2P_040 2_50V8 C

2

M_CLK_D DR#0

3

30.1_04 02_1%

12

R5209

R5210

30.1_04 02_1%

1

C5275

0.1U_040 2_16V4 Z

2

M_CLK_D DR#1[1 1,6]

M_CLK_D DR1

M_CLK_D DR1[11,6]

1

C5288

C5288 2P_040 2_50V8 C

2P_040 2_50V8 C

2

M_CLK_D DR#1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

12

R5230

R5229

30.1_04 02_1%

1

C5311

0.1U_040 2_16V4 Z

2

2011/05/16 2013/05/16

1K_040 2_1%

Compal Secret Data

Deciphered Date

+1.5V +1.5V

12

R5207

R5207 1K_040 2_1%

1K_040 2_1%

+VREF0 +VREF1

2.2U_0603_6.3V6K

C5271

0.1U_0402_16V4Z

C5271

0.1U_0402_16V4Z

C5272

12

R5212

1

1K_040 2_1%

2

12

R5208

R5208 1K_040 2_1%

1K_040 2_1%

+VREF1+VREF0

2.2U_0603_6.3V6K

C5273

0.1U_0402_16V4Z

C5273

0.1U_0402_16V4Z

C5274

12

R5213

1

2

Compal Electronics, Inc.

Title

DDRIII A Chip 2Gbit X16-I

Size Document Number Rev

D

LA-8671P_SDV

Date: Sheet of

1

10 50Thursday, Octob er 04, 20 12

AMY WEN

1.0

5

4

3

2

1

DDR_A_ MA[0..15][10 ,6]

DDR_A_ DQS#[0..7 ][10,6]

DDR_A_ DQS[0..7][10,6]

DDR_A_ D[0..63][10,6]

D D

C C

DDR_A_ MA[0..15]

DDR_A_ DQS#[0..7 ]

DDR_A_ DQS[0..7]

DDR_A_ D[0..63]

+VREF0 +VRE F1

1

C5280

C5276

2

0.1U_0402_16V4Z

DDR_A_ BS0[10,6] DDR_A_ BS1[10,6] DDR_A_ BS2[10,6]

M_CLK_D DR1[10,6]

M_CLK_D DR#1[10,6]

DDR_CK E1_DIMMA[10,6]

DDR_CS 1_DIMMA#[10,6]

DDR_A_ RAS#[10,6] DDR_A_ CAS#[10,6]

DDR_A_ WE#[10,6 ]

DDR3_D RAMRST#[10 ,6]

+VREF0 +VREF 1

UD1

DQL0

VREFCA

DQL1

VREFDQ

DQL2 DQL3

A0

DQL4

A1 A2

DQL5

A3

DQL6

A4

DQL7 A5 A6 A7

DQU0

A8

DQU1

A9

DQU2

A10/AP

DQU3

A11

DQU4

A12/BC

DQU5 DQU6

A13

DQU7

A14

BA0

VDD

BA1

VDD VDD

BA2

VDD VDD VDD

CK

VDD

CK

VDD

CKE

VDD

VDDQ

ODT CS

VDDQ

RAS

VDDQ

CAS

VDDQ

WE

VDDQ VDDQ VDDQ

DQSL

VDDQ

DQSU

VDDQ

VSS

DML

VSS

DMU

VSS VSS

DQSL

VSS

DQSU

VSS VSS VSS VSS

RESET

VSS VSS

ZQ

VSS

NC

VSSQ

NC

VSSQ VSSQ

NC

VSSQ

NC

VSSQ VSSQ

NC

VSSQ VSSQ VSSQ

96-BALL

96-BALL SDRAM DD R3L

SDRAM DD R3L

H5TC4G6 3MFR-PBA _FBGA 96

DDR1@

E4

DDR_A_ D1

F8

DDR_A_ D6

F3

DDR_A_ D5

F9

DDR_A_ D2

H4

DDR_A_ D0

H9

DDR_A_ D7

G3

DDR_A_ D4

H8

DDR_A_ D3

D8

DDR_A_ D15

C4

DDR_A_ D12

C9

DDR_A_ D10

C3

DDR_A_ D13

A8

DDR_A_ D14

A3

DDR_A_ D8

B9

DDR_A_ D11

A4

DDR_A_ D9

B3

+1.5V +1.5V+1.5V

D10 G8 K3 K9 N2 N10 R2 R10

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

B2 B10 D2 D9 E3 E9 F10 G2 G10

1

C5277

C5281

2

0.1U_0402_16V4Z

DDR_A_ DQS2

DDR_A_ DQS#2 DDR_A_ DQS#3

M9 H2

N4

DDR_A_ MA0

P8

DDR_A_ MA1

1

2

0.1U_0402_16V4Z

M_ODT1[10,6]

DDR_A_ MA2 DDR_A_ MA3 DDR_A_ MA4 DDR_A_ MA5 DDR_A_ MA6 DDR_A_ MA7 DDR_A_ MA8 DDR_A_ MA9 DDR_A_ MA10 DDR_A_ MA11 DDR_A_ MA12 DDR_A_ MA13

DDR_A_ BS0 DDR_A_ BS1 DDR_A_ BS2

M_CLK_D DR1

M_CLK_D DR#1

DDR_CK E1_DIMMA

M_ODT1

DDR_CS 1_DIMMA#

DDR_A_ RAS# DDR_A_ CAS#

DDR_A_ WE#

DDR_A_ DQS0 DDR_A_ DQS1

DDR_A_ DQS#0 DDR_A_ DQS#1

DDR3_D RAMRST#

1 2

DDR_A_ MA15

P4

N3

P9

P3 R9 R3

T9 R4

L8 R8 N8

T4

T8

M3 N9 M4

J8

K8 K10

K2

L3

J4

K4

L4

F4 C8

E8 D4

G4

B8

T3

L9

R5224240_0 402_1 % R5224240_04 02_1%

J2

L2 J10 L10

M8

DDR_A_ MA0 DDR_A_ MA1 DDR_A_ MA2 DDR_A_ MA3 DDR_A_ MA4 DDR_A_ MA5 DDR_A_ MA6 DDR_A_ MA7 DDR_A_ MA8 DDR_A_ MA9 DDR_A_ MA10 DDR_A_ MA11 DDR_A_ MA12 DDR_A_ MA13 DDR_A_ MA14

DDR_A_ BS0 DDR_A_ BS1 DDR_A_ BS2

M_CLK_D DR1 M_CLK_D DR#1 DDR_CK E1_DIMMA

M_ODT1 DDR_CS 1_DIMMA# DDR_A_ RAS# DDR_A_ CAS# DDR_A_ WE#

DDR3_D RAMRST#

1 2

240_04 02_1%

DDR_A_ MA15

M9 H2

N4

P8 P4

N3

P9

P3 R9 R3

T9 R4

L8 R8 N8

T4

T8

M3 N9 M4

J8

K8

K10

K2

L3

J4

K4

L4

F4 C8

E8 D4

G4

B8

T3

L9

R5223

J2

L2 J10 L10

M8

UD2

DQL0

VREFCA

DQL1

VREFDQ

DQL2 DQL3

A0

DQL4

A1 A2

DQL5

A3

DQL6

A4

DQL7 A5 A6 A7

DQU0

A8

DQU1

A9

DQU2

A10/AP

DQU3

A11

DQU4

A12/BC

DQU5 DQU6

A13

DQU7

A14

BA0

VDD

BA1

VDD VDD

BA2

VDD VDD VDD

CK

VDD

CK

VDD

CKE

VDD

VDDQ

ODT CS

VDDQ

RAS

VDDQ

CAS

VDDQ

WE

VDDQ VDDQ VDDQ

DQSL

VDDQ

DQSU

VDDQ

VSS

DML

VSS

DMU

VSS VSS

DQSL

VSS

DQSU

VSS VSS VSS VSS

RESET

VSS VSS

ZQ

VSS

NC

VSSQ

NC

VSSQ VSSQ

NC

VSSQ

NC

VSSQ VSSQ

NC

VSSQ VSSQ VSSQ

96-BALL

96-BALL SDRAM DD R3L

SDRAM DD R3L

H5TC4G6 3MFR-PBA _FBGA 96

DDR1@

E4

DDR_A_ D16

F8

DDR_A_ D23

F3

DDR_A_ D17

F9

DDR_A_ D18

H4

DDR_A_ D21

H9

DDR_A_ D22

G3

DDR_A_ D20

H8

DDR_A_ D19

D8

DDR_A_ D31

C4

DDR_A_ D25

C9

DDR_A_ D26

C3

DDR_A_ D28

A8

DDR_A_ D30

A3

DDR_A_ D24

B9

DDR_A_ D27

A4

DDR_A_ D29

B3

+1.5V

D10 G8 K3 K9 N2 N10 R2 R10

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

B2 B10 D2 D9 E3 E9 F10 G2 G10

+VREF0 +VREF 1 +VREF0 +VREF1

1

C5279

C5278

2

0.1U_0402_16V4Z

DDR_A_ DQS4 DDR_A_ DQS5

DDR_A_ DQS#4 DDR_A_ DQS#5

DDR3_D RAMRST#

UD3

DQL0

VREFCA

DQL1

VREFDQ

DQL2 DQL3

A0

DQL4

A1 A2

DQL5

A3

DQL6

A4

DQL7 A5 A6 A7

DQU0

A8

DQU1

A9

DQU2

A10/AP

DQU3

A11

DQU4

A12/BC

DQU5 DQU6

A13

DQU7

A14

BA0

VDD

BA1

VDD VDD

BA2

VDD VDD VDD

CK

VDD

CK

VDD

CKE

VDD

VDDQ

ODT CS

VDDQ

RAS

VDDQ

CAS

VDDQ

WE

VDDQ VDDQ VDDQ

DQSL

VDDQ

DQSU

VDDQ

VSS

DML

VSS

DMU

VSS VSS

DQSL

VSS

DQSU

VSS VSS VSS VSS

RESET

VSS VSS

ZQ

VSS

NC

VSSQ

NC

VSSQ VSSQ

NC

VSSQ

NC

VSSQ VSSQ

NC

VSSQ VSSQ VSSQ

96-BALL

96-BALL SDRAM DD R3L

SDRAM DD R3L

H5TC4G6 3MFR-PBA _FBGA 96

DDR1@

E4

DDR_A_ D32

F8

DDR_A_ D38

F3

DDR_A_ D37

F9

DDR_A_ D34

H4

DDR_A_ D33

H9

DDR_A_ D39

G3

DDR_A_ D36

H8

DDR_A_ D35 DDR_A_ D55

D8

DDR_A_ D43

C4

DDR_A_ D41

C9

DDR_A_ D47

C3

DDR_A_ D40

A8

DDR_A_ D42

A3

DDR_A_ D44

B9

DDR_A_ D46

A4

DDR_A_ D45

B3 D10 G8 K3 K9 N2 N10 R2 R10

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

B2 B10 D2 D9 E3 E9 F10 G2 G10

1

C5282

C5283

2

0.1U_0402_16V4Z

M9 H2

N4

DDR_A_ MA0

P8

DDR_A_ MA1

P4

DDR_A_ MA2

N3

DDR_A_ MA3

P9

DDR_A_ MA4

P3

DDR_A_ MA5

R9

DDR_A_ MA6

R3

DDR_A_ MA7

T9

DDR_A_ MA8

R4

DDR_A_ MA9

L8

DDR_A_ MA10

R8

DDR_A_ MA11

N8

DDR_A_ MA12

T4

DDR_A_ MA13

T8

DDR_A_ MA14

M3

DDR_A_ BS0

N9

DDR_A_ BS1

M4

DDR_A_ BS2

J8

M_CLK_D DR1

K8

M_CLK_D DR#1

K10

DDR_CK E1_DIMMA

K2

M_ODT1

L3

DDR_CS 1_DIMMA#

J4

DDR_A_ RAS#

K4

DDR_A_ CAS#

L4

DDR_A_ WE#

F4

C8

E8

D4

G4

B8

T3

L9

1 2

R5225

240_04 02_1%

J2

L2 J10 L10

M8

DDR_A_ MA15 DDR_A_ MA15

UD4

M9

H2

N4

DDR_A_ MA0

P8

DDR_A_ MA1

1

2

0.1U_0402_16V4Z

DDR_A_ MA2 DDR_A_ MA3 DDR_A_ MA4 DDR_A_ MA5 DDR_A_ MA6 DDR_A_ MA7 DDR_A_ MA8 DDR_A_ MA9 DDR_A_ MA10 DDR_A_ MA11 DDR_A_ MA12 DDR_A_ MA13 DDR_A_ MA14DDR_A_ MA14

DDR_A_ BS0 DDR_A_ BS1 DDR_A_ BS2

M_CLK_D DR1 M_CLK_D DR#1 DDR_CK E1_DIMMA

M_ODT1 DDR_CS 1_DIMMA# DDR_A_ RAS# DDR_A_ CAS# DDR_A_ WE#

DDR_A_ DQS6DDR_A_ DQS3 DDR_A_ DQS7

DDR_A_ DQS#6 DDR_A_ DQS#7

DDR3_D RAMRST#

1 2

240_04 02_1%

P4 N3 P9 P3 R9 R3 T9 R4 L8 R8 N8 T4 T8

M3

N9

M4

J8 K8

K10

K2 L3 J4 K4 L4

F4 C8

E8 D4

G4

B8

T3

L9

R5226

J2

L2 J10 L10

M8

H5TC4G6 3MFR-PBA _FBGA 96

DDR1@

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14

BA0 BA1 BA2

CK CK CKE

ODT CS RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET

ZQ

NC NC NC NC

NC

96-BALL

96-BALL SDRAM DD R3L

SDRAM DD R3L

E4

DDR_A_ D49

DQL0

F8

DDR_A_ D51

DQL1

F3

DDR_A_ D53

DQL2

F9

DDR_A_ D50

DQL3

H4

DDR_A_ D52

DQL4

H9

DDR_A_ D54

DQL5

G3

DDR_A_ D48

DQL6

H8

DQL7

D8

DDR_A_ D63

DQU0

C4

DDR_A_ D56

DQU1

C9

DDR_A_ D58

DQU2

C3

DDR_A_ D60

DQU3

A8

DDR_A_ D62

DQU4

A3

DDR_A_ D57

DQU5

B9

DDR_A_ D59

DQU6

A4

DDR_A_ D61

DQU7

B3

VDD

D10

VDD

G8

VDD

K3

VDD

K9

VDD

N2

VDD

N10

VDD

R2

VDD

R10

VDD

A2

VDDQ

A9

VDDQ

C2

VDDQ

C10

VDDQ

D3

VDDQ

E10

VDDQ

F2

VDDQ

H3

VDDQ

H10

VDDQ

A10

VSS

B4

VSS

E2

VSS

G9

VSS

J3

VSS

J9

VSS

M2

VSS

M10

VSS

P2

VSS

P10

VSS

T2

VSS

T10

VSS

B2

VSSQ

B10

VSSQ

D2

VSSQ

D9

VSSQ

E3

VSSQ

E9

VSSQ

F10

VSSQ

G2

VSSQ

G10

VSSQ

B B

CLIP2

CLIP1

1

P1

EMIST_S UL-12A2M

ME@

CLIP3

1

P1

EMIST_S UL-12A2M

ME@

A A

5

CLIP2

1

P1

EMIST_S UL-12A2M

ME@

CLIP4

1

P1

EMIST_S UL-12A2M

ME@

CLIP5

1

P1

EMIST_S UL-12A2M

ME@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Data

2011/05/16 2013/05/16

Deciphered Date

Compal Electronics, Inc.

Title

DDRIII A Chip 2Gbit X16-II

Size Document Number Rev

D

LA-8671P_SDV

Date: Sheet of

1

11 50Thursday, Octob er 04, 20 12

AMY WEN

1.0

5

W=20milsW=20mils

+RTCBATT+RTCVCC

R111

1K_0402_5%

1 2

12

C216

C216 1U_0603_10V4Z

1U_0603_10V4Z

D D

12

CLRP1

SHORT PADS

12/27

1 2

R109 10M_0402_5%R109 10M_0402_5%

32.768KHZ_12.5PF_CM31532768DZFT

1 2

Y1

C214

C214 18P_0402_50V8J

18P_0402_50V8J

Y1

1

C215

C215 18P_0402_50V8J

18P_0402_50V8J

2

1

2

CMOS

+RTCVCC

R112 1M_0402_5%R112 1M_0402_5%

1 2

R113 330K_0402_5%R113 330K_0402_5%

1 2

INTVRMEN(DCP_SUS)

H：Integrated VRM enable

*

L：Integrated VRM disable

(INTVRMEN should always be pull high.)

+3VS

1 2

R117 @ 1K_0402_5%R117 @ 1K_0402_5%

HIGH= Enable ( No Reboot ) LOW= Disable (Default)

*

C C

+3V_PCH

R118 @ 1K_0402_5%R118 @ 1K_0402_5%

Low = Disabled (Default)

*

High = Enabled [Flash Descriptor Security Overide]

+3V_PCH

R120 1K_0402_5%R120 1K_0402_5%

12

This signal has a weak internal pull-down

On Die PLL VR Select is supplied by

1.5V when smapled high

*

1.8V when sampled low Needs to be pulled High for Huron River platfrom

B B

HDA_BITCLK_AUDIO[28]

HDA_SYNC_AUDIO[28]

HDA_RST_AUDIO#[28]

HDA_SDOUT_AUDIO[28]

12

@

200_0402_5%

A A

12

@

100_0402_1%

R134

R138

12

@

12

@

R135

200_0402_5%

R139

R139 100_0402_1%

100_0402_1%

AMY WEN

R124

33_0402_5%

1 2

R126

33_0402_5%

1 2

R128

33_0402_5%

1 2

R131

33_0402_5%

1 2

5

SM_INTRUDER#

PCH_INTVRMEN

HDA_SPKR

HDA_SDOUT

HDA_SYNC

HDA_BIT_CLK

HDA_SYNC_R

HDA_RST#

HDA_SDOUT

+3V_PCH+3V_PCH+3V_PCH

12

R136

@

200_0402_5%

PCH_JTAG_TDIPCH_JTAG_TDO PCH_JTAG_TMS

12

R140

@

100_0402_1%

PCH_JTAG_TCK

12

R122

R122 51_0402_5%

51_0402_5%

PCH_WLBT_OFF_5#[32]

HDA_SYNC_R

12

R5017

R5017 1M_0402_5%

1M_0402_5%

1 2

C81 22P_0402_50V8J@C81 22P_0402_50V8J@

1 2

C83 22P_0402_50V8J@C83 22P_0402_50V8J@

Reserve for RF

EC_RSMRST#[14,34]

PBTN_OUT#[14,34,5]

+1.05VS

+3V_PCH

XDP_DBRESET#[14,5]

R290 0_0402_5%@R290 0_0402_5%@

EC_RSMRST# XDP_DBRESET#

PCH_JTAG_TDO

PCH_JTAG_TDI PCH_JTAG_TMS

PCH_JTAG_TCK

4

PCH_RTCX1

PCH_RTCX2

+3V_PCH

+RTCVCC

ME_FLASH[34]

+3VS

+5VS

G

2

S

HDA_BITCLK_AUDIO HDA_SDOUT_AUDIO

1 2

R85 1K_0402_1%@R85 1K_0402_1%@

R761 0_0402_5%

1 2

R84 1K_0402_1%@R84 1K_0402_1%@

4

12

C217

1U_0603_10V4Z

1 2

R114 20K_0402_5%R114 20K_0402_5%

1 2

R115 20K_0402_5%R115 20K_0402_5%

1U_0603_10V4Z

ME_FLASH

R121 10K_0402_5%

R5018 1K_0402_5%

Q9

Q9 BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

13

HDA_SYNC

D

@

+1.05VS_DB2

C218

@

1 2

@

12

HDA_SPKR[28]

HDA_SDIN0[28]

R119

1 2

0_0402_5%

12

CLRP2

SHORT PADS

CLRP2

SHORT PADS

12

CLRP3

SHORT PADS

CLRP3

SHORT PADS

12

JDB2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

G1

28

G2

ACES_88717-2601

ME@

3

UH1A

HDA_SDOUT

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

PANTHER-POINT_FCBGA989

PCH_RTCX1

PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BIT_CLK

HDA_SYNC

HDA_SPKR

HDA_RST#

HDA_SDIN0

PCH_WLBT_OFF_5#

PCH_GPIO13

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

SPI_CLK_PCH_R

SPI_SB_CS0#

SPI_SB_CS1#

SPI_SI

SPI_SO_R

SA00004NQ70

8M 1'S : SA000039A20 Winbond 8M 2'S : SA000046400 E-ON 8M 2'S : SA000039A10 WINBOND

4M 1'S : SA00003K800 Winbond 4M 2'S : SA00004LI00 E-ON

SPI_SB_CS0# SPI_SO_R SPI_SO_L

SPI_SB_CS1# SPI_SO_R

SPI ROM

1 2

R5168 0_0402_5%R5168 0_0402_5%

1 2

R5169 33_0402_5%R5169 33_0402_5%

SBA@

R5174 0_0402_5%

1 2 1 2

R5191 33_0402_5%

SBA@

3

2

C38

RTCIHDA

JTAG

SPI

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

LPC

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

SERIRQ

SATA0RXN SATA0RXP SATA0TXN

SATA0TXP

SATA1RXN SATA1RXP

SATA 6G

SATA1TXN

SATA1TXP

SATA2RXN SATA2RXP SATA2TXN

SATA2TXP

SATA3RXN SATA3RXP SATA3TXN

SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

SATA0GP / GPIO21

SATA1GP / GPIO19

LPC_AD0

A38

LPC_AD1

B37

LPC_AD2

C37

LPC_AD3

D36

LPC_FRAME#

E36 K36

V5

AM3 AM1 AP7

SATA_ITX_C_DRX_N0

AP5

SATA_ITX_C_DRX_P0

AM10 AM8 AP11 AP10

AD7 AD5 AH5

SATA_ITX_C_DRX_N2

AH4

SATA_ITX_C_DRX_P2

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11

Y10

AB12

AB13

AH1

RBIAS_SATA3

P3

PCH_SATALED#

V14

PCH_GPIO21

P1

ODD_DET#

SATA_COMP

SATA3_COMP

LPC_AD0 [34,36,37] LPC_AD1 [34,36,37] LPC_AD2 [34,36,37] LPC_AD3 [34,36,37]

LPC_FRAME# [34,36,37]

R116 10K_0402_5%R116 10K_0402_5%

SERIRQSERIRQ

R123

37.4_0402_1%

1 2

R125

49.9_0402_1%

1 2

R127

750_0402_1%

R130

R132

R133

12

SERIRQ [34,36]

12

10K_0402_5%

12

10K_0402_5%

12

10K_0402_5%

EC and Mini card debug port

+3VS

C2190.01U_0402_16V7K C2190.01U_0402_16V7K

12 12

C2200.01U_0402_16V7K C2200.01U_0402_16V7K

C2230.01U_0402_16V7K C2230.01U_0402_16V7K

12 12

C2240.01U_0402_16V7K C2240.01U_0402_16V7K

+1.05VS_VCC_SATA

+1.05VS_SATA3

+3VS

SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0

SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2 SATA_ITX_DRX_N2_CONN SATA_ITX_DRX_P2_CONN

For SBA SBA: 8M +4 M

R5175 0_0402_5%

0_0402_5%

R5176

R5176 33_0402_5%S BA@

33_0402_5%S BA@

2012/08/25

+3VS +3VM+3VSPI

SPI_CLK_PCH_R SPI_SI

RF Request

SPI_CLK_PCH_R SPI_SI

RF Request

NOSBA@

1 2

R5182 0_0402_5%

R5183 0_0402_5%

1 2

SBA@

C225 0.1U_0402_16V4ZC225 0.1U_0402_16V4Z

8M

U5

CS1# SPI_SO1 SPI_WP#1

1

CS#

2

SO

3

WP#

4

GND

W25Q64FVSSIG_SO8

U2202

1

CS#

2

SO

3

WP#

4

GND

W25Q32BVSSIG_SO8

SBA@

2010/08/25

CS0#

SPI_WP#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4M

VCC

HOLD#

SCLK

VCC

HOLD#

SCLK

8 7 6 5

SI

8 7 6 5

SI

1 2

SPI_HOLD#

1 2

SPI_CLK_PCH

1 2

SPI_SI_R

2

C85

C85 22P_0402_50V8J

22P_0402_50V8J

1

@

+3VSPI

SPI_HOLD#1 SPI_CLK1 SPI_SI1

Compal Secret Data

1 2 1 2

2

C86

C86 22P_0402_50V8J

22P_0402_50V8J

1

@

Deciphered Date

R5170 0_0402_5%R5170 0_0402_5%

R5172 33_0402_5%R5172 33_0402_5%

SBA@ R5175

SBA@

2

SATA_DTX_C_IRX_N0 [36]

SATA_ITX_DRX_N0 SATA_ITX_DRX_P0

SATA_DTX_C_IRX_P0 [36] SATA_ITX_DRX_N0 [36] SATA_ITX_DRX_P0 [36]

SATA_DTX_C_IRX_N2 [32] SATA_DTX_C_IRX_P2 [32] SATA_ITX_DRX_N2_CONN [32]

SATA_ITX_DRX_P2_CONN [32]

Boot BIOS Strap bit1 BBS1

GPIO19

Bit10

Boot BIOS Destination

GPIO51

Bit11

0 1

0

1

*

0

NOSBA: 8M

SPI_WP#1

SPI_HOLD#1

SPI_WP#

SPI_HOLD#

SPI_CLK_PCH_R

Title

PCH (1/8) SATA,HDA,SPI, LPC, XDP

Size Document Number Rev

Custom

LA-8671P_SDV

Date: Sheet of

R104 3.3K_0402_5%

R106 3.3K_0402_5%SBA@R106 3.3K_0402_5%SBA@

R5171 3.3K_0402_5%R5171 3.3K_0402_5%

R5173 3.3K_0402_5%R5173 3.3K_0402_5%

Reserve for EMI please close t o UH1

Compal Electronics, Inc.

Thursday, October 04, 2012

1

Reserved

SPI

(Default)

LPC

Check BOM

SBA@

1 2

2

1

R143

R143 33_0402_5%

33_0402_5%

@

C80

C80 22P_0402_50V8J

22P_0402_50V8J

@

HDD

mSATA

12

+3VSPI

1.0

50

5

PCIE_PRX_DTX_N1[22]

Card reader

WLAN

D D

LAN

Card reader

C C

WLAN

LAN

B B

PCIE_PRX_DTX_P1[22] PCIE_PTX_C_DRX_N1[22] PCIE_PTX_C_DRX_P1[22]

PCIE_PRX_DTX_N2[32]

PCIE_PRX_DTX_P2[32] PCIE_PTX_C_DRX_N2[32] PCIE_PTX_C_DRX_P2[32]

PCIE_PRX_DTX_N4[30]

PCIE_PRX_DTX_P4[30] PCIE_PTX_C_DRX_N4[30] PCIE_PTX_C_DRX_P4[30]

CLK_PCIE_CR#[22] CLK_PCIE_CR[22]

CARD_CLKREQ1#[22]

CLK_PCIE_WLAN1#[32] CLK_PCIE_WLAN1[32]

WLAN_CLKREQ#[32]

CLK_PCIE_LAN#[30] CLK_PCIE_LAN[30]

CLKREQ_LAN#[30]

+3V_PCH

+3VS

+3V_PCH

R193 10K_0402_5%R193 10K_0402_5%

+3V_PCH

1 2

C230 0 .1U_0402_10V7KC230 0 .1U_0402_10V7K

1 2

C234 0 .1U_0402_10V7KC234 0 .1U_0402_10V7K

1 2

C233 0 .1U_0402_10V7KC233 0 .1U_0402_10V7K

1 2

C229 0 .1U_0402_10V7KC229 0 .1U_0402_10V7K

1 2

C231 0 .1U_0402_10V7KC231 0 .1U_0402_10V7K

1 2

C232 0 .1U_0402_10V7KC232 0 .1U_0402_10V7K

1 2

R217 0_0402_5%

short@

1 2

R265 0_0402_5%

short@

1 2

short@

1 2

short@

1 2

short@

1 2

short@

1 2

short@

1 2

short@

1 2

short@

12

CLK_XDP_CLK#[5] CLK_XDP_CLK[5]

12

R160 10K_0402_5%R160 10K_0402_5%

R381 0_0402_5%

R208 0_0402_5%

R208 0_0402_5% R212 0_0402_5%

R212 0_0402_5%

R215 0_0402_5%

R215 0_0402_5% R167 10K_0402_5%R167 10K_0402_5%

R169 10K_0402_5%R169 10K_0402_5%

R369 0_0402_5%

R369 0_0402_5% R370 0_0402_5%

R370 0_0402_5%

R176 10K_0402_5%R176 10K_0402_5%

R371 0_0402_5%

R184 10K_0402_5%R184 10K_0402_5%

R186 10K_0402_5%R186 10K_0402_5%

R188 10K_0402_5%R188 10K_0402_5%

R190 10K_0402_5%R190 10K_0402_5%

4

PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1

PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2

PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4

CLK_PCIE_CR#_R CLK_PCIE_CR_R

CARD_CLKREQ#_R

CLK_PCIE_WLAN1_R

WLAN_CLKREQ1#

PCH_GPIO20

CLK_PCIE_LAN#_R CLK_PCIE_LAN_R

LAN_CLKREQ#

PCH_GPIO26

PCH_GPIO44

PCH_GPIO56

PCH_GPIO45

ON_ODD_DET

CLK_XDP_CLK# CLK_XDP_CLK

UH1B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

PANTHER-POINT_FCBGA989

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

CLOCKS

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N

CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N

CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N

CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

3

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

XTAL25_IN

E12

SMB_ALERT#

H14

PCH_SMBCLK

C9

PCH_SMBDATA

A12

DRAMRST_CNTRL_PCH

C8

PCH_SML0CLK

G12

PCH_SML0DATA

C13

PCH_HOT#

E14

PCH_SML1CLK

M16

PCH_SML1DATA

M7

T11

P10

M10

PEG_CLKREQ#_R

AB37 AB38

AV22

CLK_CPU_DMI#CLK_PCIE_WLAN1#_R

AU22

CLK_CPU_DMI

AM12 AM13

BF18

CLK_BUF_CPU_DMI#

BE18

CLK_BUF_CPU_DMI

BJ30

CLKIN_DMI2#

BG30

CLKIN_DMI2

G24

CLK_BUF_DREF_96M#

E24

CLK_BUF_DREF_96M

AK7

CLK_BUF_PCIE_SATA#

AK5

CLK_BUF_PCIE_SATA

K45

CLK_BUF_ICH_14M

H45

CLK_PCI_LPBACK

V47

XTAL25_IN

V49

XTAL25_OUT

Y47

XCLK_RCOMP

K43

F47

H47

K49

DGPU_PRSNT#

10K_0402_5%

12

R148

12

R152

1K_0402_5%

R153 10K_0402_5%R153 10K_0402_5%

12

+3V_PCH

R156

R156 10K_0402_5%

10K_0402_5%

1 2

CLK_CPU_DMI# [5] CLK_CPU_DMI [5]

1 2

R168 10K_0402_5%R168 10K_0402_5%

1 2

R170 10K_0402_5%R170 10K_0402_5%

1 2

R172 10K_0402_5%R172 10K_0402_5%

1 2

R174 10K_0402_5%R174 10K_0402_5%

1 2

R177 10K_0402_5%R177 10K_0402_5%

1 2

R178 10K_0402_5%R178 10K_0402_5%

1 2

R181 10K_0402_5%R181 10K_0402_5%

1 2

R183 10K_0402_5%R183 10K_0402_5%

1 2

R185 10K_0402_5%R185 10K_0402_5%

CLK_PCI_LPBACK [16]

R189

90.9_0402_1%

1 2

SMB_ALERT# [21]

+3V_PCH

DRAMRST_CNTRL_PCH [6,9]

+3V_PCH

PCH_SML0CLK

PCH_SML0DATA

+1.05VS_VCCDIFFCLKN

DGPU_PRSNT# [17]

2

2.2K_0402_5%

1 2

2.2K_0402_5%

1 2

2.2K_0402_5%

2.2K_0402_5% R206

R206

2.2K_0402_5%

R250

R149

R151

R154

R155

12

+3V_PCH

PLT_RST#[16,21,22,30,32,34,37]

XTAL25_IN

XTAL25_OUT

15P_0402_50V8J

Q2A

Q2A 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

1

6

3 4

6

3 4

C235

SMB_CLK_S3

2.2K_0402_5%

1 2

2

+3VS

1 2

5

2.2K_0402_5%

SMB_DATA_S3

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6 Q2B

Q2B

Q10A

Q10A 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

1

EC_SMB_CK2

2

+3VS

5

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6 Q10B

Q10B

EC_SMB_DA2

+3VS

12

@

R5019

R5019 10K_0402_5%

10K_0402_5%

U32

1

NC

2

NC

3

PROT#

4

GND

PCA24S08D_SO8

EEPROM SA00004MK00 EEPROM SA00004ML00

25MHZ_12PF_X3G025000DC1H~D

1

2

SMB_CLK_S3 [10,21,32,35]

On-board Ch.A RAM

R150

MINI CARD

R147

Security ROM

SMB_DATA_S3 [10,21,32,35]

EC_SMB_CK2 [33,34]

EC Thermal Sensor

EC_SMB_DA2 [33,34]

8

VCC

7

WP

6

SMB_CLK_S3

SCL

5

SMB_DATA_S3

SDA

1 2

R187 1M _0402_5%R18 7 1M_0402_5%

Y3

4

1

NC

OSC

3

2

NC

1

C236

C236 15P_0402_50V8J

15P_0402_50V8J

2

+3VS

1

C696

0.1U_0402_16V4Z

2

R196@

33_0402_5%

A A

CLK_PCI_LPBACK

33_0402_5%

12

C238@

22P_0402_50V8J

1 2

Reserve for EMI please close to P CH

Security Classification

AMY WEN

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/08/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

2012/08/25

2

Title

PCH (2/8) PCIE, SMBUS, CLK

Size Document Number Rev

Custom

LA-8671P_SDV

Date: Sheet of

Thursday, October 04, 2012

Date: Sheet of

Thursday, October 04, 2012

Date: Sheet of

Thursday, October 04, 2012

1

13

50

13

50

13

50

1.0

5

D D

+3VS

5

U2

VGATE[47]

PCH_PWROK[34]

C C

+3V_PCH

B B

+3V_PCH

+3VS

R216

R216 10K_0402_5%

10K_0402_5%

R256

R256 200_0402_5%

200_0402_5%

1

2

@

U2

IN1

VCC

OUT

IN2

GND

MC74VHC1G08DFT2G_SC70-5

3

R200

12

100K_0402_1%

R213

12

10K_0402_5%

12

R214

R214 200K_0402_1%

200K_0402_1%

12

4

SYS_PWROK

SUSWARN#

AC_PRESENT_R

PCH_RSMRST#_R

PM_DRAM_PWR GD

SYS_PWROK

SYS_PWROK [5]

SUSACK# is only used on platform that support th e Deep Sx state.

XDP_DBRESET#[12,5]

PCH_APWROK[34]

PM_DRAM_PWR GD[5]

EC_RSMRST#[12,34]

PBTN_OUT#[12,34,5]

ACIN[34,37,40]

4

DMI_CTX_PRX_N0[4] DMI_CTX_PRX_N1[4] DMI_CTX_PRX_N2[4] DMI_CTX_PRX_N3[4]

DMI_CTX_PRX_P0[4] DMI_CTX_PRX_P1[4] DMI_CTX_PRX_P2[4] DMI_CTX_PRX_P3[4]

DMI_CRX_PTX_N0[4] DMI_CRX_PTX_N1[4] DMI_CRX_PTX_N2[4] DMI_CRX_PTX_N3[4]

DMI_CRX_PTX_P0[4] DMI_CRX_PTX_P1[4] DMI_CRX_PTX_P2[4] DMI_CRX_PTX_P3[4]

+1.05VS_PCH

R5070 0_0402_5%

+3V_PCH

1 2

R197 49.9_0402_1%R197 49.9_0402_1%

1 2

R199 750_0402_1%R199 750_0402_1%

4mil width and place within 500mil of the PCH

PCH_PWROK

SBA@

1 2

T763PADT763PAD

SYS_PWROK

NOSBA@

12

R279

R279 0_0402_5%

0_0402_5%

short@

R382

R382 0_0402_5%

0_0402_5%

short@

D1

D1 RB751V_SOD323

RB751V_SOD323

R219

R219 10K_0402_5%

10K_0402_5%

R220

R220 10K_0402_5%

10K_0402_5%

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

DMI_IRCOMP

RBIAS_CPY

SUSACK#

12

APWROK

R209

R209 0_0402_5%

0_0402_5%

PM_DRAM_PWR GD

12

PCH_RSMRST#_R

SUSWARN#

12

PBTN_OUT#_R

AC_PRESENT_R

12

PCH_GPIO72

12

RI#

UH1C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPW RDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

PANTHER-POINT_FCBGA989

3

DMI

FDI

DMI

FDI

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

SLP_LAN# / GPIO29

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16

AV12

BC10

AV14

BB10

A18

E22

PCH_DPWROK

B9

PCIE_WAKE#

N3

PM_CLKRUN#_R

G8

N14

D10

H4

F4

G10

G16

AP14

K14

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWODVREN

SUS_STAT#

SUSCLK

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

SLP_A#

PM_SLP_SUS#

H_PM_SYNC

PCH_GPIO29

1 2

R210

R210 0_0402_5%

0_0402_5%

short@

R205

R205 10K_0402_5%

10K_0402_5% R207

R207

8.2K_0402_5%

2

FDI_CTX_PRX_N0 [4] FDI_CTX_PRX_N1 [4] FDI_CTX_PRX_N2 [4] FDI_CTX_PRX_N3 [4] FDI_CTX_PRX_N4 [4] FDI_CTX_PRX_N5 [4] FDI_CTX_PRX_N6 [4] FDI_CTX_PRX_N7 [4]

FDI_CTX_PRX_P0 [4] FDI_CTX_PRX_P1 [4] FDI_CTX_PRX_P2 [4] FDI_CTX_PRX_P3 [4] FDI_CTX_PRX_P4 [4] FDI_CTX_PRX_P5 [4] FDI_CTX_PRX_P6 [4] FDI_CTX_PRX_P7 [4]

FDI_INT [4]

FDI_FSYNC0 [4]

FDI_FSYNC1 [4]

FDI_LSYNC0 [4]

FDI_LSYNC1 [4]

12

PCH_RSMRST#_R

PCIE_WAKE# [30]

+3V_PCH

+3VS

T767PAD T767PAD

PM_SLP_S5# [34]

PM_SLP_S4# [34]

PM_SLP_S3# [34]

T766PAD T766PAD

H_PM_SYNC [5]

T771PAD T771PAD

SUSCLK [34]

R221

R221 0_0402_5%

0_0402_5%

SBA@

Can be left NC if no use integrated LAN.

1

+RTCVCC

12

R198

R198 330K_0402_5%

330K_0402_5%

DSWODVREN - On Die DSW VR Enable H：Enable

*

12

R202

R202 330K_0402_5%

330K_0402_5%

@

12

PCH_SLPA# [34]

L：Disable

Can be left NC when IAMT is no t support on the platfrom

@

R268

R268 200_0402_5%

200_0402_5%

A A

AMY WEN

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/08/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

2012/08/25

2

Title

PCH (3/8) DMI,FDI,PM,

Size Document Number Rev

Custom

LA-8671P_SDV

Date: Sheet of

Thursday, October 04, 2012

Date: Sheet of

Thursday, October 04, 2012

Date: Sheet of

Thursday, October 04, 2012

1

50

14

50

14

50

14

1.0

5

4

3

2

1

PORT STRAP

LVDS

PORT B

R5060

2.2K_0402_5%

PORT C

PORT D

+3VS

12

D D

2.2K_0402_5%

EDID_CLK EDID_DATA

22P_0402_50V8J

RF Request

C C

B B

C88

R5020

@

+3VS

12

1

2

12

R5021

2.2K_0402_5%

1

@

C87

C87 22P_0402_50V8J

22P_0402_50V8J

2

ENBKL[34]

R494

100K_0402_1%

+3VS

1 2

PCH_ENVDD[23]

PCH_PWM[23]

EDID_CLK[23]

EDID_DATA[23]

1 2

R5022 2.2K_0402_5%R5022 2.2K_0402_5%

1 2

R5023 2.2K_0402_5%R5023 2.2K_0402_5%

R227

2.37K_0402_1%

LVDS_ACLK#[23] LVDS_ACLK[23]

LVDS_A0#[23] LVDS_A1#[23] LVDS_A2#[23]

LVDS_A0[23] LVDS_A1[23] LVDS_A2[23]

PCH_ENVDD

PCH_PWM

EDID_CLK EDID_DATA

12

R5029

1K_0402_1%

CTRL_CLK CTRL_DATA

LVDS_IBG

CRT_IREF

12

ENBKL

UH1D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

PANTHER-POINT_FCBGA989

LVDS

CRT

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

SDVO_INTN SDVO_INTP

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_AUXN

DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_AUXN

DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38

HDMICLK_NB

M39

HDMIDAT_NB

AT49 AT47 AT40

TMDS_B_HPD

AV42

TMDS_B_DATA2#_PCH

AV40

TMDS_B_DATA2_PCH

AV45

TMDS_B_DATA1#_PCH

AV46

TMDS_B_DATA1_PCH

AU48

TMDS_B_DATA0#_PCH

AU47

TMDS_B_DATA0_PCH

AV47

TMDS_B_CLK#_PCH

AV49

TMDS_B_CLK_PCH

P46

PCH_DPC_CLK

P42

PCH_DPC_DAT

AP47

PCH_DPC_AUXN

AP49

PCH_DPC_AUXP

AT38

DPC_HPD

AY47

PCH_DPC_N0_C

AY49

PCH_DPC_P0_C

AY43

PCH_DPC_N1_C

AY45

PCH_DPC_P1_C

BA47

PCH_DPC_N2_C

BA48

PCH_DPC_P2_C

BB47

PCH_DPC_N3_C

BB49

PCH_DPC_P3_C

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

L_DDC_DATA

SDVO_CTRLDATA

DDPC_CTRLDATA

DDPD_CTRLDATA

12

R5059

2.2K_0402_5%

Near Conn.

1 2

C295 0.1U_0402_10V6KC295 0.1U_0402_10V6K

1 2

C294 0.1U_0402_10V6KC294 0.1U_0402_10V6K

1 2

C539 0.1U_0402_10V6KC539 0.1U_0402_10V6K

1 2

C538 0.1U_0402_10V6KC538 0.1U_0402_10V6K

1 2

C535 0.1U_0402_10V6KC535 0.1U_0402_10V6K

1 2

C534 0.1U_0402_10V6KC534 0.1U_0402_10V6K

1 2

C537 0.1U_0402_10V6KC537 0.1U_0402_10V6K

1 2

C536 0.1U_0402_10V6KC536 0.1U_0402_10V6K

Near Q2208

1 2

C245 0.1U_0402_10V6KC245 0.1U_0402_10V6K

1 2

C244 0.1U_0402_10V6KC244 0.1U_0402_10V6K

1 2

C243 0.1U_0402_10V6KC243 0.1U_0402_10V6K

1 2

C242 0.1U_0402_10V6KC242 0.1U_0402_10V6K

1 2

C545 0.1U_0402_10V6KC545 0.1U_0402_10V6K

1 2

C544 0.1U_0402_10V6KC544 0.1U_0402_10V6K

1 2

C541 0.1U_0402_10V6KC541 0.1U_0402_10V6K

1 2

C540 0.1U_0402_10V6KC540 0.1U_0402_10V6K

1 2

C543 0.1U_0402_10V6KC543 0.1U_0402_10V6K

1 2

C542 0.1U_0402_10V6KC542 0.1U_0402_10V6K

Near Conn.

HDMICLK_NB [24] HDMIDAT_NB [24]

TMDS_B_HPD [24]

HDMI_TX2-_CK [24] HDMI_TX2+_CK [24] HDMI_TX1-_CK [24] HDMI_TX1+_CK [24] HDMI_TX0-_CK [24] HDMI_TX0+_CK [24] HDMI_CLK-_CK [24] HDMI_CLK+_CK [24]

PCH_DPC_CLK [25] PCH_DPC_DAT [25]

PCH_DPC_AUXN_C [25] PCH_DPC_AUXP_C [25]

DPC_HPD [25]

PCH_DPC_DP_N0 [25] PCH_DPC_DP_P0 [25] PCH_DPC_DP_N1 [25] PCH_DPC_DP_P1 [25] PCH_DPC_DP_N2 [25] PCH_DPC_DP_P2 [25] PCH_DPC_DP_N3 [25] PCH_DPC_DP_P3 [25]

HDMI

+3VS

R5147

1 2

R5147

2.2K_0402_5%

1 2

R5115

2.2K_0402_5%

PCH_DPC_CLK

PCH_DPC_DAT

DP

A A

Security Classification

AMY WEN

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/08/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

2012/08/25

2

Title

PCH (4/9) LVDS,CRT,DP,HDMI

Size Document Number Rev

Custom

LA-8671P_SDV

Date: Sheet of

Thursday, October 04, 2012

Date: Sheet of

Thursday, October 04, 2012

Date: Sheet of

Thursday, October 04, 2012

1

50

15

50

15

50

15

1.0

COMPAL LA-8671P Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual