Compal LA-8481P Q3ZMC UMA, Aspire S5-391 Schematic

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Compal Confidential

Model Name : Q3ZMC

1 1

File Name : LA-8481P

Compal Confidential

2 2

Q3ZMC UMA M/B Schematics Document

Intel Ivy/Sandy Bridge SFF BGA 1023p Processor /Panther Point 989p PCH / DDR3L Memory Down *8

3 3

2012-04-11

REV:1.0(MP SMT)

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

C

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

Q3ZMC M/B LA-8481P Schematic

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1 51Thursday, April 12, 2012

1.0

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D

E

PCB

ZZZ1

LA-8481P

DAZ0NS00100

1 1

Fan Control

page 34

eDP Conn.

page 22

eDP

120MHz

Intel

Ivy Bridge ULV

Processor

Memory BUS(DDR3L)

Two Channel

1.35V DDR3L 1333Mhz

BGA1023

page 4~10

FDI x8

Thunderbolt

page 24~27

2 2

HDMI Conn.

page 23

TMDS

DP

100MHz

2.7GT/s

Intel

Panther Point-M

DMI x4

100MHz

1GB/s x4

PCH

100MHz

989pin BGA

page 13~21

Thunderbolt

port 5~8

WLAN

port 2

PCI-Express x 8 (PCIE2.0 5GT/s)

port 1

Card reader

SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S)

USB 3.0 conn x2

USB3.0 port 1,2 USB2.0 port 0,1

USBx14

HD Audio

SPI

LPC

page 31

3.3V 48MHz

3.3V 24MHz

DDR3L-ON BOARD

Debug Port

USB port 9

page 31

Camera

USB port 10

D/B

page 11,12

Bluetooth

page 22

USB port 8

HDA Codec

ALC271X-VB6/ALC281X

page 28

mSATA (Reserve)

USB port 12

page 32

page 28

page 24~27

page 28

page 22

mSATA

port 0

TPM

page 30

SPI ROM x2

page 13

Int. Speaker x 2 Phone Jack x 1

page 32

Int. DMIC x 1

page 32

LPC BUS

3 3

page 29

33MHz

ENE KB930/KB9012

RTC CKT.

page 13

Power On/Off CKT.

page 33

DC/DC Interface CKT.

page 35

4 4

Power Circuit DC/DC

page 36~45

A

LS-8481P Audio/B

page 32

LS-8482P Card Reader/B

page 22

LS-8483P LED/B

page 32

LS-8484P Battery/B

B

Touch Pad

page 33

EC ROM x1 @ for KB930

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

page 33

Issued Date

C

page 33

Int.KBD

page 33

Compal Secret Data

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Block Diagrams

Q3ZMC M/B LA-8481P Schematic

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2 51Thursday, April 12, 2012

1.0

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B

C

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E

Voltage Rails

Power Plane Description

VIN

BATT+ Battery power supply (12.6V) N/A N/A N/A

B+

+VSB +VSBP to +VSB always on power rail for sequence control ON ON*

1 1

+CPU_CORE

+VGFX_CORE Core voltage for UMA graphic ON OFF OFF

+1.05VS_VTT

+1.35V

+1.35VS

+0.675VS +0.675VSP to +0.675VS switched power rail for DDR3L terminator

+1.5VS +1.5VSP to +1.5VS power rail for PCH

+1.8VS +3VALW to 1.8VS switched power rail for PCH

+3VALW +3VALWP to +3VALW always on power rail

+3VALW_PCH +3VALW to +3VALW_PCH power rail for PCH (Short Resistor) ON ON

+3VS

+5VALW

+5VS +5VALW to +5VS switched power rail OFFON OFF

2 2

+RTCVCC RTC power

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU

+1.05VS_VTTP to +1.05VS_VTT switched power rail for CPU

+1.35VP to +1.35V power rail for DDR3L

+1.35V to +1.35VS switched power rail

+3VALW to +3VS power rail

+5VALWP to +5VALW always on power rail

S1 S3 S5

N/A N/A N/A

ON

ON OFF OFF

ON OFF OFF+1.05VS_PCH +1.05VS_VTT to +1.05VS_PCH power for PCH

ON ON OFF

ON OFF OFF

ON

N/AN/AN/A

OFF

ON ON*

ON*

OFF

ON ON*

ONON

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

Board ID / SKU ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0 1 2 3 4 5 6 7 NC

SIGNAL

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

LOW

HIGH

LOW LOW LOW LOW

100K +/- 5%Ra/Rc/Re

Rb / Rd / Rf V min

0

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

LOWLOWLOW

ON

HIGHHIGHHIGH

HIGH

V typ

AD_BID

ON

OFF

ON

OFF

V

AD_BID

0 V 0 V

0.503 V

0.819 V

1.185 V 1.264 V

2.200 V

3.300 V

ON ON

ON

OFF

max

0.538 V

0.875 V

2.341 V

3.300 V

LOW

OFF

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

EC SM Bus1 address

Device

Smart Battery

Address Address

0001 011X b

EC SM Bus2 address

Device

PCH SM Bus address

Device Address

ChannelA

ChannelB

3 3

A0A41010 000X

1010 010X

BOARD ID Table

Board ID

0.1,

0 1 2 3 4

0.2

0.3 DVT:unknown MCU+MKS Motor,With TB IC

0.4 PVT1:PADAUK MCU+MKS Motor,Without TB IC

0.4 PVT2:PADAUK MCU+MKS Motor,With TB IC

1.0

5 6 7

PCB Revision

Unpop

UMA UMA@ CPU PCH DDR3 DDR3L On Board DRAM 128bit RAM 128@ eDP LVDS

BTO Option Table

BTO Item BOM Structure

@ CONN@Connector

IVB@ HM77@ DDR3@ DDR3L@ X76@

eDP@ LVDS@

USB Port Table

BOM Config 4319HNBOL01:UMA@/DDR3L@/eDP@/USB3.0@/9012@/TB@/IVB@/HM77@/DS3@/TXM@/TPM@/128@/

4319HNBOL02:UMA@/DDR3L@/eDP@/USB3.0@/9012@/TB@/IVB@/HM77@/DS3@/TXM@/TPM@

4 4

A

B

USB 2.0 USB 1.1 Port

UHCI0

UHCI1

EHCI1

UHCI2

UHCI3

UHCI4

EHCI2

UHCI5

UHCI6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

0 1 2 3 4 5 6 7 8

9 10 11 12 13

2012/4/6 2013/4/6

2 External USB Port

USB port (Rear side 3.0) USB port (Rear side 3.0)

Debug Port Camera

mSATA(Reserve) BlueTooth

Compal Secret Data

Deciphered Date

D

USB3.0 Conn USB3.0@

USB2.0@USB2.0 Conn

Thunderbolt

KB930 KB9012

Normal S3 Deep S3

TPM+TCM TPM TCM

Custom

Date: Sheet of

TB@

930@ 9012@

S3@ DS3@

TXM@ TPM@ TCM@

Compal Electronics, Inc.

Title

Size Document Number Rev

Compal Electronics, Inc.

Notes List

Q3ZMC M/B LA-8481P Schematic

1.0

3 51Thursday, April 12, 2012

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3 51Thursday, April 12, 2012

1.0

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E

+1.05VS_ VTT

12

R532

24.9_040 2_1%

UCPU1A

1 1

DMI_CRX_P TX_N0<15> DMI_CRX_P TX_N1<15> DMI_CRX_P TX_N2<15> DMI_CRX_P TX_N3<15>

DMI_CRX_P TX_P0<15> DMI_CRX_P TX_P1<15> DMI_CRX_P TX_P2<15> DMI_CRX_P TX_P3<15>

DMI_CTX_P RX_N0<15> DMI_CTX_P RX_N1<15> DMI_CTX_P RX_N2<15> DMI_CTX_P RX_N3<15>

DMI_CTX_P RX_P0<15> DMI_CTX_P RX_P1<15> DMI_CTX_P RX_P2<15> DMI_CTX_P RX_P3<15>

FDI_CTX_P RX_N0<15> FDI_CTX_P RX_N1<15> FDI_CTX_P RX_N2<15>

2 2

eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms should not be left floating ,even if disable eDP function...

+1.05VS_ VTT

12

R118

24.9_040 2_1%

W=4mil,S=15mil,L=500mil

3 3

W=12mil,S=15mil,L=500mil

Add eDP circuit

+1.05VS_ VTT

12

R809

R809 1K_0402 _5%eDP@

1K_0402 _5%eDP@

EDP_HPD #<22>

EDP_HPD #

FDI_CTX_P RX_N3<15> FDI_CTX_P RX_N4<15> FDI_CTX_P RX_N5<15> FDI_CTX_P RX_N6<15> FDI_CTX_P RX_N7<15>

FDI_CTX_P RX_P0<15> FDI_CTX_P RX_P1<15> FDI_CTX_P RX_P2<15> FDI_CTX_P RX_P3<15> FDI_CTX_P RX_P4<15> FDI_CTX_P RX_P5<15> FDI_CTX_P RX_P6<15> FDI_CTX_P RX_P7<15>

FDI_FSYNC0<15> FDI_FSYNC1<15>

FDI_INT<15>

FDI_LSYNC0<15> FDI_LSYNC1<15>

EDP_COM P

EDP_HPD #

EDP_AUX N<22> EDP_AUX P<22>

EDP_TXN 0<22> EDP_TXN 1<22>

EDP_TXP 0<22> EDP_TXP 1<22>

UCPU1A

M2

DMI_RX#[0]

P6

DMI_RX#[1]

P1

DMI_RX#[2]

P10

DMI_RX#[3]

N3

DMI_RX[0]

P7

DMI_RX[1]

P3

DMI_RX[2]

P11

DMI_RX[3]

K1

DMI_TX#[0]

M8

DMI_TX#[1]

N4

DMI_TX#[2]

R2

DMI_TX#[3]

K3

DMI_TX[0]

M7

DMI_TX[1]

P4

DMI_TX[2]

T3

DMI_TX[3]

U7

FDI0_TX#[0]

W11

FDI0_TX#[1]

W1

FDI0_TX#[2]

AA6

FDI0_TX#[3]

W6

FDI1_TX#[0]

V4

FDI1_TX#[1]

Y2

FDI1_TX#[2]

AC9

FDI1_TX#[3]

U6

FDI0_TX[0]

W10

FDI0_TX[1]

W3

FDI0_TX[2]

AA7

FDI0_TX[3]

W7

FDI1_TX[0]

T4

FDI1_TX[1]

AA3

FDI1_TX[2]

AC8

FDI1_TX[3]

AA11

FDI0_FSYNC

AC12

FDI1_FSYNC

U11

FDI_INT

AA10

FDI0_LSYNC

AG8

FDI1_LSYNC

AF3

eDP_COMPIO

AD2

eDP_ICOMPO

AG11

eDP_HPD#

AG4

eDP_AUX#

AF4

eDP_AUX

AC3

eDP_TX#[0]

AC4

eDP_TX#[1]

AE11

eDP_TX#[2]

AE7

eDP_TX#[3]

AC1

eDP_TX[0]

AA4

eDP_TX[1]

AE10

eDP_TX[2]

AE6

eDP_TX[3]

IVY-BRIDGE_BGA1 023

IVB@

ULV type P/N:

1.SA00005B000:S IC AV8063801057400 QBP7 K0 1.7G BGA

2.SA00005AZ30:S IC AV8063801057401 QBTP K0 1.5G BGA

DMI Intel(R) FDI

eDP

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[10]

PEG_RX[11]

PEG_RX[12]

PEG_RX[13]

PEG_RX[14]

PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8]

PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PCI EXPRESS -- GRAPHICS

PEG_TX[10]

PEG_TX[11]

PEG_TX[12]

PEG_TX[13]

PEG_TX[14]

PEG_TX[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9]

PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9]

G3 G1 G4

H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7

K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6

G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4

F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4

PEG_COM P

G3,W=4mil,S=15mil,L=500mil G1,W=12mil,S=15mil,L=500mil G4,W=4mil,S=15mil,L=500mil

UMA only=>PEG NC

PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms

PEG_ICOMPO signals should be routed with - max length = 500 milstypical impedance = 14.5 mohms

4 4

Security Class ification

2012/4/6 2013/4/6

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/4/6 2013/4/6

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(1/7) DMI,FDI,PEG

Q3ZMC M/B LA-8481P Schematic

4 51Thursday, April 12, 2012

E

1.0

A

1 1

2 2

PCH->CPU UNCOREPWRGOOD: SM_DRAMPWROK:DRAM power ok RESET#:

都都都都ok後後後後後後後後

CPU

非非非非

CORE

做做做做

reset

外外外外外外外外外外外外

OK

PROC_SELECT# Future platforms,PH VCPLL and connect to PCH DF_TVS

Follow DG 1.2 & CRB1.0 Checklist1.0 P.64 Processor Graphis Disable Guide

C784 0.1U_0402_10V7K

R223 10K_0402_5%R223 10K_0402_5%

12

@

12

Follow DG 1.2 & CRB1.0

Buffered reset to CPU

3 3

PLT_RST#<17,22,24,30,32>

RESET#:

Follow DG 1.2 & CRB1.0

C101

0.1U_0402_16V4Z

SYS_PWROK<15>

4 4

PM_DRAM_PWR GD<15>

+3VS

1

NC

2

A

都都都都ok後後後後後後後後

+3VALW

1

2

U5

2

1

A

5

P

G

3

B

A

H_CPUPWRGD

1

2

U15

Y

SN74LVC1G07DCKR_SC70-5

CPU

5

P

Y

G

MC74VHC1G09DFT2G_SC70-5

3

Processor Pullups follow CRB1.0

Use open drain MOS: +1.05VS_VTT PH pop 75ohm series resister pop 43ohm

C396

0.1U_0201_10V6K

4

BUFO_CPU_RST#

做做做做

reset

4

PM_SYS_PWRGD_BUF

SUSP<35,40>

H_PROCHOT#<32>

+1.05VS_VTT

12

R226

R226 75_0402_5%

75_0402_5%

43_0402_1%

1 2

2

SUSP

G

+1.05VS_VTT

R227

+1.35VS

12

R88

R88 200_0402_5%

200_0402_5%

12

R829

R829 39_0402_5%

39_0402_5%

@

13

D

Q74

Q74 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

@

S

R220 62_0402_5%R220 62_0402_5%

BUF_CPU_RST#

12

@

R225

R225 0_0402_5%

0_0402_5%

Use open drain MOS: +1.35VS PH pop 200ohm series resister pop 130ohm

1 2

R97 130_0402_5%R97 1 30_0402_5%

偵偵偵偵偵偵偵偵

XBOX

H_CPUPWRGD<18>

B

CPU

有有有有有有有有有有有有有有有有

三三三三三三三三三三三三三三三三

12

H_THRMTRIP#<18>

UNCOREPWRGOOD:

PM_DRAM_PWR GD_R

B

H_SNB_IVB#<17>

T1 PAD@T1 PAD

H_PECI<18,32>

R216

56_0402_5%

1 2

H_PM_SYNC<15>

R80

@R80

@

0_0402_5%

1 2

除除除除除除除除

PM_DRAM_PWR GD_R

SM_DRAMPWROK:DRAM power ok

BUF_CPU_RST#

@

H_CATERR#

H_PECI

H_PROCHOT#_RH_PROCHOT#

H_CPUPWRGD_R

CPU_CORE

PM_DRAM_PWR GD

C787

100P_0201_25V8J

以以以以以以以以以以以以以以以以

1

2

UCPU1B

F49

PROC_SELECT#

C57

PROC_DETECT#

C49

CATERR#

A48

PECI

C45

PROCHOT#

D45

THERMTRIP#

C48

PM_SYNC

B46

UNCOREPWRGOOD

OK

BE45

SM_DRAMPWR OK

D44

RESET#

IVY-BRIDGE_BGA1023

IVB@

C

J3

BCLK

MISC THERMAL PWR MANAGEMENT

DPLL_REF_CLK

DPLL_REF_CLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

DDR3

MISC

DDR3

MISC

JTAG & BPM

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/4/6 2013/4/6

H2

BCLK#

AG3 AG1

AT30

BF44 BE43 BG43

N53

PRDY#

N55

PREQ#

L56

TCK

L55

TMS

J58

TRST#

M60

TDI

L59

TDO

K58

DBR#

G58

BPM#[0]

E55

BPM#[1]

E59

BPM#[2]

G55

BPM#[3]

G59

BPM#[4]

H60

BPM#[5]

J59

BPM#[6]

J61

BPM#[7]

Compal Secret Data

CLK_CPU_DPLL CLK_CPU_DPLL#

SM_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

DDR3 Compensation Signals Trace:10mil ,Spacing:13mil, Max.Length:500mil

XDP_TCK XDP_TMS XDP_TRST#

XDP_TDI XDP_TDO

XDP_DBRESET#

Deciphered Date

D

CLK_CPU_DMI <14> CLK_CPU_DMI# <14>

CLK_CPU_DPLL <1 4> CLK_CPU_DPLL# < 14>

SM_DRAMRST# <6>

R149 140_0402_1%R149 140_0402_1% R486 25.5_0402_1%R486 25.5_0402_1% R484 200_0402_1%R484 200_0402_1%

12 12 12

T2PAD@ T2PAD@ T3PAD@ T3PAD@ T4PAD@ T4PAD@

T5PAD@ T5PAD@ T6PAD@ T6PAD@

1 2

C102

C102 100P_0201_25V8J

100P_0201_25V8J

XDP_DBRESET# <15>

For EMI

D

Custom

Date: Sheet of

E

+1.05VS_VTT

CLK_CPU_DPLL#

CLK_CPU_DPLL

DIS only SKU or UMA eDP disable DPLL_REF_SSCLK PD 1K_5% to GND DPLL_REF_SSCLK# PH 1K_5% to +1.05VS_VTT

XDP_DBRESET#

CRB1.0 PH 1K +3VS Check list 1.0 PH 5K +3VS Check list 1.2 PH 10K +3VS Debug port DG1.1-1.2 50~5K ohm

Title

Size Document Number Rev

Q3ZMC M/B LA-8481P Schematic

R116 1K_0402_5%@R116 1K_0402_5%@

R117 1K_0402_5%@R117 1K_0402_5%@

R569 1K_0402_5%R569 1K_0402_5%

Compal Electronics, Inc.

PROCESSOR(2/7) PM,XDP,CLK

12

+3VS

12

5 51Thursday, April 12, 2012

E

5 51Thursday, April 12, 2012

1.0

A

UCPU1C

DDR_A_D[0..63]<11>

1 1

2 2

3 3

DDR_A_BS0<11> DDR_A_BS1<11> DDR_A_BS2<11>

DDR_A_CAS#<11> DDR_A_RAS#<11> DDR_A_WE#<11>

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

UCPU1C

AG6

SA_DQ[0]

AJ6

SA_DQ[1]

AP11

SA_DQ[2]

AL6

SA_DQ[3]

AJ10

SA_DQ[4]

AJ8

SA_DQ[5]

AL8

SA_DQ[6]

AL7

SA_DQ[7]

AR11

SA_DQ[8]

AP6

SA_DQ[9]

AU6

SA_DQ[10]

AV9

SA_DQ[11]

AR6

SA_DQ[12]

AP8

SA_DQ[13]

AT13

SA_DQ[14]

AU13

SA_DQ[15]

BC7

SA_DQ[16]

BB7

SA_DQ[17]

BA13

SA_DQ[18]

BB11

SA_DQ[19]

BA7

SA_DQ[20]

BA9

SA_DQ[21]

BB9

SA_DQ[22]

AY13

SA_DQ[23]

AV14

SA_DQ[24]

AR14

SA_DQ[25]

AY17

SA_DQ[26]

AR19

SA_DQ[27]

BA14

SA_DQ[28]

AU14

SA_DQ[29]

BB14

SA_DQ[30]

BB17

SA_DQ[31]

BA45

SA_DQ[32]

AR43

SA_DQ[33]

AW48

SA_DQ[34]

BC48

SA_DQ[35]

BC45

SA_DQ[36]

AR45

SA_DQ[37]

AT48

SA_DQ[38]

AY48

SA_DQ[39]

BA49

SA_DQ[40]

AV49

SA_DQ[41]

BB51

SA_DQ[42]

AY53

SA_DQ[43]

BB49

SA_DQ[44]

AU49

SA_DQ[45]

BA53

SA_DQ[46]

BB55

SA_DQ[47]

BA55

SA_DQ[48]

AV56

SA_DQ[49]

AP50

SA_DQ[50]

AP53

SA_DQ[51]

AV54

SA_DQ[52]

AT54

SA_DQ[53]

AP56

SA_DQ[54]

AP52

SA_DQ[55]

AN57

SA_DQ[56]

AN53

SA_DQ[57]

AG56

SA_DQ[58]

AG53

SA_DQ[59]

AN55

SA_DQ[60]

AN52

SA_DQ[61]

AG55

SA_DQ[62]

AK56

SA_DQ[63]

BD37

SA_BS[0]

BF36

SA_BS[1]

BA28

SA_BS[2]

BE39

SA_CAS#

BD39

SA_RAS#

AT41

SA_WE#

IVY-BRIDGE_BGA1023

IVB@

Follow CRB1.0

R78

0_0402_5%

1 2

@

1 2

C78

@

D

S

D

S

Q6

G

BSS138-G_SOT23-3

2

1

2

13

DIMM_DRAMRST#_RSM_DRAMRST#

@

R416

R416 0_0402_5%

0_0402_5%

1 2

CPU通通DIMM做reset

SM_DRAMRST#<5>

R79

4.99K_0402_1%

4 4

DRAMRST_CNTRL_PC H<11,12,14>

DRAMRST_CNTRL_EC<32>

A

1 2

R418 0_0402_5%R418 0_0402_5%

1 2

R413 0_0402_5%DS3@R413 0_0402_5%DS3@

.047U_0402_16V7K

B

AU36

SA_CK[0]

AV36

SA_CK#[0]

AY26

SA_CKE[0]

AT40

SA_CK[1]

AU40

SA_CK#[1]

BB26

SA_CKE[1]

BB40

SA_CS#[0]

BC41

SA_CS#[1]

AY40

SA_ODT[0]

BA41

SA_ODT[1]

AL11

SA_DQS#[0]

AR8

SA_DQS#[1]

AV11

SA_DQS#[2]

AT17

SA_DQS#[3]

AV45

SA_DQS#[4]

AY51

SA_DQS#[5]

AT55

SA_DQS#[6]

AK55

SA_DQS#[7]

AJ11

SA_DQS[0]

AR10

SA_DQS[1]

AY11

SA_DQS[2]

AU17

SA_DQS[3]

AW45

SA_DQS[4]

AV51

SA_DQS[5]

AT56

SA_DQS[6]

AK54

SA_DQS[7]

DDR SYSTEM MEMORY A

BG35

SA_MA[0]

BB34

SA_MA[1]

BE35

SA_MA[2]

BD35

SA_MA[3]

AT34

SA_MA[4]

AU34

SA_MA[5]

BB32

SA_MA[6]

AT32

SA_MA[7]

AY32

SA_MA[8]

AV32

SA_MA[9]

BE37

SA_MA[10]

BA30

SA_MA[11]

BC30

SA_MA[12]

AW41

SA_MA[13]

AY28

SA_MA[14]

AU26

SA_MA[15]

+1.35V

12

R66

1K_0402_5%

R63

R63 1K_0402_5%

1K_0402_5%

1 2

S0 DRAMRST_CNTRL_PCH hgih ,MOS ON SM_DRAMRST# HIGH,DDR3 DRAMRST# HIGH Dimm not reset S3 DRAMRST_CNTRL_PCH Low ,MOS OFF SM_DRAMRST# Low,DDR3 DRAMRST# HIGH Dimm not reset S4,S5 DRAMRST_CNTRL_PCH Low ,MOS OFF SM_DRAMRST# Low,DDR3 DRAMRST# Low Dimm reset

B

DDR_A_CLK1 DDR_A_CLK1#

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DIMM_DRAMRST# <11,12>

C

DDR_B_D[0..63]<12>

DDR_A_CLK0 <11> DDR_A_CLK0# <11> DDR_A_CKE0 <11>

12

R263

R263 75_0402_1%

75_0402_1%

DDR_A_CS0# <11>

DDR_A_ODT0 <11>

DDR_A_DQS#[0..7] <11>

DDR_A_DQS[0..7] <11>

DDR_A_MA[0..15] <11>

DDR_B_BS0<12> DDR_B_BS1<12> DDR_B_BS2<12>

DDR_B_CAS#<12> DDR_B_RAS#<12> DDR_B_WE#<12>

DIMM_DRAMRST# SM_DRAMRST#

1

C785

100P_0201_25V8J

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

Issued Date

C

2

UCPU1D

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

1

C786

C786 100P_0402_50V8J

100P_0402_50V8J

2

2012/4/6 2013/4/6

AL4

SB_DQ[0]

AL1

SB_DQ[1]

AN3

SB_DQ[2]

AR4

SB_DQ[3]

AK4

SB_DQ[4]

AK3

SB_DQ[5]

AN4

SB_DQ[6]

AR1

SB_DQ[7]

AU4

SB_DQ[8]

AT2

SB_DQ[9]

AV4

SB_DQ[10]

BA4

SB_DQ[11]

AU3

SB_DQ[12]

AR3

SB_DQ[13]

AY2

SB_DQ[14]

BA3

SB_DQ[15]

BE9

SB_DQ[16]

BD9

SB_DQ[17]

BD13

SB_DQ[18]

BF12

SB_DQ[19]

BF8

SB_DQ[20]

BD10

SB_DQ[21]

BD14

SB_DQ[22]

BE13

SB_DQ[23]

BF16

SB_DQ[24]

BE17

SB_DQ[25]

BE18

SB_DQ[26]

BE21

SB_DQ[27]

BE14

SB_DQ[28]

BG14

SB_DQ[29]

BG18

SB_DQ[30]

BF19

SB_DQ[31]

BD50

SB_DQ[32]

BF48

SB_DQ[33]

BD53

SB_DQ[34]

BF52

SB_DQ[35]

BD49

SB_DQ[36]

BE49

SB_DQ[37]

BD54

SB_DQ[38]

BE53

SB_DQ[39]

BF56

SB_DQ[40]

BE57

SB_DQ[41]

BC59

SB_DQ[42]

AY60

SB_DQ[43]

BE54

SB_DQ[44]

BG54

SB_DQ[45]

BA58

SB_DQ[46]

AW59

SB_DQ[47]

AW58

SB_DQ[48]

AU58

SB_DQ[49]

AN61

SB_DQ[50]

AN59

SB_DQ[51]

AU59

SB_DQ[52]

AU61

SB_DQ[53]

AN58

SB_DQ[54]

AR58

SB_DQ[55]

AK58

SB_DQ[56]

AL58

SB_DQ[57]

AG58

SB_DQ[58]

AG59

SB_DQ[59]

AM60

SB_DQ[60]

AL59

SB_DQ[61]

AF61

SB_DQ[62]

AH60

SB_DQ[63]

BG39

SB_BS[0]

BD42

SB_BS[1]

AT22

SB_BS[2]

AV43

SB_CAS#

BF40

SB_RAS#

BD45

SB_WE#

IVY-BRIDGE_BGA1023

IVB@

1

C788

C788 100P_0402_50V8J

100P_0402_50V8J

2

Compal Secret Data

Deciphered Date

D

BA34

SB_CK[0]

AY34

SB_CK#[0]

AR22

SB_CKE[0]

BA36

SB_CK[1] SB_CK#[1] SB_CKE[1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

DDR SYSTEM MEMORY B

SB_MA[0]

SB_MA[1]

SB_MA[2]

SB_MA[3]

SB_MA[4]

SB_MA[5]

SB_MA[6]

SB_MA[7]

SB_MA[8]

SB_MA[9]

SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

D

DDR_B_CLK1

BB36

DDR_B_CLK1#

BF27

BE41 BE47

AT43 BG47

AL3

DDR_B_DQS#0

AV3

DDR_B_DQS#1

BG11

DDR_B_DQS#2

BD17

DDR_B_DQS#3

BG51

DDR_B_DQS#4

BA59

DDR_B_DQS#5

AT60

DDR_B_DQS#6

AK59

DDR_B_DQS#7

AM2

DDR_B_DQS0

AV1

DDR_B_DQS1

BE11

DDR_B_DQS2

BD18

DDR_B_DQS3

BE51

DDR_B_DQS4

BA61

DDR_B_DQS5

AR59

DDR_B_DQS6

AK61

DDR_B_DQS7

BF32

DDR_B_MA0

BE33

DDR_B_MA1

BD33

DDR_B_MA2

AU30

DDR_B_MA3

BD30

DDR_B_MA4

AV30

DDR_B_MA5

BG30

DDR_B_MA6

BD29

DDR_B_MA7

BE30

DDR_B_MA8

BE28

DDR_B_MA9

BD43

DDR_B_MA10

AT28

DDR_B_MA11

AV28

DDR_B_MA12

BD46

DDR_B_MA13

AT26

DDR_B_MA14

AU22

DDR_B_MA15

Address 0~13:For 128*16 Address 0~14:For 256*16 Address 0~15:For 512*16

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(3/7) DDRIII

Q3ZMC M/B LA-8481P Schematic

E

DDR_B_CLK0 <12> DDR_B_CLK0# <12> DDR_B_CKE0 <12>

12

R264

R264 75_0402_1%

75_0402_1%

DDR_B_CS0# <12>

DDR_B_ODT0 <12>

DDR_B_DQS#[0..7] <12>

DDR_B_DQS[0..7] <12>

DDR_B_MA[0..15] <12>

E

1.0

6 51Thursday, April 12, 2012

1.0

A

B

C

D

E

Default "1",EDS R1.0 P.88

CFG Straps for Processor

UCPU1E

T72 PAD@T72 PAD@

+CPU_CORE

1 1

R810

@

49.9_0402_1%

1 2

VCC_VAL_SENSE

VSS_VAL_SENSE

R812

@

49.9_0402_1%

1 2

+VGFX_CORE

R811

@

49.9_0402_1%

1 2

VAXG_VAL_SENSE

R813

@

49.9_0402_1%

1 2

VSSAXG_VAL_SENSE

2 2

CFG0

CFG2

CFG4 CFG5 CFG6 CFG7

VCC_VAL_SENSE VSS_VAL_SENSE

VAXG_VAL_SENSE VSSAXG_VAL_SENSE

T56 PAD@T56 PAD@

B50

CFG[0]

C51

CFG[1]

B54

CFG[2]

D53

CFG[3]

A51

CFG[4]

C53

CFG[5]

C55

CFG[6]

H49

CFG[7]

A55

CFG[8]

H51

CFG[9]

K49

CFG[10]

K53

CFG[11]

F53

CFG[12]

G53

CFG[13]

L51

CFG[14]

F51

CFG[15]

D52

CFG[16]

L53

CFG[17]

H43

VCC_VAL_SENSE

K43

VSS_VAL_SENSE

H45

VAXG_VAL_SENSE

K45

VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

H48

RSVD6

K48

RSVD7

BA19

RSVD8

AV19

RSVD9

AT21

RSVD10

BB21

RSVD11

BB19

RSVD12

AY21

RSVD13

BA22

RSVD14

AY22

RSVD15

AU19

RSVD16

AU21

RSVD17

BD21

RSVD18

BD22

RSVD19

BD25

RSVD20

BD26

RSVD21

BG22

RSVD22

BE22

RSVD23

BG26

RSVD24

BE26

RSVD25

BF23

RSVD26

BE24

RSVD27

IVY-BRIDGE_BGA1023

IVB@

RESERVED

DC_TEST_A4 DC_TEST_C4 DC_TEST_D3

DC_TEST_D1 DC_TEST_A58 DC_TEST_A59

DC_TEST_C59

DC_TEST_A61

DC_TEST_C61

DC_TEST_D61 DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58

DC_TEST_BG4 DC_TEST_BG3 DC_TEST_BE3 DC_TEST_BG1 DC_TEST_BE1 DC_TEST_BD1

BCLK_ITP

BCLK_ITP#

RSVD30 RSVD31 RSVD32 RSVD33

RSVD34 RSVD35 RSVD36 RSVD37 RSVD38

RSVD39 RSVD40

RSVD41 RSVD42 RSVD43 RSVD44

RSVD45

N59 N58

N42 L42 L45 L47

M13 M14 U14 W14 P13

AT49 K24

AH2 AG13 AM14 AM15

N50

A4 C4 D3

DC_TEST_C4_D3

D1 A58 A59 C59

DC_TEST_A59_C59

A61 C61

DC_TEST_A61_C61

D61 BD61 BE61 BE59

DC_TEST_BE59_BE61

BG61 BG59

DC_TEST_BG59_BG61

BG58 BG4 BG3 BE3

DC_TEST_BE3_BG3

BG1 BE1

DC_TEST_BE1_BG1

BD1

These pins are for solder joint reliability and non-critical to function. For BGA only.

PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane # definition matches

CFG2

socket pin map definition

0:Lane Reversed

*

CFG2

12

R234

R234 1K_0402_1%

1K_0402_1%

eDP enable

CFG4

1:Disable

*

0:Enable

CFG4

12

eDP@

R204

R204 1K_0402_1%

1K_0402_1%

PCIE Port Bifurcation Straps

11: (Default) 1x16 PCI Express

*

CFG[6:5]

10: 2x8 PCI Express

01: Reserved

00: 1x8,2x4 PCI Express

CFG6

CFG5

12

R230

1K_0402_1% @

R228

1K_0402_1%@

3 3

PEG DEFER TRAINING

1: (Default) PEG Train immediately following

CFG7

xxRESETB de assertion

CRB1.0 P.12

0: PEG Wait for BIOS for training

CFG7

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

12

R224

R224 1K_0402_1%@

1K_0402_1%@

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(4/7) RSVD,CFG

Q3ZMC M/B LA-8481P Schematic

E

7 51Thursday, April 12, 2012

1.0

A

INTEL Recommend VCC 3*330uF,12*22uF(0805),16*2.2uF(0402) PD0.9

1 1

2 2

3 3

4 4

B

UCPU1F

ULV SC/DC 33A

+CPU_CORE

UCPU1F

A26

VCC[1]

A29

VCC[2]

A31

VCC[3]

A34

VCC[4]

A35

VCC[5]

A38

VCC[6]

A39

VCC[7]

A42

VCC[8]

C26

VCC[9]

C27

VCC[10]

C32

VCC[11]

C34

VCC[12]

C37

VCC[13]

C39

VCC[14]

C42

VCC[15]

D27

VCC[16]

D32

VCC[17]

D34

VCC[18]

D37

VCC[19]

D39

VCC[20]

D42

VCC[21]

E26

VCC[22]

E28

VCC[23]

E32

VCC[24]

E34

VCC[25]

E37

VCC[26]

E38

VCC[27]

F25

VCC[28]

F26

VCC[29]

F28

VCC[30]

F32

VCC[31]

F34

VCC[32]

F37

VCC[33]

F38

VCC[34]

F42

VCC[35]

G42

VCC[36]

H25

VCC[37]

H26

VCC[38]

H28

VCC[39]

H29

VCC[40]

H32

VCC[41]

H34

VCC[42]

H35

VCC[43]

H37

VCC[44]

H38

VCC[45]

H40

VCC[46]

J25

VCC[47]

J26

VCC[48]

J28

VCC[49]

J29

VCC[50]

J32

VCC[51]

J34

VCC[52]

J35

VCC[53]

J37

VCC[54]

J38

VCC[55]

J40

VCC[56]

J42

VCC[57]

K26

VCC[58]

K27

VCC[59]

K29

VCC[60]

K32

VCC[61]

K34

VCC[62]

K35

VCC[63]

K37

VCC[64]

K39

VCC[66]

K42

VCC[67]

L25

VCC[68]

L28

VCC[69]

L33

VCC[70]

L36

VCC[71]

L40

VCC[72]

N26

VCC[73]

N30

VCC[74]

N34

VCC[75]

N38

VCC[76]

IVY-BRIDGE_BGA1023

IVB@

C

POWER

CORE SUPPLY

VCCIO[1] VCCIO[3] VCCIO[4] VCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8]

VCCIO[9] VCCIO[10] VCCIO[11] VCCIO[12] VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16] VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20] VCCIO[21] VCCIO[22] VCCIO[23] VCCIO[24] VCCIO[25] VCCIO[26] VCCIO[27] VCCIO[28] VCCIO[29]

VCCIO[30] VCCIO[31] VCCIO[32]

PEG IO AND DDR IO

VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49]

VCCIO50

VCCIO51

VCCIO_SEL

VCCPQE[1] VCCPQE[2]

RAILS

VIDALERT#

VIDSCLK

VIDSOUT

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID QUIET

8.5A

AF46 AG48 AG50 AG51 AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48

AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15

W16 W17

BC22

AM25 AN22

A44 B43 C44

F43 G43

AN16 AN17

VCCSENSE_R VSSSENSE_R

VCCIO_SEL_R

+1.05VS_VTT

12

C951

C951 1U_0201_4V6M

1U_0201_4V6M

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

VCCIO_SENSE VSSIO_SENSE

D

+1.05VS_VTT

INTEL Recommend VCCIO PD 0.9

330uF 1+1 10uF (0603) *5 1uF (0201) *16

+1.05VS_VTT

330uF 1 10uF (0603) *5 1uF (0201) *10

10K_0402_5%

+1.05VS_VTT

R582 0_0402_5%@R582 0_0402_5%@

1 2

+1.05VS_VTT

Place the PU,PD resistors close to CPU

1 2

R579 0_0402_5%@R579 0_0402_5%@ R581 0_0402_5%@R581 0_0402_5%@

1 2

R107 10_0402_5%R107 10_0402_5%

12

R105

R105 10_0402_5%

10_0402_5%

VCCIO_SEL

10K_0402_5% @

12

R574

R574 130_0402_5%

130_0402_5%

+1.05VS_VTT

VCCIO_SENSE <41>

Should change to connect from power cirucit & layout differential with VCCIO_SENSE.

+3VALW

VCCIO_SEL For 2012 CPU support

R521

R520

1 2

R576 43_0402_1%R 576 4 3_0402_1% R577 0_0402_5%@R577 0_0402_5%@

1 2 1 2

R578 0_0402_5%@R578 0_0402_5%@

+CPU_CORE

1 2

12

A19

R588

R588 100_0402_1%

100_0402_1%

R589

R589 100_0402_1%

100_0402_1%

E

1 : +1.05VS_VTT

*

0: +1.0VS_VTT

Check List R1.5 VIDALERT#:75ohm ±5% pull-up to VCCIO close to IMVP7 VIDSCLK: 55ohm ±5% pull-up to VCCIO close to IMVP7 VIDSOUT: 130ohm ±5% pull-up to VCCIO close to CPU 130ohm ±5% pull-up to VCCIO close to IMVP7

VR_SVID_ALRT# <43> VR_SVID_CLK <43> VR_SVID_DAT <43 >

VCCSENSE <43> VSSSENSE < 43>

Check List R1.5 VCCSENSE:100ohm ±1% pull-up to VCC near processor. VSSSENSE:100ohm ±1% pull-down to GND near processor.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(5/7) PWR,BYPASS

Q3ZMC M/B LA-8481P Schematic

E

8 51Thursday, April 12, 2012

1.0

A

INTEL Recommend VAXG

+VGFX_CORE

2*330uF,5*22uF(0805),6*10uF(0603),6*1uF(0402) PD 0.9

1 1

2 2

Check List R1.5 VCCAXG_SENSE:100ohm ±5% pull-up to VCC near processor. VSSAXG_SENSE:100ohm ±5% pull-down to GND near processor.

INTEL Recommend VCCPLL 1*330uF,2*1uF(0402) PD 0.9

3 3

+1.8VS

+VCCSA

R477

0_0805_5%

1 2

1

+

C606

C606 220U_B2_2.5VM_R15M

220U_B2_2.5VM_R15M

SGA00004I00

2

1

+

C607

C607 330U_B2_2VM_R15M

330U_B2_2VM_R15M

SGA00004400

2

VCC_AXG_SENSE<43>

VSS_AXG_SENSE<43>

+1.8VS_VCCPLL

+VCCSA

C999

C998

1U_0201_4V6M

12

B

ULV SC/DC GT1: 18A GT2: 33A

R381

1 2

100_0402_5%

1 2

100_0402_5%

C583

1U_0201_4V6M

C583

1U_0201_4V6M

1

2

R381

R396

1.2A

C584

1U_0201_4V6M

C584

1U_0201_4V6M

1

2

+VGFX_CORE

6A

C1179

C1180

C1181

1U_0201_4V6M

12

1U_0201_4V6M

12

UCPU1G

AA46

VAXG[1]

AB47

VAXG[2]

AB50

VAXG[3]

AB51

VAXG[4]

AB52

VAXG[5]

AB53

VAXG[6]

AB55

VAXG[7]

AB56

VAXG[8]

AB58

VAXG[9]

AB59

VAXG[10]

AC61

VAXG[11]

AD47

VAXG[12]

AD48

VAXG[13]

AD50

VAXG[14]

AD51

VAXG[15]

AD52

VAXG[16]

AD53

VAXG[17]

AD55

VAXG[18]

AD56

VAXG[19]

AD58

VAXG[20]

AD59

VAXG[21]

AE46

VAXG[22]

N45

VAXG[23]

P47

VAXG[24]

P48

VAXG[25]

P50

VAXG[26]

P51

VAXG[27]

P52

VAXG[28]

P53

VAXG[29]

P55

VAXG[30]

P56

VAXG[31]

P61

VAXG[32]

T48

VAXG[33]

T58

VAXG[34]

T59

VAXG[35]

T61

VAXG[36]

U46

VAXG[37]

V47

VAXG[38]

V48

VAXG[39]

V50

VAXG[40]

V51

VAXG[41]

V52

VAXG[42]

V53

VAXG[43]

V55

VAXG[44]

V56

VAXG[45]

V58

VAXG[46]

V59

VAXG[47]

W50

VAXG[48]

W51

VAXG[49]

W52

VAXG[50]

W53

VAXG[51]

W55

VAXG[52]

W56

VAXG[53]

W61

VAXG[54]

Y48

VAXG[55]

Y61

VAXG[56]

F45

VAXG_SENSE

G45

VSSAXG_SENSE

BB3

VCCPLL[1]

BC1

VCCPLL[2]

BC4

VCCPLL[3]

L17

VCCSA[1]

L21

VCCSA[2]

N16

VCCSA[3]

N20

VCCSA[4]

N22

VCCSA[5]

P17

VCCSA[6]

P20

VCCSA[7]

R16

VCCSA[8]

R18

VCCSA[9]

R21

VCCSA[10]

U15

VCCSA[11]

V16

VCCSA[12]

V17

VCCSA[13]

V18

VCCSA[14]

V21

VCCSA[15]

W20

VCCSA[16]

IVY-BRIDGE_BGA1023

IVB@

POWER

VREF

DDR3 - 1.5V RAILS

GRAPHICS

SENSE

LINES

SENSE

LINES

1.8V RAIL

SA RAIL

VCCSA VID

C

SM_VREF

SA_DIMM_VREFDQ SB_DIMM_VREFDQ

VDDQ[10] VDDQ[11] VDDQ[12] VDDQ[13] VDDQ[14] VDDQ[15] VDDQ[16] VDDQ[17] VDDQ[18] VDDQ[19] VDDQ[20] VDDQ[21] VDDQ[22] VDDQ[23] VDDQ[24] VDDQ[25] VDDQ[26]

VCCDQ[1] VCCDQ[2]

QUIET RAILS

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

SENSE LINES

VCCSA_VID[0] VCCSA_VID[1]

lines

SA_DIMM_VREFDQ SB_DIMM_VREFDQ For Future CPU M3 support, Sandey bridge not support M3, Check list1.0 & CRB say can NC

AY43

+V_SM_VREF

BE7

SA_DIMM_VREFDQ

BG7

SB_DIMM_VREFDQ

5A

AJ28

VDDQ[1]

AJ33

VDDQ[2]

AJ36

VDDQ[3]

AJ40

VDDQ[4]

AL30

VDDQ[5]

AL34

VDDQ[6]

AL38

VDDQ[7]

AL42

VDDQ[8]

AM33

VDDQ[9]

AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

AM28 AN26

BC43 BA43

U10

D48 D49

+1.35VS

CPU EDS1.3 P.93 VCCSA_VID0 Must PD

H_VCCSA_VID0 H_VCCSA_VID1

12

@

R69

1K_0402_1%

C978

C977

1U_0201_4V6M

12

Place BOT OUT Conn

C986

C1002

0.1U_0201_10V6K

12

C985

C985 1U_0201_4V6M

1U_0201_4V6M

12

R129

R129 0_0402_5%

0_0402_5%

@

12

@

R68

1K_0402_1%

C979

1U_0201_4V6M

12

C1010

0.1U_0201_10V6K

12

SA_DIMM_VREFDQ <11> SB_DIMM_VREFDQ <12>

C981

C980

1U_0201_4V6M

12

C1007

C1008

0.1U_0201_10V6K

12

VCCSA_SENSE <42>

H_VCCSA_VID0 <42> H_VCCSA_VID1 <42>

D

+V_SM_VREF should have 20 mil trace width

0.1U_0201_10V6K

C647

+1.35VS

12

R534

R534 1K_0402_5%

1K_0402_5%

1

2

12

R540

R540 1K_0402_5%

1K_0402_5%

E

INTEL Recommend VDDQ 1*330uF,8*10uF(0603) ,10*1uF(0402) PD0.9

Short for +1.35VS to +1.35V_CPU_VDDQ

C988

C991

1U_0201_4V6M

12

C1006

0.1U_0201_10V6K

12

1U_0201_4V6M

12

C990

C989

10U_0603_6.3V6M

12

C994

C1009

0.1U_0201_10V6K

12

C984

C983

C982

1U_0201_4V6M

C991

1U_0201_4V6M

12

C970

C987

10U_0603_6.3V6M

12

C992

C993

0.1U_0201_10V6K

12

VCCSA_VID

For 2012 future CPU VCCSA voltage select

VCCSA

VID1

0

1

Vout

0.9V

0.8V

VID0

0

0.85V V

0 X1

1 1

0.725V

0.675V

1

+

C599

C599 330U_B2_2VM_R15M

330U_B2_2VM_R15M

SGA00004400

2

SNB IVB

V V

V

VX

+1.35VS

ULV

V

INTEL Recommend VCCSA

4 4

1*330uF,5*10uF(0603) ,5*1uF(0402)

C995

10U_0603_6.3V6M

12

C997

C996

10U_0603_6.3V6M

12

PD0.9

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(6/7) PWR

Q3ZMC M/B LA-8481P Schematic

E

9 51Thursday, April 12, 2012

1.0

A

1 1

2 2

3 3

B

UCPU1H

A13

AA13 AA50 AA51 AA52 AA53 AA55 AA56

AB16 AB18 AB21 AB48 AB61 AC10 AC14 AC46

AC6 AD17 AD20

AD4 AD61 AE13

AE8

AF1

AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58

AF59 AG10 AG14 AG18 AG47 AG52 AG61

AG7 AH4

AH58

AJ13

AJ16

AJ20

AJ22

AJ26

AJ30

AJ34

AJ38

AJ42

AJ45

AJ48

AK1

AK52

AL10

AL13

AL17

AL21

AL25

AL28

AL33

AL36

AL40

AL43

AL47

AL61 AM13 AM20 AM22 AM26 AM30 AM34

VSS[1]

A17

VSS[2]

A21

VSS[3]

A25

VSS[4]

A28

VSS[5]

A33

VSS[6]

A37

VSS[7]

A40

VSS[8]

A45

VSS[9]

A49

VSS[10]

A53

VSS[11]

A9

VSS[12]

AA1

VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20]

AA8

VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69]

AJ7

VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90]

VSS

VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]

VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180]

AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13

C

UCPU1I

BG17

VSS[181]

BG21

VSS[182]

BG24

VSS[183]

BG28

VSS[184]

BG37

VSS[185]

BG41

VSS[186]

BG45

VSS[187]

BG49

VSS[188]

BG53

VSS[189]

BG9

VSS[190]

C29

VSS[191]

C35

VSS[192]

C40

VSS[193]

D10

VSS[194]

D14

VSS[195]

D18

VSS[196]

D22

VSS[197]

D26

VSS[198]

D29

VSS[199]

D35

VSS[200]

D4

VSS[201]

D40

VSS[202]

D43

VSS[203]

D46 D50 D54 D58

E25 E29

E35 E40 F13 F15 F19 F29 F35 F40 F55 G51

G61 H10 H14 H17 H21

H53 H58

K11 K21 K51

M11 M15

VSS[204] VSS[205] VSS[206] VSS[207]

D6

VSS[208] VSS[209] VSS[210]

E3

VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221]

G6

VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227]

H4

VSS[228] VSS[229] VSS[230]

J1

VSS[231]

J49

VSS[232]

J55

VSS[233] VSS[234] VSS[235] VSS[236]

K8

VSS[237]

L16

VSS[238]

L20

VSS[239]

L22

VSS[240]

L26

VSS[241]

L30

VSS[242]

L34

VSS[243]

L38

VSS[244]

L43

VSS[245]

L48

VSS[246]

L61

VSS[247] VSS[248] VSS[249]

VSS

NCTF

VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301]

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14

D

M4 M58 M6 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P14 P16 P18 P21 P58 P59 P9 R17 R20 R4 R46 T1 T47 T50 T51 T52 T53 T55 T56 U13 U8 V20 V61 W13 W15 W18 W21 W46 W8 Y4 Y47 Y58 Y59 G48

A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61

T58PAD@ T58PAD@ T59PAD@ T59PAD@ T60PAD@ T60PAD@ T61PAD@ T61PAD@ T62PAD@ T62PAD@ T63PAD@ T63PAD@ T64PAD@ T64PAD@ T65PAD@ T65PAD@ T66PAD@ T66PAD@ T67PAD@ T67PAD@ T68PAD@ T68PAD@ T69PAD@ T69PAD@ T70PAD@ T70PAD@ T71PAD@ T71PAD@

E

CR CheckList Rev1.5

IVY-BRIDGE_BGA1023

IVB@

IVY-BRIDGE_BGA1023

4 4

A

B

IVY-BRIDGE_BGA1023

IVB@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Title

Size Document Number Rev

Compal Electronics, Inc.

PROCESSOR(7/7) VSS

Q3ZMC M/B LA-8481P Schematic

E

10 51Thursday, April 12, 2012

1.0

A

B

C

D

E

Channel A

DDR_A_MA[0..15]<6>

DDR_A_DQS#[0..7]<6>

DDR_A_DQS[0..7]<6>

DDR_A_D[0..63]<6>

+VREFCA_A

1 1

C1252

0.1U_0402_16V4Z

C1252

0.1U_0402_16V4Z

1

2

+VREFDQ_A

0.1U_0402_16V4Z

1

C1253

2

2 2

DIMM_DRAMRST#<12,6>

+0.675VS

DDR_A_MA[0..15]

DDR_A_DQS#[0..7]

DDR_A_DQS[0..7]

DDR_A_D[0..63]

U56

M8

VREFCA

H1

VREFDQ

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12

@

C1258

2.2U_0603_6.3V6K@C1258

2.2U_0603_6.3V6K

12

DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 DDR_A_MA15 DDR_A_MA15 DDR_A_MA15

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

DDR_A_CLK0 DDR_A_CLK0# DDR_A_CKE0

DDR_A_ODT0 DDR_A_CS0# DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

DDR_A_DQS1 DDR_A_DQS0

DDR_A_DQS#1 DDR_A_DQS#0

DIMM_DRAMRST#

1 2

R992

240_0402_1%

1 2

R996

240_0402_1%

C1519

10U_0603_6.3V6M

C1519

10U_0603_6.3V6M

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

H5TQ2G63BFR-11C_FBGA96

X76@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3

DDR_A_D8

F7

DDR_A_D10

F2

DDR_A_D13

F8

DDR_A_D11

H3

DDR_A_D12

H8

DDR_A_D15

G2

DDR_A_D9

H7

DDR_A_D14

D7

DDR_A_D3

C3

DDR_A_D1

C8

DDR_A_D2

C2

DDR_A_D4

A7

DDR_A_D7

A2

DDR_A_D0

B8

DDR_A_D6

A3

DDR_A_D5

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

+VREFCA_A

C1255

0.1U_0402_16V4Z

C1255

0.1U_0402_16V4Z

+VREFDQ_A

1

2

0.1U_0402_16V4Z

1

C1254

2

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12

@

C1259

2.2U_0603_6.3V6K@C1259

2.2U_0603_6.3V6K

12

DDR_A_MA13 DDR_A_MA14

DDR_A_BS0

DDR_A_BS1 DDR_A_BS2

DDR_A_CLK0 DDR_A_CLK0# DDR_A_CKE0

DDR_A_ODT0 DDR_A_CS0# DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

DDR_A_DQS2 DDR_A_DQS3

DDR_A_DQS#2 DDR_A_DQS#3

DIMM_DRAMRST#

1 2

R993

240_0402_1%

1 2

R997

240_0402_1%

U57

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

H5TQ2G63BFR-11C_FBGA96

X76@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

U58

E3

DDR_A_D16

F7

DDR_A_D19

F2

DDR_A_D20

F8

DDR_A_D18

H3

DDR_A_D22

H8

DDR_A_D23

G2

DDR_A_D17

H7

DDR_A_D21

D7

DDR_A_D25

C3

DDR_A_D29

C8

DDR_A_D27

C2

DDR_A_D28

A7

DDR_A_D31

A2

DDR_A_D30

B8

DDR_A_D26

A3

DDR_A_D24

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

+VREFCA_A

C1256

0.1U_0402_16V4Z

C1256

0.1U_0402_16V4Z

+VREFDQ_A

1

2

0.1U_0402_16V4Z

1

C1260

2

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12

C1261

2.2U_0603_6.3V6K

C1261

2.2U_0603_6.3V6K

12

DDR_A_MA13 DDR_A_MA14

DDR_A_BS0

DDR_A_BS1 DDR_A_BS2

DDR_A_CLK0 DDR_A_CLK0# DDR_A_CKE0

DDR_A_ODT0 DDR_A_CS0# DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

DDR_A_DQS4 DDR_A_DQS5

DDR_A_DQS#4 DDR_A_DQS#5

DIMM_DRAMRST#

1 2

R994

240_0402_1%

1 2

R998

240_0402_1%

U58

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

H5TQ2G63BFR-11C_FBGA96

X76@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

+1.35V

+VREFCA_A

C1257

0.1U_0402_16V4Z

C1257

0.1U_0402_16V4Z

+VREFDQ_A

E3

DDR_A_D32

F7

DDR_A_D34

F2

DDR_A_D33

F8

DDR_A_D35

H3

DDR_A_D37

H8

DDR_A_D39

G2

DDR_A_D36

H7

DDR_A_D38

D7

DDR_A_D42

C3

DDR_A_D45

C8

DDR_A_D47

C2

DDR_A_D44

A7

DDR_A_D46

A2

DDR_A_D40

B8

DDR_A_D43

A3

DDR_A_D41

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

U59

M8

VREFCA

H1

1

2

0.1U_0402_16V4Z

1

C1262

2

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12

C1263

2.2U_0603_6.3V6K

C1263

2.2U_0603_6.3V6K

12

DDR_A_MA13 DDR_A_MA14

DDR_A_BS0

DDR_A_BS1 DDR_A_BS2

DDR_A_CLK0 DDR_A_CLK0# DDR_A_CKE0

DDR_A_ODT0 DDR_A_CS0# DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

DDR_A_DQS6 DDR_A_DQS7

DDR_A_DQS#6 DDR_A_DQS#7

DIMM_DRAMRST#

1 2

R995

240_0402_1%

1 2

R999

240_0402_1%

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

H5TQ2G63BFR-11C_FBGA96

X76@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3

DDR_A_D52

F7

DDR_A_D54

F2

DDR_A_D48

F8

DDR_A_D50

H3

DDR_A_D53

H8

DDR_A_D55

G2

DDR_A_D49

H7

DDR_A_D51

D7

DDR_A_D63

C3

DDR_A_D61

C8

DDR_A_D58

C2

DDR_A_D60

A7

DDR_A_D59

A2

DDR_A_D56

B8

DDR_A_D62

A3

DDR_A_D57

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

+1.35V+1.35V +1.35V

12

C1481

DDR3 CTL/ADD Termination

+0.675VS

1 2

DDR_A_RAS#

R284 36_0201_1%R284 36_0201_1%

1 2

DDR_A_CAS#

R290 36_0201_1%R290 36_0201_1%

1 2

DDR_A_ODT0

R291 36_0201_1%R291 36_0201_1%

1 2

DDR_A_CKE0

R294 36_0201_1%R294 36_0201_1%

1 2

DDR_A_WE#

R295 36_0201_1%R295 36_0201_1%

1 2

DDR_A_MA10

R296 36_0201_1%R296 36_0201_1%

1 2

DDR_A_CS0#

R297 36_0201_1%R297 36_0201_1%

1 2

DDR_A_BS2

R298 36_0201_1%R298 36_0201_1%

1 2

DDR_A_BS0

R301 36_0201_1%R301 36_0201_1%

1 2

DDR_A_MA12

R303 36_0201_1%R303 36_0201_1%

1 2

DDR_A_MA0

R304 36_0201_1%R304 36_0201_1%

1 2

DDR_A_BS1

R306 36_0201_1%R306 36_0201_1%

1 2

DDR_A_MA3

R309 36_0201_1%R309 36_0201_1%

1 2

DDR_A_MA1

R311 36_0201_1%R311 36_0201_1%

1 2

DDR_A_MA2

R312 36_0201_1%R312 36_0201_1%

1 2

DDR_A_MA4

R313 36_0201_1%R313 36_0201_1%

1 2

DDR_A_MA5

R315 36_0201_1%R315 36_0201_1%

1 2

DDR_A_MA11

R317 36_0201_1%R317 36_0201_1%

1 2

DDR_A_MA9

R318 36_0201_1%R318 36_0201_1%

1 2

DDR_A_MA14

R319 36_0201_1%R319 36_0201_1%

1 2

DDR_A_MA13

R323 36_0201_1%R323 36_0201_1%

1 2

DDR_A_MA6

R325 36_0201_1%R325 36_0201_1%

1 2

DDR_A_MA7

R332 36_0201_1%R332 36_0201_1%

1 2

DDR_A_MA8

R333 36_0201_1%R333 36_0201_1%

1 2

DDR_A_MA15

R342 36_0201_1%R342 36_0201_1%

C

DDR3 CLK Termination

C1458

1 2

0.1U_0402_16V4Z

DDR_A_RAS# <6>

DDR_A_CAS# <6>

DDR_A_ODT0 <6>

DDR_A_CKE0 <6>

DDR_A_WE# <6>

DDR_A_CS0# <6>

DDR_A_BS2 <6>

DDR_A_BS0 <6>

DDR_A_BS1 <6>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

DDR_A_CLK0< 6>

DDR_A_CLK0#<6>

1.CAD Note: Cterm= 1.6pF should be kept near feeding point of first SDRAM

2.CAD Note: Rtt= 30.1ohms, Ctt= 0.1uF should be kept within 600mils from last SDRAM

0.1U_0402_16V4Z

R1102

30.1_0402_1%

12

R1103

30.1_0402_1%

END topology

12

C1457

1.8P_0201_50V8C

Compal Secret Data

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

D

Delete U70 SPD EEROM circuit SA00004KS00 S IC EE 2K AT24C02C-XHM-T TSSOP 8P

External DDR Thermal Sensor

+3VS

C97

0.1U_0402_16V4Z

1 2

U4

1

VDD

2

D+

3

D-

THERM#4GND

W83L771AWG-2 TSSOP8P

SA00003PU00

SA00003PU00 S IC W83L771AWG-2 TSSOP 8P SENSOR

Title

DDRIII DIMMA

Size Document Number Rev

Custom

Q3ZMC M/B LA-8481P Schematic

Date: Sheet of

8

SCLK

7

SDATA

6

5

E

1 2

R546 10K_0402_5%R546 10K_0402_5%

ALERT#

Compal E lectronics, Inc.

EC_SMB_CK2 <14,24,32>

EC_SMB_DA2 <14,24,32>

+3VS

11 51Thursday, April 12, 2012

1.0

3 3

+0.675VS

C1462

1U_0201_4V6M

C1462

1U_0201_4V6M

12

Layout Note: Place near each memory part

+1.35V

C1466

0.1U_0201_10V6K

C1466

0.1U_0201_10V6K

12

+1.35V

4 4

C1469

10U_0603_6.3V6M

C1469

10U_0603_6.3V6M

12

C1460

1U_0201_4V6M

C1460

1U_0201_4V6M

C1459

0.1U_0201_10V6K

C1459

C1461

0.1U_0201_10V6K

C1461

0.1U_0201_10V6K

12

C1476

1U_0402_6.3V6K

C1476

1U_0402_6.3V6K

12

C1479

10U_0603_6.3V6M

C1479

10U_0603_6.3V6M

12

0.1U_0201_10V6K

12

C1467

0.1U_0201_10V6K

C1467

0.1U_0201_10V6K

C1477

1U_0402_6.3V6K

C1477

1U_0402_6.3V6K

12

C1475

10U_0603_6.3V6M

C1475

10U_0603_6.3V6M

C1463

10U_0603_6.3V6M

C1463

10U_0603_6.3V6M

12

C1513

0.1U_0201_10V6K

C1513

0.1U_0201_10V6K

C1514

1U_0201_4V6M

C1514

1U_0201_4V6M

12

C1470

0.1U_0201_10V6K

C1470

0.1U_0201_10V6K

C1471

1U_0402_6.3V6K

C1471

1U_0402_6.3V6K

12

C1465

10U_0603_6.3V6M

C1465

10U_0603_6.3V6M

C1473

10U_0603_6.3V6M

C1473

10U_0603_6.3V6M

12

C1511

1U_0201_4V6M

C1511

1U_0201_4V6M

C1512

0.1U_0201_10V6K

C1512

0.1U_0201_10V6K

12

C1478

1U_0402_6.3V6K

C1478

1U_0402_6.3V6K

C1468

1U_0402_6.3V6K

C1468

1U_0402_6.3V6K

12

C1472

10U_0603_6.3V6M

C1472

10U_0603_6.3V6M

C1474

10U_0603_6.3V6M

C1474

10U_0603_6.3V6M

12

M3 support

SA_DIMM_VREFDQ<9>

BSS138_NL_SOT23-3 @

DRAMRST_CNTRL_PCH<12,14,6>

R1108

1K_0402_1%

R1107

1K_0402_1%

330U_D2_2V_Y

@

C1464

12

+

1K_0402_1%

+1.35V

@R1105

@

0_0402_5%

1 2

S

12

C1483

0.1U_0402_16V4Z

C1483

0.1U_0402_16V4Z

12

R1105

G

2

+VREFCA_A

2.2U_0603_6.3V6K

C1482

+1.35V

12

R1106

R1106 1K_0402_1%

1K_0402_1%

+VREFDQ_A

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

C1480

12

R1104

R1104 1K_0402_1%

1K_0402_1%

C1480

12

D

13

Q78

12

near U56 near U57 near U58 near U59

A

B

A

B

C

D

E

U60

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

H5TQ2G63BFR-11C_FBGA96

X76@

DDR_B_DQS#[0..7] <6 >

DDR_B_DQS[0..7] <6>

DDR_B_D[0..63] <6>

DDR_B_MA[0..15] <6>

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1

VDDQ

A8

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H2

VDDQ

H9

VDDQ

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1

VSSQ

B9

VSSQ

D1

VSSQ

D8

VSSQ

E2

VSSQ

E8

VSSQ

F9

VSSQ

G1

VSSQ

G9

VSSQ

DDR_B_D12 DDR_B_D10 DDR_B_D13 DDR_B_D11 DDR_B_D8 DDR_B_D15 DDR_B_D9 DDR_B_D14

DDR_B_D1 DDR_B_D2 DDR_B_D7 DDR_B_D5 DDR_B_D6 DDR_B_D4 DDR_B_D3 DDR_B_D0

C1295

128@

+VREFCA_B

0.1U_0402_16V4Z

+VREFDQ_B+VREFDQ_B

U61

M8

VREFCA

H1

1

128@

2

0.1U_0402_16V4Z

1

2

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10

@

DDR_B_MA11 DDR_B_MA12

C1293

2.2U_0603_6.3V6K@C1293

2.2U_0603_6.3V6K

12

DDR_B_MA13

C1299

DDR_B_MA14

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

DDR_B_CLK0 DDR_B_CLK0# DDR_B_CKE0

DDR_B_ODT0 DDR_B_CS0# DDR_B_RAS# DDR_B_CAS# DDR_B_WE#

DDR_B_DQS2 DDR_B_DQS3

DDR_B_DQS#2 DDR_B_DQS#3

DIMM_DRAMRST#

R1006

1 2

240_0402_1%

128@

R1010

1 2

240_0402_1%

128@

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

H5TQ2G63BFR-11C_FBGA96

X76@

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3

DDR_B_D16

DQL0

F7

DDR_B_D23

DQL1

F2

DDR_B_D17

DQL2

F8

DDR_B_D22

DQL3

H3

DDR_B_D21

DQL4

H8

DDR_B_D18

DQL5

G2

DDR_B_D20

DQL6

H7

DDR_B_D19

DQL7

D7

DDR_B_D30

C3

DDR_B_D25

C8

DDR_B_D27

C2

DDR_B_D28

A7

DDR_B_D26

A2

DDR_B_D29

B8

DDR_B_D31

A3

DDR_B_D24

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

C1296

0.1U_0402_16V4Z

C1296

0.1U_0402_16V4Z

1

128@

2

+VREFDQ_B

0.1U_0402_16V4Z

1

128@

+1.35V +1.35V

2

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12

C1291

2.2U_0603_6.3V6K

C1291

2.2U_0603_6.3V6K

12

DDR_B_MA13

C1300

DDR_B_MA14

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

DDR_B_CLK0 DDR_B_CLK0# DDR_B_CKE0

DDR_B_ODT0 DDR_B_CS0# DDR_B_RAS# DDR_B_CAS# DDR_B_WE#

DDR_B_DQS4 DDR_B_DQS5

DDR_B_DQS#4 DDR_B_DQS#5

DIMM_DRAMRST#

R1007

1 2

240_0402_1%

128@

R1011

1 2

240_0402_1%

128@

U62

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

H5TQ2G63BFR-11C_FBGA96

X76@

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

U63

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

H5TQ2G63BFR-11C_FBGA96

X76@

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3

DDR_B_D61

DQL0

F7

DDR_B_D58

DQL1

F2

DDR_B_D60

DQL2

F8

DDR_B_D62

DQL3

H3

DDR_B_D56

DQL4

H8

DDR_B_D59

DQL5

G2

DDR_B_D57

DQL6

H7

DDR_B_D63

DQL7

D7

DDR_B_D55

C3

DDR_B_D52

C8

DDR_B_D51

C2

DDR_B_D49

A7

DDR_B_D54

A2

DDR_B_D48

B8

DDR_B_D50

A3

DDR_B_D53

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1

VSSQ

D8 E2 E8 F9 G1 G9

+1.35V+1.35V

E3

DDR_B_D37

DQL0

F7

DDR_B_D39

DQL1

F2

DDR_B_D36

DQL2

F8

DDR_B_D38

DQL3

H3

DDR_B_D32

DQL4

H8

DDR_B_D34

DQL5

G2

DDR_B_D33

DQL6

H7

DDR_B_D35

DQL7

D7

DDR_B_D42

C3

DDR_B_D41

C8

DDR_B_D47

C2

DDR_B_D44

A7

DDR_B_D46

A2

DDR_B_D45

B8

DDR_B_D43

A3

DDR_B_D40

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1

VSSQ

D8 E2 E8 F9 G1 G9

C1297

0.1U_0402_16V4Z

C1297

0.1U_0402_16V4Z

+VREFDQ_B

128@

+VREFCA_B+VREFCA_B

1

128@

2

0.1U_0402_16V4Z

1

2

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10

128@

DDR_B_MA11 DDR_B_MA12

C1302

2.2U_0603_6.3V6K

C1302

2.2U_0603_6.3V6K

12

DDR_B_MA13

C1301

DDR_B_MA14

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

DDR_B_CLK0 DDR_B_CLK0# DDR_B_CKE0

DDR_B_CS0# DDR_B_RAS# DDR_B_CAS# DDR_B_WE#

DDR_B_DQS7 DDR_B_DQS6

DDR_B_DQS#7 DDR_B_DQS#6

DIMM_DRAMRST#

R1008

1 2

240_0402_1%

128@

R1012

1 2

240_0402_1%

128@

Channel B

+VREFCA_B

1 1

2 2

C1294

0.1U_0402_16V4Z

C1294

0.1U_0402_16V4Z

1

128@

2

0.1U_0402_16V4Z

1

128@

2

DIMM_DRAMRST#<11,6>

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10

@

DDR_B_MA11 DDR_B_MA12

C1292

2.2U_0603_6.3V6K@C1292

2.2U_0603_6.3V6K

12

DDR_B_MA13

C1298

DDR_B_MA14 DDR_B_MA15 DDR_B_MA15 DDR_B_MA15 DDR_B_MA15

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

DDR_B_CLK0 DDR_B_CLK0# DDR_B_CKE0

DDR_B_ODT0 DDR_B_ODT0 DDR_B_CS0# DDR_B_RAS# DDR_B_CAS# DDR_B_WE#

DDR_B_DQS1 DDR_B_DQS0

DDR_B_DQS#1 DDR_B_DQS#0

DIMM_DRAMRST#

R1005

1 2

240_0402_1%

128@

R1009

1 2

240_0402_1%

128@

+0.675VS

C1517

1U_0201_4V6M

C1517

C1503

1U_0201_4V6M

C1503

1U_0201_4V6M

C1502

0.1U_0201_10V6K

C1502

0.1U_0201_10V6K

1U_0201_4V6M

C1504

1U_0201_4V6M

C1504

1U_0201_4V6M

12

3 3

4 4

12

128@

Layout Note: Place near each memory part

+1.35V

0.1U_0201_10V6K

C1487

0.1U_0201_10V6K

C1487

0.1U_0201_10V6K

12

128@

+1.35V

C1490

10U_0603_6.3V6M

C1490

10U_0603_6.3V6M

12

128@

1U_0201_4V6M

12

128@

0.1U_0201_10V6K

C1497

C1498

0.1U_0201_10V6K

C1498

0.1U_0201_10V6K

12

128@

10U_0603_6.3V6M

C1500

C1485

10U_0603_6.3V6M

C1485

10U_0603_6.3V6M

12

128@

1U_0201_4V6M

C1518

0.1U_0201_10V6K

C1518

0.1U_0201_10V6K

C1501

12

128@

C1488

C1491

1U_0402_6.3V6K

C1491

1U_0402_6.3V6K

C1492

1U_0402_6.3V6K

C1492

1U_0402_6.3V6K

12

128@

C1494

10U_0603_6.3V6M

C1494

10U_0603_6.3V6M

C1496

C1486

10U_0603_6.3V6M

C1486

10U_0603_6.3V6M

12

128@

C1515

0.1U_0201_10V6K

C1515

0.1U_0201_10V6K

C1516

0.1U_0201_10V6K

C1516

0.1U_0201_10V6K

12

128@

C1489

0.1U_0201_10V6K

C1489

0.1U_0201_10V6K

C1499

1U_0402_6.3V6K

C1499

1U_0402_6.3V6K

12

128@

C1493

10U_0603_6.3V6M

C1493

10U_0603_6.3V6M

C1495

10U_0603_6.3V6M

C1495

10U_0603_6.3V6M

330U_D2_2V_Y

C1484

12

+

128@

M3 support

SB_DIMM_VREFDQ<9>

DRAMRST_CNTRL_PCH<11,14,6>

BSS138_NL_SOT23-3 @

+1.35V

12

128@

R1120

1K_0402_1%

12

128@

R1119

1K_0402_1%

C1508

0.1U_0402_16V4Z

C1508

0.1U_0402_16V4Z

12

128@

near U60 near U61 near U62 near U63

A

B

R1122

@R1122

@

0_0402_5%

1 2

S

G

2

+VREFCA_B

2.2U_0603_6.3V6K

C1507

128@

+1.35V

12

128@

R1123

R1123 1K_0402_1%

1K_0402_1%

+VREFDQ_B

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

C1509

C1510

D

13

12

Q79

128@

R1121

R1121 1K_0402_1%

1K_0402_1%

12

C1510

12

128@

C

DDR3 CTL/ADD Termination

+0.675VS

128@

1 2

DDR_B_RAS#

R380 36_0 201_1%

128@

1 2

DDR_B_CAS#

R308 36_0 201_1%

128@

1 2

DDR_B_ODT0

R339 36_0 201_1%

128@

1 2

DDR_B_CKE0

R349 36_0 201_1%

128@

1 2

DDR_B_WE#

R343 36_0 201_1%

128@

1 2

DDR_B_MA10

R348 36_0 201_1%

128@

1 2

DDR_B_CS0#

R354 36_0 201_1%

128@

1 2

DDR_B_BS2

R370 36_0 201_1%

128@

1 2

DDR_B_BS0

R340 36_0 201_1%

128@

1 2

DDR_B_MA12

R352 36_0 201_1%

128@

1 2

DDR_B_MA0

R407 36_0 201_1%

128@

1 2

DDR_B_BS1

R351 36_0 201_1%

128@

1 2

DDR_B_MA3

R392 36_0 201_1%

128@

1 2

DDR_B_MA1

R398 36_0 201_1%

128@

1 2

DDR_B_MA2

R377 36_0 201_1%

128@

1 2

DDR_B_MA4

R356 36_0 201_1%

128@

1 2

DDR_B_MA5

R355 36_0 201_1%

128@

1 2

DDR_B_MA11

R359 36_0 201_1%

128@

1 2

DDR_B_MA9

R367 36_0 201_1%

128@

1 2

DDR_B_MA14

R408 36_0 201_1%

128@

1 2

DDR_B_MA13

R335 36_0 201_1%

128@

1 2

DDR_B_MA6

R350 36_0 201_1%

128@

1 2

DDR_B_MA7

R336 36_0 201_1%

128@

1 2

DDR_B_MA8

R344 36_0 201_1%

128@

1 2

DDR_B_MA15

R390 36_0 201_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR_B_RAS# <6>

DDR_B_CAS# <6>

DDR_B_ODT0 <6>

DDR_B_CKE0 <6>

DDR_B_WE# <6>

DDR_B_CS0# <6>

DDR_B_BS2 <6>

DDR_B_BS0 <6>

DDR_B_BS1 <6>

Compal Secret Data

D

Compal Secret Data

Deciphered Date

2012/4/6 2013/4/6

Delete U71 SPD EEROM circuit SA00004KS00 S IC EE 2K AT24C02C-XHM-T TSSOP 8P

DDR_B_CLK0<6>

DDR_B_CLK0#<6>

1.CAD Note: Cterm= 1.6pF should be kept near feeding point of first SDRAM

2.CAD Note: Rtt= 30.1ohms, Ctt= 0.1uF should be kept within 600mils from last SDRAM

DDR3 CLK Termination

C1506

128@

1 2

0.1U_0402_16V4Z

R1117

30.1_0402_1%

12

128@

R1118

30.1_0402_1%

END topology

12

C1505

1.8P_0201_50V8C128@

Compal Electronics, Inc.

Title

DDRIII DIMMB

Size Document Number Rev

Custom

Q3ZMC M/B LA-8481P Schematic

Date: Sheet of

E

1.0

12 51Thursday, April 12, 2012

A

12

1

R568

+RTCVCC

R338 20K_0402_5%R338 20K_04 02_5%

R337 20K_0402_5%R337 20K_04 02_5%

1 1

+RTCVCC

C516

1U_0402_6.3V6K

1 2

C502

1U_0402_6.3V6K

1 2

R353 1M_0402_5%R353 1M_0402_5%

1 2

R347 330K_0402_5%R347 330K_0402_5 %

INTVRMEN

H

：：：：

Integrated VRM enable

*

L

：：：：

Integrated VRM disable

R568 0_0603_5%

0_0603_5%

@

2

PCH_RTCRST#

PCH_SRTCRST#

1

2

SM_INTRUDER#

PCH_INTVRMEN

1 2

R638 10M_0402_5 %R638 10M_0402_5 %

X1

SJ100004Z00

12

32.768KHZ_12.5PF_9H03200 019

1

C756

C756 18P_0402_50V8J

18P_0402_50V8J

2

(INTVRMEN should always be pull high.)

+3VS

HIGH= Enable ( No Reboot)Disable TCO timer system reboot feature

LOW= Disable (Default internal PD)

*

2 2

HDA_SDO<32>

HDA_SDO

ME debug mode,this signal has a weak internal PD

Low = Disabled (Default)

*

High = Enabled [Flash Descriptor Security Overide]

+VCCSUS3_3

This signal has a weak internal pull-down

On Die PLL VR Select is supplied by

1.5V when smapled high

*

1.8V when sampled low Needs to be pulled High for Huron River platfrom

HDA_BITCLK_AUDIO<33>

3 3

HDA_SYNC_AUDIO<33 >

HDA_RST_AUDIO#<33>

HDA_SDOUT_AUDIO<33>

+3VALW_PCH +3VALW_PCH+3VALW_PCH

12

@

12

@

4 4

@

1 2

R405 1K_0402_5%

+VCCSUS3_3

R328 1K_0402_5%R328 1K_040 2_5%

R660

200_0402_5%

PCH_JTAG_TDO PCH_JTAG_TDIPCH_JTAG_TMS

R670

100_0402_1%

R322

@R32 2

@

1K_0402_5%

12

@

R320 0_04 02_5%

12

1 2

R677

33_0402_5%

1 2

R676

33_0402_5%

1 2

R673

33_0402_5%

1 2

R665

33_0402_5%

12

R659

@

200_0402_5%

12

R671

@

100_0402_1%

+3VS

A

PCH_SPKR

HDA_SDOUT_PCH

12

HDA_SYNC_PCH

HDA_BITCLK_PCH

HDA_SYNC_PCH_R

HDA_RST_PCH#

HDA_SDOUT_PCH

12

R658

@

200_0402_5%

12

R669

@

100_0402_1%

1 2

R699 3.3K_0402_5%R 699 3.3K_0402_5 %

1 2

R700 3.3K_0402_5%R 700 3.3K_0402_5 %

1 2

R703 3.3K_0402_5%R 703 3.3K_0402_5 %

Prevent back drive issue.

+5VS

G

2

Q20

Q20 BSS138W-7-F_SOT323-3

BSS138W-7-F_SOT323-3

13

HDA_SYNC_PCH

D

S

D

S

R302

1 2

0_0402_5%@

12

PCH_SPI_CS0# SPI_WP0# SPI_HOLD0#

PCH_SPI_CS1# PCH_SPI_MISO_1 SPI_WP1#

0_0402_5%@

R468

R468 1M_0402_5%

1M_0402_5%

PCH_SPI_CLK_0

R739 33_0402_5%R739 33_0402_5%

PCH_SPI_CLK_1

R704 33_0402_5%R704 33_0402_5%

PCH_SPI_CS1# PCH_SPI_ CS1#_R

R733 0_0402_5%R733 0_0402_5%

PCH_SPI_MOSI_0

R737 33_0402_5%R737 33_0402_5%

PCH_SPI_MOSI_1

R734 33_0402_5%R734 33_0402_5%

PCH_SPI_MISO_0

R736 33_0402_5%R736 33_0402_5%

PCH_SPI_MISO_1

R738 33_0402_5%R738 33_0402_5%

U40

1

CS#

3

WP#

7

HOLD#

4

GND

MX25L3206EM2I-12G_SO8

SA00003K800

1 2 3 4

B

PCH_RTCX1

PCH_RTCX2

1

C757

C757 18P_0402_50V8J

18P_0402_50V8J

2

PCH_SPKR< 33>

HDA_SDIN0<33>

12

4MB=32Mb

U42

CS# SO WP# GND

MX25L1606EM2I-12G_SO8

SA00003FO10

VCC

SCLK

SI

SO

2MB=16Mb

VCC

HOLD#

SCLK

SI

B

8 6 5 2

8 7 6 5

R672

51_0402_5%

+3VS

PCH_SPI_CLK_0 PCH_SPI_MOSI_0 PCH_SPI_MISO_0

+3VS

SPI_HOLD1# PCH_SPI_CLK_1 PCH_SPI_MOSI_1

PCH_RTCX1

PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BITCLK_PCH

HDA_SYNC_PCH

PCH_SPKR

HDA_RST_PCH#

HDA_SDIN0

HDA_SDOUT_PCH

12

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_SPI_CLK

PCH_SPI_CS0#

PCH_SPI_MOSI

PCH_SPI_MISO

R701 3.3K_0402_5%R 701 3.3K_0402_5 %

+RTCBATT

+RTCVCC

3

1

C197

0.1U_0402_16V4Z

2

U37A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

COUGARPOINT_FCBGA989~D

HM77@

Reserve for EMI

PCH_SPI_CLK

12

1

D5

D5 BAS40-04_SOT23-3

BAS40-04_SOT23-3

2

+CHGRTC

20MIL

RTC Battery:Chargeable

RTCIHDA

JTAG

SPI

S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO!SA00005AGI0

@

1 2

R977

22P_0402_50V8J

22_0402_5%

22P_0402_50V8J

Security Classification

+3VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

LPC

FWH4 / LFRAME#

LDRQ1# / GPIO23

SATA 6G

SATA

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATA0GP / GPIO21

SATA1GP / GPIO19

@

C1216

1 2

Issued Date

C

LDRQ0#

SERIRQ

SATA0RXN SATA0RXP SATA0TXN

SATA0TXP

SATA1RXN SATA1RXP SATA1TXN

SATA1TXP

SATA2RXN SATA2RXP SATA2TXN

SATA2TXP

SATA3RXN SATA3RXP SATA3TXN

SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATALED#

C38

LPC_AD0

A38

LPC_AD1

B37

LPC_AD2

C37

LPC_AD3

D36

LPC_FRAME#

E36 K36

PCH_GPIO23

V5

SERIRQ

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11

Y10

SATA_COMP

AB12

AB13

SATA3_COMP

AH1

RBIAS_SATA3

P3

PCH_SATALED#

V14

PCH_GPIO21

P1

PCH_GPIO19

2012/4/6 2013/4/6

LPC_AD0 <30, 32> LPC_AD1 <30, 32> LPC_AD2 <30, 32> LPC_AD3 <30, 32>

LPC_FRAME# <30,32>

PCH_GPIO23 <18>

SERIRQ <30 ,32>

SATA_PRX_DTX_N0 <29 > SATA_PRX_DTX_P0 <29> SATA_PTX_DRX_N0 <29 > SATA_PTX_DRX_P0 <29>

SATA_PRX_DTX_N1 <29 > SATA_PRX_DTX_P1 <29> SATA_PTX_DRX_N1 <29 > SATA_PTX_DRX_P1 <29>

+1.05VS_PCH

R389

37.4_0402_1%

1 2

+1.05VS_PCH

R388

49.9_0402_1%

1 2

R650 750_0402_1%R650 750_0402_1%

Compal Secret Data

Deciphered Date

No use PH 10K +3VS

GPIO19 has internal Pull up

D

CRB:10K ohm

SERIRQ

PCH_SATALED#

PCH_GPIO21

Check List 1.0:8.2K ohm

R403 10K_0402_5%R403 10K_0402_5%

R662 10K_0402_5%R662 10K_0402_5%

+3VS

12

R687

10K_0402_5%

R688

@R688

@

10K_0402_5%

1 2

PCH_GPIO19

Switchable

*

12

Switchable Graph

Non SG

+3VS

R674

4.7K_0402_5%

E

+3VS

GPIO21

0 1

12

Debug Port DG 1.2 PH 4.7K +3VS

Boot BIOS Strap

Boot BIOS

GPIO51

LPC

Reserved

-

SPI

*

Compal Electronics, Inc.

Title

Size Do cument Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PCH (1/8) SATA,HDA,SPI, LPC, XDP

Q3ZMC M/B LA-8481P Schematic

GPIO19 0 0 0 1 1 1

E

1 0

1.0

13 51Thursday, April 12, 2012

1.0

A

PCIE_PRX_DTX_N1<22>

Card Reader

Mini Card 1 On Board WLAN

1 1

Thunderbolt

2 2

Mini Card 1 (On Board WLAN)

PCIE_PRX_DTX_P1<22> PCIE_PTX_C_DRX_N1<22> PCIE_PTX_C_DRX_P1<22>

PCIE_PRX_DTX_N2<28>

PCIE_PRX_DTX_P2<28> PCIE_PTX_C_DRX_N2<28> PCIE_PTX_C_DRX_P2<28>

PCIE_PRX_DTX_N5<24>

PCIE_PRX_DTX_P5<24> PCIE_PTX_C_DRX_N5<24> PCIE_PTX_C_DRX_P5<24>

PCIE_PRX_DTX_N6<24>

PCIE_PRX_DTX_P6<24> PCIE_PTX_C_DRX_N6<24> PCIE_PTX_C_DRX_P6<24>

PCIE_PRX_DTX_N7<24>

PCIE_PRX_DTX_P7<24> PCIE_PTX_C_DRX_N7<24> PCIE_PTX_C_DRX_P7<24>

PCIE_PRX_DTX_N8<24>

PCIE_PRX_DTX_P8<24> PCIE_PTX_C_DRX_N8<24> PCIE_PTX_C_DRX_P8<24>

No use PH 10K +3VALW

CLK_PCIE_MINI1#<28> CLK_PCIE_MINI1<28>

MINI1_CLKREQ#<28>

1 2

C617 0.1U_0201_10V6KC617 0.1U_0201_10V6K

1 2

C678 0.1U_0201_10V6KC678 0.1U_0201_10V6K

1 2

C573 0.1U_0201_10V6KC573 0.1U_0201_10V6K

1 2

C572 0.1U_0201_10V6KC572 0.1U_0201_10V6K

1 2

C681 0.1U_0201_10V6KC681 0.1U_0201_10V6K

1 2

C682 0.1U_0201_10V6KC682 0.1U_0201_10V6K

1 2

C684 0.1U_0201_10V6KC684 0.1U_0201_10V6K

1 2

C683 0.1U_0201_10V6KC683 0.1U_0201_10V6K

1 2

C686 0.1U_0201_10V6KC686 0.1U_0201_10V6K

1 2

C685 0.1U_0201_10V6KC685 0.1U_0201_10V6K

1 2

C688 0.1U_0201_10V6KC688 0.1U_0201_10V6K

1 2

C687 0.1U_0201_10V6KC687 0.1U_0201_10V6K

No use PH 10K +3VS

TB_SMB_DA_GPIO6<24>

No use PH 10K +3VS

No use PH 10K +3VALW

Card Reader

3 3

CLK_PCIE_CARD#<22> CLK_PCIE_CARD<22>

CARD_CLKREQ#<22>

No use PH 10K +3VALW

CLK_TB_REFCLK#<24>

CLK_TB_REFCLK<24>

TB_CLKREQ#<24>

AK14:CLKOUT_ITPXDP_N AK13:CLKOUT_ITPXDP_P

No use PH 10K +3VALW

+3VS

R424 10K_0402_5%R424 10K_0402_5%

R686 10K_0402_5%R686 10K_0402_5%

+VCCSUS3_3

4 4

R652 10K_0402_5%R652 10K_0402_5%

R399 10K_0402_5%R399 10K_0402_5%

R684 10K_0402_5%R684 10K_0402_5%

R410 10K_0402_5%R410 10K_0402_5%

R400 10K_0402_5%R400 10K_0402_5%

R414 10K_0402_5%R414 10K_0402_5%

R425 10K_0402_5%R425 10K_0402_5%

12

A

MINI1_CLKREQ#

TB_SMB_DA_GPIO6

PCH_GPIO73

LAN_CLKREQ#

CARD_CLKREQ#

MINI2_CLKREQ#

PEG_CLKREQ#

PCH_GPIO45

TB_CLKREQ#

Check List R1.0 p.37 Clock Req# pull high power source

B

PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1

PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2

PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 PCIE_PTX_DRX_N5 PCIE_PTX_DRX_P5

PCIE_PRX_DTX_N6 PCIE_PRX_DTX_P6 PCIE_PTX_DRX_N6 PCIE_PTX_DRX_P6

PCIE_PRX_DTX_N7 PCIE_PRX_DTX_P7 PCIE_PTX_DRX_N7 PCIE_PTX_DRX_P7

PCIE_PRX_DTX_N8 PCIE_PRX_DTX_P8 PCIE_PTX_DRX_N8 PCIE_PTX_DRX_P8

PCH_GPIO73

MINI1_CLKREQ#

TB_SMB_DA_GPIO6

LAN_CLKREQ#

CARD_CLKREQ#

MINI2_CLKREQ#

PEG_CLKREQ#

PCH_GPIO45

CLK_TB_REFCLK# CLK_TB_REFCLK

TB_CLKREQ#

B

U37B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GP IO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GP IO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GP IO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GP IO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GP IO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GP IO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GP IO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GP IO46

AK14

CLKOUT_BCLK0_N / CLKOUT_PCIE8N

AK13

CLKOUT_BCLK0_P / CLKOUT_PCIE8P

COUGARPOINT_FCBGA989~D

HM77@

S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO!SA00005AGI0

SMBUSController

SML1ALERT# / PC HHOT# / GPIO74

PCI-E*

CLOCKS

CLKOUT_DP_N / C LKOUT_BCLK1_N

CLKOUT_DP_P / C LKOUT_BCLK1_P

CLKIN_GND1_N CLKIN_GND1_P

C

E12

SMBALERT# / GP IO11

SMBCLK

SMBDATA

SML0ALERT# / GP IO60

SML0CLK

SML0DATA

SML1CLK / GPIO58

SML1DATA / GPIO7 5

CL_CLK1

Link

PEG_A_CLKRQ# / GPIO47

CLKIN_SATA_N / CKS SCD_N CLKIN_SATA_P / CKS SCD_P

FLEX CLOCKS

CL_DATA1

CL_RST1#

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_DMI2_N CLKIN_DMI2_P

CLKIN_DOT_96N CLKIN_DOT_96P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / G PIO64

CLKOUTFLEX1 / G PIO65

CLKOUTFLEX2 / G PIO66

CLKOUTFLEX3 / G PIO67

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

SMB_ALERT#

H14

PCH_SMBCLK

C9

PCH_SMBDATA

A12

DRAMRST_CNTRL_PC H

C8

G12

C13

PCH_GPIO74

E14

PCH_SML1CLK

M16

PCH_SML1DATA

M7

T11

P10

M10

PCH_GPIO47

AB37 AB38

AV22

CLK_CPU_DMI#

AU22

CLK_CPU_DMI

AM12

CLK_CPU_DPLL#

AM13

CLK_CPU_DPLL

BF18

CLK_BUF_CPU_DMI#

BE18

CLK_BUF_CPU_DMI

BJ30

CLKIN_GND1#

BG30

CLKIN_GND1

G24

CLK_BUF_DREF_96M#

E24

CLK_BUF_DREF_96M

AK7

CLK_BUF_PCIE_SATA#

AK5

CLK_BUF_PCIE_SATA

K45

CLK_BUF_ICH_14M

H45

CLK_PCI_LPBACK

V47

XTAL25_IN

V49

XTAL25_OUT

Y47

XCLK_RCOMP

K43

CLK_FLEX0

F47

CLK_FLEX1

H47

CLK_FLEX2

K49

DGPU_PRSNT#

2012/4/6 2013/4/6

SMB_ALERT# <33>

DRAMRST_CNTRL_PC H <11,12,6>

S3 reduse

CLK_CPU_DMI# <5> CLK_CPU_DMI <5>

CLK_CPU_DPLL# <5> CLK_CPU_DPLL <5>

1 2

R357 10K_0402_5%R357 10K_0402_5%

1 2

R358 10K_0402_5%R358 10K_0402_5%

1 2

R330 10K_0402_5%R330 10K_0402_5%

1 2

R331 10K_0402_5%R331 10K_0402_5%

1 2

R346 10K_0402_5%R346 10K_0402_5%

1 2

R345 10K_0402_5%R345 10K_0402_5%

1 2

R387 10K_0402_5%R387 10K_0402_5%

1 2

R393 10K_0402_5%R393 10K_0402_5%

1 2

R292 10K_0402_5%R292 10K_0402_5%

R293 33_0402_5%

@

Reserve for EMI please close to PCH

R289

90.9_0402_1%

1 2

@

PAD

T52

@

PAD

T53

@

PAD

T21

Compal Secret Data

Deciphered Date

D

No use PH 10K +3VALW

PH 2.2K +3VALW

No use PH 10K +3VALWS3 reduse

No use PH 10K +3VALW

PH 2.2K +3VALW

No use PH 10K +3VALW

120MHz for eDP.

12

1 2

C421 22P_0402_50V8J

@

+1.05VS_PCH

UMA@

DGPU_PRSNT#

@

DIS,Optimus

UMA

D

Pull down 10K ohm for using internal Clock

+3VS

12

R610

R610 10K_0402_5%

10K_0402_5%

12

R628

R628 10K_0402_5%

10K_0402_5%

GPIO67

DGPU_PRSNT#

0 1

E

SMB_ALERT#

PCH_SMBCLK

PCH_SMBDATA

DRAMRST_CNTRL_PC H

PCH_GPIO74

PCH_SML1CLK

PCH_SML1DATA

PCH_GPIO47

+3VS

3 4

Q27A

Q27A DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

PCH_SMBCLK

+3VS

PCH_SML1DATA

PCH_SML1CLK

CLK_PCI_LPBACK <17>

3 4

Q22A

Q22A DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

XTAL25_IN

XTAL25_OUT

C744

8.2P_0402_50V8D

Title

Size Document Number Rev

Custom

Q3ZMC M/B LA-8481P Schematic

Date: Sheet of

1 2

R383 10K_0402_5%R383 10K_0402_5%

1 2

R668 2.2K_0402_5%R668 2.2K_0402_5%

1 2

R664 2.2K_0402_5%R664 2.2K_0402_5%

1 2

R648 1K_0402_5%R648 1K_0402_5%

1 2

R647 10K_0402_5%R647 10K_0402_5%

1 2

R375 2.2K_0402_5%R375 2.2K_0402_5%

1 2

R369 2.2K_0402_5%R369 2.2K_0402_5%

1 2

R683 10K_0402_5%R683 10K_0402_5%

For TP

R427

4.7K_0402_5%

5

1 2

SGD

2

G

6 1

S

D

S

D

Q27B

Q27B DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

5

SGD

2

G

6 1

S

D

S

D

Q22B

Q22B DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

1

2

Compal Electronics, Inc.

PCH (2/8) PCIE, SMBUS, CLK

+3VS

D_CK_SDATAPCH_SMBDATA

R415

4.7K_0402_5%

1 2

+3VS

D_CK_SCLK

Pull up at EC side. For DDR,EC

EC_SMB_DA2

EC_SMB_CK2

1 2

R611 1M_0402_5%R611 1M_0402_5%

25MHZ_10PF_7V25000014

3

GND

4

Y1

E

+VCCSUS3_3

D_CK_SDATA <33>

D_CK_SCLK <33>

EC_SMB_DA2 <11,24,32>

EC_SMB_CK2 <11,24,32>

1

GND

2

14 51Thursday, April 12, 2012

1

C745

8.2P_0402_50V8D

2

1.0

A

+VCCSUS3_3

R378 10K_0402_5%R378 10K_0402_5%

R402 10K_0402_5%R402 10K_0402_5%

R649 10K_0402_5%R649 10K_0402_5%

R373 200_0402_5%R373 200_0402_5%

+3VALW_PCH

1 1

R341 10K_0402_5%@R341 10K_0402_5%@

R634 10K_0402_5%R634 10K_0402_5%

2 2

ACPRESENT<32>

12

not support AMT APWROK can mux with PWROK (check list1.0 P.40)

R456 0_0402_ 5%R456 0_0402_5%

PCH_GPIO30

PCH_GPIO72

RI#

PM_DRAM_PWR GD

PCH_ACIN

PCH_RSMRST#

not support Deep S4,S5 mux with SUS_PWR_DN_ACK

1 2

PCH_ACIN

SUSACK#<32>

XDP_DBRESET#<5>

PM_DRAM_PWR GD<5>

PCH_RSMRST#<32>

SUSWARN#<32>

PBTN_OUT#<32>

No use PH 10K +3VALW

Ring Indicator CRB1.0 PH 10K +3VALW

DMI_CTX_PRX_N0<4> DMI_CTX_PRX_N1<4> DMI_CTX_PRX_N2<4> DMI_CTX_PRX_N3<4>

DMI_CTX_PRX_P0<4> DMI_CTX_PRX_P1<4> DMI_CTX_PRX_P2<4> DMI_CTX_PRX_P3<4>

DMI_CRX_PTX_N0<4> DMI_CRX_PTX_N1<4> DMI_CRX_PTX_N2<4> DMI_CRX_PTX_N3<4>

DMI_CRX_PTX_P0<4> DMI_CRX_PTX_P1<4> DMI_CRX_PTX_P2<4> DMI_CRX_PTX_P3<4>

+1.05VS_PCH

PCH_PWROK

ACIN<32,35,38,39>

B

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

1 2

R625 49.9_0402_1%R625 49.9_0402_1%

1 2

R632 750_0402_1%R632 750_0402_1%

4mil width and place within 500mil of the PCH

1 2

SUSACK#_R

@

R372 0_0402_5%

1 2

XDP_DBRESET#_R

@

R661 0_0402_5%

R382 0_0402_5%

R412 0_0402_5%

D19 RB751V-40_S OD323-2

1 2

@

1 2

@

SYS_PWROK

PCH_PWROK_R

PM_DRAM_PWR GD

PCH_RSMRST#

PCH_GPIO30

PBTN_OUT#

21

PCH_ACIN

DMI_IRCOMP

DMI2RBIAS

PCH_GPIO72

RI#

U37C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN# / SUS_PW R_DN_ACK / GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

COUGARPOINT_FCBGA989~D

HM77@

S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO!SA00005AGI0

C

DMI

FDI

DMI

FDI

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

SLP_LAN# / GPIO29

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16

AV12

BC10

AV14

BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWODVREN

PCH_PCIE_WAKE#

CLKRUN#

SUS_STAT#

SUSCLK_R

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

SLP_A#

SLP_SUS#

H_PM_SYNC

PCH_GPIO29

是是是是是是是是是是是是是是是是

1 2

PCH_RSMRST#

S3@

R426 0_0402_5%

1 2

DPWROK

@

R421 0_0402_5%

T15 PAD

@

R973

@R973

@

1 2

0_0402_5%

T51 PAD

@

NC

D

FDI_CTX_PRX_N0 <4> FDI_CTX_PRX_N1 <4> FDI_CTX_PRX_N2 <4> FDI_CTX_PRX_N3 <4> FDI_CTX_PRX_N4 <4> FDI_CTX_PRX_N5 <4> FDI_CTX_PRX_N6 <4> FDI_CTX_PRX_N7 <4>

FDI_CTX_PRX_P0 <4> FDI_CTX_PRX_P1 <4> FDI_CTX_PRX_P2 <4> FDI_CTX_PRX_P3 <4> FDI_CTX_PRX_P4 <4> FDI_CTX_PRX_P5 <4> FDI_CTX_PRX_P6 <4> FDI_CTX_PRX_P7 <4>

FDI_INT <4>

FDI_FSYNC0 <4>

FDI_FSYNC1 <4>

FDI_LSYNC0 <4>

FDI_LSYNC1 <4>

DPWROK <32>

PCH_PCIE_WAKE# <24,28>

CLKRUN# <3 0>

No use PH 10K +3VS

PM_SLP_S5# <32>

PM_SLP_S4# <32>

PM_SLP_S3# <32>

SLP_SUS# <32>

H_PM_SYNC <5>

No use PH 10K +3VALW

SUSCLK <32>

Can be left NC when IAMT is not support on the platfrom

not support Deep S4,S5 can NC PCH EDS1.2 P.74

E

+RTCVCC

1 2

12

R463

100K_0402_5%

+VCCSUS3_3

+3VS

DSWODVREN

*

not support Deep S4,S5 DPWROK mux with RSMRST# check list1.0 P.42

PCH_PCIE_WAKE#

PCH_GPIO29

CLKRUN#

R361 330K_0402_5%R361 330K_0402_5%

R360 330K_0402_5%@R360 330K_0402_5%@

DSWODVREN - On Die DSW VR Enable

H

：：：：

Enable internal DSW +1.05VS

L

：：：：

Disable

Must always PH at +RTCVCC

CRB=>1k ohm Follow Check Li st R1.5

R656 10K_0402_5%R656 10K_0402_5%

R395 10K_0402_5%@R395 10K_0402_5%@

R653 8.2K_0402_5%R653 8.2K_0402_5%

DPWROK

3 3

tell PCH all power ok but cpu core

PCH_PWROK<32>

4 4

A

VGATE<43>

12

R680

R680 10K_0402_5%

10K_0402_5%

VGATE VGATE

1

C790

C790 100P_0402_50V8J

100P_0402_50V8J

2

+3VS

5

U39

2

B

1

A

3

ALL power OK

P

4

SYS_PWROK

Y

G

MC74VHC1G08DFT2G_SC70-5

1

C791

C791 100P_0201_25V8J

100P_0201_25V8J

2

12

R681

R681 10K_0402_5%

10K_0402_5%

B

1

C603

.047U_0402_16V7K

2

@

SYS_PWROK <5>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

SYS_PWROK

1

C789

C789 100P_0402_50V8J

100P_0402_50V8J

2

Compal Secret Data

2012/4/6 2013/4/6

C

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PCH (3/8) DMI,FDI,PM

Q3ZMC M/B LA-8481P Schematic

E

15 51Thursday, April 12, 2012

1.0

A

B

C

D

E

UMA Panel Backlight ON/OFF

ENBKL<32>

R612 0_0402_5%@R612 0_0402_5%@

12

PD 100K at EC side

1 1

2 2

3 3

IGPU_BKLT_ENENBKL

U37D

PCH_ENVDD<22 >

DPST_PWM<22>

IGPU_BKLT_EN

Delete LVDS function

LVDS disable: DATA/Clock/Control can NC VCC_TX_LVDS,VCCA_LVDS connected to GND

CRT disable: DATA/Clock/Control can NC DAC_IREF still need PD VCCADAC connected to +3VS

CRT_IREF

For CRT diable =>Change 1K 0.5% to 5%

1K_0402_5%

R307

12

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

COUGARPOINT_FCBGA989~D

HM77@

SDVO_TVCLKINN

SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

CRT

S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO!SA00005AGI0

DDPD_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

SDVO_CTRLDATA strap pull high at level shift page

P38

SDVO_SCLK

M39

SDVO_SDATA

AT49 AT47 AT40

PCH_DPB_HPD

AV42

PCH_DPB_N0

AV40

PCH_DPB_P0

AV45

PCH_DPB_N1

AV46

PCH_DPB_P1

AU48

PCH_DPB_N2

AU47

PCH_DPB_P2

AV47

PCH_DPB_N3

AV49

PCH_DPB_P3

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43

PCH_DPD_CLK

M36

PCH_DPD_DAT

AT45

PCH_DPD_AUXN

AT43

PCH_DPD_AUXP

BH41

DPD_HPD

BB43

PCH_DPD_N0

BB45

PCH_DPD_P0

BF44

PCH_DPD_N1

BE44

PCH_DPD_P1

BF42

PCH_DPD_N2

BE42

PCH_DPD_P2

BJ42

PCH_DPD_N3

BG42

PCH_DPD_P3

SDVO_SCLK < 23> SDVO_SDATA <23>

PCH_DPB_HPD <2 3>

PCH_DPB_N0 <23> PCH_DPB_P0 <23> PCH_DPB_N1 <23> PCH_DPB_P1 <23> PCH_DPB_N2 <23> PCH_DPB_P2 <23> PCH_DPB_N3 <23> PCH_DPB_P3 <23>

PCH_DPD_CLK <2 5> PCH_DPD_DAT <25>

PCH_DPD_AUXN <24>

PCH_DPD_AUXP <24> DPD_HPD <24>

PCH_DPD_N0 <24> PCH_DPD_P0 <24> PCH_DPD_N1 <24> PCH_DPD_P1 <24> PCH_DPD_N2 <24> PCH_DPD_P2 <24> PCH_DPD_N3 <24> PCH_DPD_P3 <24>

HDMI D2

HDMI D1

HDMI D0

HDMI CLK

Thunderbolt

+3VS

1 2

R252 2.2K_0402_5 %R252 2.2K_0402_5 %

1 2

R254 2.2K_0402_5 %R254 2.2K_0402_5 %

4 4

Security Classification

2012/4/6 2013/4/6

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

2012/4/6 2013/4/6

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PCH (4/9) LVDS,CRT,DP,HDMI

Q3ZMC M/B LA-8481P Schematic

PCH_DPD_CLK

PCH_DPD_DAT

1.0

16 51Thursday, April 12 , 2012

E