Compal LA-8481P Schematics

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B

C

D

E

Compal Confidential

Model Name : Q3ZMC

1 1

File Name : LA-8481P

Compal Confidential

2 2

Q3ZMC UMA M/B Schematics Document

Intel Ivy/Sandy Bridge SFF BGA 1023p Processor /Panther Point 989p PCH / DDR3L Memory Down *8

3 3

2012-04-11

REV:1.0(MP SMT)

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

C

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

Q3ZMC M/B LA-8481P Schematic

E

1 51Thursday, April 12, 2012

1.0

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B

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D

E

PCB

ZZZ1

LA-8481P

DAZ0NS00100

1 1

Fan Control

page 34

eDP Conn.

page 22

eDP

120MHz

Intel

Ivy Bridge ULV

Processor

Memory BUS(DDR3L)

Two Channel

1.35V DDR3L 1333Mhz

BGA1023

page 4~10

FDI x8

Thunderbolt

page 24~27

2 2

HDMI Conn.

page 23

TMDS

DP

100MHz

2.7GT/s

Intel

Panther Point-M

DMI x4

100MHz

1GB/s x4

PCH

100MHz

989pin BGA

page 13~21

Thunderbolt

port 5~8

WLAN

port 2

PCI-Express x 8 (PCIE2.0 5GT/s)

port 1

Card reader

SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S)

USB 3.0 conn x2

USB3.0 port 1,2 USB2.0 port 0,1

USBx14

HD Audio

SPI

LPC

page 31

3.3V 48MHz

3.3V 24MHz

DDR3L-ON BOARD

Debug Port

USB port 9

page 31

Camera

USB port 10

D/B

page 11,12

Bluetooth

page 22

USB port 8

HDA Codec

ALC271X-VB6/ALC281X

page 28

mSATA (Reserve)

USB port 12

page 32

page 28

page 24~27

page 28

page 22

mSATA

port 0

TPM

page 30

SPI ROM x2

page 13

Int. Speaker x 2 Phone Jack x 1

page 32

Int. DMIC x 1

page 32

LPC BUS

3 3

page 29

33MHz

ENE KB930/KB9012

RTC CKT.

page 13

Power On/Off CKT.

page 33

DC/DC Interface CKT.

page 35

4 4

Power Circuit DC/DC

page 36~45

A

LS-8481P Audio/B

page 32

LS-8482P Card Reader/B

page 22

LS-8483P LED/B

page 32

LS-8484P Battery/B

B

Touch Pad

page 33

EC ROM x1 @ for KB930

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

page 33

Issued Date

C

page 33

Int.KBD

page 33

Compal Secret Data

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Block Diagrams

Q3ZMC M/B LA-8481P Schematic

E

2 51Thursday, April 12, 2012

1.0

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B

C

D

E

Voltage Rails

Power Plane Description

VIN

BATT+ Battery power supply (12.6V) N/A N/A N/A

B+

+VSB +VSBP to +VSB always on power rail for sequence control ON ON*

1 1

+CPU_CORE

+VGFX_CORE Core voltage for UMA graphic ON OFF OFF

+1.05VS_VTT

+1.35V

+1.35VS

+0.675VS +0.675VSP to +0.675VS switched power rail for DDR3L terminator

+1.5VS +1.5VSP to +1.5VS power rail for PCH

+1.8VS +3VALW to 1.8VS switched power rail for PCH

+3VALW +3VALWP to +3VALW always on power rail

+3VALW_PCH +3VALW to +3VALW_PCH power rail for PCH (Short Resistor) ON ON

+3VS

+5VALW

+5VS +5VALW to +5VS switched power rail OFFON OFF

2 2

+RTCVCC RTC power

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU

+1.05VS_VTTP to +1.05VS_VTT switched power rail for CPU

+1.35VP to +1.35V power rail for DDR3L

+1.35V to +1.35VS switched power rail

+3VALW to +3VS power rail

+5VALWP to +5VALW always on power rail

S1 S3 S5

N/A N/A N/A

ON

ON OFF OFF

ON OFF OFF+1.05VS_PCH +1.05VS_VTT to +1.05VS_PCH power for PCH

ON ON OFF

ON OFF OFF

ON

N/AN/AN/A

OFF

ON ON*

ON*

OFF

ON ON*

ONON

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

Board ID / SKU ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0 1 2 3 4 5 6 7 NC

SIGNAL

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

LOW

HIGH

LOW LOW LOW LOW

100K +/- 5%Ra/Rc/Re

Rb / Rd / Rf V min

0

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

LOWLOWLOW

ON

HIGHHIGHHIGH

HIGH

V typ

AD_BID

ON

OFF

ON

OFF

V

AD_BID

0 V 0 V

0.503 V

0.819 V

1.185 V 1.264 V

2.200 V

3.300 V

ON ON

ON

OFF

max

0.538 V

0.875 V

2.341 V

3.300 V

LOW

OFF

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

EC SM Bus1 address

Device

Smart Battery

Address Address

0001 011X b

EC SM Bus2 address

Device

PCH SM Bus address

Device Address

ChannelA

ChannelB

3 3

A0A41010 000X

1010 010X

BOARD ID Table

Board ID

0.1,

0 1 2 3 4

0.2

0.3 DVT:unknown MCU+MKS Motor,With TB IC

0.4 PVT1:PADAUK MCU+MKS Motor,Without TB IC

0.4 PVT2:PADAUK MCU+MKS Motor,With TB IC

1.0

5 6 7

PCB Revision

Unpop

UMA UMA@ CPU PCH DDR3 DDR3L On Board DRAM 128bit RAM 128@ eDP LVDS

BTO Option Table

BTO Item BOM Structure

@ CONN@Connector

IVB@ HM77@ DDR3@ DDR3L@ X76@

eDP@ LVDS@

USB Port Table

BOM Config 4319HNBOL01:UMA@/DDR3L@/eDP@/USB3.0@/9012@/TB@/IVB@/HM77@/DS3@/TXM@/TPM@/128@/

4319HNBOL02:UMA@/DDR3L@/eDP@/USB3.0@/9012@/TB@/IVB@/HM77@/DS3@/TXM@/TPM@

4 4

A

B

USB 2.0 USB 1.1 Port

UHCI0

UHCI1

EHCI1

UHCI2

UHCI3

UHCI4

EHCI2

UHCI5

UHCI6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

0 1 2 3 4 5 6 7 8

9 10 11 12 13

2012/4/6 2013/4/6

2 External USB Port

USB port (Rear side 3.0) USB port (Rear side 3.0)

Debug Port Camera

mSATA(Reserve) BlueTooth

Compal Secret Data

Deciphered Date

D

USB3.0 Conn USB3.0@

USB2.0@USB2.0 Conn

Thunderbolt

KB930 KB9012

Normal S3 Deep S3

TPM+TCM TPM TCM

Custom

Date: Sheet of

TB@

930@ 9012@

S3@ DS3@

TXM@ TPM@ TCM@

Compal Electronics, Inc.

Title

Size Document Number Rev

Compal Electronics, Inc.

Notes List

Q3ZMC M/B LA-8481P Schematic

1.0

3 51Thursday, April 12, 2012

E

3 51Thursday, April 12, 2012

1.0

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E

+1.05VS_ VTT

12

R532

24.9_040 2_1%

UCPU1A

1 1

DMI_CRX_P TX_N0<15> DMI_CRX_P TX_N1<15> DMI_CRX_P TX_N2<15> DMI_CRX_P TX_N3<15>

DMI_CRX_P TX_P0<15> DMI_CRX_P TX_P1<15> DMI_CRX_P TX_P2<15> DMI_CRX_P TX_P3<15>

DMI_CTX_P RX_N0<15> DMI_CTX_P RX_N1<15> DMI_CTX_P RX_N2<15> DMI_CTX_P RX_N3<15>

DMI_CTX_P RX_P0<15> DMI_CTX_P RX_P1<15> DMI_CTX_P RX_P2<15> DMI_CTX_P RX_P3<15>

FDI_CTX_P RX_N0<15> FDI_CTX_P RX_N1<15> FDI_CTX_P RX_N2<15>

2 2

eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms should not be left floating ,even if disable eDP function...

+1.05VS_ VTT

12

R118

24.9_040 2_1%

W=4mil,S=15mil,L=500mil

3 3

W=12mil,S=15mil,L=500mil

Add eDP circuit

+1.05VS_ VTT

12

R809

R809 1K_0402 _5%eDP@

1K_0402 _5%eDP@

EDP_HPD #<22>

EDP_HPD #

FDI_CTX_P RX_N3<15> FDI_CTX_P RX_N4<15> FDI_CTX_P RX_N5<15> FDI_CTX_P RX_N6<15> FDI_CTX_P RX_N7<15>

FDI_CTX_P RX_P0<15> FDI_CTX_P RX_P1<15> FDI_CTX_P RX_P2<15> FDI_CTX_P RX_P3<15> FDI_CTX_P RX_P4<15> FDI_CTX_P RX_P5<15> FDI_CTX_P RX_P6<15> FDI_CTX_P RX_P7<15>

FDI_FSYNC0<15> FDI_FSYNC1<15>

FDI_INT<15>

FDI_LSYNC0<15> FDI_LSYNC1<15>

EDP_COM P

EDP_HPD #

EDP_AUX N<22> EDP_AUX P<22>

EDP_TXN 0<22> EDP_TXN 1<22>

EDP_TXP 0<22> EDP_TXP 1<22>

UCPU1A

M2

DMI_RX#[0]

P6

DMI_RX#[1]

P1

DMI_RX#[2]

P10

DMI_RX#[3]

N3

DMI_RX[0]

P7

DMI_RX[1]

P3

DMI_RX[2]

P11

DMI_RX[3]

K1

DMI_TX#[0]

M8

DMI_TX#[1]

N4

DMI_TX#[2]

R2

DMI_TX#[3]

K3

DMI_TX[0]

M7

DMI_TX[1]

P4

DMI_TX[2]

T3

DMI_TX[3]

U7

FDI0_TX#[0]

W11

FDI0_TX#[1]

W1

FDI0_TX#[2]

AA6

FDI0_TX#[3]

W6

FDI1_TX#[0]

V4

FDI1_TX#[1]

Y2

FDI1_TX#[2]

AC9

FDI1_TX#[3]

U6

FDI0_TX[0]

W10

FDI0_TX[1]

W3

FDI0_TX[2]

AA7

FDI0_TX[3]

W7

FDI1_TX[0]

T4

FDI1_TX[1]

AA3

FDI1_TX[2]

AC8

FDI1_TX[3]

AA11

FDI0_FSYNC

AC12

FDI1_FSYNC

U11

FDI_INT

AA10

FDI0_LSYNC

AG8

FDI1_LSYNC

AF3

eDP_COMPIO

AD2

eDP_ICOMPO

AG11

eDP_HPD#

AG4

eDP_AUX#

AF4

eDP_AUX

AC3

eDP_TX#[0]

AC4

eDP_TX#[1]

AE11

eDP_TX#[2]

AE7

eDP_TX#[3]

AC1

eDP_TX[0]

AA4

eDP_TX[1]

AE10

eDP_TX[2]

AE6

eDP_TX[3]

IVY-BRIDGE_BGA1 023

IVB@

ULV type P/N:

1.SA00005B000:S IC AV8063801057400 QBP7 K0 1.7G BGA

2.SA00005AZ30:S IC AV8063801057401 QBTP K0 1.5G BGA

DMI Intel(R) FDI

eDP

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[10]

PEG_RX[11]

PEG_RX[12]

PEG_RX[13]

PEG_RX[14]

PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8]

PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PCI EXPRESS -- GRAPHICS

PEG_TX[10]

PEG_TX[11]

PEG_TX[12]

PEG_TX[13]

PEG_TX[14]

PEG_TX[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9]

PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9]

G3 G1 G4

H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7

K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6

G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4

F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4

PEG_COM P

G3,W=4mil,S=15mil,L=500mil G1,W=12mil,S=15mil,L=500mil G4,W=4mil,S=15mil,L=500mil

UMA only=>PEG NC

PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms

PEG_ICOMPO signals should be routed with - max length = 500 milstypical impedance = 14.5 mohms

4 4

Security Class ification

2012/4/6 2013/4/6

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/4/6 2013/4/6

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(1/7) DMI,FDI,PEG

Q3ZMC M/B LA-8481P Schematic

4 51Thursday, April 12, 2012

E

1.0

A

1 1

2 2

PCH->CPU UNCOREPWRGOOD: SM_DRAMPWROK:DRAM power ok RESET#:

都都都都ok後後後後後後後後

CPU

非非非非

CORE

做做做做

reset

外外外外外外外外外外外外

OK

PROC_SELECT# Future platforms,PH VCPLL and connect to PCH DF_TVS

Follow DG 1.2 & CRB1.0 Checklist1.0 P.64 Processor Graphis Disable Guide

C784 0.1U_0402_10V7K

R223 10K_0402_5%R223 10K_0402_5%

12

@

12

Follow DG 1.2 & CRB1.0

Buffered reset to CPU

3 3

PLT_RST#<17,22,24,30,32>

RESET#:

Follow DG 1.2 & CRB1.0

C101

0.1U_0402_16V4Z

SYS_PWROK<15>

4 4

PM_DRAM_PWR GD<15>

+3VS

1

NC

2

A

都都都都ok後後後後後後後後

+3VALW

1

2

U5

2

1

A

5

P

G

3

B

A

H_CPUPWRGD

1

2

U15

Y

SN74LVC1G07DCKR_SC70-5

CPU

5

P

Y

G

MC74VHC1G09DFT2G_SC70-5

3

Processor Pullups follow CRB1.0

Use open drain MOS: +1.05VS_VTT PH pop 75ohm series resister pop 43ohm

C396

0.1U_0201_10V6K

4

BUFO_CPU_RST#

做做做做

reset

4

PM_SYS_PWRGD_BUF

SUSP<35,40>

H_PROCHOT#<32>

+1.05VS_VTT

12

R226

R226 75_0402_5%

75_0402_5%

43_0402_1%

1 2

2

SUSP

G

+1.05VS_VTT

R227

+1.35VS

12

R88

R88 200_0402_5%

200_0402_5%

12

R829

R829 39_0402_5%

39_0402_5%

@

13

D

Q74

Q74 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

@

S

R220 62_0402_5%R220 62_0402_5%

BUF_CPU_RST#

12

@

R225

R225 0_0402_5%

0_0402_5%

Use open drain MOS: +1.35VS PH pop 200ohm series resister pop 130ohm

1 2

R97 130_0402_5%R97 1 30_0402_5%

偵偵偵偵偵偵偵偵

XBOX

H_CPUPWRGD<18>

B

CPU

有有有有有有有有有有有有有有有有

三三三三三三三三三三三三三三三三

12

H_THRMTRIP#<18>

UNCOREPWRGOOD:

PM_DRAM_PWR GD_R

B

H_SNB_IVB#<17>

T1 PAD@T1 PAD

H_PECI<18,32>

R216

56_0402_5%

1 2

H_PM_SYNC<15>

R80

@R80

@

0_0402_5%

1 2

除除除除除除除除

PM_DRAM_PWR GD_R

SM_DRAMPWROK:DRAM power ok

BUF_CPU_RST#

@

H_CATERR#

H_PECI

H_PROCHOT#_RH_PROCHOT#

H_CPUPWRGD_R

CPU_CORE

PM_DRAM_PWR GD

C787

100P_0201_25V8J

以以以以以以以以以以以以以以以以

1

2

UCPU1B

F49

PROC_SELECT#

C57

PROC_DETECT#

C49

CATERR#

A48

PECI

C45

PROCHOT#

D45

THERMTRIP#

C48

PM_SYNC

B46

UNCOREPWRGOOD

OK

BE45

SM_DRAMPWR OK

D44

RESET#

IVY-BRIDGE_BGA1023

IVB@

C

J3

BCLK

MISC THERMAL PWR MANAGEMENT

DPLL_REF_CLK

DPLL_REF_CLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

DDR3

MISC

DDR3

MISC

JTAG & BPM

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/4/6 2013/4/6

H2

BCLK#

AG3 AG1

AT30

BF44 BE43 BG43

N53

PRDY#

N55

PREQ#

L56

TCK

L55

TMS

J58

TRST#

M60

TDI

L59

TDO

K58

DBR#

G58

BPM#[0]

E55

BPM#[1]

E59

BPM#[2]

G55

BPM#[3]

G59

BPM#[4]

H60

BPM#[5]

J59

BPM#[6]

J61

BPM#[7]

Compal Secret Data

CLK_CPU_DPLL CLK_CPU_DPLL#

SM_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

DDR3 Compensation Signals Trace:10mil ,Spacing:13mil, Max.Length:500mil

XDP_TCK XDP_TMS XDP_TRST#

XDP_TDI XDP_TDO

XDP_DBRESET#

Deciphered Date

D

CLK_CPU_DMI <14> CLK_CPU_DMI# <14>

CLK_CPU_DPLL <1 4> CLK_CPU_DPLL# < 14>

SM_DRAMRST# <6>

R149 140_0402_1%R149 140_0402_1% R486 25.5_0402_1%R486 25.5_0402_1% R484 200_0402_1%R484 200_0402_1%

12 12 12

T2PAD@ T2PAD@ T3PAD@ T3PAD@ T4PAD@ T4PAD@

T5PAD@ T5PAD@ T6PAD@ T6PAD@

1 2

C102

C102 100P_0201_25V8J

100P_0201_25V8J

XDP_DBRESET# <15>

For EMI

D

Custom

Date: Sheet of

E

+1.05VS_VTT

CLK_CPU_DPLL#

CLK_CPU_DPLL

DIS only SKU or UMA eDP disable DPLL_REF_SSCLK PD 1K_5% to GND DPLL_REF_SSCLK# PH 1K_5% to +1.05VS_VTT

XDP_DBRESET#

CRB1.0 PH 1K +3VS Check list 1.0 PH 5K +3VS Check list 1.2 PH 10K +3VS Debug port DG1.1-1.2 50~5K ohm

Title

Size Document Number Rev

Q3ZMC M/B LA-8481P Schematic

R116 1K_0402_5%@R116 1K_0402_5%@

R117 1K_0402_5%@R117 1K_0402_5%@

R569 1K_0402_5%R569 1K_0402_5%

Compal Electronics, Inc.

PROCESSOR(2/7) PM,XDP,CLK

12

+3VS

12

5 51Thursday, April 12, 2012

E

5 51Thursday, April 12, 2012

1.0

A

UCPU1C

DDR_A_D[0..63]<11>

1 1

2 2

3 3

DDR_A_BS0<11> DDR_A_BS1<11> DDR_A_BS2<11>

DDR_A_CAS#<11> DDR_A_RAS#<11> DDR_A_WE#<11>

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

UCPU1C

AG6

SA_DQ[0]

AJ6

SA_DQ[1]

AP11

SA_DQ[2]

AL6

SA_DQ[3]

AJ10

SA_DQ[4]

AJ8

SA_DQ[5]

AL8

SA_DQ[6]

AL7

SA_DQ[7]

AR11

SA_DQ[8]

AP6

SA_DQ[9]

AU6

SA_DQ[10]

AV9

SA_DQ[11]

AR6

SA_DQ[12]

AP8

SA_DQ[13]

AT13

SA_DQ[14]

AU13

SA_DQ[15]

BC7

SA_DQ[16]

BB7

SA_DQ[17]

BA13

SA_DQ[18]

BB11

SA_DQ[19]

BA7

SA_DQ[20]

BA9

SA_DQ[21]

BB9

SA_DQ[22]

AY13

SA_DQ[23]

AV14

SA_DQ[24]

AR14

SA_DQ[25]

AY17

SA_DQ[26]

AR19

SA_DQ[27]

BA14

SA_DQ[28]

AU14

SA_DQ[29]

BB14

SA_DQ[30]

BB17

SA_DQ[31]

BA45

SA_DQ[32]

AR43

SA_DQ[33]

AW48

SA_DQ[34]

BC48

SA_DQ[35]

BC45

SA_DQ[36]

AR45

SA_DQ[37]

AT48

SA_DQ[38]

AY48

SA_DQ[39]

BA49

SA_DQ[40]

AV49

SA_DQ[41]

BB51

SA_DQ[42]

AY53

SA_DQ[43]

BB49

SA_DQ[44]

AU49

SA_DQ[45]

BA53

SA_DQ[46]

BB55

SA_DQ[47]

BA55

SA_DQ[48]

AV56

SA_DQ[49]

AP50

SA_DQ[50]

AP53

SA_DQ[51]

AV54

SA_DQ[52]

AT54

SA_DQ[53]

AP56

SA_DQ[54]

AP52

SA_DQ[55]

AN57

SA_DQ[56]

AN53

SA_DQ[57]

AG56

SA_DQ[58]

AG53

SA_DQ[59]

AN55

SA_DQ[60]

AN52

SA_DQ[61]

AG55

SA_DQ[62]

AK56

SA_DQ[63]

BD37

SA_BS[0]

BF36

SA_BS[1]

BA28

SA_BS[2]

BE39

SA_CAS#

BD39

SA_RAS#

AT41

SA_WE#

IVY-BRIDGE_BGA1023

IVB@

Follow CRB1.0

R78

0_0402_5%

1 2

@

1 2

C78

@

D

S

D

S

Q6

G

BSS138-G_SOT23-3

2

1

2

13

DIMM_DRAMRST#_RSM_DRAMRST#

@

R416

R416 0_0402_5%

0_0402_5%

1 2

CPU通通DIMM做reset

SM_DRAMRST#<5>

R79

4.99K_0402_1%

4 4

DRAMRST_CNTRL_PC H<11,12,14>

DRAMRST_CNTRL_EC<32>

A

1 2

R418 0_0402_5%R418 0_0402_5%

1 2

R413 0_0402_5%DS3@R413 0_0402_5%DS3@

.047U_0402_16V7K

B

AU36

SA_CK[0]

AV36

SA_CK#[0]

AY26

SA_CKE[0]

AT40

SA_CK[1]

AU40

SA_CK#[1]

BB26

SA_CKE[1]

BB40

SA_CS#[0]

BC41

SA_CS#[1]

AY40

SA_ODT[0]

BA41

SA_ODT[1]

AL11

SA_DQS#[0]

AR8

SA_DQS#[1]

AV11

SA_DQS#[2]

AT17

SA_DQS#[3]

AV45

SA_DQS#[4]

AY51

SA_DQS#[5]

AT55

SA_DQS#[6]

AK55

SA_DQS#[7]

AJ11

SA_DQS[0]

AR10

SA_DQS[1]

AY11

SA_DQS[2]

AU17

SA_DQS[3]

AW45

SA_DQS[4]

AV51

SA_DQS[5]

AT56

SA_DQS[6]

AK54

SA_DQS[7]

DDR SYSTEM MEMORY A

BG35

SA_MA[0]

BB34

SA_MA[1]

BE35

SA_MA[2]

BD35

SA_MA[3]

AT34

SA_MA[4]

AU34

SA_MA[5]

BB32

SA_MA[6]

AT32

SA_MA[7]

AY32

SA_MA[8]

AV32

SA_MA[9]

BE37

SA_MA[10]

BA30

SA_MA[11]

BC30

SA_MA[12]

AW41

SA_MA[13]

AY28

SA_MA[14]

AU26

SA_MA[15]

+1.35V

12

R66

1K_0402_5%

R63

R63 1K_0402_5%

1K_0402_5%

1 2

S0 DRAMRST_CNTRL_PCH hgih ,MOS ON SM_DRAMRST# HIGH,DDR3 DRAMRST# HIGH Dimm not reset S3 DRAMRST_CNTRL_PCH Low ,MOS OFF SM_DRAMRST# Low,DDR3 DRAMRST# HIGH Dimm not reset S4,S5 DRAMRST_CNTRL_PCH Low ,MOS OFF SM_DRAMRST# Low,DDR3 DRAMRST# Low Dimm reset

B

DDR_A_CLK1 DDR_A_CLK1#

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DIMM_DRAMRST# <11,12>

C

DDR_B_D[0..63]<12>

DDR_A_CLK0 <11> DDR_A_CLK0# <11> DDR_A_CKE0 <11>

12

R263

R263 75_0402_1%

75_0402_1%

DDR_A_CS0# <11>

DDR_A_ODT0 <11>

DDR_A_DQS#[0..7] <11>

DDR_A_DQS[0..7] <11>

DDR_A_MA[0..15] <11>

DDR_B_BS0<12> DDR_B_BS1<12> DDR_B_BS2<12>

DDR_B_CAS#<12> DDR_B_RAS#<12> DDR_B_WE#<12>

DIMM_DRAMRST# SM_DRAMRST#

1

C785

100P_0201_25V8J

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

Issued Date

C

2

UCPU1D

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

1

C786

C786 100P_0402_50V8J

100P_0402_50V8J

2

2012/4/6 2013/4/6

AL4

SB_DQ[0]

AL1

SB_DQ[1]

AN3

SB_DQ[2]

AR4

SB_DQ[3]

AK4

SB_DQ[4]

AK3

SB_DQ[5]

AN4

SB_DQ[6]

AR1

SB_DQ[7]

AU4

SB_DQ[8]

AT2

SB_DQ[9]

AV4

SB_DQ[10]

BA4

SB_DQ[11]

AU3

SB_DQ[12]

AR3

SB_DQ[13]

AY2

SB_DQ[14]

BA3

SB_DQ[15]

BE9

SB_DQ[16]

BD9

SB_DQ[17]

BD13

SB_DQ[18]

BF12

SB_DQ[19]

BF8

SB_DQ[20]

BD10

SB_DQ[21]

BD14

SB_DQ[22]

BE13

SB_DQ[23]

BF16

SB_DQ[24]

BE17

SB_DQ[25]

BE18

SB_DQ[26]

BE21

SB_DQ[27]

BE14

SB_DQ[28]

BG14

SB_DQ[29]

BG18

SB_DQ[30]

BF19

SB_DQ[31]

BD50

SB_DQ[32]

BF48

SB_DQ[33]

BD53

SB_DQ[34]

BF52

SB_DQ[35]

BD49

SB_DQ[36]

BE49

SB_DQ[37]

BD54

SB_DQ[38]

BE53

SB_DQ[39]

BF56

SB_DQ[40]

BE57

SB_DQ[41]

BC59

SB_DQ[42]

AY60

SB_DQ[43]

BE54

SB_DQ[44]

BG54

SB_DQ[45]

BA58

SB_DQ[46]

AW59

SB_DQ[47]

AW58

SB_DQ[48]

AU58

SB_DQ[49]

AN61

SB_DQ[50]

AN59

SB_DQ[51]

AU59

SB_DQ[52]

AU61

SB_DQ[53]

AN58

SB_DQ[54]

AR58

SB_DQ[55]

AK58

SB_DQ[56]

AL58

SB_DQ[57]

AG58

SB_DQ[58]

AG59

SB_DQ[59]

AM60

SB_DQ[60]

AL59

SB_DQ[61]

AF61

SB_DQ[62]

AH60

SB_DQ[63]

BG39

SB_BS[0]

BD42

SB_BS[1]

AT22

SB_BS[2]

AV43

SB_CAS#

BF40

SB_RAS#

BD45

SB_WE#

IVY-BRIDGE_BGA1023

IVB@

1

C788

C788 100P_0402_50V8J

100P_0402_50V8J

2

Compal Secret Data

Deciphered Date

D

BA34

SB_CK[0]

AY34

SB_CK#[0]

AR22

SB_CKE[0]

BA36

SB_CK[1] SB_CK#[1] SB_CKE[1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

DDR SYSTEM MEMORY B

SB_MA[0]

SB_MA[1]

SB_MA[2]

SB_MA[3]

SB_MA[4]

SB_MA[5]

SB_MA[6]

SB_MA[7]

SB_MA[8]

SB_MA[9]

SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

D

DDR_B_CLK1

BB36

DDR_B_CLK1#

BF27

BE41 BE47

AT43 BG47

AL3

DDR_B_DQS#0

AV3

DDR_B_DQS#1

BG11

DDR_B_DQS#2

BD17

DDR_B_DQS#3

BG51

DDR_B_DQS#4

BA59

DDR_B_DQS#5

AT60

DDR_B_DQS#6

AK59

DDR_B_DQS#7

AM2

DDR_B_DQS0

AV1

DDR_B_DQS1

BE11

DDR_B_DQS2

BD18

DDR_B_DQS3

BE51

DDR_B_DQS4

BA61

DDR_B_DQS5

AR59

DDR_B_DQS6

AK61

DDR_B_DQS7

BF32

DDR_B_MA0

BE33

DDR_B_MA1

BD33

DDR_B_MA2

AU30

DDR_B_MA3

BD30

DDR_B_MA4

AV30

DDR_B_MA5

BG30

DDR_B_MA6

BD29

DDR_B_MA7

BE30

DDR_B_MA8

BE28

DDR_B_MA9

BD43

DDR_B_MA10

AT28

DDR_B_MA11

AV28

DDR_B_MA12

BD46

DDR_B_MA13

AT26

DDR_B_MA14

AU22

DDR_B_MA15

Address 0~13:For 128*16 Address 0~14:For 256*16 Address 0~15:For 512*16

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(3/7) DDRIII

Q3ZMC M/B LA-8481P Schematic

E

DDR_B_CLK0 <12> DDR_B_CLK0# <12> DDR_B_CKE0 <12>

12

R264

R264 75_0402_1%

75_0402_1%

DDR_B_CS0# <12>

DDR_B_ODT0 <12>

DDR_B_DQS#[0..7] <12>

DDR_B_DQS[0..7] <12>

DDR_B_MA[0..15] <12>

E

1.0

6 51Thursday, April 12, 2012

1.0

A

B

C

D

E

Default "1",EDS R1.0 P.88

CFG Straps for Processor

UCPU1E

T72 PAD@T72 PAD@

+CPU_CORE

1 1

R810

@

49.9_0402_1%

1 2

VCC_VAL_SENSE

VSS_VAL_SENSE

R812

@

49.9_0402_1%

1 2

+VGFX_CORE

R811

@

49.9_0402_1%

1 2

VAXG_VAL_SENSE

R813

@

49.9_0402_1%

1 2

VSSAXG_VAL_SENSE

2 2

CFG0

CFG2

CFG4 CFG5 CFG6 CFG7

VCC_VAL_SENSE VSS_VAL_SENSE

VAXG_VAL_SENSE VSSAXG_VAL_SENSE

T56 PAD@T56 PAD@

B50

CFG[0]

C51

CFG[1]

B54

CFG[2]

D53

CFG[3]

A51

CFG[4]

C53

CFG[5]

C55

CFG[6]

H49

CFG[7]

A55

CFG[8]

H51

CFG[9]

K49

CFG[10]

K53

CFG[11]

F53

CFG[12]

G53

CFG[13]

L51

CFG[14]

F51

CFG[15]

D52

CFG[16]

L53

CFG[17]

H43

VCC_VAL_SENSE

K43

VSS_VAL_SENSE

H45

VAXG_VAL_SENSE

K45

VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

H48

RSVD6

K48

RSVD7

BA19

RSVD8

AV19

RSVD9

AT21

RSVD10

BB21

RSVD11

BB19

RSVD12

AY21

RSVD13

BA22

RSVD14

AY22

RSVD15

AU19

RSVD16

AU21

RSVD17

BD21

RSVD18

BD22

RSVD19

BD25

RSVD20

BD26

RSVD21

BG22

RSVD22

BE22

RSVD23

BG26

RSVD24

BE26

RSVD25

BF23

RSVD26

BE24

RSVD27

IVY-BRIDGE_BGA1023

IVB@

RESERVED

DC_TEST_A4 DC_TEST_C4 DC_TEST_D3

DC_TEST_D1 DC_TEST_A58 DC_TEST_A59

DC_TEST_C59

DC_TEST_A61

DC_TEST_C61

DC_TEST_D61 DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58

DC_TEST_BG4 DC_TEST_BG3 DC_TEST_BE3 DC_TEST_BG1 DC_TEST_BE1 DC_TEST_BD1

BCLK_ITP

BCLK_ITP#

RSVD30 RSVD31 RSVD32 RSVD33

RSVD34 RSVD35 RSVD36 RSVD37 RSVD38

RSVD39 RSVD40

RSVD41 RSVD42 RSVD43 RSVD44

RSVD45

N59 N58

N42 L42 L45 L47

M13 M14 U14 W14 P13

AT49 K24

AH2 AG13 AM14 AM15

N50

A4 C4 D3

DC_TEST_C4_D3

D1 A58 A59 C59

DC_TEST_A59_C59

A61 C61

DC_TEST_A61_C61

D61 BD61 BE61 BE59

DC_TEST_BE59_BE61

BG61 BG59

DC_TEST_BG59_BG61

BG58 BG4 BG3 BE3

DC_TEST_BE3_BG3

BG1 BE1

DC_TEST_BE1_BG1

BD1

These pins are for solder joint reliability and non-critical to function. For BGA only.

PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane # definition matches

CFG2

socket pin map definition

0:Lane Reversed

*

CFG2

12

R234

R234 1K_0402_1%

1K_0402_1%

eDP enable

CFG4

1:Disable

*

0:Enable

CFG4

12

eDP@

R204

R204 1K_0402_1%

1K_0402_1%

PCIE Port Bifurcation Straps

11: (Default) 1x16 PCI Express

*

CFG[6:5]

10: 2x8 PCI Express

01: Reserved

00: 1x8,2x4 PCI Express

CFG6

CFG5

12

R230

1K_0402_1% @

R228

1K_0402_1%@

3 3

PEG DEFER TRAINING

1: (Default) PEG Train immediately following

CFG7

xxRESETB de assertion

CRB1.0 P.12

0: PEG Wait for BIOS for training

CFG7

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

12

R224

R224 1K_0402_1%@

1K_0402_1%@

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(4/7) RSVD,CFG

Q3ZMC M/B LA-8481P Schematic

E

7 51Thursday, April 12, 2012

1.0

A

INTEL Recommend VCC 3*330uF,12*22uF(0805),16*2.2uF(0402) PD0.9

1 1

2 2

3 3

4 4

B

UCPU1F

ULV SC/DC 33A

+CPU_CORE

UCPU1F

A26

VCC[1]

A29

VCC[2]

A31

VCC[3]

A34

VCC[4]

A35

VCC[5]

A38

VCC[6]

A39

VCC[7]

A42

VCC[8]

C26

VCC[9]

C27

VCC[10]

C32

VCC[11]

C34

VCC[12]

C37

VCC[13]

C39

VCC[14]

C42

VCC[15]

D27

VCC[16]

D32

VCC[17]

D34

VCC[18]

D37

VCC[19]

D39

VCC[20]

D42

VCC[21]

E26

VCC[22]

E28

VCC[23]

E32

VCC[24]

E34

VCC[25]

E37

VCC[26]

E38

VCC[27]

F25

VCC[28]

F26

VCC[29]

F28

VCC[30]

F32

VCC[31]

F34

VCC[32]

F37

VCC[33]

F38

VCC[34]

F42

VCC[35]

G42

VCC[36]

H25

VCC[37]

H26

VCC[38]

H28

VCC[39]

H29

VCC[40]

H32

VCC[41]

H34

VCC[42]

H35

VCC[43]

H37

VCC[44]

H38

VCC[45]

H40

VCC[46]

J25

VCC[47]

J26

VCC[48]

J28

VCC[49]

J29

VCC[50]

J32

VCC[51]

J34

VCC[52]

J35

VCC[53]

J37

VCC[54]

J38

VCC[55]

J40

VCC[56]

J42

VCC[57]

K26

VCC[58]

K27

VCC[59]

K29

VCC[60]

K32

VCC[61]

K34

VCC[62]

K35

VCC[63]

K37

VCC[64]

K39

VCC[66]

K42

VCC[67]

L25

VCC[68]

L28

VCC[69]

L33

VCC[70]

L36

VCC[71]

L40

VCC[72]

N26

VCC[73]

N30

VCC[74]

N34

VCC[75]

N38

VCC[76]

IVY-BRIDGE_BGA1023

IVB@

C

POWER

CORE SUPPLY

VCCIO[1] VCCIO[3] VCCIO[4] VCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8]

VCCIO[9] VCCIO[10] VCCIO[11] VCCIO[12] VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16] VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20] VCCIO[21] VCCIO[22] VCCIO[23] VCCIO[24] VCCIO[25] VCCIO[26] VCCIO[27] VCCIO[28] VCCIO[29]

VCCIO[30] VCCIO[31] VCCIO[32]

PEG IO AND DDR IO

VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49]

VCCIO50

VCCIO51

VCCIO_SEL

VCCPQE[1] VCCPQE[2]

RAILS

VIDALERT#

VIDSCLK

VIDSOUT

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID QUIET

8.5A

AF46 AG48 AG50 AG51 AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48

AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15

W16 W17

BC22

AM25 AN22

A44 B43 C44

F43 G43

AN16 AN17

VCCSENSE_R VSSSENSE_R

VCCIO_SEL_R

+1.05VS_VTT

12

C951

C951 1U_0201_4V6M

1U_0201_4V6M

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

VCCIO_SENSE VSSIO_SENSE

D

+1.05VS_VTT

INTEL Recommend VCCIO PD 0.9

330uF 1+1 10uF (0603) *5 1uF (0201) *16

+1.05VS_VTT

330uF 1 10uF (0603) *5 1uF (0201) *10

10K_0402_5%

+1.05VS_VTT

R582 0_0402_5%@R582 0_0402_5%@

1 2

+1.05VS_VTT

Place the PU,PD resistors close to CPU

1 2

R579 0_0402_5%@R579 0_0402_5%@ R581 0_0402_5%@R581 0_0402_5%@

1 2

R107 10_0402_5%R107 10_0402_5%

12

R105

R105 10_0402_5%

10_0402_5%

VCCIO_SEL

10K_0402_5% @

12

R574

R574 130_0402_5%

130_0402_5%

+1.05VS_VTT

VCCIO_SENSE <41>

Should change to connect from power cirucit & layout differential with VCCIO_SENSE.

+3VALW

VCCIO_SEL For 2012 CPU support

R521

R520

1 2

R576 43_0402_1%R 576 4 3_0402_1% R577 0_0402_5%@R577 0_0402_5%@

1 2 1 2

R578 0_0402_5%@R578 0_0402_5%@

+CPU_CORE

1 2

12

A19

R588

R588 100_0402_1%

100_0402_1%

R589

R589 100_0402_1%

100_0402_1%

E

1 : +1.05VS_VTT

*

0: +1.0VS_VTT

Check List R1.5 VIDALERT#:75ohm ±5% pull-up to VCCIO close to IMVP7 VIDSCLK: 55ohm ±5% pull-up to VCCIO close to IMVP7 VIDSOUT: 130ohm ±5% pull-up to VCCIO close to CPU 130ohm ±5% pull-up to VCCIO close to IMVP7

VR_SVID_ALRT# <43> VR_SVID_CLK <43> VR_SVID_DAT <43 >

VCCSENSE <43> VSSSENSE < 43>

Check List R1.5 VCCSENSE:100ohm ±1% pull-up to VCC near processor. VSSSENSE:100ohm ±1% pull-down to GND near processor.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(5/7) PWR,BYPASS

Q3ZMC M/B LA-8481P Schematic

E

8 51Thursday, April 12, 2012

1.0

A

INTEL Recommend VAXG

+VGFX_CORE

2*330uF,5*22uF(0805),6*10uF(0603),6*1uF(0402) PD 0.9

1 1

2 2

Check List R1.5 VCCAXG_SENSE:100ohm ±5% pull-up to VCC near processor. VSSAXG_SENSE:100ohm ±5% pull-down to GND near processor.

INTEL Recommend VCCPLL 1*330uF,2*1uF(0402) PD 0.9

3 3

+1.8VS

+VCCSA

R477

0_0805_5%

1 2

1

+

C606

C606 220U_B2_2.5VM_R15M

220U_B2_2.5VM_R15M

SGA00004I00

2

1

+

C607

C607 330U_B2_2VM_R15M

330U_B2_2VM_R15M

SGA00004400

2

VCC_AXG_SENSE<43>

VSS_AXG_SENSE<43>

+1.8VS_VCCPLL

+VCCSA

C999

C998

1U_0201_4V6M

12

B

ULV SC/DC GT1: 18A GT2: 33A

R381

1 2

100_0402_5%

1 2

100_0402_5%

C583

1U_0201_4V6M

C583

1U_0201_4V6M

1

2

R381

R396

1.2A

C584

1U_0201_4V6M

C584

1U_0201_4V6M

1

2

+VGFX_CORE

6A

C1179

C1180

C1181

1U_0201_4V6M

12

1U_0201_4V6M

12

UCPU1G

AA46

VAXG[1]

AB47

VAXG[2]

AB50

VAXG[3]

AB51

VAXG[4]

AB52

VAXG[5]

AB53

VAXG[6]

AB55

VAXG[7]

AB56

VAXG[8]

AB58

VAXG[9]

AB59

VAXG[10]

AC61

VAXG[11]

AD47

VAXG[12]

AD48

VAXG[13]

AD50

VAXG[14]

AD51

VAXG[15]

AD52

VAXG[16]

AD53

VAXG[17]

AD55

VAXG[18]

AD56

VAXG[19]

AD58

VAXG[20]

AD59

VAXG[21]

AE46

VAXG[22]

N45

VAXG[23]

P47

VAXG[24]

P48

VAXG[25]

P50

VAXG[26]

P51

VAXG[27]

P52

VAXG[28]

P53

VAXG[29]

P55

VAXG[30]

P56

VAXG[31]

P61

VAXG[32]

T48

VAXG[33]

T58

VAXG[34]

T59

VAXG[35]

T61

VAXG[36]

U46

VAXG[37]

V47

VAXG[38]

V48

VAXG[39]

V50

VAXG[40]

V51

VAXG[41]

V52

VAXG[42]

V53

VAXG[43]

V55

VAXG[44]

V56

VAXG[45]

V58

VAXG[46]

V59

VAXG[47]

W50

VAXG[48]

W51

VAXG[49]

W52

VAXG[50]

W53

VAXG[51]

W55

VAXG[52]

W56

VAXG[53]

W61

VAXG[54]

Y48

VAXG[55]

Y61

VAXG[56]

F45

VAXG_SENSE

G45

VSSAXG_SENSE

BB3

VCCPLL[1]

BC1

VCCPLL[2]

BC4

VCCPLL[3]

L17

VCCSA[1]

L21

VCCSA[2]

N16

VCCSA[3]

N20

VCCSA[4]

N22

VCCSA[5]

P17

VCCSA[6]

P20

VCCSA[7]

R16

VCCSA[8]

R18

VCCSA[9]

R21

VCCSA[10]

U15

VCCSA[11]

V16

VCCSA[12]

V17

VCCSA[13]

V18

VCCSA[14]

V21

VCCSA[15]

W20

VCCSA[16]

IVY-BRIDGE_BGA1023

IVB@

POWER

VREF

DDR3 - 1.5V RAILS

GRAPHICS

SENSE

LINES

SENSE

LINES

1.8V RAIL

SA RAIL

VCCSA VID

C

SM_VREF

SA_DIMM_VREFDQ SB_DIMM_VREFDQ

VDDQ[10] VDDQ[11] VDDQ[12] VDDQ[13] VDDQ[14] VDDQ[15] VDDQ[16] VDDQ[17] VDDQ[18] VDDQ[19] VDDQ[20] VDDQ[21] VDDQ[22] VDDQ[23] VDDQ[24] VDDQ[25] VDDQ[26]

VCCDQ[1] VCCDQ[2]

QUIET RAILS

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

SENSE LINES

VCCSA_VID[0] VCCSA_VID[1]

lines

SA_DIMM_VREFDQ SB_DIMM_VREFDQ For Future CPU M3 support, Sandey bridge not support M3, Check list1.0 & CRB say can NC

AY43

+V_SM_VREF

BE7

SA_DIMM_VREFDQ

BG7

SB_DIMM_VREFDQ

5A

AJ28

VDDQ[1]

AJ33

VDDQ[2]

AJ36

VDDQ[3]

AJ40

VDDQ[4]

AL30

VDDQ[5]

AL34

VDDQ[6]

AL38

VDDQ[7]

AL42

VDDQ[8]

AM33

VDDQ[9]

AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

AM28 AN26

BC43 BA43

U10

D48 D49

+1.35VS

CPU EDS1.3 P.93 VCCSA_VID0 Must PD

H_VCCSA_VID0 H_VCCSA_VID1

12

@

R69

1K_0402_1%

C978

C977

1U_0201_4V6M

12

Place BOT OUT Conn

C986

C1002

0.1U_0201_10V6K

12

C985

C985 1U_0201_4V6M

1U_0201_4V6M

12

R129

R129 0_0402_5%

0_0402_5%

@

12

@

R68

1K_0402_1%

C979

1U_0201_4V6M

12

C1010

0.1U_0201_10V6K

12

SA_DIMM_VREFDQ <11> SB_DIMM_VREFDQ <12>

C981

C980

1U_0201_4V6M

12

C1007

C1008

0.1U_0201_10V6K

12

VCCSA_SENSE <42>

H_VCCSA_VID0 <42> H_VCCSA_VID1 <42>

D

+V_SM_VREF should have 20 mil trace width

0.1U_0201_10V6K

C647

+1.35VS

12

R534

R534 1K_0402_5%

1K_0402_5%

1

2

12

R540

R540 1K_0402_5%

1K_0402_5%

E

INTEL Recommend VDDQ 1*330uF,8*10uF(0603) ,10*1uF(0402) PD0.9

Short for +1.35VS to +1.35V_CPU_VDDQ

C988

C991

1U_0201_4V6M

12

C1006

0.1U_0201_10V6K

12

1U_0201_4V6M

12

C990

C989

10U_0603_6.3V6M

12

C994

C1009

0.1U_0201_10V6K

12

C984

C983

C982

1U_0201_4V6M

C991

1U_0201_4V6M

12

C970

C987

10U_0603_6.3V6M

12

C992

C993

0.1U_0201_10V6K

12

VCCSA_VID

For 2012 future CPU VCCSA voltage select

VCCSA

VID1

0

1

Vout

0.9V

0.8V

VID0

0

0.85V V

0 X1

1 1

0.725V

0.675V

1

+

C599

C599 330U_B2_2VM_R15M

330U_B2_2VM_R15M

SGA00004400

2

SNB IVB

V V

V

VX

+1.35VS

ULV

V

INTEL Recommend VCCSA

4 4

1*330uF,5*10uF(0603) ,5*1uF(0402)

C995

10U_0603_6.3V6M

12

C997

C996

10U_0603_6.3V6M

12

PD0.9

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(6/7) PWR

Q3ZMC M/B LA-8481P Schematic

E

9 51Thursday, April 12, 2012

1.0

A

1 1

2 2

3 3

B

UCPU1H

A13

AA13 AA50 AA51 AA52 AA53 AA55 AA56

AB16 AB18 AB21 AB48 AB61 AC10 AC14 AC46

AC6 AD17 AD20

AD4 AD61 AE13

AE8

AF1

AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58

AF59 AG10 AG14 AG18 AG47 AG52 AG61

AG7 AH4

AH58

AJ13

AJ16

AJ20

AJ22

AJ26

AJ30

AJ34

AJ38

AJ42

AJ45

AJ48

AK1

AK52

AL10

AL13

AL17

AL21

AL25

AL28

AL33

AL36

AL40

AL43

AL47

AL61 AM13 AM20 AM22 AM26 AM30 AM34

VSS[1]

A17

VSS[2]

A21

VSS[3]

A25

VSS[4]

A28

VSS[5]

A33

VSS[6]

A37

VSS[7]

A40

VSS[8]

A45

VSS[9]

A49

VSS[10]

A53

VSS[11]

A9

VSS[12]

AA1

VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20]

AA8

VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69]

AJ7

VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90]

VSS

VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]

VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180]

AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13

C

UCPU1I

BG17

VSS[181]

BG21

VSS[182]

BG24

VSS[183]

BG28

VSS[184]

BG37

VSS[185]

BG41

VSS[186]

BG45

VSS[187]

BG49

VSS[188]

BG53

VSS[189]

BG9

VSS[190]

C29

VSS[191]

C35

VSS[192]

C40

VSS[193]

D10

VSS[194]

D14

VSS[195]

D18

VSS[196]

D22

VSS[197]

D26

VSS[198]

D29

VSS[199]

D35

VSS[200]

D4

VSS[201]

D40

VSS[202]

D43

VSS[203]

D46 D50 D54 D58

E25 E29

E35 E40 F13 F15 F19 F29 F35 F40 F55 G51

G61 H10 H14 H17 H21

H53 H58

K11 K21 K51

M11 M15

VSS[204] VSS[205] VSS[206] VSS[207]

D6

VSS[208] VSS[209] VSS[210]

E3

VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221]

G6

VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227]

H4

VSS[228] VSS[229] VSS[230]

J1

VSS[231]

J49

VSS[232]

J55

VSS[233] VSS[234] VSS[235] VSS[236]

K8

VSS[237]

L16

VSS[238]

L20

VSS[239]

L22

VSS[240]

L26

VSS[241]

L30

VSS[242]

L34

VSS[243]

L38

VSS[244]

L43

VSS[245]

L48

VSS[246]

L61

VSS[247] VSS[248] VSS[249]

VSS

NCTF

VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301]

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14

D

M4 M58 M6 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P14 P16 P18 P21 P58 P59 P9 R17 R20 R4 R46 T1 T47 T50 T51 T52 T53 T55 T56 U13 U8 V20 V61 W13 W15 W18 W21 W46 W8 Y4 Y47 Y58 Y59 G48

A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61

T58PAD@ T58PAD@ T59PAD@ T59PAD@ T60PAD@ T60PAD@ T61PAD@ T61PAD@ T62PAD@ T62PAD@ T63PAD@ T63PAD@ T64PAD@ T64PAD@ T65PAD@ T65PAD@ T66PAD@ T66PAD@ T67PAD@ T67PAD@ T68PAD@ T68PAD@ T69PAD@ T69PAD@ T70PAD@ T70PAD@ T71PAD@ T71PAD@

E

CR CheckList Rev1.5

IVY-BRIDGE_BGA1023

IVB@

IVY-BRIDGE_BGA1023

4 4

A

B

IVY-BRIDGE_BGA1023

IVB@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Title

Size Document Number Rev

Compal Electronics, Inc.

PROCESSOR(7/7) VSS

Q3ZMC M/B LA-8481P Schematic

E

10 51Thursday, April 12, 2012

1.0

A

B

C

D

E

Channel A

DDR_A_MA[0..15]<6>

DDR_A_DQS#[0..7]<6>

DDR_A_DQS[0..7]<6>

DDR_A_D[0..63]<6>

+VREFCA_A

1 1

C1252

0.1U_0402_16V4Z

C1252

0.1U_0402_16V4Z

1

2

+VREFDQ_A

0.1U_0402_16V4Z

1

C1253

2

2 2

DIMM_DRAMRST#<12,6>

+0.675VS

DDR_A_MA[0..15]

DDR_A_DQS#[0..7]

DDR_A_DQS[0..7]

DDR_A_D[0..63]

U56

M8

VREFCA

H1

VREFDQ

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12

@

C1258

2.2U_0603_6.3V6K@C1258

2.2U_0603_6.3V6K

12

DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 DDR_A_MA15 DDR_A_MA15 DDR_A_MA15

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

DDR_A_CLK0 DDR_A_CLK0# DDR_A_CKE0

DDR_A_ODT0 DDR_A_CS0# DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

DDR_A_DQS1 DDR_A_DQS0

DDR_A_DQS#1 DDR_A_DQS#0

DIMM_DRAMRST#

1 2

R992

240_0402_1%

1 2

R996

240_0402_1%

C1519

10U_0603_6.3V6M

C1519

10U_0603_6.3V6M

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

H5TQ2G63BFR-11C_FBGA96

X76@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3

DDR_A_D8

F7

DDR_A_D10

F2

DDR_A_D13

F8

DDR_A_D11

H3

DDR_A_D12

H8

DDR_A_D15

G2

DDR_A_D9

H7

DDR_A_D14

D7

DDR_A_D3

C3

DDR_A_D1

C8

DDR_A_D2

C2

DDR_A_D4

A7

DDR_A_D7

A2

DDR_A_D0

B8

DDR_A_D6

A3

DDR_A_D5

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

+VREFCA_A

C1255

0.1U_0402_16V4Z

C1255

0.1U_0402_16V4Z

+VREFDQ_A

1

2

0.1U_0402_16V4Z

1

C1254

2

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12

@

C1259

2.2U_0603_6.3V6K@C1259

2.2U_0603_6.3V6K

12

DDR_A_MA13 DDR_A_MA14

DDR_A_BS0

DDR_A_BS1 DDR_A_BS2

DDR_A_CLK0 DDR_A_CLK0# DDR_A_CKE0

DDR_A_ODT0 DDR_A_CS0# DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

DDR_A_DQS2 DDR_A_DQS3

DDR_A_DQS#2 DDR_A_DQS#3

DIMM_DRAMRST#

1 2

R993

240_0402_1%

1 2

R997

240_0402_1%

U57

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

H5TQ2G63BFR-11C_FBGA96

X76@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

U58

E3

DDR_A_D16

F7

DDR_A_D19

F2

DDR_A_D20

F8

DDR_A_D18

H3

DDR_A_D22

H8

DDR_A_D23

G2

DDR_A_D17

H7

DDR_A_D21

D7

DDR_A_D25

C3

DDR_A_D29

C8

DDR_A_D27

C2

DDR_A_D28

A7

DDR_A_D31

A2

DDR_A_D30

B8

DDR_A_D26

A3

DDR_A_D24

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

+VREFCA_A

C1256

0.1U_0402_16V4Z

C1256

0.1U_0402_16V4Z

+VREFDQ_A

1

2

0.1U_0402_16V4Z

1

C1260

2

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12

C1261

2.2U_0603_6.3V6K

C1261

2.2U_0603_6.3V6K

12

DDR_A_MA13 DDR_A_MA14

DDR_A_BS0

DDR_A_BS1 DDR_A_BS2

DDR_A_CLK0 DDR_A_CLK0# DDR_A_CKE0

DDR_A_ODT0 DDR_A_CS0# DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

DDR_A_DQS4 DDR_A_DQS5

DDR_A_DQS#4 DDR_A_DQS#5

DIMM_DRAMRST#

1 2

R994

240_0402_1%

1 2

R998

240_0402_1%

U58

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

H5TQ2G63BFR-11C_FBGA96

X76@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

+1.35V

+VREFCA_A

C1257

0.1U_0402_16V4Z

C1257

0.1U_0402_16V4Z

+VREFDQ_A

E3

DDR_A_D32

F7

DDR_A_D34

F2

DDR_A_D33

F8

DDR_A_D35

H3

DDR_A_D37

H8

DDR_A_D39

G2

DDR_A_D36

H7

DDR_A_D38

D7

DDR_A_D42

C3

DDR_A_D45

C8

DDR_A_D47

C2

DDR_A_D44

A7

DDR_A_D46

A2

DDR_A_D40

B8

DDR_A_D43

A3

DDR_A_D41

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

U59

M8

VREFCA

H1

1

2

0.1U_0402_16V4Z

1

C1262

2

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12

C1263

2.2U_0603_6.3V6K

C1263

2.2U_0603_6.3V6K

12

DDR_A_MA13 DDR_A_MA14

DDR_A_BS0

DDR_A_BS1 DDR_A_BS2

DDR_A_CLK0 DDR_A_CLK0# DDR_A_CKE0

DDR_A_ODT0 DDR_A_CS0# DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

DDR_A_DQS6 DDR_A_DQS7

DDR_A_DQS#6 DDR_A_DQS#7

DIMM_DRAMRST#

1 2

R995

240_0402_1%

1 2

R999

240_0402_1%

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

H5TQ2G63BFR-11C_FBGA96

X76@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3

DDR_A_D52

F7

DDR_A_D54

F2

DDR_A_D48

F8

DDR_A_D50

H3

DDR_A_D53

H8

DDR_A_D55

G2

DDR_A_D49

H7

DDR_A_D51

D7

DDR_A_D63

C3

DDR_A_D61

C8

DDR_A_D58

C2

DDR_A_D60

A7

DDR_A_D59

A2

DDR_A_D56

B8

DDR_A_D62

A3

DDR_A_D57

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

+1.35V+1.35V +1.35V

12

C1481

DDR3 CTL/ADD Termination

+0.675VS

1 2

DDR_A_RAS#

R284 36_0201_1%R284 36_0201_1%

1 2

DDR_A_CAS#

R290 36_0201_1%R290 36_0201_1%

1 2

DDR_A_ODT0

R291 36_0201_1%R291 36_0201_1%

1 2

DDR_A_CKE0

R294 36_0201_1%R294 36_0201_1%

1 2

DDR_A_WE#

R295 36_0201_1%R295 36_0201_1%

1 2

DDR_A_MA10

R296 36_0201_1%R296 36_0201_1%

1 2

DDR_A_CS0#

R297 36_0201_1%R297 36_0201_1%

1 2

DDR_A_BS2

R298 36_0201_1%R298 36_0201_1%

1 2

DDR_A_BS0

R301 36_0201_1%R301 36_0201_1%

1 2

DDR_A_MA12

R303 36_0201_1%R303 36_0201_1%

1 2

DDR_A_MA0

R304 36_0201_1%R304 36_0201_1%

1 2

DDR_A_BS1

R306 36_0201_1%R306 36_0201_1%

1 2

DDR_A_MA3

R309 36_0201_1%R309 36_0201_1%

1 2

DDR_A_MA1

R311 36_0201_1%R311 36_0201_1%

1 2

DDR_A_MA2

R312 36_0201_1%R312 36_0201_1%

1 2

DDR_A_MA4

R313 36_0201_1%R313 36_0201_1%

1 2

DDR_A_MA5

R315 36_0201_1%R315 36_0201_1%

1 2

DDR_A_MA11

R317 36_0201_1%R317 36_0201_1%

1 2

DDR_A_MA9

R318 36_0201_1%R318 36_0201_1%

1 2

DDR_A_MA14

R319 36_0201_1%R319 36_0201_1%

1 2

DDR_A_MA13

R323 36_0201_1%R323 36_0201_1%

1 2

DDR_A_MA6

R325 36_0201_1%R325 36_0201_1%

1 2

DDR_A_MA7

R332 36_0201_1%R332 36_0201_1%

1 2

DDR_A_MA8

R333 36_0201_1%R333 36_0201_1%

1 2

DDR_A_MA15

R342 36_0201_1%R342 36_0201_1%

C

DDR3 CLK Termination

C1458

1 2

0.1U_0402_16V4Z

DDR_A_RAS# <6>

DDR_A_CAS# <6>

DDR_A_ODT0 <6>

DDR_A_CKE0 <6>

DDR_A_WE# <6>

DDR_A_CS0# <6>

DDR_A_BS2 <6>

DDR_A_BS0 <6>

DDR_A_BS1 <6>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

DDR_A_CLK0< 6>

DDR_A_CLK0#<6>

1.CAD Note: Cterm= 1.6pF should be kept near feeding point of first SDRAM

2.CAD Note: Rtt= 30.1ohms, Ctt= 0.1uF should be kept within 600mils from last SDRAM

0.1U_0402_16V4Z

R1102

30.1_0402_1%

12

R1103

30.1_0402_1%

END topology

12

C1457

1.8P_0201_50V8C

Compal Secret Data

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

D

Delete U70 SPD EEROM circuit SA00004KS00 S IC EE 2K AT24C02C-XHM-T TSSOP 8P

External DDR Thermal Sensor

+3VS

C97

0.1U_0402_16V4Z

1 2

U4

1

VDD

2

D+

3

D-

THERM#4GND

W83L771AWG-2 TSSOP8P

SA00003PU00

SA00003PU00 S IC W83L771AWG-2 TSSOP 8P SENSOR

Title

DDRIII DIMMA

Size Document Number Rev

Custom

Q3ZMC M/B LA-8481P Schematic

Date: Sheet of

8

SCLK

7

SDATA

6

5

E

1 2

R546 10K_0402_5%R546 10K_0402_5%

ALERT#

Compal E lectronics, Inc.

EC_SMB_CK2 <14,24,32>

EC_SMB_DA2 <14,24,32>

+3VS

11 51Thursday, April 12, 2012

1.0

3 3

+0.675VS

C1462

1U_0201_4V6M

C1462

1U_0201_4V6M

12

Layout Note: Place near each memory part

+1.35V

C1466

0.1U_0201_10V6K

C1466

0.1U_0201_10V6K

12

+1.35V

4 4

C1469

10U_0603_6.3V6M

C1469

10U_0603_6.3V6M

12

C1460

1U_0201_4V6M

C1460

1U_0201_4V6M

C1459

0.1U_0201_10V6K

C1459

C1461

0.1U_0201_10V6K

C1461

0.1U_0201_10V6K

12

C1476

1U_0402_6.3V6K

C1476

1U_0402_6.3V6K

12

C1479

10U_0603_6.3V6M

C1479

10U_0603_6.3V6M

12

0.1U_0201_10V6K

12

C1467

0.1U_0201_10V6K

C1467

0.1U_0201_10V6K

C1477

1U_0402_6.3V6K

C1477

1U_0402_6.3V6K

12

C1475

10U_0603_6.3V6M

C1475

10U_0603_6.3V6M

C1463

10U_0603_6.3V6M

C1463

10U_0603_6.3V6M

12

C1513

0.1U_0201_10V6K

C1513

0.1U_0201_10V6K

C1514

1U_0201_4V6M

C1514

1U_0201_4V6M

12

C1470

0.1U_0201_10V6K

C1470

0.1U_0201_10V6K

C1471

1U_0402_6.3V6K

C1471

1U_0402_6.3V6K

12

C1465

10U_0603_6.3V6M

C1465

10U_0603_6.3V6M

C1473

10U_0603_6.3V6M

C1473

10U_0603_6.3V6M

12

C1511

1U_0201_4V6M

C1511

1U_0201_4V6M

C1512

0.1U_0201_10V6K

C1512

0.1U_0201_10V6K

12

C1478

1U_0402_6.3V6K

C1478

1U_0402_6.3V6K

C1468

1U_0402_6.3V6K

C1468

1U_0402_6.3V6K

12

C1472

10U_0603_6.3V6M

C1472

10U_0603_6.3V6M

C1474

10U_0603_6.3V6M

C1474

10U_0603_6.3V6M

12

M3 support

SA_DIMM_VREFDQ<9>

BSS138_NL_SOT23-3 @

DRAMRST_CNTRL_PCH<12,14,6>

R1108

1K_0402_1%

R1107

1K_0402_1%

330U_D2_2V_Y

@

C1464

12

+

1K_0402_1%

+1.35V

@R1105

@

0_0402_5%

1 2

S

12

C1483

0.1U_0402_16V4Z

C1483

0.1U_0402_16V4Z

12

R1105

G

2

+VREFCA_A

2.2U_0603_6.3V6K

C1482

+1.35V

12

R1106

R1106 1K_0402_1%

1K_0402_1%

+VREFDQ_A

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

C1480

12

R1104

R1104 1K_0402_1%

1K_0402_1%

C1480

12

D

13

Q78

12

near U56 near U57 near U58 near U59

A

B

A

B

C

D

E

U60

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

H5TQ2G63BFR-11C_FBGA96

X76@

DDR_B_DQS#[0..7] <6 >

DDR_B_DQS[0..7] <6>

DDR_B_D[0..63] <6>

DDR_B_MA[0..15] <6>

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1

VDDQ

A8

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H2

VDDQ

H9

VDDQ

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1

VSSQ

B9

VSSQ

D1

VSSQ

D8

VSSQ

E2

VSSQ

E8

VSSQ

F9

VSSQ

G1

VSSQ

G9

VSSQ

DDR_B_D12 DDR_B_D10 DDR_B_D13 DDR_B_D11 DDR_B_D8 DDR_B_D15 DDR_B_D9 DDR_B_D14

DDR_B_D1 DDR_B_D2 DDR_B_D7 DDR_B_D5 DDR_B_D6 DDR_B_D4 DDR_B_D3 DDR_B_D0

C1295

128@

+VREFCA_B

0.1U_0402_16V4Z

+VREFDQ_B+VREFDQ_B

U61

M8

VREFCA

H1

1

128@

2

0.1U_0402_16V4Z

1

2

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10

@

DDR_B_MA11 DDR_B_MA12

C1293

2.2U_0603_6.3V6K@C1293

2.2U_0603_6.3V6K

12

DDR_B_MA13

C1299

DDR_B_MA14

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

DDR_B_CLK0 DDR_B_CLK0# DDR_B_CKE0

DDR_B_ODT0 DDR_B_CS0# DDR_B_RAS# DDR_B_CAS# DDR_B_WE#

DDR_B_DQS2 DDR_B_DQS3

DDR_B_DQS#2 DDR_B_DQS#3

DIMM_DRAMRST#

R1006

1 2

240_0402_1%

128@

R1010

1 2

240_0402_1%

128@

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

H5TQ2G63BFR-11C_FBGA96

X76@

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3

DDR_B_D16

DQL0

F7

DDR_B_D23

DQL1

F2

DDR_B_D17

DQL2

F8

DDR_B_D22

DQL3

H3

DDR_B_D21

DQL4

H8

DDR_B_D18

DQL5

G2

DDR_B_D20

DQL6

H7

DDR_B_D19

DQL7

D7

DDR_B_D30

C3

DDR_B_D25

C8

DDR_B_D27

C2

DDR_B_D28

A7

DDR_B_D26

A2

DDR_B_D29

B8

DDR_B_D31

A3

DDR_B_D24

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

C1296

0.1U_0402_16V4Z

C1296

0.1U_0402_16V4Z

1

128@

2

+VREFDQ_B

0.1U_0402_16V4Z

1

128@

+1.35V +1.35V

2

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12

C1291

2.2U_0603_6.3V6K

C1291

2.2U_0603_6.3V6K

12

DDR_B_MA13

C1300

DDR_B_MA14

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

DDR_B_CLK0 DDR_B_CLK0# DDR_B_CKE0

DDR_B_ODT0 DDR_B_CS0# DDR_B_RAS# DDR_B_CAS# DDR_B_WE#

DDR_B_DQS4 DDR_B_DQS5

DDR_B_DQS#4 DDR_B_DQS#5

DIMM_DRAMRST#

R1007

1 2

240_0402_1%

128@

R1011

1 2

240_0402_1%

128@

U62

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

H5TQ2G63BFR-11C_FBGA96

X76@

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

U63

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

H5TQ2G63BFR-11C_FBGA96

X76@

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

E3

DDR_B_D61

DQL0

F7

DDR_B_D58

DQL1

F2

DDR_B_D60

DQL2

F8

DDR_B_D62

DQL3

H3

DDR_B_D56

DQL4

H8

DDR_B_D59

DQL5

G2

DDR_B_D57

DQL6

H7

DDR_B_D63

DQL7

D7

DDR_B_D55

C3

DDR_B_D52

C8

DDR_B_D51

C2

DDR_B_D49

A7

DDR_B_D54

A2

DDR_B_D48

B8

DDR_B_D50

A3

DDR_B_D53

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1

VSSQ

D8 E2 E8 F9 G1 G9

+1.35V+1.35V

E3

DDR_B_D37

DQL0

F7

DDR_B_D39

DQL1

F2

DDR_B_D36

DQL2

F8

DDR_B_D38

DQL3

H3

DDR_B_D32

DQL4

H8

DDR_B_D34

DQL5

G2

DDR_B_D33

DQL6

H7

DDR_B_D35

DQL7

D7

DDR_B_D42

C3

DDR_B_D41

C8

DDR_B_D47

C2

DDR_B_D44

A7

DDR_B_D46

A2

DDR_B_D45

B8

DDR_B_D43

A3

DDR_B_D40

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1

VSSQ

D8 E2 E8 F9 G1 G9

C1297

0.1U_0402_16V4Z

C1297

0.1U_0402_16V4Z

+VREFDQ_B

128@

+VREFCA_B+VREFCA_B

1

128@

2

0.1U_0402_16V4Z

1

2

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10

128@

DDR_B_MA11 DDR_B_MA12

C1302

2.2U_0603_6.3V6K

C1302

2.2U_0603_6.3V6K

12

DDR_B_MA13

C1301

DDR_B_MA14

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

DDR_B_CLK0 DDR_B_CLK0# DDR_B_CKE0

DDR_B_CS0# DDR_B_RAS# DDR_B_CAS# DDR_B_WE#

DDR_B_DQS7 DDR_B_DQS6

DDR_B_DQS#7 DDR_B_DQS#6

DIMM_DRAMRST#

R1008

1 2

240_0402_1%

128@

R1012

1 2

240_0402_1%

128@

Channel B

+VREFCA_B

1 1

2 2

C1294

0.1U_0402_16V4Z

C1294

0.1U_0402_16V4Z

1

128@

2

0.1U_0402_16V4Z

1

128@

2

DIMM_DRAMRST#<11,6>

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10

@

DDR_B_MA11 DDR_B_MA12

C1292

2.2U_0603_6.3V6K@C1292

2.2U_0603_6.3V6K

12

DDR_B_MA13

C1298

DDR_B_MA14 DDR_B_MA15 DDR_B_MA15 DDR_B_MA15 DDR_B_MA15

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

DDR_B_CLK0 DDR_B_CLK0# DDR_B_CKE0

DDR_B_ODT0 DDR_B_ODT0 DDR_B_CS0# DDR_B_RAS# DDR_B_CAS# DDR_B_WE#

DDR_B_DQS1 DDR_B_DQS0

DDR_B_DQS#1 DDR_B_DQS#0

DIMM_DRAMRST#

R1005

1 2

240_0402_1%

128@

R1009

1 2

240_0402_1%

128@

+0.675VS

C1517

1U_0201_4V6M

C1517

C1503

1U_0201_4V6M

C1503

1U_0201_4V6M

C1502

0.1U_0201_10V6K

C1502

0.1U_0201_10V6K

1U_0201_4V6M

C1504

1U_0201_4V6M

C1504

1U_0201_4V6M

12

3 3

4 4

12

128@

Layout Note: Place near each memory part

+1.35V

0.1U_0201_10V6K

C1487

0.1U_0201_10V6K

C1487

0.1U_0201_10V6K

12

128@

+1.35V

C1490

10U_0603_6.3V6M

C1490

10U_0603_6.3V6M

12

128@

1U_0201_4V6M

12

128@

0.1U_0201_10V6K

C1497

C1498

0.1U_0201_10V6K

C1498

0.1U_0201_10V6K

12

128@

10U_0603_6.3V6M

C1500

C1485

10U_0603_6.3V6M

C1485

10U_0603_6.3V6M

12

128@

1U_0201_4V6M

C1518

0.1U_0201_10V6K

C1518

0.1U_0201_10V6K

C1501

12

128@

C1488

C1491

1U_0402_6.3V6K

C1491

1U_0402_6.3V6K

C1492

1U_0402_6.3V6K

C1492

1U_0402_6.3V6K

12

128@

C1494

10U_0603_6.3V6M

C1494

10U_0603_6.3V6M

C1496

C1486

10U_0603_6.3V6M

C1486

10U_0603_6.3V6M

12

128@

C1515

0.1U_0201_10V6K

C1515

0.1U_0201_10V6K

C1516

0.1U_0201_10V6K

C1516

0.1U_0201_10V6K

12

128@

C1489

0.1U_0201_10V6K

C1489

0.1U_0201_10V6K

C1499

1U_0402_6.3V6K

C1499

1U_0402_6.3V6K

12

128@

C1493

10U_0603_6.3V6M

C1493

10U_0603_6.3V6M

C1495

10U_0603_6.3V6M

C1495

10U_0603_6.3V6M

330U_D2_2V_Y

C1484

12

+

128@

M3 support

SB_DIMM_VREFDQ<9>

DRAMRST_CNTRL_PCH<11,14,6>

BSS138_NL_SOT23-3 @

+1.35V

12

128@

R1120

1K_0402_1%

12

128@

R1119

1K_0402_1%

C1508

0.1U_0402_16V4Z

C1508

0.1U_0402_16V4Z

12

128@

near U60 near U61 near U62 near U63

A

B

R1122

@R1122

@

0_0402_5%

1 2

S

G

2

+VREFCA_B

2.2U_0603_6.3V6K

C1507

128@

+1.35V

12

128@

R1123

R1123 1K_0402_1%

1K_0402_1%

+VREFDQ_B

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

C1509

C1510

D

13

12

Q79

128@

R1121

R1121 1K_0402_1%

1K_0402_1%

12

C1510

12

128@

C

DDR3 CTL/ADD Termination

+0.675VS

128@

1 2

DDR_B_RAS#

R380 36_0 201_1%

128@

1 2

DDR_B_CAS#

R308 36_0 201_1%

128@

1 2

DDR_B_ODT0

R339 36_0 201_1%

128@

1 2

DDR_B_CKE0

R349 36_0 201_1%

128@

1 2

DDR_B_WE#

R343 36_0 201_1%

128@

1 2

DDR_B_MA10

R348 36_0 201_1%

128@

1 2

DDR_B_CS0#

R354 36_0 201_1%

128@

1 2

DDR_B_BS2

R370 36_0 201_1%

128@

1 2

DDR_B_BS0

R340 36_0 201_1%

128@

1 2

DDR_B_MA12

R352 36_0 201_1%

128@

1 2

DDR_B_MA0

R407 36_0 201_1%

128@

1 2

DDR_B_BS1

R351 36_0 201_1%

128@

1 2

DDR_B_MA3

R392 36_0 201_1%

128@

1 2

DDR_B_MA1

R398 36_0 201_1%

128@

1 2

DDR_B_MA2

R377 36_0 201_1%

128@

1 2

DDR_B_MA4

R356 36_0 201_1%

128@

1 2

DDR_B_MA5

R355 36_0 201_1%

128@

1 2

DDR_B_MA11

R359 36_0 201_1%

128@

1 2

DDR_B_MA9

R367 36_0 201_1%

128@

1 2

DDR_B_MA14

R408 36_0 201_1%

128@

1 2

DDR_B_MA13

R335 36_0 201_1%

128@

1 2

DDR_B_MA6

R350 36_0 201_1%

128@

1 2

DDR_B_MA7

R336 36_0 201_1%

128@

1 2

DDR_B_MA8

R344 36_0 201_1%

128@

1 2

DDR_B_MA15

R390 36_0 201_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR_B_RAS# <6>

DDR_B_CAS# <6>

DDR_B_ODT0 <6>

DDR_B_CKE0 <6>

DDR_B_WE# <6>

DDR_B_CS0# <6>

DDR_B_BS2 <6>

DDR_B_BS0 <6>

DDR_B_BS1 <6>

Compal Secret Data

D

Compal Secret Data

Deciphered Date

2012/4/6 2013/4/6

Delete U71 SPD EEROM circuit SA00004KS00 S IC EE 2K AT24C02C-XHM-T TSSOP 8P

DDR_B_CLK0<6>

DDR_B_CLK0#<6>

1.CAD Note: Cterm= 1.6pF should be kept near feeding point of first SDRAM

2.CAD Note: Rtt= 30.1ohms, Ctt= 0.1uF should be kept within 600mils from last SDRAM

DDR3 CLK Termination

C1506

128@

1 2

0.1U_0402_16V4Z

R1117

30.1_0402_1%

12

128@

R1118

30.1_0402_1%

END topology

12

C1505

1.8P_0201_50V8C128@

Compal Electronics, Inc.

Title

DDRIII DIMMB

Size Document Number Rev

Custom

Q3ZMC M/B LA-8481P Schematic

Date: Sheet of

E

1.0

12 51Thursday, April 12, 2012

A

12

1

R568

+RTCVCC

R338 20K_0402_5%R338 20K_04 02_5%

R337 20K_0402_5%R337 20K_04 02_5%

1 1

+RTCVCC

C516

1U_0402_6.3V6K

1 2

C502

1U_0402_6.3V6K

1 2

R353 1M_0402_5%R353 1M_0402_5%

1 2

R347 330K_0402_5%R347 330K_0402_5 %

INTVRMEN

H

：：：：

Integrated VRM enable

*

L

：：：：

Integrated VRM disable

R568 0_0603_5%

0_0603_5%

@

2

PCH_RTCRST#

PCH_SRTCRST#

1

2

SM_INTRUDER#

PCH_INTVRMEN

1 2

R638 10M_0402_5 %R638 10M_0402_5 %

X1

SJ100004Z00

12

32.768KHZ_12.5PF_9H03200 019

1

C756

C756 18P_0402_50V8J

18P_0402_50V8J

2

(INTVRMEN should always be pull high.)

+3VS

HIGH= Enable ( No Reboot)Disable TCO timer system reboot feature

LOW= Disable (Default internal PD)

*

2 2

HDA_SDO<32>

HDA_SDO

ME debug mode,this signal has a weak internal PD

Low = Disabled (Default)

*

High = Enabled [Flash Descriptor Security Overide]

+VCCSUS3_3

This signal has a weak internal pull-down

On Die PLL VR Select is supplied by

1.5V when smapled high

*

1.8V when sampled low Needs to be pulled High for Huron River platfrom

HDA_BITCLK_AUDIO<33>

3 3

HDA_SYNC_AUDIO<33 >

HDA_RST_AUDIO#<33>

HDA_SDOUT_AUDIO<33>

+3VALW_PCH +3VALW_PCH+3VALW_PCH

12

@

12

@

4 4

@

1 2

R405 1K_0402_5%

+VCCSUS3_3

R328 1K_0402_5%R328 1K_040 2_5%

R660

200_0402_5%

PCH_JTAG_TDO PCH_JTAG_TDIPCH_JTAG_TMS

R670

100_0402_1%

R322

@R32 2

@

1K_0402_5%

12

@

R320 0_04 02_5%

12

1 2

R677

33_0402_5%

1 2

R676

33_0402_5%

1 2

R673

33_0402_5%

1 2

R665

33_0402_5%

12

R659

@

200_0402_5%

12

R671

@

100_0402_1%

+3VS

A

PCH_SPKR

HDA_SDOUT_PCH

12

HDA_SYNC_PCH

HDA_BITCLK_PCH

HDA_SYNC_PCH_R

HDA_RST_PCH#

HDA_SDOUT_PCH

12

R658

@

200_0402_5%

12

R669

@

100_0402_1%

1 2

R699 3.3K_0402_5%R 699 3.3K_0402_5 %

1 2

R700 3.3K_0402_5%R 700 3.3K_0402_5 %

1 2

R703 3.3K_0402_5%R 703 3.3K_0402_5 %

Prevent back drive issue.

+5VS

G

2

Q20

Q20 BSS138W-7-F_SOT323-3

BSS138W-7-F_SOT323-3

13

HDA_SYNC_PCH

D

S

D

S

R302

1 2

0_0402_5%@

12

PCH_SPI_CS0# SPI_WP0# SPI_HOLD0#

PCH_SPI_CS1# PCH_SPI_MISO_1 SPI_WP1#

0_0402_5%@

R468

R468 1M_0402_5%

1M_0402_5%

PCH_SPI_CLK_0

R739 33_0402_5%R739 33_0402_5%

PCH_SPI_CLK_1

R704 33_0402_5%R704 33_0402_5%

PCH_SPI_CS1# PCH_SPI_ CS1#_R

R733 0_0402_5%R733 0_0402_5%

PCH_SPI_MOSI_0

R737 33_0402_5%R737 33_0402_5%

PCH_SPI_MOSI_1

R734 33_0402_5%R734 33_0402_5%

PCH_SPI_MISO_0

R736 33_0402_5%R736 33_0402_5%

PCH_SPI_MISO_1

R738 33_0402_5%R738 33_0402_5%

U40

1

CS#

3

WP#

7

HOLD#

4

GND

MX25L3206EM2I-12G_SO8

SA00003K800

1 2 3 4

B

PCH_RTCX1

PCH_RTCX2

1

C757

C757 18P_0402_50V8J

18P_0402_50V8J

2

PCH_SPKR< 33>

HDA_SDIN0<33>

12

4MB=32Mb

U42

CS# SO WP# GND

MX25L1606EM2I-12G_SO8

SA00003FO10

VCC

SCLK

SI

SO

2MB=16Mb

VCC

HOLD#

SCLK

SI

B

8 6 5 2

8 7 6 5

R672

51_0402_5%

+3VS

PCH_SPI_CLK_0 PCH_SPI_MOSI_0 PCH_SPI_MISO_0

+3VS

SPI_HOLD1# PCH_SPI_CLK_1 PCH_SPI_MOSI_1

PCH_RTCX1

PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BITCLK_PCH

HDA_SYNC_PCH

PCH_SPKR

HDA_RST_PCH#

HDA_SDIN0

HDA_SDOUT_PCH

12

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_SPI_CLK

PCH_SPI_CS0#

PCH_SPI_MOSI

PCH_SPI_MISO

R701 3.3K_0402_5%R 701 3.3K_0402_5 %

+RTCBATT

+RTCVCC

3

1

C197

0.1U_0402_16V4Z

2

U37A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

COUGARPOINT_FCBGA989~D

HM77@

Reserve for EMI

PCH_SPI_CLK

12

1

D5

D5 BAS40-04_SOT23-3

BAS40-04_SOT23-3

2

+CHGRTC

20MIL

RTC Battery:Chargeable

RTCIHDA

JTAG

SPI

S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO!SA00005AGI0

@

1 2

R977

22P_0402_50V8J

22_0402_5%

22P_0402_50V8J

Security Classification

+3VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

LPC

FWH4 / LFRAME#

LDRQ1# / GPIO23

SATA 6G

SATA

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATA0GP / GPIO21

SATA1GP / GPIO19

@

C1216

1 2

Issued Date

C

LDRQ0#

SERIRQ

SATA0RXN SATA0RXP SATA0TXN

SATA0TXP

SATA1RXN SATA1RXP SATA1TXN

SATA1TXP

SATA2RXN SATA2RXP SATA2TXN

SATA2TXP

SATA3RXN SATA3RXP SATA3TXN

SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATALED#

C38

LPC_AD0

A38

LPC_AD1

B37

LPC_AD2

C37

LPC_AD3

D36

LPC_FRAME#

E36 K36

PCH_GPIO23

V5

SERIRQ

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11

Y10

SATA_COMP

AB12

AB13

SATA3_COMP

AH1

RBIAS_SATA3

P3

PCH_SATALED#

V14

PCH_GPIO21

P1

PCH_GPIO19

2012/4/6 2013/4/6

LPC_AD0 <30, 32> LPC_AD1 <30, 32> LPC_AD2 <30, 32> LPC_AD3 <30, 32>

LPC_FRAME# <30,32>

PCH_GPIO23 <18>

SERIRQ <30 ,32>

SATA_PRX_DTX_N0 <29 > SATA_PRX_DTX_P0 <29> SATA_PTX_DRX_N0 <29 > SATA_PTX_DRX_P0 <29>

SATA_PRX_DTX_N1 <29 > SATA_PRX_DTX_P1 <29> SATA_PTX_DRX_N1 <29 > SATA_PTX_DRX_P1 <29>

+1.05VS_PCH

R389

37.4_0402_1%

1 2

+1.05VS_PCH

R388

49.9_0402_1%

1 2

R650 750_0402_1%R650 750_0402_1%

Compal Secret Data

Deciphered Date

No use PH 10K +3VS

GPIO19 has internal Pull up

D

CRB:10K ohm

SERIRQ

PCH_SATALED#

PCH_GPIO21

Check List 1.0:8.2K ohm

R403 10K_0402_5%R403 10K_0402_5%

R662 10K_0402_5%R662 10K_0402_5%

+3VS

12

R687

10K_0402_5%

R688

@R688

@

10K_0402_5%

1 2

PCH_GPIO19

Switchable

*

12

Switchable Graph

Non SG

+3VS

R674

4.7K_0402_5%

E

+3VS

GPIO21

0 1

12

Debug Port DG 1.2 PH 4.7K +3VS

Boot BIOS Strap

Boot BIOS

GPIO51

LPC

Reserved

-

SPI

*

Compal Electronics, Inc.

Title

Size Do cument Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PCH (1/8) SATA,HDA,SPI, LPC, XDP

Q3ZMC M/B LA-8481P Schematic

GPIO19 0 0 0 1 1 1

E

1 0

1.0

13 51Thursday, April 12, 2012

1.0

A

PCIE_PRX_DTX_N1<22>

Card Reader

Mini Card 1 On Board WLAN

1 1

Thunderbolt

2 2

Mini Card 1 (On Board WLAN)

PCIE_PRX_DTX_P1<22> PCIE_PTX_C_DRX_N1<22> PCIE_PTX_C_DRX_P1<22>

PCIE_PRX_DTX_N2<28>

PCIE_PRX_DTX_P2<28> PCIE_PTX_C_DRX_N2<28> PCIE_PTX_C_DRX_P2<28>

PCIE_PRX_DTX_N5<24>

PCIE_PRX_DTX_P5<24> PCIE_PTX_C_DRX_N5<24> PCIE_PTX_C_DRX_P5<24>

PCIE_PRX_DTX_N6<24>

PCIE_PRX_DTX_P6<24> PCIE_PTX_C_DRX_N6<24> PCIE_PTX_C_DRX_P6<24>

PCIE_PRX_DTX_N7<24>

PCIE_PRX_DTX_P7<24> PCIE_PTX_C_DRX_N7<24> PCIE_PTX_C_DRX_P7<24>

PCIE_PRX_DTX_N8<24>

PCIE_PRX_DTX_P8<24> PCIE_PTX_C_DRX_N8<24> PCIE_PTX_C_DRX_P8<24>

No use PH 10K +3VALW

CLK_PCIE_MINI1#<28> CLK_PCIE_MINI1<28>

MINI1_CLKREQ#<28>

1 2

C617 0.1U_0201_10V6KC617 0.1U_0201_10V6K

1 2

C678 0.1U_0201_10V6KC678 0.1U_0201_10V6K

1 2

C573 0.1U_0201_10V6KC573 0.1U_0201_10V6K

1 2

C572 0.1U_0201_10V6KC572 0.1U_0201_10V6K

1 2

C681 0.1U_0201_10V6KC681 0.1U_0201_10V6K

1 2

C682 0.1U_0201_10V6KC682 0.1U_0201_10V6K

1 2

C684 0.1U_0201_10V6KC684 0.1U_0201_10V6K

1 2

C683 0.1U_0201_10V6KC683 0.1U_0201_10V6K

1 2

C686 0.1U_0201_10V6KC686 0.1U_0201_10V6K

1 2

C685 0.1U_0201_10V6KC685 0.1U_0201_10V6K

1 2

C688 0.1U_0201_10V6KC688 0.1U_0201_10V6K

1 2

C687 0.1U_0201_10V6KC687 0.1U_0201_10V6K

No use PH 10K +3VS

TB_SMB_DA_GPIO6<24>

No use PH 10K +3VS

No use PH 10K +3VALW

Card Reader

3 3

CLK_PCIE_CARD#<22> CLK_PCIE_CARD<22>

CARD_CLKREQ#<22>

No use PH 10K +3VALW

CLK_TB_REFCLK#<24>

CLK_TB_REFCLK<24>

TB_CLKREQ#<24>

AK14:CLKOUT_ITPXDP_N AK13:CLKOUT_ITPXDP_P

No use PH 10K +3VALW

+3VS

R424 10K_0402_5%R424 10K_0402_5%

R686 10K_0402_5%R686 10K_0402_5%

+VCCSUS3_3

4 4

R652 10K_0402_5%R652 10K_0402_5%

R399 10K_0402_5%R399 10K_0402_5%

R684 10K_0402_5%R684 10K_0402_5%

R410 10K_0402_5%R410 10K_0402_5%

R400 10K_0402_5%R400 10K_0402_5%

R414 10K_0402_5%R414 10K_0402_5%

R425 10K_0402_5%R425 10K_0402_5%

12

A

MINI1_CLKREQ#

TB_SMB_DA_GPIO6

PCH_GPIO73

LAN_CLKREQ#

CARD_CLKREQ#

MINI2_CLKREQ#

PEG_CLKREQ#

PCH_GPIO45

TB_CLKREQ#

Check List R1.0 p.37 Clock Req# pull high power source

B

PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1

PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2

PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 PCIE_PTX_DRX_N5 PCIE_PTX_DRX_P5

PCIE_PRX_DTX_N6 PCIE_PRX_DTX_P6 PCIE_PTX_DRX_N6 PCIE_PTX_DRX_P6

PCIE_PRX_DTX_N7 PCIE_PRX_DTX_P7 PCIE_PTX_DRX_N7 PCIE_PTX_DRX_P7

PCIE_PRX_DTX_N8 PCIE_PRX_DTX_P8 PCIE_PTX_DRX_N8 PCIE_PTX_DRX_P8

PCH_GPIO73

MINI1_CLKREQ#

TB_SMB_DA_GPIO6

LAN_CLKREQ#

CARD_CLKREQ#

MINI2_CLKREQ#

PEG_CLKREQ#

PCH_GPIO45

CLK_TB_REFCLK# CLK_TB_REFCLK

TB_CLKREQ#

B

U37B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GP IO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GP IO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GP IO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GP IO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GP IO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GP IO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GP IO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GP IO46

AK14

CLKOUT_BCLK0_N / CLKOUT_PCIE8N

AK13

CLKOUT_BCLK0_P / CLKOUT_PCIE8P

COUGARPOINT_FCBGA989~D

HM77@

S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO!SA00005AGI0

SMBUSController

SML1ALERT# / PC HHOT# / GPIO74

PCI-E*

CLOCKS

CLKOUT_DP_N / C LKOUT_BCLK1_N

CLKOUT_DP_P / C LKOUT_BCLK1_P

CLKIN_GND1_N CLKIN_GND1_P

C

E12

SMBALERT# / GP IO11

SMBCLK

SMBDATA

SML0ALERT# / GP IO60

SML0CLK

SML0DATA

SML1CLK / GPIO58

SML1DATA / GPIO7 5

CL_CLK1

Link

PEG_A_CLKRQ# / GPIO47

CLKIN_SATA_N / CKS SCD_N CLKIN_SATA_P / CKS SCD_P

FLEX CLOCKS

CL_DATA1

CL_RST1#

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_DMI2_N CLKIN_DMI2_P

CLKIN_DOT_96N CLKIN_DOT_96P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / G PIO64

CLKOUTFLEX1 / G PIO65

CLKOUTFLEX2 / G PIO66

CLKOUTFLEX3 / G PIO67

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

SMB_ALERT#

H14

PCH_SMBCLK

C9

PCH_SMBDATA

A12

DRAMRST_CNTRL_PC H

C8

G12

C13

PCH_GPIO74

E14

PCH_SML1CLK

M16

PCH_SML1DATA

M7

T11

P10

M10

PCH_GPIO47

AB37 AB38

AV22

CLK_CPU_DMI#

AU22

CLK_CPU_DMI

AM12

CLK_CPU_DPLL#

AM13

CLK_CPU_DPLL

BF18

CLK_BUF_CPU_DMI#

BE18

CLK_BUF_CPU_DMI

BJ30

CLKIN_GND1#

BG30

CLKIN_GND1

G24

CLK_BUF_DREF_96M#

E24

CLK_BUF_DREF_96M

AK7

CLK_BUF_PCIE_SATA#

AK5

CLK_BUF_PCIE_SATA

K45

CLK_BUF_ICH_14M

H45

CLK_PCI_LPBACK

V47

XTAL25_IN

V49

XTAL25_OUT

Y47

XCLK_RCOMP

K43

CLK_FLEX0

F47

CLK_FLEX1

H47

CLK_FLEX2

K49

DGPU_PRSNT#

2012/4/6 2013/4/6

SMB_ALERT# <33>

DRAMRST_CNTRL_PC H <11,12,6>

S3 reduse

CLK_CPU_DMI# <5> CLK_CPU_DMI <5>

CLK_CPU_DPLL# <5> CLK_CPU_DPLL <5>

1 2

R357 10K_0402_5%R357 10K_0402_5%

1 2

R358 10K_0402_5%R358 10K_0402_5%

1 2

R330 10K_0402_5%R330 10K_0402_5%

1 2

R331 10K_0402_5%R331 10K_0402_5%

1 2

R346 10K_0402_5%R346 10K_0402_5%

1 2

R345 10K_0402_5%R345 10K_0402_5%

1 2

R387 10K_0402_5%R387 10K_0402_5%

1 2

R393 10K_0402_5%R393 10K_0402_5%

1 2

R292 10K_0402_5%R292 10K_0402_5%

R293 33_0402_5%

@

Reserve for EMI please close to PCH

R289

90.9_0402_1%

1 2

@

PAD

T52

@

PAD

T53

@

PAD

T21

Compal Secret Data

Deciphered Date

D

No use PH 10K +3VALW

PH 2.2K +3VALW

No use PH 10K +3VALWS3 reduse

No use PH 10K +3VALW

PH 2.2K +3VALW

No use PH 10K +3VALW

120MHz for eDP.

12

1 2

C421 22P_0402_50V8J

@

+1.05VS_PCH

UMA@

DGPU_PRSNT#

@

DIS,Optimus

UMA

D

Pull down 10K ohm for using internal Clock

+3VS

12

R610

R610 10K_0402_5%

10K_0402_5%

12

R628

R628 10K_0402_5%

10K_0402_5%

GPIO67

DGPU_PRSNT#

0 1

E

SMB_ALERT#

PCH_SMBCLK

PCH_SMBDATA

DRAMRST_CNTRL_PC H

PCH_GPIO74

PCH_SML1CLK

PCH_SML1DATA

PCH_GPIO47

+3VS

3 4

Q27A

Q27A DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

PCH_SMBCLK

+3VS

PCH_SML1DATA

PCH_SML1CLK

CLK_PCI_LPBACK <17>

3 4

Q22A

Q22A DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

XTAL25_IN

XTAL25_OUT

C744

8.2P_0402_50V8D

Title

Size Document Number Rev

Custom

Q3ZMC M/B LA-8481P Schematic

Date: Sheet of

1 2

R383 10K_0402_5%R383 10K_0402_5%

1 2

R668 2.2K_0402_5%R668 2.2K_0402_5%

1 2

R664 2.2K_0402_5%R664 2.2K_0402_5%

1 2

R648 1K_0402_5%R648 1K_0402_5%

1 2

R647 10K_0402_5%R647 10K_0402_5%

1 2

R375 2.2K_0402_5%R375 2.2K_0402_5%

1 2

R369 2.2K_0402_5%R369 2.2K_0402_5%

1 2

R683 10K_0402_5%R683 10K_0402_5%

For TP

R427

4.7K_0402_5%

5

1 2

SGD

2

G

6 1

S

D

S

D

Q27B

Q27B DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

5

SGD

2

G

6 1

S

D

S

D

Q22B

Q22B DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

1

2

Compal Electronics, Inc.

PCH (2/8) PCIE, SMBUS, CLK

+3VS

D_CK_SDATAPCH_SMBDATA

R415

4.7K_0402_5%

1 2

+3VS

D_CK_SCLK

Pull up at EC side. For DDR,EC

EC_SMB_DA2

EC_SMB_CK2

1 2

R611 1M_0402_5%R611 1M_0402_5%

25MHZ_10PF_7V25000014

3

GND

4

Y1

E

+VCCSUS3_3

D_CK_SDATA <33>

D_CK_SCLK <33>

EC_SMB_DA2 <11,24,32>

EC_SMB_CK2 <11,24,32>

1

GND

2

14 51Thursday, April 12, 2012

1

C745

8.2P_0402_50V8D

2

1.0

A

+VCCSUS3_3

R378 10K_0402_5%R378 10K_0402_5%

R402 10K_0402_5%R402 10K_0402_5%

R649 10K_0402_5%R649 10K_0402_5%

R373 200_0402_5%R373 200_0402_5%

+3VALW_PCH

1 1

R341 10K_0402_5%@R341 10K_0402_5%@

R634 10K_0402_5%R634 10K_0402_5%

2 2

ACPRESENT<32>

12

not support AMT APWROK can mux with PWROK (check list1.0 P.40)

R456 0_0402_ 5%R456 0_0402_5%

PCH_GPIO30

PCH_GPIO72

RI#

PM_DRAM_PWR GD

PCH_ACIN

PCH_RSMRST#

not support Deep S4,S5 mux with SUS_PWR_DN_ACK

1 2

PCH_ACIN

SUSACK#<32>

XDP_DBRESET#<5>

PM_DRAM_PWR GD<5>

PCH_RSMRST#<32>

SUSWARN#<32>

PBTN_OUT#<32>

No use PH 10K +3VALW

Ring Indicator CRB1.0 PH 10K +3VALW

DMI_CTX_PRX_N0<4> DMI_CTX_PRX_N1<4> DMI_CTX_PRX_N2<4> DMI_CTX_PRX_N3<4>

DMI_CTX_PRX_P0<4> DMI_CTX_PRX_P1<4> DMI_CTX_PRX_P2<4> DMI_CTX_PRX_P3<4>

DMI_CRX_PTX_N0<4> DMI_CRX_PTX_N1<4> DMI_CRX_PTX_N2<4> DMI_CRX_PTX_N3<4>

DMI_CRX_PTX_P0<4> DMI_CRX_PTX_P1<4> DMI_CRX_PTX_P2<4> DMI_CRX_PTX_P3<4>

+1.05VS_PCH

PCH_PWROK

ACIN<32,35,38,39>

B

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

1 2

R625 49.9_0402_1%R625 49.9_0402_1%

1 2

R632 750_0402_1%R632 750_0402_1%

4mil width and place within 500mil of the PCH

1 2

SUSACK#_R

@

R372 0_0402_5%

1 2

XDP_DBRESET#_R

@

R661 0_0402_5%

R382 0_0402_5%

R412 0_0402_5%

D19 RB751V-40_S OD323-2

1 2

@

1 2

@

SYS_PWROK

PCH_PWROK_R

PM_DRAM_PWR GD

PCH_RSMRST#

PCH_GPIO30

PBTN_OUT#

21

PCH_ACIN

DMI_IRCOMP

DMI2RBIAS

PCH_GPIO72

RI#

U37C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN# / SUS_PW R_DN_ACK / GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

COUGARPOINT_FCBGA989~D

HM77@

S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO!SA00005AGI0

C

DMI

FDI

DMI

FDI

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

SLP_LAN# / GPIO29

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16

AV12

BC10

AV14

BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWODVREN

PCH_PCIE_WAKE#

CLKRUN#

SUS_STAT#

SUSCLK_R

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

SLP_A#

SLP_SUS#

H_PM_SYNC

PCH_GPIO29

是是是是是是是是是是是是是是是是

1 2

PCH_RSMRST#

S3@

R426 0_0402_5%

1 2

DPWROK

@

R421 0_0402_5%

T15 PAD

@

R973

@R973

@

1 2

0_0402_5%

T51 PAD

@

NC

D

FDI_CTX_PRX_N0 <4> FDI_CTX_PRX_N1 <4> FDI_CTX_PRX_N2 <4> FDI_CTX_PRX_N3 <4> FDI_CTX_PRX_N4 <4> FDI_CTX_PRX_N5 <4> FDI_CTX_PRX_N6 <4> FDI_CTX_PRX_N7 <4>

FDI_CTX_PRX_P0 <4> FDI_CTX_PRX_P1 <4> FDI_CTX_PRX_P2 <4> FDI_CTX_PRX_P3 <4> FDI_CTX_PRX_P4 <4> FDI_CTX_PRX_P5 <4> FDI_CTX_PRX_P6 <4> FDI_CTX_PRX_P7 <4>

FDI_INT <4>

FDI_FSYNC0 <4>

FDI_FSYNC1 <4>

FDI_LSYNC0 <4>

FDI_LSYNC1 <4>

DPWROK <32>

PCH_PCIE_WAKE# <24,28>

CLKRUN# <3 0>

No use PH 10K +3VS

PM_SLP_S5# <32>

PM_SLP_S4# <32>

PM_SLP_S3# <32>

SLP_SUS# <32>

H_PM_SYNC <5>

No use PH 10K +3VALW

SUSCLK <32>

Can be left NC when IAMT is not support on the platfrom

not support Deep S4,S5 can NC PCH EDS1.2 P.74

E

+RTCVCC

1 2

12

R463

100K_0402_5%

+VCCSUS3_3

+3VS

DSWODVREN

*

not support Deep S4,S5 DPWROK mux with RSMRST# check list1.0 P.42

PCH_PCIE_WAKE#

PCH_GPIO29

CLKRUN#

R361 330K_0402_5%R361 330K_0402_5%

R360 330K_0402_5%@R360 330K_0402_5%@

DSWODVREN - On Die DSW VR Enable

H

：：：：

Enable internal DSW +1.05VS

L

：：：：

Disable

Must always PH at +RTCVCC

CRB=>1k ohm Follow Check Li st R1.5

R656 10K_0402_5%R656 10K_0402_5%

R395 10K_0402_5%@R395 10K_0402_5%@

R653 8.2K_0402_5%R653 8.2K_0402_5%

DPWROK

3 3

tell PCH all power ok but cpu core

PCH_PWROK<32>

4 4

A

VGATE<43>

12

R680

R680 10K_0402_5%

10K_0402_5%

VGATE VGATE

1

C790

C790 100P_0402_50V8J

100P_0402_50V8J

2

+3VS

5

U39

2

B

1

A

3

ALL power OK

P

4

SYS_PWROK

Y

G

MC74VHC1G08DFT2G_SC70-5

1

C791

C791 100P_0201_25V8J

100P_0201_25V8J

2

12

R681

R681 10K_0402_5%

10K_0402_5%

B

1

C603

.047U_0402_16V7K

2

@

SYS_PWROK <5>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

SYS_PWROK

1

C789

C789 100P_0402_50V8J

100P_0402_50V8J

2

Compal Secret Data

2012/4/6 2013/4/6

C

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PCH (3/8) DMI,FDI,PM

Q3ZMC M/B LA-8481P Schematic

E

15 51Thursday, April 12, 2012

1.0

A

B

C

D

E

UMA Panel Backlight ON/OFF

ENBKL<32>

R612 0_0402_5%@R612 0_0402_5%@

12

PD 100K at EC side

1 1

2 2

3 3

IGPU_BKLT_ENENBKL

U37D

PCH_ENVDD<22 >

DPST_PWM<22>

IGPU_BKLT_EN

Delete LVDS function

LVDS disable: DATA/Clock/Control can NC VCC_TX_LVDS,VCCA_LVDS connected to GND

CRT disable: DATA/Clock/Control can NC DAC_IREF still need PD VCCADAC connected to +3VS

CRT_IREF

For CRT diable =>Change 1K 0.5% to 5%

1K_0402_5%

R307

12

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

COUGARPOINT_FCBGA989~D

HM77@

SDVO_TVCLKINN

SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

CRT

S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO!SA00005AGI0

DDPD_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

SDVO_CTRLDATA strap pull high at level shift page

P38

SDVO_SCLK

M39

SDVO_SDATA

AT49 AT47 AT40

PCH_DPB_HPD

AV42

PCH_DPB_N0

AV40

PCH_DPB_P0

AV45

PCH_DPB_N1

AV46

PCH_DPB_P1

AU48

PCH_DPB_N2

AU47

PCH_DPB_P2

AV47

PCH_DPB_N3

AV49

PCH_DPB_P3

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43

PCH_DPD_CLK

M36

PCH_DPD_DAT

AT45

PCH_DPD_AUXN

AT43

PCH_DPD_AUXP

BH41

DPD_HPD

BB43

PCH_DPD_N0

BB45

PCH_DPD_P0

BF44

PCH_DPD_N1

BE44

PCH_DPD_P1

BF42

PCH_DPD_N2

BE42

PCH_DPD_P2

BJ42

PCH_DPD_N3

BG42

PCH_DPD_P3

SDVO_SCLK < 23> SDVO_SDATA <23>

PCH_DPB_HPD <2 3>

PCH_DPB_N0 <23> PCH_DPB_P0 <23> PCH_DPB_N1 <23> PCH_DPB_P1 <23> PCH_DPB_N2 <23> PCH_DPB_P2 <23> PCH_DPB_N3 <23> PCH_DPB_P3 <23>

PCH_DPD_CLK <2 5> PCH_DPD_DAT <25>

PCH_DPD_AUXN <24>

PCH_DPD_AUXP <24> DPD_HPD <24>

PCH_DPD_N0 <24> PCH_DPD_P0 <24> PCH_DPD_N1 <24> PCH_DPD_P1 <24> PCH_DPD_N2 <24> PCH_DPD_P2 <24> PCH_DPD_N3 <24> PCH_DPD_P3 <24>

HDMI D2

HDMI D1

HDMI D0

HDMI CLK

Thunderbolt

+3VS

1 2

R252 2.2K_0402_5 %R252 2.2K_0402_5 %

1 2

R254 2.2K_0402_5 %R254 2.2K_0402_5 %

4 4

Security Classification

2012/4/6 2013/4/6

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

2012/4/6 2013/4/6

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PCH (4/9) LVDS,CRT,DP,HDMI

Q3ZMC M/B LA-8481P Schematic

PCH_DPD_CLK

PCH_DPD_DAT

1.0

16 51Thursday, April 12 , 2012

E

A

+3VS

1 2

R423 8.2K_0402_5%R423 8.2K_0402_5%

1 2

R428 8.2K_0402_5%R428 8.2K_0402_5%

1 2

R431 8.2K_0402_5%R431 8.2K_0402_5%

1 2

R432 8.2K_0402_5%R432 8.2K_0402_5%

1 1

2 2

1 2

R433 8.2K_0402_5%R433 8.2K_0402_5%

1 2

R434 8.2K_0402_5%R434 8.2K_0402_5%

1 2

R435 8.2K_0402_5%R435 8.2K_0402_5%

1 2

R439 8.2K_0402_5%R439 8.2K_0402_5%

1 2

R442 8.2K_0402_5%R442 8.2K_0402_5%

1 2

R443 8.2K_0402_5%R443 8.2K_0402_5%

1 2

R444 8.2K_0402_5%R444 8.2K_0402_5%

1 2

R445 8.2K_0402_5%R445 8.2K_0402_5%

+3VS

1 2

R267 10K_0402_5%R267 10K_0402_5%

+3VS

1 2

R310 8.2K_0402_5%R310 8.2K_0402_5%

Boot BIOS Strap

GPIO51GPIO19

Bit11

GNT1#/ GPIO51

Internal PH

Used as GPIO only. External pull-up of

Only GPIO function

3 3

4 4

8.2 kOhms to 10 kOhms to +V3.3S required.

Used as GPIO only.

無無無無無無無無

IRST_RST#<32>

Bit10

0 1

1

0

1 1

00

PH(Internal PH),

PLT_RST#

IRST_RST#

PCI_PIRQC# PCI_PIRQB#

PCI_PIRQA#

PCI_PIRQD#

PCH_GPIO55 PCH_GPIO53 PCH_GPIO52

PCH_GPIO5

PCH_GPIO51 PCH_GPIO2 ODD_DA# PCH_GPIO4

DGPU_PWR_EN

DGPU_HOLD_RST#

Boot BIOS Destination

Reserved

PCI

SPI

*

LPC

如如如如如如如如

GPIO PH +3VS

CLK_PCI_LPBACK<14>

CLK_PCI_LPC<32>

CLK_PCI_TXM<30>

1 2

IRST_RST_R#

MC74VHC1G08DFT2G_SC70-5

R462 0_0402_5%@R462 0_0402_5%@

R461 0_0402_5%R461 0_0402_5%

USB3.0

0_0402_5%

U26

2

B

1

A

R371

+3VS

CLK_PCI_LPBACK CLK_PCI_LPC CLK_PCI_TXM

12

@

5

P

Y

G

3

PCH_USB3_RX1_N<31> PCH_USB3_RX2_N<31>

PCH_USB3_RX1_P<31> PCH_USB3_RX2_P<31>

PCH_USB3_TX1_N<31> PCH_USB3_TX2_N<31>

PCH_USB3_TX1_P<31> PCH_USB3_TX2_P<31>

PCI Interrupt Requests

R604 22_0402_5%R604 22_0402_5% R316 22_0402_5%R316 22_0402_5% R327 22_0402_5%R327 22_0402_5%

4

12

R376

100K_0402_5%

B

PLT_RST#<22,24,30,32,5>

1 2 1 2

PCH_USB3_RX1_N PCH_USB3_RX2_N

PCH_USB3_RX1_P PCH_USB3_RX2_P

PCH_USB3_TX1_N PCH_USB3_TX2_N

PCH_USB3_TX1_P PCH_USB3_TX2_P

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

DGPU_HOLD_RST# PCH_GPIO52 DGPU_PWR_EN

PCH_GPIO51 PCH_GPIO53 PCH_GPIO55

PCH_GPIO2 ODD_DA# PCH_GPIO4 PCH_GPIO5

T13PAD @T13PAD @

PLT_RST#

12

T7PAD @T7PAD @ T8PAD @T8PAD @

PLT_RST_BUF# <28>

CLK_PCI0 CLK_PCI1 CLK_PCI2 CLK_PCI3 CLK_PCI4

U37E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28:USB3Rn1

BE28

TP25

BC30:USB3Rn2

BC30

TP26

BE32:USB3Rn3

BE32

TP27

BJ32:USB3Rn4

BJ32

TP28

BC28:USB3Rp1

BC28

TP29

BE30:USB3Rp2

BE30

TP30

BF32:USB3Rp3

BF32

TP31

BG32:USB3Rp4

BG32

TP32

AV26:USB3Tn1

AV26

TP33

BB26:USB3Tn2

BB26

TP34

AU28:USB3Tn3

AU28

TP35

AY30:USB3Tn4

AY30

TP36

AU26:USB3Tp1

AU26

AY26:USB3Tp2

TP37

AY26

AV28:USB3Tp3

TP38

AV28

AW30:USB3Tp4

TP39

AW30

TP40

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

COUGARPOINT_FCBGA989~D

HM77@

C

AY7

NV_CE#0

AV7

NV_CE#1

AU3

NV_CE#2

BG4

NV_CE#3

AT10

NV_DQS0

BC8

NV_DQS1

NV_ALE NV_CLE

NV_RCOMP

NV_RB#

USBP0N

USBP0P

USBP1N

USBP1P

USBP2N

USBP2P

USBP3N

USBP3P

USBP4N

USBP4P

USBP5N

USBP5P

USBP6N

USBP6P

USBP7N

USBP7P

USBP8N

USBP8P

USBP9N

USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

AV5 AY1

DF_TVS

AV10

AT8

AY5 BA2

AT12 BF3

C24

USB20_N0

A24

USB20_P0

C25

USB20_N1

B25

USB20_P1

C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28

Some PCH config not support USB port 6 & 7.

M28 L30

USB20_N8

K30

USB20_P8

G30

USB20_N9

E30

USB20_P9

C30

USB20_N10

A30

USB20_P10

L32 K32 G32 E32 C32 A32

C33

USBRBIAS

B33

A14

USB_OC0#

K20

USB_OC1#

B17

USB_OC2#

C16

USB_OC3#

L16

USB_OC4#

A16

USB_OC5#

D14

USB_OC6#

C14

USB_OC7#

NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8 NV_DQ9 / NV_IO9

NV_DQ10 / NV_IO10

NVRAM

NV_DQ11 / NV_IO11 NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15

RSVD

NV_RE#_WRB0 NV_RE#_WRB1

NV_WE#_CK0 NV_WE#_CK1

PCI

USB

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43

OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO!SA00005AGI0

DMI,FDI Termination Voltage

DF_TVS

DG1.2 CRB1.0 PH 2.2K series 1K For 2012 support

R654 1K_0402_5%R654 1K_0402_5%

Set to Vcc when HIGH

Set to Vss when LOW

+1.8VS

12

CLOSE TO THE BRANCHING POINT

USB20_N0 <31> USB20_P0 <31> USB20_N1 <31> USB20_P1 <31>

USB3 ( side)

USB20_N8 <28> USB20_P8 <28> USB20_N9 <31> USB20_P9 <31> USB20_N10 <22> USB20_P10 <22>

WLAN USB(Bluetooth)

Debug Port

CMOS Camera (LVDS)

Mini Card (mSATA)

1 2

R620 22.6_0402_1%R620 22.6_0402_1%

Within 500 mils

USB_OC0# <31>

12

R651

2.2K_0402_5%

D

H_SNB_IVB# <5>

EHCI 1

EHCI 2

USB_OC0#

USB_OC2#

USB_OC7#

USB_OC5#

USB_OC1#

USB_OC4#

USB_OC3#

USB_OC6#

E

R384 10K_0402_5%R384 10K_0402_5%

R401 10K_0402_5%R401 10K_0402_5%

R374 10K_0402_5%R374 10K_0402_5%

R379 10K_0402_5%R379 10K_0402_5%

R448 10K_0402_5%R448 10K_0402_5%

R447 10K_0402_5%R447 10K_0402_5%

R386 10K_0402_5%R386 10K_0402_5%

R446 10K_0402_5%R446 10K_0402_5%

12

+VCCSUS3_3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

C

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PCH (5/9) PCI, USB, NVRAM

Q3ZMC M/B LA-8481P Schematic

E

17 51Thursday, April 12, 2012

1.0

A

HDA_SYNC PH(PLL =+1.5VS)

GPIO28

On-Die PLL Voltage Regulator

This signal has a weak internal pull up

H

：：：：

On-Die PLL voltage regulator enable

*

L

：：：：

On-Die PLL Voltage Regulator disable

+VCCSUS3_3

1 1

Deep S4,S5 wake event signal RTC alarm,Power BTN,GPIO27 PCH_GPIO27 (Have internal Pull-High) Deep S4,S5 wake event signal No use PD to GND,HR Check list1.0 P.70

2 2

12

R422

4.7K_0402_5%

PCH_GPIO28

R417

@

1K_0402_5%

1 2

Debug Port DG 1.2 PH 4.7K +3VALW_PCH

1 2

R362 10K_0402_5%R362 10K_0402_5%

HR Check List

1 2

R363 10K_0402_5%R363 10K_0402_5%

1 2

R364 10K_0402_5%R364 10K_0402_5%

PCH_GPIO27

ODD_DETECT#

WWAN_OFF#

No use PH 10K +3VS

No use PH +3VALW

No use PH +3VS

No use PH 10K +3VS

CRB1.0 PH 10K +3VALW

No use PD 10K to GND

No use PH 10K +3VALW

No use PH 10K +3VS

No use can NC(+3VS power plane)

Can't PH

SATA2GP/GPIO36,SATA3GP/GPIO37

1.Used as for Mechanical Presence detect Use a weak external pull-up (150K-200k Ohms) to Vcc3_3 or use 10K external pull-up that is enabled only after PLTRST# de-assertion.

2.Used as GP Input (Pin HW default) Ensure GPI is not driven high during strap sampling window

3.Unused as GPIO or SATA*GP Use 8.2K-10K pull-down to ground.

+3VS

1 2

R406 10K_0402_5%@R406 10K_0402_5%@

1 2

R614 10K_0402_5%R614 10K_0402_5%

3 3

1 2

R326 10K_0402_5%R326 10K_0402_5%

1 2

R663 10K_0402_5%R663 10K_0402_5%

1 2

R305 10K_0402_5%R305 10K_0402_5%

TB_PLUG_EVENT

PCH_GPIO1

DGPU_HPD_INT#

MSATA_DET#

DGPU_PWROK

No use PH 10K +3VS

SATA5GP&TEMP_ALERT# CRB PH 10K +3VS

No use PH +3VALW

+3VS

UMA@

1 2

R429 10K_0402_5%

@

1 2

R430 10K_0402_5%

Muxless

*

nonMuxless

1 2

R675 10K_0402_5%R675 10K_0402_5%

1 2

R679 10K_0402_5%R679 10K_0402_5%

1 2

R404 10K_0402_5%R404 10K_0402_5%

+VCCSUS3_3

1 2

R657 10K_0402_5%@R657 10K_0402_5%@

1 2

R391 1K_0402_5%R391 1K_0402_5%

4 4

1 2

R397 10K_0402_5%R397 10K_0402_5%

GPIO24 Unmultiplexed NOTE: GPIO24 configuration register bits are not cleared by CF9h reset event. CRB1.0 PH10K to +3VALW

PCH_GPIO34

PCH_GPIO48

TB_SMB_CK_GPIO7

TB_FORCE_PWR

EC_LID_OUT#

PCH_GPIO57

A

Define Q5LJ1(DDR3) or Q3ZMC(DDR3L)

+VCCSUS3_3

1 2

R458 10K_0402_5%

DDR3@

1 2

R457 10K_0402_5%

DDR3L@

*

DDR3L(Q3ZMC) DDR3

GPIO36/GPIO37 is Strap functionality that requires internal pull down to be sampled at rising PWROK. When uses as SATA2GP/SATA3GP for mechanical presence detect

-use a external pull up 150K-200K ohm to Vcc3_3 When used as GP input

-ensure GPI is not driven high during strap sampling window When Unused as GPIO or SATA*GP

-use 8.2K-10K pull-down check list page 47

B

TB_PLUG_EVENT<24>

EC_SCI#<32>

EC_SMI#<32>

EC LID SW OUT

TB_FORCE_PWR<24>

EC_LID_OUT#<32>

MSATA_DET#<29>

RAID0_DET<29>

Optimus(L)/ non optimus(H)

TB_SMB_CK_GPIO7<24>

OPTIMUS_EN#

GPIO38

OPTIMUS_EN#

0 1

PCH_GPIO24

GPIO24

PCH_GPIO24

0 1

B

TB_PLUG_EVENT

PCH_GPIO1

DGPU_HPD_INT#

EC_SCI#

EC_SMI#

TB_FORCE_PWR

EC_LID_OUT#

MSATA_DET#

DGPU_PWROK

PCH_GPIO22

PCH_GPIO24

PCH_GPIO27

PCH_GPIO28

PCH_GPIO34

RAID0_DET

ODD_DETECT#

WWAN_OFF#

OPTIMUS_EN#

PCH_GPIO39

PCH_GPIO48

TB_SMB_CK_GPIO7

PCH_GPIO57

C

LVDS/eDP

LVDS

GPIO71

1

eDP 0

PECI

RCIN#

NC_1

NC_2

NC_3

NC_4

NC_5

PCH_GPIO71

C40

B41

C41

A40

P4

AU16

P5

AY11

AY10

T14

AH8

AK11

AH10

AK10

P37

BG2

BG48

BH3

BH47

BJ4

BJ44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

F1

F49

For eDP only,

不不不

eDP or LVDS

U37F

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24 / MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

COUGARPOINT_FCBGA989~D

HM77@

S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO!SA00005AGI0

Remove NCTF test point 2011/9/23

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

TACH4 / GPIO68

TACH5 / GPIO69

TACH6 / GPIO70

TACH7 / GPIO71

A20GATE

PROCPWRGD

GPIO

THRMTRIP#

CPU/MISC

INIT3_3V#

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

NCTF

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

2012/4/6 2013/4/6

+3VS

12

@

R615

10K_0402_5%

@

R618

10K_0402_5%

1 2

ODD_EN#

PCH_GPIO69

PCH_GPIO70

PCH_GPIO71

PCH_PECI_R

EC_KBRST#

PCH_THRMTRIP#_R

Compal Secret Data

Deciphered Date

D

R616

@R616

@

10K_0402_5%

PCH_GPIO69 PCH_GPIO70

R619

10K_0402_5%

+3VS

R419

R419 10K_0402_5%

10K_0402_5%

1 2

@

R2480_0402_5%@R2480_0402_5%

1 2

R385 390_0402_5%R385 390_0402_5%

INIT3_3V

This signal has weak internal PU, can't pull low,leave NC

TS_VSS1~4 PD to GND

H_PECI <32,5>

EC_KBRST# <32>

H_CPUPWRGD <5>

H_THRMTRIP#

Check list1.0 P.59

Elpida DDP 1GB*8 (Ch A,B) Elpida DDP 1GB*4 (Ch A) Elpida Mono 512MB*8(Ch A,B) Hynix Mono 512MB*8(Ch A,B)

D

+3VS +3VS

12

1 2

R617

@R617

@

10K_0402_5%

R621

10K_0402_5%

+3VS

GATEA20 <32>

R274 10K_0402_5%X76@R274 10K_0402_5%X76@

R275 10K_0402_5%X76@R275 10K_0402_5%X76@

R278 10K_0402_5%X76@R278 10K_0402_5%X76@

R279 10K_0402_5%X76@R279 10K_0402_5%X76@

R281 10K_0402_5%X76@R281 10K_0402_5%X76@

R282 10K_0402_5%X76@R282 10K_0402_5%X76@

E

Project ID GPIO70

*

12

x x x x

1 2

GPIO69

0 0 1

0 1 0 11

PECI CPU-EC

CTRL+ALT+DEL

non CPU power ok

ODD_EN#

EC_KBRST#

130c shut sown

1 2

R324 10K_0402_5%R324 10K_0402_5%

1 2

R420 10K_0402_5%R420 10K_0402_5%

+3VS

H_THRMTRIP# <5>

GPIO22GPIO23GPIO39

0 0 0

0 0 1

0 1 1

1 2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PCH (6/9) GPIO, CPU, MISC

Q3ZMC M/B LA-8481P Schematic

PCH_GPIO22

PCH_GPIO23

PCH_GPIO39

E

PCH_GPIO23 <13>

18 51Thursday, April 12, 2012

0 1 0

1.0

A

+1.05VS_VCCPP

1 1

J3

@

J3

@

12

PAD-OPEN 4x4m

JUMP_43X79

+1.05VS_PCH +VCCADAC

C505

0.1U_0201_10V6K

C505

C754

10U_0603_6.3V6M

C754

10U_0603_6.3V6M

C519

1U_0201_4V6M

C519

1U_0201_4V6M

1

12

2

0.1U_0201_10V6K

C517

1U_0201_4V6M

C517

1U_0201_4V6M

1

2

Place Near AA23

+1.05VS_PCH

+VCCAPLLEXP

T33PAD @T33PAD @

On-Die PLL Voltage Regulator

H

：：：：

On-Die PLL voltage regulator enable

VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,VCCAPLLSATA

2 2

3 3

On-Die PLL Voltage Regulator

H

VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,VCCAPLLSATA

4 4

+1.05VS_PCH

C543

10U_0603_6.3V6M

C543

10U_0603_6.3V6M

C496

1U_0201_4V6M@C496

1U_0201_4V6M

1

2

+3VS

：：：：

On-Die PLL voltage regulator enable

@

2

Place Near AN16,AN21,AN33

Place Near BH29

A

C486

1U_0201_4V6M

C486

1U_0201_4V6M

1

2

1

C749

0.1U_0201_10V6K

2

+VCCAFDI_VRM

@

T14PAD@T14PAD

C474

1U_0201_4V6M

C474

1U_0201_4V6M

1

2

+1.05VS_VCCAPLL_FDI

+1.05VS_PCH

C492

1U_0201_4V6M

C492

1U_0201_4V6M

1

C491

C491 1U_0201_4V6M

1U_0201_4V6M

2

Near AU20

Trace 20mil

U37G

PPT:1700mA CPT:1300mA

AA23

VCCCORE[1]

AC23

VCCCORE[2]

AD21

VCCCORE[3]

AD23

VCCCORE[4]

AF21

VCCCORE[5]

AF23

VCCCORE[6]

AG21

VCCCORE[7]

AG23

VCCCORE[8]

AG24

VCCCORE[9]

AG26

VCCCORE[10]

AG27

VCCCORE[11]

AG29

VCCCORE[12]

AJ23

VCCCORE[13]

AJ26

VCCCORE[14]

AJ27

VCCCORE[15]

AJ29

VCCCORE[16]

AJ31

VCCCORE[17]

AN19

VCCIO[28]

BJ22

VCCAPLLEXP

AN16

VCCIO[15]

AN17

VCCIO[16]

PPT:3711mA CPT:3709mA

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29

VCC3_3[3]

AP16

VCCVRM[2]

BG6

VCCFDIPLL

AP17

VCCIO[27]

AU20

VCCDMI[2]

COUGARPOINT_FCBGA989~D

SA00005AGI0

SA00005AGI0 HM77@

HM77@

+1.5VS

VCCVRM==>1.5V FOR MOBILE VCCVRM==>1.8V FOR DESKTOP VCCVRM = 160mA detal waiting for newest spec

配配配配

HDA_SYNC PH(PLL =+1.5VS)

B

Thermal Senser share with VCCADAC power rail so can't remove this power

POWER

PPT:63mA CPT:1mA

CRTLVDS

1mA

VCC CORE

VCCTX_LVDS[1]

VCCTX_LVDS[2]

VCCTX_LVDS[3]

40mA

VCCTX_LVDS[4]

228mA

PPT:167mA CPT:175mA

PPT:47mA CPT:42mA

DMI

VCCIO

VCCPNAND[1]

2mA

VCCPNAND[2]

VCCPNAND[3]

VCCPNAND[4]

NAND / SPI HVCMOS

10mA

FDI

S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO!

1 2

R394 0_0402_5%@R394 0_0402_5 %@

B

U48

VCCADAC

U47

VSSADAC

AK36

VCCALVDS

AK37

VSSALVDS

AM37

AM38

AP36

AP37

V33

VCC3_3[6]

V34

VCC3_3[7]

AT16

VCCVRM[3]

AT20

VCCDMI[1]

AB36

VCCIO[1]

AG16

AG17

AJ16

AJ17

VCCPNAND change to VccDFTERM

V1

VCCSPI

+VCCAFDI_VRM

0.01U_0402_16V7K

+VCCA_LVDS

+3VS

1

2

+1.05VS_PCH

1

C480

C480 1U_0201_4V6M

1U_0201_4V6M

place

2

near AB36

+1.8VS

1

2

+3VS

1

C770

C770 1U_0402_6.3V6K

1U_0402_6.3V6K

2

+VCCAFDI_VRM

Place Near U48

1

C419

2

12

R270

R270 0_0402_5%

0_0402_5%

eDP@

Place Near AM37

Place Near V33

C449

0.1U_0201_10V6K

+VCCAFDI_VRM

+1.05VS_PCH

1

C477

C477 1U_0201_4V6M

1U_0201_4V6M

2

C523

0.1U_0201_10V6K

place near AG16

C

C420

.1U_0402_16V7K

MBK1608221YZF_2P

1

C418

C418 10U_0603_6.3V6M

10U_0603_6.3V6M

2

1 2

R272 0_0402_5%LVDS@R272 0_0402_5%LVDS@

L23

+3VS

12

+3VS

+VCCTX_LVDS

12

R280

R280 0_0402_5%

0_0402_5%

eDP@

1 2

R271 0_040 2_5%LVDS@R271 0_0402_5%LVDS@

D

+1.8VS

I/O Buffer Voltage

PCH Power Rail Table

Voltage

1.05

5

3.3

1.05

3.3

S0 Iccmax Current(A)

0.001

0.266

0.001

0.08

1.3

0.042

Trace 20mil

place near AT20

Internal PLL and VRM(+1.5VS)

DMI buffer logic

Core Well I/O Buffer

VccDFTERM should PH +1.8VS or +3VS

For SPI control logi

Voltage Rail

V_PROC_IO

V5REF

V5REF_Sus

Vcc3_3

VccADAC

VccADPLLA

VccADPLLB

VccCore

VccDMI

VccIO 2.925

VccASW 1.01

VccSPI 0.02

VccDSW 0.003

1.8 0.19VccpNAND

VccRTC 6 uA

VccSus3_3

3.3

0.266

3.3

3.3 / 1.5VccSusHDA

0.01

VccVRM 1.8 / 1.5 0.16

VccCLKDMI

VccSSC 0.095

VccDIFFCLKN 0.055

VccALVDS

VccTX_LVDS 0.06

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

D

1.05

3.3

1.8

0.02

0.001

E

Processor I/F

PCH Core Well Reference Voltage

Suspend Well Reference Voltag

I/O Buffer Voltage

Display DAC Analog Power. This power is supplied by the core well.

Display PLL A power

Display PLL B power

Internal Logic Voltage

DMI Buffer Voltage

Core Well I/O buffers

1.05 V Supply for Intel R Management Engine and Integrated LAN

3.3 V Supply for SPI Controller Logic

3.3v supply for Deep S4/S5 well

1.8V power supply for DF_TVS

Battery Voltage

Suspend Well I/O Buffer Voltage

High Definition Audio Controller Suspend Voltage

1.8 V Internal PLL and VRMs (1.8 V for Desktop)

DMI Clock Buffer Voltage

Spread Modulators Power Supply

Differential Clock Buffers Power Supply

Analog power supply for LVDS (Mobile Only) Analog power supply for LVDS (Mobile Only)

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PCH (7/9) PWR

Q3ZMC M/B LA-8481P Schematic

E

19 51Thursday, April 12, 2012

1.0

A

+3VS

L26

10UH_LB2012T100MR_20%

1 2

10U_0603_6.3V6M

1 1

C465

+3VS_VCC_CLKF33

1

2

Near T38

+1.05V analog internal clock PLL Can NC

C440

1U_0402_6.3V6K

C440

1U_0402_6.3V6K

1

Not support Deep S4,S5 connect to +3VALW

2

suppied by internal

1.05V VR must NC

GPIO28

On-Die PLL Voltage Regulator

H

：：：：

On-Die PLL voltage regulator enable

,VCCAPLLSATA

2 2

+1.05VS_PCH

3 3

+1.05VS_PCH

C524

1

1U_0201_4V6M

Place

2

near AF17

isolation between SSC (AG33) and DIFFCLKN(AF33,AF34,AG34) 18mil width(DIFFCLKN) 10mil (SSC)

4 4

L54

10UH_LB2012T100MR_20%

1 2

L49

10UH_LB2012T100MR_20%

+1.05VS_PCH

+1.05VS_VCCA_A_DPL

C751

22U_0805_6.3V6M

C751

22U_0805_6.3V6M

1

2

+1.05VS_VCCA_B_DPL

C752

22U_0805_6.3V6M

C752

22U_0805_6.3V6M

1

2

C467

1

1U_0201_4V6M

Place

2

near AF33, AF34,AG34

A

C426

1U_0201_4V6M

C426

1U_0201_4V6M

1

Near BD47

2

C429

1U_0201_4V6M

C429

1U_0201_4V6M

1

Near BF47

2

suppied by internal

1.05V VR Must NC

suppied by internal

1.05V VR must NC

+1.05VS_PCH

C476

1

1U_0201_4V6M

Place

2

near AG33

Near N16

C521 0.1U_0201_10V6KC521 0.1U_0201_10V6K

VCCIO[8,9, 11] change to VccDIF FCLKN VCCIO[10] change to VccSSC

Near V16

+1.05VS_PCH

4.7U_0603_6.3V6K

1

2

Place near BJ8

+1.05VS_PCH

1

2

C544

0.1U_0201_10V6K

1

2

B

+1.05VS_PCH

+3VALW_PCH

T12PAD @T12PAD @

T32PAD @T32PAD @

T9PAD @T9PAD @

C518

1U_0201_4V6M

C518

1U_0201_4V6M

Near AA19

12

+VCCAFDI_VRM

C537

0.1U_0201_10V6K

1

2

B

R273

@R273

@

1 2

0_0402_5%

1

C520

0.1U_0201_10V6K

2

Near T16

+PCH_VCCDSW

+3VS_VCC_CLKF33

+VCCAPLL_CPY_PCH

+1.05VS_PCH

+VCCSUS1

C547

22U_0805_6.3V6M

C547

22U_0805_6.3V6M

C552

22U_0805_6.3V6M

C552

22U_0805_6.3V6M

1

2

C513

1U_0201_4V6M

C513

1U_0201_4V6M

C478

1U_0201_4V6M@C478

1U_0201_4V6M

1

@

2

+VCCRTCEXT

+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DPL

C526 0.1U_0201_10V6KC526 0.1U_0201_10V6K

+1.05VM_VCCSUS

T10PAD@T10PAD

@

C541

+RTCVCC

C493

1U_0402_6.3V6K

C493

1U_0402_6.3V6K

1

2

Near A22

12

1

2

+VCCACLK

+VCCSST

C494

0.1U_0201_10V6K

C494

0.1U_0201_10V6K

AD49

T16

V12

T38

BH23

AL29

AL24

AA19

AA21

AA24

AA26

AA27

AA29

AA31

AC26

AC27

AC29

AC31

AD29

AD31

W21

W23

W24

W26

W29

W31

W33

N16

Y49

BD47

BF47

AF17 AF33 AF34

AG34

AG33

V16

T17 V19

BJ8

A22

C495

0.1U_0201_10V6K

C495

0.1U_0201_10V6K

1

2

POWER

1mA

POWER

1mA

Deep S3 PPT:126mA CPT:119mA

903mA

Clock and Miscellaneous

PPT:80mA CPT:75mA

55mA

95mA

CPURTC

S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO!SA00005AGI0

U37J

VCCACLK

VCCDSW3_3

DCPSUSBYP

VCC3_3[5]

VCCAPLLDMI2

VCCIO[14]

DCPSUS[3]

VCCASW[1]

VCCASW[2]

VCCASW[3]

VCCASW[4]

VCCASW[5]

VCCASW[6]

VCCASW[7]

VCCASW[8]

VCCASW[9]

VCCASW[10]

VCCASW[11]

VCCASW[12]

VCCASW[13]

VCCASW[14]

VCCASW[15]

VCCASW[16]

VCCASW[17]

VCCASW[18]

VCCASW[19]

VCCASW[20]

DCPRTC

VCCVRM[4]

VCCADPLLA

VCCADPLLB

VCCIO[7] VCCIO[8] VCCIO[9] VCCIO[11]

VCCIO[10]

DCPSST

DCPSUS[1] DCPSUS[2]

V_PROC_IO

VCCRTC

COUGARPOINT_FCBGA989~D

HM77@

PCI/GPIO/LPCMISC

SATA USB

HDA

1mA

10mA

C

VCCIO[29]

VCCIO[30]

VCCIO[31]

VCCIO[32]

VCCIO[33]

VCCSUS3_3[7]

VCCSUS3_3[8]

VCCSUS3_3[9]

VCCSUS3_3[10]

VCCSUS3_3[6]

VCCIO[34]

V5REF_SUS

DCPSUS[4]

VCCSUS3_3[1]

1mA

VCCSUS3_3[2]

VCCSUS3_3[3]

VCCSUS3_3[4]

VCCSUS3_3[5]

VCC3_3[1]

VCC3_3[8]

VCC3_3[4]

VCC3_3[2]

VCCIO[5]

VCCIO[12]

VCCIO[13]

VCCIO[6]

VCCAPLLSATA

VCCVRM[1]

VCCIO[2]

VCCIO[3]

VCCIO[4]

VCCASW[22]

VCCASW[23]

VCCASW[21]

VCCSUSHDA

V5REF

N26

P26

P28

T27

T29

T23

T24

V23

V24

P24

T26

M26

AN23

AN24

P34

N20

N22

P20

P22

AA16

W16

T34

AJ2

AF13

AH13

AH14

AF14

AK1

AF11

AC16

AC17

AD17

T21

V21

T19

P32

+1.05VS_PCH

1

2

1

C490

0.1U_0201_10V6K

2

+1.05VS_PCH

+PCH_V5REF_SUS

+VCCA_USBSUS

+VCCSUS3_3

+PCH_V5REF_RUN

+1.05VS_PCH

+VCCSATAPLL

+1.05VS_PCH

1

C473

0.1U_0201_10V6K

2

C468

C468 1U_0201_4V6M

1U_0201_4V6M

PCH_PWR_EN#<35>

Near N26

1

C497

0.1U_0201_10V6K

2

Near M26

T11 PAD @

PAD @

1

C501

0.1U_0201_10V6K

2

1

C771

0.1U_0201_10V6K

Place near

2

AJ2

Near AH13,AH14,AF13

1

C533

C533 1U_0201_4V6M

1U_0201_4V6M

2

+VCCAFDI_VRM

Near N20

T48 PAD@ T48 PAD@

0.1U_0402_16V4Z

+VCCSUS3_3

1 2

C484

T11

Near AC16

1

C482

C482 1U_0201_4V6M

1U_0201_4V6M

2

Near P24Near T23VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2

suppied by internal

1.05V VR Must NC

1

2

D

+3VALW

AP2301GN-HF_SOT23-3 DS3@

+VCCSUS3_3

RB751V-40_SOD323-2

C522

0.1U_0201_10V6K

Place near AA16,W16

+1.05VS_PCH

+VCCSUS3_3

For Deep SX turn off +V5REF_SUS,+VCCSUS3_3

+VCCSUS3_3

3 1

Q68

C819

21

1

C471

0.1U_0201_10V6K

Place near

2

T34

2

1

2

1 2

R756

2.2K_0402_5%

0.01U_0402_16V7K

+VCCSUS3_3 +V5REF_ SUS

D16

+3VS

GPIO28

On-Die PLL Voltage Regulator

H

：：：：

On-Die PLL voltage regulator enable

VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,VCCAPLLSATA

Need +3VALW and 0.1U close PCH

.1U_0402_16V7K

1

2

12

R334

100_0402_5%

RB751V-40_SOD323-2

C817

Near P32

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

D

E

10mil20mil

+V5REF_SUS

C816

.1U_0402_16V7K

C816

.1U_0402_16V7K

1

2

R755

20K_0402_5%

R755

20K_0402_5%

12

C470

1U_0603_10V6K

+5VALW

AP2301GN-HF_SOT23-3 DS3@

PCH_PWR_EN#

0.01U_0402_16V7K

+3VS +5VS

21

12

D14

R321

100_0402_5%

1

2

1 2

R757

1K_0402_5%

3 1

Q64

2

1

C820

2

Near P34

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PCH (8/9) PWR

Q3ZMC M/B LA-8481P Schematic

E

20 51Thursday, April 12, 2012

R752

20K_0402_5%

R752

20K_0402_5%

12

1.0

A

1 1

2 2

3 3

4 4

A

U37H

H5

VSS[0]

AA17

VSS[1]

AA2

VSS[2]

AA3

VSS[3]

AA33

VSS[4]

AA34

VSS[5]

AB11

VSS[6]

AB14

VSS[7]

AB39

VSS[8]

AB4

VSS[9]

AB43

VSS[10]

AB5

VSS[11]

AB7

VSS[12]

AC19

VSS[13]

AC2

VSS[14]

AC21

VSS[15]

AC24

VSS[16]

AC33

VSS[17]

AC34

VSS[18]

AC48

VSS[19]

AD10

VSS[20]

AD11

VSS[21]

AD12

VSS[22]

AD13

VSS[23]

AD19

VSS[24]

AD24

VSS[25]

AD26

VSS[26]

AD27

VSS[27]

AD33

VSS[28]

AD34

VSS[29]

AD36

VSS[30]

AD37

VSS[31]

AD38

VSS[32]

AD39

VSS[33]

AD4

VSS[34]

AD40

VSS[35]

AD42

VSS[36]

AD43

VSS[37]

AD45

VSS[38]

AD46

VSS[39]

AD8

VSS[40]

AE2

VSS[41]

AE3

VSS[42]

AF10

VSS[43]

AF12

VSS[44]

AD14

VSS[45]

AD16

VSS[46]

AF16

VSS[47]

AF19

VSS[48]

AF24

VSS[49]

AF26

VSS[50]

AF27

VSS[51]

AF29

VSS[52]

AF31

VSS[53]

AF38

VSS[54]

AF4

VSS[55]

AF42

VSS[56]

AF46

VSS[57]

AF5

VSS[58]

AF7

VSS[59]

AF8

VSS[60]

AG19

VSS[61]

AG2

VSS[62]

AG31

VSS[63]

AG48

VSS[64]

AH11

VSS[65]

AH3

VSS[66]

AH36

VSS[67]

AH39

VSS[68]

AH40

VSS[69]

AH42

VSS[70]

AH46

VSS[71]

AH7

VSS[72]

AJ19

VSS[73]

AJ21

VSS[74]

AJ24

VSS[75]

AJ33

VSS[76]

AJ34

VSS[77]

AK12

VSS[78]

AK3

VSS[79]

COUGARPOINT_FCBGA989~D

HM77@

S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO!SA00005AGI0

B

U37I

AY4

VSS[159]

AY42

VSS[160]

AY46

VSS[161]

AY8

VSS[162]

B11

VSS[163]

B15

VSS[164]

B19

VSS[165]

B23

VSS[166]

AK38

VSS[80]

AK4

VSS[81]

AK42

VSS[82]

AK46

VSS[83]

AK8

VSS[84]

AL16

VSS[85]

AL17

VSS[86]

AL19

VSS[87]

AL2

VSS[88]

AL21

VSS[89]

AL23

VSS[90]

AL26

VSS[91]

AL27

VSS[92]

AL31

VSS[93]

AL33

VSS[94]

AL34

VSS[95]

AL48

VSS[96]

AM11

VSS[97]

AM14

VSS[98]

AM36

VSS[99]

AM39

VSS[100]

AM43

VSS[101]

AM45

VSS[102]

AM46

VSS[103]

AM7

VSS[104]

AN2

VSS[105]

AN29

VSS[106]

AN3

VSS[107]

AN31

VSS[108]

AP12

VSS[109]

AP19

VSS[110]

AP28

VSS[111]

AP30

VSS[112]

AP32

VSS[113]

AP38

VSS[114]

AP4

VSS[115]

AP42

VSS[116]

AP46

VSS[117]

AP8

VSS[118]

AR2

VSS[119]

AR48

VSS[120]

AT11

VSS[121]

AT13

VSS[122]

AT18

VSS[123]

AT22

VSS[124]

AT26

VSS[125]

AT28

VSS[126]

AT30

VSS[127]

AT32

VSS[128]

AT34

VSS[129]

AT39

VSS[130]

AT42

VSS[131]

AT46

VSS[132]

AT7

VSS[133]

AU24

VSS[134]

AU30

VSS[135]

AV16

VSS[136]

AV20

VSS[137]

AV24

VSS[138]

AV30

VSS[139]

AV38

VSS[140]

AV4

VSS[141]

AV43

VSS[142]

AV8

VSS[143]

AW14

VSS[144]

AW18

VSS[145]

AW2

VSS[146]

AW22

VSS[147]

AW26

VSS[148]

AW28

VSS[149]

AW32

VSS[150]

AW34

VSS[151]

AW36

VSS[152]

AW40

VSS[153]

AW48

VSS[154]

AV11

VSS[155]

AY12

VSS[156]

AY22

VSS[157]

AY28

VSS[158]

B

B27

VSS[167]

B31

VSS[168]

B35

VSS[169]

B39

VSS[170]

B7

VSS[171]

F45

VSS[172]

BB12

VSS[173]

BB16

VSS[174]

BB20

VSS[175]

BB22

VSS[176]

BB24

VSS[177]

BB28

VSS[178]

BB30

VSS[179]

BB38

VSS[180]

BB4

VSS[181]

BB46

VSS[182]

BC14

VSS[183]

BC18

VSS[184]

BC2

VSS[185]

BC22

VSS[186]

BC26

VSS[187]

BC32

VSS[188]

BC34

VSS[189]

BC36

VSS[190]

BC40

VSS[191]

BC42

VSS[192]

BC48

VSS[193]

BD46

VSS[194]

BD5

VSS[195]

BE22

VSS[196]

BE26

VSS[197]

BE40

VSS[198]

BF10

VSS[199]

BF12

VSS[200]

BF16

VSS[201]

BF20

VSS[202]

BF22

VSS[203]

BF24

VSS[204]

BF26

VSS[205]

BF28

VSS[206]

BD3

VSS[207]

BF30

VSS[208]

BF38

VSS[209]

BF40

VSS[210]

BF8

VSS[211]

BG17

VSS[212]

BG21

VSS[213]

BG33

VSS[214]

BG44

VSS[215]

BG8

VSS[216]

BH11

VSS[217]

BH15

VSS[218]

BH17

VSS[219]

BH19

VSS[220]

H10

VSS[221]

BH27

VSS[222]

BH31

VSS[223]

BH33

VSS[224]

BH35

VSS[225]

BH39

VSS[226]

BH43

VSS[227]

BH7

VSS[228]

D3

VSS[229]

D12

VSS[230]

D16

VSS[231]

D18

VSS[232]

D22

VSS[233]

D24

VSS[234]

D26

VSS[235]

D30

VSS[236]

D32

VSS[237]

D34

VSS[238]

D38

VSS[239]

D42

VSS[240]

D8

VSS[241]

E18

VSS[242]

E26

VSS[243]

G18

VSS[244]

G20

VSS[245]

G26

VSS[246]

G28

VSS[247]

G36

VSS[248]

G48

VSS[249]

H12

VSS[250]

H18

VSS[251]

H22

VSS[252]

H24

VSS[253]

H26

VSS[254]

H30

VSS[255]

H32

VSS[256]

H34

VSS[257]

F3

VSS[258]

COUGARPOINT_FCBGA989~D

HM77@

C

H46

VSS[259]

K18

VSS[260]

K26

VSS[261]

K39

VSS[262]

K46

VSS[263]

K7

VSS[264]

L18

VSS[265]

L2

VSS[266]

L20

VSS[267]

L26

VSS[268]

L28

VSS[269]

L36

VSS[270]

L48

VSS[271]

M12

VSS[272]

P16

VSS[273]

M18

VSS[274]

M22

VSS[275]

M24

VSS[276]

M30

VSS[277]

M32

VSS[278]

M34

VSS[279]

M38

VSS[280]

M4

VSS[281]

M42

VSS[282]

M46

VSS[283]

M8

VSS[284]

N18

VSS[285]

P30

VSS[286]

N47

VSS[287]

P11

VSS[288]

P18

VSS[289]

T33

VSS[290]

P40

VSS[291]

P43

VSS[292]

P47

VSS[293]

P7

VSS[294]

R2

VSS[295]

R48

VSS[296]

T12

VSS[297]

T31

VSS[298]

T37

VSS[299]

T4

VSS[300]

W34

VSS[301]

T46

VSS[302]

T47

VSS[303]

T8

VSS[304]

V11

VSS[305]

V17

VSS[306]

V26

VSS[307]

V27

VSS[308]

V29

VSS[309]

V31

VSS[310]

V36

VSS[311]

V39

VSS[312]

V43

VSS[313]

V7

VSS[314]

W17

VSS[315]

W19

VSS[316]

W2

VSS[317]

W27

VSS[318]

W48

VSS[319]

Y12

VSS[320]

Y38

VSS[321]

Y4

VSS[322]

Y42

VSS[323]

Y46

VSS[324]

Y8

VSS[325]

BG29

VSS[328]

N24

VSS[329]

AJ3

VSS[330]

AD47

VSS[331]

B43

VSS[333]

BE10

VSS[334]

BG41

VSS[335]

G14

VSS[337]

H16

VSS[338]

T36

VSS[340]

BG22

VSS[342]

BG24

VSS[343]

C22

VSS[344]

AP13

VSS[345]

M14

VSS[346]

AP3

VSS[347]

AP1

VSS[348]

BE16

VSS[349]

BC16

VSS[350]

BG28

VSS[351]

BJ28

VSS[352]

S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO!SA 00005AGI0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

D

Custom

Date: Sheet of

D

Date: Sheet of

E

Compal Electronics, Inc.

Title

Size Document Number Rev

Compal Electronics, Inc.

PCH (9/9) VSS

Q3ZMC M/B LA-8481P Schematic

E

21 51Thursday, April 12, 2012

1.0

5

4

3

2

1

Panel POWER CIRCUIT

SM010014520 3000ma 220ohm@100mhz DCR 0.04

B+ +INVPW R_B+

FBMA-L11-201 209-221LMA30T_0805

L1

68P_0402_5 0V8J

W=40mils

12

1

C7

2

eDP panel + Card Reader Conn.

20mils

+3VALW

ON/OFFBTN#<33>

LID_SW#<32>

PLT_RST#<1 7,24,30,32,5>

CARD_CLKREQ#<14>

PCIE_PTX_C_DRX_P1<14> PCIE_PTX_C_DRX_N1<14>

PCIE_PRX_DTX_P1<14> PCIE_PRX_DTX_N1<14>

CLK_PCIE_CARD<1 4> CLK_PCIE_CARD#<14>

USB20_P10<17> USB20_N10< 17>

BKOFF#<32>

60mils

1 2 1 2 1 2 1 2 1 2 1 2

BATT_BLUE_LED#<32>

BATT_AMB_LED#<32>

PWR_LED#<32>

PWR_SUSP_LED #<32>

2

C9120 .1U_0201_10V6K eDP@ C9120 .1U_0201_10V6K eDP@ C9130 .1U_0201_10V6K eDP@ C9130 .1U_0201_10V6K eDP@ C9100 .1U_0201_10V6K eDP@ C9100 .1U_0201_10V6K eDP@ C9110 .1U_0201_10V6K eDP@ C9110 .1U_0201_10V6K eDP@ C9140 .1U_0201_10V6K eDP@ C9140 .1U_0201_10V6K eDP@ C9150 .1U_0201_10V6K eDP@ C9150 .1U_0201_10V6K eDP@

ON/OFFBTN# LID_SW#

40mils

20mils

+3VS

PLT_RST# CARD_CLKREQ#

PCIE_PTX_C_DRX_P1 PCIE_PTX_C_DRX_N1

PCIE_DTX_C_PRX_P1

PCIE_DTX_C_PRX_N1

CLK_PCIE_CARD CLK_PCIE_CARD#

USB20_P10 USB20_N10

+3VS

BKOFF# DPST_PWM EDP_HPD

+LCDVDD

EDP_TXP1_C EDP_TXN1_C EDP_TXP0_C EDP_TXN0_C EDP_AUXP_C EDP_AUXN_C

+3VALW

BATT_BLUE_LED# BATT_AMB_LED# PWR_LED# PWR_SUSP_LED #

Title

Size Document Num ber Rev

Custom

Q3ZMC M/B LA-8481P Schematic

Date: Sheet of

1

C11

C11 680P_0402_ 50V7K

680P_0402_ 50V7K

2

+INVPWR_B+

Compal Electronics, Inc.

LVDS Connector

W=40mils

JLVDS1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

ACES_50398-04 071-001

CONN@

To LED/B Conn.

ACES_88058-06 0N

8

GND

7

GND

6

5

4

3

2

1

JLED1

CONN@

1

22 51Thursday, April 12 , 2012

41

G1

42

G2

43

G3

44

G4

45

G5

1.0

2

1

2

C562

13

D

S

+3VS

W=60mils

31

AP2301GN-HF_SOT23 -3

Q28

+LCDVDD

1

2

EDP_HPD

G

12

eDP@

R480

100K_0402_ 5%

4

1

C479

4.7U_0603_6 .3V6K

2

W=60mils

1

C10

0.1U_0402_1 6V4Z

2

D15

@ D15

@

6

I/O4

+3VS

USB20_N10

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

5

VDD

4

I/O3

AZC099-04S.R7G _SOT23-6

2012/4/6 2013/4/6

3

USB20_P10

I/O2

2

GND

1

I/O1

Compal Secret Data

EDP_TXP1<4>

EDP_TXN1<4>

EDP_TXP0<4>

EDP_TXN0<4> EDP_AUXP<4> EDP_AUXN<4>

Deciphered Date

+LCDVDD +3VALW

12

R5

300_0603_5 %

D D

DMN66D0LDW -7_SOT363-6

PCH_ENVDD<16>

C C

B B

A A

5

Q1A

34

D

S

DPST_PWM<16>

G

5

G

2

12

R4

100K_0402_ 5%

61

D

S

R6

10K_0402_5 %

R2

1 2

1K_0402_5%

.047U_0402_ 16V7K

Q1B

Q1B DMN66D0LDW -7_SOT363-6

DMN66D0LDW -7_SOT363-6

DPST_PWM

R86 10K_0402_5%R86 10K_0402_5%

BKOFF#

R18 10K_0402_5%R18 10K_0402_5%

EDP_HPD#<4>

SSM3K7002FU_ SC70-3

12

C2

4.7U_0603_6 .3V6K

1 2

C5 100P_0201_25V8JC5 100 P_0201_25V8J

1 2

C8 100P_0201_25V8JC8 100 P_0201_25V8J

1 2

eDP@

Q29

5

W=40mils

+HDMI_5V_OUT

F1

+5VS

D D

21

1.1A_6VDC_FUSE

1

C345

0.1U_0402_1 6V4Z

2

4

3

2

1

PCH_DPB_N0<16> PCH_DPB_P0<16>

PCH_DPB_N1<16> PCH_DPB_P1<16>

PCH_DPB_N2<16> PCH_DPB_P2<16>

PCH_DPB_N3<16> PCH_DPB_P3<16>

C C

+3VS

1 2

R250 2.2K_0402_5 %R250 2.2K_0402_5 %

1 2

R253 2.2K_0402_5 %R253 2.2K_0402_5 %

C280 .1U_0402_16 V7KC280 .1U_0402_16 V7K C281 .1U_0402_16 V7KC281 .1U_0402_16 V7K

C283 .1U_0402_16 V7KC283 .1U_0402_16 V7K C282 .1U_0402_16 V7KC282 .1U_0402_16 V7K

C287 .1U_0402_16 V7KC287 .1U_0402_16 V7K C286 .1U_0402_16 V7KC286 .1U_0402_16 V7K

C285 .1U_0402_16 V7KC285 .1U_0402_16 V7K C284 .1U_0402_16 V7KC284 .1U_0402_16 V7K

12 12

SDVO_SCLK

SDVO_SDATA

Pull high at connector side

SDVO_SCLK<16>

SDVO_SDATA<16>

B B

SDVO_SCLK

SDVO_SDATA

HDMI_TX2HDMI_TX2+

HDMI_TX1HDMI_TX1+

HDMI_TX0HDMI_TX0+

HDMI_CLKHDMI_CLK+

+3VS

@

R785

R785 0_0402_5%

0_0402_5%

1 2

5

34

SGD

2

Q16A

G

DMN66D0LDW -7_SOT363-6

61

S

D

S

D

Q16B

Q16B DMN66D0LDW -7_SOT363-6

DMN66D0LDW -7_SOT363-6

Place closed to JHDMI1

+HDMI_5V_OUT

R257

1 2

2.2K_0402_5%

HDMI_TX2HDMI_TX2+

HDMI_TX1HDMI_TX1+

R255

1 2

2.2K_0402_5%

HDMI_SCLK

HDMI_SDATA

HDMI_TX0HDMI_TX0+

HDMI_CLKHDMI_CLK+

1 2

R592 680_0402_5%R592 680_0402_5%

1 2

R594 680_0402_5%R594 680_0402_5%

1 2

R583 680_0402_5%R583 680_0402_5%

1 2

R587 680_0402_5%R587 680_0402_5%

1 2

R564 680_0402_5%R564 680_0402_5%

1 2

R570 680_0402_5%R570 680_0402_5%

1 2

R573 680_0402_5%R573 680_0402_5%

1 2

R590 680_0402_5%R590 680_0402_5%

+3VS

HDMI_GND

61

D

G

2

Q14B

S

DMN66D0LDW -7_SOT363-6

HDMI connector

+3VS

+HDMI_5V_OUT

12

R198

1M_0402_5 %

PCH_DPB_HPD< 16>

A A

5

Q14A

Q14A DMN66D0LDW -7_SOT363-6

DMN66D0LDW -7_SOT363-6

34

SGD

R219

100K_0402_ 5%

HDMI_HPDHDMI_HPD

1

12

C324

C324 100P_0201_ 25V8J

100P_0201_ 25V8J

2

HDMI_HPD

HDMI_SDATA HDMI_SCLK

HDMI_CLK-

HDMI_CLK+ HDMI_TX0-

HDMI_TX0+ HDMI_TX1-

HDMI_TX1+ HDMI_TX2-

HDMI_TX2+

CONCR_099AMAC1 9CBACNF

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

CONN@

JHDMI1

GND GND GND GND

20 21 22 23

Security Classification

2012/4/6 2013/4/6

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

2012/4/6 2013/4/6

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HDMI Connector

Q3ZMC M/B LA-8481P Schematic

23 51Thursday, April 12 , 2012

1

1.0

+3VS_LC +3VS_LC

12

1

U65

TB@

U65

TB@

@

2

C1331

0.1U_0402_16V4Z

R1023

3.3K_0402_5%

TB@

EE_CLK EE_DI

@

R1018

R1018 0_0402_5%

0_0402_5%

INTEL Recommend 32K EEPROM

1 2

1

ATMEL: AT25512(64KB):SA000055T00 AT25256B(32KB):SA00005G500

C1330

CAT:CAT25256VI-GT3(32KB):SA00005DB00

2

0.01U_0402_16V7K

TB@

8

VCC

7

HOLD#

6

SCK

5

SI

AT25512N-SH-T_SO8

SA00005G500

PCIE_PRX_DTX_P5<14> PCIE_PRX_DTX_N5<14>

PCIE_PRX_DTX_P6<14> PCIE_PRX_DTX_N6<14>

PCIE_PRX_DTX_P7<14> PCIE_PRX_DTX_N7<14>

PCIE_PRX_DTX_P8<14> PCIE_PRX_DTX_N8<14>

CRYSTAL_P

TB@

12

R1024

3.3K_0402_5%

TB@

1

EE_CS_N

CS#

2

EE_DO

SO

3

WP#

4

GND

PCH_DPD_P3<16> PCH_DPD_N3<16>

PCH_DPD_P2<16> PCH_DPD_N2<16>

PCH_DPD_P1<16> PCH_DPD_N1<16>

PCH_DPD_P0<16> PCH_DPD_N0<16>

PCH_DPD_AUXP<16> PCH_DPD_AUXN<16>

PCH_DPD_P3 PCH_DPD_N3

PCH_DPD_P2 PCH_DPD_N2

PCH_DPD_P1 PCH_DPD_N1

PCH_DPD_P0 PCH_DPD_N0

PCH_DPD_AUXP PCH_DPD_AUXN

12

R1025

R1026

3.3K_0402_5%

TB@

PCIE_PRX_DTX_P5 PCIE_PRX_DTX_N5

PCIE_PRX_DTX_P6 PCIE_PRX_DTX_N6

PCIE_PRX_DTX_P7 PCIE_PRX_DTX_N7

PCIE_PRX_DTX_P8 PCIE_PRX_DTX_N8

TB@

C1338

+3VS_LC

R1101 1 M_0402_5%

25MHZ_10PF_7V25000014

3

6.8P_0402_50V8C

3

1

2

C1332 0.1U_0201_10V6KTB@C1332 0.1U_0201_10V6KTB@ C1333 0.1U_0201_10V6KTB@C1333 0.1U_0201_10V6KTB@

C1334 0.1U_0201_10V6KTB@C1334 0.1U_0201_10V6KTB@ C1335 0.1U_0201_10V6KTB@C1335 0.1U_0201_10V6KTB@

C1336 0.1U_0201_10V6KTB@C1336 0.1U_0201_10V6KTB@ C1337 0.1U_0201_10V6KTB@C1337 0.1U_0201_10V6KTB@

C1339 0.1U_0201_10V6KTB@C1339 0.1U_0201_10V6KTB@ C1341 0.1U_0201_10V6KTB@C1341 0.1U_0201_10V6KTB@

C1342 0.1U_0201_10V6KTB@C1342 0.1U_0201_10V6KTB@ C1343 0.1U_0201_10V6KTB@C1343 0.1U_0201_10V6KTB@

C1345 0.1U_0201_10V6KTB@C1345 0.1U_0201_10V6KTB@ C1346 0.1U_0201_10V6KTB@C1346 0.1U_0201_10V6KTB@

C1347 0.1U_0201_10V6KTB@C1347 0.1U_0201_10V6KTB@ C1348 0.1U_0201_10V6KTB@C1348 0.1U_0201_10V6KTB@

C1349 0.1U_0201_10V6KTB@C1349 0.1U_0201_10V6KTB@ C1350 0.1U_0201_10V6KTB@C1350 0.1U_0201_10V6KTB@

C1351 0.1U_0201_10V6KTB@C1351 0.1U_0201_10V6KTB@ C1352 0.1U_0201_10V6KTB@C1352 0.1U_0201_10V6KTB@

PLT_RST#<17,22,30,32,5>

1 2

GND

4

Y2

TB@

EE_CLK

1 2 1 2 1 2 1 2

12 12

TO PCH

12 12

GND

CRYSTAL_N

1

6.8P_0402_50V8C

1

TB@

2

C1340

2

12

TB@

R1038 0_0402_5%

1 2

R1032 1K_0402_1%TB @R1032 1K_0402_1%TB@

R101910K_0402_5% TB@ R101910K_0 402_5% TB@ R102010K_0402_5% TB@ R102010K_0 402_5% TB@ R102110K_0402_5% TB@ R102110K_0 402_5% TB@ R102210K_0402_5% TB@ R102210K_0 402_5% TB@

PCH_DPD_AUXN_C

DPD_HPD<16>

T75PAD @T75PAD @

PCIE_PRX_C_DTX_P5 PCIE_PRX_C_DTX_N5

PCIE_PRX_C_DTX_P6 PCIE_PRX_C_DTX_N6

PCIE_PRX_C_DTX_P7 PCIE_PRX_C_DTX_N7

PCIE_PRX_C_DTX_P8 PCIE_PRX_C_DTX_N8

1 2

R1052 0 _0402_5%

TB@

EE_DI EE_DO EE_CS_N EE_CLK_R

CRYSTAL_P CRYSTAL_N

CR_JTCK CR_JTMS CR_JTDI CR_TDO

PCH_DPD_P3_C PCH_DPD_N3_C

PCH_DPD_P2_C PCH_DPD_N2_C

PCH_DPD_P1_C PCH_DPD_N1_C

PCH_DPD_P0_C PCH_DPD_N0_C

PCH_DPD_AUXP_C

DPD_HPD

12

TB@

R1049

R1049 100K_0402_5%

100K_0402_5%

DPSNK1_HPD

PERST#

AD23 AC24

W18 W16

AD3

AB5

U20

W20

AA24 AB23

AA6 AB3

D13

D15

D17

D19

D11

AD5 AD7

AD9

AD11

AD13 AD15

AD17 AD19

R4

P5

W4

N4

V1

R2

Y7

U4

E14

E16

E18

E20

A6 B5

U6

E6

D5

E8

D7

E10

D9

E12

A4 B3

T5

R6

intra pair skew : 5 mil. inter pair skew : 10 mil

U66A

MONDC0 MONDC1

MONOBS_P MONOBS_N

EE_DI EE_DO EE_CS_N EE_CLK

TEST_EN TEST_PWR_GOOD

RSENSE RBIAS

XTAL_25_IN XTAL_25_OUT

TCK TMS TDI TDO

THERMDA NC

DPSNK0_3_P DPSNK0_3_N

DPSNK0_2_P DPSNK0_2_N

DPSNK0_1_P DPSNK0_1_N

DPSNK0_0_P DPSNK0_0_N

DPSNK0_AUX_P DPSNK0_AUX_N

DPSNK0_HPD

DPSNK1_3_P DPSNK1_3_N

DPSNK1_2_P DPSNK1_2_N

DPSNK1_1_P DPSNK1_1_N

DPSNK1_0_P DPSNK1_0_N

DPSNK1_AUX_P DPSNK1_AUX_N

DPSNK1_HPD

PETP_0 PETN_0

PETP_1 PETN_1

PETP_2 PETN_2

PETP_3 PETN_3

PERST_N

MISC

GPIO__8_EN_CIO_PWR_N_OD

GPIO_10__PA_CIO_SEL__BYP1

GPIO_11__PB_CIO_SEL__BYP1 GPIO_12__PA_DP_PWRDN__BYP2 GPIO_13__PB_DP_PWRDN__BYP2

SINK PORT 0

SINK PORT 1

PCIe

TRANSMIT

CACTUS-RIDGE_FCBGA288

TB@ SA00005QT20

PCIe_RST_0_N PCIe_RST_1_N PCIe_RST_2_N PCIe_RST_3_N

PCIE_CLKREQ_OD_N

TMU_CLK_OUT

TMU_CLK_IN

GPIO_0__PA_HV_EN__BYP0 GPIO_1__PB_HV_EN__BYP0

GPIO_2__GO2SX

GPIO_3

GPIO_4_WAKE_OD_N GPIO_5_CIO_PLUG_EVENT GPIO_6_OD__CIO_SDA_OD GPIO_7_OD__CIO_SCL_OD

GPIO_9__OK2GO2SX_N_OD

GPIO_14 GPIO_15

PWR_ON_POC_RSTN

EN_LC_PWR

DPSRC_3_P

DPSRC_3_N

DPSRC_2_P

DPSRC_2_N

DPSRC_1_P

DPSRC_1_N

DPSRC_0_P

DPSRC_0_N

DPSRC_AUX_P

SOURCE PORT 0

DPSRC_AUX_N

DPSRC_HPD_OD

Display Port

PERP_0 PERN_0

PERP_1 PERN_1

PERP_2 PERN_2

RECEIVE

PERP_3 PERN_3

REFCLK_100_IN_P REFCLK_100_IN_N

N6

PCIE_RST_0_N

T1

PCIE_RST_1_N

Y5

PCIE_RST_2_N

U2

PCIE_RST_3_N

W6

TB_CLKREQ#_R

AA4 Y3

TMU_CLK_IN

G2

PA_HV_EN

M1

TB_GPIO1

Y1

TB_GO2SX

W2

TB_FORCE_PWR_R

J4

TB_WAKE#

AA2

CIO_PLUG_EVENT

AB1

TB_SMB_DA

AC2

TB_SMB_CK

P3

EN_CIO_PWR#

M5

TB_OK2GO2SX#

M3

PA_CIO_SEL

L2

TB_GPIO11

H3

PA_DP_PWRDN

L4

TB_GPIO13

T3

TB_GPIO14

V5

TB_GPIO15

J2

TB_PWRON_POC_RST#

K5

EN_LC_PWR

A14 B15

A12 B13

A10 B11

A8 B9

C2 D3

V3

R1050

R1050 10K_0402_5%

10K_0402_5%

1 2

AB9

PCIE_PTX_C_DRX_P5

AA10

PCIE_PTX_C_DRX_N5

AA12

PCIE_PTX_C_DRX_P6

AB13

PCIE_PTX_C_DRX_N6

AB15

PCIE_PTX_C_DRX_P7

AA16

PCIE_PTX_C_DRX_N7

AA18

PCIE_PTX_C_DRX_P8

AB19

PCIE_PTX_C_DRX_N8

AB21

CLK_TB_REFCLK

AD21

CLK_TB_REFCLK#

TB@

TB_GO2SX

T76PAD@ T76PAD@ T77PAD@ T77PAD@ T78PAD@ T78PAD@ T79PAD@ T79PAD@

PA_HV_EN <45>

TB_GO2SX <32>

R1097 0_0402_5%TB@R1097 0_0402_5%TB@

R1039 0_0402_5%TB@R1039 0_0402_5%TB@

12

EN_CIO_PWR# <27> TB_OK2GO2SX# <32> PA_CIO_SEL <25>

PA_DP_PWRDN <25>

TB_PWRON_POC_RST# <32>

EN_LC_PWR <42 >

TB@

R1051

10K_0402_5%

EN_CIO_PWR#

PCIE_PTX_C_DRX_P5 <14> PCIE_PTX_C_DRX_N5 <14>

PCIE_PTX_C_DRX_P6 <14> PCIE_PTX_C_DRX_N6 <14>

PCIE_PTX_C_DRX_P7 <14> PCIE_PTX_C_DRX_N7 <14>

PCIE_PTX_C_DRX_P8 <14> PCIE_PTX_C_DRX_N8 <14>

CLK_TB_REFCLK <14> CLK_TB_REFCLK# <14>

R1066 10K_0402_5%@R1066 10K_0402_5%@

R1048 10K_0402_5%TB@R1048 10K_0402_5%TB@

PCH_PCIE_WAKE# <15,28>

EC control~~ tr ig after SUSP# asserted for 3 0ms

TB_SMB_CK

TB_SMB_DA

TB_SMB_CK

TB_SMB_DA

+3VS_POC +3VS_POC

12

34

TB@

D

G

5

Q89A

S

DMN66D0LDW-7_SOT363-6

+3VS_POC

12

TB_FORCE_PWR < 18>

R1129 0_0402_5%TB@R1129 0_0402_5%TB@

R1128 0_0402_5%TB@R1128 0_0402_5%TB@

R1131 0_0402_5%@R1131 0_0402_5%@

R1130 0_0402_5%@R1130 0_0402_5%@

TB@

C1344

0.1U_0402_16V4Z

CIO_PLUG_EVENT

TB_SMB_DA TB_SMB_CK

TMU_CLK_IN

TB_CLKREQ#_R

EN_CIO_PWR# TB_OK2GO2SX# PA_DP_PWRDN TB_GPIO13

PA_HV_EN TB_GPIO1

TB_FORCE_PWR_R

TB_GPIO11 TB_GPIO14 TB_GPIO15 EN_LC_PWR

12

TB@

5

U67

2

P

B

4

Y

1

A

G

MC74VHC1G08DFT2G_SC70-5

3

+3VS_LC

2

TB@

G

61

S

D

S

D

Q89B

Q89B DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

R1053

@

0_0402_5%

R1036 2.2K_0402_5%@R1036 2.2K_0402_5%@ R1037 2.2K_0402_5%@R1037 2.2K_0402_5%@

R1046 2.2K_0402_5%TB@R1046 2.2K_0402_5%TB@ R1047 2.2K_0402_5%TB@R1047 2.2K_0402_5%TB@

R1033 10K_0402_5%TB@R1033 10K_0402_5%TB@

R1031 10K_0402_5%TB@R1031 10K_0402_5%TB@

R1034 10K_0402_5%TB@R1034 10K_0402_5%TB@ R1029 10K_0402_5%TB@R1029 10K_0402_5%TB@ R1035 10K_0402_5%TB@R1035 10K_0402_5%TB@ R1028 10K_0402_5%TB@R1028 10K_0402_5%TB@

R1040 1K_0402_5%TB@R1040 1K_0402_5%TB@ R1027 10K_0402_5%TB@R1027 10K_0402_5%TB@

R1041 10K_0402_5%TB@R1041 10K_0402_5 %TB@

R1042 10K_0402_5%TB@R1042 10K_0402_5%TB@ R1043 10K_0402_5%TB@R1043 10K_0402_5%TB@ R1044 10K_0402_5%TB@R1044 10K_0402_5%TB@ R1045 100K_0402_5%TB@R1045 100K_0402_5%TB@

TB_SMB_CK_GPIO7 <18>

TB_SMB_DA_GPIO6 <14>

EC_SMB_CK2 <11,14,32>

EC_SMB_DA2 <11,14,32>

TB_PLUG_EVENT

TB_CLKREQ#TB_CLKREQ#_R

12

1 2 1 2

1 2

+3VS_LC

12

+3VS_POC

12 12 12 12

12 12

12

12 12 12

TB_PLUG_EVENT <18>

TB_CLKREQ# <14>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

Intel Thunderbolt(1/4)

Q3ZMC M/B LA-8481P Schematic

of

24 51Thursday, April 12, 2012

1.0

Function

Port A is active

Port B is active

+3VS_POC

1

2

C1368

C1367

TB@

PA_CFG1_LSEO0

0.1U_0201_10V6K

+3VS_POC

1

2

C1373

C1371

TB@

0.1U_0201_10V6K

+3VS_POC

1 2

R1059 100K_0402_5%

1 2

R1061 10K_0402_5%

1 2

R1067 1M_0402_5%

1 2

R1068 100K_0402_5%

1 2

R1069 10K_0402_5%

1 2

R1070 470K_0402_5%

1 2

R1071 470K_0402_5%

1 2

R1072 470K_0402_5%

1 2

R1073 470K_0402_5%

PA_CIO_SEL

TB@

TB_CIO_RX_P1_C

TB_CIO_RX_N1_C

650NH +-5% LQW18CNR65J00D

DPA_AUX_N DPA_AUX_P

R1127

10K_0402_5%

TB@

0.1U_0201_10V6K

R1076

+3VS_POC

1 2

1

2

C1369

TB@

1

2

C1372

TB@

12

R1077

1.5K_0402_5%

TB@

R1126

R1126 10K_0402_5%

10K_0402_5%

TB@

1 2

61

TB@

D

G

2

S

Q88B

Q88B DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

34

TB@

D

G

5

S

Q88A

Q88A DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

SEL/HPD_SEL /AUX_SEL

L

H

1

2

C1370

TB@

0.1U_0201_10V6K

PA_DP_PWRDN<24>

PA_CIO_SEL<24>

1

2

0.1U_0201_10V6K

DPA_AUX_N

PA_LSTX_LSEO1_R

PA_LSRX_LSOE1_U

DPA_AUX_P

DPA_AUX_HPD

TB_CIO_TX_P0

TB_CIO_TX_N0

TB_CIO_TX_P1

TB_CIO_TX_N1

12

TB@

1.5K_0402_5%

1.5K_0402_5% D47 BAR90-02LRH_TSLP-2-7-2

D47 BAR90-02LRH_TSLP-2-7-2

BAR90-02LRH_TSLP-2-7-2TB@

D46

TB@

L63

TB@

C1379

30P_0402_50V8J

PA_CFG1_LSEO0_A PA_CFG2_LSOE0

PA_CFG1_LSEO0

2

G

S

D

S

D

Q81B

DMN66D0LDW-7_SOT363-6

D

42

Q91B

TB@

Q91B

TB@

G

NTGD4161PT1G_TSOP6~D

3

PA_DPSRC_3P_C PA_DPSRC_3N_C

PA_DPSRC_1P_C PA_DPSRC_1N_C

PA_AUX_P_C PA_AUX_N_C

TB_CIO_TX_P0

TB_CIO_TX_P1

PA_LSTX_LSEO1_R PA_LSRX_LSOE1_R

C1353 0.22U_0402_10V6KTB@C1353 0.22U_0402_10V6KTB@ C1358 0.22U_0402_10V6KTB@C1358 0.22U_0402_10V6KTB@

C1359 0.22U_0402_10V6KTB@C1359 0.22U_0402_10V6KTB@ C1360 0.22U_0402_10V6KTB@C1360 0.22U_0402_10V6KTB@

C1361 0.22U_0402_10V6KTB@C1361 0.22U_0402_10V6KTB@ C1354 0.22U_0402_10V6KTB@C1354 0.22U_0402_10V6KTB@

C1355 0.22U_0402_10V6KTB@C1355 0.22U_0402_10V6KTB@ C1362 0.22U_0402_10V6KTB@C1362 0.22U_0402_10V6KTB@

C1363 0.22U_0402_10V6KTB@C1363 0.22U_0402_10V6KTB@ C1356 0.22U_0402_10V6KTB@C1356 0.22U_0402_10V6KTB@

C1357 0.22U_0402_10V6KTB@C1357 0.22U_0402_10V6KTB@ C1364 0.22U_0402_10V6KTB@C1364 0.22U_0402_10V6KTB@

C1365 0.22U_0402_10V6KTB@C1365 0.22U_0402_10V6KTB@ C1366 0.22U_0402_10V6KTB@C1366 0.22U_0402_10V6KTB@

HPD CFG1 CFG2 LSrx Mode

PCH_DPD_DAT <16> PCH_DPD_CLK <16>

DMN66D0LDW-7_SOT363-6

NTGD4161PT1G_TSOP6~D

1 2 1 2

PA_DPSRC_3P PA_DPSRC_3N

PA_DPSRC_1P PA_DPSRC_1N

PA_AUX_P PA_AUX_N

PA_DPSRC_HPD

1 2 1 2

1 2

R1058 0_0402_5%TB@R1058 0_0402_5%TB@

1 2

R1060 0_0402_5%TB@R1060 0_0402_5%TB@

TB_CIO_TX_P0_C

TB_CIO_TX_N0_CTB_CIO_TX_N0

TB_CIO_RX_P0TB_CIO_RX_P0_C TB_CIO_RX_N0TB_CIO_RX_N0_C

PA_CFG1_LSEO0 PA_CFG2_LSOE0

TB_CIO_TX_P1_C TB_CIO_TX_N1_CTB_CIO_TX_N1

TB_CIO_RX_P1TB_CIO_RX_P1_C TB_CIO_RX_N1TB_CIO_RX_N1_C

PA_LSTX_LSEO1 PA_LSRX_LSOE1

Comments

TB@

SGD

Q81A

6 5

D

Q91A

5

TB@

34

6 1

S

G

1

+3VS_POC

PA_SRC_3P

1

PA_SRC_3N PA_LSTX_SRC_1P PA_LSRX_SRC_1N

2

DPA_AUX_P DPA_AUX_N DPA_AUX_HPD

PA_DP_PWRDN

PA_CIO_SEL

U68

3

VDD

9 12 16 20 29

1

2

4

5

6

7

8

10 11 32

D0+A

VDD

D0-A

VDD

D1+A

VDD

D1-A VDD VDD

AUX+A

AUX-A

HPD_A

D0+

D0+B

D0-

D0-B

D1+

D1+B

D1-

D1-B AUX+ AUX-

AUX+B

HPD

AUX-B

HPD_B

SEL

GND

HPD_SEL AUX_SEL

GND

GPAD

PI3VEDP212ZLEX_TQFN32_6X3~D

TB@

31 30 27 26

19 18 17

25 24 23 22

15 14 13

21 28 33

PA_DPSRC_3P_C PA_DPSRC_3N_C PA_DPSRC_1P_C PA_DPSRC_1N_C

PA_AUX_P_C PA_AUX_N_C

D0+B D0-B PA_LSTX_LSEO1_R PA_LSRX_LSOE1_U

R1054

1 2

1K_0402_5%

TB@

PA_AUX_N_C PCH_DPD_DAT PA_AUX_P_C

DMN66D0LDW-7_SOT363-6

NTGD4161PT1G_TSOP6~D

R1055

R1057

R1056

49.9_0402_1%

1 2

1K_0402_5%

1 2

@

+3VS_POC

12

G

5

61

D

G

S

TB@

Q86B

Q86B DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

12

TB@

R1116

R1116 10K_0402_5%

10K_0402_5%

PA_DPSRC_HPD

34

D

S

TB@

Q86A

Q86A DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

10K_0402_5%

MDP_HPD

TB@

R1115

2

1 0 0 X DP

U3

TB@U3

12 12

12

1

2

AUX_CHP

AUX_CHN

12

TB@

L64

L64 650NH +-5% LQW18CNR65J00D

650NH +-5% LQW18CNR65J00D

1

TB@

C1380

C1380 30P_0402_50V8J

30P_0402_50V8J

2

TB_CIO_RX_P0_C TB_CIO_RX_N0_C

TB@

R1091

R1090

1 2

1M_0402_5%

TB@

1 2

TB@

R1075 100K_0402_5%

PA_LSRX_LSOE1_U

TB@

1

OE#

2

IN

3

GND

74AHC1G125GW_SOT353-5

+3VS_POC

5

VCC

C1374 0.1U_0201_10V6K

4

OUT

PA_LSRX_LSOE1_R

TB@

12

D0+B

13

D

LEGO@

2

Q30

TB_LED<32>

G

Q30

SSM3K7002FU_SC70-3

S

+3VS_POC

12

LEGO@

Pull High +3VS at PCH side

TB_EJECT_BTN<32>

SSM3K7002FU_SC70-3

+3VS_POC

TB@

R711

10K_0402_5%

Q84

TB@Q84

TB@

BC846B_SOT23-3

1

TB@

2

3

1

2

3

Q85

Q85 BC846B_SOT23-3

BC846B_SOT23-3

R1114

TB@

1 2

2.05K_0402_1%

+HV_12V

R1113

R1113 10K_0402_5%

R1085

R1087

1 2

1K_0402_5%

TB@

1

C1387

C1386

2

330P_0402_50V7K

TB@

10K_0402_5%

1 2

TB@

PA_CFG1_LSEO0, PA_CFG2_LSOE0 should be used by GPU as the DP CONFIG1/CONFIG2 inputs, if required

12

LEGO@

Q31

12

TB@

R712

R712 10K_0402_5%

10K_0402_5%

HV_EN

13

D

S

10K_0402_5%

2

D0-B

G

+3VS_POC

LEGO@

R1125

R1074 10K_0402_5%TB@R1074 10K_0402_5%TB@

R1084 0_0402_5%TB@R1084 0_0402_5%TB@

R1112 36.5K_0402_1%TB@R1112 36.5K_0402_1%TB@ R1110 35.7K_0402_1%TB@R1110 35.7K_0402_1%TB@ R1111 35.7K_0402_1%TB@R1111 35.7K_0402_1%TB@

Current limited: Ilim = 40Kohm/Rset

EN HV_EN OUT

0 0

001

1

1 1

TB@

1 2

1 2 1 2 1 2

60mil

C1000

150U_B2_6.3VM_R35M

HV_EN

1 1 X X HDMI

0 0 1 0 TBT

0 0 1 1 TBT

0 X 0 X None

TB_CIO_RX_P0_C

TB_CIO_RX_N0_C

TB_CIO_TX_P0

TB_CIO_TX_N0

1

+

C1001

2

TB@

0.1U_0402_16V4Z

U2

5

EN

11

HV_EN

17

S0

8

ISET_V3P3

9

ISET_S3

10

ISET_S0

1

D42

@

1

2

4

5

3

8

L05ESDL5V0NA-4 SLP2510P8

TB@

20

7

VHV6VHV

V3P319V3P3

OUT OUT

V3P3OUT

RSVD RSVD

GND3GND2GND4GND

GND13TPad

21

TB@

TPS22980RGPR_VQFN20_4X4

TBT cable but no TBT link

TBT mode

Cable is disconnected

9

TB_CIO_RX_P0_C

10

8

TB_CIO_RX_N0_C

9

7

TB_CIO_TX_P0

7

6

TB_CIO_TX_N0

65

40mil

+HV_12V+3VS_POC

1

C1003

2

0.1U_0402_16V4Z

12 14

18

+VCC3V3_PA

15

@

16

T73

T73 PAD

PAD

TB@

40mil

+VCC_DP_L

1

C1004

2

0.1U_0402_16V4Z

TB@

C1005

0.1U_0402_16V4Z

0V

Security Classification

3.3V

12V

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/4/6 2013/4/6

Compal Secret Data

Q82A

6 5

D

TB@

Q92A

A18 B19

A16 B17

H1

G24 E24

G22 E22

G4

L24 J24

L22 J22

N2

PA_LSTX_SRC_1P

PA_LSRX_SRC_1N

PA_SRC_3P

PA_SRC_3N

FBMA-L11-201209-221LMA30T_0805

1

C1417

2

TB@

0.01U_0402_16V7K

Deciphered Date

5

TB@

34

SGD

1

U66B

PA_DPSRC_3_P PA_DPSRC_3_N

PA_DPSRC_1_P PA_DPSRC_1_N

F3

PA_AUX_P

F1

PA_AUX_N

6 1

S

G

PA_DPSRC_HPD

PA_CIO0_TX_P__DPSRC_0_P PA_CIO0_TX_N__DPSRC_0_N

PA_CIO0_RX_P PA_CIO0_RX_N

K1

PA_CONFIG1__CIO_0_LSEO PA_CONFIG2__CIO_0_LSOE

PA_CIO1_TX_P__DPSRC_2_P PA_CIO1_TX_N__DPSRC_2_N

PA_CIO1_RX_P PA_CIO1_RX_N

PA_LSTX__CIO_1_LSEO

J6

PA_LSRX__CIO_1_LSOE

CACTUS-RIDGE_FCBGA288

TB@ SA00005QT20

All Thunderbolt TX traces have pi filter when embedded c apacitors befor e and after inductor should be 0.45pF

Route Thunderbo lt traces as 85 Ohm control i mpedance. Match inside pa ir 2 mil.Match between lanes NA Thunderbolt len ght must be bet ween 0.8 inch to 2 inch

D43

@

1

2

4

5

3

8

L05ESDL5V0NA-4 SLP2510P8

+VCC_DP

TB@

L65

1 2

PA_CFG1_LSEO0

2

G

PCH_DPD_CLK

S

D

S

D

Q82B

Q82B DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

D

42

Q92B

TB@

Q92B

TB@

G

NTGD4161PT1G_TSOP6~D

3

9

PA_LSTX_SRC_1P

10

8

PA_LSRX_SRC_1N

9

7

PA_SRC_3P

7

6

PA_SRC_3N

65

R1079

1 2

100K_0402_5%

TB@

@

R1086

+3VS_POC

12

13

D

TB@

Q32

SSM3K7002FU_SC70-3

PB_DPSRC_3_P PB_DPSRC_3_N

PB_DPSRC_1_P PB_DPSRC_1_N

PB_AUX_P

DPSRC Port A

DPSRC Port B

PORT0PORT1

CIO

PB_CIO2_TX_P__DPSRC_0_P

PB_CIO2_TX_N__DPSRC_0_N

PB_CONFIG1__CIO_2_LSEO

PORT2PORT3

PB_CONFIG2__CIO_2_LSOE

PB_CIO3_TX_P__DPSRC_2_P

PB_CIO3_TX_N__DPSRC_2_N

PB_AUX_N

PB_DPSRC_HPD

PB_CIO2_RX_P PB_CIO2_RX_N

PB_CIO3_RX_P PB_CIO3_RX_N

PB_LSTX__CIO_3_LSEO PB_LSRX__CIO_3_LSOE

TB_CIO_TX_P1

TB_CIO_TX_N1

AUX_CHP

AUX_CHN

1 2

R1083 0_0402_5%TB@R1083 0_0402_5%TB@

1 2

TB@R1078

TB@

0_0402_5%

1 2

TB@R1089

TB@

1 2

TB@R1080

TB@

0_0402_5%

1 2 1 2

mDP_HPD_RMDP_HPD

C1377

1 2

R1078

1

R1089 R1080

C1378

2

0.01U_0402_50V7K

R1081 0_0402_5%TB@R1081 0_0402_5%TB@ R1082 0_0402_5%TB@R1082 0_0402_5%TB@

40mil

+VCC_DP

12

0_0402_5%

40mil

L66

TB@

BLM31PG500SN1L 1206

VCC_DP@3V , max current 500mA VCC_DP@12V, max current 0.8A

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Q3ZMC M/B LA-8481P Schematic

Q32

S

A22 B23

A20 B21

D1 E2

K3

R24 N24

R22 N22

P1 H5

W24 U24

W22 U22

PAD

L6

T80

@ T80

@

G6

R1062

1 2

10K_0402_5%

TB@

D44

@

1

2

4

5

3

8

L05ESDL5V0NA-4 SLP2510P8

C1376

0.01U_0402_50V7K

1 2

TB@

TB_CIO_TX_P0

TB_CIO_RX_P0_C

TB_CIO_TX_N0

TB_CIO_RX_N0_C

0.01U_0402_50V7K

TB@

PA_LSTX_SRC_1P

PA_SRC_3P

PA_LSRX_SRC_1N

PA_SRC_3N

TB_CIO_TX_P1 AUX_CHP TB_CIO_TX_N1 AUX_CHN RETURN

12

TB@

R1088

R1088 0_0402_5%

0_0402_5%

1

TB@

C1381

0.01U_0402_50V7K

2

Intel Thunderbolt(2/4)

TB@

R1124

R1124 1K_0402_5%

1K_0402_5%

2

PA_CFG1_LSEO0

G

R1064

R1063

1 2

10K_0402_5%

TB@

9

TB_CIO_TX_P1

10

8

TB_CIO_TX_N1

9

7

AUX_CHP

7

6

AUX_CHN

65

JTB1

1

GND

2 3

LANE0_P

4 5

LANE0_N

6 7

GND

8 9

LANE1_P

10 11

LANE1_N

12 13

GND

14 15

LANE2_P

16 17

LANE2_N

18 19

RETURN

20

21 22 23 24

GND

JAE_SP11-11986-T01

25 51Thursday, April 12, 2012

R1065

1 2

10K_0402_5%

TB@

HPD

CONFIG1

CONFIG2

GND

LANE3_P

LANE3_N

GND

AUX_CHP

AUX_CHN

DP_PWR

1.0

+1.05VS_LC

TB@

1

2

1

2

TB@

+3VS_LC

TB@

+1.05VS_CIO

1

TB@

2

C1412

C1433

2

C1413

0.01U_0201_10V7K

2

1

1000P_0201_16V7K

U66C

J8

VCC1P0_ON

J10

VCC1P0_ON

2

TB@

1

C1398

C1397

1000P_0201_16V7K

1

TB@

2

C1415

C1434

C1443

2

C1416

0.01U_0201_10V7K

1

TB@

2

C1435

0.1U_0201_10V6K

1

TB@

2

C1444

0.1U_0201_10V6K

J12

VCC1P0_ON

J14

VCC1P0_ON

J16

VCC1P0_ON

K17

VCC1P0_ON

T15

VCC1P0_ON

U14

VCC1P0_ON

V7

VCC1P0_ON

W8

VCC1P0_ON

G10

VCC1P0_PE

G12

VCC1P0_PE

G14

VCC1P0_PE

G16

VCC1P0_PE

G18

VCC1P0_PE

H19

VCC1P0_PE

K19

VCC1P0_PE

M19

VCC1P0_PE

P19

VCC1P0_PE

T19

VCC1P0_PE

V15

VCC1P0_PE

V19

VCC1P0_PE

W12

VCC1P0_PE

W14

VCC1P0_PE

G8

VCC1P0_DPAUX

H9

VCC1P0_DPAUX

CACTUS-RIDGE_FCBGA288

TB@ SA00005QT20

U66D

A2

VSSPE

A24

VSSPE

B1

VSSPE

B7

VSSPE

C4

VSSPE

C6

VSSPE

C8

VSSPE

C10

VSSPE

C12

VSSPE

C14

VSSPE

C16

VSSPE

C18

VSSPE

C20

VSSPE

C22

VSSPE

C24

VSSPE

D21

VSSPE

D23

VSSPE

E4

VSSPE

F5

VSSPE

F7

VSSPE

GND

F9

VSSPE

F11

VSSPE

F13

VSSPE

F15

VSSPE

F17

VSSPE

F19

VSSPE

F21

VSSPE

F23

VSSPE

G20

VSSPE

H21

VSSPE

H23

VSSPE

J18

VSSPE

J20

VSSPE

K21

VSSPE

K23

VSSPE

L20

VSSPE

M21

VSSPE

M23

VSSPE

N20

VSSPE

P21

VSSPE

P23

VSSPE

R20

VSSPE

T21

VSSPE

T23

VSSPE

U18

VSSPE

V13

VSSPE

V17

VSSPE

V21

VSSPE

V23

VSSPE

Y9

VSSPE

CACTUS-RIDGE_FCBGA288

TB@ SA00005QT20

VCC

VCC3P3_CIO VCC3P3_CIO VCC3P3_CIO

VCC3P3_DPAUX

VCC3P3_POC

VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE

VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0 VCC1P0

VCC3P3 VCC3P3 VCC3P3

VCC3P3_DP VCC3P3_DP VCC3P3_DP VCC3P3_DP

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

K9 K13 L8 L12 L16 M9 M13 M17 N8 N12 N16 P9 P13 P17 R8 R12 R16 T9 T13 T17 U8 U12 U16 V9 AD1 Y11 Y13 Y15 Y17 Y19 Y21 Y23 AA8 AA14 AA20 AA22 AB7 AB11 AB17 AC4 AC6 AC8 AC10 AC12 AC14 AC16 AC18 AC20 AC22

W10 V11 U10 T11 R14 R10 P15 P11 N14 N10 M15 M11 L14 L10 K15 K11

M7 P7 T7 L18 N18 R18 H11 H13 H15 H17 H7 K7

TB@

1

TB@

2

C1406

C1407

0.1U_0201_10V6K

1

TB@

2

C1424

C1425

.1U_0402_16V7K

+3VS_POC

1

2

C1445

0.1U_0201_10V6K

1

TB@

2

C1409

C1408

0.1U_0201_10V6K

1

TB@

2

.1U_0402_16V7K

0.1U_0201_10V6K

1

TB@

2

C1427

C1428

0.1U_0201_10V6K

0.01U_0201_10V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Intel Thunderbolt(3/4)

Q3ZMC M/B LA-8481P Schematic

26 51Thursday, April 12, 2012

1.0

+3VS_POC to +3VS_LC

+3VS_POC

+5VALW

1U_0402_6.3V6K

12

TB@

R1095

100K_0402_5%

EN_3VLC_PWR#

34

TB@

D

G

5

Q71A

1.05VS_LC_PG<42>

Q71A

S

DMN66D0LDW-7_SOT363-6

C1446

TB@

1

2

TB@

1 2

R1096

100K_0402_5%

AP2301GN-HF_SOT23-3

3 1

VCC3V3_LC max current 350mA

TB@

Q70

2

3VS_LC_GATE

TB@

1

C1448

C1448 .1U_0603_25V7K

.1U_0603_25V7K

2

+3VS_LC

1

TB@

C1447

C1447 1U_0402_6.3V6K

1U_0402_6.3V6K

2

+3VALW to +3VS_POC

60mil40mil 40m il

J2

112

JUMP_43X79

J4

112

JUMP_43X79

+3VS_POC

+3VALW

2

+3VS

2

VCC3V3POC, IC CONN max current 500mA , VCC3V3POC, DP CONN max current 500mA , VCC3V3POC to VCC3V3 max current 350mA ,

EN_3VLC_PWR#

+3VS_LC +1.05VS_LC +1.05VS_CIO

12

TB@

R1092

R1092 220_0402_5%

220_0402_5%

3VS_LC_CHG

61

D

G

2

TB@

S

Q71B

Q71B DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

Discharge circuit

12

TB@

R1093

R1093 220_0402_5%

220_0402_5%

1.05LC_CHG

13

D

EN_3VLC_PWR#

2

G

TB@

Q72

Q72 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

EN_CIO_PWR#

12

TB@

R1094

R1094 220_0402_5%

220_0402_5%

1.05VS_CIO_CHG

61

D

G

2

TB@

S

Q75B

Q75B DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

_VCC1V05_LC,max current 750mA _VCC1V05_CIO,max current 1.5A _VCC3V3POC,max current 5mA _VCC3V3_LC,max current 350mA _VCC_DP@3V,max current 500mA _VCC_DP@12V,max current 0.8A in the case of 12V min power should be 10W

+3VS_POC

T1?

TB_PWRON_POC_RST#

+1.05VS_LC

T2

+3VS_LC

VCC1V05_LC, max current 750mA

VCC1V05_CIO, max current 1.5A

EN_CIO_PWR#<24>

EN_CIO_PWR#

A1

+3VS_POC

VV

A2

TB_PWRON_POC_RS T#

U66

CACTUS RIDGE

V

U68

PA_DP_PWRDN PA_CIO_SEL 1=TB 0=DP

PCH_PCIE_WAKE#

V V

PCH

TB_PLUG_EVENT

TB@

R1099

100K_0402_5%

5

V V

S1

S3

Rds=2.6mΩ(Typ)

3.2mΩ(Max)

+VSB

1 2

34

TB@

D

G

Q75A

S

DMN66D0LDW-7_SOT363-6

1.05VS_LC_PG EN_LC_PWR

EN_CIO_PWR#

PA_HV_EN

TB_OK2GO2SX#

+1.05VS_LC to +1.05VS_CIO

A4

H1

TB_GO2SX

80mil 80mil

TB@

C1452

10U_0603_6.3V6M

12

@

R1109

R1109 1M_0402_5%

1M_0402_5%

S4A3

Q70, +3VS_LC

V

PU11, +1.05VS_L C

S2

U74, +1.05VS_CI O

V

PU16, PQ47

V

+12VS_TB

TB@

U74

U74 SI7716ADN-T1-GE3_POWERPAK8-5

SI7716ADN-T1-GE3_POWERPAK8-5

5

1

2

1.05CIO_GATE

4

1 2

1

2

EC

1 2 3

TB@

R1100

R1100 10K_0402_5%

10K_0402_5%

TB@

C1456

C1456 .1U_0603_25V7K

.1U_0603_25V7K

V

+1.05VS_CIO+1.05VS_LC

TB@

10U_0603_6.3V6M

0.1U_0402_16V4Z

TB@

C1454

C1453

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Intel Thunderbolt(4/4)

Q3ZMC M/B LA-8481P Schematic

27 51Thursday, April 12, 2012

1.0

5

4

3

2

1

For Wireless LAN

60mil

J10

1 2

JUMP_43 X79

@

D D

AOAC_ON< 32>

C C

@

+3VALW

.1U_0402 _16V7K

1 2

R451 100K_0 402_5%R451 10 0K_0402_5%

R185

1K_0402 _5%

1 2

BT_ON#

BT_CTRL

BT_ON#< 32>

+3VS_W LAN+3VS +3VS_ WLAN

1

C403

4.7U_080 5_10V4Z

2

G

12

C500

BT BT

Enable Disable

L H

H L

2

G

1

2

1 2

R472 1K_0402 _5%

13

D

Q61

Q61 SSM3K70 02FU_SC70-3

SSM3K70 02FU_SC70-3

S

BT_CTRL

13

D

Q62

Q62 SSM3K70 02FU_SC70-3

SSM3K70 02FU_SC70-3

S

C735

0.1U_020 1_10V6K

Mini Card Power Rating

+3VS_W LAN

1

C387

0.1U_020 1_10V6K

2

Q47

AP2301G N-HF_SOT23-3

3 1

3VSW LAN_GATE3VSWLAN_ GATE_R

2

12

C539

0.1U_020 1_10V6K

+3VS_W LAN+ 3VALW

40mil(1A)

CLK_PCIE_ MINI1#<14>

CLK_PCIE_ MINI1<14>

MINI1_CLKREQ #<14>

PCIE_PRX_ DTX_N2<14>

PCIE_PRX_ DTX_P2<14> PCIE_PTX_ C_DRX_P2<14> PCIE_PTX_ C_DRX_N2<14>

USB20_P 8<17> USB20_N 8<1 7>

PLT_RST _BUF#<17 >

PCH_PCIE_ WAKE#<15,24>

EC_PME#<32>

WL_ OFF#< 32>

BT_CTRL

BT_LED<32>

+3VS_W LAN

BT_LED

1 2

R962 10K _0402_5%R962 10K _0402_5%

+3VS_W LAN

1 2

R702 0_0 402_5%@R702 0 _0402_5%@

1 2

R490 0_0 402_5%R49 0 0_0402_5%

1 2

R491 0_0 402_5%R49 1 0_0402_5%

1 2

R492 0_0 402_5%@R492 0 _0402_5%@

PCH_PCIE_ WAKE#_R

BT_CTRL _R BT_LED_ R

U1

F12

3V3

G4

3.3VAUX

L4

REFCLK-

L5

REFCLK+

F1

CLKREQ_L

L6

PERN0

L7

PERP0

L8

PETN0

L9

PETP0

G9

USB_D+

G10

USB_D-

D1

PERST_L

E1

WAKE_L

G6

WIFI_DISABLE

G7

WIFI_LED

E12

BT_DISABLE

G8

BT_LED

F4

NC

G1

GND[1]

G3

GND[2]

G5

GND[3]

G12

GND[4]

H1

GND[5]

H2

GND[6]

H11

GND[7]

H12

GND[8]

L1

GND[9]

L2

GND[10]

L3

GND[11]

L10

GND[12]

L11

GND[13]

L12

GND[14]

F10

GND[15]

F9

GND[16]

F8

GND[17]

T77H281 .01_81P

Power

Clock

PCIE signal

USB signal

Control

GND

GND[18] GND[19] GND[20] GND[21] GND[22] GND[23] GND[24] GND[25] GND[26] GND[27] GND[28] GND[29] GND[30] GND[31] GND[32] GND[33] GND[34] GND[35] GND[36] GND[37] GND[38] GND[39] GND[40] GND[41] GND[42] GND[43] GND[44] GND[45] GND[46] GND[47] GND[48] GND[49] GND[50] GND[51] GND[52] GND[53] GND[54] GND[55] GND[56] GND[57] GND[58] GND[59] GND[60] GND[61] GND[62] GND[63]

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B11 B12 C1 C4 C5 C6 C7 C8 C9 C10 C12 D3 D4 D5 D6 D7 D8 D9 D10 D12 E3 E4 E5 E6 E7 E8 E9 E10 F3 F5 F6 F7

B B

A A

Security Class ification

2012/4/6 2013/4/6

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/4/6 2013/4/6

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Custom

Q3ZMC M/B LA-8481P Schematic

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

On Board WLAN

28 51Thu rsday, April 12, 2012

1

1.0

A

For mSATA

40mil

+3VS_FU LL +1.5VS+3VS +3 VS_FULL

J8

@J 8

@

2

112

JUMP_43 X39

1 1

2 2

1

C455

4.7U_060 3_6.3V6K

2

1

C475

0.1U_020 1_10V6K

2

1

C466

0.1U_020 1_10V6K

2

B

20mil

@

1

C442

0.1U_040 2_16V4Z

2

1

C441

0.1U_040 2_16V4Z

2

C

1 2

SATA_PT X_DRX_N1<13 > SATA_PT X_DRX_P1<13>

SATA_PR X_DTX_P1<13> SATA_PR X_DTX_N1<13 >

C625 0 .01U_0201_10V 7KC6 25 0.01U_020 1_10V7K

1 2

C627 0 .01U_0201_10V 7KC6 27 0.01U_020 1_10V7K

1 2

C628 0 .01U_0201_10V 7KC6 28 0.01U_020 1_10V7K

1 2

C626 0 .01U_0201_10V 7KC6 26 0.01U_020 1_10V7K

From DG=>Change to 0.01u

1 2

SATA_PR X_DTX_P0<13> SATA_PR X_DTX_N0<13 >

SATA_PT X_DRX_N0<13 > SATA_PT X_DRX_P0<13>

E51TXD_ P80DATA<32>

E51RXD_ P80CLK<3 2>

100K_04 02_5%

C621 0 .01U_0201_10V 7KC6 21 0.01U_020 1_10V7K

1 2

C622 0 .01U_0201_10V 7KC6 22 0.01U_020 1_10V7K

1 2

C623 0 .01U_0201_10V 7KC6 23 0.01U_020 1_10V7K

1 2

C624 0 .01U_0201_10V 7KC6 24 0.01U_020 1_10V7K

+3VS_FU LL

1 2

R299 0_0 402_5%R29 9 0_0402_5%

1 2

R287 0_0 402_5%R28 7 0_0402_5%

12

R300

12

R288

R288 1K_0402 _5%

1K_0402 _5%

D

SATA_PT X_C_DRX_N1 SATA_PT X_C_DRX_P1

SATA_PR X_C_DTX_P1 SATA_PR X_C_DTX_N1

SATA_PR X_C_DTX_P0 SATA_PR X_C_DTX_N0

SATA_PT X_C_DRX_N0 SATA_PT X_C_DRX_P0

E51TXD_ P80DATA_R E51RXD_ P80CLK_R

E

Function

Port0,1

Port0

+3VS_FU LL

JMINI1

1

1 3 5 7 9 11 13 15

17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

G153G254G355G4

2 4 6

8 10 12 14 16

18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

56

3 5 7

9 11 13 15

17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

+1.5VS

2 4 6 8 10 12 14 16

18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

BELLW _80060-1021

12

R329

100K_04 02_5%

RAID0_DET

H

L

RAID0_DET <18>

MSATA_D ET#

3 3

4 4

Security Class ification

2012/4/6 2013/4/6

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/4/6 2013/4/6

C

Compal Secret Data

Deciphered Date

MSATA_D ET# <1 8>

D

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

mSATA HDD Connector

Q3ZMC M/B LA-8481P Schematic

29 51Thu rsday, April 12, 2012

E

1.0

5

4

3

2

1

MOTOR/RTC

40mils40mils

D

S

45

Q87

Q87 SI3456DDV-T1-GE3_TSOP6

SI3456DDV-T1-GE3_TSOP6

G

3

1

C811

0.1U_0603_25V7K

2

+3V_MCU

JMR1

1 2 3 4 5 6 7 8 9 10

+MT_VCC +3V_MCU

MOTOR_PPS_L MOTOR_PPS_R

VR_LEFT VR_RIGHT

+RTCBATT_R

40mil

20mil

VR_LEFT <32> VR_RIGHT <32>

MOTOR_PPS_L <32> MOTOR_PPS_R < 32>

MOTOR_PWR_ON<32,45>

DMN66D0LDW-7_SOT363-6

+3VALW

12

R21

R21 10K_0402_5%

10K_0402_5%

MOTOR_PWR_ON# MOTOR_GATE

61

2

Q93A

1

D D

C C

2 3 4 5 6 7

8 GND GND

E-T_4260K-Q08N-13L

CONN@

10mils

5

+VSB

+3VALW

R789

R789 470K_0402_5%

470K_0402_5%

1 2

34

Q93B

Q93B DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

6

2 1

TPM

+3VALW

J17

@J17

@

2

112

JUMP_43X39

+3VS

J15

@J15

@

2

112

JUMP_43X39

TXM@

10U_0603_6.3V6M

B B

1 2

R963 10K_0402_5%@R963 10K_0402_5%@

CLKRUN#<15>

LPC_AD0<13,32>

LPC_AD1<13,32>

LPC_AD2<13,32>

LPC_AD3<13,32>

CLK_PCI_TXM<17>

LPC_FRAME#<13,32>

PLT_RST#<17,22,24,32,5>

SERIRQ<13,32>

A A

CLK_PCI_TXM

1

12

TXM@

C3

C1

C3

0.1U_0201_10V6K

2

near pin24 near pin19 near pin5

CLK_PCI_TXM LPC_FRAME# PLT_RST# SERIRQ

@

1 2

R716

33_0402_5%

5

10mil 10mil

+3V_TXM

1

TXM@

C4

0.1U_0201_10V6K

2

U7

TPM@U7

TPM@

1

GPIO0/XOR_OUT

2

GPIO1

6

GPIO2/GPX

9

BADD_BA0 CLKRUN#

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

@C724

@

1 2

22P_0402_50V8J

C724

GPIO3/BADD

15

GPIO4/CLKRUN#

26

LAD0

23

LAD1

20

LAD2

17

LAD3

28

LPCPD#

21

LCLK

22

LFRAME#

16

LRESET#

27

SERIRQ

7

PP

NPCT42XAA0WX_TS SOP28

SA00005PH00

+3VALW +3VALW_TPM

J16

112

JUMP_43X39

10U_0603_6.3V6M

5

+3VALW_TPM_R

VSB

19

VDD1

24

VDD2

8

TEST

3

NC

10

NC

11

NC

12

NC

13

NC

14

NC

4

VSS1

18

VSS2

25

VSS3

@J16

@

TPM@

+3V_TXM

2

C6

12

R966 0_040 2_5%TPM@R966 0_0402_5%TPM @

4

1

TPM@

C9

0.1U_0201_10V6K

2

1 2

+3VALW_TPM

TPM -Address: Pin9 BADD 1: 7Eh-7Fh (Default) 0: EEh-EFh

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

TPM

Q3ZMC M/B LA-8481P Schematic

1

30 51Thursday, April 12, 2012

1.0

5

1 2

R9 0_0402_ 5%@R9 0_ 0402_5%@

USB3.0@

12

PCH_USB 3_TX1_P<1 7>

PCH_USB 3_TX1_N<17>

D D

PCH_USB 3_RX1_P<17>

PCH_USB 3_RX1_N<17>

USB20_P 0<17>

USB20_N 0<1 7>

USB20_P 9<17>

USB20_N 9<1 7>

C424 0.1U_0201 _10V6K

C422 0.1U_0201 _10V6K

1 2

R710 0_0 402_5%R71 0 0_0402_5%

1 2

R713 0_0 402_5%R71 3 0_0402_5%

1 2

R715 0_0 402_5%

1 2

R714 0_0 402_5%

USB3.0@

@

PCH_USB 3_TX1_P_C

12

PCH_USB 3_TX1_N_C

PCH_USB 3_RX1_P

USB20_P 0P9

USB20_N 0N9

USB20_P 0P9

USB20_N 0N9

USB3.0@

2

3

L3 O CE2012120YZF_4 P

1 2

R10 0_0402_ 5%@R1 0 0_ 0402_5%@

1 2

R11 0_0402_ 5%@R1 1 0_ 0402_5%@

USB3.0@

2

3

L4 OCE 2012120YZF_4P

1 2

R12 0_0402_ 5%@R1 2 0_ 0402_5%@

R691 0_0 402_5%

USB20_N 0N9 U2DN0

USB20_P 0P9

L52 WC M2012F2S-900T 04_0805

R689 0_0 402_5%

Resister overlap with L52

C C

2

3

USB3.0@

1

4

1

4

1 2

@

2

3

1 2

@

4

For ESD request

D35

1

U3TXDP1

4

U3TXDN1

1

U3RXDP1

4

U3RXDN1PCH_USB 3_RX1_N

1

4

U3TXDP1

U3TXDN1

U3RXDP1

+USB3_V CCA

U2DP0

1

2

4

5

3

8

L05ESDL 5V0NA-4 SLP251 0P8

For USB2.0 ESD request

D24

6

U2DP0

I/O4

5

VDD

4

I/O3

AZC099-0 4S.R7G_SOT23-6

3

@

9

10

9

7

65

U3TXDP1

8

U3TXDN1

7

U3RXDP1

6

U3RXDN1U3RXDN1

0.01U_04 02_16V7K

USB_EN#<3 2> USB_OC0 # <17>

W=80mils

3

I/O2

2

GND

I/O1

1

U2DN0

USB_HPD #<32>

+3VALW

12

R744

R744 100K_04 02_5%

100K_04 02_5%

C432

1 2

2

1

U2DN0 U2DP0

U3RXDN1 U3RXDP1

U3TXDN1 U3TXDP1

2

+5VALW

U17

1

GND

VOUT

2

VOUT

VIN VIN3VOUT

4

+USB3_V CCA

C393

470P_0402_50V7K

C393

470P_0402_50V7K

SGA00001E00 S POLY C 150U 6.3V M B2LESR45M PSL H1.9

USB3.0 Conn.

JUSB1

1

VBUS

2

D-

3

D+

4

GND

5

SSRX-

6

SSRX+

7

GND

8

SSTX-

9

SSTX+

10

DET

TAIWI_US B005-107CRL-TW

CONN@

FLG

EN

EPAD

AP2301M PG-13_MSOP8

9

11

GND

12

GND

13

GND

14

GND

+USB3_V CCA

8 7 6 5

R314

@R 314

@

0_0402_ 5%

1 2

1

C417

@

0.1U_040 2_16V4Z

2

1

1 2

R20 0_0402_ 5%@R2 0 0_ 0402_5%@

USB3.0@

12

PCH_USB 3_TX2_P<1 7>

PCH_USB 3_TX2_N<17>

PCH_USB 3_RX2_P<17>

PCH_USB 3_RX2_N<17>

B B

A A

C428 .1U_0402_ 16V7K

C427 .1U_0402_ 16V7K

USB3.0@

USB20_P 1<17>

12

USB20_N 1<1 7>

PCH_USB 3_TX2_P_C

PCH_USB 3_TX2_N_C

PCH_USB 3_RX2_P

PCH_USB 3_RX2_N

USB3.0@

2

3

L6 O CE2012120YZF_4 P

1 2

R15 0_0402_ 5%@R1 5 0_ 0402_5%@

1 2

R16 0_0402_ 5%@R1 6 0_ 0402_5%@

USB3.0@

2

3

L5 OCE 2012120YZF_4P

1 2

R17 0_0402_ 5%@R1 7 0_ 0402_5%@

1 2

R743 0_0 402_5%

USB3.0@

2

3

L53 WC M2012F2S-900T 04_0805

1 2

R693 0_0 402_5%

1

4

1

4

@

1

4

@

U3TXDP2

U3TXDN2

U3RXDP2

U3RXDN2

U2DN1

U2DP1

+USB3_V CCA

For ESD request

D36

U3TXDP2

U3TXDN2

U3RXDP2

1

2

4

5

3

8

L05ESDL 5V0NA-4 SLP251 0P8

For USB2.0 ESD request

D33

6

U2DP1

I/O4

5

VDD

4

I/O3

AZC099-0 4S.R7G_SOT23-6

+3VALW

12

R745

R745 100K_04 02_5%

100K_04 02_5%

W=80mils

150U_B2_6.3VM_R35M

@

9

U3TXDP2

8

U3TXDN2

7

U3RXDP2

6

U3RXDN2U3RXDN2

USB_HPD #

3

2

1

U2DN1

I/O2

GND

I/O1

10

9

7

65

+USB3_V CCA

C391

470P_0402_50V7K

C391

470P_0402_50V7K

2

1

C394

+

1

2

SGA00001E00 S POLY C 150U 6.3V M B2LESR45M PSL H1.9

USB3.0 Conn.

JUSB2

1

VBUS

U2DN1 U2DP1

U3RXDN2 U3RXDP2

U3TXDN2 U3TXDP2

2

D-

3

D+

4

GND

5

SSRX-

6

SSRX+

7

GND

8

SSTX-

9

SSTX+

10

DET

TAIWI_US B005-107CRL-TW

CONN@

GND GND GND GND

11 12 13 14

Security Class ification

2012/4/6 2013/4/6

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/4/6 2013/4/6

3

Compal Secret Data

Deciphered Date

Title

Size Document Num ber Rev

Custom

Date: Sheet of

2

Date: Sheet of

USB3.0

Q3ZMC M/B LA-8481P Schematic

31 51Thu rsday, April 12, 2012

1

1.0

A

C1205

@ C1205

@

22P_0402_50V8J

12

+3VALW_EC

1 1

2 2

3 3

R938 47K _0402_5%R938 47K_0402_5%

C1208 0.1U_0201_10V6KC1208 0.1U_0201_10V6K

+3VALW_EC

1 2

R939 1K_0402_5%@R939 1K_0402_5%@

1 2

R941 2.2K_0402_5%R941 2.2K_0402_5%

1 2

R942 2.2K_0402_5%R942 2.2K_0402_5%

1 2

R943 10K_0402_5%@R943 10K_0402_5%@

+3VS

1 2

R944 2.2K_0402_5%R944 2.2K_0402_5%

1 2

R945 2.2K_0402_5%R945 2.2K_0402_5%

1 2

R946 10K_0402_5%R946 10K_0402_5%

1 2

R949 100K_0402_5%R949 100K_0402_5%

1 2

C1209 0.01U_0402_16V7K

@

+3VALW

R957

R957 100K_0402_5%

100K_0402_5%

Ra

1 2

AD_BID0

R960

R960 56K_0402_5%

56K_0402_5%

Rb

1 2

R933

@ R 933

@

33_0402_5%

12

CLK_PCI_LPC

12

EC_RST#

EC_SMI#

EC_SMB_DA1

EC_SMB_CK1

EC_PME#

EC_SMB_CK2

EC_SMB_DA2

EC_SCI#

PLT_RST#

ESD request

R951 0_0402_5%R951 0_0402_5%

USB_EN#<31>

+3VALW_EC

Board ID

Analog Board ID definition, Please see page 3.

1

C1213

0.1U_0201_10V6K

2

R952 0_0402_5%@R952 0_0402_5 %@

1 2

R965 10K_0402_5%R965 10K_0402_5%

+3VALW

+3VLP

12 12

SYSON# <35>

IRST_RST#

J9

112

JUMP_43X39

J11

112

JUMP_43X39

KSI[0..7]<33>

KSO[0..15]<33>

SUSCLK<15>

@J9

@

@J11

@

E51TXD_P80DATA<29> E51RXD_P80CLK<29>

B

2

C1198

0.1U_0201_10V6K

C1198

0.1U_0201_10V6K

1

2

GATEA20<18>

EC_KBRST#<18>

SERIRQ<13,30>

LPC_FRAME#<13,30>

LPC_AD3<13,30> LPC_AD2<13,30> LPC_AD1<13,30> LPC_AD0<13,30>

CLK_PCI_LPC<17>

PLT_RST#<17,22,24,30,5>

EC_SCI#<18> AOAC_ON<28>

KSI[0..7]

KSO[0..15]

ACPRESENT<15>

EC_SMB_CK1<37,38> EC_SMB_DA1<37,38> EC_SMB_CK2<11,14,24> EC_SMB_DA2<11,14,24>

PM_SLP_S3#<15> PM_SLP_S5#<15>

EC_SMI#<18> PCH_PWR_EN<35> MOTOR_BTN<33>

DPWROK<15>

IRST_RST#<17>

BI_DET< 33>

FAN_SPEED1<34>

EC_PME#<28>

PWR_SUSP_LED#<22>

MOTOR_LED#<33>

TB_LED<25>

1 2

R959 0_0402_ 5%

R961 100K_0402_5%R961 100K_0402_5%

C1215 20P_0402_50V 8C 1215 2 0P_0402_50V8

Follow KB930 checking List

C1199

0.1U_0201_10V6K

C1199

0.1U_0201_10V6K

1

2

GATEA20 EC_KBRST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

CLK_PCI_LPC PLT_RST# EC_RST# EC_SCI# AOAC_ON

USB_EN#_R ACPRESENT

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

PM_SLP_S3# PM_SLP_S5# EC_SMI#

PCH_PWR_EN

MOTOR_BTN

DPWROK

IRST_RST# BI_DET FAN_SPEED1 EC_PME# E51TXD_P80DATA E51RXD_P80CLK 9012_PCH_PWROK PWR_SUSP_LED# MOTOR_LED#

TB_LED

@

12

1 2

0.1U_0201_10V6K

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15

C

L56

L56 FBMA-L11-160808-800LMT_0603

FBMA-L11-160808-800LMT_0603

Int. K/B

Int. K/B Matrix

Matrix

1 2

9

22

EC_VDD/VCC

PS2 Interface

SM Bus

11

EC_VDD/VCC

GND/GND

C1202

1000P_0201_16V7K

C1202

1000P_0201_16V7K

2

1

U53

1

GATEA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ

4

LPC_FRAME#

5

LPC_AD3

7

LPC_AD2

8

LPC_AD1

10

LPC_AD0

12

CLK_PCI_EC

13

PCIRST#/GPIO05

37

EC_RST#

20

EC_SCII#/GPIO0E

38

GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

EC_SMB_CK1/GPIO44

78

EC_SMB_DA1/GPIO45

79

EC_SMB_CK2/GPIO46

80

EC_SMB_DA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

GPIO0A

17

GPIO0B

18

GPIO0C

19

GPIO0D

25

EC_INVT_PWM/GPIO11

28

FAN_SPEED1/GPIO14

29

EC_PME#/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

PCH_PWROK/GPIO18

34

SUSP_LED#/GPIO19

36

NUM_LED#/GPIO1A

122

XCLKI/GPIO5D

123

XCLKO/GPIO5E

+3VALW_EC

C1203

1000P_0201_16V7K

C1203

1000P_0201_16V7K

LPC & MISC

9012@

C1201

0.1U_0201_10V6K

C1201

0.1U_0201_10V6K

C1200

1

2

+EC_VCCA

+EC_VCC

33

67

96

111

125

EC_VDD0

EC_VDD/VCC

EC_VDD/AVCC

PWM Output

DA Output

SPI Device Interface

GPIO

GND/GND

24

35

BATT_TEMP/GPIO38

AD Input

CPU1.5V_S3_GATE/GPXIOA00

HDA_SDO/GPXIOA02 VCIN0_PH/GPXIOD00

SPI Flash ROM

PECI_KB930/GPIO41

BATT_CHG_LED#/GPIO52

GPIO

BATT_LOW_LED#/GPIO55

PM_SLP_S4#/GPIO59

EC_RSMRST#/GPXIOA03

EC_LID_OUT#/GPXIOA04 PROCHOT_IN/GPXIOA05

H_PROCHOT#_EC/GPXIOA06

VCOUT0_PH/GPXIOA07

GPO

PBTN_OUT#/GPXIOA09

PCH_APWROK/GPXIOA10

SA_PGOOD/GPXIOA11

GPI

PECI_KB9012/GPXIOD07

GND/GND

AGND/AGND

GND/GND

GND0

69

94

20mil

113

ECAGND

FBMA-L11-160808-800LMT_0603

+EC_VCC <37>

GPIO0F

BEEP#/GPIO10

GPIO12

ACOFF/GPIO13

GPIO39

ADP_I/GPIO3A

GPIO3B GPIO42

IMON/GPIO43

DAC_BRIG/GPIO3C

EN_DFAN1/GPIO3D

IREF/GPIO3E

CHGVADJ/GPIO3F

EC_MUTE#/GPIO4A

USB_EN#/GPIO4B

CAP_INT#/GPIO4C

EAPD/GPIO4D

TP_CLK/GPIO4E

TP_DATA/GPIO4F

WOL_EN/GPXIOA01

SPIDI/GPIO5B

SPIDO/GPIO5C SPICLK/GPIO58 SPICS#/GPIO5A

ENBKL/GPIO40

FSTCHG/GPIO50

CAPS_LED#/GPIO53

PWR_LED#/GPIO54

SYSON/GPIO56 VR_ON/GPIO57

BKOFF#/GPXIOA08

AC_IN/GPXIOD01

EC_ON/GPXIOD02

ON/OFF/GPXIOD03

LID_SW#/GPXIOD04

SUSP#/GPXIOD05

GPXIOD06

V18R

KB9012QF-A3_LQFP128_14X14

L57

21

MOTOR_PWR_ON

23

BEEP#

26

FAN_PWM

27

ACOFF

63

BATT_TEMP

64 65

ADP_I

66

AD_BID0

75

VR_RIGHT

76

TB_OK2GO2SX#

68

SUSACK#

70

TB_GO2SX

71

WL_OFF#

72

TB_PWRON_POC_RST#

83

EC_MUTE#

84

SLP_SUS#

85

MOTOR_PPS_L

86

EAPD

87

TP_CLK

88

TP_DATA

97

USB_HPD#

98

DRAMRST_CNTRL_EC

99

HDA_SDO

109

VCIN0_PH_R

119

BT_LED

120

EC_SPOK

126

MOTOR_VID0

128

MOTOR_VID1

73

ENBKL

74

VR_LEFT

89

FSTCHG

90

BATT_BLUE_LED#

91

MOTOR_PPS_R

92

PWR_LED#

93

BATT_AMB_LED#

95

SYSON

121

VR_ON

127

PM_SLP_S4#

100

PCH_RSMRST#

101

EC_LID_OUT#

102

VCIN1_PROCHOT_R

103

H_PROCHOT#_EC

104

GPXIOA07

105

BKOFF#

106

PBTN_OUT#

107

SUSWARN#

108

SA_PGOOD

110

EC_ACIN

112

EC_ON

114

ON/OFF

115

LID_SW#

116

SUSP#

117

BT_ON#

118

KB9012_PECI

124

+V18REC_XCLK0

12

1

C1204

0.1U_0201_10V6K

2

ECAGND

C1206 100P _0402_50V8JC1206 100P_0402_50V8J

2

1

1000P_0201_16V7K

BEEP# <33> FAN_PWM <34> ACOFF <36>

12

BATT_TEMP <37>

TB_EJECT_BTN < 25>

ADP_I <37,38>

VR_RIGHT <30>

TB_GO2SX <24>

TB_PWRON_POC_RST# <24>

EC_MUTE# <33>

SLP_SUS# <15>

EAPD <33> TP_CLK <33> TP_DATA <33>

USB_HPD# <31> DRAMRST_CNTRL_EC <6>

HDA_SDO <13>

BT_LED <28> EC_SPOK <37> MOTOR_VID0 <45> MOTOR_VID1 <45>

12

R950 100K_0402_5%R950 100K_0402_5%

C1214

4.7U_0603_6.3V6K

ENBKL <16> VR_LEFT <30> FSTCHG <38> BATT_BLUE_LED# <22>

PWR_LED# <22>

BATT_AMB_LED# <22>

SYSON <35,40> VR_ON <43>

PCH_RSMRST# <15> EC_LID_OUT# <18>

BKOFF# <22> PBTN_OUT# <15>

SUSWARN# <1 5> SA_PGOOD <42>

EC_ON <39> ON/OFF <33> LID_SW# <22> SUSP# <35,38,40,41> BT_ON# <28>

MOTOR_PWR_ON <30,45>

TB_OK2GO2SX# <24>

SUSACK# <15>

WL_OFF# <28>

MOTOR_PPS_L <30>

MOTOR_PPS_R < 30>

PM_SLP_S4# <15>

C451

D

FAN_PWMFAN _SPEED1

1

2

ECAGND

1

C450

C450 1000P_0201_16V7K

1000P_0201_16V7K

2

ECAGND <37>

LID_SW#

EC_MUTE#

BKOFF#

TP_CLK

TP_DATA

EC_ACIN

VR_HOT#<43>

E

1 2

2 1

12

VR_HOT#

H_PROCHOT#_EC

12

R940

R940 0_0402_5%

0_0402_5%

@

2

G

R948 100K_0402_5%R948 100K_0402_5%

R928 10K_0402_5%@R928 10K_0402_5%@

R934 10K_0402_5%@R934 10K_0402_5%@

R929 4.7K_0402_5%R929 4.7K_0402_5%

R931 4.7K_0402_5%R931 4.7K_0402_5%

R935 200K_0402_5%930@R935 200K_0 402_5%930@

R1017 200K_0402_5%9012@R101 7 200K_0402_5%9012@

D37 RB751V-40_SOD323-2D37 RB751V-40_SOD323-2

C1207 100P_0402_50V8JC1207 100P_0402_50V8J

12

13

D

S

+3VALW

+3VS

+3VALW

+3VLP

ACIN <15,35,38,39>

H_PROCHOT# <5>

Q60

Q60 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

Latest design guide suggest change to 74LVC1G06.

KB930&9012 Co-Layout Item

Pin 111 is a power source for HW operation of KB9012. So, power plan will be different between KB930 and KB9012.

+EC_VCC

Pin74(KB930),Pin118(KB9012) are with different PECI pin location, so HW must co-layout for it. Please make sure which EC pin will be connected to PECI circuit.

KB9012_PECI

Pin104 co-layout circuit is for power fail function of KB930 and KB9012. At KB930, PCH_PWROK will be connected to pin 104. At KB9012,PCH_PWROK will be connected to pin 32, and VCOUT0_PH will be connected to pin 104.

9012_PCH_PWROK

GPXIOA07

VCIN0_PH_R

VCIN1_PROCHOT_R

KSO1

KSO2

1 2

R930 0_0402_5%

1 2

R932 0_0402_5%

R958 43_0402_1%9012@R958 43_0402_1%9012@

R956 0_040 2_5%

R955 0_0402_5%930@R955 0_0402_5%930@

R954 0_0402_5%9012@R954 0_0402_5%9012@

R936 47K_0402_5%930@R936 47K_0402_5%930@

R937 47K_0402_5%930@R937 47K_0402_5%930@

TB_EJECT_BTN

930@

9012@

1 2

R947 0_0402_5%

R953 0_0402_5%

R976 2.2K_0402_5%R976 2.2K_0402_5%

12

@

12

1 2

@

1 2

@

12

1 2

+3VALW

+3VLP

+3VALW_EC

H_PECI <18,5>

PCH_PWROK <15>

MAINPWON <39>

VCIN0_PH <37>

VCIN1_PROCHOT <37>

+3VALW_EC

4 4

VR_RIGHT

R454

R454 100K_0402_1%

100K_0402_1%

1 2

A

VR_LEFT

R455

R455 100K_0402_1%

100K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

B

C

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

EC ENE-KB930/KB9012

Q3ZMC M/B LA-8481P Schematic

E

32 51Thursday, April 12, 2012

1.0

1

2

3

4

5

6

7

8

R974

R974 0_0402_5%

0_0402_5%

R908

100K_0402_5%

+3VALW +3VLP

930@

R144

R144 100K_0402_5%

100K_0402_5%

1 2

+3VALW_EC +3VL P

1 2

9012@

R907

R907 100K_0402_5%

100K_0402_5%

1 2

@

R909

R909 100K_0402_5%

100K_0402_5%

MOTOR_BTN <32>

ON/OFF <32>ON/OFFBTN#<22>

TP Conn.

JKB1

1

KSI0

1

2

KSI1

2

3

KSI2

3

4

KSO0

4

5

KSO1

5

6

KSO2

6

7

KSI3

7

8

KSO3

8

A A

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

GND1

26

GND2

ACES_85208-24071

CONN@

KSO4 KSO5 KSO6 KSO7 KSO8 KSI4 KSO9 KSI5 KSI6 KSO10 KSO11 KSI7 KSO12 KSO13 KSO14 KSO15

KSI[0..7]

KSO[0..15]

BOT side

KSO15

KSO14

B B

KSO13

KSO12

KSI0

KSO11

KSO10

KSI1

KSI2

KSO9

KSI3

KSO8

C C

1 2

C260 100P_ 0201_25V8J@C260 100P_0201_25V 8J@

1 2

C259 100P_ 0201_25V8J@C259 100P_0201_25V 8J@

1 2

C258 100P_ 0201_25V8J@C258 100P_0201_25V 8J@

1 2

C271 100P_ 0201_25V8J@C271 100P_0201_25V 8J@

1 2

C263 100P_ 0201_25V8J@C263 100P_0201_25V 8J@

1 2

C256 100P_ 0201_25V8J@C256 100P_0201_25V 8J@

1 2

C255 100P_ 0201_25V8J@C255 100P_0201_25V 8J@

1 2

C272 100P_ 0201_25V8J@C272 100P_0201_25V 8J@

1 2

C265 100P_ 0201_25V8J@C265 100P_0201_25V 8J@

1 2

C254 100P_ 0201_25V8J@C254 100P_0201_25V 8J@

1 2

C266 100P_ 0201_25V8J@C266 100P_0201_25V 8J@

1 2

C253 100P_ 0201_25V8J@C253 100P_0201_25V 8J@

KSO7

KSO6

KSO5

KSO4

KSO3

KSI4

KSO2

KSO1

KSO0

KSI5

KSI6

KSI7

EMI request

1 2

C252 100P_ 0201_25V8J@C252 100P_0201_25V 8J@

1 2

C251 100P_ 0201_25V8J@C251 100P_0201_25V 8J@

1 2

C250 100P_ 0201_25V8J@C250 100P_0201_25V 8J@

1 2

C249 100P_ 0201_25V8J@C249 100P_0201_25V 8J@

1 2

C248 100P_ 0201_25V8J@C248 100P_0201_25V 8J@

1 2

C267 100P_ 0201_25V8J@C267 100P_0201_25V 8J@

1 2

C247 100P_ 0201_25V8J@C247 100P_0201_25V 8J@

1 2

C246 100P_ 0201_25V8J@C246 100P_0201_25V 8J@

1 2

C245 100P_ 0201_25V8J@C245 100P_0201_25V 8J@

1 2

C268 100P_ 0201_25V8J@C268 100P_0201_25V 8J@

1 2

C269 100P_ 0201_25V8J@C269 100P_0201_25V 8J@

1 2

C270 100P_ 0201_25V8J@C270 100P_0201_25V 8J@

KSI[0..7] <32>

KSO[0..15] <32>

+3VS

CONN@

JTP1

10

G

9

G

8

7

6

5

4

3

2

1

E-T_6701K-Q08N-00R

+3VS

1

C196

0.1U_0201_10V6K

2

SMB_ALERT#_R

12

R971

R971 10K_0402_5%

10K_0402_5%

1

+3VS

C217

100P_0402_50V8J

AZ5125-02S.R7G_SOT23-3

2

@D6

@

D6

Audio/B 20pin

JAUDIO

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

G1

22

G2

23

G3

24

G4

ACES_50406-02071-001

CONN@

BEEP

BI_GATE#

MOTOR_BTN_SW#

HDA_BITCLK_AUDIO <13>

HDA_RST_AUDIO# <13>

HDA_SYNC_AUDIO <13>

HDA_SDOUT_AUDIO <13>

HDA_SDIN0 <13>

EAPD <32>

EC_MUTE# <32>

MOTOR_LED# <32> +3VALW +3VS +5VS

SMB_ALERT#<14>

1

C216

C216 100P_0402_50V8J

100P_0402_50V8J

2

3

1

10mil 20mil 60mil

D_CK_SCLK <14> D_CK_SDATA <14>

TP_DATA <32>

TP_CLK <32>

D_CK_SCLK

D_CK_SDATA

+3VS

2

G

1 3

SMB_ALERT#_R

D

S

D

S

Q9

SSM3K7002FU_SC70-3

TP_DATA

TP_CLK

2

3

D4

@D4

@

AZ5125-02S.R7G_SOT23-3

1

BEEP#<32>

PCH_SPKR<13>

Battery Reset

BI_GATE#

ON/OFF BTNKB Conn.

Motor BTN

1 2

C1224

1U_0402_6.3V6K

1 2

C1227

1U_0402_6.3V6K

10mil

+RTCVCC

12

R969

1K_0402_5%

13

2

G

MOTOR_BTN_SW#

+3VS

12

R968

10K_0402_5%

R970

1 2

560_0402_5%

R972

1 2

560_0402_5%

1 2

R850 510K_0402_5%R850 510K_0402_5%

D

Q8

Q8 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

Need Check Gate Threshold Volt age Battery BI Low voltage is 0.8V

BEEP

12

D41

D41 RB751V-40_SOD323-2

RB751V-40_SOD323-2

ON/OFFBTN#

BAV70W_SOT323-3

R975 0_0402_5%@R975 0_0402_5 %@

BI_DET <32>

BI <37>

D22

1

1 2

R967 0_0402_5%@R967 0_0402_5 %@

2

3

1 2

D D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

1

2

3

4

2012/4/6 2013/4/6

5

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Q3ZMC M/B LA-8481P Schematic

Date: Sheet of

6

Date: Sheet of

7

Compal Electronics, Inc.

BIOS, I/O Port & K/B Connector

33 51Thursday, April 12, 2012

8

1.0

FAN Conn

FAN_SPEED1<32>

20mil

+5VS

+3VS

12

R489

R489 10K_0402_5%

10K_0402_5%

1

C579

C579 1000P_0402_50V7K@

1000P_0402_50V7K@

2

C585

10U_0805_25V6K

1 2

C587

1000P_0402_50V7K

1 2

FD1

@

1

FIDUCIAL_C40M80

FD2

@

1

FIDUCIAL_C40M80

FD3

@

1

FIDUCIAL_C40M80

FD4

@

1

FIDUCIAL_C40M80

Stand-Off

H3

H4

H5

H2

H1

JFAN1

4

6

4

G2

3

FAN_SPEED1

FAN_PWM<32>

FAN_PWM

5

3

G1

2

1

ACES_88266-04001

CONN@

H1

H_5P2

@

1

Thermal module

H6

H_4P0

@

1

定定定定定定定定定定定定

H10

H_2P5x3P0

@

1

H_5P2

H7

H_4P0

1

@

H11

H_4P0N

H_5P2

H_4P0

1

@

1

H8

@

1

@

H_5P2

H9

H_4P0

H5

H_5P2

@

1

@

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Step Motor,FAN,Screw Hole

Q3ZMC M/B LA-8481P Schematic

34 51Thursday, April 12, 2012

1.0

A

B

C

D

E

+5VALW to +5VS +3VALW to +3VALW_PCH(PCH AUX Power)

Ω

Rds=13.5m

16.5mΩ(Max)

1 1

(Typ)

+VSB

20mil

+5VALW

C464

4.7U_0603_10V6K

C464

4.7U_0603_10V6K

5

2

1

12

R437

R437 20K_0402_5%

20K_0402_5%

5

SUSP

Q19A

DMN66D0LDW-7_SOT363-6

Q19A

U22

U22 SI7716ADN-T1-GE3_POWERPAK8-5

SI7716ADN-T1-GE3_POWERPAK8-5

4

10mil

5VS_GATE

34

D

G

S

1 2 3

+5VS

4.7U_0603_10V6K

2

1

C499

C499 .1U_0603_25V7K

.1U_0603_25V7K

2

C498

C469

1U_0603_10V6K

C469

1U_0603_10V6K

1

R440

470_0603_5%

2

470_0603_5%

1 2

61

D

G

2

SUSP

S

Q19B

Q19B DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

+3VALW

R629 0_0402_5%@R629 0_0402_5 %@

20mil

+3VALW_PCH

12

C701

4.7U_0603_6.3V6K

C701

4.7U_0603_6.3V6K

2

1

SUSP<40,5>

SUSP#<32,38,40,41>

10K_0402_5%

SUSP

R251

+5VALW

1 2

34

D

G

5

S

12

R246

R246 100K_0402_5%

100K_0402_5%

DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6 Q59A

Q59A

+3VALW to +3VS

Rds=13.5mΩ(Typ)

16.5mΩ(Max)

12

2 2

+VSB

+3VALW

U21

U21 SI7716ADN-T1-GE3_POWERPAK8-5

SI7716ADN-T1-GE3_POWERPAK8-5

C375

10U_0603_6.3V6M

C375

10U_0603_6.3V6M

5

4

R368

47K_0402_5%

10mil

12

3VS_GATE

20mil

34

D

G

5

SUSP

DMN66D0LDW-7_SOT363-6

Rds=2.6mΩ(Typ)

3.2mΩ(Max)

C460

10U_0603_6.3V6M

C460

10U_0603_6.3V6M

12

1

2

3 3

+VSB

20mil

C377

0.1U_0402_16V4Z

C377

0.1U_0402_16V4Z

+1.35V

C376

0.1U_0402_16V4Z

C376

0.1U_0402_16V4Z

1

2

R269

R269 200K_0402_5%

200K_0402_5%

SUSP

DMN66D0LDW-7_SOT363-6

ACIN<15,32,38,39>

S

Q25A

+1.35V to +1.35VS

U12

U12 SI7716ADN-T1-GE3_POWERPAK8-5

SI7716ADN-T1-GE3_POWERPAK8-5

5

4

10mil

12

1.35VS_GATE SUSP

12

@

R268

510K_0402_5%@R268

510K_0402_5%

34

D

G

5

S

Q15A

13

D

@

2

ACIN

G

S

Q21

Q21 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

1 2 3

12

1

C463

C463 .1U_0603_25V7K

.1U_0603_25V7K

2

@

R277

1M_0402_5%@R277

1M_0402_5%

+3VS

4.7U_0603_6.3V6K

2

1

+1.35VS

2

1

C380

C380 .1U_0603_25V7K

.1U_0603_25V7K

2

C458

1U_0402_6.3V6K

C458

1U_0402_6.3V6K

C461

1

2

C339

4.7U_0603_6.3V6K

C339

4.7U_0603_6.3V6K

C338

1U_0402_6.3V6K

C338

1U_0402_6.3V6K

1

2

R436

R436 470_0603_5%

470_0603_5%

1 2

61

D

G

2

SUSP

S

Q25B

Q25B DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

R245

R245 470_0603_5%

470_0603_5%

1 2

61

D

G

2

S

Q15B

Q15B DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

SYSON#<32>

SYSON<32,40>

SYSON#

SYSON

R438

100K_0402_5%

+5VALW

R441

R441 100K_0402_5%

100K_0402_5%

1 2

61

D

G

2

Q59B

S

DMN66D0LDW-7_SOT363-6

12

DMN66D0LDW-7_SOT363-6

+5VALW

R449

R449 100K_0402_5%

100K_0402_5%

1 2

PCH_PWR_EN#<20>

13

D

2

Q26

PCH_PWR_EN<32>

100K_0402_5%

R450

12

G

Q26 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

+1.8VS+0.675VS +1.05VS_VTT+1.35V

4 4

R365

@R365

@

470_0603_5%

1 2

Q24

13

D

@

2

G

SSM3K7002FU_SC70-3

S

12

R366

R366 22_0603_5%

22_0603_5%

13

D

Q23

2

G

SSM3K7002FU_SC70-3

S

A

R29

R29 470_0603_5%

470_0603_5%

1 2 13

D

Q5

2

G

SSM3K7002FU_SC70-3

S

R508

R508 470_0603_5%

470_0603_5%

1 2 13

D

Q34

SUSP SUSPSUSPSYSON#

B

2

G

SSM3K7002FU_SC70-3

S

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

DC Interface

Q3ZMC M/B LA-8481P Schematic

E

35 51Thursday, April 12, 2012

1.0

A

B

C

D

1 1

PJP1

1

2

3

4

5

GND

6

GND

ACES_88266-04001

2 2

LL4148_LL34-2

3 3

LL4148_LL34-2

BATT+

PD4

@PD4

@

12

DC_IN_S1

12

PC1

PC1 1000P_0402_50V7K

1000P_0402_50V7K

VS

PL1

SMB3025500YA_2P

1 2

12

PC2

100P_0402_50V8J

12

PC3

100P_0402_50V8J

12

PC4

1000P_0402_50V7K

PR1

1K_1206_5%

1 2

PR2

1K_1206_5%

VIN

ACOFF<32>

1K_1206_5%

1 2

PR3

1K_1206_5%

1 2

PR4

1K_1206_5%

1 2

0_0402_5%

PR22

12

+5VALWP

PJ1

+3VALWP +3VALW +5VALWP +5VALW

+VSBP +VSB

112

JUMP_43X79

PJ8

112

JUMP_43X39

PJ3

112

JUMP_43X39

2

PD2

BAS40CW _SOT323-3

2

1

3

LL4148_LL34-2

PD1

12

2

Pre_CHG

12

PR5

13

TP0610K-T1-E3_SOT23- 3

12

PR6

100K_0402_5%

PQ2

PQ2 PDTC115EU_SOT323-3

PDTC115EU_SOT323-3

2

JUMP_43X39

PQ1

2

12

100K_0402_5%

13

PJ2

112

JUMP_43X79

PJ10

112

PJ4

112

JUMP_43X79

PJ5

112

JUMP_43X79

13

PR7

PQ3

PQ3 PDTC115EU_SOT323-3

PDTC115EU_SOT323-3

2

B+

+1.35V+1.35VP

VIN

PJ7

PJ6

+1.8VSP +1.8VS

+3VLP

PR102

PR57

4 4

+RTCBATT_R

A

PR57

560_0603_5%

1 2

PR102

560_0603_5%

1 2

+RTCBATT

+CHGRTC

PR12

0_0402_5%

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

+VCCSAP +VCCSA

JUMP_43X118

+1.05VS_LCP +1.05VS_LC

Compal Secret Data

2012/4/6 2013/4/6

Compal Secret Data

112

JUMP_43X39

PJ9

112

JUMP_43X39

PJ11

112

PJ15

112

JUMP_43X39

Deciphered Date

C

2

+0.675VS+0.675VSP

+1.05VS_VCCPP

+HV_12VP +HV_12V

Title

Size D ocument Number Rev

Custom

Date: Sheet of

PJ7

2

112

JUMP_43X79

PJ12

2

112

JUMP_43X39

Compal Electronics, Inc.

DCIN/PRECHARGE

Chief River VC

D

+1.05VS_VTT

36 51Thursday, April 12, 2012

1.0

A

CONN@

ACES_88231-08001

1 1

2 2

GND1 GND2

PJP2

1

2

3

EC_SMDA

3

4

EC_SMCA

4

5

TH

5

6

BI+

6

7

8

9 10

<40,41>

VMB

BATT_S1

12

PL2

SMB3025500YA_2P

1 2

PC8

PC8 1000P_0402_50V7K

1000P_0402_50V7K

BATT+

12

PC9

0.01U_0402_25V7K

<40,41>

12

PR19

PR19 1K_0402_5%

1K_0402_5%

BI <33>

100_0402_1%

6.49K_0402_1%

12

PR21

PR21 1K_0402_1%

1K_0402_1%

PR17

PR20

B

12

PR15

PR15 100_0402_1%

100_0402_1%

12

EC_SMB_DA1 <32,38>

EC_SMB_CK1 <32,38>

C

D

G718 ENE9012

12

+3VALW

BATT_TEMP <32>

65W

90W

VCIN1

3.92K

8.87K

1.456V

1.148V

2.21K

6.98K

1.2V

0.925V

For 65W adapter==>action 70W , Recovery 54W

For 90W adapter==>action 97W , Recovery 75W

For 40W thunder bolt adapter==>action 50W , Recovery 38W

65W@ PR33

65W@

1.65K_0402_1%

12

90W@ PR33

90W@

6.98K_0402_1%

12

PR38

PR38 10K_0402_1%

10K_0402_1%

PR33

ADP_I <32,38>

PR33

VCIN1_PROCHOT <32>

VCIN1=0.9V recover = 0.683V

PQ6

TP0610K-T1-E3_SOT23- 3

B+

3 3

EC_SPOK<32>

VL

12

PR28

@PR2 8

@

100K_0402_1%

PR34

@PR3 4

@

1K_0402_5%

1U_0402_6.3V6K

A

1 2

PC15

@PC1 5

@

12

SPOK<39>

4 4

13

2

G

100K_0402_1%

PR27

22K_0402_1%

D

PQ7

PQ7 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

PR26

12

PC12

@

0.22U_0603_25V7K

12

0.22U_0603_25V7K

13

2

B

+VSBP

12

PC13

0.1U_0603_25V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2012/4/6 2013/4/6

PH1 under CPU botten side : CPU thermal protection at 92 degree C for reference

+EC_VCC <32>

Compal Secret Data

Deciphered Date

C

12

PC14

.1U_0402_16V7K

12.4K_0402_1%

12

PC17

.1U_0402_16V7K

EC side

100K_0201_1%_TSMAB104F4251R Z

12

PR29

12

PH1

ECAGNDECAGND

ECAGND <32>

Compal Electronics, Inc.

Title

Size D ocument Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

BATTERY CONN / OTP

VCIN0_PH <32>

Chief River VC

D

1.0

37 51Thursday, April 12, 2012

1.0

A

B

C

D

for reverse input protection

1

D

2

G

1 2 3

PR64

100K_04 02_1%

2

G

A

1 2

PR40

3M_0402 _5%

P1 B+VIN

12

PR42

@

0_0402_5%

2

13

D

PQ15

PQ15 SSM3K70 02FU_SC70-3

SSM3K70 02FU_SC70-3

S

1 2

PR39

1 1

PC25

2200P_0402_50V7K

2 2

3 3

battery 4.35/cell *4 =17.4, battery voltage --> back to back --> Vin

FSTCHG<32>

4 4

SUSP#<32,3 5,40,41>

PR39

1M_0402 _5%

PQ9

SIS412DN-T 1-GE3_POWE RPAK8-5

12

PQ9

5

4

1 2

PQ8

SI1304BDL-T1-E3_SC70-3

S

3

PQ10

SIS412DN-T 1-GE3_POWE RPAK8-5

12

PC16

12

PR45

ACDET

12

PR59

PR59 2M_0402 _1%

2M_0402 _1%

12

PR62

PR62 2M_0402 _1%

2M_0402 _1%

13

PQ10

1 2 3

4

0.1U_0402_25V6

12

PR46

4.12K_0603_1%

PQ14

PQ14 PDTC115 EU_SOT323-3

PDTC115 EU_SOT323-3

P2

5

BQ24725_CMSRC

BQ24725_ACDRV

+3VLP

1 2

100K_04 02_1%

ACIN<15,32,35,39>

VIN

1 2

0.02_120 6_1%

1

2

PC26

0.1U_040 2_25V6

1 2

12

PC30

0.1U_0603_25V7K

PR56

PR60

280K_06 03_0.1%

154K_06 03_0.1%

12

PR41

PJ21

PC29

PR66

DH_CHG

18

HIDRV

PJ21

112

JUMP_43 X79

12

PR48

2.2_0603_5%

BQ24725_BST

17

BTST

12

2012/4/6

2

12

DH_CHG

PD7

PD7 RB751V-40_SOD323-2

RB751V-40_SOD323-2

PC33

1 2

1U_0603 _25V6K

16

REGN

15

LODRV

14

GND

13

SRP

12

SRN

11

BATDRV

10

12

PR61

100K_0402_1%

EC_SMB_CK1 <32,37>

EC_SMB_DA1 <32,37>

ADP_I <32,37>

PC45

@P C45

@

0.1U_040 2_16V7K

12

PC22

PC21

10U_0805_25V6K

PR50

0_0402_ 5%

1 2

DH_CHG-1

DL_CHG

PR54

10_0603 _5%

1 2

SRP

1 2

SRN

PR55

6.8_0603 _5%

BQ24725_BATDRV

1 2

PR58

316K_04 02_1%

PC42

0.01U_0402_25V7K

Compal Secret Data

Deciphered Date

4

3

VIN

2

3

PD6

PD6 BAS40CW_S OT323-3

12

BQ24725_ACN

PC31

1 2

1U_0603 _25V6K

BQ24725_ACP

PU4

21

1

2

3

4

5

ACOK

Pre_CHG

12

PD9

PD9 RB751V-40_SOD323-2

RB751V-40_SOD323-2

12

PR63

ACDET

12

PR65

PC43

PR65

66.5K_06 03_0.1%

0.1U_0402_16V7K

100P_04 02_50V8J

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

BAS40CW_S OT323-3

PC28

1

0.1U_0402_25V6

0.047U_0 402_25V7K

1 2

12

PR47

10_1206_1%

BQ24725_LX

19

20

PAD

VCC

ACN

ACP

CMSRC

ACDRV

ACOK

PC44

PHASE

BQ24725RGRR_VQFN2 0_3P5X3P5

ACDET6IOUT7SDA8SCL9ILIM

0_0402_ 5%

12

1 2

Close EC

Issued Date

PC23

0.1U_0402_25V6

CSOP1

CSON1

+3VALW

CHG_B+

12

PC24

2200P_0402_50V7K

BQ24725_BATDRV

5

PQ12

SIS412DN-T 1-GE3_POWE RPAK8-5

4

SIS412DN-T 1-GE3_POWE RPAK8-5

123

4.7UH_FDSD0630-H-4R7M-P3 _5.5A_20%

BQ24725_LX CHG

5

12

PQ13

123

12

PC41

0.1U_0603_25V7K

12

SIS412DN-T1-GE3_POWERPAK8-5

1 2

PR53

@

4.7_1206_5%

PC40

@

680P_0402_50V7K

SIS412DN-T 1-GE3_POWE RPAK8-5

5

1 2

PR44

4.12K_06 03_1%

PL4

1

2

CSOP1

12

PC37

0.01_120 6_1%

0.1U_0402_25V6

Vin Dectector

Min. Typ Max. L-->H 17.852V 18.063V 18.275V H-->L 17.476V 17.687V 17.898V

ILIM and external DPM

Min. Typ Max.

3.906A 4.006A 4.108A

Title

2013/4/6

C

Title

Size Document Number Rev

Custom

Date: Sheet of

PQ11

1 2 3

12

PC27

PR43

@

0.01U_0402_50V7K

12

PC34

10U_0805_25V6K

PR52

4

3

CSON1

12

PC38

0.1U_0402_25V6

Compal Electronics, Inc.

PWR DCIN / Pre-charge

Q3ZMC M/B LA-8481P Schematic

Thursday, April 12, 2012

D

0_0402_5%

BATT+

12

PC35

10U_0805_25V6K

38

PC36

PC39

0.01U_0402_50V7K

2200P_0402_50V7K

1.0

51

5

Note: Use TPS51125 IC can remove RTC refernece LDO Use TPS51427 IC must keep RTC refernece LDO

4

3

2

1

2VREF_8205

D D

PR67

13.7K_0402_1%

1 2

PR69

RT8205_B+

PJ17

B+

C C

B B

ACIN

A A

2

PJ17

112

JUMP_43X79

VIN

930@ P R84

930@

1M_0402_1%

1 2

VL

13

VS

PQ22

930@ P Q22

930@

PDTC115EU_SOT323-3

2

MAINPWON<32>

PR84

G

PC49

0.1U_0603_25V7K

5

12

+3VALWP

EC_ON<32>

12

PC51

PC50

4.7U_0805_25V6-K

PC60

150U_B2_6.3VM_R35M

PC60

DMN66D0LDW -7_SOT363-6

VL

PR80

930@ P R81

930@

PD11

930@ P D11

930@

LL4148_LL34-2

VS

61

D

S

DMN66D0LDW -7_SOT363-6

930@

12

930@ P R83

930@

316K_0402_1%

1 2

PQ23A

1M_0402_1%

1 2

12

PC52

2200P_0402_50V7K

PL6

3.3UH_FDSD0630-H- 3R3M-P3_6.6A_20%

9012@ PR100

9012@

2.2K_0402_1%

1 2

0_0402_5%

1 2

PR81

PR83

5

G

PL6

1

+

2

PQ20A

PR100

PR80

12

PR85

930@ PR85

930@

10K_0402_1%

34

D

930@

DMN66D0LDW -7_SOT363-6

S

12

PR75

@

4.7_1206_5%

PC61

@

680P_0402_50V7K

ENTRIP1

61

D

S

PR79

100K_0402_1%

12

PR82

930@ PR82

930@

402K_0402_1%

PQ23B

5

PQ16

4

SIS412DN-T1-GE3_POW ERPAK8-5

123

12

5

PQ18

SI7716ADN-T1-GE3_POW ERPAK8-5

123

2

G

4

Typ 13.5m ohm max 16.5m ohm

5

G

13

PQ21

PQ21 PDTC115EU_SOT323-3

PDTC115EU_SOT323-3

4

B+

12

2

PC67

1U_0603_10V6K

Typ: 175mA

12

PC54

4.7U_0805_10V6K

0.1U_0603_25V7K

PD10

RLZ5.1B_LL34

1 2

ENTRIP2

34

D

PQ20B

DMN66D0LDW -7_SOT363-6

S

+3VLP

PR73

12

2.2_0603_5%

PC58

PR77

499K_0402_1%

1 2

PR78

+3.3VALWP Ipeak=7A ; Imax=4.9A Delta I=2.2036A=>1/2Delta I=1.1017A (F=375K Hz) Rds(on)=16.5m ohm(max) ; Rds(on)=13.5m ohm(typical) Ilimit_min=(147K*10uA)/(10*16.5m*1.2)=7.42A Ilimit_max=(147K*10uA)/(10*13.5m*1.2)=9.07A Iocp=Ilimit+1/2Delta I=8.52A~10.174A

PR69

20K_0402_1%

PR71

147K_0402_1%

PU5

25

P PAD

7

VOUT2

8

VREG3

9

BST_3V

BOOT2

10

UG_3V

UGATE2

11

LX_3V

PHASE2

12

LG_3V

LGATE2

12

PC64

150K_0402_1%

1U_0603_10V6K

2VREF_8205

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

12

PC46

1U_0603_10V6K

12

ENTRIP2

2

3

4

5

6

FB2

REF

TONSEL

ENTRIP2

RT8205LZQW (2)_WQFN24_4X4

VFB=2.0V

SKIPSEL

VIN16GND

EN

14

17

15

13

12

RT8205_B+

12

PC66

3

1

FB1

PGOOD

UGATE1

PHASE1

LGATE1

PC65

0.1U_0603_25V7K

2012/4/6

PR68

30K_0402_1%

PR70

20K_0402_1%

1 2

147K_0402_1%

1 2

ENTRIP1

VOUT1

BOOT1

SECFB18VREG5

4.7U_0805_10V6K

PR72

24

23

22

21

20

19

VL

Typ: 175mA

12

RT8205_B+

12

PC55

4.7U_0805_25V6-K

PR74

2.2_0603_5%

1 2

BST_5V

UG_5V

LX_5V

LG_5V

Compal Secret Data

Deciphered Date

12

PC56

4.7U_0805_25V6-K

SPOK <37>

PC59

0.1U_0603_25V7K

1 2

SI7716ADN-T1-GE3_POW ERPAK8-5

Typ 13.5m ohm max 16.5m ohm

12

PC57

PC53

0.1U_0603_25V7K

2200P_0402_50V7K

PQ19

RT8205 TONSEL=VREF (1) SMPS1=300KHZ (+ 5VALWP) (2) SMPS2=375KHZ(+3 VALWP)

TPS51125A TONSEL=VREF (1)SMPS1=245KHZ (+5VALWP) (2)SMPS2=305KHZ(+3VALWP)

3.3VALWP Delta I = 2.709A (Freq=305KHz) Iocp = 8.7746A ~ 10.42 5VALWP Delta I = 3.199A (Freq=245KHz) Iocp = 9.0195A ~ 10.673A

+5VALWP Ipeak=7A ; Imax=4.9A Delta I=2.6129A=>1/2Delta I=1.3064A (F=300K Hz) Rds(on)=16.5m ohm(max) ; Rds(on)=13.5m ohm(typical) Ilimit_min=(147K*10uA)/(10*16.5m*1.2)=7.42A Ilimit_max=(147K*10uA)/(10*13.5m*1.2)=9.074A Iocp=Ilimit+1/2Delta I=8.7264A ~ 10.38A

2013/4/6

2

5

PQ17

4

SIS412DN-T1-GE3_POW ERPAK8-5

123

PL7

4.7UH_FDSD0630-H- 4R7M-P3_5.5A_20%

1 2

12

5

4

PR76

@

4.7_1206_5%

12

PC63

123

@

680P_0402_50V7K

Compal Electronics, Inc.

Title

Size D ocument Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Thursday, April 12, 2012

+5VALWP

1

+

PC62

150U_B2_6.3VM_R35M

2

3VALW/5VALW

Chief River VC

1

39 51

1.0

A

B

C

D

Ipeak = 9.8A, Imax = 6.86A Delta I = 2.88A, F= 290KHz, Rton= 887K ohm Rtrip = 19.6K ohm OCP= 13.45~16.56A

1 1

+0.675VSP

12

PC72

10U_0805_25V6K

SUSP#<32,35,38,41>

SYSON<32,35>

+VTT_REFP

12

PR91

680K_0402_1%

1 2

PC325

.1U_0402_16V7K <BOM Structure>

2 2

SUSP<35,5>

3 3

PJ24

JUMP_43X39

靠靠

Output Cap PAD

PC73

10U_0805_25V6K

+1.35VP

PC76

0.033U_0402_16V7K

PR92

0_0402_5%

1 2

12

0.1U_0402_16V7K

13

D

2

PQ26

PQ26 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

G

S

PC79

@ PC79

@

5.76K_0402_1%

STATE S3 S5 1.35VP VTT_REFP 0.675VSP

S0

Hi Hi

S3

4 4

S4/S5

HiLo

Lo Lo

On

Off (Discharge)

On

Off (Discharge)

On

Off (Hi-Z)

Off (Discharge)

1

2

PU6

21

PAD

1

VTTGND

2

VTTSNS

3

GND

4

VTTREF

5

VDDQ

12

PR95

+1.35VP+1.35VS

1

PJ13

1

JUMP_43X39

2

PR86

UG_1.5V

BST_1.5V

18

19

VLDOIN

S3

7

S3_1.5V

17

BOOT

UGATE

S5

TON

8

9

S5_1.5V

PR94

4.64K_0402_1%

20

VTT

RT8207MZQW _WQFN20_3X3

FB

6

FB=0.75V

12

To GND = 1.5V To VDD = 1.35V

PR86

2.2_0603_5%

1 2

LX_1.5V

16

PHASE LGATE

PGND

CS

VDDP

VDD

PGOOD

10

PR93

887K_0402_1%

12

BST_1.5V-1

15

LG_1.5V

14

PR88

19.6K_0402_1%

13

12

11

+3VALW

12

PR90

@

12

1.5V_B+

12

PC77

1U_0603_10V6K

PGOOD_1.5V

10K_0402_5%

PC71

0.1U_0603_25V7K

1 2

12

+3VALW

SUSP#

SY8033B enable pin without internal pull down, and RT8061or other 2nd source has 500K pull down resistor!So please review your application if R1>249K will cause enable pin logic high level is not enough

PR89

5.1_0603_5%

PC78

1U_0603_10V6K

PJ14

112

JUMP_43X39

22U_0805_6.3VAM

PR257

100K_0402_1%

1 2

1M_0402_5%

4

PR98

12

2

5

SIS412DN-T1-GE3_POW ERPAK8-5

123

5

123

PQ25

SI7716ADN-T1-GE3_POW ERPAK8-5

Rds=13.5mΩ(Typ)

16.5mΩ(Max)

+5VALW

12

PC80

+1.8VSP_ON

12

PQ24

12

PR87

@PR8 7

@

4.7_1206_5%

12

PC75

@PC7 5

@

680P_0402_50V7K

need change OCP setting

PU7

4

10

PVIN

PG

9

PVIN

8

SVIN

5

EN

TP

7

11

PC84

0.1U_0402_16V7K

12

1.5V_B+

12

PC68

10U_0805_25V6K

PL9

1.5UH_MMD-06CZ- 1R5M-V1_9A_20%

NC

SY8033BDBC_DFN10_3X3

PL9

FB=0.6V

Note:Iload(max)=3.5A

1UH_PH041H-1R0MS_3. 8A_20%

2

LX

3

LX

6

FB

NC

1

PC87

@

47P_0402_50V8J

1UH_PH041H-1R0MS_3. 8A_20%

LX_1.8V

12

112

JUMP_43X79

PL10

1 2

20K_0402_1%

PR96

4.7_0805_5%

FB_1.8V

10K_0402_1%

PC85

680P_0402_50V7K

PJ18

PR97

PR99

2

B+

+1.35VP

1

+

PC74

PC74 330U_B2_2.5VM_R15M

330U_B2_2.5VM_R15M

2

12

PC81

68P_0402_50V8J

12

PC82

22U_0805_6.3VAM

+1.8VSP

Note: S3 - sleep ; S5 - power off

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

C

Title

Size D ocument Number Rev

Custom

Date: Sheet of

1.5VP/0.75VSP/1.8VSP

Chief River VC

D

40 51Thursday, April 12, 2012

1.0

5

+3VS

12

PR101

0_0402_5%

PR112

52.3K_0402_1%

12

470K_0402_1%

D D

C C

VCCPPWRGOOD<42>

PR113

330K_0402_1%

1 2

SUSP#

PC100

0.1U_0402_16V7K

VFB=0.7V

12

PR119

10K_0402_1%

4

PR261

10K_0402_1%

PR274

@PR274

@

0_0402_5%

TRIP_+1.05VS_VTTP

FB_+1.05VS_VTTP

RF_+1.05VS_VTTP

PR114

VFB= 0.704V Vo=VFB*(1+PR116/PR119)= 1.05V Freq= 266~314KHz , 290KHz(typ)

Cesr= 15m ohm Ipeak= 15.24A Imax= 10.668A Delta I= 3.306A ==>1/2 Delta I= 1.653A Vtrip=Rtrip*10uA= 0.523V Iocp= 18.74A~22.66A

PU9

1

PGOOD

2

TRIP

3

EN

4

VFB

5

TST

TPS51212DSCR_SON10_3X3

VBST

DRVH

V5IN

DRVL

10

BST_+1.05VS_VTTP

9

UG_+1.05VS_VTTP

8

7

6

11

SW_+1.05VS_VTTPEN_+1.05VS_VTTP

LG_+1.05VS_VTTP

12

SW

TP

1 2

+5VALW

PC101

PC101 1U_0603_10V6K

1U_0603_10V6K

PR111

2.2_0603_5%

3

PC99

0.1U_0603_25V7K

1 2

MDU1511RH_POWER DFN56-8-5

Rds=2.6mΩ(Typ)

3.2mΩ(Max)

PQ30

4

5

5

+1.05VS_VTTP_B+

PQ29

MDV1525URH_PDFN33-8-5

123

PC105

1000P_0402_50V7K

等等等等

IVB ES2

2

12

PC95

0.1U_0402_25V6

1UH_VMPI0703AR-1R0M-Z01_11A_20%

12

@PR115

@

4.7_1206_5%

12

@PC104

@

680P_0402_50V7K

12

PC96

2200P_0402_50V7K

PL14

1 2

PR115

PC104

PR116

4.87K_0402_1%

PR117

1.2K_0402_1%

改改改改改改改改

12

PC97

12

1.05V

10U_0805_25V6K

12

之之之之之之之之之之之之之之之之

PC103

.1U_0402_16V7K

等等等等

IVB ES2

PR118

100_0402_1%

1 2

PJ19

112

JUMP_43X79

1

+

2

改改改改改改改改

2

PC102

PC102 330U_B2_2.5VM_R15M

330U_B2_2.5VM_R15M

1.05V

之之之之之之之之改改改改之之之之

VCCIO_SENSE <8>

1

B+

+1.05VS_VCCPP

0.1U_0402_16V7K

+1.8VS

+5VALW

B B

7

PR106

100K_0402_5%

SUSP#<32,35,38,40>

A A

5

1 2

PR103

47K_0402_5%

12

PC89

0.1U_0402_16V7K

8

POK

EN

12

PC86

1U_0402_6.3V6K

6

5

VIN

4

VOUT

VCNTL

3

VOUT

2

FB

9

VIN

GND

1

PU8

APL5915KAI-TRL_SO8

4

2

PJ20

2

JUMP_43X39

@

1

12

PC91

4.7U_0805_6.3V6K

PR105

1.54K_0402_1%

12

PR104

1.74K_0402_1%

PC88

+1.5VS

Compal Secret Data

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

2

12

PC90

0.01U_0402_25V7K

PR104

12

22U_0805_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

+1.05VS_VTTP/+1.0VSP

Chief River VC

1

41 51Thursday, April 12, 2012

1.0

5

4

3

2

1

VID [0] VID[1] VCCSA Vout

+VCC_SAP TDC 4.2A Peak Current 6 A OCP current 7.2 A

D D

PU10 SY8037DCC_DFN12_3X3

12

PU10 SY8037DCC_DFN12_3X3

12

PVIN

11

PVIN

10

SVIN

9

FB

8

VOUT

7

VID1

VID0

GND

13

+VCCSA_VID1

LX

PG

EN

1

+VCCSA_PHASE+VCCSA_PWR_SRC

2

3

4

+VCCSA_PWRGD

5

6

+VCCSA_VID0

+VCCSA_EN

100K_0402_5%

1 2

PR122

1K_0402_5%

PR121

1K_0402_5%

PR120

1 2

PR124

0_0402_5%

PC107

@PC107

@

.1U_0402_16V7K

12

SA_PGOOD <32>

+3VS

VCCPPWRGOOD <41>

H_VCCSA_VID0 <9>

The 1k PD on the VCCSA VIDs are empty. These should be stuffed to ensure that VCCSA VID is 00 prior to VCCIO stability.

H_VCCSA_VID1 <9>

PJ23

+3VALW +VCCSAP

C C

112

JUMP_43X79

2

1

PC119

PC118

2200P_0402_50V7K

PC120

1 2

2

1 2

0.1U_0603_25V7K

0.1U_0603_25V7K 22U_0805_6.3V6M

22U_0805_6.3V6M

PC106

68P_0402_50V8J

PL15

0.47UH +-20% PCMC042T-R47MN 6A

1 2

12

PR126

@PR126

@

4.7_0805_5%

12

PC109

@ PC109

@

680P_0402_50V7K

12

PC112

.1U_0402_16V7K

PR128

100_0402_5%

PR130

0_0402_5%

0 0 0.9V 0 1 0.8V 1 0 0.725V 1 1 0.675V

output voltage adjustable netw ork

12

PC114

PC115

1 2

22U_0805_6.3V6M

PC115

2200P_0402_50V7K

VCCSA_SENSE <9>

PC113

1 2

22U_0805_6.3V6M

12

+3VALW

PC92

22U_0805_6.3VAM

PJ16

PR107

1M_0402_1%

JUMP_43X39

1.05VS_LC_PG<27>

+1.05TPP_ONEN_LC_PWR

12

PJ16

112

+3VALW

PR258

0_0402_5%

B B

A A

EN_LC_PWR<24>

5

1 2

12

PR123

100K_0402_5%

12

2

4

IN

5

PG

FB6EN

3

LX_1.05TPP

LX

2

GND

1

FB=0.6V

PU11

SY8032ABC_SOT23-6

12

PC117

@

SY8032ABC_SOT23-6

PC111

0.1U_0402_16V7K

4

PC111

680P_0402_50V7K

PL8

1UH_PH041H-1R0MS_3.8A_20%

1 2

12

PR110

4.7_0805_5%

12

FB_1.05TPP

PR109

7.5K_0402_1%

PR108

10K_0402_1%

12

PC94

12

3

PC108

68P_0402_50V8J

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

+1.05VS_LCP

12

PC93

22U_0805_6.3VAM

Compal Secret Data

2012/4/6

Deciphered Date

2

2013/4/6

Compal Electronics, Inc.

Title

VCC_SAP/+1.5VSDGPUP/+1.05VS_DGPU

Size Document Number Rev

Date: Sheet of

Chief River VC

Thursday, April 12, 2012

42 51

1

42 51

1.0C

5

local sense rev ese HW

PH3

10K_0402_1%_ERTJ0EG103FA

D D

PR152

27.4K_0402_1%

PC156

@ PC156

@

27.4K_0402_1%

PH4

1 2

PR161 0_0402_5%PR161 0_0402_5%

1 2

PR165 0_0402_5%PR165 0_0402_5%

12

PR158

3.83K_0402_1%

VR_SVID_ALRT#<8>

VR_SVID_CLK<8>

VR_SVID_DAT<8>

1 2

VR_HOT#<32>

VR_ON<32>

47P_0402_50V8J

C C

+1.05VS_VTT

PC162

470P_0402_50V7K

PC167

470P_0402_50V7K

B B

470P_0402_50V7K

1.91K_0402_1%

VSUMG-

12

PC137

PR141

.1U_0402_16V7K

2.61K_0402_1%

VSUMG+

12

+5VS

12

1 2

470K_0402_5%_ TSM0B474J4702RE

PR160 0_0402_5%PR160 0_0402_5%

1 2

PR164 0_0402_5%PR164 0_0402_5%

PR169

PR168

@

0_0402_5%

1 2

12

PC126

@PC126

@

0.1U_0402_16V7K

PR176

2K_0402_1%

12

2K_0402_1%

PR183

499_0402_1%

PR189

12

VCCSENSE<8>

VSSSENSE<8>

12

137K_0402_1%

42.2K_0402_1%

68P_0402_50V8J

150P_0402_50V8J

PR190

1 2

PR142

11K_0402_1%

1 2

PR155

0_0402_5%

1 2

PR170

1 2

75_0402_5%

130_0402_1%

PR177

PC170

PC174

12

PC140

1 2

PR171

12

54.9_0402_1%

1 2

12

PC141

1 2

@ PC141

@

0.1U_0603_25V7K

1000P_0402_50V7K

ISEN2G

NTCG SCLK

ALERT#

SDA

12

PH5

PR172

27.4K_0402_1%

+5VS

12

PR173

470K_0402_5%_ TSM0B474J4702 RE

3.83K_0402_1%

PC180

@PC180

@

330P_0402_50V7K

PC186

0.01UF_0402_25V7K

4

VCC_AXG_SENSE<9> VSS_AXG_SENSE<9>

PR135

523_0402_1%

PU13

1 2 3 4 5 6 7 8 9

10

41

PR196

PR196 0_0402_5%

0_0402_5%

1 2

12

ISUMPG ISEN1G ISEN2G NTCG SCLK ALERT# SDA VR_HOT# VR_ON NTC

TP

3

12

PC125

@ PC125

@

1000P_0402_50V7K

PC127

0.01UF_0402_25V7K

PC133

68P_0402_50V8J

150P_0402_50V8J

12

+3VS

12

PR147 1.91K_0402_1%PR147 1.91K_0402 _1%

37

39

38

36

35

34

40

11

33

FBG

RTNG

COMPG

PWM2G

ISUMNG

PGOODG

LGATE1G

ISEN212FB17ISUMP14ISEN3/FB2

RTN16ISEN1

18

15

13

12

PR136

137K_0402_1%

12

PR143

36.5K_0402_1%

32

31

BOOT1G

PHASE1G

COMP

30

UGATE1G

BOOT2

29

UGATE2

28

PHASE2

27

LGATE2

26

VCCP

25

VDD

24

PWM3

23

LGATE1

22

PHASE1

21

UGATE1

PGOOD19ISUMN

BOOT1

ISL95836HRTZ-T_TQFN40_5X5~D

20

PR174 1.91K_0402_1%PR174 1.91K_0402_1%

PR187

1 2

PC135

12

523_0402_1%

12

LGATE1G

PHASE1G

UGATE1G

BOOT1G

12

470P_0402_50V7K

2.61K_0402_1%

+3VS

PC169

@ PC169

@

PC134

12

PR137

0_0603_5%

LGATE1

PHASE1

UGATE1

BOOT1

VGATE <15>

1000P_0402_50V7K

PR134

499_0402_1%

12

+5VS

PR159

PC166

1 2

0.1U_0603_25V7K

1 2

12

PHASE1G

12

PR162

1_0603_5%

12

PC154

1U_0603_10V6K

VSUM+

12

PR180

12

2.61K_0402_1%

PH6

PR184 11K_ 0402_1%PR184 11K_0402_1%

10K_0402_1%_ERTJ0EG103FA

VSUM-

Close Phase 1 choke

12

PC175

.1U_0402_16V7K

BOOT1G

12

UGATE1G

PC155

1U_0603_10V6K

PQ38

MDV1525URH_PDFN33-8-5

PC189

0.22U_0603_16V7K

1 2 12

LGATE1G

PR206

2.2_0603_5%

PQ40

MDU1511RH_POWERDFN56-8-5

Rds(on)typ : 2. 4m ohm max: 3.3m ohm

MDV1525URH_PDFN33-8-5

PR192

PR192 0_0603_5%

0_0603_5%

PR194

2.2_0603_5%

1 2

12

UGATE1

PHASE1

BOOT1

LGATE1

4

1 2

PC187

0.22U_0603_16V7K

2

CPU_B+

123

4

PQ39

12

PC181

10U_0805_25V6K

5

123

5

123

PC182

@

PC190

680P_0402_50V7K

CPU_B+

5

123

5

4

PQ37

UGATE1-1

MDU1511RH_POWERDFN56-8-5

Rds(on)typ : 2. 4m ohm max: 3.3m ohm

1

12

PC184

PC183

10U_0805_25V6K

DCR: 1.19mΩ±5%

PL23

0.24UH_FDUE0630J-H-R24M-P3_22A_20%

1 2

12

PC177

10U_0805_25V6K

12

PR195

4.7_1206_5%

@

12

PC188

680P_0402_50V7K

12

PR203

1 2

3.65K_0603_1%

VSUMG+

For ULV 17W 1+1 CPU_CORE LL= -2.9mΩ, GFX_CORE LL= -3.9mΩ,

12

PC178

10U_0805_25V6K

1 2

VSUM+

3.65K_0603_1%

VSUM-

VSUMG-

1

12

PC157

2

PC179

10U_0805_25V6K

33U_D_25VM_R60M

0.24UH_FDUE0630J-H-R24M-P3_22A_20%

PR198

PR201

1_0402_5%

PR204

1_0402_5%

+

1 2

12

PR200

4.7_1206_5%

12

PC176

10U_0805_25V6K

@

+VGFX_CORE

12

PL16

FBMA-L11-322513-151LMA50T_1210

DCR: 1.19mΩ±5%

PL21

+CPU_CORE

12

B+

local sense rev ese HW

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

CPU_CORE

Chief River VC

1.0

43 51Thursday, April 12, 2012

1

1.0

5

4

3

2

1

PWR Rule CPU LL=2.9m ohm dedign 330uF/9m *4, 22uF *12, 2.2uF*16

+VGFX_CORE

GFX LL=3.9m ohm design 330uF/9m *2, 22uF*6, 10uF*6 , 1uF*11

1.05V 330uF*2 10uF*10, 1u*26

12

D D

PC230

12

PC231

PC232

1U_0201_4V6M

12

PC234

PC233

1U_0201_4V6M

12

PC264

PC258

PC235

1U_0201_4V6M

12

PC292

1U_0201_4V6M

12

PC293

PC294

1U_0201_4V6M

+CPU_CORE

PC319

1U_0201_4V6M

PC319

PC228

1U_0201_4V6M

PC228

PC225

1U_0201_4V6M

PC225

1U_0201_4V6M

12

PC226

1U_0201_4V6M

PC226

1U_0201_4V6M

12

1U_0201_4V6M

12

1U_0201_4V6M

PC227

12

PC229

1U_0201_4V6M

PC229

1U_0201_4V6M

12

PC275

1U_0201_4V6M

PC275

1U_0201_4V6M

12

1U_0201_4V6M

PC317

1U_0201_4V6M

PC317

1U_0201_4V6M

12

For BOT side

PC320

2.2U_0402_6.3V6M

PC320

PC240

1U_0201_4V6M

PC240

1U_0201_4V6M

PC239

2.2U_0402_6.3V6M

PC239

PC236

1U_0201_4V6M

PC236

1U_0201_4V6M

12

PC237

2.2U_0402_6.3V6M

PC237

2.2U_0402_6.3V6M

12

2.2U_0402_6.3V6M

PC238

1U_0201_4V6M

PC238

1U_0201_4V6M

12

PC316

1U_0201_4V6M

PC316

1U_0201_4V6M

12

2.2U_0402_6.3V6M

PC318

2.2U_0402_6.3V6M

PC318

2.2U_0402_6.3V6M

12

PC242

PC247

10U_0603_6.3V6M

1

C C

330U_B_2.5VM_R9M

+

PC255

330U_B_2.5VM_R9M

1

+

PC256

2

PC256

2

330U_D2_2V_Y

12

PC244

PC243

10U_0603_6.3V6M

12

Vaxg

Can connect to GND if motherboard only

‧‧‧‧

supports external graphics and if GFX VR is not stuffed in a common motherboard design,

VAXG can be left floating in a common

‧‧‧‧

motherboard design (Gfx VR keeps VAXG from floating) if the VR is stuffed

12

PC353

B B

12

PC326

12

PC352

1U_0201_4V6M

12

PC324

1U_0201_4V6M

12

PC351

PC334

PC333

1U_0201_4V6M

12

PC323

1U_0201_4V6M

PC333

1U_0201_4V6M

12

PC321

PC322

1U_0201_4V6M

12

PC332

1U_0201_4V6M

12

PC289

1U_0201_4V6M

12

PC331

1U_0201_4V6M

12

PC288

1U_0201_4V6M

12

PC246

PC245

10U_0603_6.3V6M

47U_0805_6.3V6M

12

PC259

47U_0805_6.3V6M

12

PC260

PC261

+CPU_CORE

PC254

47U_0805_6.3V6M

PC254

PC250

22U_0805_6.3V6M

PC250

22U_0805_6.3V6M

PC249

22U_0805_6.3V6M

PC249

22U_0805_6.3V6M

1

2

PC251

22U_0805_6.3V6M

PC251

22U_0805_6.3V6M

1

2

PC252

47U_0805_6.3V6M

PC252

47U_0805_6.3V6M

12

47U_0805_6.3V6M

PC253

47U_0805_6.3V6M

PC253

47U_0805_6.3V6M

12

For TOP side

PC267

22U_0805_6.3V6M

PC267

22U_0805_6.3V6M

PC266

22U_0805_6.3V6M

PC266

22U_0805_6.3V6M

PC265

22U_0805_6.3V6M

PC265

22U_0805_6.3V6M

1

2

+1.05VS_VTT

12

PC327

PC328

PC329

PC330

1U_0201_4V6M

12

PC287

1U_0201_4V6M

12

PC279

1U_0201_4V6M

12

PC284

PC285

PC286

1U_0201_4V6M

12

PC282

PC283

22U_0805_6.3V6M

12

PC356

PC354

1U_0201_4V6M

12

1U_0201_4V6M

12

PC281

1U_0201_4V6M

12

PC355

PC357

1U_0201_4V6M

12

PC280

22U_0805_6.3V6M

+CPU_CORE

1

+

PC271

PC271 330U_D2_2V_Y

330U_D2_2V_Y

2

1

2

1

+

PC272

@+PC272

@

330U_D2_2V_Y

2

1

2

PC273 need link SGA00006J00.

1

+

PC273

PC273 560U 2V M D2

560U 2V M D2

2

1

+

PC291

2

330U_B2_2.5VM_R15M

A A

330U_B2_2.5VM_R15M

INTEL Recommend 3*330uF(1 in other page),12*22uF, 5 no stuff from PDDG 1.0

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/4/6 2013/4/6

3

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

CPU_CORE_CAP

Chief River VC

44 51Thursday, April 12, 2012

1

1.0

5

PQ47

AON7403L_DFN8-5

12

10K_0402_5%

1 2

PR292

AON7403L_DFN8-5

1

3

PC358

0.01U_0402_16V7K

PR290

2

G

100K_0402_5%

4

1 2 13

D

PQ48

PQ48 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

+5VALW

PR293

1 2

PJ22

2

112

JUMP_43X39

PR288

100K_0402_5%

D D

PA_HV_EN<24>

C C

100K_0402_5%

1 2

10K_0402_5%

3V3/2V JACKET

12

PC366

PC366 1U_0402_16V6K

1U_0402_16V6K

5V_BST#

12

PR298

PR298 10_0402_5%

10_0402_5%

B B

MOTOR_PWR_ON<30,32>

1 2

10K_0402_5%

PR299

100K_0402_5%

PR302

4

52

12

PC359

PC360

0.01U_0402_16V7K

PR294

0_0402_5%

1 2

EN_12VSP

12

PC363

0.1U_0402_10V7K

Motor_BST

12

PC371 4.7U_0603_10V6KPC371 4.7U_0603_10V6K

Motor_VCC

Motor_EN

@

12

PC374

0.1U_0201_10V6K

PL27

4.7UH_MMD-04BZ-4R7M-S1L_2.4A_20%

1 2

1U_0402_6.3V6K

PU16

8

Vin

FREQ_12VSP SS_12VSP

FREQ9SS

3

EN

RT9297GQW_WDFN10 _3X3

PU17

PU17 MP2334DD-LF-Z_QFN12_2X3

MP2334DD-LF-Z_QFN12_2X3

GND1GND

2

SW

3

BST

4

VCC

5

EN

>1.6V ENABLE

6

PG

LX_12VSP

7

LX6LX

2

FB_12VSP

FB

10

1

COMP_12VSP

COMP

GND5GND

PAD

4

11

GND

12

13

SW

10

SW

9

IN

8

FREQ

7

FB

1 2

12

Motor_SW

Motor_IN

Motor_FREQ

Motor_FB

PD15

12

SX34 SMA

12

PR295

PR295 10K_0402_1%

10K_0402_1%

PC364

PC364 4700P_0402_25V7K

4700P_0402_25V7K

PR296

PR296 300K_0402_1%

300K_0402_1%

1 2

PR300 432K_0402_1%PR300 432K_0402_1%

12

PC373

PC373 1000P_0402_25V8J

1000P_0402_25V8J

3

PR289

86.6K_0402_1%

1 2

PR291

10K_0402_1%

1 2

FB =1.24V

PC365

0.01U_0402_16V7K

Rdc=40ohm(max)

PL28

<BOM Structure>PL28

2.2UH_1231AS-H-2R2M-P3_1.9A_20%

1 2

PC367

PC367 470P_0402_50V7K

470P_0402_50V7K

Motor_Compensate

12

PC368

0.01U_0402_25V7K

JUMP_43X39

12

112

12

PC372

PC372 10U_0805_25V6K

10U_0805_25V6K

+HV_12VP+5VALW

12

PC361

PC362

10U_0805_25V6K

L/RDC=C*R

2.2uL/40mohm=0.00022uF*250Kohm

12

PJ26

2

12K_0402_1%

B+

8.45K_0402_1%

PR297

Motor_FB

PR301

12

2

1

PC369

PC369 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

+MT_VCC

FB=0.815V

Motor_FB

12

PR303

7.68K_0402_1%

61

D

PQ49A

DMN66D0LDW-7_SOT363-6

A A

D

S

2

G

100K_0402_5%

1 2

12

0.1U_0402_25V6

PR307

PC375

@PR309

@

10K_0402_5%

PR309

+3VALW

1 2

12

PR305

<BOM Structure>PR305

10K_0402_5%

MOTOR_VID0 <32>

DMN66D0LDW-7_SOT363-6

5.76K_0402_1%

PQ49B

PR304

Motor_FB

12

+3VALW

PR306

10K_0402_5%

PR310

@PR310

@

10K_0402_5%

1 2

12

MOTOR_VID1 <32>

PR308

34

D

5

G

S

100K_0402_5%

1 2

12

0.1U_0402_25V6

PR308

PC376

10K_0402_5%

VID0 VID1

0

1

0

0 1

+MT_VCC

2

3.3

reserve

51 1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

12V & MOTOR Power

45 51Thursday, April 12, 2012

1

1.0

5

4

3

2

1

D D

VR_ON

VGA_ON

(PU1000) ISL6266ACRZ-T

Page 55TQFN48

(PU998) APW7138NITRL

ADAPTER

SYSON

B+

BATTERY

C C

VS_ON

(SUSP#)

VCCPWRGOOD

CHARGER

(PU5) RT8209BGQW

WQFN14

(PU6) RT8209BGQW

WQFN14 Page 53

(PU3) RT8205EGQW

WQFN24 Page 49

Page 54SSOP16

Page 51

+CPU_CORE

+VGA_CORE

+1.5V

+1.05V_VCCP

+VCCSA

SUSP

PJP25

U38

(U13) SI4800BDY-T1-GE3

Page 44

(PU8) APL5331KAC-TRL

SO8 Page 53

+1.05VS_PCH

+1.05VSDGPU

L76

+1.5VS_DMC

+1.5VS

+0.75VS

+CLK_1.05VS

VGA_ON#

(U40) AO4430L

Page 44

SO8

+1.5VSDGPU

(PU3) RT8205EGQW

WQFN24 Page 49

+5VALW

SUSP

(U49) SI4800BDY

B B

SO8 Page 44

SYSON#

(U46)

TPS2062ADR

SUSP

(PU6)

SY8033BDBC

DFN10 Page 51

PCH_PWR_EN#

(U14) SI4800BDY SI4800BDY

SO8 Page 44

R599

(RE1)

+3VALW

SUSP

(U68)

SO8 Page 44

SUSP

(UB1) RT9701-PB

SOT23-5 Page 45

+5VS

+CRT_VCC

+HDMI_5V_OUT

+USB_VCCB

+1.8VS

+3VALW_PCH

+3V_LAN

(U39) BCM57780

+1.2V_LAN

+3VALW_EC

ENVDD

(Q51) AO3413L

SO23-3 Page 37

+BT_VCC

+3VS

+3V

+3VS_CK505

+DVDD_AUDIO

ENVDD

(Q30) AO3413L

+LCDVDD

VGA_ON

(Q34) AO3413L

SO23-3 Page 24SO23-3 Page 30

+3VSDGPU

+5VS_HDD1

+3V_WLAN

+5VS_ODD

+3V_DMC

A A

+5VAMP +VDDA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Power Rail

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Q3ZMC M/B LA-8481P Schematic

1

46 51Thursday, April 12, 2012

1.0

5

4

3

2

1

D D

AC MODE

BATT MODE

A1

VIN

BATT

B1

V

PU4

A3

B4

+3VALW

B5

V

A5

B7 2

V

A2

PU6

V

B+

V

B2

B+

PCH_PWR_EN#

2

V

PQ4

EC

VV

A5

A4

ON/OFF

B7

B6

V

PBTN_OUT#

PM_SLP_S3# PM_SLP_S4# PM_SLP_S5# PM_SLP_A#

V

PM_SLP_SUS#

SYSON

SUSP#,SUSP

B3

51ON#

C C

EC_ON

2

4

PCH_RSMRST#

5

7 SYSON#

8

U14,+3VALW_PCH

V

QH4,+5VALW_PCH

+3VALW_PCH

3

+5VALW_PCH

V

V V

PCH

SYS_PWROK

PM_DRAM_PWRGD

H_CPUPWRGD

PLT_RST#

13

V

14

CPU

V

15

V

6

+1.35V

V

PU6

U22

V

+5VS

U21

V

11

VGATE

+3VS

B B

V

U12 +1.35VS

PU6

VV

VCCPPWRGOOD

V

PU9 +1.05VS_VCCP

VR_ON

A A

5

4

9

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

Issued Date

PU13 +CPU_CORE

V

3

+0.675V

PU10 +VCCSA

Compal Secret Data

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Power sequence

Q3ZMC M/B LA-8481P Schematic

1

47 51Thursday, April 12, 2012

1.0

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 2

for PWR

Reason for change Rev. PG# Modify List Date PhaseFixed IssueItem

1

D D

Add ADP_ID circuit

2

Add Jack_TEMP and PH1 circuit

Adjust 1.35V ocp setting and

3

add boost resistor

Add 1.05V boost resistor and adjust output voltage

4

Change choke to 1uH

Acer will add pull down resistor in adapter to detect ADP_ID.

Acer request add a thermistor on jack of DC in cable to protect jack.

Adjust 1.35V ocp setting Add boost resistor

Add 1.05V boost resistor and adjust output voltage Change choke to 1uH for efficiency of heavy load

0.1 36

0.1 37

0.1 40

0.1 41

Add PU1 SA003310280 (S IC LMV331IDCKRG4 SC70 5P COMPARATORS) Add PQ27 SB000009Q80(S TR 2N7002KW 1N SOT323-3) Add PR13 PR16 SD034100280(S RES 1/16W 10K +-1% 0402) Add PR14 SD034100380(S RES 1/16W 100K +-1% 0402)

Add PU3 SA00003K300 (S IC G718TM1U SOT23 8P OTP) Add PR30 SD000009R00(S RES 1/16W 46.4K +-1% 0402) Add PR35 SD034953180(S RES 1/16W 9.53K +-1% 0402) Add PR37 SD034232280(S RES 1/16W 23.2K +-1% 0402) Del PR127 SD028000080(S RES 1/16W 0 +-5% 0402)

Change PR88 to SD000003580(S RES 1/16W 19.6K +-1% 0402) Change PR86 to SD013220B80(S RES 1/10W 2.2 +-5% 0603)

Change PR111 to SD013220B80(S RES 1/10W 2.2 +-5% 0603) Change PR116 to SD034487100(S RES 1/16W 4.87K +-1% 0402 (LF)) Change PL14 to SH00000KS00(S COIL 1UH +-20% VMPI0703AR-1R0M-Z01 11A)

2011/12/05

EVT2

Adjust GFX frequence Adjust GFX frequence to 400kHz for reduce ripple 0.1 43

5

Adjust CPU output cap Adjust CPU output cap for transient 0.1 44

6

C C

7

Adjust 0.675V enable timing 0.1 40Adjust 0.675V enable timing

8

Adjust 1.05VS_LCP sequence

Change 1.05VS_LCP from APL5930 to SY8032 for thoundbolt sequence.

0.2 42

9

10

11

B B

12

13

14

15

add boost resistor add Charger boost resistor

add boost resistor

add 3V5V boost resistor 0.2 39

add CPU and GFX boost resistor

Change main source Change main source for reduce component kind 0.2 39

Adjust Jack_TEMP resistor Adjust Jack_TEMP resistor, because PCCP change

thermistor to 0603 size(TSM1A104F4361RZ)

Add ADP_ID circuit Add ADP_ID circuit(65W) 0.2 36

0.2 38

0.2 37

Change PR143 to SD034365280(S RES 1/16W 36.5K +-1% 0402) 2011/12/05

Change PC273 to SGA00006J00(S POLY C 560U 2V M D2 LESR4.5M SX H1.9) unpop PC272 SGA20331E10(S POLY C 330U 2V Y D2 LESR9M EEFSX H1.9)

Change PC325 to SE076104K80(S CER CAP .1U 16V K X7R 0402) 2011/12/05

Change PU11 to SA000055100(S IC SY8032ABC SOT23 6P PWM) Change PR107 to SD034100480(S RES 1/16W 1M +-1% 0402) Add PL8 to SH00000MN00(S COIL 1UH +-20% PH041H-1R0MS 3.8A) Add PR110 to SD002470B80(S RES 1/8W 4.7 +-5% 0805) Change PC111 to SE074681K80(S CER CAP 680P 50V K X7R 0402) Change PC92 to SE000008L80(S CER CAP 22U 6.3V M X6S 0805 H1.25) Add PR123 to SD028100380(S RES 1/16W 100K +-5% 0402) Change PR108 to SD034100280(S RES 1/16W 10K +-1% 0402) Change PR109 to SD034750180(S RES 1/16W 7.5K +-1% 0402) Change PC94 to SE071680J80(S CER CAP 68P 50V J NPO 0402)

Change PR48 to SD013220B80(S RES 1/10W 2.2 +-5% 0603) 2012/01/05

Change PR73 and PR74 to SD013220B80(S RES 1/10W 2.2 +-5% 0603) 2012/01/05

Change PR194 and PR206 to SD013220B80(S RES 1/10W 2.2 +-5% 0603)432012/01/05

Change PL7 to SH00000MB00(S COIL 4.7UH +-20% FDSD0630-H-4R7M=P3 5.5A (7*7*3))

change PR30 to SD034442280(S RES 1/16W 44.2K +-1% 0402) change PR37 to SD034215280(S RES 1/16W 21.5K +-1% 0402)

Add PR23 to SD028000080(S RES 1/16W 0 +-5% 0402) change PR16 to SD034270280(S RES 1/16W 27K +-1% 0402) Add PC142 to SE074102K80(S CER CAP 1000P 50V K X7R 0402)

2011/12/05

2012/01/05

EVT2

DVT

DVT0.2

DVT

16

A A

Change main source Change main source for

不不不不不

with HW 0.2

change PQ7,PQ26,PQ15,PQ27,PQ48 from SB000009Q80 to SB000009610(S TR SSM3K7002FU 1N SC70-3)

2012/01/31

DVT

17

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2012/4/6 2013/4/6

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size D ocument Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PIR (PWR)

Q3ZMC M/B LA-8481P Schematic

48 51Thursday, April 12, 2012

1

1.0

5

4

3

2

1

Version change list (P.I.R. List) Page 2 of 2

for PWR

Reason for change Rev. PG# Modify List Date PhaseFixed IssueItem

18

D D

Del ADP_ID circuit

Acer will change adapter type to so del ADP_ID circuit.

音音音

from PoGo,

0.3 36

19

20

Del jack_temp circuit 0.3 37

SPOK change to EC_SPOK For reduce power consumption of DS3, so close +VSB

21

change VCCSA IC version SY8037C IC version change to SY8037D for accord with

22

Acer will change adapter type to so del jack_temp protect circuit.

power in DS3, DS4, DS5.

intel VCCSA spec.

音音音

from PoGo,

0.3 37

0.3 42

Del PU1 SA003310280 (S IC LMV331IDCKRG4 SC70 5P COMPARATORS) Del PQ27 SB000009Q80(S TR 2N7002KW 1N SOT323-3) Del PR13 SD034100280(S RES 1/16W 10K +-1% 0402) Del PR14 SD034100380(S RES 1/16W 100K +-1% 0402) Del PR23 to SD028000080(S RES 1/16W 0 +-5% 0402) Del PR16 to SD034270280(S RES 1/16W 27K +-1% 0402) Del PC142 to SE074102K80(S CER CAP 1000P 50V K X7R 0402)

Del PU3 SA00003K300 (S IC G718TM1U SOT23 8P OTP) Del PR30 to SD034442280(S RES 1/16W 44.2K +-1% 0402) Del PR35 SD034953180(S RES 1/16W 9.53K +-1% 0402) Del PR37 to SD034215280(S RES 1/16W 21.5K +-1% 0402) Add PC17 SE076104K80(S CER CAP .1U 16V K X7R 0402) Change PR29 to SD00000AJ80(S RES 1/16W 12.4K +-1% 0402)

Del PR28 SD034100380(S RES 1/16W 100K +-1% 0402) Del PR34 SD028100180(S RES 1/16W 1K +-5% 0402) Del PC15 SE000000K80(S CER CAP 1U 6.3V K X5R 0402)

Change PU10 to SA00005O000(S IC SY8037DDCC DFN 12P PWM)

2012/03/13

PVT

Add snubber Add snubber of GFX by hw request. 0.3 43

23

C C

24

Add MOTOR POWER

HW change motor power solution to PWM. 0.3 45

25

26

27

28

B B

Adjust HW throttling point

Because thunder bolt adapter is 40W, OCP 130% adjust HW throttling to 125% 50W recover point 38W

0.3 37

Add PR200 SD001470B80(S RES 1/4W 4.7 +-5% 1206) Add PC190 SE074681K80(S CER CAP 680P 50V K X7R 0402)

Add PU17 SA00005NY00(S IC MP2334DD-LF-Z QFN 12P PWM) Add PL28 SH00000N000(S COIL 2.2UH +-20% 1231AS-H-2R2M=P3 1.9A) Add PC366 SE00000OU00(S CER CAP 1U 16V K X5R 0402) Add PC367 SE074471K80(S CER CAP 470P 50V K X7R 0402) Add PC368 SE075103K80(S CER CAP .01U 25V K X7R 0402) Add PC369, PC371 SE00000MA00(S CER CAP 4.7U 10V K X5R 0603) Add PC372 SE00000QK00(S CER CAP 10U 25V K X5R 0805 H1.25) Add PC373 SE068102J80(S CER CAP 1000P 25V J NPO 0402) Add PC375, PC376 SE00000G880(S CER CAP 0.1U 25V K X5R 0402) Add PR296 SD034300380(S RES 1/16W 300K +-1% 0402) Add PR297 SD034120280(S RES 1/16W 12K +-1% 0402) Add PR298 SD028100A00(S RES 1/16W 10 +-5% 0402) Add PR300 SD034432380(S RES 1/16W 432K +-1% 0402) Add PR301 SD000000680(S RES 1/16W 8.45K +-1% 0402) Add PR302, PR307, PR308 SD028100380(S RES 1/16W 100K +-5% 0402) Add PR303 SD000002300(S RES 1/16W 7.68K +-1% 0402) Add PR304 SD034576180(S RES 1/16W 5.76K +-1% 0402) Add PR299, PR305, PR306 SD028100280(S RES 1/16W 10K +-5% 0402) Add PQ49 SB00000DH00(S TR DMN66D0LDW-7 2N SOT363-6)

Change PR33 to SD034165180(S RES 1/16W 1.65K +-1% 0402) 2012/03/13

2012/03/13

PVT

29

30

31

32

33

A A

34

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2012/4/6 2013/4/6

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size D ocument Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PIR (PWR)

Q3ZMC M/B LA-8481P Schematic

49 51Thursday, April 12, 2012

1

1.0

5

Request

Item

Item Issue Description

ItemItem

Page# Title

Page#Page#

Title

TitleTitle

Date

DateDate

RequestRequest Owner

Owner

OwnerOwner

4

Version Change List ( P. I. R. List )

Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )

Issue DescriptionDate

Issue DescriptionIssue Description

3

Page 1

Page 1Page 1

2

Solution Description

Solution Description Rev.

Solution DescriptionSolution Description

1

Rev.Page#

Rev.Rev.

0919(In Layout)

D D

1.Update R,C 0201,0402,0603,0805,1206 PCB footprint to small size

2.Swap DDR Data BUS

0920

1.Change U74,U21,U22 mos to 3*3 thermal pad package:SB00000GW00

0921

1.TB chip:U66 footprint add "-NH" for Non HDI

2.1.8p_0402:C402,C404 change to 75ohm_0402:R263,R264

0922

1.Change C1457,C1505 form 1.8P 0402 to 0201:SE00000HB80

2.Del DDR CHA,B no use CLK1,CLK1# circuit

3.Change C606,C607 from D2 330uF to B2 330uF 2.5V ESR 15mohm:SGA00004400

4.Swap total KB connector:JKB1 pin define

0923

1.Add DS3 function:SUSWARN#,SUSACK#,EC_DRAMRST_GATE

2.Add Motor function:Motor_IN1,Motor_IN2,Motor_IN3,Motor_IN4, Door_Det_L,Button: KSI0 & KSO10

3.Remove PCH NCTF test point

4.HDMI Fuse:F1 change to P5WS5 use footprint:F_1812

C C

5.Remove HDMI common mode choke:L36,L38,L39,L40

6.Change 0.1uF_0402_16V7K to 0.1uF_0201_10V6K:SE00000SV00 =>C521,C520,C526,C449,C523,C537,C541,C494,C495,C490,C497,C771,C522,C471,C473

7.Change 0.01uF_0402_16V7K to 0.01uF_0201_10V7K:SE172103K80 =>C425,C462

8.Change C751,C752 to B2 220uF 2.5V ESR 15mohm:SGA00004500

0924

1.Make MB to Audio/B connector pin define

2.Change RP 8.2K:R256,R262,R276,R386 to 8.2K_0402

3.Change RP 10K:R386 to 10K_0402

4.Update TB schematic p.24,25,27

5.Change Q64,Q68 from AO3419L:SB000006R10 to AP2301GN-HF:SB000007H10

6.Integration of all 2N7002 SOT23 parts to SSM3K7002F_SC59-3:SB000009080 =>Q74,Q20,Q1,Q2,Q32,Q16,Q17,Q14,Q37,Q7,Q21,Q23,Q24,Q5,Q34,Q29,Q60,Q66,Q67,Q72 Not yet=>Q6,Q78,Q79

0925

1.Delete LVDS function,Combine eDP,Card Reader function to JLVDS1 Remove:R259,R260,R285,R286,R156,R157,TXCLK+-,TX0+1,TX1+-,TX2+-,DDC CLK,DATA Remove:C462,C425,C412,L20,only place PU:R271,R272,PD:R270,R280

2.Change all SSM3K7002F_SC59-3:SB000009080 to SSM37K002FU_SC70-3:SB000009610

B B

=>Q74,Q20,Q1,Q2,Q32,Q16,Q17,Q14,Q37,Q7,Q21,Q23,Q24,Q5,Q34,Q29,Q60,Q66,Q67,Q72 Not yet=>Q6,Q78,Q79

3.Change 10U_0805_6.3V6M:SE093106M80 to 10U_0603_6.3V6M:SE000005T80 =>C754,C543,C418,C465

4.Remove 0_0603_5%:R416,R421,R426,R327

0926

1.Change HDMI level shift Q16,Q17 to DMN66D0LDW-7_SOT363-6:SB00000DH00

2.Modify TB schematic 0402 cap to 0201

0927

1.Remove J7

2.Change C599 330U D2 2V ESR 9mohm to 330U B2 2.5V ESR 15mohm:SGA00004400

3.Change EC +3VALW_EC

0.1U_0402_16V4Z to 0.1U_0201_10V6K:SE00000SV00 =>C1198,C1199,C1200,C1201,C1204 1000P_0402_50V7K to 1000P_0201_16V7K:SE000007U80 =>C1202,C1203

4.Remove R329

5.Change C751,C752 to 22U_0805_6.3V6M:SE000000I10

6.Remove J4(one of +1.05VS_VTT to +1.05VS_PCH jumper)

A A

0928

1.Change RTC cap from 1U 0603 to 1U 0402:C502,C516

2.Remove FAN some parts:R753,C788,D51,D52

3.Change USB connector foot print to TAIWI_USB005-107CRL-TW_10P-T

4.Change C196,C387,C735,C102 to 0.1uF_0201_10V6K:SE00000SV00

5.Remove L2

0929

1.Remove C510,C511

2.Remove Camera Choke:L7,R13,R14

3.Q1,Q2 change to DMN66D0LDW-7_SOT363-6:SB00000DH00

4.R273,R394 change from 0_0603 to 0_0402

5.Remove Step Motor SW1

6.Change LED/B connector from 8 pin to 4 pin

7.Change Jumper from 43*118 to 43*79 =>J2,J8,J10,J11

0930

1.Remove +VCCSA cap:C1182,C1183

2.Remove +USB3_VCCA cap:C390

3.Change C427,C428 to 0.1U_0201_10V6K

4.Add ESD diode:D6 for TP SMBUS

5.Change L65 to 220ohm 3A 0805

6.Swap DDR ChB Data,DQS# 6,7

7.Change U12 mos to 3*3 thermal pad package:SB00000GW00

8.Remove X2,C1361,C1362

9.C378+C375 change to 10uF*1

10.C460+C459 change to 10uF*1

11.Remove C986,C987,C989,C990 =>Add 1uF 0201*10

1003

1.Change EC side GPIO:PWR_LED to PWR_LED#,Remove Q32,R512

2.For separate coaxial and wire,update eDP MB connector pin define

3.Remove JLED1 connector

4.Change C427:0.1U_0402_16V4Z to 0.1U_0201_10V6K:SE00000VS00

1005

1.Swap DDR ChB Data,DQS# 6,7

2.Change PCH PCIE 0.1U_0402_16V7K to 0.1U_0201_10V6K:SE00000SV00 =>C572,C573,C617,C618,C681,C682,C683,C684,C685,C686,C687,C688

2.Change eDP cap from 0.1U_0402_16V7K to 0.1U_0201_10V6K:SE00000SV00 =>C910,C911,C912,C913,C914,C915

3.Add R80:0ohm of H_CPU_PWRGD for ESD request

4.Remove On Board WLAN:MD225

5.Add Motor parts(Not Ready)

6.Add iSSD i100 parts(Not Ready)

1006

1.Change R754,R751 0ohm from 0603 to 0402

2.Change C484 0.1U from 0603 to 0402

3.For DS3,Change power source from +3VALW_PCH to +VCCSUS3_3

4.Change R629 from 0_0805 to 0_0402

5.Change SATA cap from 0.1U_0402_16V7K to 0.01U_0201_10V7K =>C621~C628

1010

1.Add BATT_RST#,VR_LEFT,VR_RIGHT pin

2.Add iSSD i100 128GB*2 schematic

3.Add USB_HPD# pin

1011

1.Add Battery Reset function

2.Swap USB2.0,3.0 choke for connector side

順順順順順順順順

1013

1.Add Step Motor circuit

2.On Board iSSD:i100 change to mSATA SSD

3.WLAN change to on board:MD225

4.Change Card Reader PCIE from Port4 to Port1 CLK from Port5 to Port4

5.Change mSATA SATA port from Port1 to Port0

6.Add USB port 12 for mSATA

7.Remove D11,D12 and C357,C358 (HDMI RF request)

8.C396,C324 change to 0201

9.Remove C472 for +5VALW source cap

1014

1.Remove DPST_PWM buffer:U13,R783,R85

2.Change +3VS_FULL cap:C475,C466 from 0.1uF_0402 to 0201

3.Change SATA cap:C621,C622,C623,C624 from 0.01uF_0402 to 0201

1017

1.Add power source of +VCCAFDI_VRM at P.20

2.Update DS3,AOAC control signal connected to EC

1018~1021

1024

1.Remove R130

2.Define DRAM ID

3.Update TB schematic

4.Swap USB2.0 ESD pin

5.Add on/off BTN for debug

1027

1.Swap JTP1 pin for new module

2.Gerber schematic

1028 For Load BOM

1.Update Block Diagram

2.Update CPU,PCH part number

3.Update BOM config

1101

1.For

整整整整整整整整整整整整

2.Combine PWR schematic

3.A test SMT schematic

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

EE P.I.R

Q3ZMC M/B LA-8481P Schematic

1

50 51Thursday, April 12, 2012

1.0

5

Version Change List ( P. I. R. List )

Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )

Request

Page# Title

Item

Item Issue Description

Page#Page#

ItemItem

1201(EVT2 Gerber)

1.Modify EVT1 SMT memo into Schematic

2.Add 1U_0201_4V_6M *4(C1511,C1512,C1513,C1514) for ChA

D D

3.Add 1U_0201_4V_6M *4(C1515,C1516,C1517,C1518) for ChB

4.Delete ChA,ChB SPD ROM(U70,U72) circuit

5.JLVDS.15 change from VR_LEFT to GND

6.TB,pull high PCH_DPD_CLK,PCH_DPD_DAT to +3VS(R252,R254)

7.TB,add Buffer:U3 EN pin pull down resistor:R1075

8.TB,Change R1067 pull down form PA_LSRX_LSOE1_R to PA_LSRX_LSOE1_U

9.WLAN,Modify PCIE TX,RX,change P/N of RX signal

10.WL_OFF# connected to EC_Pin71 BT_ON# connected to EC_Pin117

11.mSATA,+3VS_FULL:Change C455 to 4.7U_0603_6.3V_6K,+1.5VS:Delete C433

12.Update Motor circuit,P.30

13.Add TPM/TCM co-layout circuit,P.30

14.USB PWR SW IC enable pin co-lay SYSON# and USB_EN#_R(EC_Pin81)

15.EC,P.32 (1)power source co-lay +3VALW/+3VLP (2)DC mode S4/S5 turn on +3VALW,+5VALW for Motor, MOTOR_BTN(EC_Pin17) (3)PPS_L connected to MOTOR_PPS_L(EC_Pin85) (4)PPS_R connected to MOTOR_PPS_R(EC_Pin91) (5)Turn on/off Motor +5VALW connected to MOTOR_PWR_ON(EC_Pin21) (6)Audio/B add Motor LED connected to MOTOR_LED#(EC_Pin36) (7)BI_DET changed to EC_Pin25 (8)Adapter ID pin connected to ADP_ID(EC_Pin64)

16.Update JAUDIO connector type and pin define,P.33

17.Add Motor BTN circuit,P.33 1207

C C

1.PCH_ACIN pull high R341 Change from 200K to 10K

0108(DVT)

1.For DS3,change P.18 PCH power source from +3VALW_PCH to +VCCSUS3_3 (R422,R657,R391,R397,R458)

2.Change TB_CLKREQ#_R power source from +3VS_POC to +3VS_LC (Q67,R1031)

3.Change Q67 direction

4.Change TB_SMB_DA,TB_SMB_CLK from PH +3VS_LC(R1036,R1037) to PL(R1046,R1047)

5.Change Q71 +3VS_LC enable pin from EN_LC_PWR to 1.05VS_LC_PG

6.Change R1110 from 348K_0402_1% to 35.7K_0402_1%

7.Change TB_GO2SX from PL to PH +3VS_POC(R1066)

8.Add TCM (U8) package into board file

9.For EC_PME#,R490 change to pop

10.For Motor BTN,R974 change to pop

11.Add MSATA RAID0 function (C625,C627,C626,C628)

12.Add PCH:GPIO35 to RAID0_DET,external pull down(R329)

13.Change TP from 6 pin to 8 pin,Add level shift Q9

14.Combine Q66,Q67 to Q89 dual package

15.For DS3,Add EC.82 ACPRESENT to PCH_ACIN(pop R456,unpop D19)

16.For eDP only,PCH_GPIO71 change from PL to NC(unpop R618)

17.For Motor VR,change from PH to PL 100K(R454,R455)

B B

0113

1.Remove mSATA USB port12

2.For ESD request,Reserve 0.1uf for FAN_SPEED1,FAN_PWM (C451,C450) 0117 (Final Schematic for Gerber)

1.Add Q30,Q31 for "LED" TB cable

2.Add MD222 BT_LED test point:T74

3.Add test point T75,T76,T77,T78,T79,T80 for TB boundary scan 0120

1.Unpop Power BTN(SW1)

2.For change BID from 0 to 1,pop R957:8.2K

3.For DS3,S3,Change R418 BOM config from S3@ to normal 0131

1.For

缺缺缺缺缺缺缺缺

2.For

3.For

4.For Vendor Report, Change Y1,Y2 from SJ10000DJ00:25MHZ 20PF +-30PPM 7V25000016 to SJ10000E800:25MHZ 10PF +-20PPM 7V25000014 Change C744,C745 form 27pf to 10pf Change C1338,C1340 from 20pf to 6.8pf

5.For cost,C496,C478 change to unpop

6.For cost,Change C505 from 1uF 0201 to 0.1uF 0201

7.For cost,Change C993,C992,C1009,C994,C1006,C1008,C1007,C1010,C986,C1002 from 1uF 0201 to 0.1uF 0201

8.For ESD request,pop 1000pf for FAN_SPEED1,FAN_PWM (C451,C450)

A A

and Unpop C579 1000p of FAN_SPEED1

9.For IOAC power control by EC,pop Q47

,Change C394,C1000 from SGA00001E00 to SGA00002N80

統統統統統統統統缺缺缺缺

,Change C599,C607 main source:SGA00004700,2nd source:SGA00004400

統統統統統統統統缺缺缺缺

,Change C1484,C1464 main source from SGA20331E10 to SGA19331D10

Title

TitleTitle

Date

DateDate

RequestRequest Owner

Owner

OwnerOwner

4

Issue DescriptionDate

Issue DescriptionIssue Description

0303 (PVT) Modify DVT SMT memo for BOM

1.C744,C745 change from 10P 25V J NPO 0402:SE00000F180 to 10P 50V J NPO 0402:SE071100J80

2.For INTEL TB review,pop R1036,R1037,R1048,unpop R1046,R1047,R1066

3.TB,C1424,C1425 change from SE000000K80:1U_0402_6.3V6K to SE076104K80:.1U_0402_16V7K

4.For USB enable pin change from SYSON#:R952 to USB_EN#:R951 Modify PVT layout

0.Remove on/off# BTN SW1 footprint

1.Change BT port from Port13 to Port8

2.Remove TCM parts:U8,R964,R965,C12,C1225

3.Remove EC 930 SPI ROM:U38,R694,R690,R698,R705,R692,C722,R695,C727

4.Remove SUS_PWR_DN_ACK for S3:EC U53.19,R409,R411

5.Update JLVDS1 pin define for +3VALW short issue

6.Add JLED1 connector

7.Remove JMT1,JMT2,JRTC1 and Change to JMR1 8pin conn.

8.Add EC U53.19:IRST_RST# (R461) to U26.1 for IOAC+IRST issue

9.Change 0ohm to 0ohm_short:R80,R314,R320,R372,R382,R394,R412,R421, R577,R578,R579,R581,R582,R612,R629,R661,R785,R940,R947,R953,R956, R959,R967,R973,R974

10.For WLAN from +3VALW to +3VS_WLAN.Add R962,Remove R943

11.Change Motor Power source from PMOS to NMOS Remove:R452,R453,Q69,C818,R754,J14 Add:U23,Q90,R459,C472,C503,C504,C481,R460

12.Remove net :ADP_ID

13.For TB ref. design,Add dual PMOS Q91,Q92,NMOS Q32,R1124 0306

14.Add DPWROK PL:R463 for INTEL suggestion

15.Remove JP1 EC debug port

16.Remove MDP_HPD ESD:D45

17.Add H11:H_4P0N for eDP connector

18.Add EC_SPOK(U53.120) to control +VSBP

19.add BT_LED U53.119 control pin,R492

20.add TB_FORCE_PWR:R1097 to PCH_GPIO12

21.Add WLAN discharge circuit:Q62B,R473=>Remove

22.For ACER TB request,add PH R1125 to +3VS_POC 0308

23.Remove ME RST# 0ohm:R561

24.Add C785,C786,C787,C788,C789 for ESD request

25.Add Q69 group(Q69,Q62B,R452,R453,R754,C818,R474,C540) for +3V_MCU

26.Change +3VS_FULL:J8 from 43*79 to 43*39 0309

27.Change Q62 dual 2N7002 to normal 2N7002

28.Add IRST_RST# PH:R965 to +3VALW_EC

29.Motor +3V_MCU design: Delete PMOS:Q69 group(Q69,Q62B,R452,R453,R754,C818,R474,C540) Add NMOS:Q87 group(Q87,Q93,R21,R789,C811)

0312 Modify for PVT SMT

1.For EC_SMI#,R939 change to @

2.For PCH_ACIN,R341 change to @

3.For ACER only,TPM change from SA00005EG00 to SA00005PH00

4.Change SPOK control function from PWR to EC_SPOK

5.Change HDMI cap form SE076103K80:0.01u to SE076104K80:0.1u:C280~C287

6.Change Board ID form 1 to 2,R960 chnage to 18K_0402_5%

7.For Vgs(th) issue,change Q20 from 2N7002 to BSS138(SB000002X00)

8.For Q5LJ1 RTC issue, change X1 from SJ10000DM00:S CRYSTAL 32.768KHZ 12.5PF 9H03200019 to SJ100004Z00:S CRYSTAL 32.768K 12.5PF 1TJF125DP1A000D

9.Remove KB cap 100P_0201*24pcs C245,C246,C247,C248,C249,C250,C251,C252,C253,C254,C255,C256,C258,C259, C260,C263,C265,C266,C267,C268,C269,C270,C271,C272

10.For ME PE review,remove C442

11.For cost,Change DDR C1464 to @

12.For cost,Change DDR C1258,C1259,C1261,C1291,C1292,C1293 to @

13.For cost,Change DDR cap from 1uF_0201 to 0.1uF_0201 C1462,C1461,C1460,C1459,C1514,C1513,C1512,C1511, C1466,C1476,C1477,C1467,C1470,C1471,C1478,C1468 C1504,C1503,C1502,C1501, C1518,C1517,C1516,C1515, C1487,C1497,C1498,C1488,C1491,C1492,C1499,C1489

14.For cost,Change TB C1406,C1407,C1443,C1444 from 1uF_0201 to 0.1uF_0201 0314

15.For HF parts,change Q6 from SB501380020 to SB501380050

16.For HF parts,change Q87 from SB534560020 to SB534560030 0315

17.Combine Power latest schematic

漏漏漏漏漏漏漏漏

issue,Change PCH_PCIE_WAKE#_R(EC_PME#) pull high

3

Page 2

Page 2Page 2

2

Solution Description

Solution Description Rev.

Solution DescriptionSolution Description

0402 Modify for 1.0 layout

1.Add soft start R756,C819 of Q68:+VCCSUS3_3 and R757,C820 of Q64:+V5REF_SUS

2.Add TB GPIO7(R1129) to PCH GPIO49,GPIO6(R1128) to PCH GPIO20

3.Add TB wake# colay:R1098 to U53.64(EC GPIO49),PH R976 to +3VALW_EC

4.Add TB +3VS_POC jumper colay +3VS(J4) and +3VALW(J2)

5.Delete colay J13(+3VALW to +VCCSUS3_3),R751(+5VALW to +V5REF_SUS)

6.Add C1519:10U_0603 for +0.675VS

7.Change C1468,C1471,C1476,C1477,C1478,C1491,C1492,C1499 from

0.1U_0201_10V6K to 1U_0402_6.3V6K

8.Add R277,R1109 for MOS Vgs(th) reserve.

9.Change Motor BTN SW:R974 from 0ohm_short to normal 0ohm

10.Add C790,C791 of VGATE for ESD team

11.Reduce Jumper size from 43*118 to 43*79:PJ17,PJ7,J3 Change Jumper sixe from 43*118(PJ1) to 43*79(PJ1)+43*39(PJ8) Change Jumper sixe from 43*118(PJ2) to 43*79(PJ2)+43*39(PJ10)

0411 Modify for PreMP SMT update PVT SMT memo

1.Add C787:100P_0201_25V8J for PM_DRAM_PWRGD

2.Add C785:100P_0201_25V8J and C786:100P_0402_50V8J for DIMM_DRAMRST#

3.Add C788:100P_0402_50V8J for SM_DRAMRST#

4.Add C789:100P_0402_50V8J for SYS_PWROK

5.For TB GPIO6,GPIO7,change PH to PL,unpop R1036,R1037,pop R1046,R1047

6.Delete Q65 for TB GPIO6,GPIO7

7.Add TB_FORCE_PWR_R to PCH,pop R1097,unpop PH:R657 at PCH side

8.For TB_PLUG_EVENT,unpop PCH side PH:R406 update for PreMP

1.Add C790:100P_0402_50V8J,C791:100P_0201_25V8J for VGATE

2.Change Board ID to "4" for 1.0=>R960:56K

3.Change PCH from SA00005AG00:HM77 QPRG to MP version SA00005AGI0:HM77 SLJ8C

4.TB chip change to MP version:NA

5.Change LA8481P from DA6:DAA00003N00 to DAZ:DAZ0NS00100

6.Change Y1:25MHz cap:C744,C745 from 10P to 8.2P_0402_50V8D

7.For VR,change R454,R455 from 100K_5% to 100K_1%

8.Add C1261,C1291 2.2U_0603_6.3V6K for DDR Memory test issue

9.Change C1504,C1501,C1517,C1503,C1511,C1460,C1462,C1514 from 0.1uF 0201 to 1uF 0201

10.Change TB R1083,R1078,R1089,R1080,R1081,R1082,R1088,R1086 from 12.1ohm to 0ohm,R1086 change to @

0412 Modify for 1A layout

11.For Motor_BTN,add PH:R909 to +3VLP

12.Remove EC_TB_WAKE#:R1098

13.For LEGO,Change control pin from PCH to EC (1)LED:PCH_GPIO34 change to EC_GPIO122(TB_LED) (2)Eject:PCH_GPIO48 change to EC_GPIO64,pop R976(TB_EJECT_BTN) (3)pop Q30,Q31,R1125,unpop R1056,R1057

Rev.Page#

Rev.Rev.

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/4/6 2013/4/6

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

EE P.I.R

Q3ZMC M/B LA-8481P Schematic

1

51 51Thursday, April 12, 2012

1.0

Compal LA-8481P Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual