COMPAL LA-8441P Schematics

1 1

2 2

Compal Confidential

QAU20 M/B Schematics Document

Date : 2011/11/08

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/03

Compal Secret Data

Deciphered Date

Title

Cover Page

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

LA-8441P

146Monday, November 14, 2011

0.1

Compal Confidential

0RGHO1DPH4$8 )LOH1DPH/$3

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Page 4~10

Memory BUS(DDRIII)

1.5V DDRIII 1066/1333/1600 for CR

1.5V DDRIII 1066/1333 for HR

Channel A

(256MX16) X4 chips

2GB/4GB chips

Page 11

DMI x4FDI x8

/9'6&RQQ

0LQL+'0,&RQQ

Page 23

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2 2

0XUDWD/;5:+)$$

LVDS

HDMI

SMBus

,QWHO

USB3.0

USB

PCIE2

SATA

HDA

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Port 0

Page 22

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Page 29

USB

670)5'<75 :/&6330&8

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LPC

Page 27

Compal Secret Data

2009/08/01 2011/10/18

Compal Secret Data

Deciphered Date

/RFDWLRQ8+8+

7R,2ERDUGFRQQ

4 4

Page 25

Page 12

(1(.% $

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

&RPER-DFNZ+30,&

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

*<526&23( /*'75/*$3

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Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Block Diagrams

LA-8441P

246Monday, November 14, 2011

0.1

SPI

QAZ50 (LA-8101P Ver:0.1)

Voltage Rails

Power Plane Description

VIN

BATT+

B+

+CPU_CORE

1 1

+VCCSA ON

+VGFX_CORE Core voltage for UMA graphic

+0.75VS

+CHGRTC BATT+ or Vin to +CHGRTC always on power rail for sequence control

+RTCVCC

+VCCP

+1.5V

+1.5VS

+LG_OUT Voltage for LCD Panel Backlight LED Power

+1.8VS

+3VALW

+3VALW_EC

+LAN_IO

+3V_PCH

+3VS

+5VALW

+5V_PCH

+5VS

2 2

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

2011/08/19 Modify

Adapter power supply (19V)

Battery power supply (7.2V)

AC or battery power rail for power circuit.

Core voltage for CPU

+0.75VP to +0.75VS switched power rail for DDR term inator

RTC power

+VCCP (1.05V ) power for PCH

+1.5VP to +1.5V power rail for DDRIII (1.35V OR 1.5V)

+1.5VS switched power rail

(+5VALW ) to 1.8V switched power rail to PCH & GPU

+3VALW always on power rail

+3VALW always to KBC

+3VALW to +LAN_IO power rail for LAN

+3VALW to +3V_PCH power rail for PCH (Short Jum per)

+3VALW to +3VS power rail

+5VALWP to +5VALW power rail

+5VALW to +5V_PCH power rail for PCH (Short resister )

+5VALW to +5VS switched power rail OFFONOFF

S3 S5

N/A N/A N/A

OFF

OFF OFFVoltage for CPU SA RALL

OFF OFF

ON ON*

OFF OFF

ON ON

OFF OFF

OFF

ON ON*

ON ON ON*

ON ON

OFF

ON ON*

ON ON

N/AN/AN/A

OFF

ONON

OFF

ON*

OFF

ON*

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S1# SLP_S3#

EC SM Bus1 address

Device

Smart Battery

Address

0001 011X b

EC SM Bus2 address

Device

PCH ( Reserve)

Address

1010 0110b

SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

LOW

LOW LOW LOW LOW

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

ONONON ON

OFF

LOW

OFF

SMBUS Control Table

SOURCE

EC_SMB_CK1 EC_SMB_DA1

EC_SMB_CK2 EC_SMB_DA2

PCH_SMBCLK PCH_SMBDATA PCH

3 3

PCH_SMLCLK PCH_SMLDATA

KB9012

PCH

CLKOUT_PCIE0

CLKOUT_PCIE1

CLKOUT_PCIE2

CLK

CLKOUT_PCIE3

CLKOUT_PCIE4

4 4

CLKOUT_PCIE5

CLKOUT_PCIE7 None

CLKOUT_PEG_B

2011/07/28 Modify

MINI2

MINI1

BATT

(WLan1)

(mSATA)

DESTINATIONDIFFERENTIAL

10/100/1G LAN

MINI CARD WLAN

None

CARD READER

None

NoneCLKOUT_PCIE6

None

EC_SMB_CK2

EC_SMB_DA2

PCH_SMBCLK

PCH_SMBDATA

FLEX CLOCKS DESTINATION

CLKOUTFLEX0

CLKOUTFLEX1

CLKOUTFLEX2

CLKOUTFLEX3

None

Symbol Note :

: means Digital Ground

: means Analog Ground

CLKOUT

PCI0

PCI1

PCI2

PCI3

PCI4

DESTINATION

PCH_LPBACK

PCI_LPC

None

SATA

SATA0

SATA1

SATA2

SATA3

SATA4

SATA5

DESTINATION

m-SATA,JSSD1

None

2011/08/19 Modify

CONN@@Option

CR UMA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

Compal Secret Dat a

2009/08/01 2011/10/18

Compal Secret Dat a

Deciphered D ate

USB Port Table

USB 2.0 USB 1.1 Port

UHCI0

EHCI1

EHCI2

USB 3.0 Port

UHCI1

UHCI2

UHCI3

UHCI4

UHCI5

UHCI6

USB/B ( External)

Title

Size Document Number Rev

Date: Sheet

2011/07/12 Check

2 External

0 1 2 3 4 5 6 7 8

9 10 11 12 13

LA-8441P

USB Port

USB/B ( External) USB/B ( External)

Mini Card(WLAN) Camera

Test Point (RH274,RH310)

2 External USB Port

USB/B ( External) USB/B ( External)

Compal Electronics, Inc.

Notes List

0.1

346M onday, November 14, 2011

0.1

D D

C C

+VCCP

RC2

24.9_0402_1%

eDP_COMPIO and ICOMPO signals should be shorted near balls

B B

and routed with typical impedance <25 mohms

+VCCP

RC86 10K_0402_5%@RC86 10K_0402_5%@

DMI_CRX_PTX_N0{14} DMI_CRX_PTX_N1{14} DMI_CRX_PTX_N2{14} DMI_CRX_PTX_N3{14}

DMI_CRX_PTX_P0{14} DMI_CRX_PTX_P1{14} DMI_CRX_PTX_P2{14} DMI_CRX_PTX_P3{14}

DMI_CTX_PRX_N0{14} DMI_CTX_PRX_N1{14} DMI_CTX_PRX_N2{14} DMI_CTX_PRX_N3{14}

DMI_CTX_PRX_P0{14} DMI_CTX_PRX_P1{14} DMI_CTX_PRX_P2{14} DMI_CTX_PRX_P3{14}

FDI_CTX_PRX_N0{14} FDI_CTX_PRX_N1{14} FDI_CTX_PRX_N2{14} FDI_CTX_PRX_N3{14} FDI_CTX_PRX_N4{14} FDI_CTX_PRX_N5{14} FDI_CTX_PRX_N6{14} FDI_CTX_PRX_N7{14}

FDI_CTX_PRX_P0{14} FDI_CTX_PRX_P1{14} FDI_CTX_PRX_P2{14} FDI_CTX_PRX_P3{14} FDI_CTX_PRX_P4{14} FDI_CTX_PRX_P5{14} FDI_CTX_PRX_P6{14} FDI_CTX_PRX_P7{14}

FDI_FSYNC0{14} FDI_FSYNC1{14}

FDI_INT{14}

FDI_LSYNC0{14} FDI_LSYNC1{14}

1 2

EDP_COMP

UCPU1A

DMI_RX#[0]

DMI_RX#[1]

DMI_RX#[2]

P10

DMI_RX#[3]

DMI_RX[0]

DMI_RX[1]

DMI_RX[2]

P11

DMI_RX[3]

DMI_TX#[0]

DMI_TX#[1]

DMI_TX#[2]

DMI_TX#[3]

DMI_TX[0]

DMI_TX[1]

DMI_TX[2]

DMI_TX[3]

FDI0_TX#[0]

W11

FDI0_TX#[1]

FDI0_TX#[2]

AA6

FDI0_TX#[3]

FDI1_TX#[0]

FDI1_TX#[1]

FDI1_TX#[2]

AC9

FDI1_TX#[3]

FDI0_TX[0]

W10

FDI0_TX[1]

FDI0_TX[2]

AA7

FDI0_TX[3]

FDI1_TX[0]

FDI1_TX[1]

AA3

FDI1_TX[2]

AC8

FDI1_TX[3]

AA11

FDI0_FSYNC

AC12

FDI1_FSYNC

U11

FDI_INT

AA10

FDI0_LSYNC

AG8

FDI1_LSYNC

AF3

eDP_COM PIO

AD2

eDP_ICOMPO

AG11

eDP_HPD#

AG4

eDP_AUX#

AF4

eDP_AUX

AC3

eDP_TX#[0]

AC4

eDP_TX#[1]

AE11

eDP_TX#[2]

AE7

eDP_TX#[3]

AC1

eDP_TX [0]

AA4

eDP_TX [1]

AE10

eDP_TX [2]

AE6

eDP_TX [3]

IVY-BRIDGE_BGA1023

SA00004SX00

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

G3 G1 G4

H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7

K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6

G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4

F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

DMI Intel(R) FDI

PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14]

PCI EXPRESS -- GRAPHICS

PEG_TX#[15]

eDP

PEG_COMP

RC1

24.9_0402_1%

+VCCP

PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typi cal impedance = 43 mohms

PEG_ICOMPO signals should be routed with max length = 500 mils

- typical impedance = 14.5 mohms

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENT IAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENT IAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/04/26 2011/10/18

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(1/7) DMI,FDI,PEG

LA-8101P

446Monday, November 14, 2011

0.1

Buffered reset to CPU

+3VS

CC1

0.1U_0402_16V4Z

D D

UCPU1B

F49

PROC_SELECT#

C57

PROC_DETECT#

C49

CATERR#

A48

PECI

C45

PROCHOT#

D45

THERMTRIP#

C48

PM_SYNC

B46

UNCOREPWRGOOD

BE45

SM_DRAMPWROK

D44

RESET#

PLT_RST#

PLT_RST#{15,25,28}

This pin is for compability with future platforms. A pull up resistor to VCCIO is required if connected to the DF_TVS strap on the PCH.

H_SNB_IVB#{16}

PROC_DETECT (Processor Detect): pulled to ground on the processor package. There is no connection to the processor silicon for this signal. System board designers may use this

+VCCP

C C

Processor Pullups

RC8 62_0402_5%RC8 62_0402_5%

RC11 10K_0402_5%RC11 10K_0402_5%

H_PROCHOT#

H_CPUPWRGD_R

signal to determine if the processor is present

H_PROCHOT#{28}

H_THRMTRIP#{16}

H_PM_SYNC{14}

H_CPUPWRGD{16}

For EMI Request

H_CPUPWRGD

CC4

1 2

0.1U_0402_16V4Z

B B

0.1U_0402_16V4Z

XDP_DBRESET#

CC5

1 2

0.1U_0402_16V4Z

CC5 near RC17

1 2

RC7 10K_0402_5%@RC7 10K_0402_5%@

T5PAD@T5PAD

H_PECI{16,28} H_DRAMRST# {6}

H_PROCHOT#_R

1 2

RC10 56_0402_5%RC10 56_0402_5%

H_THEMTRIP#

1 2

RC13 0_0402_5%RC13 0_0402_5%

1 2

RC16 0_0402_5%RC16 0_0402_5%

1 2

RC18 130_0402_5%RC18 130_0402_5%

H_PM_SYNC_R

H_CPUPWRGD_R

PM_DRAM_PWRGD_RPM_SYS_PWRGD_BUF

BUF_CPU_RST#

UC1

SN74LVC1G07DCKR_SC70-5

MISC THERMAL PWR MANAGEMENT

+VCCP

RC3

RC3 75_0402_5%

75_0402_5%

RC4

43_0402_1%

BUFO_CPU_RST# BUF_CPU_RST#

43_0402_1%

1 2

BCLK

BCLK#

DPLL_REF_CLK

DPLL_REF_CLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

DDR3

MISC

DDR3

MISC

PRDY#

PREQ#

TCK

TMS

TRST#

TDI

TDO

DBR#

BPM#[0] BPM#[1] BPM#[2]

JTAG & BPM

BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

RC6

RC6 0_0402_5%

0_0402_5%

J3 H2

RC12 1K_0402_1%RC12 1K_0402_1%

AG3

RC35 1K_0402_1%RC35 1K_0402_1%

AG1

H_DRAMRST#

AT30

SM_RCOMP0

BF44

SM_RCOMP1

BE43

SM_RCOMP2

BG43

N53 N55

XDP_TCK

L56

XDP_TMS

L55

XDP_TRST#

J58

M60 L59

XDP_DBRESET#_R

K58

G58 E55 E59 G55

XDP_BPM#4_R

G59

XDP_BPM#5_R

H60

XDP_BPM#6_R

J59

XDP_BPM#7_R

J61

1 2 1 2

XDP_TDI XDP_TDO

CLK_CPU_DMI {13} CLK_CPU_DMI# {13}

RC17 0_0402_5%RC17 0_0402_5%

1 2

RC19 0_0402_5%@RC19 0_0402_5%@

1 2

RC20 0_0402_5%@RC20 0_0402_5%@

1 2

RC21 0_0402_5%@RC21 0_0402_5%@

1 2

RC22 0_0402_5%@RC22 0_0402_5%@

1 2

XDP_DBRESET#

+VCCP

XDP_DBRESET#

RC5 1K_0402_5%RC5 1K_0402_5%

circuit check 10k

XDP_DBRESET# {14}

CFG12 {7} CFG13 {7} CFG14 {7} CFG15 {7}

+3VS

IVY-BRIDGE_BGA1023

SA00004SX00

Issued Date

SA00004SX00

Compal Secret Data

2010/4/26 2011/10/18

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PROCESSOR(2/7) PM,XDP,CLK

Size Document Number Rev

Custom

Date: Sheet

LA-8101P

546Monday, November 14, 2011

0.1

Follow PBL22 LA-7391 PR04

SYS_PWROK{14}

PM_DRAM_PWRGD{14}

A A

+3V_PCH

Modify 2011/10/03

RUN_ON_CPU1.5VS3#{9}

RC84

10K_0402_5%

RC27

@ RC27

0_0402_5%

1 2

RC28

1 2

200_0402_5%

+3VS

Part Number = SA00003Y000

Modify

+3V_PCH

2011/10/03

UC2

UC2 74AHC1G09GW_TSSOP5

74AHC1G09GW_TSSOP5

RUN_ON_CPU1.5VS3#

+1.5V_CPU_VDDQ

CC2

0.1U_0402_16V4Z

RC29

RC29 39_0402_5%

39_0402_5%

QC1

QC1 2N7002_SOT23

2N7002_SOT23

RC25

RC25 200_0402_5%

200_0402_5%

PM_SYS_PWRGD_BUF

DDR3 Compensation Signals

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

PU/PD for JTAG signals

XDP_TMS

RC30 51_0402_5%RC30 51_0402_5%

XDP_TDI

RC31 51_0402_5%RC31 51_0402_5%

XDP_TDO

RC32 51_0402_5%RC32 51_0402_5%

XDP_TCK

RC33 51_0402_5%RC33 51_0402_5%

XDP_TRST#

RC34 51_0402_5%RC34 51_0402_5%

RC23 140_0402_1%RC23 140_0402_1%

RC24 25.5_0402_1%

RC26 200_0402_1%RC26 200_0402_1%

SD00000X700

+VCCP

Security Classification

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENT IAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENT IAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

UCPU1C

DDR_A_D[0..63]{11}

D D

C C

DDR_A_BS0{11}

B B

DDR_A_BS1{11} DDR_A_BS2{11}

DDR_A_CAS#{11} DDR_A_RAS#{11} DDR_A_WE#{11}

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

AG6

AP11

AJ10

AR11

AP6 AU6 AV9 AR6

AP8 AT13 AU13

BC7

BB7 BA13 BB11

BA7

BA9

BB9 AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43

AW48

BC48 BC45 AR45 AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56

BD37 BF36 BA28

BE39 BD39 AT41

AJ6

AL6

AJ8 AL8 AL7

UCPU1C

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

SA_CK[0] SA_CK#[0] SA_CKE[0]

SA_CK[1] SA_CK#[1] SA_CKE[1]

SA_CS#[0] SA_CS#[1]

SA_ODT[0] SA_ODT[1]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

M_CLK_DDR0

AU36

M_CLK_DDR#0

AV36

DDR_CKE0_DIMMA

AY26

M_CLK_DDR1

AT40

M_CLK_DDR#1

AU40

1 2

BB26

RC81 36.5_0402_1%RC81 36.5_0402_1%

BB40

1 2

BC41

RC82 36.5_0402_1%RC82 36.5_0402_1%

AY40

1 2

BA41

RC83 36.5_0402_1%RC83 36.5_0402_1%

DDR_A_DQS#0

AL11

DDR_A_DQS#1

AR8

DDR_A_DQS#2

AV11

DDR_A_DQS#3

AT17

DDR_A_DQS#4

AV45

DDR_A_DQS#5

AY51

DDR_A_DQS#6

AT55

DDR_A_DQS#7

AK55

DDR_A_DQS0

AJ11

DDR_A_DQS1

AR10

DDR_A_DQS2

AY11

DDR_A_DQS3

AU17

DDR_A_DQS4

AW45

DDR_A_DQS5

AV51

DDR_A_DQS6

AT56

DDR_A_DQS7

AK54

DDR_A_MA0

BG35

DDR_A_MA1

BB34

DDR_A_MA2

BE35

DDR_A_MA3

BD35

DDR_A_MA4

AT34

DDR_A_MA5

AU34

DDR_A_MA6

BB32

DDR_A_MA7

AT32

DDR_A_MA8

AY32

DDR_A_MA9

AV32

DDR_A_MA10

BE37

DDR_A_MA11

BA30

DDR_A_MA12

BC30

DDR_A_MA13

AW41

DDR_A_MA14

AY28

DDR_A_MA15

AU26

M_CLK_DDR0 {11} M_CLK_DDR#0 {11} DDR_CKE0_DIMMA {11}

+0.75VS

DDR_CS0_DIMMA# {11}

+0.75VS

M_ODT0 {11}

+0.75VS

DDR_A_DQS#[0..7] {11}

M_CLK_DDR1

M_CLK_DDR#1

DDR_A_DQS[0..7] {11}

DDR_A_MA[0..15] {11}

30.1_0402_1%

RC87

CC10

CC10 2P_0402_50V8C

2P_0402_50V8C

RC88

30.1_0402_1%

0.1U_0402_16V4Z

CC11

BD13

BF12

BD10 BD14 BE13

BF16 BE17 BE18 BE21 BE14 BG14 BG18

BF19 BD50

BF48 BD53

BF52 BD49 BE49 BD54 BE53

BF56 BE57 BC59

AY60 BE54 BG54 BA58

AW59 AW58

AU58 AN61 AN59 AU59 AU61 AN58 AR58 AK58

AL58 AG58 AG59 AM60

AL59

AF61 AH60

BG39 BD42

AT22

AV43

BF40 BD45

AN3 AR4 AK4 AK3 AN4 AR1 AU4 AT2 AV4 BA4 AU3 AR3 AY2 BA3 BE9 BD9

BF8

AL4 AL1

UCPU1D

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

BA34

SB_CK[0]

AY34

SB_CK#[0]

AR22

SB_CKE[0]

BA36

SB_CK[1]

BB36

SB_CK#[1]

BF27

SB_CKE[1]

BE41

SB_CS#[0]

BE47

SB_CS#[1]

AT43

SB_ODT[0]

BG47

SB_ODT[1]

AL3

SB_DQS#[0]

AV3

SB_DQS#[1]

BG11

SB_DQS#[2]

BD17

SB_DQS#[3]

BG51

SB_DQS#[4]

BA59

SB_DQS#[5]

AT60

SB_DQS#[6]

AK59

SB_DQS#[7]

AM2

SB_DQS[0]

AV1

SB_DQS[1]

BE11

SB_DQS[2]

BD18

SB_DQS[3]

BE51

SB_DQS[4]

BA61

SB_DQS[5]

AR59

SB_DQS[6]

AK61

SB_DQS[7]

DDR SYSTEM MEMORY B

BF32

SB_MA[0]

BE33

SB_MA[1]

BD33

SB_MA[2]

AU30

SB_MA[3]

BD30

SB_MA[4]

AV30

SB_MA[5]

BG30

SB_MA[6]

BD29

SB_MA[7]

BE30

SB_MA[8]

BE28

SB_MA[9]

BD43

SB_MA[10]

AT28

SB_MA[11]

AV28

SB_MA[12]

BD46

SB_MA[13]

AT26

SB_MA[14]

AU22

SB_MA[15]

IVY-BRIDGE_BGA1 023

SA00004SX00

+1.5V

RC36

1K_0402_5%

DDR3_DRAMRST#_RH_DRAMRST#

1 2

QC2

QC2 BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

CC3

0.047U_0402_16V4Z

H_DRAMRST#{5}

RC38

4.99K_0402_1%

A A

DRAMRST_CNTRL_PCH{9,13}

DRAMRST_CNTRL_EC{28}

RC39

0_0402_5%@

1 2

RC53

1 2

0_0402_5%

DRAMRST_CNTRL

RC37

RC37 1K_0402_5%

1K_0402_5%

1 2

DDR3_DRAMRST# {11}

Security Classification

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENT IAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENT IAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/04/26 2011/10/18

IVY-BRIDGE_BGA1023

SA00004SX00

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(3/7) DDRIII

LA-8101P

0.1

646Monday, November 14, 2011

CFG Straps for Processor

CFG2

D D

RC40

RC40 1K_0402_1%

1K_0402_1%

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2

UCPU1E

CFG0

T9T9

CFG1

T6T6

CFG2 CFG3

T11T11

CFG4

C C

CFG12{5} CFG13{5} CFG14{5} CFG15{5}

RC42 49.9_0402_1%RC42 49.9_0402_1%

+CPU_CORE

RC44 49.9_0402_1%RC44 49.9_0402_1%

+VGFX_CORE

RC46

1K_0402_1%

B B

1K_0402_1%

1 2

RC45 49.9_0402_1%RC45 49.9_0402_1%

CPU_RSVD6 CPU_RSVD7

RC47

RC47 1K_0402_1%

1K_0402_1%

1 2

RC43 49.9_0402_1%RC43 49.9_0402_1%

CFG5 CFG6 CFG7 CFG8

T8T8

CFG9

T14T14

CFG10

T15T15

CFG11

T16T16

CFG12 CFG13 CFG14 CFG15 CFG16

T17T17

CFG17

T18T18

VAXG_VAL_SENSE

VSSAXG_VAL_SENSE

1 2

RC9 0_0402_5%RC9 0_0402_5%

VCC_VAL_SENSE VSS_VAL_SENSE

T25T25

B50

CFG[0]

C51

CFG[1]

B54

CFG[2]

D53

CFG[3]

A51

CFG[4]

C53

CFG[5]

C55

CFG[6]

H49

CFG[7]

A55

CFG[8]

H51

CFG[9]

K49

CFG[10]

K53

CFG[11]

F53

CFG[12]

G53

CFG[13]

L51

CFG[14]

F51

CFG[15]

D52

CFG[16]

L53

CFG[17]

H43

VCC_VAL_SENSE

K43

VSS_VAL_SENSE

H45

VAXG_VAL_SENSE

K45

VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

G48

RSVD47

H48

RSVD6

K48

RSVD7

BA19

RSVD8

AV19

RSVD9

AT21

RSVD10

BB21

RSVD11

BB19

RSVD12

AY21

RSVD13

BA22

RSVD14

AY22

RSVD15

AU19

RSVD16

AU21

RSVD17

BD21

RSVD18

BD22

RSVD19

BD25

RSVD20

BD26

RSVD21

BG22

RSVD22

BE22

RSVD23

BG26

RSVD24

BE26

RSVD25

BF23

RSVD26

BE24

RSVD27

BCLK_ITP

BCLK_ITP#

RESERVED

DC_TEST_A4 DC_TEST_C4 DC_TEST_D3

DC_TEST_D1 DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61 DC_TEST_D61

DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58

DC_TEST_BG4 DC_TEST_BG3

DC_TEST_BE3

DC_TEST_BG1

DC_TEST_BE1

DC_TEST_BD1

RSVD30 RSVD31 RSVD32 RSVD33

RSVD34 RSVD35 RSVD36 RSVD37 RSVD38

RSVD39 RSVD40

RSVD41 RSVD42 RSVD43 RSVD44

RSVD45

N59 N58

N42 L42 L45 L47

M13 M14 U14 W14 P13

AT49 K24

AH2 AG13 AM14 AM15

N50

A4 C4 D3 D1 A58 A59 C59 A61 C61 D61 BD61 BE61 BE59 BG61 BG59 BG58 BG4 BG3 BE3 BG1 BE1 BD1

CLK_RES_ITP {13} CLK_RES_ITP# {13}

DC_TEST_C4_D3

DC_TEST_A59_C59

DC_TEST_A61_C61

DC_TEST_BE59_BE61

DC_TEST_BG59_BG61

DC_TEST_BE3_BG3

DC_TEST_BE1_BG1

These pins are for solder joint reliability and non-critical to function. For BGA only.

Display Port Presence Strap

CFG4

PCIE Port Bifurcation Straps

CFG[6:5]

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

CFG4

1K_0402_1%

11: (Default) x16 - Device 1 functions 1 and 2 disabled

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled

01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

RC41

RC41 1K_0402_1%

1K_0402_1%

1 : Disabled; No Physical Display Port attached to Embedded Display Port

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

CFG6

CFG5

CFG7

@RC48

RC48

@RC50

RC49

@RC49

1K_0402_1%

RC50 1K_0402_1%

1K_0402_1%

IVY-BRIDGE_BGA1023

SA00004SX00

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENT IAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENT IAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/04/26 2011/10/18

PEG DEFER TRAINING

CFG7

Compal Secret Data

Deciphered Date

1: (Default) PEG Train immediately following

xxRESETB de assertion

0: PEG Wait for BIOS for training

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(4/7) RSVD,CFG

LA-8101P

0.1

746Monday, November 14, 2011

0.1

D D

C C

B B

ULV type CPU

+CPU_CORE

28A

UCPU1F

POWER

+VCCP

18A

AF46

VCCIO[1]

AG48

VCCIO[3]

AG50

A26

VCC[1]

A29

VCC[2]

A31

VCC[3]

A34

VCC[4]

A35

VCC[5]

A38

VCC[6]

A39

VCC[7]

A42

VCC[8]

C26

VCC[9]

C27

VCC[10]

C32

VCC[11]

C34

VCC[12]

C37

VCC[13]

C39

VCC[14]

C42

VCC[15]

D27

VCC[16]

D32

VCC[17]

D34

VCC[18]

D37

VCC[19]

D39

VCC[20]

D42

VCC[21]

E26

VCC[22]

E28

VCC[23]

E32

VCC[24]

E34

VCC[25]

E37

VCC[26]

E38

VCC[27]

F25

VCC[28]

F26

VCC[29]

F28

VCC[30]

F32

VCC[31]

F34

VCC[32]

F37

VCC[33]

F38

VCC[34]

F42

VCC[35]

G42

VCC[36]

H25

VCC[37]

H26

VCC[38]

H28

VCC[39]

H29

VCC[40]

H32

VCC[41]

H34

VCC[42]

H35

VCC[43]

H37

VCC[44]

H38

VCC[45]

H40

VCC[46]

J25

VCC[47]

J26

VCC[48]

J28

VCC[49]

J29

VCC[50]

J32

VCC[51]

J34

VCC[52]

J35

VCC[53]

J37

VCC[54]

J38

VCC[55]

J40

VCC[56]

J42

VCC[57]

K26

VCC[58]

K27

VCC[59]

K29

VCC[60]

K32

VCC[61]

K34

VCC[62]

K35

VCC[63]

K37

VCC[64]

K39

VCC[66]

K42

VCC[67]

L25

VCC[68]

L28

VCC[69]

L33

VCC[70]

L36

VCC[71]

L40

VCC[72]

N26

VCC[73]

N30

VCC[74]

N34

VCC[75]

N38

VCC[76]

CORE SUPPLY

VCCIO[4]

AG51

VCCIO[5]

AJ17

VCCIO[6]

AJ21

VCCIO[7]

AJ25

VCCIO[8]

AJ43

VCCIO[9]

AJ47

VCCIO[10]

AK50

VCCIO[11]

AK51

VCCIO[12]

AL14

VCCIO[13]

AL15

VCCIO[14]

AL16

VCCIO[15]

AL20

VCCIO[16]

AL22

VCCIO[17]

AL26

VCCIO[18]

AL45

VCCIO[19]

AL48

VCCIO[20]

AM16

VCCIO[21]

AM17

VCCIO[22]

AM21

VCCIO[23]

AM43

VCCIO[24]

AM47

VCCIO[25]

AN20

VCCIO[26]

AN42

VCCIO[27]

AN45

VCCIO[28]

AN48

VCCIO[29]

AA14

VCCIO[30]

AA15

VCCIO[31]

AB17

VCCIO[32] VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49]

VCCIO50 VCCIO51

VCCIO_SEL

VCCPQE[1] VCCPQE[2]

AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15

W16 W17

BC22

+1.05VS_VCCPQ

AM25 AN22

PEG IO AND DDR IO

RAILS

RC51

1 2

0_0805_5%

VCCP_PWRCTRL_R

choose low or high

RC54

1 2

0_0805_5%

1 2

CC73 1U_0402_6.3V6KCC73 1U_0402_6.3V6K

+VCCP

+VCCP +VCCP

+VCCP

RC52

RC52 75_0402_5%@

75_0402_5%@

Voltage selection for VCCIO: For Huron River platforms, this pin must be pulled high on the motherboard.

RC55

RC55 130_0402_5%

130_0402_5%

+VCCP

RC56

RC56 75_0402_5%

75_0402_5%

VIDALERT#

VIDSCLK VIDSOUT

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID QUIET

2010/04/26 2011/10/18

A A

IVY-BRIDGE_BGA1023

SA00004SX00

Security Classification

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENT IAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, IN C. AND CONTAINS CONFIDENT IAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

H_CPU_SVIDCLK

B43

H_CPU_SVIDDAT

C44

VCCSENSE_R

F43

VSSSENSE_R

G43

VCCIO_SENSE_R

AN16 AN17

RC61 0_0402_5%RC61 0_0402_5%

1 2

RC62 0_0402_5%RC62 0_0402_5%

1 2

RC63

1 2

10_0402_1%

RC65 0_0402_5%RC65 0_0402_5%

1 2

10_0402_1%

10_0402_1% RC66

RC66

SD034100A80

Compal Secret Data

Deciphered Date

H_CPU_SVIDALRT#

A44

RC57 43_0402_1%RC57 43_0402_1%

1 2

RC58 0_0402_5%RC58 0_0402_5%

1 2

RC59 0_0402_5%RC59 0_0402_5%

1 2

RC60 100_0402_1%RC60 100_0402_1%

+VCCP

VCCIO_SENSE {39}

VR_SVID_ALRT# {43} VR_SVID_CLK {43} VR_SVID_DATA {43}

+CPU_CORE

1 2

Title

Size Document Number Rev

Custom

Date: Sheet

Place the PU resistors close to CPU

VCCSENSE {43}

VSSSENSE {43}

RC64

RC64 100_0402_1%

100_0402_1%

Place the PU resistors close to VR

Compal Electronics, Inc.

PROCESSOR(5/7) PWR,BYPASS

LA-8101P

0.1

846Monday, November 14, 2011

0.1

+1.5V_CPU_VDDQ +1.5V

CC74 0.1U_0402_10V7KCC74 0.1U_0402_10V7K

D D

Can connect to GND if motherboard only

ɄɄɄɄ

supports external graphics and if GFX VR is not stuffed in a common motherboard design,

ɄɄɄɄ

VAXG can be left floating in a common motherboard desig n (Gfx VR keeps VAXG from floating) if the VR is stuffed

C C

B B

A A

CC75 0.1U_0402_10V7KCC75 0.1U_0402_10V7K

VCC_AXG_SENSE{43} VSS_AXG_SENSE{43}

+1.8VS

0_0805_5%

1 2

+VCCSA

RC77

CC120

330U_D2_2VM_R6M

1U_0402_6.3V6K

+VCCSA

+VGFX_CORE

+1.8VS_VCCPLL

CC121

1U_0402_6.3V6K

CC122

26A

AA46 AB47 AB50 AB51 AB52 AB53 AB55 AB56 AB58 AB59 AC61 AD47 AD48 AD50 AD51 AD52 AD53 AD55 AD56 AD58 AD59 AE46

UCPU1G

VAXG[1] VAXG[2] VAXG[3] VAXG[4] VAXG[5] VAXG[6] VAXG[7] VAXG[8] VAXG[9] VAXG[10] VAXG[11] VAXG[12] VAXG[13] VAXG[14] VAXG[15] VAXG[16] VAXG[17] VAXG[18] VAXG[19] VAXG[20] VAXG[21] VAXG[22]

N45

VAXG[23]

P47

VAXG[24]

P48

VAXG[25]

P50

VAXG[26]

P51

VAXG[27]

P52

VAXG[28]

P53

VAXG[29]

P55

VAXG[30]

P56

VAXG[31]

P61

VAXG[32]

T48

VAXG[33]

T58

VAXG[34]

T59

VAXG[35]

T61

VAXG[36]

U46

VAXG[37]

V47

VAXG[38]

V48

VAXG[39]

V50

VAXG[40]

V51

VAXG[41]

V52

VAXG[42]

V53

VAXG[43]

V55

VAXG[44]

V56

VAXG[45]

V58

VAXG[46]

V59

VAXG[47]

W50

VAXG[48]

W51

VAXG[49]

W52

VAXG[50]

W53

VAXG[51]

W55

VAXG[52]

W56

VAXG[53]

W61

VAXG[54]

Y48

VAXG[55]

Y61

VAXG[56]

F45

VAXG_SENSE

G45

VSSAXG_SENSE

BB3

VCCPLL[1]

BC1

VCCPLL[2]

BC4

VCCPLL[3]

L17

VCCSA[1]

L21

VCCSA[2]

N16

VCCSA[3]

N20

VCCSA[4]

N22

VCCSA[5]

P17

VCCSA[6]

P20

VCCSA[7]

R16

VCCSA[8]

R18

VCCSA[9]

R21

VCCSA[10]

U15

VCCSA[11]

V16

VCCSA[12]

V17

VCCSA[13]

V18

VCCSA[14]

V21

VCCSA[15]

W20

VCCSA[16]

IVY-BRIDGE_BGA1023

SA00004SX00

POWER

AY43

SM_VREF

SA_DIMM_VREFDQ SB_DIMM_VREFDQ

VREF

VDDQ[10] VDDQ[11] VDDQ[12] VDDQ[13] VDDQ[14] VDDQ[15] VDDQ[16] VDDQ[17] VDDQ[18]

DDR3 - 1.5V RAILS

VDDQ[19] VDDQ[20] VDDQ[21] VDDQ[22]

QUIET RAILS

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

SENSE LINES

VCCSA_VID[0]

VCCSA_VID[1]

VCCSA VID

lines

VCCSA VID

lines

VDDQ[23] VDDQ[24] VDDQ[25] VDDQ[26]

VCCDQ[1] VCCDQ[2]

GRAPHICS

SENSE

LINES

SENSE

LINES

1.8V RAIL

SA RAIL

VID[0] VID[1] 2011 2012 0 0 0.90 V Yes Yes 0 1 0.80 V Yes Yes 1 0 0.725 V No Yes 1 1 0.675 V No Yes

VDDQ[1] VDDQ[2] VDDQ[3] VDDQ[4] VDDQ[5] VDDQ[6] VDDQ[7] VDDQ[8] VDDQ[9]

+V_DDR_REFA_R

BE7

+V_DDR_REFB_R

BG7

AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

CPU1.5V_S3_GATE{28}

AM28 AN26

BC43 BA43

VCCSA_SENSE

U10

D48 D49

+V_SM_VREF should

+1.5V_CPU_VDDQ

+V_SM_VREF_CNT +V_SM_VREF

QC9

RC118

1U_0402_6.3V6K

CC87

RC74

0_0402_5%

RC75

@RC75

1K_0402_1%

1U_0402_6.3V6K

CC88

VCCSA_VID0 {38} VCCSA_VID1 {38}

BSS138_NL_SOT23-3

RC117

BSS138_NL_SOT23-3

1U_0402_6.3V6K

CC89

CC90

+3VALW

RC72

RC72 100K_0402_5%

100K_0402_5%

RUN_ON_CPU1.5VS3#

QC5A

SB00000AR10

2N7002DWH_SOT363-6

1U_0402_6.3V6K

DRAMRST_CNTRL_PCH{6,13}

CC85

SUSP#{28,31,39,40,41}

1U_0402_6.3V6K

1 2

CC119

RC790_0402_5% RC790_0402_5%

1 2 1 2

RC80 0_0402_5%RC80 0_0402_5%

1U_0402_6.3V6K

RC78 0_0402_5%@ RC78 0_0402_5%@

1U_0402_6.3V6K

CC86

+1.5V_CPU_VDDQ

1 2

VCCSA_VID0 VCCSA_VID1

1K_0402_1%

1 2

0_0402_5%

1 2

RC76

RC76 0_0603_5%

0_0603_5%

+VREF0

RC1150_0402_5%~D @ RC1150_0402_5%~D @

RC1160_0402_5%~D @ RC1160_0402_5%~D @

QC10

1U_0402_6.3V6K

CC91

CC92

+VSB

CC101

RUN_ON_CPU1.5VS3# {5}

have 20 mil trace width

RC67

0_0402_5%

RC85

RC85 1K_0402_1%

1K_0402_1%

RC89

RC89 1K_0402_1%

1K_0402_1%

RUN_ON_CPU1.5VS3

DRAMRST_CNTRL_PCH

1U_0402_6.3V6K

+1.5V +1.5V_CPU_VDDQ

RC70

RC70 100K_0402_5%

100K_0402_5%

RUN_ON_CPU1.5VS3

SB00000AR10

2N7002DWH_SOT363-6

2N7002DWH_SOT363-6 QC5B

QC5B

QC3

@ QC3

AP2302GN-HF_SOT23-3

+VREFB

1U_0402_6.3V6K

10U_0603_6.3V6M

CC103

AON7212L_DFN8-5

RC73

QC4

CC93

10U_0603_6.3V6M

CC94

CC118

0.1U_0402_16V4Z

10U_0603_6.3V6M

CC102

+1.5V_CPU_VDDQ Source

330K_0402_5%

Follow DG 0.71 page 6

10U_0603_6.3V6M

CC95

1 2 3

10U_0603_6.3V6M

CC96

+1.5V

RC68

RC68 1K_0402_1%

1K_0402_1%

RC69

RC69 1K_0402_1%

1K_0402_1%

+1.5V_CPU_VDDQ

10U_0603_6.3V6M

CC98

CC97

RC71

RC71 470_0603_5%

470_0603_5%

1 2

QC6

RUN_ON_CPU1.5VS3#

SB570020110

2N7002E-T1-E3_SOT23-3

10U_0603_6.3V6M

CC100

CC99

330U_D2_2V_Y

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

2010/04/26 2011/10/18

Compal Secret Dat a

Deciphered D ate

Compal Electronics, Inc.

Title

PROCESSOR(6/7) PWR

Size Document Number Rev

Date: Sheet

LA-8101P

946M onday, November 14, 2011

0.1

UCPU1H

A13

VSS[1]

A17

VSS[2]

A21

VSS[3]

A25

VSS[4]

AA1 AA13 AA50 AA51 AA52 AA53 AA55 AA56

AA8 AB16 AB18 AB21 AB48 AB61 AC10 AC14 AC46

AC6 AD17 AD20

AD4 AD61 AE13

AE8

AF1 AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58 AF59 AG10 AG14 AG18 AG47 AG52 AG61

AG7

AH4 AH58

AJ13 AJ16 AJ20 AJ22 AJ26 AJ30 AJ34 AJ38 AJ42 AJ45 AJ48

AK1 AK52 AL10 AL13 AL17 AL21 AL25 AL28 AL33 AL36 AL40 AL43 AL47 AL61

AM13 AM20 AM22 AM26 AM30 AM34

A28

VSS[5]

A33

VSS[6]

A37

VSS[7]

A40

VSS[8]

A45

VSS[9]

A49

VSS[10]

A53

VSS[11]

VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69]

AJ7

VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90]

VSS

D D

C C

B B

A A

VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]

VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180]

AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13

UCPU1I

BG17 BG21 BG24 BG28 BG37 BG41 BG45 BG49 BG53

BG9

C29 C35 C40 D10 D14 D18 D22 D26 D29 D35

D4 D40 D43 D46 D50 D54 D58

D6 E25 E29

E3 E35 E40 F13 F15 F19 F29 F35 F40 F55 G51

G6 G61 H10 H14 H17 H21

H4 H53 H58

J1 J49 J55

K11 K21 K51

K8 L16 L20 L22 L26 L30 L34 L38 L43 L48 L61

M11 M15

VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249]

IVY-BRIDGE_BGA1023

SA00004SX00

VSS

VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300]

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11

NCTF

VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14

M4 M58 M6 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P14 P16 P18 P21 P58 P59 P9 R17 R20 R4 R46 T1 T47 T50 T51 T52 T53 T55 T56 U13 U8 V20 V61 W13 W15 W18 W21 W46 W8 Y4 Y47 Y58 Y59

A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61

IVY-BRIDGE_BGA1023

SA00004SX00

Security Classification

2010/04/26 2011/10/18

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIO N OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIO N OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/04/26 2011/10/18

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

PROCESSOR(7/7) VSS

LA-8101P

0.1

10 46Monday, November 14, 2011

DDR_A_MA[0..15]{6}

DDR_A_DQS#[0..7]{6}

DDR_A_DQS[0..7]{6}

DDR_A_D[0..63]{6}

D D

C C

DDR_A_MA[0..15]

DDR_A_DQS#[0..7]

DDR_A_DQS[0..7]

DDR_A_D[0..63]

+VREF0 +VREF1

CD1

CD2

0.1U_0402_16V4Z

DDR_A_BS0{6} DDR_A_BS1{6} DDR_A_BS2{6}

M_CLK_DDR0{6}

M_CLK_DDR#0{6}

DDR_CKE0_DIMMA{6}

DDR_CS0_DIMMA#{6}

DDR_A_RAS#{6} DDR_A_CAS#{6}

DDR_A_WE#{6}

DDR3_DRAMRST#{6 }

M_ODT0{6}

0.1U_0402_16V4Z

DDR_CKE0_DIMMA

DDR_CS0_DIMMA#

DDR_A_DQS0 DDR_A_DQS1

DDR_A_DM0 DDR_A_DM1

DDR_A_DQS#0 DDR_A_DQS#1

DDR3_DRAMRST#

DDR_A_MA15

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

M_CLK_DDR0

M_CLK_DDR#0

M_ODT0

DDR_A_RAS# DDR_A_CAS#

DDR_A_WE#

1 2

M9 H2

N4 P8 P4 N3 P9 P3 R9 R3 T9 R4 L8 R8 N8 T4 T8

M3 N9 M4

J8 K8

K10

K2 L3 J4 K4 L4

F4 C8

E8 D4

G4 B8

R225240_0402_1% R225240_0402_1%

L2 J10 L10

UD1

DQL0

VREFCA

DQL1

VREFDQ

DQL2 DQL3

DQL4

A1 A2

DQL5

DQL6

DQL7 A5 A6 A7

DQU0

DQU1

DQU2

A10/AP

DQU3

A11

DQU4

A12/BC

DQU5 DQU6

A13

DQU7

A14

BA0

VDD

BA1

VDD VDD

BA2

VDD VDD VDD

VDD

CKE

VDD

VDDQ

ODT CS

VDDQ

RAS

VDDQ

CAS

VDDQ

VDDQ VDDQ VDDQ

DQSL

VDDQ

DQSU

VDDQ

VSS

DML

VSS

DMU

VSS VSS

DQSL

VSS

DQSU

VSS VSS VSS VSS

RESET

VSS VSS

VSS

VSSQ

VSSQ VSSQ

VSSQ VSSQ VSSQ

96-BALL

96-BALL SDRAM DDR3L

SDRAM DDR3L

H5TC4G63MFR-PBA_FBGA96

+VREF0

+VREF1

DDR_A_D6

DDR_A_D1

DDR_A_D7

DDR_A_D2

DDR_A_D5

DDR_A_D4

DDR_A_D3

DDR_A_D0

DDR_A_D15

DDR_A_D12

DDR_A_D14

DDR_A_D8

DDR_A_D10

DDR_A_D13

DDR_A_D11

DDR_A_D9

+1.5V +1.5V+1.5V D10 G8 K3 K9 N2 N10 R2 R10

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

B2 B10 D2 D9 E3 E9 F10 G2 G10

CD3

0.1U_0402_16V4Z

CD4

0.1U_0402_16V4Z

DDR_A_DQS2

DDR_A_DM2

DDR_A_DM3

DDR_A_DQS#2 DDR_A_DQS#3

DDR3_DRAMRST#

DDR_A_MA15

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

M_CLK_DDR0 M_CLK_DDR#0 DDR_CKE0_DIMMA

M_ODT0 DDR_CS0_DIMMA# DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

1 2

240_0402_1%

M9 H2

N4 P8 P4 N3 P9 P3 R9 R3 T9 R4

L8 R8 N8 T4 T8

M3 N9 M4

J8 K8

K10

J4 K4

F4 C8

E8 D4

G4 B8

RD1

J10 L10

UD2

DQL0

VREFCA

DQL1

VREFDQ

DQL2 DQL3

DQL4

A1 A2

DQL5

DQL6

DQL7 A5 A6 A7

DQU0

DQU1

DQU2

A10/AP

DQU3

A11

DQU4

A12/BC

DQU5 DQU6

A13

DQU7

A14

BA0

VDD

BA1

VDD VDD

BA2

VDD VDD VDD

VDD

CKE

VDD

VDDQ

ODT CS

VDDQ

RAS

VDDQ

CAS

VDDQ

VDDQ VDDQ VDDQ

DQSL

VDDQ

DQSU

VDDQ

VSS

DML

VSS

DMU

VSS VSS

DQSL

VSS

DQSU

VSS VSS VSS VSS

RESET

VSS VSS

VSS

VSSQ

VSSQ VSSQ

VSSQ VSSQ VSSQ

96-BALL

96-BALL SDRAM DDR3L

SDRAM DDR3L

H5TC4G63MFR-PBA_FBGA96

DDR_A_D19

DDR_A_D17

DDR_A_D18

DDR_A_D23

DDR_A_D21

DDR_A_D20

DDR_A_D22

DDR_A_D16

DDR_A_D27

DDR_A_D30

DDR_A_D25

DDR_A_D29

DDR_A_D31

DDR_A_D24

DDR_A_D26

DDR_A_D28

+1.5V D10 G8 K3 K9 N2 N10 R2 R10

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

B2 B10 D2 D9 E3 E9 F10 G2 G10

+VREF0

+VREF1 +VREF0 +V REF1

M9 H2

DDR_A_MA0

DDR_A_MA1

CD5

CD6

0.1U_0402_16V4Z

DDR_A_MA2

DDR_A_MA3

DDR_A_MA4

DDR_A_MA5

DDR_A_MA6

DDR_A_MA7

DDR_A_MA8

DDR_A_MA9

DDR_A_MA10

DDR_A_MA11

DDR_A_MA12

DDR_A_MA13

DDR_A_MA14

DDR_A_BS0

DDR_A_BS1

DDR_A_BS2

M_CLK_DDR0

M_CLK_DDR#0

DDR_CKE0_DIMMA

K10

M_ODT0

DDR_CS0_DIMMA#

DDR_A_RAS#

DDR_A_CAS#

DDR_A_WE#

DDR_A_DQS4

DDR_A_DQS5

DDR_A_DM4

DDR_A_DM5

DDR_A_DQS#4

DDR_A_DQS#5

DDR3_DRAMRST#

RD2

1 2

240_0402_1%

L2 J10 L10

DDR_A_MA15 DDR_A_MA15

UD3

DQL0

VREFCA

DQL1

VREFDQ

DQL2 DQL3

DQL4

A1 A2

DQL5

DQL6

DQL7 A5 A6 A7

DQU0 A8

DQU1 A9

DQU2 A10/AP

DQU3 A11

DQU4 A12/BC

DQU5

DQU6

A13

DQU7

A14

BA0

VDD

BA1

VDD VDD

BA2

VDD VDD VDD

VDD

CKE

VDD

VDDQ

ODT CS

VDDQ

RAS

VDDQ

CAS

VDDQ

VDDQ VDDQ VDDQ

DQSL

VDDQ

DQSU

VDDQ

VSS

DML

VSS

DMU

VSS VSS

DQSL

VSS

DQSU

VSS VSS VSS VSS

RESET

VSS VSS

VSS

VSSQ NC

VSSQ

96-BALL

96-BALL SDRAM DDR3L

SDRAM DDR3L

H5TC4G63MFR-PBA_FBGA96

UD4

DDR_A_D39

DDR_A_D34

DDR_A_D35

DDR_A_D38

DDR_A_D32

DDR_A_D37

DDR_A_D36

DDR_A_D33

DDR_A_D47

DDR_A_D41

DDR_A_D43

DDR_A_D44

DDR_A_D42

DDR_A_D45

DDR_A_D46

DDR_A_D40

B3 D10 G8 K3 K9 N2 N10 R2 R10

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

B2 B10 D2 D9 E3 E9 F10 G2 G10

CD7

0.1U_0402_16V4Z

CD8

0.1U_0402_16V4Z

DDR_A_DQS6DDR_A_DQS3 DDR_A_DQS7

DDR_A_DM6 DDR_A_DM7

DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14DDR_A_MA14

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

M_CLK_DDR0 M_CLK_DDR#0 DDR_CKE0_DIMMA

M_ODT0 DDR_CS0_DIMMA# DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

DDR3_DRAMRST#

1 2

240_0402_1%

M9 H2

N4 P8 P4 N3 P9 P3 R9 R3 T9 R4

L8 R8 N8 T4 T8

M3 N9 M4

K10

F4 C8

E8 D4

RD3

J10 L10

UD4

DQL0

VREFCA

DQL1

VREFDQ

DQL2 DQL3

DQL4

A1 A2

DQL5

DQL6

DQL7 A5 A6 A7

DQU0 A8

DQU1 A9

DQU2 A10/AP

DQU3 A11

DQU4 A12/BC

DQU5

DQU6

A13

DQU7

A14

BA0

VDD

BA1

VDD VDD

BA2

VDD VDD VDD

VDD

CKE

VDD

VDDQ

ODT CS

VDDQ

RAS

VDDQ

CAS

VDDQ

VDDQ VDDQ VDDQ

DQSL

VDDQ

DQSU

VDDQ

VSS

DML

VSS

DMU

VSS VSS

DQSL

VSS

DQSU

VSS VSS VSS VSS

RESET

VSS VSS

VSS

VSSQ

VSSQ VSSQ

VSSQ

VSSQ VSSQ

VSSQ VSSQ VSSQ

96-BALL

96-BALL SDRAM DDR3L

SDRAM DDR3L

H5TC4G63MFR-PBA_FBGA96

DDR_A_D54

DDR_A_D49

DDR_A_D55

DDR_A_D51

DDR_A_D53

DDR_A_D48

DDR_A_D50

DDR_A_D52

DDR_A_D59

DDR_A_D56

DDR_A_D58

DDR_A_D57

DDR_A_D63

DDR_A_D61

DDR_A_D62

DDR_A_D60

B3 D10 G8 K3 K9 N2 N10 R2 R10

A2 A9 C2 C10 D3 E10 F2 H3 H10

A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10

B2 B10 D2 D9 E3 E9 F10 G2 G10

B B

+0.75VS

DDR_A_RAS#

4 5

DDR_A_CAS#

3 6

M_ODT0

2 7

36_0804_8P4R_5%

DDR_CKE0_DIMMA

DDR_A_WE# DDR_A_MA10 DDR_CS0_DIMMA# DDR_A_BS2

DDR_A_BS0 DDR_A_MA12 DDR_A_MA0 DDR_A_MA15

DDR_A_MA3 DDR_A_MA1

+1.5V

10U_0603_6.3V6M

CD14

CD15

A A

10U_0603_6.3V6M

CD16

10U_0603_6.3V6M

CD17

10U_0603_6.3V6M

CD18

10U_0603_6.3V6M

CD19

0.1U_0402_16V7K

0.1U_0402_16V7K CD20

CD20

0.1U_0402_16V7K

0.1U_0402_16V7K CD21

CD21

0.1U_0402_16V7K

0.1U_0402_16V7K CD22

CD22

0.1U_0402_16V7K

0.1U_0402_16V7K CD23

CD23

CD24

CD24 330U_B2_2.5VM_R15M

330U_B2_2.5VM_R15M

SGA00004400

+0.75VS

CD25

1U_0402_6.3V6K

CD26

1U_0402_6.3V6K

CD27

CD28

1U_0402_6.3V6K

CD29

1U_0402_6.3V6K

CD30

10U_0603_6.3V6M

CD30

10U_0603_6.3V6M

CD31

10U_0603_6.3V6M

CD31

10U_0603_6.3V6M

DDR_A_MA2 DDR_A_MA4

DDR_A_MA5 DDR_A_MA11 DDR_A_MA9 DDR_A_MA14

DDR_A_MA13 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8

DDR_A_BS1

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

36_0804_8P4R_5%

1 8

RPD1

4 5 3 6 2 7

36_0804_8P4R_5%

1 8

RPD2

4 5 3 6 2 7

36_0804_8P4R_5%

1 8

RPD3

4 5 3 6 2 7

36_0804_8P4R_5%

1 8

RPD4

4 5 3 6 2 7

36_0804_8P4R_5%

1 8

RPD5

4 5 3 6 2 7

36_0804_8P4R_5%

1 8

RPD6

RPD7

1 4

36_0404_4P2R_5%

2 3

RD11 0_0402_5%RD11 0_0402_5%

1 2

RD10 0_0402_5%RD10 0_0402_5%

1 2

RD12 0_0402_5%RD12 0_0402_5%

1 2

RD13 0_0402_5%RD13 0_0402_5%

1 2

RD14 0_0402_5%RD14 0_0402_5%

1 2

RD15 0_0402_5%RD15 0_0402_5%

1 2

RD16 0_0402_5%RD16 0_0402_5%

1 2

RD17 0_0402_5%RD17 0_0402_5%

1 2

1U_0402_6.3V6K

CD9

CD10

1U_0402_6.3V6K

CD10

1U_0402_6.3V6K

CD11

1U_0402_6.3V6K

CD11

1U_0402_6.3V6K

CD12

M_CLK_DDR0

CD37

1.8P_0402_50V8

M_CLK_DDR#0

LA-8441P

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RD18

30.1_0402_1%

RD19

30.1_0402_1%

CD38

0.1U_0402_16V4Z

2010/04/26 2011/10/18

1K_0402_1%

Compal Secret Dat a

Decipher ed Date

+1.5V +1.5V

RD4

RD4 1K_0402_1%

1K_0402_1%

+VREF0 +VREF1

2.2U_0603_6.3V6K

CD32

0.1U_0402_16V4Z

CD32

0.1U_0402_16V4Z

CD33

RD8

1K_0402_1%

RD5

RD5 1K_0402_1%

1K_0402_1%

+VREF1+VREF0

2.2U_0603_6.3V6K

CD34

0.1U_0402_16V4Z

CD34

0.1U_0402_16V4Z

CD35

RD9

Title

DDRIII ON BOARD CHIPS

Size Document Number Rev

Date: Sheet

11 46Monday, November 1 4, 2011

0.1

PCH_RTCX1

1 2

RH115 10M_0402_5%RH115 10M_0402_5%

18P_0402_50V8J

CH2

OSC4OSC

YH1

D D

C C

B B

YH1

far away hot spot

HDA_BITCLK_AUDIO{30}

HDA_RST_AUDIO#{30}

HDA_SYNC_AUDIO{30}

ME_EN{28}

HDA_SDOUT_AUDIO{30}

+3V_PCH +3V_PCH+3V_PCH

RH127

@RH127

200_0402_5%

PCH_JTAG_TDO PCH_JTAG_TDIPCH_JTAG_TMS

RH133

100_0402_1%

22P_0402_50V8J

NC3NC

CH1

PCH_RTCX2

32.768KHZ_12.5PF_Q13MC14610002

CH3

CH3 18P_0402_50V8J

18P_0402_50V8J

1 2

RH119 33_0402_5%RH119 33_0402_5%

1 2

RH120 33_0402_5%RH120 33_0402_5%

1 2

RH121

33_0402_5%

RH13

1M_0402_5%

1 2

RH123 0_0402_5%RH123 0_0402_5%

1 2

RH125 33_0402_5%RH125 33_0402_5%

RH128

@RH128

200_0402_5%

RH134

RH134 100_0402_1%

100_0402_1%

RH15051_0402_5% RH15051_0402_5%

RH151

1 2

33_0402_5%

+RTCVCC

HDA_BIT_CLK

HDA_RST#

HDA_SYNC_R

PCH_JTAG_TCK

PCH_SPI_CLK

+RTCVCC

1U_0603_10V4Z

1 2

RH117 20K_0402_5%RH117 20K_0402_5%

1 2

RH118 20K_0402_5%RH118 20K_0402_5%

1U_0603_10V4Z

SB000002X00

BSS138W-7-F_SOT323-3

RH122 0_0402_5%@RH122 0_0402_5%@

HDA_SDOUT

RH129

@RH129

200_0402_5%

RH135

100_0402_1%

RH116

CH4

CH5

QH1

1 2

NFC_EN_1V8{27}

1 2

1M_0402_5%

CMOS

CLRP1

SHORT PADS

CLRP2

SHORT PADS

ME CMOS

CLP1 & CLP2 place near DIMM

+5VS

HDA_SYNC

SM_INTRUDER#

HDA_SPKR{30}

HDA_SDIN0{30}

+3VS

10K_0402_5%

10K_0402_5% RH148

RH148

1 2

RH158 0_0402_5%RH158 0_0402_5%

PCH_RTCX1

PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BIT_CLK

HDA_SYNC

HDA_SPKR

HDA_RST#

HDA_SDIN0

HDA_SDOUT

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_SPI_CLK

PCH_SPI_CS#

PCH_SPI_SI

PCH_SPI_SO

Reserve for EMI please close to U48

UH1A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTR UDER #

PCH_GPIO33

C17

INTVR MEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CLK

Y14

SPI_CS0#

SPI_CS1#

SPI_MOSI

SPI_MISO

PANTHER-POINT _FCBGA989

Part Number = SA00004NQ20

RTCIHDA

JTAG

SPI

SPI ROM FOR ME ( 4MByte )

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

LPC

FWH4 / LFR AME#

LDRQ0#

LDRQ1# / GPIO23

SERIRQ

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP

SATA 6G

SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

SATA0GP / GPIO21

SATA1GP / GPIO19

C38 A38 B37 C37

D36

E36 K36

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11

Y10

AB12

AB13

AH1

V14

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

LPC_FRAME#

SERIRQ

SATA_COMP

SATA3_COMP

RBIAS_SATA3

SATA_LED#

PCH_GPIO21

BBS_BIT0_R

LPC_AD0 {28} LPC_AD1 {28} LPC_AD2 {28} LPC_AD3 {28}

LPC_FRAME# {28}

SERIRQ {28}

SATA_PRX_DTX_N0 {26} SATA_PRX_DTX_P0 {26} SATA_PTX_DRX_N0 {26} SATA_PTX_DRX_P0 {26}

SATA_PRX_DTX_N1 {29} SATA_PRX_DTX_P1 {29} SATA_PTX_DRX_N1 {29} SATA_PTX_DRX_P1 {29}

1 2

RH130 37.4_0402_1%RH130 37.4_0402_1%

1 2

RH132 49.9_0402_1%RH132 49.9_0402_1%

1 2

RH137 750_0402_1%RH137 750_0402_1%

T39T39

T35 PAD~D@ T35 PAD~D@

iSSD

mSATA

+1.05VS_VCC_SATA

+1.05VS_SATA3

HDA_SDO

ME debug mode , this signal has a weak internal PD

L=>security measures defined in the Flash Descriptor will be in effect (default)

H=>Flash Descriptor Security will be overridden

PCH_INTVRMEN

RH124 330K_0402_5%RH124 330K_0402_5%

PCH_INTVRMEN

RH126 330K_0402_5%@RH126 330K_0402_5%@

INTVRMEN

H烉Integrated VRM enable

烉

Integrated VRM disable

PCH_GPIO19

BBS_BIT0_R

RH16 10K_0402_5%RH16 10K_0402_5%

SERIRQ

RH131 10K_0402_5%RH131 10K_0402_5%

PCH_GPIO21

RH136 10K_0402_5%RH136 10K_0402_5%

SATA_LED#

RH138 10K_0402_5%RH138 10K_0402_5%

HDA_SPKR

RH139 1K_0402_5%@RH139 1K_0402_5%@

LOW=Default HIGH=No Reboot

HDA_SDOUT

RH140 1K_0402_5%@RH140 1K_0402_5%@

Low = Disabled

High = Enabled

+RTCVCC

+3VS

+3V_PCH

RH141

@ RH141

3.3K_0402_5%

1 2

0_0402_5%

0_0402_5% RH142

PCH_SPI_SO PCH_SPI_SO_R

+3V_PCH

RH142

RH143 33_0402_5%RH143 33_0402_5%

1 2

RH145 3.3K_0402_5%RH145 3.3K_0402_5%

SPI BIOS Pinout

A A

(1)CS# (5)DIO (2)DO (6)CLK (3)WP# (7)HOLD# (4)GND (8)VCC

SPI ROM FOR ME ( 4MByte )

UH2

PCH_SPI_CS#_RPCH_SPI_CS#

PCH_SPI_WP#

UH2

CS#

WP#

GND

W25Q32BVSSIG_SO 8

PCB Footprint = W 25Q32BVSSIG_SO8

HOLD#

+3V_PCH

VCC

PCH_SPI_HOLD#

PCH_SPI_CLK_R

CLK

RH146 33_0402_5%RH146 33_0402_5%

1 2

RH144 3.3K_0402_5%RH144 3.3K_0402_5%

PCH_SPI_CLK

PCH_SPI_SIPCH_SPI_SI_R

RH14733_0402_5% RH14733_0402_5%

CH6

0.1U_0402_16V4Z

+RTCVCC

1 2

R171 0_0402_5%R171 0_0402_5%

W=20mils

Delete RTC Battery add 0ohm

+3VLP

HDA_SYNC

This signal has a weak internal pull-down On Die PLL VR is supplied by

1.5V when smapled high

1.8V when sampled low Needs to be pulled High for Huron River platfrom

HDA_SYNC

RH149 1K_0402_5%RH149 1K_0402_5%

+3V_PCH

W25X32

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPR IETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPR IETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHO RIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/07/06 2011/10/18

Compal Secret Dat a

Deciph ered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PCH (1/8) SATA,HDA,SPI, LPC

LA-8441P

12 46Monday, November 14, 2011

0.1

XTAL25_IN

XTAL25_OUT

PCIE_PRX_DTX_N1{25} PCIE_PRX_DTX_P1{25}

PCIE_PTX_C_DRX_N1{25}

PCIE_PTX_C_DRX_P1{25}

PCIE_PRX_DTX_N2{22}

PCIE_PRX_DTX_P2{22} PCIE_PTX_C_DRX_N2{22} PCIE_PTX_C_DRX_P2{22}

CLK_PCIE_MINI1#{22} CLK_PCIE_MINI1{22}

MINI1_CLKREQ#{22}

CLK_RES_ITP#{7}

CLK_RES_ITP{7}

CH10 0. 1U_0402_10V7KCH10 0.1U_0402_10V7K CH11 0. 1U_0402_10V7KCH11 0.1U_0402_10V7K

CH83 0.1U_0402_10V7KCH83 0.1U_0402_10V7K CH82 0.1U_0402_10V7KCH82 0.1U_0402_10V7K

CLK_PCIE_CD#{25} CLK_PCIE_CD{25}

+3V_PCH

+3VS

+3V_PCH

CLK_PCH_14M

1 2 1 2

RH177 10K_0402_5%RH177 10K_0402_5%

RH178 0_0402_5%RH178 0_0402_5% RH179 0_0402_5%RH179 0_0402_5% RH180 10K_0402_5%RH 180 10K_0402_5%

RH174 10K_0402_5%R H174 10K_0402_5%

RH175 10K_0402_5%R H175 10K_0402_5%

RH181 10K_0402_5%RH 181 10K_0402_5%

RH182 10K_0402_5%RH182 10K_0402_5%

RH183 10K_0402_5%RH183 10K_0402_5%

RH185 10K_0402_5%RH 185 10K_0402_5%

RH189 10K_0402_5%RH189 10K_0402_5%

RH190 0_0402_5%@RH190 0_0402_5%@ RH191 0_0402_5%@RH191 0_0402_5%@

D D

PCIE Card Reader

MiniWLAN --->

C C

Card Reader--->

MiniWLAN (Mini Card)--->

B B

RH1871M_0402_5% RH1871M_0402_5%

YH2

1 2

18P_0402_50V8J

25MHZ_20PF_7A25000012

CH12

CH13

18P_0402_50V8J

Reserve for EMI please close to UH1

CLK_PCI_LPBACK

A A

Reserve for EMI please close to UH1

RH4 0_0402_5%RH4 0_0402_5% RH5 0_0402_5%RH5 0_0402_5%

CDCLK_REQ#{25}

12 12 12

1 2

12 12

RH193

1 2

22P_0402_50V8J

33_0402_5%

RH195

1 2

22P_0402_50V8J

33_0402_5%

PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1

PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2

12 12

PCIE_MINI1# PCIE_MINI1

MINI1CLK_REQ#

GPIO46

CLK_BCLK_ITP# CLK_BCLK_ITP

CH14

CH15

PCIE_CD# PCIE_CD

UH1B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

PANTHER-POINT_FCBGA989

Part Number = SA00004NQ20

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

CLOCKS

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N

CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N

CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / G PIO64

CLKOUTFLEX1 / G PIO65

CLKOUTFLEX2 / G PIO66

CLKOUTFLEX3 / G PIO67

FLEX CLOCKS

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

XTAL25_IN

SMBALERT#

E12

SMBCLK

H14

SMBDATA

DRAMRST_CNTRL_PCH

A12

SML0CLK

SML0DATA

G12

PCH_HOT#

C13

SML1CLK

E14

SML1DATA

M16

T11

P10

PCH_GPIO47

M10

AB37 AB38

AV22

CLK_CPU_DMI_PCH

AU22

AM12 AM13

CLKIN_DMI#

BF18

CLKIN_DMI

BE18

CLKIN_DMI2#

BJ30

CLKIN_DMI2

BG30

CLKIN_DOT96#

G24

CLKIN_DOT96

E24

CLKIN_SATA#

AK7

CLKIN_SATA

AK5

CLK_PCH_14M

K45

CLK_PCI_LPBACK

H45

XTAL25_IN

V47

XTAL25_OUT

V49

XCLK_RCOMP

Y47

K43

F47

H47

DGPU_PRSNT#

K49

RH155 10K_0402_5%RH155 10K_0402_5%

1 2

RH14

DRAMRST_CNTRL_PCH {6,9}

PCH_HOT# {28}

Total device

10K_0402_5%

RH172 0_0402_5%RH172 0_0402_5% RH173 0_0402_5%RH173 0_0402_5%

CLK_PCI_LPBACK {15}

1 2

RH184 90. 9_0402_1%RH184 90.9_0402_1%

1 2

RH18 10K_0402_5%RH18 10K_0402_5%

Pull High to UMA Mode

+3VS

PCH_I2C2_SMBA

0_0402_5%

20090512 add double mosfet prevent ATI M92 electric leakage

RH8

+3V_PCH

CLK_CPU_DMI#CLK_CPU_DMI#_PCH

CLK_CPU_DMI

+1.05VS_VCCDIFFCLKN

+3VS

PCH_I2C2_SMBA {21}

CLK_CPU_DMI# {5} CLK_CPU_DMI {5}

SB00000AR10

2N7002DWH_SOT363-6

SML1CLK

SML1DATA

SB00000AR10

2N7002DWH_SOT363-6

SMBCLK

SMBDATA

+3V_PCH

PCH_HOT#

SMBDATA

SMBCLK

SML0CLK

SML0DATA

SML1CLK

SML1DATA

DRAMRST_CNTRL_PCH

CLKIN_DMI2# CLKIN_DMI2 CLKIN_DMI# CLKIN_DMI CLKIN_DOT96# CLKIN_DOT96 CLKIN_SATA# CLKIN_SATA CLK_PCH_14M

If use extenal CLK gen, please place close to CLK gen else, please place close to PCH

6 1

QH3A

RH200

1 2

0_0402_5%

2N7002DWH_SOT363-6

6 1

QH2A

RH192

1 2

0_0402_5%

2N7002DWH_SOT363-6

1 2

RH19 10K_0402_5%RH19 10K_0402_5%

1 2

RH152 2. 2K_0402_5%RH152 2.2K_0402_5%

1 2

RH153 2. 2K_0402_5%RH153 2.2K_0402_5%

1 2

RH156 2. 2K_0402_5%RH156 2.2K_0402_5%

1 2

RH157 2. 2K_0402_5%RH157 2.2K_0402_5%

1 2

RH159 2. 2K_0402_5%RH159 2.2K_0402_5%

1 2

RH160 2. 2K_0402_5%RH160 2.2K_0402_5%

1 2

RH161 10K_0402_5%R H161 10K_0402_5%

RH162 10K_0402_5%RH162 10K_0402_5% RH163 10K_0402_5%RH163 10K_0402_5% RH164 10K_0402_5%RH164 10K_0402_5% RH165 10K_0402_5%RH165 10K_0402_5% RH166 10K_0402_5%RH166 10K_0402_5% RH167 10K_0402_5%RH167 10K_0402_5% RH168 10K_0402_5%RH168 10K_0402_5% RH169 10K_0402_5%RH169 10K_0402_5% RH170 10K_0402_5%RH170 10K_0402_5%

+3VS +3VS

2.2K_0402_5%

@RH200

3 4

QH3B

RH232

1 2

0_0402_5%

+3VS

2.2K_0402_5%

@RH192

3 4

QH2B

RH194

1 2

0_0402_5%

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

RH208

RH186

+3VS

1 2

RH198

2.2K_0402_5%

1 2

RH188

2.2K_0402_5%

1 2

PCH_SML1CLK {28}

PCH_SML1DATA {28}

PCH_SMBCLK {21,22,27}

PCH_SMBDATA {21,22,27}

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

2010/07/06 2011/10/18

Compal Secret Dat a

Deciphered D ate

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PCH (2/8) PCIE, SMBUS, CLK

LA-8441P

13 46Monday, November 14, 2011

0.1

UH1C

DMI_CTX_PRX_N0{4} DMI_CTX_PRX_N1{4} DMI_CTX_PRX_N2{4}

D D

For Deep S3

C C

B B

A A

PCH_PWROK{28}

SYS_PWROK{5}

PCH_APWROK

PCH_RSMRST#{28}

SUSWARN#{28}

PCH_GPIO72

RI#

WAKE#

ACIN_R

SUSWARN#_R

PCH_RSMRST#

DMI_CTX_PRX_N3{4}

DMI_CTX_PRX_P0{4} DMI_CTX_PRX_P1{4} DMI_CTX_PRX_P2{4} DMI_CTX_PRX_P3{4}

DMI_CRX_PTX_N0{4} DMI_CRX_PTX_N1{4} DMI_CRX_PTX_N2{4} DMI_CRX_PTX_N3{4}

DMI_CRX_PTX_P0{4} DMI_CRX_PTX_P1{4} DMI_CRX_PTX_P2{4} DMI_CRX_PTX_P3{4}

+VCCP

4mil width and place within 500mil of the PCH

RH273

SUSACK#{28}

XDP_DBRESET#{5}

PCH_PWROK

RH273

SYS_PWROK

RH203 0_0402_5%RH203 0_0402_5%

1 2

RH204 0_0402_5%@RH204 0_0402_5%@

PM_DRAM_PWRGD{5}

PCH_RSMRST# PCH_RSMRST#_R

PBTN_OUT#{28}

RH210 10K_0402_5%RH210 10K_0402_5%

RH211 10K_0402_5%RH211 10K_0402_5%

RH212 1K_0402_5%RH212 1K_0402_5%

RH279 0_0402_5%RH279 0_0402_5%

ACIN{28,37}

SCS00000Z00

RB751V-40_SOD323-2

1 2

RH214 200K_0402_5%RH214 200K_0402_5%

1 2

RH216 10K_0402_5%RH 216 10K_0402_5%

1 2

RH217 10K_0402_5%RH 217 10K_0402_5%

1 2

PCH_PWROK

VGATE{43}

RH223 10K_0402_5%RH223 10K_0402_5%

RH196 49.9_0402_1%RH196 49.9_0402_1%

RH197 750_0402_1%RH197 750_0402_1%

1 2

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

1 2

SUSACK#_R

0_0402_5%~D

XDP_DBRESET#

1 2

PM_DRAM_PWRGD

1 2

SUSWARN#_R

1 2

DH2

1 2

PCH_GPIO72

+3V_PCH

+3VS

VCC

IN1

OUT

IN2

GND

MC74VHC1G08DFT2G_SC70-5

DMI_IRCOMP

RBIAS_CPY

PCH_APWROK_R

UH3

1 2

RH202 0_0402_5%RH202 0_0402_5%

RH11 0_0402_5%RH11 0_0402_5%

1 2

RH206 0_0402_5%RH206 0_0402_5%

1 2

RH209 0_0402_5%RH209 0_0402_5%

PM_PWROK_R

PBTN_OUT#_R

ACIN_R

RI#

SYS_PWROK

UH1C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

PANTHER-POINT_FCBGA989

Part Number = SA00004NQ20

DSWODVREN

DSWODVREN - On Die DSW VR Enable

H烉Enable

烉

Disable

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6

DMI

FDI

DMI

FDI

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

CLKRUN# / GPIO32

SUS_STAT# / GPIO6 1

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

System Power Management

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

Check EC for S3 S4 LED

RH213 330K_0402_5%RH213 330K_0402_5%

RH215 330K_0402_5%

+3VS

RH218 8.2K_0402_5%

RH219 2.2K_0402_5%RH219 2.2K_0402_5%

RH221 2.2K_0402_5%RH221 2.2K_0402_5%

1 2

RH222 2.37K_0402_1%RH222 2.37K_0402_1%

1 2

RH224 100K_0402_5%RH224 100K_0402_5%

1 2

RH225 100K_0402_5%RH225 100K_0402_5%

WAKE#

+RTCVCC

1 2

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16

AV12

BC10

AV14

BB10

A18

E22

N14

D10

G10

G16

AP14

K14

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWODVREN

PCH_DPWROK

WAKE#

PM_CLKRUN#

SUS_STAT#

SUSCLK

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

H_PM_SYNC

LVDS_IBG

PCH_ENVDD

ENBKL

RH199 0_0402_5%@ RH199 0_0402_5%@

1 2

RH201 0_0402_5%RH201 0_0402_5%

RH205 0_0402_5%RH205 0_0402_5%

T19 PAD~DT19 PAD~D

SLP_SUS#

T4 PAD~DT4 PAD~D

PM_CLKRUN#

CTRL_CLK

CTRL_DATA

FDI_CTX_PRX_N0 {4} FDI_CTX_PRX_N1 {4} FDI_CTX_PRX_N2 {4} FDI_CTX_PRX_N3 {4} FDI_CTX_PRX_N4 {4} FDI_CTX_PRX_N5 {4} FDI_CTX_PRX_N6 {4} FDI_CTX_PRX_N7 {4}

FDI_CTX_PRX_P0 {4} FDI_CTX_PRX_P1 {4} FDI_CTX_PRX_P2 {4} FDI_CTX_PRX_P3 {4} FDI_CTX_PRX_P4 {4} FDI_CTX_PRX_P5 {4} FDI_CTX_PRX_P6 {4} FDI_CTX_PRX_P7 {4}

FDI_INT {4}

FDI_FSYNC0 {4}

FDI_FSYNC1 {4}

FDI_LSYNC0 {4}

FDI_LSYNC1 {4}

PCH_DPWROK {28}

T36 PAD~DT36 PAD~D

PM_SLP_S5# {28}

PM_SLP_S4# {28}

PM_SLP_S3# {28}

H_PM_SYNC {5}

PCH_RSMRST#

PCH_PCIE_WAKE# {22}

SUSCLK_R {28}

SLP_SUS# {28}

PM_CLKRUN#

EC Request on 20110309

RH308

RH308 10K_0402_5%

10K_0402_5%

PCH_ENVDD{23}

DPST_PWM{23}

PCH_LCD_CLK{23}

PCH_LCD_DATA{23}

PCH_TXCLK-{23} PCH_TXCLK+{23}

PCH_TXOUT0-{23} PCH_TXOUT1-{23} PCH_TXOUT2-{23}

PCH_TXOUT0+{23} PCH_TXOUT1+{23} PCH_TXOUT2+{23}

ENBKL{28}

PCH_LCD_CLK PCH_LCD_DATA

T37PAD~D T37PAD~D

LVD_VREF

1 2

RH207 0_0402_5%RH207 0_0402_5%

PCH_TXCLKPCH_TXCLK+

PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2-

PCH_TXOUT0+ PCH_TXOUT1+ PCH_TXOUT2+

RH220

1K_0402_0.5%

ENBKL

CTRL_CLK CTRL_DATA

LVDS_IBG

CRT_IREF

UH1D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

PANTHER-POINT_FCBGA989

Part Number = SA00004NQ20

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_AUXN

DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_AUXN

DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_CTRLCLK

SDVO_CTRLDAT A

HDMI

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

mDP

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

CRT

DMC

PCH_HDMI_CLK {20} PCH_HDMI_DAT {20}

PCH_HDMI_HPD {20}

PCH_HDMI_N2 {20} PCH_HDMI_P2 {20} PCH_HDMI_N1 {20} PCH_HDMI_P1 {20} PCH_HDMI_N0 {20} PCH_HDMI_P0 {20} PCH_HDMI_N3 {20} PCH_HDMI_P3 {20}

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRON ICS, INC.

2010/07/06 2011/10/18

Compal Secret Dat a

Deciphered D ate

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PCH (3/8) DMI,FDI,PM,GFX,DP

LA-8441P

14 46Monday, November 14, 2011

0.1

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