Compal LA-6054P NALAE Hamburg 10ADG, Satellite L670, Satellite L670D, Satellite L675, Satellite L675D Schematic

A
1 1
B
C
D
E
Compal confidential
2 2
Hamburg 10ADG
NALAE LA-6054P Schematics Document
Mobile AMD S1G4/ RS880M / SB820M
3 3
2009-02-04 Rev. 0.2
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
401871
401871
401871
152Wednesday, May 19, 2010
152Wednesday, May 19, 2010
152Wednesday, May 19, 2010
E
B
B
B
of
of
of
A
B
C
D
E
Compal Confidential
Model Name : NALAE File Name : LA-6054P
1 1
CRT
page 17
LCD Conn.
page 18
HDMI Conn.
page 19
2 2
Thermal Sensor Fan Control
ADM1032ARMZ
page 7
page 5
Madison & Park
Page 35,36,37,38,39 40,41,42,43
AMD S1G4 CPU
uFCPGA-638 Package
page 5,6,7,8
Hyper Transport Link 2.6GHz
16X16
AMD
RS880M
page 11,12,13,14,15
A-Link Express II
Memory BUS(DDRIII)
Dual Channel
1.5V DDRIII 1066/1333MHZ
PCIe 4x
1.5V 2.5GHz(250MB/s)
200pin DDRIII-SO-DIMM X2
BANK 0, 1, 2, 3
PCIeMini Card WLAN
USB Port 8
RTL 8105E 10/100
PCIe Port 2
page 28
PCIe port 3
page 26
page 9,10
RJ45
page 26
4X PCI-E
SATA port 0
5V 1.5GHz(150MB/s)
AMD
page 28
page 28
Card Reader
USB port 5
page 27
Int. Camera
USB port 9
page 18
USB
5V 480MHz
SB820M
page 20,21,22,23,24
SATA port 1
5V 1.5GHz(150MB/s)
SATA port 3
5V 1.5GHz(150MB/s)
USB port 2
5V 480MHz
USB/B
USB port 0,1
BT conn
USB port 6
3 3
SATA HDD
page 25
SATA ODD
page 25
eSATA
page 25
Clock Generator
3.3V 24.576MHz/48Mhz
SLG8SP626
RTC CKT.
Power On/Off CKT.
DC/DC Interface CKT.
Power Circuit DC/DC
4 4
page 16
page 20
page 33
page 34
page 44,45,46.47 48,49,50,51
ODD/B
page 25
Power/B
page 33
Audio & USB/B
page 33
LED/B
page 33
Touch Pad/B
page 33
Debug Port
page 32
Int.KBD
page 32
LPC BUS
3.3V 33 MHz
ENE KB926 D3
page 31
HD Audio
SPI ROM
page 32
Int.
MIC CONN
page 18
HDA Codec
ALC259Q
MDC 1.5 Conn
page 32 page 29
MIC CONN
page 30
HP CONN
page 30
SPK CONN
page 30
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
401871
401871
401871
252Wednesday, May 19, 2010
252Wednesday, May 19, 2010
252Wednesday, May 19, 2010
E
B
B
B
of
of
of
5
4
3
2
1
DESIGN CURRENT 0.1A
B+
RT8205EGQW
Ipeak = 5A, Imax = 3.5A, Iocp_min = 7.7A
Ipeak = 5A, Imax = 3.5A, Iocp_min = 7.9A
D D
N-CHANNEL
SUSP
DESIGN CURRENT 0.1A
DESIGN CURRENT 5A
DESIGN CURRENT 5A
DESIGN CURRENT 2A
SI4800
SUSP#
MP2121DQ
WOL_EN#
P-CHANNEL
AO3413
N-CHANNEL
SI4800
C C
NALAE Hamburg AMD DIS
POK
RT8209BGQW
Ipeak = 12A, Imax = 8.4A, Iocp_min = 18.7A
VLDT_EN#
N-CHANNEL
SUSP
P-CHANNEL
AO3413
P-CHANNEL
AO3413
APL5508
VGA_ENVDD
BT_PWR#
DESIGN CURRENT 2.5A
DESIGN CURRENT 330mA
DESIGN CURRENT 1.5A
DESIGN CURRENT 1A
DESIGN CURRENT 180mA
DESIGN CURRENT 300mA
DESIGN CURRENT 12A
DESIGN CURRENT 3.5A
IRF8113
N-CHANNEL
VLDT_EN#
DESIGN CURRENT 6A
IRF8113
VR_ON
Ipeak = 36A, Imax = 25.2A, Iocp_min = 54A
B B
ISL6265A
SYSON
Ipeak = 11A, Imax = 7.7A, Iocp_min = 19.16A
RT8209BGQW
A A
APW7138NITRL
SUSP#
Ipeak = 20A, Imax = 14A, Iocp_min = 20.14A
SUSP
N-CHANNEL
IRF8113
VR_ON#
APL5331KAC
SUSP
APL5331KAC
SUSP#
APL5930KAI
DESIGN CURRENT 36A
DESIGN CURRENT 4A
DESIGN CURRENT 11A
DESIGN CURRENT 5A
DESIGN CURRENT 1A
DESIGN CURRENT 1.5A
DESIGN CURRENT 2.5A
DESIGN CURRENT 20A
+CPU_CORE_0
+3VL
+5VL +3VALW +5VALW
+5VS
+1.8VS
+3V_LAN
+3VS
+LCD_VDD
+BT_VCC
+2.5VS
+1.1VALW
+1.1VS
+NB_CORE
+VDDNB
+1.5V
+1.5VS
+0.75VS
+1.05VS
+1.0VS
+VGA_CORE
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
401871
401871
401871
352Wednesday, May 19, 2010
352Wednesday, May 19, 2010
352Wednesday, May 19, 2010
1
B
B
B
of
of
of
A
Voltage Rails
O : ON X : OFF
+5VS
1 1
2 2
S5 S4/ Battery only
S5 S4/AC & Battery don't exist
State
S0
S1
S3
S5 S4/AC
power plane
B+
+3VL +5VL
+RTCVCC
O O O O O
X
+5VALW +3VALW +1.1VALW
O O O O
X XX X
+3VS +2.5VS +1.8VS +1.5VS +1.1VS +1.05VS
+1.5V
+0.75VS +VGA_CORE +VDDNB +CPU_CORE
+NB_CORE
OO OO
O
X XX X
X
B
Symbol Note :
: Digital Ground
: Analog Ground
@ : just reserve , no build
Function
Description (Y)
Explain
BTO
C
GPU
Manhattan
M96/M92
Platform Danube
S1G4 SB820M
BTO (Build-To-Order) Option Table
BLUE TOOTH
( B )
BT@
HDMI
H@
D
RS880M SB820MS1G4 RS880M SB820MS1G4 RS880M SB820MS1G4
NB
RS880M
MADISON
PARK M96 M92
VGA
NA
SB820MRS880MS1G4
Madison@ or PARK@ +4PCS or 8PCS
M9X@+M96@ or M92@ +4PCS or 8PCS
E
CommentCPU SBNB VGA
CommentCPU SB
SMBUS Control Table
I2C / SMBUS ADDRESSING
DEVICE
DDR SO-DIMM 0
3 3
DDR SO-DIMM 1 CLOCK GENERATOR (EXT.)
HEX
A0
D2
EC SM Bus1 address
Device Address Smart Battery HDMI-CEC EC KB926D4
HEX 16H 34H
0001 011X b 0011 010X b
ADDRESS
1 0 1 0 0 0 0 X 1 0 1 0 0 0 1 XA2 1 1 0 1 0 0 1 0
EC SM Bus2 address
Device ADI1032-1 CPU ADI1032-2 VGA EC KB926D3
HEX 98H 9AH
Address
1001 100X b 1001 101X b
EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 I2C_CLK I2C_DATA DDC_CLK0 DDC_DATA0
SCL0 SDA0 SCL1 SDA1
SOURCE
KB926
KB926
RS880M
RS880M
SB820
SB820
BATT
V
CPU THERMAL SENSOR
V
SODIMM
I / II
CLK GEN
VV
WLAN
V
LCD DDC ROM
V
HDMI DDC ROM
V
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
401871
401871
401871
452Wednesday, May 19, 2010
452Wednesday, May 19, 2010
452Wednesday, May 19, 2010
E
B
B
B
of
of
of
A
+1.1VS
250 mil
1
C1
C1 10U_0805_10V4Z
10U_0805_10V4Z
1 1
2
1
C2
C2 10U_0805_10V4Z
10U_0805_10V4Z
2
Near CPU SocketVLDT CAP.
1
C3
C3
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C4
C4
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
B
1
C5
C5 180P_0402_50V8J
180P_0402_50V8J
2
1
C6
C6 180P_0402_50V8J
180P_0402_50V8J
2
C
D
E
VLDT_B0 VLDT_B1 VLDT_B2 VLDT_B3
H_CADOP[0..15] H_CADON[0..15]
+1.1VS
+VLDT_B
AE2 AE3 AE4 AE5
AD1 AC1 AC2 AC3 AB1 AA1 AA2 AA3 W2 W3 V1 U1 U2 U3 T1 R1 AD4 AD3 AD5 AC5 AB4 AB3 AB5 AA5 Y5 W5 V4 V3 V5 U5 T4 T3
Y1 W1 Y4 Y3
R2 R3 T5 R5
1 2
H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7 H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15
H_CADOP[0..15] <11> H_CADON[0..15] <11>H_CADIN[0..15]<11>
C7
C7 10U_0805_10V4Z
10U_0805_10V4Z
< To NB >< From NB >
H_CLKOP0 <11> H_CLKON0 <11> H_CLKOP1 <11> H_CLKON1 <11>
H_CTLOP0 <11> H_CTLON0 <11> H_CTLOP1 <11> H_CTLON1 <11>
< VLDT_A & VLDT_B : HyperTransport I/O ring power >
H_CADIP[0..15]<11>
2 2
H_CLKIP0<11> H_CLKIN0<11> H_CLKIP1<11> H_CLKIN1<11>
H_CTLIP0<11>
3 3
H_CTLIN0<11> H_CTLIP1<11> H_CTLIN1<11>
H_CADIP[0..15] H_CADIN[0..15]
VLDT=500mA
H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7 H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15
+1.1VS
JCPUA
JCPUA
D1
VLDT_A0
D2
VLDT_A1
D3
VLDT_A2
D4
VLDT_A3
E3
L0_CADIN_H0
E2
L0_CADIN_L0
E1
L0_CADIN_H1
F1
L0_CADIN_L1
G3
L0_CADIN_H2
G2
L0_CADIN_L2
G1
L0_CADIN_H3
H1
L0_CADIN_L3
J1
L0_CADIN_H4
K1
L0_CADIN_L4
L3
L0_CADIN_H5
L2
L0_CADIN_L5
L1
L0_CADIN_H6
M1
L0_CADIN_L6
N3
L0_CADIN_H7
N2
L0_CADIN_L7
E5
L0_CADIN_H8
F5
L0_CADIN_L8
F3
L0_CADIN_H9
F4
L0_CADIN_L9
G5
L0_CADIN_H10
H5
L0_CADIN_L10
H3
L0_CADIN_H11
H4
L0_CADIN_L11
K3
L0_CADIN_H12
K4
L0_CADIN_L12
L5
L0_CADIN_H13
M5
L0_CADIN_L13
M3
L0_CADIN_H14
M4
L0_CADIN_L14
N5
L0_CADIN_H15
P5
L0_CADIN_L15
J3
L0_CLKIN_H0
J2
L0_CLKIN_L0
J5
L0_CLKIN_H1
K5
L0_CLKIN_L1
N1
L0_CTLIN_H0
P1
L0_CTLIN_L0
P3
L0_CTLIN_H1
P4
L0_CTLIN_L1
FOX_PZ6382A-284S-41F_Champlian
FOX_PZ6382A-284S-41F_Champlian
HT LINK
HT LINK
L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15
L0_CLKOUT_H0 L0_CLKOUT_L0 L0_CLKOUT_H1 L0_CLKOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
< FAN Control Circuit : Vout = 1.6 x Vset >
+5VS
1A
GND GND GND GND
C1119
C1119
8 7 6 5
2
1
B
2
C1121
C1121
@
@
1000P_0402_25V8J
1000P_0402_25V8J
1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
+FAN1
JFAN
JFAN
1
1
2
2
3
3
4
GND
5
GND
ACES_85204-0300N@
ACES_85204-0300N@
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
+3VS
12
R795
R795 10K_0402_5%
10K_0402_5%
2
C1122
C1122
@
@
0.01U_0402_25V7K
0.01U_0402_25V7K
1
Deciphered Date
Deciphered Date
Deciphered Date
FAN_SPEED1 <30>
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
401871
401871
401871
552Wednesday, May 19, 2010
552Wednesday, May 19, 2010
552Wednesday, May 19, 2010
E
of
of
of
B
B
B
+FAN1
1
C1120
C1120 10U_0805_10V4Z
10U_0805_10V4Z
2
4 4
EN_DFAN1<30>
A
10U_0805_10V4Z
10U_0805_10V4Z
U31
U31
1
EN
2
VIN
3
VOUT
4
VSET
APL5607KI-TRG_SO8
APL5607KI-TRG_SO8
A
< DDR2 VREF is 0.5 ratio >
+1.5V
R1
R1 1K_0402_1%
1K_0402_1%
1 2
R2
R2
1 1
1K_0402_1%
1K_0402_1%
1 2
2 2
+1.5V
< To SO_DIMMA >
< To SO_DIMMA >
< To SO_DIMMA >
< To SO_DIMMA >
< To SO_DIMMA >
3 3
< To SO_DIMMA >
< To SO_DIMMA >
+MCH_REF
1
C9
C9
0.1U_0402_16V7K
0.1U_0402_16V7K
2
Place them close to CPU within 1"
DDR_A_ODT0<9> DDR_A_ODT1<9>
DDR_CS0_DIMMA#<9> DDR_CS1_DIMMA#<9> DDR_CS0_DIMMB# <10>
DDR_CKE0_DIMMA<9> DDR_CKE1_DIMMA<9>
DDR_A_CLK0<9> DDR_A_CLK#0<9>
DDR_A_CLK1<9> DDR_A_CLK#1<9> DDR_A_MA[15..0]<9>
DDR_A_BS#0<9> DDR_A_BS#1<9> DDR_A_BS#2<9>
DDR_A_RAS#<9> DDR_A_CAS#<9> DDR_A_WE#<9>
1
C8
C8 1000P_0402_25V8J
1000P_0402_25V8J
2
R4 39.2_0402_1%R4 39.2_0402_1%
1 2
R5 39.2_0402_1%R5 39.2_0402_1%
1 2
MEM_MA_RST#<9>
JCPUB
JCPUB
D10
VDDR1
MEM:CMD/CTRL/CLK
MEM:CMD/CTRL/CLK
C10
VDDR2
B10
VDDR3
AD10
MEM_P MEM_N VTT_SENSE
MEM_MA_RST#
DDR_A_ODT0 DDR_A_ODT1
DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMB#
DDR_CKE0_DIMMA DDR_CKE1_DIMMA
DDR_A_CLK0 DDR_A_CLK#0
DDR_A_CLK1 DDR_A_CLK#1
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15
DDR_A_BS#0 DDR_A_BS#1 DDR_A_BS#2
DDR_A_RAS# DDR_A_CAS# DDR_A_WE#
VDDR4
AF10
MEMZP
AE10
MEMZN
H16
MA_RESET_L
T19
MA0_ODT0
V22
MA0_ODT1
U21
MA1_ODT0
V19
MA1_ODT1
T20
MA0_CS_L0
U19
MA0_CS_L1
U20
MA1_CS_L0
V20
MA1_CS_L1
J22
MA_CKE0
J20
MA_CKE1
N19
MA_CLK_H5
N20
MA_CLK_L5
E16
MA_CLK_H1
F16
MA_CLK_L1
Y16
MA_CLK_H7
AA16
MA_CLK_L7
P19
MA_CLK_H4
P20
MA_CLK_L4
N21
MA_ADD0
M20
MA_ADD1
N22
MA_ADD2
M19
MA_ADD3
M22
MA_ADD4
L20
MA_ADD5
M24
MA_ADD6
L21
MA_ADD7
L19
MA_ADD8
K22
MA_ADD9
R21
MA_ADD10
L22
MA_ADD11
K20
MA_ADD12
V24
MA_ADD13
K24
MA_ADD14
K19
MA_ADD15
R20
MA_BANK0
R23
MA_BANK1
J21
MA_BANK2
R19
MA_RAS_L
T22
MA_CAS_L
T24
MA_WE_L
FOX_PZ6382A-284S-41F_Champlian
FOX_PZ6382A-284S-41F_Champlian
B
VDDR5 VDDR6 VDDR7 VDDR8 VDDR9
VDDR_SENSE
MEMVREF
MB_RESET_L
MB0_ODT0 MB0_ODT1 MB1_ODT0
MB0_CS_L0 MB0_CS_L1 MB1_CS_L0
MB_CKE0 MB_CKE1
MB_CLK_H5 MB_CLK_L5 MB_CLK_H1 MB_CLK_L1 MB_CLK_H7 MB_CLK_L7 MB_CLK_H4 MB_CLK_L4
MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8
MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15
MB_BANK0 MB_BANK1 MB_BANK2
MB_RAS_L MB_CAS_L
MB_WE_L
+1.05VS+1.05VS
W10 AC10 AB10
< VTT regulator voltage >
AA10 A10
Y10
+MCH_REF
W17
MEM_MB_RST#
B18
DDR_B_ODT0
W26
DDR_B_ODT1
W23 Y26
V26
DDR_CS1_DIMMB#
W25 U22
DDR_CKE0_DIMMB
J25
DDR_CKE1_DIMMB
H26
DDR_B_CLK0
P22
DDR_B_CLK#0
R22 A17 A18 AF18 AF17
DDR_B_CLK1
R26
DDR_B_CLK#1
R25
DDR_B_MA0
P24
DDR_B_MA1
N24
DDR_B_MA2
P26
DDR_B_MA3
N23
DDR_B_MA4
N26
DDR_B_MA5
L23
DDR_B_MA6
N25
DDR_B_MA7
L24
DDR_B_MA8
M26
DDR_B_MA9
K26
DDR_B_MA10
T26
DDR_B_MA11
L26
DDR_B_MA12
L25
DDR_B_MA13
W24
DDR_B_MA14
J23
DDR_B_MA15
J24
DDR_B_BS#0
R24
DDR_B_BS#1
U26
DDR_B_BS#2
J26
DDR_B_RAS#
U25
DDR_B_CAS#
U24
DDR_B_WE#
U23
T1PAD T1PAD
MEM_MB_RST# <10>
DDR_B_ODT0 <10> DDR_B_ODT1 <10>
DDR_CS1_DIMMB# <10>
DDR_CKE0_DIMMB <10> DDR_CKE1_DIMMB <10>
DDR_B_CLK0 <10> DDR_B_CLK#0 <10>
DDR_B_CLK1 <10> DDR_B_CLK#1 <10>
DDR_B_MA[15..0] <10>
DDR_B_BS#0 <10> DDR_B_BS#1 <10> DDR_B_BS#2 <10>
DDR_B_RAS# <10> DDR_B_CAS# <10> DDR_B_WE# <10>
C
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
D
E
< Processor DDR3 Memory Interface >
JCPUC
DDR_B_D[63..0]<10>
< From/To SO_DIMMB >
DDR_B_DM[7..0]<10> DDR_A_DM[7..0] <9>
< To SO_DIMMB > < To SO_DIMMA >
DDR_B_DQS0<10> DDR_B_DQS#0<10> DDR_B_DQS1<10> DDR_B_DQS#1<10> DDR_B_DQS2<10> DDR_B_DQS#2<10> DDR_B_DQS3<10> DDR_B_DQS#3<10> DDR_B_DQS4<10> DDR_B_DQS#4<10> DDR_B_DQS5<10> DDR_B_DQS#5<10> DDR_B_DQS6<10> DDR_B_DQS#6<10> DDR_B_DQS7<10> DDR_B_DQS#7<10>
< From/To SO_DIMMB > < From/To SO_DIMMA >
DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7
DDR_B_DQS0 DDR_B_DQS#0 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS7 DDR_B_DQS#7
JCPUC
MEM:DATA
MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63
MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7
MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7
MEM:DATA C11 A11 A14 B14 G11 E11 D12 A13 A15 A16 A19 A20 C14 D14 C18 D18 D20 A21 D24 C25 B20 C20 B24 C24 E23 E24 G25 G26 C26 D26 G23 G24
AA24 AA23 AD24 AE24 AA26 AA25 AD26 AE25 AC22 AD22 AE20 AF20 AF24 AF23 AC20 AD20 AD18 AE18 AC14 AD14 AF19 AC18 AF16 AF15 AF13 AC12 AB11
Y11
AE14 AF14 AF11 AD11
A12 B16 A22 E25
AB26 AE22 AC16 AD12
C12 B12 D16 C16 A24 A23 F26 E26
AC25 AC26 AF21 AF22 AE16 AD16 AF12 AE12
FOX_PZ6382A-284S-41F_Champlian
FOX_PZ6382A-284S-41F_Champlian
MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8
MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63
MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7
MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7
G12 F12 H14 G14 H11 H12 C13 E13 H15 E15 E17 H17 E14 F14 C17 G17 G18 C19 D22 E20 E18 F18 B22 C23 F20 F22 H24 J19 E21 E22 H20 H22 Y24 AB24 AB22 AA21 W22 W21 Y22 AA22 Y20 AA20 AA18 AB18 AB21 AD21 AD19 Y18 AD17 W16 W14 Y14 Y17 AB17 AB15 AD15 AB13 AD13 Y12 W11 AB14 AA14 AB12 AA12
E12 C15 E19 F24 AC24 Y19 AB16 Y13
G13 H13 G16 G15 C22 C21 G22 G21 AD23 AC23 AB19 AB20 Y15 W15 W12 W13
DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9
DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7
DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7
DDR_A_D[63..0] <9>
< From/To SO_DIMMA >
DDR_A_DQS0 <9> DDR_A_DQS#0 <9> DDR_A_DQS1 <9> DDR_A_DQS#1 <9> DDR_A_DQS2 <9> DDR_A_DQS#2 <9> DDR_A_DQS3 <9> DDR_A_DQS#3 <9> DDR_A_DQS4 <9> DDR_A_DQS#4 <9> DDR_A_DQS5 <9> DDR_A_DQS#5 <9> DDR_A_DQS6 <9> DDR_A_DQS#6 <9> DDR_A_DQS7 <9> DDR_A_DQS#7 <9>
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
401871
401871
401871
652Wednesday, May 19, 2010
652Wednesday, May 19, 2010
652Wednesday, May 19, 2010
E
B
B
B
of
of
of
A
< Filtered PLL Supply Voltage >
12
R10
R10 169_0402_1%
169_0402_1%
+2.5VDDA+2.5VS
1
C14
C14
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
+1.5V
+1.5V
+2.5VDDA
R40 300_0402_5%R40 300_0402_5%
1 2 R39 220_0402_5%R39 220_0402_5%
R38 220_0402_5%R38 220_0402_5% R37 220_0402_5%R37 220_0402_5% R36 220_0402_5%R36 220_0402_5%
L1 FBM_L11_201209_300L_0805L1 FBM_L11_201209_300L_0805
1 2
1
+
+
C11
C11
@
@
150U_B2_6.3VM_R45M
150U_B2_6.3VM_R45M
2
1 1
< 200-MHz PLL Reference Clock >
CLK_CPU_BCLK<19>
CLK_CPU_BCLK#<19>
2 2
+1.5V
R22 510_0402_5%R22 510_0402_5%
R28 1K_0402_5%R28 1K_0402_5% R27 510_0402_5%R27 510_0402_5% R29 1K_0402_5%R29 1K_0402_5% R30 1K_0402_5%R30 1K_0402_5% R31 1K_0402_5%R31 1K_0402_5% R32 1K_0402_5%R32 1K_0402_5% R33 1K_0402_5%R33 1K_0402_5% R34 1K_0402_5%R34 1K_0402_5% R265 1K_0402_5%R265 1K_0402_5% R35 1K_0402_5%R35 1K_0402_5%
3 3
LDT_RST#<19>
H_PWRGD<19,49>
4 4
LDT_STOP#<12,19>
1
C12
C12
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
C16
C16 3900P_0402_50V7K
3900P_0402_50V7K
1 2
C15
C15 3900P_0402_50V7K
3900P_0402_50V7K
1 2
Address:100_1100 Place close to CPU wihtin 1.5"
12 12
1 2
12 12 12 12 12 12 12 12
+1.5VS
R17
R17 300_0402_5%
300_0402_5%
1 2
LDT_RST#
1
C17
C17
@
@
0.01U_0402_25V7K
0.01U_0402_25V7K
2
+1.5VS
R21
R21 300_0402_5%
300_0402_5%
1 2
H_PWRGD
1
C19
C19
@
@
0.1U_0402_16V7K
0.1U_0402_16V7K
2
+1.5VS
R18
R18 300_0402_5%
300_0402_5%
1 2
LDT_STOP#
1
C18
C18
@
@
0.01U_0402_25V7K
0.01U_0402_25V7K
2
A
VDDA=300mA
1
C13
C13 3300P_0402_50V7-K
3300P_0402_50V7-K
2
CPU_TEST25H
CPU_TEST27
CPU_TEST25L
CPU_TEST12 CPU_TEST18 CPU_TEST19 CPU_TEST20 CPU_TEST21 CPU_TEST22 CPU_TEST23 CPU_TEST24
1 2 1 2 1 2 1 2
B
+2.5VDDA
CPU_CLKIN_SC_P CPU_CLKIN_SC_N
LDT_RST# H_PWRGD LDT_STOP#
+1.5V +1.5V
R12 1K_0402_5%R12 1K_0402_5% R14 1K_0402_5%R14 1K_0402_5%
R15 44.2_0402_1%R15 44.2_0402_1% R16 44.2_0402_1%R16 44.2_0402_1%
+1.1VS
CPU_VDD0_RUN_FB_H<49> CPU_VDD0_RUN_FB_L<49>
CPU_VDD1_RUN_FB_H<49> CPU_VDD1_RUN_FB_L<49>
1 2 1 2
1 2 1 2
1 2
CPU_SIC CPU_SID
CPU_HTREF0 CPU_HTREF1
CPU_VDD0_RUN_FB_H CPU_VDD0_RUN_FB_L
CPU_VDD1_RUN_FB_H CPU_VDD1_RUN_FB_L
CPU_DBRDY CPU_TMS CPU_TCK CPU_TRST# CPU_TDI
CPU_TEST23 CPU_TEST18
CPU_TEST19 CPU_TEST25H
CPU_TEST25L CPU_TEST21
CPU_TEST20 CPU_TEST24 CPU_TEST22 CPU_TEST12 CPU_TEST27
R24
R24 0_0402_5%
0_0402_5%
T2 PADT2 PAD
C
JCPUD
JCPUD
F8
VDDA1
F9
VDDA2
A9
CLKIN_H
A8
CLKIN_L
B7
RESET_L
A7
PWROK
F10
LDTSTOP_L
C6
LDTREQ_L
AF4
SIC
AF5
SID
AE6
ALERT_L
R6
HT_REF0
P6
HT_REF1
F6
VDD0_FB_H
E6
VDD0_FB_L
Y6
VDD1_FB_H
AB6
VDD1_FB_L
G10
DBRDY
AA9
TMS
AC9
TCK
AD9
TRST_L
AF9
TDI
AD7
TEST23
H10
TEST18
G9
TEST19
E9
TEST25_H
E8
TEST25_L
AB8
TEST21
AF7
TEST20
AE7
TEST24
AE8
TEST22
AC8
TEST12
AF8
TEST27
C2
TEST9
AA6
TEST6
A3
RSVD1
A5
RSVD2
B3
RSVD3
B5
RSVD4
C1
RSVD5
FOX_PZ6382A-284S-41F_Champlian
FOX_PZ6382A-284S-41F_Champlian
VSS
RSVD11
SVC SVD
THERMTRIP_L
PROCHOT_L
MEMHOT_L
THERMDC THERMDA
VDDIO_FB_H VDDIO_FB_L
VDDNB_FB_H VDDNB_FB_L
DBREQ_L
TDO
TEST28_H
TEST28_L
TEST17 TEST16 TEST15 TEST14
TEST7
TEST10
TEST8
TEST29_H
TEST29_L
RSVD10
RSVD9 RSVD8 RSVD7 RSVD6
M11 W18
CPU_SVC
A6
CPU_SVD
A4
< Serial VID Interface clock & data >
CPU_THERMTRIP#_R
AF6
CPU_PROCHOT#
AC7 AA8
W7 W8
W9 Y9
H6 G6
E10 AE9
J7 H8
D7 E7 F7 C7
C3 K8
C4
C9 C8
H18 H19 AA7 D5 C5
T3PAD T3PAD
THERMDC_CPU THERMDA_CPU
route as differential as short as possible testpoint under package
CPU_VDDNB_RUN_FB_H CPU_VDDNB_RUN_FB_L
CPU_DBREQ#
CPU_TDO
CPU_TEST17 CPU_TEST16 CPU_TEST15 CPU_TEST14
CPU_TEST29_H_FBCLKOUT_P CPU_TEST29_L_FBCLKOUT_N
+1.5V
D
CPU_SVC <49> CPU_SVD <49>
CPU_VDDNB_RUN_FB_H <49> CPU_VDDNB_RUN_FB_L <49>
R6 10K_0402_5%R6 10K_0402_5%
T4PAD T4PAD T5PAD T5PAD
R7 1K_0402_5%R7 1K_0402_5%
T6PAD T6PAD T7PAD T7PAD
CPU_THERMTRIP#_R
R25 80.6_0402_1%R25 80.6_0402_1%
+1.5V
1 2
1 2
12
R11
R11
1 2
CPU_PROCHOT#
B
B
2
Q1
Q1
E
E
3 1
C
C
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
CPU_SVC CPU_SVD
300_0402_5%
300_0402_5%
1 2
R13
@R13
@
0_0402_5%
0_0402_5%
E
1 2 1 2
+1.5V
R191K_0402_5% R191K_0402_5% R201K_0402_5% R201K_0402_5%
H_PROCHOT# <19>
H_THERMTRIP# <20>
< HDT Connector >
JP2
JP2
2
1
4
3
6
CPU_DBREQ# CPU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST# CPU_TDO
+1.5V
B
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
2423 26
SAMTEC_ASP-68200-07
@ SAMTEC_ASP-68200-07
@
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Issued Date
Issued Date
LDT_RST#
C
0.1U_0402_16V7K
0.1U_0402_16V7K
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
Deciphered Date
Deciphered Date
Deciphered Date
+3VS
1
C20
C20
1 2
2
@
@
D
THERMDA_CPU THERMDC_CPU
C21
C21 3300P_0402_50V7-K
3300P_0402_50V7-K
< Thermal Sensor >
U1
U1
1
VDD
2
D+
3
SDATA
ALERT#
D­THERM#4GND
ADM1032ARM-1 ZREEL_MSOP8
ADM1032ARM-1 ZREEL_MSOP8
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
EC_SMB_CK2
8
SCLK
EC_SMB_DA2
7 6 5
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
401871
401871
401871
E
EC_SMB_CK2 <30,42> EC_SMB_DA2 <30,42>
752Wednesday, May 19, 2010
752Wednesday, May 19, 2010
752Wednesday, May 19, 2010
of
of
of
B
B
B
A
VDD decoupling : +CPU_CORE
+CPU_CORE
1
+
+
C26
C26 330U_X_2VM_R6M
330U_X_2VM_R6M
2
1 1
1
+
+
+
+
@
@ C23
C23
2
330U_2.5V_M
330U_2.5V_M
Near CPU Socket
330U_X_2VM_R6M
330U_X_2VM_R6M
VDDIO decoupling : DDR SDRAM I/O ring power
+1.5V
1
C44
C44 22U_0805_6.3V6M
22U_0805_6.3V6M
2
Under CPU Socket
+1.5V
2 2
1
C54
C54
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
Between CPU Socket and DIMM
+1.5V
1
C64
C64
0.01U_0402_25V7K
0.01U_0402_25V7K
2
Between CPU Socket and DIMM
+1.5V
180PF Qt'y follow the distance between CPU socket and DIMM0. <2.5inch>
1
C66
C66 180P_0402_50V8J
180P_0402_50V8J
2
Between CPU Socket and DIMM
+1.5V
3 3
1
C71
C71
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
Between CPU Socket and DIMM
+1.05VS
VDDR decoupling.
1
C57
C57
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
Near CPU Socket Right side
+1.05VS
1
C76
C76
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
Near CPU Socket Left side
4 4
+VDDNB decoupling : Northbridge power
+VDDNB
1
C42
C42 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
2
C89
C89
330U_X_2VM_R6M
330U_X_2VM_R6M
1
C45
C45 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C51
C51
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C67
C67 180P_0402_50V8J
180P_0402_50V8J
2
1
C72
C72
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C58
C58
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C77
C77
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C43
C43 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
+
+
C25
C25 330U_X_2VM_R6M
330U_X_2VM_R6M
2
1
+
C24
@+C24
@
2
A
+CPU_CORE +CPU_CORE
1
C35
C35 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C34
C34 22U_0805_6.3V6M
22U_0805_6.3V6M
2
Under CPU Socket
+CPU_CORE +CPU_CORE+CPU_CORE
1
+
+
2
330U_2.5V_M
330U_2.5V_M
1
2
1
2
1
C30
C30
C90
C90
22U_0805_6.3V6M
22U_0805_6.3V6M
2
Under CPU Socket
1
C46
C46
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C52
C52
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C65
C65
0.01U_0402_25V7K
0.01U_0402_25V7K
2
1
C68
C68 180P_0402_50V8J
180P_0402_50V8J
2
1
C73
C73
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
C59
C59
0.22U_0603_16V4Z
0.22U_0603_16V4Z
C78
C78
0.22U_0603_16V4Z
0.22U_0603_16V4Z
1
C49
C49 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
2
1
C47
C47
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C53
C53
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C69
C69 180P_0402_50V8J
180P_0402_50V8J
2
1
C74
C74
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C60
C60
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C79
C79
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
C31
C31 22U_0805_6.3V6M
22U_0805_6.3V6M
1
C48
C48 180P_0402_50V8J
180P_0402_50V8J
2
390U_2.5V_M_R10
390U_2.5V_M_R10
1
C61
C61 1000P_0402_25V8J
1000P_0402_25V8J
2
1
C80
C80 1000P_0402_25V8J
1000P_0402_25V8J
2
B
1
C28
C28 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C32
C32 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C50
C50 180P_0402_50V8J
180P_0402_50V8J
2
C56 Co-layout with C75
+1.5V
1
+
+
C56
C56
2
1
@
@
+
+
C75
C75
2
330U_D2E_2.5VM_R6M
330U_D2E_2.5VM_R6M
1
C62
C62 1000P_0402_25V8J
1000P_0402_25V8J
2
1
C81
C81 1000P_0402_25V8J
1000P_0402_25V8J
2
B
1
C29
C29 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C33
C33 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C63
C63 180P_0402_50V8J
180P_0402_50V8J
2
1
C82
C82 180P_0402_50V8J
180P_0402_50V8J
2
1
C36
C36
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
Under CPU SocketNear CPU Socket
1
C39
C39
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
Under CPU Socket
1
C70
C70 180P_0402_50V8J
180P_0402_50V8J
2
1
C83
C83 180P_0402_50V8J
180P_0402_50V8J
2
C
1
C37
C37
0.01U_0402_25V7K
0.01U_0402_25V7K
2
1
C40
C40
0.01U_0402_25V7K
0.01U_0402_25V7K
2
1
C38
C38 180P_0402_50V8J
180P_0402_50V8J
2
1
C41
C41 180P_0402_50V8J
180P_0402_50V8J
2
C1124 Co-layout with C1125
+1.05VS
1
+
+
C1124
C1124
390U_2.5V_M_R10
390U_2.5V_M_R10
2
+1.05VS
330U_D2E_2.5VM
330U_D2E_2.5VM
1
C1125
C1125
+
+
2
@
@
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
Deciphered Date
Deciphered Date
Deciphered Date
+CPU_CORE
+VDDNB
+1.5V
D
JCPUE
JCPUE
G4
VDD0_1
H2
VDD0_2
J9
VDD0_3
J11
VDD0_4
J13
VDD0_5
J15
VDD0_6
K6
VDD0_7
K10
VDD0_8
K12
VDD0_9
K14
VDD0_10
L4
VDD0_11
L7
VDD0_12
L9
VDD0_13
L11
VDD0_14
L13
VDD0_15
L15
VDD0_16
M2
VDD0_17
M6
VDD0_18
M8
VDD0_19
M10
VDD0_20
N7
VDD0_21
N9
VDD0_22
N11
VDD0_23
K16
VDDNB_1
M16
VDDNB_2
P16
VDDNB_3
T16
VDDNB_4
V16
VDDNB_5
H25
VDDIO1
J17
VDDIO2
K18
VDDIO3
K21
VDDIO4
K23
VDDIO5
K25
VDDIO6
L17
VDDIO7
M18
VDDIO8
M21
VDDIO9
M23
VDDIO10
M25
VDDIO11
N17
VDDIO12
FOX_PZ6382A-284S-41F_Champlian
FOX_PZ6382A-284S-41F_Champlian
JCPUF
JCPUF
AA4
VSS1
AA11
VSS2
AA13
VSS3
AA15
VSS4
AA17
VSS5
AA19
VSS6
AB2
VSS7
AB7
VSS8
AB9
VSS9
AB23
VSS10
AB25
VSS11
AC11
VSS12
AC13
VSS13
AC15
VSS14
AC17
VSS15
AC19
VSS16
AC21
VSS17
AD6
VSS18
AD8
VSS19
AD25
VSS20
AE11
VSS21
AE13
VSS22
AE15
VSS23
AE17
VSS24
AE19
VSS25
AE21
VSS26
AE23
VSS27
B4
VSS28
B6
VSS29
B8
VSS30
B9
VSS31
B11
VSS32
B13
VSS33
B15
VSS34
B17
VSS35
B19
VSS36
B21
VSS37
B23
VSS38
B25
VSS39
D6
VSS40
D8
VSS41
D9
VSS42
D11
VSS43
D13
VSS44
D15
VSS45
D17
VSS46
D19
VSS47
D21
VSS48
D23
VSS49
D25
VSS50
E4
VSS51
F2
VSS52
F11
VSS53
F13
VSS54
F15
VSS55
F17
VSS56
F19
VSS57
F21
VSS58
F23
VSS59
F25
VSS60
H7
VSS61
H9
VSS62
H21
VSS63
H23
VSS64
J4
VSS65
FOX_PZ6382A-284S-41F_Champlian
FOX_PZ6382A-284S-41F_Champlian
D
401871
401871
401871
E
852Wednesday, May 19, 2010
852Wednesday, May 19, 2010
852Wednesday, May 19, 2010
E
+CPU_CORE
P8
VDD1_1
P10
VDD1_2
R4
VDD1_3
R7
VDD1_4
R9
VDD1_5
R11
VDD1_6
T2
VDD1_7
T6
VDD1_8
T8
VDD1_9
T10
VDD1_10
T12
VDD1_11
T14
VDD1_12
U7
VDD1_13
U9
VDD1_14
U11
VDD1_15
U13
VDD1_16
U15
VDD1_17
V6
VDD1_18
V8
VDD1_19
V10
VDD1_20
V12
VDD1_21
V14
VDD1_22
W4
VDD1_23
Y2
VDD1_24
AC4
VDD1_25 VDD1_26
VDDIO27 VDDIO26 VDDIO25 VDDIO24 VDDIO23 VDDIO22 VDDIO21 VDDIO20 VDDIO19 VDDIO18 VDDIO17 VDDIO16 VDDIO15 VDDIO14 VDDIO13
VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98
VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
+1.5V
AD2 Y25
V25 V23 V21 V18 U17 T25 T23 T21 T18 R17 P25 P23 P21 P18
J6 J8 J10 J12 J14 J16 J18 K2 K7 K9 K11 K13 K15 K17 L6 L8 L10 L12 L14 L16 L18 M7 M9 AC6 M17 N4 N8 N10 N16 N18 P2 P7 P9 P11 P17 R8 R10 R16 R18 T7 T9 T11 T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Compal Electronics, Inc.
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
B
B
B
of
of
of
A
+1.5V +1.5V
JDDRL
+VREF_DQ
1 1
2 2
3 3
4 4
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
2
C84
C84
DDR_CKE0_DIMMA<6>
DDR_CS1_DIMMA#<6>
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1000P_0402_25V8J
1000P_0402_25V8J
0.01U_0402_25V7K
0.01U_0402_25V7K
2
C85
C85
1
DDR_A_DQS#1<6> DDR_A_DQS1<6>
DDR_A_DQS#2<6> DDR_A_DQS2<6>
DDR_A_BS#2<6>
DDR_A_CLK0<6> DDR_A_CLK#0<6>
DDR_A_BS#0<6>
DDR_A_WE#<6>
DDR_A_CAS#<6> DDR_A_ODT0 <6>
DDR_A_DQS#4<6> DDR_A_DQS4<6>
DDR_A_DQS#6<6> DDR_A_DQS6<6>
+3VS
C91
C91
DDR_A_D0 DDR_A_D1
1
DDR_A_DM0
C10
C10
DDR_A_D2
2
DDR_A_D3 DDR_A_D8
DDR_A_D9 DDR_A_DQS#1
DDR_A_DQS1 DDR_A_D10
DDR_A_D11 DDR_A_D16
DDR_A_D17 DDR_A_DQS#2
DDR_A_DQS2 DDR_A_D18
DDR_A_D19 DDR_A_D24
DDR_A_D25 DDR_A_DM3 DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA
DDR_A_BS#2 DDR_A_MA12
DDR_A_MA9 DDR_A_MA8
DDR_A_MA5 DDR_A_MA3
DDR_A_MA1 DDR_A_CLK0
DDR_A_CLK#0 DDR_A_MA10
DDR_A_BS#0 DDR_A_WE#
DDR_A_CAS# DDR_A_ODT0 DDR_A_MA13
DDR_CS1_DIMMA#
DDR_A_D32 DDR_A_D33
DDR_A_DQS#4 DDR_A_DQS4
DDR_A_D34 DDR_A_D35
DDR_A_D40 DDR_A_D41
DDR_A_DM5 DDR_A_D42
DDR_A_D43 DDR_A_D48
DDR_A_D49 DDR_A_DQS#6
DDR_A_DQS6 DDR_A_D50
DDR_A_D51 DDR_A_D56
DDR_A_D57 DDR_A_DM7 DDR_A_D58
DDR_A_D59
+0.75VS
1
2
JDDRL
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1 DQS129RESET# VSS1131VSS12
33
DQ10
35
DQ11 VSS1337VSS14
39
DQ16
41
DQ17 VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25 VSS2261DQS#3
63
DM3 VSS2365VSS24
67
DQ26
69
DQ27 VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
TYCO_2-2013289-1
TYCO_2-2013289-1
DQ4 DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6 DQ7
VSS8 DQ12 DQ13
VSS10
DM1
DQ14 DQ15
DQ20 DQ21
DM2
VSS17
DQ22 DQ23
VSS19
DQ28 DQ29
VSS21
DQS3 DQ30
DQ31
CKE1 VDD2
VDD4
VDD6
VDD8
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36 DQ37
VSS30
DM4
VSS31
DQ38 DQ39
VSS33
DQ44 DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46 DQ47
VSS40
DQ52 DQ53
VSS42
DM6
VSS43
DQ54 DQ55
VSS45
DQ60 DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62 DQ63
VSS52
EVENT#
SDA
SCL
VTT2
B
2
DDR_A_D4
4
DDR_A_D5
6 8
DDR_A_DQS#0
10
DDR_A_DQS0
12 14
DDR_A_D6
16
DDR_A_D7
18 20
DDR_A_D12
22
DDR_A_D13
24 26
DDR_A_DM1
28
MEM_MA_RST#
30 32
DDR_A_D14
34
DDR_A_D15
36 38
DDR_A_D20
40
DDR_A_D21
42 44
DDR_A_DM2
46 48
DDR_A_D22
50
DDR_A_D23
52 54
DDR_A_D28
56
DDR_A_D29
58 60
DDR_A_DQS#3
62
DDR_A_DQS3
64 66
DDR_A_D30
68
DDR_A_D31
70 72
DDR_CKE1_DIMMA
74 76
DDR_A_MA15
78
A15 A14
A11
A7 A6
A4 A2
A0
S0#
G2
DDR_A_MA14
80 82
DDR_A_MA11
84
DDR_A_MA7
86 88
DDR_A_MA6
90
DDR_A_MA4
92 94
DDR_A_MA2
96
DDR_A_MA0
98 100
DDR_A_CLK1
102
DDR_A_CLK#1
104 106
DDR_A_BS#1
108
DDR_A_RAS#
110 112
DDR_CS0_DIMMA#
114 116 118
DDR_A_ODT1
120 122 124 126 128
DDR_A_D36
130
DDR_A_D37
132 134
DDR_A_DM4
136 138
DDR_A_D38
140
DDR_A_D39
142 144
DDR_A_D44
146
DDR_A_D45
148 150
DDR_A_DQS#5
152
DDR_A_DQS5
154 156
DDR_A_D46
158
DDR_A_D47
160 162
DDR_A_D52
164
DDR_A_D53
166 168
DDR_A_DM6
170 172
DDR_A_D54
174
DDR_A_D55
176 178
DDR_A_D60
180
DDR_A_D61
182 184
DDR_A_DQS#7
186
DDR_A_DQS7
188 190
DDR_A_D62
192
DDR_A_D63
194 196 198 200 202 204
206
+0.75VS
DDR_A_DQS#0 <6> DDR_A_DQS0 <6>
MEM_MA_RST# <6>
DDR_A_DQS#3 <6> DDR_A_DQS3 <6>
DDR_CKE1_DIMMA <6>
DDR_A_CLK1 <6> DDR_A_CLK#1 <6>
DDR_A_BS#1 <6> DDR_A_RAS# <6>
DDR_CS0_DIMMA# <6>
DDR_A_ODT1 <6>
1
C680
C680
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1000P_0402_25V8J
1000P_0402_25V8J
DDR_A_DQS#5 <6> DDR_A_DQS5 <6>
DDR_A_DQS#7 <6> DDR_A_DQS7 <6>
SMB_CK_DAT0 <10,20> SMB_CK_CLK0 <10,20>
1
C235
C235
2
2
1
0.01U_0402_25V7K
0.01U_0402_25V7K
C
DDR_A_D[0..63] DDR_A_DM[0..7]
DDR_A_MA[0..15]
C351
C351
+VREF_CA
0.1U_0402_16V4Z
0.1U_0402_16V4Z
D
DDR_A_D[0..63] <6>
DDR_A_DM[0..7] <6>
DDR_A_MA[0..15] <6>
+1.5V
R48
R48 1K_0402_1%
1K_0402_1%
+VREF_DQ +VREF_CA
1 2
R49
R49 1K_0402_1%
1K_0402_1%
1 2
< Close to JDDRH & JDDRL >
+1.5V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C87
C87
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+0.75VS
2
1
2
C88
C88
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C665
C665
2
1
2
C664
C664
1
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z 2
C640
C640
1
1
C961
C961
2
C641
C641
2
C642
C642
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z 2
C643
C643
1
2
C644
C644
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z 2
C645
C645
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.5V
2
C646
C646
1
1 2
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
E
R310
R310 1K_0402_1%
1K_0402_1%
R315
R315 1K_0402_1%
1K_0402_1%
2
C647
C647
1
Place near DIMM1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
DIMM_A STD H:5.2 mm
<Address: 00>
A
B
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
401871
401871
401871
952Wednesday, May 19, 2010
952Wednesday, May 19, 2010
952Wednesday, May 19, 2010
E
B
B
B
of
of
of
A
B
C
D
E
DQ4 DQ5
VSS3
VSS6
DQ6 DQ7
VSS8
DM1
DM2
CKE1
CK1
CK1#
BA1
RAS#
NC2
DM4
DM6
SDA SCL
VTT2
+1.5V+1.5V
2
DDR_B_D4
4
DDR_B_D5
6 8
DDR_B_DQS#0
10
DDR_B_DQS0
12 14
DDR_B_D6
16
DDR_B_D7
18 20
DDR_B_D12
22
DDR_B_D13
24 26
DDR_B_DM1
28
MEM_MB_RST#
30 32
DDR_B_D14
34
DDR_B_D15
36 38
DDR_B_D20
40
DDR_B_D21
42 44
DDR_B_DM2
46 48
DDR_B_D22
50
DDR_B_D23
52 54
DDR_B_D28
56
DDR_B_D29
58 60
DDR_B_DQS#3
62
DDR_B_DQS3
64 66
DDR_B_D30
68
DDR_B_D31
70 72
DDR_CKE1_DIMMB
74 76
DDR_B_MA15
78
A15 A14
A11
A7 A6
A4 A2
A0
S0#
G2
DDR_B_MA14
80 82
DDR_B_MA11
84
DDR_B_MA7
86 88
DDR_B_MA6
90
DDR_B_MA4
92 94
DDR_B_MA2
96
DDR_B_MA0
98 100
DDR_B_CLK1
102
DDR_B_CLK#1
104 106
DDR_B_BS#1
108
DDR_B_RAS#
110 112
DDR_CS0_DIMMB#
114
DDR_B_ODT0DDR_B_CAS#
116 118
DDR_B_ODT1
120 122 124 126 128
DDR_B_D36
130
DDR_B_D37
132 134
DDR_B_DM4
136 138
DDR_B_D38
140
DDR_B_D39
142 144
DDR_B_D44
146
DDR_B_D45
148 150
DDR_B_DQS#5
152
DDR_B_DQS5
154 156
DDR_B_D46
158
DDR_B_D47
160 162
DDR_B_D52
164
DDR_B_D53
166 168
DDR_B_DM6
170 172
DDR_B_D54
174
DDR_B_D55
176 178
DDR_B_D60
180
DDR_B_D61
182 184
DDR_B_DQS#7
186
DDR_B_DQS7
188 190
DDR_B_D62
192
DDR_B_D63
194 196 198 200 202 204
206
+0.75VS
DDR_B_DQS#0 <6> DDR_B_DQS0 <6>
MEM_MB_RST# <6>
DDR_B_DQS#3 <6> DDR_B_DQS3 <6>
DDR_CKE1_DIMMB <6>
DDR_B_CLK1 <6> DDR_B_CLK#1 <6>
DDR_B_BS#1 <6> DDR_B_RAS# <6>
DDR_CS0_DIMMB# <6> DDR_B_ODT0 <6>
DDR_B_ODT1 <6>
1000P_0402_25V8J
1000P_0402_25V8J
1
C683
C683
2
DDR_B_DQS#5 <6> DDR_B_DQS5 <6>
DDR_B_DQS#7 <6> DDR_B_DQS7 <6>
SMB_CK_DAT0 <9,20> SMB_CK_CLK0 <9,20>
DDR_B_D[0..63]
DDR_B_DM[0..7]
DDR_B_MA[0..15]
C353
C353
+VREF_CA
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C352
C352
0.1U_0402_16V4Z
1
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
2
+1.5V
2
C666
C666
1
+0.75VS
2
1
DDR_B_D[0..63] <6>
DDR_B_DM[0..7] <6>
DDR_B_MA[0..15] <6>
0.1U_0402_16V4Z
0.1U_0402_16V4Z 2
C667
C667
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z 2
C675
C675
C676
C676
1
2
C668
C668
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C925
C925
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z 2
C669
C669
1
2
C670
C670
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z 2
C671
C671
1
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C128 Co-layout with C86
+1.5V
1
+
C86
@+C86
@
2
330U_X_2VM_R6M
330U_X_2VM_R6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z 2
C672
C672
1
+1.5V
1
+
+
C128
C128
2
390U_2.5V_M_R10
390U_2.5V_M_R10
C673
C673
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C674
C674
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z 2
C677
C677
1
JDDRH
+VREF_DQ
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C92
C92
1 1
2 2
3 3
4 4
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
1
2
C682
C682
C93
C93
2
1000P_0402_25V8J
1000P_0402_25V8J
DDR_B_DQS#1<6> DDR_B_DQS1<6>
DDR_B_DQS#2<6> DDR_B_DQS2<6>
DDR_CKE0_DIMMB<6>
DDR_B_BS#2<6>
DDR_B_CLK0<6> DDR_B_CLK#0<6>
DDR_B_BS#0<6>
DDR_B_WE#<6>
DDR_B_CAS#<6>
DDR_CS1_DIMMB#<6>
DDR_B_DQS#4<6> DDR_B_DQS4<6>
DDR_B_DQS#6<6> DDR_B_DQS6<6>
+3VS
+0.75VS
DDR_B_D0 DDR_B_D1
DDR_B_DM0 DDR_B_D2
DDR_B_D3 DDR_B_D8
DDR_B_D9 DDR_B_DQS#1
DDR_B_DQS1 DDR_B_D10
DDR_B_D11 DDR_B_D16
DDR_B_D17 DDR_B_DQS#2
DDR_B_DQS2 DDR_B_D18
DDR_B_D19 DDR_B_D24
DDR_B_D25 DDR_B_DM3 DDR_B_D26
DDR_B_D27
DDR_CKE0_DIMMB
DDR_B_BS#2 DDR_B_MA12
DDR_B_MA9 DDR_B_MA8
DDR_B_MA5 DDR_B_MA3
DDR_B_MA1 DDR_B_CLK0
DDR_B_CLK#0 DDR_B_MA10
DDR_B_BS#0 DDR_B_WE#
DDR_B_MA13 DDR_CS1_DIMMB#
DDR_B_D32 DDR_B_D33
DDR_B_DQS#4 DDR_B_DQS4
DDR_B_D34 DDR_B_D35
DDR_B_D40 DDR_B_D41
DDR_B_DM5 DDR_B_D42
DDR_B_D43 DDR_B_D48
DDR_B_D49 DDR_B_DQS#6
DDR_B_DQS6 DDR_B_D50
DDR_B_D51 DDR_B_D56
DDR_B_D57 DDR_B_DM7 DDR_B_D58
DDR_B_D59
JDDRH
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1 DQS129RESET#
31
VSS11
33
DQ10
35
DQ11
37
VSS13
39
DQ16
41
DQ17
43
VSS15
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25 VSS2261DQS#3
63
DM3
65
VSS23
67
DQ26
69
DQ27
71
VSS25
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
LOTES_AAA-DDR-111-K01
LOTES_AAA-DDR-111-K01
DQS#0
DQS0
DQ12 DQ13
VSS10
VSS12
DQ14 DQ15
VSS14
DQ20 DQ21
VSS16 VSS17
DQ22 DQ23
VSS19
DQ28 DQ29
VSS21
DQS3
VSS24
DQ30 DQ31
VSS26
VDD2
VDD4
VDD6
VDD8
VDD10
VDD12
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36 DQ37
VSS30 VSS31
DQ38 DQ39
VSS33
DQ44 DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46 DQ47
VSS40
DQ52 DQ53
VSS42 VSS43
DQ54 DQ55
VSS45
DQ60 DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62 DQ63
VSS52
EVENT#
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
DIMM_B STD H:9.2 mm
<Address: 01>
A
B
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
401871
401871
401871
10 52Wednesday, May 19, 2010
10 52Wednesday, May 19, 2010
10 52Wednesday, May 19, 2010
E
B
B
B
of
of
of
A
PCIE_GTX_C_MRX_P[0..15]<34> PCIE_GTX_C_MRX_N[0..15]<34>
1 1
2 2
PCIE_GTX_C_MRX_P[0..15] PCIE_GTX_C_MRX_N[0..15]
< To WLAN > < To LAN >
PCIE_PTX_C_IRX_P2<27> PCIE_PTX_C_IRX_N2<27> PCIE_PTX_C_IRX_P3<25> PCIE_PTX_C_IRX_N3<25>
< From SB820 : x4 PCIE A-link >
H_CADON[0..15]
3 3
4 4
H_CADOP[0..15] <5> H_CADON[0..15] <5>
< From S1G4 CPU : x16 HT> < To S1G4 CPU : x16 HT>
0718 Place within 1" layout 1:2
SB_RX0P<19> SB_RX0N<19> SB_RX1P<19> SB_RX1N<19> SB_RX2P<19> SB_RX2N<19> SB_RX3P<19> SB_RX3N<19>
H_CLKOP0<5>
H_CLKON0<5>
H_CLKOP1<5>
H_CLKON1<5>
H_CTLOP0<5> H_CTLON0<5>
H_CTLON1<5>
1 2
PCIE_GTX_C_MRX_N0 PCIE_GTX_C_MRX_P0 PCIE_GTX_C_MRX_P1 PCIE_GTX_C_MRX_N1 PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_P2 PCIE_GTX_C_MRX_N3 PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_P4 PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_P6 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_P10 PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_P11 PCIE_GTX_C_MRX_N12 PCIE_GTX_C_MRX_P12 PCIE_GTX_C_MRX_N13 PCIE_GTX_C_MRX_P13 PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_P14 PCIE_GTX_C_MRX_N15 PCIE_GTX_C_MRX_P15
H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7
H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15
R60301_0402_1% R60301_0402_1%
B
H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1
HT_RXCALP HT_RXCALN
AC24 AC25 AB25 AB24 AA24 AA25
W21 W20
AB23 AA22
M22 M23
D4 C4 A3 B3 C2 C1 E5 F5 G5 G6 H5 H6
M8
P7
M7
P5
M5
R8 P8 R6 R5 P4 P3 T4 T3
AE3 AD4 AE2 AD3 AD1 AD2
V5
W6
U5 U6 U8 U7
AA8
Y8
AA7
Y7 AA5 AA6
W5
Y5
Y25 Y24 V22 V23 V25 V24 U24 U25 T25 T24 P22 P23 P25 P24 N24 N25
Y22 Y23
V21 V20 U20 U21 U19 U18
T22 T23
R21 R20
C23 A24
U3B
U3B
GFX_RX0P GFX_RX0N GFX_RX1P GFX_RX1N GFX_RX2P GFX_RX2N GFX_RX3P GFX_RX3N GFX_RX4P GFX_RX4N GFX_RX5P GFX_RX5N
J6
GFX_RX6P
J5
GFX_RX6N
J7
GFX_RX7P
J8
GFX_RX7N
L5
GFX_RX8P
L6
GFX_RX8N GFX_RX9P
L8
GFX_RX9N GFX_RX10P GFX_RX10N GFX_RX11P GFX_RX11N GFX_RX12P GFX_RX12N GFX_RX13P GFX_RX13N GFX_RX14P GFX_RX14N GFX_RX15P GFX_RX15N
GPP_RX0P GPP_RX0N GPP_RX1P GPP_RX1N GPP_RX2P GPP_RX2N GPP_RX3P GPP_RX3N GPP_RX4P GPP_RX4N GPP_RX5P GPP_RX5N
SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N
U3A
U3A
HT_RXCAD0P HT_RXCAD0N HT_RXCAD1P HT_RXCAD1N HT_RXCAD2P HT_RXCAD2N HT_RXCAD3P HT_RXCAD3N HT_RXCAD4P HT_RXCAD4N HT_RXCAD5P HT_RXCAD5N HT_RXCAD6P HT_RXCAD6N HT_RXCAD7P HT_RXCAD7N
HT_RXCAD8P HT_RXCAD8N HT_RXCAD9P HT_RXCAD9N HT_RXCAD10P HT_RXCAD10N HT_RXCAD11P HT_RXCAD11N HT_RXCAD12P HT_RXCAD12N HT_RXCAD13P HT_RXCAD13N HT_RXCAD14P HT_RXCAD14N HT_RXCAD15P HT_RXCAD15N
HT_RXCLK0P HT_RXCLK0N HT_RXCLK1P HT_RXCLK1N
HT_RXCTL0P HT_RXCTL0N HT_RXCTL1P HT_RXCTL1N
HT_RXCALP HT_RXCALN
C
PCIE_MTX_GRX_P0
A5
PART 2 OF 6
PART 2 OF 6
PCIE I/F GPP
PCIE I/F GPP
PCIE I/F SB
PCIE I/F SB
PCE_CALRP(PCE_BCALRP) PCE_CALRN(PCE_BCALRN)
RS780M_FCBGA528880MR1@
RS780M_FCBGA528880MR1@
PART 1 OF 6
PART 1 OF 6
RS780M_FCBGA528880MR1@
RS780M_FCBGA528880MR1@
GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
PCIE I/F GFX
PCIE I/F GFX
GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N GPP_TX4P GPP_TX4N GPP_TX5P GPP_TX5N
SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N
HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N HT_TXCAD3P HT_TXCAD3N HT_TXCAD4P HT_TXCAD4N HT_TXCAD5P HT_TXCAD5N HT_TXCAD6P HT_TXCAD6N HT_TXCAD7P HT_TXCAD7N
HT_TXCAD8P HT_TXCAD8N HT_TXCAD9P
HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
HYPER TRANSPORT CPU I/F
HYPER TRANSPORT CPU I/F
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
HT_TXCALP HT_TXCALN
PCIE_MTX_GRX_N0
B5
PCIE_MTX_GRX_P1
A4
PCIE_MTX_GRX_N1
B4
PCIE_MTX_GRX_P2
C3
PCIE_MTX_GRX_N2
B2
PCIE_MTX_GRX_P3
D1 D2
PCIE_MTX_GRX_P4
E2
PCIE_MTX_GRX_N4
E1
PCIE_MTX_GRX_P5
F4 F3
PCIE_MTX_GRX_P6
F1
PCIE_MTX_GRX_N6
F2
PCIE_MTX_GRX_P7
H4
PCIE_MTX_GRX_N7
H3
PCIE_MTX_GRX_P8
H1 H2
PCIE_MTX_GRX_P9
J2
PCIE_MTX_GRX_N9
J1 K4
PCIE_MTX_GRX_N10
K3
PCIE_MTX_GRX_P11
K1
PCIE_MTX_GRX_N11
K2
PCIE_MTX_GRX_P12
M4
PCIE_MTX_GRX_N12
M3
PCIE_MTX_GRX_P13
M1 M2
PCIE_MTX_GRX_P14
N2
PCIE_MTX_GRX_N14
N1
PCIE_MTX_GRX_P15
P1 P2
AC1 AC2 AB4 AB3
PCIE_ITX_PRX_P2
AA2
PCIE_ITX_PRX_N2
AA1
PCIE_ITX_PRX_P3
Y1
PCIE_ITX_PRX_N3
Y2 Y4 Y3 V1 V2
SB_TX0P_C
AD7
SB_TX0N_C
AE7
SB_TX1P_C
AE6
SB_TX1N_C
AD6
SB_TX2P_C
AB6
SB_TX2N_C
AC6
SB_TX3P_C
AD5
SB_TX3N_C
AE5
PCIE_CALRP
AC8
PCIE_CALRN
AB8
H_CADIP0
D24
H_CADIN0
D25
H_CADIP1
E24
H_CADIN1
E25
H_CADIP2
F24
H_CADIN2
F25
H_CADIP3
F23
H_CADIN3
F22
H_CADIP4
H23
H_CADIN4
H22
H_CADIP5
J25
H_CADIN5
J24
H_CADIP6
K24
H_CADIN6
K25
H_CADIP7
K23
H_CADIN7
K22
H_CADIP8
F21
H_CADIN8
G21
H_CADIP9
G20
H_CADIN9
H21
H_CADIP10
J20
H_CADIN10
J21
H_CADIP11
J18
H_CADIN11
K17
H_CADIP12
L19
H_CADIN12
J19
H_CADIP13
M19
H_CADIN13
L18
H_CADIP14
M21
H_CADIN14
P21
H_CADIP15
P18
H_CADIN15
M18 H24
H25 L21 L20
H_CTLIP0
M24
H_CTLIN0
M25
H_CTLIP1
P19
H_CTLIN1
R18
HT_TXCALP
B24
HT_TXCALN
B25
0718 Place within 1" layout 1:2
C95 0.1U_0402_16V7KC95 0.1U_0402_16V7K
1 2
C96 0.1U_0402_16V7KC96 0.1U_0402_16V7K
1 2
C97 0.1U_0402_16V7KC97 0.1U_0402_16V7K
1 2
C98 0.1U_0402_16V7KC98 0.1U_0402_16V7K
1 2
C99 0.1U_0402_16V7KC99 0.1U_0402_16V7K
1 2
C100 0.1U_0402_16V7KC100 0.1U_0402_16V7K
1 2
C101 0.1U_0402_16V7KC101 0.1U_0402_16V7K
1 2
C102 0.1U_0402_16V7KC102 0.1U_0402_16V7K
1 2
C103 0.1U_0402_16V7KC103 0.1U_0402_16V7K
1 2
C104 0.1U_0402_16V7KC104 0.1U_0402_16V7K
1 2
C105 0.1U_0402_16V7KC105 0.1U_0402_16V7K
1 2
C106 0.1U_0402_16V7KC106 0.1U_0402_16V7K
1 2
C107 0.1U_0402_16V7KC107 0.1U_0402_16V7K
1 2
C108 0.1U_0402_16V7KC108 0.1U_0402_16V7K
1 2
C109 0.1U_0402_16V7KC109 0.1U_0402_16V7K
1 2
C110 0.1U_0402_16V7KC110 0.1U_0402_16V7K
1 2
C111 0.1U_0402_16V7KC111 0.1U_0402_16V7K
1 2
C112 0.1U_0402_16V7KC112 0.1U_0402_16V7K
1 2
C113 0.1U_0402_16V7KC113 0.1U_0402_16V7K
1 2
C114 0.1U_0402_16V7KC114 0.1U_0402_16V7K
1 2
C115 0.1U_0402_16V7KC115 0.1U_0402_16V7K
1 2
C116 0.1U_0402_16V7KC116 0.1U_0402_16V7K
1 2
C117 0.1U_0402_16V7KC117 0.1U_0402_16V7K
1 2
C118 0.1U_0402_16V7KC118 0.1U_0402_16V7K
1 2
C119 0.1U_0402_16V7KC119 0.1U_0402_16V7K
1 2
C120 0.1U_0402_16V7KC120 0.1U_0402_16V7K
1 2
C121 0.1U_0402_16V7KC121 0.1U_0402_16V7K
1 2
C122 0.1U_0402_16V7KC122 0.1U_0402_16V7K
1 2
C123 0.1U_0402_16V7KC123 0.1U_0402_16V7K
1 2
C124 0.1U_0402_16V7KC124 0.1U_0402_16V7K
1 2
C125 0.1U_0402_16V7KC125 0.1U_0402_16V7K
1 2
C126 0.1U_0402_16V7KC126 0.1U_0402_16V7K
1 2
C129 0.1U_0402_16V7KC129 0.1U_0402_16V7K
1 2
C130 0.1U_0402_16V7KC130 0.1U_0402_16V7K
1 2
C131 0.1U_0402_16V7KC131 0.1U_0402_16V7K
1 2
C132 0.1U_0402_16V7KC132 0.1U_0402_16V7K
1 2
C133 0.1U_0402_16V7KC133 0.1U_0402_16V7K
1 2
C134 0.1U_0402_16V7KC134 0.1U_0402_16V7K
1 2
C135 0.1U_0402_16V7KC135 0.1U_0402_16V7K
1 2
C136 0.1U_0402_16V7KC136 0.1U_0402_16V7K
1 2
C137 0.1U_0402_16V7KC137 0.1U_0402_16V7K
1 2
C138 0.1U_0402_16V7KC138 0.1U_0402_16V7K
1 2
C139 0.1U_0402_16V7KC139 0.1U_0402_16V7K
1 2
C140 0.1U_0402_16V7KC140 0.1U_0402_16V7K
1 2
R59 1.27K_0402_1%R59 1.27K_0402_1%
1 2
R58 2K_0402_1%R58 2K_0402_1%
1 2
H_CADIP[0..15]H_CADOP[0..15] H_CADIN[0..15]
H_CLKIP0 <5> H_CLKIN0 <5> H_CLKIP1 <5> H_CLKIN1 <5>
H_CTLIP0 <5>
H_CTLIN0 <5>
H_CTLIP1 <5>H_CTLOP1<5>
H_CTLIN1 <5>
R61 301_0402_1%R61 301_0402_1%
1 2
D
PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_N1 PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_N3 PCIE_MTX_C_GRX_P3PCIE_MTX_GRX_N3 PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_P5 PCIE_MTX_C_GRX_N5PCIE_MTX_GRX_N5 PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_P7 PCIE_MTX_C_GRX_N7 PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_N8PCIE_MTX_GRX_N8 PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_P10PCIE_MTX_GRX_P10 PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_N11 PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_N13PCIE_MTX_GRX_N13 PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_P15 PCIE_MTX_C_GRX_N15PCIE_MTX_GRX_N15
PCIE_ITX_C_PRX_P2 <27> PCIE_ITX_C_PRX_N2 <27> PCIE_ITX_C_PRX_P3 <25> PCIE_ITX_C_PRX_N3 <25>
SB_TX0P <19> SB_TX0N <19> SB_TX1P <19> SB_TX1N <19> SB_TX2P <19> SB_TX2N <19> SB_TX3P <19> SB_TX3N <19>
+1.1VS
H_CADIP[0..15] <5> H_CADIN[0..15] <5>
< Transmitter Calibration Resistor to HT_TXCALN >
PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]
< To WLAN > < To LAN >
< To SB820 : x4 PCEI A-link>
< TX Impedance Calibration. Connect to GND > < RX Impedance Calibration. Connect to VDDPCIE >
E
PCIE_MTX_C_GRX_P[0..15] <34> PCIE_MTX_C_GRX_N[0..15] <34>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2009-02-12 2009-02-12
2009-02-12 2009-02-12
2009-02-12 2009-02-12
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
401871
401871
401871
11 52Wednesday, May 19, 2010
11 52Wednesday, May 19, 2010
11 52Wednesday, May 19, 2010
E
B
B
B
of
of
of
+3VS
1 2
+1.8VS
1 1
+1.8VS
+1.1VS
1 2
+1.8VS
1 2
2 2
+1.8VS
+1.8VS
L4
L4 0_0603_5%
0_0603_5%
1 2
1 2
1 2
L3
L3 BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
L2
L2 BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
L5
L5 BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
A
1
C142
C142
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
L6
L6 BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
L7
L7 BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
L9
L9 BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
+AVDD1
1
C144
C144
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
+AVDD2
1
C145
C145
0.1U_0402_16V7K
0.1U_0402_16V7K
2
+AVDDQ
1
C148
C148
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
+NB_PLLVDD
1
C141
C141
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
+NB_HTPVDD
1
C146
C146
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
+VDDA18HTPLL
1
C150
C150
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
+VDDA18PCIEPLL
1
C154
C154
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
NB_REFCLK_P<19> NB_REFCLK_N<19>
UMA_CRT_HSYNC<15> UMA_CRT_VSYNC<15>
+VDDA18HTPLL
+VDDA18PCIEPLL
PLT_RST#<15,19,25,27,30,31,34> NB_PWRGD<20>
CPU_LDT_REQ#<19>
CLK_SBSRC_BCLK<19> CLK_SBSRC_BCLK#<19>
+NB_PLLVDD
+NB_HTPVDD
HT_REFCLKP<19> HT_REFCLKN<19>
Strap pin
AUX_CAL<15>
B
+AVDD1 +AVDD2 +AVDDQ
R65 715_0402_1%R65 715_0402_1%
1 2
R66 0_0402_5%R66 0_0402_5%
1 2
NB_LDTSTOP#
NB_REFCLK_P NB_REFCLK_N
R69 4.7K_0402_5%R69 4.7K_0402_5%
1 2
R70 4.7K_0402_5%R70 4.7K_0402_5%
1 2
AVDD=100mA
UMA_CRT_HSYNC UMA_CRT_VSYNC
T8 PADT8 PAD
+NB_PLLVDD +NB_HTPVDD
NB_RESET# NB_PWRGD
T19 PADT19 PAD T21 PADT21 PAD
U3C
U3C
F12
AVDD1(NC)
E12
AVDD2(NC)
F14
AVDDDI(NC)
G15
AVSSDI(NC)
H15
AVDDQ(NC)
H14
AVSSQ(NC)
E17
C_Pr(DFT_GPIO5)
F17
Y(DFT_GPIO2)
F15
COMP_Pb(DFT_GPIO4)
G18
RED(DFT_GPIO0)
G17
REDb(NC)
E18
GREEN(DFT_GPIO1)
F18
GREENb(NC)
E19
BLUE(DFT_GPIO3)
F19
BLUEb(NC)
A11
DAC_HSYNC(PWM_GPIO4)
B11
DAC_VSYNC(PWM_GPIO6)
F8
DAC_SCL(PCE_RCALRN)
E8
DAC_SDA(PCE_TCALRN)
G14
DAC_RSET(PWM_GPIO1)
A12
PLLVDD(NC)
D14
PLLVDD18(NC)
B12
PLLVSS(NC)
H17
VDDA18HTPLL
D7
VDDA18PCIEPLL1
E7
VDDA18PCIEPLL2
D8
SYSRESETb
A10
POWERGOOD
C10
LDTSTOPb
C12
ALLOW_LDTSTOP
C25
HT_REFCLKP
C24
HT_REFCLKN
E11
REFCLK_P/OSCIN(OSCIN)
F11
REFCLK_N(PWM_GPIO3)
T2
GFX_REFCLKP
T1
GFX_REFCLKN
U1
GPP_REFCLKP
U2
GPP_REFCLKN
V4
GPPSB_REFCLKP(SB_REFCLKP)
V3
GPPSB_REFCLKN(SB_REFCLKN)
B9
I2C_CLK
A9
I2C_DATA
B8
DDC_DATA0/AUX0N(NC)
A8
DDC_CLK0/AUX0P(NC)
B7
DDC_CLK1/AUX1P(NC)
A7
DDC_DATA1/AUX1N(NC)
B10
STRP_DATA
G11
RSVD
C8
AUX_CAL(NC)
C
PART 3 OF 6
PART 3 OF 6
RS780M_FCBGA528880MR1@
RS780M_FCBGA528880MR1@
< Dedicated power for the DAC which can affect display quality >
TXOUT_L0P(NC) TXOUT_L0N(NC) TXOUT_L1P(NC) TXOUT_L1N(NC) TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)
TXOUT_U0P(NC)
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U3P(PCIE_RESET_GPIO5)
CRT/TVOUT
CRT/TVOUT
TXCLK_UN(PCIE_RESET_GPIO1)
PM
PM
CLOCKs PLL PWR
CLOCKs PLL PWR
MIS.
MIS.
TXOUT_U0N(NC)
TXOUT_U2P(NC)
TXOUT_U2N(NC) TXOUT_U3N(NC)
TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
TXCLK_UP(PCIE_RESET_GPIO4)
VDDLTP18(NC) VSSLTP18(NC)
VDDLT18_1(NC) VDDLT18_2(NC) VDDLT33_1(NC)
LVTM
LVTM
VDDLT33_2(NC)
VSSLT1(VSS) VSSLT2(VSS) VSSLT3(VSS) VSSLT4(VSS) VSSLT5(VSS) VSSLT6(VSS) VSSLT7(VSS)
LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)
TMDS_HPD(NC)
SUS_STAT#(PWM_GPIO5)
THERMALDIODE_P THERMALDIODE_N
TESTMODE
HPD(NC)
A22 B22 A21 B21 B20 A20 A19
< LVDS dual channel : channel 1 >
B19 B18
A18 A17 B17 D20 D21 D18
< LVDS dual channel : channel 2 >
D19 B16
A16 D16 D17
+VDDLTP18
A13 B13
+VDDLT18
A15 B15 A14 B14
C14 D15 C16 C18 C20 E20 C22
E9 F7 G12
D9 D10
D12 AE8
AD8 D13
T22PAD T22PAD
R84 1.8K_0402_5%R84 1.8K_0402_5%
D
1 2
+VDDLTP18
+VDDLT18
C156
C156
0.1U_0402_16V7K
0.1U_0402_16V7K
SUS_STAT# <15,20>
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
1
C153
C153
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
1
4.7U_0805_10V4Z
4.7U_0805_10V4Z 2
2
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
1
C157
C157
2
< Strap option pin or gate side-port memory IO >
E
L8
L8
L10
L10
+1.8VS
1 2
+1.8VS
1 2
5
U2
U2
P
4
Y
G
NC7SZ08P5X_NL_SC70-5
NC7SZ08P5X_NL_SC70-5
3
@
@
+1.8VS
R83
R83
2.2K_0402_5%
2.2K_0402_5%
1 2
NB_LDTSTOP#
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2009-02-12 2009-02-12
2009-02-12 2009-02-12
2009-02-12 2009-02-12
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
401871
401871
401871
12 52Wednesday, May 19, 2010
12 52Wednesday, May 19, 2010
12 52Wednesday, May 19, 2010
E
of
of
of
B
B
B
3 3
R68 300_0402_5%R68 300_0402_5%
+1.8VS
4 4
1 2
R366 1K_0402_1%R366 1K_0402_1%
1 2
A
NB_PWRGD
CPU_LDT_REQ#
+1.8VS
C149
C149
1 2
0.1U_0402_16V7K
0.1U_0402_16V7K
LDT_STOP#<7,19>
2
B
1
A
1 2
R101 0_0402_5%
R101 0_0402_5%
B
2
U3D
U3D
AB12 AE16
V11 AE15 AA12 AB16 AB14 AD14 AD13 AD15 AC16 AE13 AC14
Y14 AD16
AE17 AD17
W12
Y12 AD18 AB13 AB18
V14
V15
B B
W14
AE12 AD12
MEM_A0(NC) MEM_A1(NC) MEM_A2(NC) MEM_A3(NC) MEM_A4(NC) MEM_A5(NC) MEM_A6(NC) MEM_A7(NC) MEM_A8(NC) MEM_A9(NC) MEM_A10(NC) MEM_A11(NC) MEM_A12(NC) MEM_A13(NC)
MEM_BA0(NC) MEM_BA1(NC) MEM_BA2(NC)
MEM_RASb(NC) MEM_CASb(NC) MEM_WEb(NC) MEM_CSb(NC) MEM_CKE(NC) MEM_ODT(NC)
MEM_CKP(NC) MEM_CKN(NC)
MEM_COMPP(NC) MEM_COMPN(NC)
PAR 4 OF 6
PAR 4 OF 6
MEM_DQ0/DVO_VSYNC(NC) MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC) MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC) MEM_DQ5/DVO_D1(NC) MEM_DQ6/DVO_D2(NC) MEM_DQ7/DVO_D4(NC) MEM_DQ8/DVO_D3(NC) MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC) MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC) MEM_DQ14/DVO_D10(NC) MEM_DQ15/DVO_D11(NC)
MEM_DQS0P/DVO_IDCKP(NC) MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC) MEM_DQS1N(NC)
MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)
SBD_MEM/DVO_I/F
SBD_MEM/DVO_I/F
RS780M_FCBGA528880MR1@
RS780M_FCBGA528880MR1@
IOPLLVDD18(NC)
IOPLLVDD(NC)
IOPLLVSS(NC)
MEM_VREF(NC)
AA18 AA20 AA19 Y19 V17 AA17 AA15 Y15 AC20 AD19 AE22 AC18 AB20 AD22 AC22 AD21
Y17 W18 AD20 AE21
W17 AE19
AE23 AE24
AD23 AE18
+1.8VS +1.1VS
1
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2009-02-12 2009-02-12
2009-02-12 2009-02-12
2009-02-12 2009-02-12
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
1
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
401871
401871
401871
13 52Wednesday, May 19, 2010
13 52Wednesday, May 19, 2010
13 52Wednesday, May 19, 2010
B
B
B
of
of
of
A
B
C
D
E
U3E
M16
AE25 AD24 AC23 AB22 AA21
W19
M17
M10
AE11 AD11
W22 W24 W25
AD25
M14
W11
W15 AC12 AA14
AB11 AB15 AB17 AB19 AE20 AB21
J17 K16 L16
P16 R16 T16
H18 G19 F20 E21 D22 B23 A23
Y20 V18
U17 T17 R17 P17
J10 P10 K10
L10
W9
H9 T10 R10
Y9 AA9 AB9 AD9 AE9 U10
F9
G9
A25 D23 E22 G22 G24 G25 H19
J22 L17 L22 L24 L25 M20 N22 P20 R19 R22 R24 R25 H20 U22 V19
Y21
L12 N13
P12 P15 R11 R14 T12 U14 U11 U15 V12
Y18
K11
U3E
VDDHT_1 VDDHT_2 VDDHT_3 VDDHT_4 VDDHT_5 VDDHT_6 VDDHT_7
VDDHTRX_1 VDDHTRX_2 VDDHTRX_3 VDDHTRX_4 VDDHTRX_5 VDDHTRX_6 VDDHTRX_7
VDDHTTX_1 VDDHTTX_2 VDDHTTX_3 VDDHTTX_4 VDDHTTX_5 VDDHTTX_6 VDDHTTX_7 VDDHTTX_8 VDDHTTX_9 VDDHTTX_10 VDDHTTX_11 VDDHTTX_12 VDDHTTX_13
VDDA18PCIE_1 VDDA18PCIE_2 VDDA18PCIE_3 VDDA18PCIE_4 VDDA18PCIE_5 VDDA18PCIE_6 VDDA18PCIE_7 VDDA18PCIE_8 VDDA18PCIE_9 VDDA18PCIE_10 VDDA18PCIE_11 VDDA18PCIE_12 VDDA18PCIE_13 VDDA18PCIE_14 VDDA18PCIE_15
VDD18_1 VDD18_2 VDD18_MEM1(NC) VDD18_MEM2(NC)
U3F
U3F
VSSAHT1 VSSAHT2 VSSAHT3 VSSAHT4 VSSAHT5 VSSAHT6 VSSAHT7 VSSAHT8 VSSAHT9 VSSAHT10 VSSAHT11 VSSAHT12 VSSAHT13 VSSAHT14 VSSAHT15 VSSAHT16 VSSAHT17 VSSAHT18 VSSAHT19 VSSAHT20 VSSAHT21 VSSAHT22 VSSAHT23 VSSAHT24 VSSAHT25 VSSAHT26 VSSAHT27
VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34
PART 5/6
PART 5/6
RS780M_FCBGA528880MR1@
RS780M_FCBGA528880MR1@
PART 6/6
PART 6/6
RS780M_FCBGA528880MR1@
RS780M_FCBGA528880MR1@
VDDPCIE_1 VDDPCIE_2 VDDPCIE_3 VDDPCIE_4 VDDPCIE_5 VDDPCIE_6 VDDPCIE_7 VDDPCIE_8
VDDPCIE_9 VDDPCIE_10 VDDPCIE_11 VDDPCIE_12 VDDPCIE_13 VDDPCIE_14 VDDPCIE_15 VDDPCIE_16 VDDPCIE_17
VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8
VDDC_9 VDDC_10 VDDC_11 VDDC_12
POWER
POWER
VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22
VDD_MEM1(NC) VDD_MEM2(NC) VDD_MEM3(NC) VDD_MEM4(NC) VDD_MEM5(NC) VDD_MEM6(NC)
VDD33_1(NC) VDD33_2(NC)
VSSAPCIE1 VSSAPCIE2 VSSAPCIE3 VSSAPCIE4 VSSAPCIE5 VSSAPCIE6 VSSAPCIE7 VSSAPCIE8
VSSAPCIE9 VSSAPCIE10 VSSAPCIE11 VSSAPCIE12 VSSAPCIE13 VSSAPCIE14 VSSAPCIE15 VSSAPCIE16 VSSAPCIE17 VSSAPCIE18 VSSAPCIE19 VSSAPCIE20 VSSAPCIE21 VSSAPCIE22 VSSAPCIE23 VSSAPCIE24 VSSAPCIE25 VSSAPCIE26 VSSAPCIE27 VSSAPCIE28 VSSAPCIE29 VSSAPCIE30
GROUND
GROUND
VSSAPCIE31 VSSAPCIE32 VSSAPCIE33 VSSAPCIE34 VSSAPCIE35 VSSAPCIE36 VSSAPCIE37 VSSAPCIE38 VSSAPCIE39 VSSAPCIE40
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9
VSS10
2A
L11 0_0805_5%L11 0_0805_5%
+1.1VS
1 1
+1.1VS
+1.8VS
2 2
+1.8VS
1
2
3 3
4 4
12
1
C165
C165
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
2A < IO power for HyperTransport receive interface >
L13 0_0805_5%L13 0_0805_5%
12
C179
C179 10U_0805_10V4Z
10U_0805_10V4Z
2A < IO power for HyperTransport transmit interface >
L14 0_0805_5%L14 0_0805_5%
12
1
C1127
C1127
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
2A < 1.8V IO power for PCI-E graphics, SB, and GPP interfaces >
L15 0_0805_5%L15 0_0805_5%
12
1
C181
C181
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
C197
C197 1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C166
C166
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C164
C164
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C175
C175
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C1128
C1128
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
< Digital IO power for HyperTransport interface >
1
C167
C167
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C169
C169
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C176
C176
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C185
C185
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C168
C168
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C170
C170
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C177
C177
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C190
C190
0.1U_0402_16V7K
0.1U_0402_16V7K
2
< 1.8V IO transform power >
1
C159
C159
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C161
C161
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C178
C178
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C186
C186
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C192
C192
0.1U_0402_16V7K
0.1U_0402_16V7K
2
+VDDHT
+VDDHTRX
+VDDHTTX
+VDDA18PCIE
< Main IO power for PCI-E graphics, SB, and GPP interfaces >
+VDDA11PCIE
A6 B6 C6
VDDA_12=2.5A
A2 B1 D3 D5 E4 G1 G2 G4 H7 J4 R7 L1 L2 L4 L7 M6 N4 P6 R1 R2 R4 V7 U4 V8 V6 W1 W2 W4 W7 W8 Y6 AA4 AB5 AB1 AB7 AC3 AC4 AE1 AE4 AB2
AE14 D11 G8 E14 E15 J15 J12 K14 M11 L15
D6 E6 F6 G7 H8 J9 K9 M9 L9 P9 R9 T9 V9 U9
K12 J14 U16 J11 K15 M12 L14 L11 M13 M15 N12 N14 P11 P13 P14 R12 R15 T11 T15 U12 T14 J16
AE10 AA11 Y11 AD10 AB10 AC10
H11 H12
< 3.3V IO power >
1
C198
C198
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C1601U_0402_6.3V4Z C1601U_0402_6.3V4Z
C1741U_0402_6.3V4Z C1741U_0402_6.3V4Z
C1731U_0402_6.3V4Z C1731U_0402_6.3V4Z
1
1
2
2
C1910.1U_0402_16V7K C1910.1U_0402_16V7K
C1820.1U_0402_16V7K C1820.1U_0402_16V7K
C1870.1U_0402_16V7K C1870.1U_0402_16V7K
2
2
1
1
C1621U_0402_6.3V4Z C1621U_0402_6.3V4Z
1
1
2
2
C1930.1U_0402_16V7K C1930.1U_0402_16V7K
2
2
1
1
C1630.1U_0402_16V7K C1630.1U_0402_16V7K
C11260.1U_0402_16V7K C11260.1U_0402_16V7K
2
1
C1940.1U_0402_16V7K C1940.1U_0402_16V7K
C1800.1U_0402_16V7K C1800.1U_0402_16V7K
C1880.1U_0402_16V7K C1880.1U_0402_16V7K
2
2
1
1
1
C199
C199
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1 2
C17210U_0805_10V4Z C17210U_0805_10V4Z
C17110U_0805_10V4Z C17110U_0805_10V4Z
2
1
+NB_CORE
L44FBMA-L11-201209-221LMA30T_0805 L44FBMA-L11-201209-221LMA30T_0805
+1.1VS
VDD_CORE:GM=5A/PM=10A< Core power >
@
@
C1129 Co-layout with C189
C1830.1U_0402_16V7K C1830.1U_0402_16V7K
C1950.1U_0402_16V7K C1950.1U_0402_16V7K
2
2
1
1
+3VS
1
2
C18410U_0805_10V4Z C18410U_0805_10V4Z
2
1
1
1
C19610U_0805_10V4Z C19610U_0805_10V4Z
C189330U_D2E_2.5VM
C189330U_D2E_2.5VM
+
+
2
2
+NB_CORE
1
+
+
2
C1129
C1129 330U_2.5V_M
330U_2.5V_M
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2009-02-12 2009-02-12
2009-02-12 2009-02-12
2009-02-12 2009-02-12
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
401871
401871
401871
14 52Wednesday, May 19, 2010
14 52Wednesday, May 19, 2010
14 52Wednesday, May 19, 2010
E
B
B
B
of
of
of
A
B
C
D
E
< RS880 VSYNC mux at CRT_VSYNC pull High to 3K >
< VSYNC : STRAP_DEBUG_BUS_GPIO_ENABLEb >
Enables the Test Debug Bus using GPIO.
R92
R92 3K_0402_5%
3K_0402_5%
UMA_CRT_VSYNC<12>
1 1
12
R93
R93 3K_0402_5%@
3K_0402_5%@
12
< RS880 use register to control PCI-E configure >
< RS880 SUS_STAT# >
R85
R85 150_0402_1%
150_0402_1%
PLT_RST# <12,19,25,27,30,31,34>
D1
D1 CH751H-40PT_SOD323-2@
CH751H-40PT_SOD323-2@
1 2
AUX_CAL<12>
2 2
SUS_STAT#<12,20>
2 1
< RS880 use HSYNC to enable SIDE PORT (internal pull high) >
1 : Disable (RX881, RS880)
+3VS
0 : Enable (RX881, RS880)
PIN: RS880--> VSYNC#
< DFT_GPIO[4:2] : STRAP_PCIE_GPP_CFG[2:0] >
These pin straps are used to configure PCI-E GPP mode. 000 : 00001 001 : 00010 010 : 01011 011 : 00100 100 : 01010 101 : 01100 111 : 01011
< SUS_SATA# : LOAD_EEPROM_STRAPS >
Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values 0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected
RS880:SUS_STAT#
< HSYNC : STRAP_DEBUG_BUS_PCIE_ENABLEb >
RX881: Enables the Test Debug Bus using PCIE bus
R94
R94 3K_0402_5%
3K_0402_5%
UMA_CRT_HSYNC<12>
12
+3VS
1 : Disable ( Can still be enabled using nbcfg register access ) 0 : Enable
RS880: Enables Side port memory ( RS780 use HSYNC#)
1. Disable (RS880) 0 : Enable (RS880)
3 3
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2009-02-12 2009-02-12
2009-02-12 2009-02-12
2009-02-12 2009-02-12
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
401871
401871
401871
15 52Wednesday, May 19, 2010
15 52Wednesday, May 19, 2010
15 52Wednesday, May 19, 2010
E
B
B
B
of
of
of
A
B
< CRT CONNECTOR >
C
+5VS
D
D7
D7
2 3
1
RB491D_SOT23-3
RB491D_SOT23-3
+R_CRT_VCC
F1
F1 1A_6VDC_MINISMDC110
1A_6VDC_MINISMDC110
21
E
+CRT_VCC
1
C237
C237
0.1U_0402_16V4Z@
0.1U_0402_16V4Z@
2
1
C244
C244 6P_0402_50V8K
6P_0402_50V8K
2
1
2
2
C247
C247 10P_0402_50V8J@
10P_0402_50V8J@
1
D21
D21
DAN217_SC59@
DAN217_SC59@
3
RED_L
GREEN_L
BLUE_L
+3VS
RED_L D_DDCDATA
GREEN_L HSYNC
+CRT_VCC
HSYNC
VSYNC
1
C248
C248 10P_0402_50V8J@
10P_0402_50V8J@
2
BLUE_L VSYNC
D_DDCCLK
< SYNC SIGNAL >
JCRT
JCRT
6
RGND
11
ID0
1
Red
7
GGND
12
SDA
2
Green
8
BGND
13
Hsync
3
Blue
9
+5V
14
Vsync
4
res
10
SGND
15
SCL
5
GND
16
GND
17
GND
SUYIN_070546FR015S263ZR@
SUYIN_070546FR015S263ZR@
1
D19
D19
DAN217_SC59@
2
3
C242
C242 6P_0402_50V8K
6P_0402_50V8K
R817
R817 10K_0402_5%
10K_0402_5%
D_HSYNC
D_VSYNC
DAN217_SC59@
1 1
L22
L22 NBQ100505T-800Y-N_2P
NBQ100505T-800Y-N_2P L23
L23 NBQ100505T-800Y-N_2P
NBQ100505T-800Y-N_2P L24
L24 NBQ100505T-800Y-N_2P
NBQ100505T-800Y-N_2P
+CRT_VCC
1
5
P
4
OE#
A2Y
G
U5
U5 SN74AHCT1G125GW_SOT353-5
SN74AHCT1G125GW_SOT353-5
3
+CRT_VCC
1
5
P
4
OE#
A2Y
G
U6
U6 SN74AHCT1G125GW_SOT353-5
SN74AHCT1G125GW_SOT353-5
3
1
2
1 2
12
R100
R100 150_0402_1%
150_0402_1%
RED
GREEN
BLUE
1
C239
C239 6P_0402_50V8K
6P_0402_50V8K
2
R_HSYNC
R_VSYNC
1
C240
C240 6P_0402_50V8K
6P_0402_50V8K
2
C245 0.1U_0402_16V4ZC245 0.1U_0402_16V4Z
RED<35>
GREEN<35>
BLUE<35>
R98
R98 150_0402_1%
150_0402_1%
12
R99
R99 150_0402_1%
150_0402_1%
12
2 2
R_HSYNC<35,42>
R_VSYNC<35,42>
1 2
1 2
1 2
1 2
1
C241
C241 6P_0402_50V8K
6P_0402_50V8K
2
1
D20
D20
DAN217_SC59@
DAN217_SC59@
2
3
1
C243
C243 6P_0402_50V8K
6P_0402_50V8K
2
L25 10_0402_5%L25 10_0402_5%
1 2
L26 10_0402_5%L26 10_0402_5%
1 2
12
R805
R805 2K_0402_1%
2K_0402_1%
1
C251
C251 470P_0402_50V8J@
470P_0402_50V8J@
2
Deciphered Date
Deciphered Date
Deciphered Date
+CRT_VCC
12
1
C252
C252 470P_0402_50V8J@
470P_0402_50V8J@
2
D
R806
R806 2K_0402_1%
2K_0402_1%
D_DDCDATA
< Display Data Channel >
D_DDCCLK
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
SCHEMATIC,MB A6054
401871
401871
401871
E
B
B
B
of
of
of
16 52Wednesday, May 19, 2010
16 52Wednesday, May 19, 2010
16 52Wednesday, May 19, 2010
3 3
12
R824
R824
4.7K_0402_5%
4.7K_0402_5%
CRT_DATA<35>
CRT_CLK<35>
4 4
A
CRT_DATA
CRT_CLK
12
12
FOR EMI
C255
C255 33P_0402_50V8K@
33P_0402_50V8K@
C256
C256 33P_0402_50V8K@
33P_0402_50V8K@
B
+3VS
R825
R825
4.7K_0402_5%
4.7K_0402_5%
1 2
+3VS
5
Q32B
Q32B 2N7002KDW_SOT363-6
2N7002KDW_SOT363-6
3
4
+3VS
2
Q32A
Q32A 2N7002KDW_SOT363-6
2N7002KDW_SOT363-6
61
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008-09-25 2009-09-25
2008-09-25 2009-09-25
2008-09-25 2009-09-25
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