Compal LA-6032P NDU01, LA-6032P NDU11 Schematic

A

1 1

B

C

D

E

Compal confidential

2 2

Thin & Light

NDU01/NDU11 LA-6032P REV 1.0 Schematics Document

Mobile AMD ASB2/RS880M/SB820M

2010-03-22 Rev. 1.0

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA-6032P

145Tuesday, March 23, 2010

E

of

1.0

A

B

C

D

E

Compal Confidential

Model Name : NDU01(11.3)-S/NDU11(13.6)-M

File Name : LA-6032P

1 1

Fan Control

CRT

page 17

LCD Conn.

page 18

page 5

AMD ASB2 CPU

BGA-812 Package

page 5,6,7,8

Hyper Transport Link 2.6GHz

16X16

ATI

RS880M

HDMI Conn.

page 19

page 11,12,13,14,15

2 2

USB/B Right

USB port 0,1

page 29

BT conn

USB port 6

page 29

Int. Camera

USB port 9

page 18

A-Link Express II
4X PCI-E

USB

5V 480MHz

ATI

SB820M

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 800MHZ

PCIe 4 x

1.5V 2.5GHz(250MB/s)

SATA port 0

5V 1.5GHz(150MB/s)

SATA HDD0

ADM1032ARMZ

FUJIN OZ600FJ1

5IN1

PCIe port 1

PCIeMini Card
WLAN (Slot 1)

USB Port 8

RTL8105E
LAN 10/100M

PCIe port 3

PCIeMini Card
WWAN / 3G (Slot2)

USB Port 10 for 3G card

page 25

page 7

200pin DDRIII-SO-DIMM X2

BANK 0, 1, 2, 3

page 30

PCIe Port 2

page 26

page 27

Thermal Sensor

Clock Generator

page 9,10

5IN1

page 30

RJ45

page 17

page 16

SLG8SP626

page 26

SATA port 3

5V 1.5GHz(150MB/s)

USB port 2

5V 480MHz

3.3V 24.576MHz/48Mhz

GSENSOR

page 32

G-Sensor Controller

R5F211B4D34SP

LPC BUS

3.3V 33 MHz

ENE KB926 D3

SPI ROM

page 20,21,22,23,24

HD Audio

page 31

page 32

EC
SMBUS

page 33

SPI ROM

page 34

Debug Port

page 32

Int.KBD

page 32

3 3

RTC CKT.

page 20

Right USB&Audio/B
LS-6031P

page 29

RJ45&VGA/B

Power On/Off CKT.

page 33

DC/DC Interface CKT.

page 34

LS-6032P

HD/B
LS-6033P

LED/B
LS-6034P

Power Circuit DC/DC

4 4

page 37,38,39.40
41,42,43,44

Touch Pad BTN/B
LS-6035P(13.3)

page 17

page 25

page 33

page 33

Touch Pad BTN/B
LS-6037P(11.6)

page 32

eSATA

page 25

Int.

MIC CONN

page 18

HDA Codec

ALC259Q

page 28

page 29 page 29 page 29

HP CONN

SPK CONNMIC CONN

PWR BTN
LS-6036P

A

page 33

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE CO MPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. N EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

Title

Size Document Num ber Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Block Diagram

LA-6032P

E

of

245Tuesday, March 23, 2010

1.0

A

B+

SUSP

N-CHANNEL

1 1

SI4800BDY

SUSP#

MP2121DQ

TPS51125RGER

SUSP

N-CHANNEL

SI4800BDY

2 2

B

DESIGN CURRENT 0.1A

DESIGN CURRENT 0.1A

DESIGN CURRENT 4.5A

DESIGN CURRENT 2A

+5VS

LDO

G9191

ENVDD

P-CHANNEL

AO-3413

BT_PWR#

P-CHANNEL

AO-3413

WOL_EN#

P-CHANNEL

AO-3413

DESIGN CURRENT 300mA

DESIGN CURRENT 1.5A

DESIGN CURRENT 1A

DESIGN CURRENT 4A

DESIGN CURRENT 1.0A

DESIGN CURRENT 180mA

DESIGN CURRENT 500mA

C

+3VL
+5VL
+5VALW

+5VS

+3VS_HDP

+1.8VS

+3VALW

+3VS

+LCD_VDD

+BT_VCC

+3V_LAN

D

E

LDO

APL5508

POK

RT8209BGQW

3 3

VR_ON

VGATE#

N-CHANNEL

IRF8113PBF

VLDT_EN#

N-CHANNEL

IRF8113PBF

ISL6265

SYSON

RT8209BGQW

4 4

SUSP

N-CHANNEL

IRF8113PBF

SUSP

LDO

G2992F1U

VR_ON#

LDO

G2992F1U

DESIGN CURRENT 300mA

DESIGN CURRENT 0.3A

DESIGN CURRENT 6.5A

DESIGN CURRENT 7.6A

DESIGN CURRENT 15A

DESIGN CURRENT 2A

DESIGN CURRENT 7A

DESIGN CURRENT 1A

DESIGN CURRENT 0.5A

DESIGN CURRENT 1.5A

+2.5VS

+1.1VALW

+1.1VS

+NB_CORE

+CPU_CORE0

+VDDNB

+1.5V

+1.5VS

+0.75VS

+0.9V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/04/14 2009/04/14

C

Compal Secret Dat a

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

D

Date: Sheet

Power Map

LA-5381P

E

1.0

of

345Tuesday, March 23, 2010

A

Voltage Rails

1 1

State

O MEANS ON X MEANS OFF

power
plane

+RTCVCC

B+

+3VL

+5VL

+3VALW

+1.1VALW

B

+5VS

+3VS

+2.5VS

+1.8VS

+1.5VS

+1.5V+5VALW

+1.1VS

+0.9VS

+0.75VS
+NB_CORE

+VDDNB

+CPU_CORE_0

GSENSOR@ : means just reserve for G sensor part

1STGSENSOR@ : means just reserve 1st G sensor IC

C

Symbol Note :

: means Digital Ground : means Analog Ground

@ : means just reserve , no build
K625R3@ : means just for 1.5G CPU
K125R3@ : means just for 1.7G CPU
K325R3@ : means just for 1.3G CPU
K625R1@ : means just for 1.5G CPU
K125R1@ : means just for 1.7G CPU
K325R1@ : means just for 1.3G CPU

M@ : means just reserve for 13.3 control
S@ : means just reserve for 11.6 control

1ST@ : means just reserve 1st G sensor IC

D

U1
K125 CPU

K625R3@

E

For 11.6 and 13.3 DAZ

ZZZ

PCB-MB

K125 mean 1.7G CPU

U1

K125R1@

K125 CPU

K125 mean 1.7G CPU K325 mean 1.3G CPUK625 mean 1.7G CPU

U1

K125R3@

K125 CPU

RS880M SB820M

U5

RS880MR3@

RS880M

K325 mean 1.3G CPU

U1
K325 CPU

U1
K325 CPU

U7
SB820M

K325R1@

K325R3@

SB820MR3@

2ND@ : means just reserve 2nd G sensor IC

2NDGSENSOR@ : means just reserve 2nd G sensor IC

S0

2 2

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

O

O

O

O

O

X

O

O

O

O

X

O

XX

X

OO

OO

X

X

XX X

NOSIDE@ : means just reserve NOSIDE

SIDE@ : means just reserve SIDE port
RS880MR1@ : means just for RS880MR1
RS880MR3@ : means just for RS880MR3
SB820MR1@ : means just for SB820MR1
SB820MR3@ : means just for SB820MR3

SB SM Bus1 Address

HEX

A0 H

D2 H

Address

1010 0000 b

1010 0100 bA4 H

1101 0010 b

Power

3 3

+3VS

+3VS

+3VS

Device

DDR SO-DIMM 0

DDR SO-DIMM 1

Clock Generator

EC SM Bus1 Address

Device Address Address

+3VL +3VS

4 4

HEX HEX

16 H

0001 011X bSmart Battery

A

PowerPower

+3VS

SB SM Bus2 Address

DevicePower

+3VALW

WLAN/WIMAX

EC SM Bus2 Address

Device

G-Sensor

B

HEX Address

98 H

1001 100X bCPU_ADM1032-1

SMBUS Control Table

SOURCE

EC_SMB_CK1

EC_SMB_DA1

EC_SMB_CK2

EC_SMB_DA2

I2C_CLK

I2C_DATA

DDC_CLK0

DDC_DATA0

SCL0

SDA0

SCL1

SDA1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

KB926

KB926

RS880M

RS880M

SB820

SB820

2008/04/14 2009/04/14

BATT

V

Compal Secret Data

Deciphered Date

CPU

THERMAL

SENSOR

V

D

SODIMM

I / II

CLK
GEN

VV

Custom

Date: Sheet

WLAN

LCD
DDC
ROM

DDC
ROM

G-sensor

HDMI

V

V

V

V

Title

Size Document Number Rev

Compal Electronics, Inc.

Notes List

LA-6032P

445Tuesday, March 23, 2010

E

of

1.0

A

1 1

B

C

D

E

H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8
H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4
H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0

H_CLKOP1
H_CLKON1

H_CLKOP0
H_CLKON0

H_CTLOP1
H_CTLON1

H_CTLOP0
H_CTLON0

H_CADOP[0..15]

H_CADON[0..15]

H_CADOP[0..15] 11

H_CADON[0..15] 11H_CADIN[0..15]11

H_CLKOP1 11
H_CLKON1 11

H_CLKOP0 11
H_CLKON0 11

H_CTLOP1 11
H_CTLON1 11

H_CTLOP0 11
H_CTLON0 11

FAN Control Circuit

+5VS

1A

12

@

1SS355_SOD323-2

2

1

D1

12

2

@

D2

1

1SS355_SOD323-2

+FAN1

C2
1000P_0402_50V7K

@

@

C1

10U_0805_10V6K

U2

1

EN

2

EN_DFAN131

+FAN1

1

2

3
4

APL5607KI-TRG_SO8
C3
10U_0805_10V6K

VIN
VOUT
VSET

GND
GND
GND
GND

8
7
6
5

1
2
3

4
5

ACES_88231-03041

10K_0402_5%

2

C4

0.01U_0402_25V7K

1

JFAN1

1
2
3

GND
GND

R1

@

12

+3VS

FAN_SPEED1 31

H_CADIP[0..15]11

2 2

3 3

H_CLKIP111
H_CLKIN111

H_CLKIP011
H_CLKIN011

H_CTLIP111
H_CTLIN111

H_CTLIP011
H_CTLIN011

H_CADIP[0..15]

H_CADIN[0..15]

H_CADIP15
H_CADIN15
H_CADIP14
H_CADIN14
H_CADIP13
H_CADIN13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10
H_CADIP9
H_CADIN9
H_CADIP8
H_CADIN8
H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0

H_CLKIP1
H_CLKIN1

H_CLKIP0
H_CLKIN0

H_CTLIP1
H_CTLIN1

H_CTLIP0
H_CTLIN0

U1A

W7

L0_CADIN_H15

W6

L0_CADIN_L15

U6

L0_CADIN_H14

U5

L0_CADIN_L14

R7

L0_CADIN_H13

R6

L0_CADIN_L13

P6

L0_CADIN_H12

P5

L0_CADIN_L12

L6

L0_CADIN_H11

L5

L0_CADIN_L11

J6

L0_CADIN_H10

J5

L0_CADIN_L10

H4

L0_CADIN_H9

H3

L0_CADIN_L9

G6

L0_CADIN_H8

G5

L0_CADIN_L8

T3

L0_CADIN_H7

T4

L0_CADIN_L7

T2

L0_CADIN_H6

T1

L0_CADIN_L6

P3

L0_CADIN_H5

P4

L0_CADIN_L5

P2

L0_CADIN_H4

P1

L0_CADIN_L4

M2

L0_CADIN_H3

M1

L0_CADIN_L3

K3

L0_CADIN_H2

K4

L0_CADIN_L2

K2

L0_CADIN_H1

K1

L0_CADIN_L1

H2

L0_CADIN_H0

H1

L0_CADIN_L0

M8

L0_CLKIN_H1

M7

L0_CLKIN_L1

M3

L0_CLKIN_H0

M4

L0_CLKIN_L0

Y6

L0_CTLIN_H1

Y5

L0_CTLIN_L1

V2

L0_CTLIN_H0

V1

L0_CTLIN_L0

TMK625DBV23GM_FCBGA812

K625@

L0_CADOUT_H15

L0_CADOUT_L15

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H9

L0_CADOUT_L9

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H6

HT LINK

L0_CADOUT_L6

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H0

L0_CADOUT_L0

L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

AB6
AB5
AB9
AB8
AC7
AC6
AE6
AE5
AE9
AE8
AH3
AH4
AK3
AK4
AH1
AH2
Y1
Y2
Y4
Y3
AB1
AB2
AB4
AB3
AD4
AD3
AF1
AF2
AF4
AF3
AK1
AK2

AF6
AF5

AD1
AD2

Y8
Y9

V4
V3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

AMD CPU S1G2 HT I/F

LA-6032P

545Tuesday, March 23, 2010

E

of

1.0

A

B

C

D

E

DDR_B_MA[15..0]10

1 1

DDR_B_BS#210
DDR_B_BS#110
DDR_B_BS#010

DDR_B_DQS710
DDR_B_DQS#710
DDR_B_DQS610
DDR_B_DQS#610
DDR_B_DQS510
DDR_B_DQS#510

2 2

3 3

DDR_B_DQS410
DDR_B_DQS#410
DDR_B_DQS310
DDR_B_DQS#310
DDR_B_DQS210
DDR_B_DQS#210
DDR_B_DQS110
DDR_B_DQS#110
DDR_B_DQS010
DDR_B_DQS#010

DDR_B_CLK010

DDR_B_CLK#010

DDR_B_CLK110

DDR_B_CLK#110

DDR_CKE1_DIMMB10
DDR_CKE0_DIMMB10

DDR_B_ODT110
DDR_B_ODT010

DDR_CS1_DIMMB#10
DDR_CS0_DIMMB#10

DDR_B_RAS#10
DDR_B_CAS#10

DDR_B_WE#10

MEM_MB_RST#10 MEM_MA_RST#9

+1.5V

1 2

R792 1K_0402_5%

DDR_B_MA15
DDR_B_MA14
DDR_B_MA13
DDR_B_MA12
DDR_B_MA11
DDR_B_MA10
DDR_B_MA9
DDR_B_MA8
DDR_B_MA7
DDR_B_MA6
DDR_B_MA5
DDR_B_MA4
DDR_B_MA3
DDR_B_MA2
DDR_B_MA1
DDR_B_MA0

DDR_B_BS#2
DDR_B_BS#1
DDR_B_BS#0

DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS0
DDR_B_DQS#0

DDR_B_CLK0

DDR_B_CLK#0

DDR_B_CLK1

DDR_B_CLK#1

DDR_CKE1_DIMMB
DDR_CKE0_DIMMB

DDR_B_ODT1
DDR_B_ODT0

DDR_CS1_DIMMB#
DDR_CS0_DIMMB#

DDR_B_RAS#
DDR_B_CAS#

DDR_B_WE#

MB_EVENT_L

U1C

P33

MB_ADD15

P31

MB_ADD14

AJ33

MB_ADD13

T32

MB_ADD12

T31

MB_ADD11

AD32

MB_ADD10

T33

MB_ADD9

V32

MB_ADD8

U33

MB_ADD7

V33

MB_ADD6

V31

MB_ADD5

W33

MB_ADD4

Y31

MB_ADD3

Y33

MB_ADD2

Y32

MB_ADD1

AC33

MB_ADD0

R33

MB_BANK2

AD33

MB_BANK1

AE33

MB_BANK0

K33

MB_CHECK7

K31

MB_CHECK6

G32

MB_CHECK5

F32

MB_CHECK4

L33

MB_CHECK3

K32

MB_CHECK2

H31

MB_CHECK1

G33

MB_CHECK0

J33

MB_DQS_H8

H32

MB_DQS_L8

AM14

MB_DQS_H7

AN14

MB_DQS_L7

AL20

MB_DQS_H6

AM20

MB_DQS_L6

AN26

MB_DQS_H5

AM26

MB_DQS_L5

AN30

MB_DQS_H4

AM30

MB_DQS_L4

D33

MB_DQS_H3

D32

MB_DQS_L3

B28

MB_DQS_H2

A28

MB_DQS_L2

A21

MB_DQS_H1

B20

MB_DQS_L1

B16

MB_DQS_H0

A15

MB_DQS_L0

AN22

MB_CLK_H7

AM22

MB_CLK_L7

AN21

MB_CLK_H6

AM21

MB_CLK_L6

AA32

MB_CLK_H5

AA33

MB_CLK_L5

AB33

MB_CLK_H4

AB32

MB_CLK_L4

AB31

MB_CLK_H3

AB30

MB_CLK_L3

AD31

MB_CLK_H2

AD30

MB_CLK_L2

C22

MB_CLK_H1

B22

MB_CLK_L1

A22

MB_CLK_H0

A23

MB_CLK_L0

N33

MB_CKE1

P32

MB_CKE0

AK31

MB1_ODT1

AH31

MB1_ODT0

AK32

MB0_ODT1

AH33

MB0_ODT0

AK33

MB1_CS_L1

AF33

MB1_CS_L0

AJ32

MB0_CS_L1

AF31

MB0_CS_L0

AF32

MB_RAS_L

AH32

MB_CAS_L

AG33

MB_WE_L

L32

MB_RESET_L

M33

FREE|MB_EVENT_L

TMK625DBV23GM_FCBGA812

DDR III: CHANNEL B

MB_DATA63
MB_DATA62
MB_DATA61
MB_DATA60
MB_DATA59
MB_DATA58
MB_DATA57
MB_DATA56
MB_DATA55
MB_DATA54
MB_DATA53
MB_DATA52
MB_DATA51
MB_DATA50
MB_DATA49
MB_DATA48
MB_DATA47
MB_DATA46
MB_DATA45
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
MB_DATA36
MB_DATA35
MB_DATA34
MB_DATA33
MB_DATA32
MB_DATA31
MB_DATA30
MB_DATA29
MB_DATA28
MB_DATA27
MB_DATA26
MB_DATA25
MB_DATA24
MB_DATA23
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
MB_DATA18
MB_DATA17
MB_DATA16
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
MB_DATA11
MB_DATA10

MB_DATA9
MB_DATA8
MB_DATA7
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
MB_DATA2
MB_DATA1
MB_DATA0

MB_DM8
MB_DM7
MB_DM6
MB_DM5
MB_DM4
MB_DM3
MB_DM2
MB_DM1
MB_DM0

AN13
AL14
AL16
AN17
AN12
AM12
AM16
AN16
AL18
AN19
AM24
AN24
AM18
AN18
AL22
AN23
AM25
AL26
AN28
AL28
AL24
AN25
AN27
AM28
AM29
AL30
AL32
AL33
AK28
AN29
AM31
AM32
E33
D31
B31
A31
F33
F31
C32
B32
C30
A29
B26
A26
B30
A30
A27
C26
A24
B24
C18
A18
A25
C24
C20
A19
C16
A16
B14
A13
B18
A17
C14
A14

H33
AN15
AN20
AK26
AN31
C33
C28
A20
D14

K625@

DDR_B_D63
DDR_B_D62
DDR_B_D61
DDR_B_D60
DDR_B_D59
DDR_B_D58
DDR_B_D57
DDR_B_D56
DDR_B_D55
DDR_B_D54
DDR_B_D53
DDR_B_D52
DDR_B_D51
DDR_B_D50
DDR_B_D49
DDR_B_D48
DDR_B_D47
DDR_B_D46
DDR_B_D45
DDR_B_D44
DDR_B_D43
DDR_B_D42
DDR_B_D41
DDR_B_D40
DDR_B_D39
DDR_B_D38
DDR_B_D37
DDR_B_D36
DDR_B_D35
DDR_B_D34
DDR_B_D33
DDR_B_D32
DDR_B_D31
DDR_B_D30
DDR_B_D29
DDR_B_D28
DDR_B_D27
DDR_B_D26
DDR_B_D25
DDR_B_D24
DDR_B_D23
DDR_B_D22
DDR_B_D21
DDR_B_D20
DDR_B_D19
DDR_B_D18
DDR_B_D17
DDR_B_D16
DDR_B_D15
DDR_B_D14
DDR_B_D13
DDR_B_D12
DDR_B_D11
DDR_B_D10
DDR_B_D9
DDR_B_D8
DDR_B_D7
DDR_B_D6
DDR_B_D5
DDR_B_D4
DDR_B_D3
DDR_B_D2
DDR_B_D1
DDR_B_D0

DDR_B_DM7
DDR_B_DM6
DDR_B_DM5
DDR_B_DM4
DDR_B_DM3
DDR_B_DM2
DDR_B_DM1
DDR_B_DM0

DDR_B_D[63..0] 10

DDR_B_DM[7..0] 10

DDR_A_MA[15..0]9

DDR_A_BS#29
DDR_A_BS#19
DDR_A_BS#09

DDR_A_DQS79

DDR_A_DQS#79

DDR_A_DQS69

DDR_A_DQS#69

DDR_A_DQS59

DDR_A_DQS#59

DDR_A_DQS49

DDR_A_DQS#49

DDR_A_DQS39

DDR_A_DQS#39

DDR_A_DQS29

DDR_A_DQS#29

DDR_A_DQS19

DDR_A_DQS#19

DDR_A_DQS09

DDR_A_DQS#09

DDR_A_CLK09

DDR_A_CLK#09

DDR_A_CLK19

DDR_A_CLK#19

DDR_CKE1_DIMMA9
DDR_CKE0_DIMMA9

DDR_A_ODT19
DDR_A_ODT09

DDR_CS1_DIMMA#9
DDR_CS0_DIMMA#9

DDR_A_RAS#9
DDR_A_CAS#9
DDR_A_WE#9

+1.5V

1 2

R793 1K_0402_5%

DDR_A_MA15
DDR_A_MA14
DDR_A_MA13
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0

DDR_A_BS#2
DDR_A_BS#1
DDR_A_BS#0

DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS0
DDR_A_DQS#0

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1

DDR_CKE1_DIMMA
DDR_CKE0_DIMMA

DDR_A_ODT1

DDR_CS1_DIMMA#
DDR_CS0_DIMMA#

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

MA_EVENT_L

U1B

P30

MA_ADD15

M29

MA_ADD14

AG28

MA_ADD13

P28

MA_ADD12

T30

MA_ADD11

AC28

MA_ADD10

P27

MA_ADD9

R26

MA_ADD8

R27

MA_ADD7

U28

MA_ADD6

V30

MA_ADD5

U27

MA_ADD4

Y30

MA_ADD3

AB29

MA_ADD2

W29

MA_ADD1

AC26

MA_ADD0

R29

MA_BANK2

AC29

MA_BANK1

AE28

MA_BANK0

K30

MA_CHECK7

J29

MA_CHECK6

G29

MA_CHECK5

F29

MA_CHECK4

L28

MA_CHECK3

L29

MA_CHECK2

H29

MA_CHECK1

H27

MA_CHECK0

J27

MA_DQS_H8

J26

MA_DQS_L8

AJ11

MA_DQS_H7

AK12

MA_DQS_L7

AG15

MA_DQS_H6

AH15

MA_DQS_L6

AH22

MA_DQS_H5

AG22

MA_DQS_L5

AG26

MA_DQS_H4

AH26

MA_DQS_L4

E28

MA_DQS_H3

F28

MA_DQS_L3

E25

MA_DQS_H2

F25

MA_DQS_L2

G17

MA_DQS_H1

H17

MA_DQS_L1

E12

MA_DQS_H0

F12

MA_DQS_L0

AK18

MA_CLK_H7

AJ17

MA_CLK_L7

AH17

MA_CLK_H6

AG17

MA_CLK_L6

Y28

MA_CLK_H5

Y27

MA_CLK_L5

AB27

MA_CLK_H4

AB26

MA_CLK_L4

W27

MA_CLK_H3

W26

MA_CLK_L3

P26

MA_CLK_H2

M26

MA_CLK_L2

D18

MA_CLK_H1

F19

MA_CLK_L1

E20

MA_CLK_H0

E19

MA_CLK_L0

M30

MA_CKE1

M28

MA_CKE0

AJ29

MA1_ODT1

AF27

MA1_ODT0

AJ30

MA0_ODT1

AG29

MA0_ODT0

AH29

MA1_CS_L1

AE29

MA1_CS_L0

AH30

MA0_CS_L1

AF29

MA0_CS_L0

AC27

MA_RAS_L

AF30

MA_CAS_L

AE27

MA_WE_L

L27

MA_RESET_L

M32

FREE|MA_EVENT_L

TMK625DBV23GM_FCBGA812

DDR III: CHANNEL A

MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10

MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0

MA_DM8
MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0

AG11
AH11
AJ12
AJ14
AF11
AF12
AG12
AH12
AK14
AF15
AH19
AK20
AF14
AG14
AF17
AG19
AG20
AJ20
AF22
AK24
AF19
AF20
AJ23
AG23
AF23
AF25
AH27
AK30
AJ25
AG25
AJ26
AJ28
D28
G28
D26
E26
F30
E29
F27
H26
H25
D24
H22
E22
F26
G26
D22
G23
G22
G20
G15
F15
D20
F22
D16
E17
H15
H14
G12
H12
E15
E14
E11
F11

H30
AL12
AK16
AK22
AJ27
E27
E23
H19
G14

K625@

DDR_A_D63
DDR_A_D62
DDR_A_D61
DDR_A_D60
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D55
DDR_A_D54
DDR_A_D53
DDR_A_D52
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_A_D47
DDR_A_D46
DDR_A_D45
DDR_A_D44
DDR_A_D43
DDR_A_D42
DDR_A_D41
DDR_A_D40
DDR_A_D39
DDR_A_D38
DDR_A_D37
DDR_A_D36
DDR_A_D35
DDR_A_D34
DDR_A_D33
DDR_A_D32
DDR_A_D31
DDR_A_D30
DDR_A_D29
DDR_A_D28
DDR_A_D27
DDR_A_D26
DDR_A_D25
DDR_A_D24
DDR_A_D23
DDR_A_D22
DDR_A_D21
DDR_A_D20
DDR_A_D19
DDR_A_D18
DDR_A_D17
DDR_A_D16
DDR_A_D15
DDR_A_D14
DDR_A_D13
DDR_A_D12
DDR_A_D11
DDR_A_D10
DDR_A_D9
DDR_A_D8
DDR_A_D7
DDR_A_D6
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D2
DDR_A_D1
DDR_A_D0

DDR_A_DM7
DDR_A_DM6
DDR_A_DM5
DDR_A_DM4
DDR_A_DM3
DDR_A_DM2
DDR_A_DM1DDR_A_ODT0
DDR_A_DM0

DDR_A_D[63..0] 9

DDR_A_DM[7..0] 9

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

AMD CPU S1G2 DDRII I/F

LA-6032P

645Tuesday, March 23, 2010

E

of

1.0

A

B

C

D

E

1 2

R2 10K_0402_5%

1 2

R3 1K_0402_5%

CPU_THERMTRIP#_R

1 2

R4 300_0402_5%

CPU_PROCHOT #_1.8

+1.5V

+1.1VS

+1.5V

@

@

@

@

R43220_0402_5%

R42220_0402_5%

R41220_0402_5%

R44300_0402_5%

12

12

12

12

D

B

2

E

3 1

MMBT3904_NL_SOT23-3

R5

@

1 2

0_0402_5%

CPU_DBREQ#
CPU_TEST27_SINGLECHAIN

CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN

CPU_TEST15_BP1
CPU_TEST14_BP0

CPU_TEST18_PLLTEST1
CPU_TEST19_PLLTEST0
CPU_TEST23_TSTUPD
CPU_DBRDY

R45300_0402_5%

1 2

CPU_TCK_R
CPU_TMS_R
CPU_TDI_R
CPU_TRST#_R
CPU_TDO_R

CONN@

Title

Size Document Number Rev

Custom

Date: Sheet

D4 CH751H-40PT_SOD323-2

Q1

C

21

CPU_VDDNB_RUN_FB_H

Close to CPU

CPU_SVC

CPU_SVD

R19 300_0402_5%

1 2

R21 1K_0402_5%

1 2

R23 300_0402_5% @

1 2

R24 1K_0402_5%

1 2
1 2

R26 1K_0402_5%

1 2

R27 1K_0402_5%

1 2

R28 300_0402_5% @

1 2

R29 300_0402_5% @

1 2

R30 1K_0402_5%

1 2

R31 1K_0402_5%

1 2

R32 1K_0402_5%

1 2

R34 300_0402_5% @

1 2

JP1

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

2423
26

SAMTEC_ASP-68200-07

R12 1K_0402_5%

R13 1K_0402_5%

+1.5V

@

Compal Electronics, Inc.

AMD CPU S1G2 CTRL

LA-6032P

E

H_THERMTRIP# 21

H_PROCHOT# 20

R9 10_0402_5%

1 2

+VDDNB

1 2

1 2

CPU_TEST26_BURNIN_L

R20 1K_0402_5%

1 2

745Tuesday, March 23, 2010

of

+1.5V

LDT_RST#

1.0

R18

80.6_0402_1%

1 2

T10 PAD@
T11 PAD@

T16 PAD@
T18 PAD@

+1.5V

+1.5V

+2.5VDDA

+2.5VS

@

100U_D2_10VM

1 1

CLK_CPU_BCLK20

CLK_CPU_BCLK#20

+1.5VS

R11
300_0402_5%

1 2

LDT_RST#20

2 2

H_PWRGD20,42

3 3

LDT_STOP#12,20

4 4

C17

1 2

LDT_RST#

1

C11

0.01U_0402_25V7K

2

+1.5VS

1 2

1

2

+1.5VS

1 2

1

2

+3VS

1

C16

2

0.1U_0402_16V4Z

THERMDA_CPU

THERMDC_CPU

2200P_0402_50V7K

A

@

R17
300_0402_5%

H_PWRGD

C13

0.1U_0402_16V7K

R33
300_0402_5%

LDT_STOP#

C14

0.01U_0402_25V7K

@

Thermal Sensor

R8 Close to CPU within 0.6"

L

C9 C10 Close to CPU within 1.2"

U4

1

VDD

2

D+

3

D-

THERM#4GND

ADM1032ARM-1 ZREEL_MSOP8

1 2

C10

1 2

C9 3900P_0402_50V7K

+1.1VALW

+1.5V

+0.9V

L

+1.5V

R802
1K_0402_1%

1 2

R803
1K_0402_1%

1 2

8

SCLK

7

SDATA

6

ALERT#

5

R355 10_0402_5%

R356 10_0402_5%

R357 10_0402_5%

Close to CPU within
1"

L1

1 2

FBM_L11_201209_300L_0805

1

+

C5

2

3900P_0402_50V7K

12

R8
169_0402_1%

@

@

@

0.01U_0402_25V7K

2

C654

1

EC_SMB_CK2 31,32

EC_SMB_DA2 31,32

+1.5V

CPU_VLDT_SENSE

CPU_VDDIO_SENSE

CPU_VDD0_RUN_FB_L42

CPU_VDD0_RUN_FB_H42

CPU_VDDNB_RUN_FB_H42

0.1U_0402_16V7K

@
@
@
@

M_VREF

1

C655

2

1000P_0402_25V8J

B

3300P_0402_50V7K

1

1

C7

C64.7U_0805_10V4Z

2

2

CPU_CLKIN_SC_P
CPU_CLKIN_SC_N

R7 1K_0402_5%

1 2

R10 1K_0402_5%

1 2

C12

@

1 2

1 2

CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

CPU_TEST9_ANALOGIN

R22

1 2

0_0402_5%

T12 PAD
T14 PAD
T15 PAD
T17 PAD

CPU_TEST17_BP3

T22PAD@

CPU_TEST16_BP2

T23PAD@ R25 1K_0402_5%

CPU_TEST15_BP1
CPU_TEST14_BP0

CPU_TEST7_ANALOG_T
CPU_TEST6_DIECRACKMON
CPU_TEST3
CPU_TEST2

+2.5VDDA@250mA

1

C8

0.22U_0603_16V4Z

2

H_PWRGD
LDT_STOP#
LDT_RST#

CPU_SIC
CPU_SID

CPU_TDI
CPU_TRST#
CPU_TCK
CPU_TMS

CPU_DBREQ#

CPU_VDD0_RUN_FB_L
CPU_VLDT_SENSE
CPU_VDD0_RUN_FB_H
CPU_VDDNB_RUN_FB_H
CPU_VDDIO_SENSE
CPU_VDDR_SENSECPU_VDDR_SENSE

M_VREF

R16

39.2_0402_1~D

R35

@

1 2

510_0402_5%

R38

1 2

510_0402_5%

U1D

A8

VDDA_1

B8

VDDA_2

A6

CLKIN_H

A7

CLKIN_L

D10

PWROK

E9

LDTSTOP_L

F9

RESET_L

AN4

SIC

AN5

SID

AM2

RSVD_SA0

AN3

ALERT_L

AM8

TDI

AL8

TRST_L

AK8

TCK

AN8

TMS

G9

DBREQ_L

D2

VSS_SENSE

E2

VLDT_SENSE

E1

VDD_SENSE

D1

VDDNB_SENSE

D3

VDDIO_SENSE

C2

VDDR_SENSE

A11

M_ZP
M_ZN

CPU_TEST25_H_BYPASSCLK_H

CPU_TEST25_L_BYPASSCLK_L

M_VREF

AM9

M_ZN_H

AN9

M_ZN_L

A9

BYPASSCLK_H

B9

BYPASSCLK_L

A5

PLLTEST0

B6

PLLTEST1

G8

ANALOGIN

F8

BP3

C8

BP2

D9

BP1

E8

BP0

C6

ANALOG_T

AH7

DIECRACKMON

AK5

GATE0

AJ7

DRAIN0

TMK625DBV23GM_FCBGA812 K625@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MISC

R36

1 2

510_0402_5%

R39

1 2

510_0402_5%

@

C

RSVD|CORE_TYPE

THERMTRIP_L

PROCHOT_L

CPU_PRESENT_L

FBCLKOUT_H

FBCLKOUT_L

SCANSHIFTEN

SINGLECHAIN

ANALOGOUT

+1.5V

M31

CPU_SVC

C1

SVC

CPU_SVD

B2

SVD

THERMDC_CPU

AL6

THERMDC
THERMDA

TDO

DBRDY

RSVD3

HTREF1
HTREF0

SCANCLK1

TSTUPD

SCANEN

SCANCLK2

PLLCHRZ_H

PLLCHRZ_L

BURNIN_L

DIG_T

M_TEST

THERMDA_CPU

AM5

CPU_THERMTRIP#_R

AK6

CPU_PROCHOT#_1.8

AN6

AN7

CPU_DBRDY

H9

T1 PAD @

AM6

CPU_PRESENT_L

AJ9

CPU_HTREF1

V10

CPU_HTREF0

V9

CPU_TEST29_H_FBCLKOUT_P

B10

CPU_TEST29_L_FBCLKOUT_N

A10

CPU_TEST24_SCANCLK1

AK7

CPU_TEST23_TSTUPD

AG8

CPU_TEST22_SCANSHIFTEN

AK9

CPU_TEST21_SCANEN

AH9

CPU_TEST20_SCANCLK2

AM7

CPU_TEST28_H_PLLCHRZ_P

G11

CPU_TEST28_L_PLLCHRZ_N

H11

CPU_TEST27_SINGLECHAIN

AJ8

CPU_TEST26_BURNIN_L

AM4

CPU_TEST10_ANALOGOUT

D7

CPU_TEST8_DIG_T

B5

AG9

CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

2008/04/14 2009/04/14

CPU_SVC 42
CPU_SVD 42

CPU_TDO

R801 1K_0402_5%

1 2

R14 R15 Close to CPU within 1.5"

L

R14 44.2_0402_1%

1 2

R15 44.2_0402_1%

1 2

R850 0_0402_5%

1 2

R851 0_0402_5%

1 2

R852 0_0402_5%

1 2

R853 0_0402_5%

1 2

R854 0_0402_5%

1 2

Compal Secret Data

Deciphered Date

A

+CPU_CORE_0@15000mA

+CPU_CORE_0 +CPU_CORE_0

1 1

2 2

U1E

D4

VDD_1

D5

VDD_2

D6

VDD_3

E5

VDD_4

E6

VDD_5

E7

VDD_6

F5

VDD_7

F6

VDD_8

F7

VDD_9

H7

VDD_10

H8

VDD_11

J8

VDD_12

E4

VDD_13

J10

VDD_14

J12

VDD_15

J14

VDD_16

J18

VDD_17

J20

VDD_18

J21

VDD_19

J23

VDD_20

J9

VDD_21

K10

VDD_22

K12

VDD_23

K14

VDD_24

K18

VDD_25

K20

VDD_26

K21

VDD_27

K23

VDD_28

N4

VDD_29

L11

VDD_30

L13

VDD_31

L7

VDD_32

L9

VDD_33

M10

VDD_34

M12

VDD_35

R4

VDD_36

M5

VDD_37

N11

VDD_38

N24

VDD_39
VDD_40W4VDD_46

N9

VDD_41

P15

VDD_42

P18

VDD_43

TMK625DBV23GM_FCBGA812

K625@

VDD_85
VDD_84
VDD_83
VDD_82
VDD_81
VDD_80
VDD_79
VDD_78
VDD_77
VDD_76
VDD_75
VDD_74
VDD_73
VDD_72
VDD_71
VDD_70
VDD_69
VDD_68
VDD_67

POWER1

VDD_66
VDD_65
VDD_64
VDD_63
VDD_62
VDD_61
VDD_60
VDD_59
VDD_58
VDD_57
VDD_56
VDD_55
VDD_54
VDD_53
VDD_52
VDD_51
VDD_50
VDD_49
VDD_48
VDD_47

VDD_45
VDD_44

AE12
AD9
AE21
AD21
AD18
AD14
AD12
AD11
AC5
AE18
AC24
AC12
AC10
AB13
AB11
AE14
AA24
AA12
AA10
Y19
Y16
Y14
W5
W20
W18
W15
AE23
V24
V19
V16
V14
T20
T18
T15
T10
R5
R19
R16
R14
AC4
P24
P20

3000mA

VLDT_A&VLDT_B(+1.1VS) decoupling.

+1.1VS

1

C18

4.7U_0805_10V4Z

2

1

C19

4.7U_0805_10V4Z

2

1

C20
22U_0805_6.3V6M

2

1

C21

0.22U_0603_16V4Z

2

1

C22

0.22U_0603_16V4Z

2

B

+1.5V

M27
Y26
U26
N32
U32
N30
P29
R28
R30
R32
U29

U30
W28
W30
W32

Y29

AA30
AB28
AE32
AC30
AC32
AE26
AE30
AF28
AG30
AG32
AD25
AA25
AC25

V25

P25

N25
M25

K25

L25

T25

Y25

AB25

1

C23
180P_0402_50V8J

2

U1F

POWER2

PROGEN_L

1

C24
180P_0402_50V8J

2

VLDT_A_1
VLDT_A_2
VLDT_A_3
VLDT_A_4

VLDT_B_1
VLDT_B_2
VLDT_B_3
VLDT_B_4

VDDR_1
VDDR_2
VDDR_3
VDDR_4

VDDR_5
VDDR_6
VDDR_7
VDDR_8

VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5
VDDNB_6

FREE_1
FREE_2
FREE_3
FREE_4
FREE_5
FREE_6
FREE_7
FREE_8
FREE_9

VDDIO_1
VDDIO_2
VDDIO_3
VDDIO_4
VDDIO_5
VDDIO_6
VDDIO_7
VDDIO_8
VDDIO_9
VDDIO_10
VDDIO_11
VDDIO_12
VDDIO_13
VDDIO_14
VDDIO_15
VDDIO_16
VDDIO_17
VDDIO_18
VDDIO_19
VDDIO_20
VDDIO_21
VDDIO_22
VDDIO_23
VDDIO_24
VDDIO_25
VDDIO_26
VDDIO_27
VDDIO_28
VDDIO_29
VDDIO_30
VDDIO_31
VDDIO_32
VDDIO_33
VDDIO_34
VDDIO_35
VDDIO_36
VDDIO_37
VDDIO_38

TMK625DBV23GM_FCBGA812

K625@

+1.1VS

F1
F2

+1.1VS@1500mA

F3
F4

AL1
AL2
AL3
AL4

A12
B12
C12
D12

AK10
AL10
AM10
AN10

+VDDNB

A3
A4
B3
B4

+VDDNB@2000mA

C3
C4

B11

G7
B7
AH8
AJ6
B25
AM3
AN11
P9
P8

C

+0.9V

+0.9V@1250mA

U1G

B1

VSS_1

N2

VSS_28

N22

VSS_29

N23

VSS_30

B13

VSS_2

B15

VSS_3

B17

VSS_4

M21

VSS_27

B19

VSS_5

B21

VSS_6

B23

VSS_7

B27

VSS_8

B29

VSS_9

B33

VSS_10

C10

VSS_11

P10

VSS_31

P14

VSS_32

P16

VSS_33

P19

VSS_34

P7

VSS_35

C31

VSS_12

D11

VSS_13

D13

VSS_14

D15

VSS_15

R1

VSS_36

D17

VSS_16

D19

VSS_17

D21

VSS_18

D23

VSS_19

D25

VSS_20

D27

VSS_21

R15

VSS_37

R18

VSS_38

R2

VSS_39

R20

VSS_40

D29

VSS_46

D30

VSS_47

D8

VSS_48

E30

VSS_49

E32

VSS_50

F14

VSS_51

F17

VSS_52

R8

VSS_53

T14

VSS_54

T16

VSS_55

F20

VSS_56

T19

VSS_57

T24

VSS_58

T9

VSS_59

U1

VSS_60

F23

VSS_61

N1

VSS_62

G1

VSS_63

G19

VSS_64

G2

VSS_65

G25

VSS_66

G27

VSS_67

N10

VSS_115

TMK625DBV23GM_FCBGA812

K625@

VSS_45
VSS_44
VSS_43
VSS_42
VSS_26
VSS_25
VSS_41
VSS_24
VSS_23
VSS_22
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75

GND1

VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114

W19
W1
V20
V18
M11
L8
V15
L4
L30
L26
L24
L23
L22
L21
L2
L12
L10
L1
K9
M6
K24
K22
K16
M22
K13
M24
K11
M23
J7
W16
J4
W14
J32
J30
M13
J28
U8
J25
U4
J24
U7
U2
J2
J16
J13
J11
J1
H6
H5
H28
H23
H20
J22
M9
G4
G30
N12

D

U1H

AM19

VSS_207

AF7

VSS_167

AF26

VSS_166

AE7

VSS_165

AF8

VSS_168

AF9

VSS_169

AG1

VSS_170

AG2

VSS_171

AG27

VSS_172

AG4

VSS_173

AG5

VSS_174

AG6

VSS_175

AG7

VSS_176

AE4

VSS_164

AE25

VSS_163

AE24

VSS_162

AE22

VSS_161

AE20

VSS_160

AE2

VSS_159

AE16

VSS_158

AE13

VSS_157

AH14

VSS_177

AE11

VSS_156

AE10

VSS_155

AE1

VSS_154

AD24

VSS_153

AD23

VSS_152

AD22

VSS_151

AH20

VSS_178

AH23

VSS_179

AH25

VSS_180

AH28

VSS_181

AD20

VSS_150

AD16

VSS_149

AD13

VSS_148

AD10

VSS_147

AC9

VSS_146

AC8

VSS_145
VSS_214A2VSS_215

AC23

VSS_144

AH5

VSS_182

AJ1

VSS_183

AJ15

VSS_184

W2

VSS_116

A32

VSS_213

W8

VSS_117

Y10

VSS_118

Y15

VSS_119

Y18

VSS_120

AJ19

VSS_185

AJ2

VSS_186

AJ22

VSS_187

AJ4

VSS_188

Y20

VSS_121

Y24

VSS_122

AK11

VSS_189

AK13

VSS_190

Y7

VSS_123

AA1

VSS_124

AA11

VSS_125

TMK625DBV23GM_FCBGA812

VSS_191
VSS_192
VSS_193
VSS_194
VSS_126
VSS_127
VSS_128
VSS_195
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_196
VSS_197

GND2

VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_137
VSS_138
VSS_205
VSS_206
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212

E

AK15
AK17
AK19
AK21
AA2
AA22
AA23
AK23
AA4
AA9
AB10
AB12
AB21
AB22
AB23
AB24
AK25
AK27
AK29
AJ5
AH6
AL31
AM1
AM13
AB7
AC1
AM15
AM17
AC11
AC13
AC2
AC21
AC22
AM23
AM27
AM33
AN2
AN32
AM11

K625@

VDDR(+0.9V) decoupling.

+0.9V

1

C25

4.7U_0805_10V4Z

2

3 3

+0.9V

1

C36

1000P_0402_50V7K

2

1

C26

4.7U_0805_10V4Z

2

1

C37

1000P_0402_50V7K

2

1

C27

4.7U_0805_10V4Z

2

1

C38

1000P_0402_50V7K

2

VDD(+CPU_CORE_0) decoupling.

+CPU_CORE_0

1

C50
22U_0805_6.3V6M

2

4 4

+CPU_CORE_0

1

C59
22U_0805_6.3V6M

2

CPU BOT site

L

1

C51
22U_0805_6.3V6M

2

1

C60
22U_0805_6.3V6M

2

A

1

2

1

2

1

2

1

1000P_0402_50V7K

2

C52
22U_0805_6.3V6M

C61
22U_0805_6.3V6M

C28

4.7U_0805_10V4Z

C39

1

C53
22U_0805_6.3V6M

2

1

C62
22U_0805_6.3V6M

2

1

C29

0.22U_0603_16V4Z

2

1

C40
180P_0402_50V8J

2

1

C54

0.22U_0603_16V4Z

2

1

C63

0.22U_0603_16V4Z

2

1

C30

0.22U_0603_16V4Z

2

1

C41
180P_0402_50V8J

2

1

C55

0.01U_0402_25V7K

2

1

C64

0.01U_0402_25V7K

2

B

1

C31

0.22U_0603_16V4Z

2

1

C42
180P_0402_50V8J

2

1

C56
180P_0402_50V8J

2

1

C65
180P_0402_50V8J

2

1

C32

0.22U_0603_16V4Z

2

1

C43
180P_0402_50V8J

2

C526

330U_2.5V_M

VDD(+CPU_CORE_0) decoupling.

+CPU_CORE_0

1

+

C494
330U_SX_2VY~D

2

1

+

C495
330U_SX_2VY~D

2

1

+

C496
330U_SX_2VY~D

2

1

+

C497
330U_SX_2VY~D

@

2

1

C649

4.7U_0805_10V4Z

2

1

2

VDDIO(+1.5V) decoupling.

+1.5V

1

1

+

C44
22U_0805_6.3V6M

2

2

+1.5V

1

C651

0.22U_0603_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

1

C652

0.22U_0603_16V4Z

2

C

C45
22U_0805_6.3V6M

1

C57

4.7U_0805_10V4Z

2

1

C625

0.22U_0603_16V4Z

2

2008/04/14 2009/04/14

1

C58

4.7U_0805_10V4Z

2

1

C626

0.22U_0603_16V4Z

2

Compal Secret Data

Deciphered Date

1

C623

4.7U_0805_10V4Z

2

1

C627

0.22U_0603_16V4Z

2

1

C628

0.22U_0603_16V4Z

2

D

1

C624

4.7U_0805_10V4Z

2

1

2

VDDNB(+VDDNB) decoupling.

+VDDNB

1

C650

4.7U_0805_10V4Z

1

C48
180P_0402_50V8J

2

C46

0.22U_0603_16V4Z

Title

Size Document Number Rev

Custom

Date: Sheet

C33
22U_0805_6.3V6M

2

1

C49
180P_0402_50V8J

2

1

C47

0.22U_0603_16V4Z

2

Compal Electronics, Inc.

AMD CPU S1G2 PWR & GND

1

C34
22U_0805_6.3V6M

2

1

C653
180P_0402_50V8J

2

1

C630

0.1U_0402_16V7K

2

LA-6032P

E

1

C35
22U_0805_6.3V6M

2

1

C629

0.01U_0402_25V7K

2

1

C631

0.1U_0402_16V7K

2

845Tuesday, March 23, 2010

of

1.0

A

B

C

D

E

+VREF_DQ

DDR_A_D0
DDR_A_D1

DDR_A_DM0

DDR_A_D2

1 1

DDR_A_DQS#16
DDR_A_DQS16

DDR_A_DQS#26
DDR_A_DQS26

DDR_CKE0_DIMMA6

2 2

3 3

4 4

DDR_CS1_DIMMA#6

DDR_A_DQS#46
DDR_A_DQS46

DDR_A_DQS#66
DDR_A_DQS66

+3VS

C445

2.2U_0805_10V6K

DDR_A_BS#26

DDR_A_CLK06
DDR_A_CLK#06

DDR_A_BS#06

DDR_A_WE#6

DDR_A_CAS#6 DDR_A_ODT0 6

1

C446

0.1U_0402_16V4Z

2

A

DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS#2

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

DDR_A_CLK0
DDR_A_CLK#0

DDR_A_MA10
DDR_A_BS#0

DDR_A_WE#
DDR_A_CAS# DDR_A_ODT0

DDR_A_MA13
DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_DM5

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_DM7

DDR_A_D58
DDR_A_D59

R285 10K_0402_5%

+3VS

1

2

1 2

+1.5V +1.5V

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

12

R286

10K_0402_5%

203

VTT1

205

G1

FOX_AS0A626-U4RN-7F
CONN@

DIMM_A STD H:4mm

<Address: 00>

DQ4
DQ5

VSS3

DQS#0

DQS0
VSS6

DQ6

DQ7
VSS8
DQ12
DQ13

VSS10

DM1

DQ14
DQ15

DQ20
DQ21

DM2

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

VDD10

CK1
CK1#

VDD12

BA1
RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35
DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47
DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA

SCL
VTT2

2

DDR_A_D4

4

DDR_A_D5

6
8

DDR_A_DQS#0

10

DDR_A_DQS0

12
14

DDR_A_D6

16

DDR_A_D7

18
20

DDR_A_D12

22

DDR_A_D13

24
26

DDR_A_DM1

28

MEM_MA_RST#

30
32

DDR_A_D14

34

DDR_A_D15

36
38

DDR_A_D20

40

DDR_A_D21

42
44

DDR_A_DM2

46
48

DDR_A_D22

50

DDR_A_D23

52
54

DDR_A_D28

56

DDR_A_D29

58
60

DDR_A_DQS#3

62

DDR_A_DQS3

64
66

DDR_A_D30

68

DDR_A_D31

70
72

DDR_CKE1_DIMMA

74
76

DDR_A_MA15

78

A15
A14

A11

A7

A6
A4

A2
A0

S0#

G2

80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

B

DDR_A_MA14

DDR_A_MA11
DDR_A_MA7

DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

DDR_A_CLK1
DDR_A_CLK#1

DDR_A_BS#1
DDR_A_RAS#

DDR_CS0_DIMMA#

DDR_A_ODT1

DDR_A_D36
DDR_A_D37

DDR_A_DM4

DDR_A_D38
DDR_A_D39

DDR_A_D44
DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D46
DDR_A_D47

DDR_A_D52
DDR_A_D53

DDR_A_DM6

DDR_A_D54
DDR_A_D55

DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

EVENT#_A

+0.75VS

DDR_A_DQS#0 6
DDR_A_DQS0 6

MEM_MA_RST# 6

DDR_A_DQS#3 6
DDR_A_DQS3 6

DDR_CKE1_DIMMA 6

DDR_A_CLK1 6
DDR_A_CLK#1 6

DDR_A_BS#1 6
DDR_A_RAS# 6

DDR_CS0_DIMMA# 6

DDR_A_ODT1 6

1

C431

2

DDR_A_DQS#5 6
DDR_A_DQS5 6

DDR_A_DQS#7 6
DDR_A_DQS7 6

+VREF_CA

1000P_0402_25V8J

DDR_A_D[0..63]

DDR_A_DM[0..7]

DDR_A_MA[0..15]

12/25 Solve layout test point issue

SMB_CK_DAT0 10,21
SMB_CK_CLK0 10,21

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

DDR_A_D[0..63] 6

DDR_A_DM[0..7] 6

DDR_A_MA[0..15] 6

1

C427

2

1000P_0402_25V8J

2

C433

1

0.1U_0402_16V4Z

C443

4.7U_0603_6.3V6K

1

C701
180P_0402_50V8J

2

+1.5V

R281
1K_0402_1%

1 2

R283
1K_0402_1%

1 2

0.1U_0402_16V4Z

C434

1

C444

2

2

C435

1

0.1U_0402_16V4Z

1

C702
180P_0402_50V8J

2

D

2

1

+VREF_DQ

+VREF_DQ

0.01U_0402_25V7K

1

2

C425

C426

@

2

+1.5V

0.1U_0402_16V4Z

2

C432

1

+0.75VS

2

C442

1

0.1U_0402_16V4Z

+1.5V

1

C700
180P_0402_50V8J

2

Compal Secret Data

1

2

1

0.1U_0402_16V4Z

2

1

Deciphered Date

4.7U_0805_10V4Z

0.1U_0402_16V4Z

2008/10/06 2010/03/12

4.7U_0805_10V4Z

0.1U_0402_16V4Z

C436

1

C703
180P_0402_50V8J

2

+1.5V+VREF_CA

R282
1K_0402_1%

1

C428

@

2

2

C437

1

+VREF_CA

0.01U_0402_25V7K

2

C429

1

2

C438

1

0.1U_0402_16V4Z

1

2

1000P_0402_25V8J

0.1U_0402_16V4Z

2

1

C430

C439

0.1U_0402_16V4Z

1 2

1 2

2

C440

1

R284
1K_0402_1%

0.1U_0402_16V4Z

2

C441

1

Place near DIMM1

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DDRII SO-DIMM 1

LA-6032P

E

945Tuesday, March 23, 2010

1.0

of

A

B

C

D

E

DQ4
DQ5

DQ6
DQ7

DM1

DM2

CK1

BA1

NC2

DM4

DM6

SDA
SCL

+1.5V+1.5V

2

DDR_B_D4

4

DDR_B_D5

6
8

DDR_B_DQS#0

10

DDR_B_DQS0

12
14

DDR_B_D6

16

DDR_B_D7

18
20

DDR_B_D12

22

DDR_B_D13

24
26

DDR_B_DM1

28

MEM_MB_RST#

30
32

DDR_B_D14

34

DDR_B_D15

36
38

DDR_B_D20

40

DDR_B_D21

42
44

DDR_B_DM2

46
48

DDR_B_D22

50

DDR_B_D23

52
54

DDR_B_D28

56

DDR_B_D29

58
60

DDR_B_DQS#3

62

DDR_B_DQS3

64
66

DDR_B_D30

68

DDR_B_D31

70
72

DDR_CKE1_DIMMB

74
76

DDR_B_MA15

78

A15
A14

A11

A7

A6
A4

A2
A0

S0#

G2

80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

DDR_B_MA14

DDR_B_MA11
DDR_B_MA7

DDR_B_MA6
DDR_B_MA4

DDR_B_MA2
DDR_B_MA0

DDR_B_CLK1
DDR_B_CLK#1

DDR_B_BS#1
DDR_B_RAS#

DDR_CS0_DIMMB#
DDR_B_ODT0DDR_B_CAS#

DDR_B_ODT1

DDR_B_D36
DDR_B_D37

DDR_B_DM4

DDR_B_D38
DDR_B_D39

DDR_B_D44
DDR_B_D45

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D46
DDR_B_D47

DDR_B_D52
DDR_B_D53

DDR_B_DM6

DDR_B_D54
DDR_B_D55

DDR_B_D60
DDR_B_D61

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

EVENT#_B

+0.75VS

DDR_B_DQS#0 6
DDR_B_DQS0 6

MEM_MB_RST# 6

DDR_B_DQS#3 6
DDR_B_DQS3 6

DDR_CKE1_DIMMB 6

DDR_B_CLK1 6
DDR_B_CLK#1 6

DDR_B_BS#1 6
DDR_B_RAS# 6

DDR_CS0_DIMMB# 6
DDR_B_ODT0 6

DDR_B_ODT1 6

+VREF_CA

1

C453

2

1000P_0402_25V8J

DDR_B_DQS#5 6
DDR_B_DQS5 6

DDR_B_DQS#7 6
DDR_B_DQS7 6

12/25 Solve layout test point issue

SMB_CK_DAT0 9,21
SMB_CK_CLK0 9,21

DDR_B_D[0..63]

DDR_B_DM[0..7]

DDR_B_MA[0..15]

+VREF_DQ

+1.5V

2

1

0.1U_0402_16V4Z

+0.75VS

0.1U_0402_16V4Z

1

C447

2

4.7U_0805_10V4Z

0.1U_0402_16V4Z

C454

0.1U_0402_16V4Z

2

C464

1

DDR_B_D[0..63] 6

DDR_B_DM[0..7] 6

DDR_B_MA[0..15] 6

+VREF_DQ

0.1U_0402_16V4Z

1

C448

2

2

C455

1

0.1U_0402_16V4Z

2

C465

1

4.7U_0603_6.3V6K

1

2

1000P_0402_25V8J

2

C456

1

1

C466

2

+VREF_CA

C449

0.1U_0402_16V4Z

2

C457

1

1

C450

2

4.7U_0805_10V4Z

2

C458

1

0.1U_0402_16V4Z

+VREF_CA

0.1U_0402_16V4Z

1

C451

2

1000P_0402_25V8J

0.1U_0402_16V4Z

2

C459

1

0.1U_0402_16V4Z

C468 Co-layout with C467

Place near DIMM2

1

C452

2

2

1

0.1U_0402_16V4Z

C460

+1.5V

1

+

C468
330U_2.5V_M

2

2

C461

1

2

C462

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

C463

1

+VREF_DQ

DDR_B_D0
DDR_B_D1

DDR_B_DM0

DDR_B_D2

+3VS

DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_CKE0_DIMMB

DDR_B_BS#2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

DDR_B_CLK0
DDR_B_CLK#0

DDR_B_MA10
DDR_B_BS#0

DDR_B_WE#

DDR_B_MA13
DDR_CS1_DIMMB#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_DM5

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_DM7

DDR_B_D58
DDR_B_D59

R287 10K_0402_5%

1 2

12

R288

10K_0402_5%

1 1

DDR_B_DQS#16
DDR_B_DQS16

DDR_B_DQS#26
DDR_B_DQS26

DDR_CKE0_DIMMB6

2 2

3 3

4 4

DDR_B_BS#26

DDR_B_CLK06
DDR_B_CLK#06

DDR_B_BS#06

DDR_B_WE#6

DDR_B_CAS#6

DDR_CS1_DIMMB#6

DDR_B_DQS#46
DDR_B_DQS46

DDR_B_DQS#66
DDR_B_DQS66

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U4SN-7F

CONN@

VSS3

DQS#0

DQS0

VSS6

VSS8
DQ12
DQ13

VSS10

DQ14
DQ15

DQ20
DQ21

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

VTT2

Security Classification

Issued Date

DIMM_B STD H:4mm

<Address: 01>

A

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/10/06 2010/03/12

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

DDRII SO-DIMM 2

LA-6032P

E

10 45Tuesday, March 23, 2010

1.0

of

A

1 1

< To Card crader >

< To WLAN >

< To LAN >

2 2

H_CADIP[0..15]

H_CADIN[0..15]

3 3

H_CADIP[0..15] 5

H_CADIN[0..15] 5

PCIE_PTX_C_IRX_P130
PCIE_PTX_C_IRX_N130
PCIE_PTX_C_IRX_P226
PCIE_PTX_C_IRX_N226
PCIE_PTX_C_IRX_P327
PCIE_PTX_C_IRX_N327

< From S1G4 CPU : x16 HT> < To S1G4 CPU : x16 HT>

H_CLKOP05
H_CLKON05
H_CLKOP15
H_CLKON15

H_CTLOP05

H_CTLON05

H_CTLOP15

H_CTLON15

4 4

R52 301_0402_1%

L L

SB_RX0P20
SB_RX0N20
SB_RX1P20
SB_RX1N20
SB_RX2P20
SB_RX2N20
SB_RX3P20
SB_RX3N20

1 2

B

H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7

H_CADOP8
H_CADON8
H_CADOP9

H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15

H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1

H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1

U5B

D4

GFX_RX0P

AD4

AD3
AD1
AD2

AE3

AE2

AA8

AA7

AA5
AA6

C4

A3

B3
C2
C1

E5

F5
G5
G6
H5
H6

J6

J5

J7

J8

L5

L6
M8

L8

P7
M7

P5
M5
R8

P8
R6
R5

P4

P3

T4

T3

V5

W6

U5
U6
U8
U7

Y8

Y7

W5

Y5

GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N

GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

PART 2 OF 6

PCIE I/F GFX

PCIE I/F GPP

PCIE I/F SB

PCE_CALRP(PCE_BCALRP)

PCE_CALRN(PCE_BCALRN)

RS880M_FCBGA528

U5A

Y25

HT_RXCAD0P

Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25

AC24
AC25
AB25
AB24
AA24
AA25

Y22

Y23
W21
W20

V21

V20

U20

U21

U19

U18

T22

T23

AB23
AA22

M22
M23

R21

R20

C23

A24

RS880M_FCBGA528 RS880MR1@

HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N

HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N

HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N

HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N

HT_RXCALP
HT_RXCALN

PART 1 OF 6

HYPER TRANSPORT CPU I/F

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P

GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

GPP_TX0P

GPP_TX0N

GPP_TX1P

GPP_TX1N

GPP_TX2P

GPP_TX2N

GPP_TX3P

GPP_TX3N

GPP_TX4P

GPP_TX4N

GPP_TX5P

GPP_TX5N

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

RS880MR1@

HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N

HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P

HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N

HT_TXCLK0P

HT_TXCLK0N

HT_TXCLK1P

HT_TXCLK1N

HT_TXCTL0P

HT_TXCTL0N

HT_TXCTL1P

HT_TXCTL1N

HT_TXCALP
HT_TXCALN

C

HDMI_TXD2+

A5

HDMI_TXD2-

B5

HDMI_TXD1+

A4

HDMI_TXD1-

B4

HDMI_TXD0+

C3

HDMI_TXD0-

B2

HDMI_CLK0+

D1

HDMI_CLK0-

D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2

AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2

AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5

AC8
AB8

< If integrated GFX is used, some PCIE pairs are used as HDMI signal pairs >

RS880M Display Port Support (muxed on GFX)

PCIE_ITX_PRX_P1
PCIE_ITX_PRX_N1
PCIE_ITX_PRX_P2
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P3
PCIE_ITX_PRX_N3

SB_TX0P_C
SB_TX0N_C
SB_TX1P_C
SB_TX1N_C
SB_TX2P_C
SB_TX2N_C
SB_TX3P_C
SB_TX3N_C

R51 1.27K_0402_1%
R54 2K_0402_1%

C122 0.1U_0402_16V7K
C123 0.1U_0402_16V7K
C124 0.1U_0402_16V7K
C125 0.1U_0402_16V7K
C126 0.1U_0402_16V7K
C127 0.1U_0402_16V7K

C130 0.1U_0402_16V7K
C131 0.1U_0402_16V7K
C132 0.1U_0402_16V7K
C133 0.1U_0402_16V7K
C134 0.1U_0402_16V7K
C135 0.1U_0402_16V7K
C136 0.1U_0402_16V7K
C137 0.1U_0402_16V7K

1 2
1 2

L

H_CADIP0

D24

H_CADIN0

D25

H_CADIP1

E24

H_CADIN1

E25

H_CADIP2

F24

H_CADIN2

F25

H_CADIP3

F23

H_CADIN3

F22

H_CADIP4

H23

H_CADIN4

H22

H_CADIP5

J25

H_CADIN5

J24

H_CADIP6

K24

H_CADIN6

K25

H_CADIP7

K23

H_CADIN7

K22

H_CADIP8

F21

H_CADIN8

G21

H_CADIP9

G20

H_CADIN9

H21

H_CADIP10

J20

H_CADIN10

J21

H_CADIP11

J18

H_CADIN11

K17

H_CADIP12

L19

H_CADIN12

J19

H_CADIP13

M19

H_CADIN13

L18

H_CADIP14

M21

H_CADIN14

P21

H_CADIP15

P18

H_CADIN15

M18

H_CLKIP0

H24

H_CLKIN0

H25

H_CLKIP1

L21

H_CLKIN1

L20

H_CTLIP0

M24

H_CTLIN0

M25

H_CTLIP1

P19

H_CTLIN1

R18

R53 301_0402_1%

B24
B25

1 2

Place within 1" layout 1:2Place within 1" layout 1:2

HDMI_TXD2+ 19
HDMI_TXD2- 19
HDMI_TXD1+ 19
HDMI_TXD1- 19
HDMI_TXD0+ 19
HDMI_TXD0- 19
HDMI_CLK0+ 19
HDMI_CLK0- 19

GFX_TX0,TX1,TX2 and TX3

GFX_TX4,TX5,TX6 and TX7

1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

R51 within U5 1"
R54 within U5 1"

H_CLKIP0 5
H_CLKIN0 5
H_CLKIP1 5
H_CLKIN1 5

H_CTLIP0 5
H_CTLIN0 5
H_CTLIP1 5
H_CTLIN1 5

AUX0 and HPD0

AUX1 and HPD1

+1.1VS

D

HDMI

PCIE_ITX_C_PRX_P1 30
PCIE_ITX_C_PRX_N1 30
PCIE_ITX_C_PRX_P2 26
PCIE_ITX_C_PRX_N2 26
PCIE_ITX_C_PRX_P3 27
PCIE_ITX_C_PRX_N3 27

SB_TX0P 20
SB_TX0N 20
SB_TX1P 20
SB_TX1N 20
SB_TX2P 20
SB_TX2N 20
SB_TX3P 20
SB_TX3N 20

H_CADOP[0..15]5

H_CADON[0..15]5

< To Card crader >

< To WLAN >

< To LAN >

< To WWAN >

< To SB820 : x4 PCEI A-link>< From SB820 : x4 PCIE A-link >

< TX Impedance Calibrati on. Connect to GND >
< RX Impedance Cali bration. Connect to VDDPCIE >

H_CADOP[0..15]

H_CADON[0..15]

E

/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet

Compal Electronics, Inc.

RS880M HT/PCIE

LA-6032P

11 45Tuesday, March 23, 2010

E

of

1.0Custom

A

B

C

D

E

+3VS

1 2

BLM18PG121SN1D_0603

+1.8VS

1 1

+1.8VS

BLM18PG121SN1D_0603

0_0603_5%

2.2U_0603_6.3V6K

1 2

Total +1.1VS_PLL@230mA

+1.1VS

1 2

BLM18PG121SN1D_0603

2.2U_0603_6.3V6K

2 2

3 3

4 4

Total +1.8VS PLL@100mA

1 2

BLM18PG121SN1D_0603

2.2U_0603_6.3V6K

+1.8VS +VDDA18HTPLL

+1.8VS +VDDA18PCIEPLL

L9

1 2

BLM18PG121SN1D_0603

2.2U_0603_6.3V6K

L10

1 2

BLM18PG121SN1D_0603

2.2U_0603_6.3V6K

+1.8VS

R804

1 2

R63 300_0402_5%

CPU_LDT_REQ# Pull +1.8VS on page 20

+AVDD1@125mA

L3

C139

2.2U_0603_6.3V6K

L5

1

C142

2

L6

C144

2.2U_0603_6.3V6K

C145

C146

C147

C148

CPU_LDT_REQ#

NB_PWRGD

+NB_PLLVDD

1

2

1

2

1

2

1

2

L7

L8

12

1K_0402_5%

1 2

R55 140_0402_1%

1 2

R56 150_0402_1%

1 2

R57 150_0402_1%

+AVDD1

1

2

+AVDD2

1

C143

0.1U_0402_16V4Z

2

+AVDDQ

1

2

+NB_HTPVDD+1.8VS

12/07 Internal clock gen

12

RS15

4.7K_0402_5%

CRT_R_R

CRT_G_R

CRT_B_R

U5C

F12

AVDD1(NC)

E12

AVDD2(NC)

F14

AVDDDI(NC)

G15

AVSSDI(NC)

H15

AVDDQ(NC)

H14

AVSSQ(NC)

E17

C_Pr(DFT_GPIO5 )

F17

Y(DFT_GPIO2)

F15

COMP_Pb(DFT_GPIO4)

G18

RED(DFT_GPIO0)

G17

REDb(NC)

E18

GREEN(DFT_ GPIO1)

F18

GREENb(NC)

E19

BLUE(DFT_GPIO3)

F19

BLUEb(NC)

A11

DAC_HSYNC(PWM_GPIO4)

B11

DAC_VSYNC(PWM_GPIO6)

F8

DAC_SCL(PCE_RCALRN)

E8

DAC_SDA(PCE_TCALRN)

G14

DAC_RSET(PWM_GPIO1)

A12

PLLVDD(NC)

D14

PLLVDD18(NC)

B12

PLLVSS(NC)

H17

VDDA18HTPLL

D7

VDDA18PCIEPLL1

E7

VDDA18PCIEPLL2

D8

SYSRESETb

A10

POWERGOOD

C10

LDTSTOPb

C12

ALLOW_LDTSTOP

C25

HT_REFCLKP

C24

HT_REFCLKN

E11

REFCLK_P/OSCIN(OSCIN)

F11

REFCLK_N(PWM_GPIO3)

T2

GFX_REFCL KP

T1

GFX_REFCL KN

U1

GPP_REFCLKP

U2

GPP_REFCLKN

V4

GPPSB_REFCLKP(SB_REFCLKP)

V3

GPPSB_REFCLKN(SB_REFCLKN)

B9

I2C_CLK

A9

I2C_DATA

B8

DDC_DATA0/AUX0N(NC)

A8

DDC_CLK0/AUX0P(NC)

B7

DDC_CLK1/AUX1P(NC)

A7

DDC_DATA1/AUX1N(NC)

B10

STRP_DATA

G11

RSVD

C8

AUX_CAL(NC)

PART 3 OF 6

RS880M_FCBGA528

+1.8VS

R805

2.2K_0402_5%

E

3 1

MMBT3904_NL_SOT23-3

R822 0_0402_5%

1 2

+1.8VS

12

B

2

Q36

C

@

TXOUT_L2N(DBG_GPIO0)

TXOUT_L3N(DBG_GPIO2)

TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)

TXOUT_U3P(PCIE_RESET_GPIO5)

CRT/TVOUT

TXCLK_LP(DBG_GPIO1)

TXCLK_LN(DBG_GPIO3)
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)

LVTM

PM

LVDS_DIGON(P CE_TCALRP)

LVDS_BLON(PCE_RCALRP)

LVDS_ENA_BL(PWM_GPIO2)

CLOCKs PLL PWR

MIS.

SUS_STAT#(PWM_GPIO5)

12

R806

2.2K_0402_5%

NB_LDTSTOP#

TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)

TXOUT_L3P(NC)

TXOUT_U0P(NC)
TXOUT_U0N(NC)

TXOUT_U2P(NC)
TXOUT_U2N(NC)

TXOUT_U3N(NC)

VDDLTP18(NC)

VSSLTP18(NC)

VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)

VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)

TMDS_HPD(NC)

HPD(NC)

THERMALDIODE_P
THERMALDIODE_N

TESTMODE

RS880MR1@

A22
B22
A21
B21
B20
A20
A19

< LVDS dual channel : channel 1 >

B19

B18
A18
A17
B17
D20
D21
D18
D19

B16
A16
D16
D17

+VDDLTP18

A13
B13

+VDDLT18

A15
B15
A14
B14

C14
D15
C16
C18
C20
E20
C22

E9
F7
G12

12

@

4.7K_0402_5%

R778

HPD

D9
D10

SUS_STAT#

D12

AE8
AD8

D13

1 2

R65 1.8K_0402_5%

12

@

R781

4.7K_0402_5%

VARY_ENBKL

LCD_TXOUT0+ 18
LCD_TXOUT0- 18
LCD_TXOUT1+ 18
LCD_TXOUT1- 18
LCD_TXOUT2+ 18
LCD_TXOUT2- 18

LCD_TXCLK+ 18
LCD_TXCLK- 18

12

@

R779

Strap pin

2/2 Fine tune pin define

PLT_RST#15,20,26,27,30,31,32

NBGFX_CLK
NBGFX_CLK#

12

RS16

4.7K_0402_5%

LCD_EDID_CLK18

LCD_EDID_DATA18

+AVDD1

+AVDD2

+AVDDQ

CRT_HSYNC15,17

CRT_VSYNC15,17
UMA_CRT_CLK17
UMA_CRT_DATA17

R58 715_0402_1%

+NB_PLLVDD

+NB_HTPVDD

+VDDA18HTPLL

+VDDA18PCIEPLL

R59

1 2

NB_PWRGD21

CPU_LDT_REQ#20

CLK_NBHT20
CLK_NBHT#20

CLK_NB_REFCLK20
CLK_NB_REFCLK#20

CLK_SBLINK_BCLK20
CLK_SBLINK_BCLK#20

HDMIDAT_UMA19

HDMICLK_UMA19

+3VS

R66 150_0402_1%

CRT_R_R

CRT_G_R

CRT_B_R

UMA_CRT_CLK
UMA_CRT_DATA

1 2

0_0402_5%

R64 10K_0402_5%

@

NB_RESET#
NB_PWRGD
NB_LDTSTOP#
CPU_LDT_REQ#

CLK_NBHT
CLK_NBHT#

CLK_NB_REFCLK
CLK_NB_REFCLK#

NBGFX_CLK
NBGFX_CLK#

CLK_SBLINK_BCLK
CLK_SBLINK_BCLK#

LCD_EDID_CLK
LCD_EDID_DATA
HDMIDAT_UMA
HDMICLK_UMA

@

12

AUX_CAL

12

Strap pin

LDT_STOP#7,20

Contact with NB signal Contact to CRT conn signal

CRT_R_R

L41 NBQ100505T-800Y-N_2P

CRT_G_R

CRT_B_R

1 2

L42 NBQ100505T-800Y-N_2P

1 2

L43 NBQ100505T-800Y-N_2P

1 2

1

C913

2.2P_0402_50V8C

2

1

C912

2.2P_0402_50V8C

2

1

C911

2.2P_0402_50V8C

2

CRT_R 17

CRT_G 17

CRT_B 17

+VDDLT18@220mA

+VDDLTP18

+VDDLT18

C140

0.1U_0402_16V4Z

If support VB, R780 R777->SMT, R776->@
If no support VB, R776-->SMT, R780 R777->@

R776 0_0402_5%@

1 2

R780 0_0402_5%

1 2

R777 0_0402_5%

1 2

4.7K_0402_5%

PS:Need to fine tune R783 and R784 on Page17

HPD 19

SUS_STAT# 15,21

< HDMI hot-plug detecti on >

< Strap option pin or gate s ide-port memory IO >

1 2

BLM18PG121SN1D_0603

1

C138

2

2.2U_0603_6.3V6K

BLM18PG121SN1D_0603

1

1

C141

2

2

4.7U_0805_10V4Z

UMA_ENVDD 18

UMA_ENBKL 31

GMCH_INVT_PWM 18

L2

L4

1 2

+1.8VS

+1.8VS

2/2 Add L41 L42 L43 C911 C912 C913 for EMI request

/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

RS880M VEDIO/CLK GEN

LA-6032P

12 45Tuesday, March 23, 2010

E

of

1.0

2

1

@

SP_DDR3_RST#21

MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12

MEM_A13

MEM_BA0
MEM_BA1
MEM_BA2

MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_CS#
MEM_CKE
MEM_ODT

MEM_CLKP
MEM_CLKN

MEM_COMP_P

MEM_COMP_N

12

R341 10K_0402_5%SIDE@

243_0402_1%

/

Security Classification

+MEM_VREF MEM_DQ0

MEM_BA0
MEM_BA1
MEM_BA2

MEM_CKE

MEM_ODT
MEM_CS#
MEM_RAS#
MEM_CAS#
MEM_WE#

MEM_DQS_P0
MEM_DQS_P1

MEM_DM0
MEM_DM1

MEM_DQS_N0
MEM_DQS_N1

+1.5VS

2

SIDE@

C600
1U_0402_6.3V4Z

1

B B

A A

+1.5VS

1

2

1

2

+1.5VS

1

2

1

2

2

SIDE@

C601
1U_0402_6.3V4Z

1

SIDE@

C608

0.1U_0402_16V4Z

SIDE@

C609

0.1U_0402_16V4Z

SIDE@

C610

0.1U_0402_16V4Z

SIDE@

C611

0.1U_0402_16V4Z

1

SIDE@

C602

0.1U_0402_16V4Z

2

SIDE@

R335
1K_0402_1%

1 2

+MEM_VREF

SIDE@

R337
1K_0402_1%

1 2

SIDE@

R338
1K_0402_1%

1 2

+MEM_VREF1

SIDE@

R339
1K_0402_1%

1 2

1

SIDE@

C603

0.1U_0402_16V4Z

2

1

SIDE@

C614

10U_0603_6.3V6M

2

1

SIDE@

C604
10U_0603_6.3V6M

2

R334

SIDE@

SIDE@

+1.5VS

MEM_COMP_P and MEM_COMP_N trace
width >=10mils and 10mils s pacing from
other Signals in X,Y, Z directions

R336

12

12

+1.5VS

For Side port only

40.2_0402_1%

40.2_0402_1%

R340 100_0402_1%

MEM_CLKP
MEM_CLKN

12

R342

SIDE@

AB12
AE16

V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14

Y14

AD16
AE17
AD17

W12

Y12
AD18
AB13
AB18

V14

V15

W14

AE12
AD12

MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
MEM_A13

U5D

1 2

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PAR 4 OF 6

MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)

MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)

MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)

MEM_CKP(NC)
MEM_CKN(NC)

MEM_COMPP(NC)
MEM_COMPN(NC)

M9
H2

N4
P8
P4
N3
P9
P3
R9
R3

T9

R4

L8
R8
N8

T4

T8
M8

M3
N9
M4

J8
K8

K10

K2

L3

J4
K4

L4

F4
C8

E8
D4

G4
B8

T3

L9

J2

L2

J10

L10

A1

A11

T1

T11

2008/04/14 2009/04/14

MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)

MEM_DQ2/DVO_DE(NC)

MEM_DQ3/DVO_D0(NC)

MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)

MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)

MEM_DQ12(NC)

MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)

MEM_DQS0P/DVO_IDCKP(NC)

MEM_DQS0N/DVO_IDCKN(NC)

MEM_DQS1P(NC)
MEM_DQS1N(NC)

MEM_DM0(NC)

MEM_DM1/DVO_D8(NC)

SBD_MEM/DVO_I/F

RS880M_FCBGA528RS880MR1@

U27

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

BA0
BA1
BA2

CK
CK
CKE/CKE0

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET

ZQ/ZQ0

NC/ODT1
NC/CS1
NC/CE1
NC/ZQ1

NC
NC
NC
NC

100-BALL
SDRAM DDR3

K4W1G1646D-EC15_FBGA100

SIDE@

IOPLLVDD18(NC)

IOPLLVDD(NC)

MEM_VREF(NC)

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

Compal Secret Data

IOPLLVSS(NC)

E4
F8
F3
F9
H4
H9
G3
H8

D8
C4
C9
C3
A8
A3
B9
A4

B3
D10
G8
K3
K9
N2
N10
R2
R10

A2
A9
C2
C10
D3
E10
F2
H3
H10

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

B2
B10
D2
D9
E3
E9
F10
G2
G10

Deciphered Date

AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21

Y17
W18
AD20
AE21

W17
AE19

AE23
AE24

AD23

AE18

MEM_DQ6
MEM_DQ2
MEM_DQ5
MEM_DQ3
MEM_DQ7
MEM_DQ1
MEM_DQ4

MEM_DQ11
MEM_DQ15
MEM_DQ9
MEM_DQ10
MEM_DQ12
MEM_DQ14
MEM_DQ8
MEM_DQ13

+1.5VS

MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15

MEM_DQS_P0
MEM_DQS_N0
MEM_DQS_P1
MEM_DQS_N1

MEM_DM0
MEM_DM1

+1.8V_IOPLLVDD
+NB_IOPLLVDD

+MEM_VREF1

R332

0_0603_5%

1 2

1

SIDE@

C605

2.2U_0603_6.3V4Z

2

R333

0_0603_5%

1 2

1

SIDE@

C606

2.2U_0603_6.3V4Z

2

Title

Size Document Number Rev

Custom

1

Date: Sheet

Compal Electronics, Inc.

RS880M SIDE PORT

+1.8VS

+1.1VS

LA-6032P

13 45Tuesday, March 23, 2010

1.0

of

A

1 1

2 2

3 3

+1.1VS

+1.1VS

+1.8VS

0_0805_5%

0_0805_5%

0_0805_5%

4.7U_0805_10V4Z

+VDDHT/+VDDHTRX@680mA

L12

12

1

C150

C151

2

4.7U_0805_10V4Z

L13

L14

0_0805_5%

L16

0.1U_0402_16V4Z

12

C156

10U_0805_10V6K

12

4.7U_0805_10V4Z

12

C173

4.7U_0805_10V4Z

1U_0402_6.3V4Z

1

C162

C157

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+VDDHTTX@680mA

1

C169

C168

2

0.1U_0402_16V4Z

+VDDA18PCIE@640mA

1

1

C175

C174

2

2

0.1U_0402_16V4Z

+1.8VS

1

C192

2

1

1

C152

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C163

2

0.1U_0402_16V4Z

1

1

C170

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C179

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C153

C171

C180

1

C158

2

1

C154

2

0.1U_0402_16V4Z

+VDDHTRX

1

2

0.1U_0402_16V4Z

1

C172

2

0.1U_0402_16V4Z

1

C176

2

0.1U_0402_16V4Z

5mA

+1.8VS

+VDDHT

1

2

+VDDHTTX

1

2

+VDDA18PCIE

1

2

1 2

0_0603_5%

50mA

B

U5E

J17

VDDHT_1

K16

2A

L18

L16
M16
P16
R16
T16

H18
G19
F20
E21
D22
B23
A23

AE25
AD24
AC23
AB22
AA21

Y20

W19

V18
U17
T17
R17
P17

M17

P10
K10

M10

L10

T10
R10

AA9
AB9

AD9

AE9
U10

AE11
AD11

1

SIDE@

C193
1U_0402_6.3V4Z

2

J10

W9

H9

Y9

F9

G9

PART 5/6

VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7

VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7

VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13

VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15

VDD18_1
VDD18_2
VDD18_MEM1(NC)
VDD18_MEM2(NC)

RS880M_FCBGA528 RS880MR1@

+VDDA11PCIE@2500mA

VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8

VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

VDDC_9
VDDC_10
VDDC_11
VDDC_12

POWER

VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22

VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)

VDD33_1(NC)
VDD33_2(NC)

A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9

K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16

AE10
AA11
Y11
AD10
AB10
AC10

H11
H12

C

+VDDA11PCIE

60mA

1 2

FBMA-L11-201209-221LMA30T_0805

C159

C155

C160 1U_0402_6.3V4Z
C161 1U_0402_6.3V4Z
C164 1U_0402_6.3V4Z
C165 1U_0402_6.3V4Z
C166 0.1U_0402_16V4Z
C167 0.1U_0402_16V4Z

+NB_CORE@7600mA

1

1

1

C1810.1U_0402_16V4Z

2

+3VS

1

C1820.1U_0402_16V4Z

2

1

1

C1840.1U_0402_16V4Z

C1830.1U_0402_16V4Z

C1850.1U_0402_16V4Z

C1770.1U_0402_16V4Z

2

2

2

2

1 2

1 2

L11

1 2
1 2
1 2
1 2

1

C1860.1U_0402_16V4Z

2

10U_0805_10V6K

10U_0805_10V6K

12
12

1

1

C1870.1U_0402_16V4Z

C1780.1U_0402_16V4Z

2

2

C1940.1U_0402_16V4Z

C2000.1U_0402_16V4Z

1

C18810U_0805_10V6K

2

+NB_CORE

1

C18910U_0805_10V6K

2

0_0402_5%

NOSIDE@

R67

+1.1VS

C191

1

2

1000P_0402_50V7K

D

U5F

A25

VSSAHT1

D23

VSSAHT2

E22

VSSAHT3

G22

VSSAHT4

G24

VSSAHT5

G25

VSSAHT6

H19

VSSAHT7

J22

VSSAHT8

L17

VSSAHT9

L22

VSSAHT10

L24

VSSAHT11

L25

VSSAHT12

M20

VSSAHT13

N22

VSSAHT14

P20

VSSAHT15

R19

VSSAHT16

R22

VSSAHT17

R24

VSSAHT18

R25

VSSAHT19

H20

VSSAHT20

U22

VSSAHT21

V19

VSSAHT22

W22

VSSAHT23

W24

VSSAHT24

W25

VSSAHT25

Y21

VSSAHT26

AD25

VSSAHT27

L12

VSS11

M14

VSS12

N13

VSS13

P12

VSS14

P15

VSS15

R11

VSS16

R14

VSS17

T12

VSS18

U14

VSS19

U11

VSS20

U15

VSS21

V12

VSS22

W11

VSS23

W15

VSS24

AC12

VSS25

1

C5970.1U_0402_16V4Z SIDE@

2

AA14

VSS26

Y18

VSS27

AB11

VSS28

AB15

VSS29

AB17

VSS30

AB19

VSS31

AE20

VSS32

AB21

VSS33

K11

VSS34

RS880M_FCBGA528 RS880MR1@

L82

SIDE@

1 2

0_0603_5%

1

1

C5990.1U_0402_16V4Z SIDE@

C5980.1U_0402_16V4Z SIDE@

2

2

12

1

1

C6131U_0402_6.3V4Z SIDE@

C6124.7U_0805_10V4Z SIDE@

2

2

PART 6/6

VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8

VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30

GROUND

VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

VSS10

+1.8VS

A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2

AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15

E

4 4

/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet

Compal Electronics, Inc.

RS880MPWR/GND

LA-6032P

14 45Tuesday, March 23, 2010

E

1.0Custom

of

A

B

C

D

E

RS880 DFT_GPIO5 mux at CRT_VSYNC pull High to 3K

CRT_VSYNC12,17

1 1

12

R68 3K_0402_5%

12

R69 3K_0402_5%@

+3VS

DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb

Enables the Test Debug Bus using GPIO.
1 : Disable (RS880)
0 : Enable (RS880)
PIN: RS880-->VSYNC#

DFT_GPIO[4:2] : STRAP_PCIE_GPP_CFG[2:0]

These pin straps are used to configure PCI-E GPP mode.
000 : 00001
001 : 00010

RS780 use register to control PCI-E configure

2 2

010 : 01011
011 : 00100
100 : 01010
101 : 01100
111 : 01011

DFT_GPIO1: LOAD_EEPROM_ST RAPS

Selects Loading of STRAPS from EPROM

D5

@

SUS_STAT#12,21

2 1

CH751H-40PT_SOD323-2

PLT_RST# 12,20,26,27,30,31,32

1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
RS880:SUS_STAT#

3 3

RS880 use HSYNC to enable SIDE PORT (internal pull high)

CRT_HSYNC12,17

4 4

A

B

12

R70 3K_0402_5%

SIDE@

12

R71 3K_0402_5%

+3VS

/

DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb

RX881: Enables the Test Debug Bus using PCIE bus
1 : Disable ( Can still be enabled using nbcfg register access )
0 : Enable

RS880: Enables Side port memory ( RS780 use HSYNC#)

1. Disable (RS880)

0 : Enable (RS880)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

Size Document Number Rev

D

Date: Sheet

Title

Compal Electronics, Inc.

RS880M STRAPS

LA-6032P

15 45Tuesday, March 23, 2010

E

of

1.0Custom

A

B

C

D

E

Use SB820M internal clock gen

1 1

2 2

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009-02-12 2009-02-12

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

CLOCK GENERATOR

LA-6051P

16 45Tuesday, March 23, 2010

E

of

1.0

A

B

C

D

E

CRT+RJ45 FFC conn
Pin=20pin, pitch=0.5

1 1

1/28 Fine tune JP4 pin define

RJ45_GND27

RJ45_MIDI1+27
RJ45_MIDI1-27

3/23 switch noise soluation

UMA_CRT_CLK12
UMA_CRT_DATA12

2 2

C914

@

1

1

C915

@

2

2

+3VS

10P_0402_25V8K

+5VS

10P_0402_25V8K

C909

0.1U_0402_16V4Z

RJ45_MIDI0+27
RJ45_MIDI0-27

CRT_VSYNC12,15
CRT_HSYNC12,15

CRT_R12
CRT_G12
CRT_B12

1

0.1U_0402_16V4Z

2

C910

RJ45_GND
RJ45_MIDI1+
RJ45_MIDI1-

RJ45_MIDI0+
RJ45_MIDI0-

1

2

1/31 EMI request

3 3

JP4

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19
20

21

19

GND1

22

20

GND2

STARC_107K20-000000-G4

CONN@

4 4

/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet

Compal Electronics, Inc.

CRT/TV-OUT Connector

LA-6032P

E

17 45Tuesday, March 23, 2010

of

1.0Custom

A

B

C

D

E

LCD/PANEL BD. Conn.

+LCD_VDD

1 1

2N7002DW-T/R7_SOT363-6

UMA_ENVDD12

1 2

R75 0_0402_5%

Q2A

ENVDD

R76

100K_0402_5%

12

R72
150_0603_5%

61

2

12

+3VS

12

R73
100K_0402_5%

3

Q2B

5

2N7002DW-T/R7_SOT363-6

4

0.1U_0402_16V7K

R74

1 2

47K_0402_5%

C201

+3VS

2

1

G

2

2

1 3

C202

0.01U_0402_25V7K

1

1

2

W= 60 mils

S

Q3
AO3413_SOT23

D

Inrush current = 0A

C203

@

4.7U_0805_10V4Z

+LCD_VDD

1

2

W= 60 mils

C204

0.1U_0402_16V4Z

< LVDS Connector >

2 2

+LCDVDD_R

+3VS

1

1

@

C208

2

0.1U_0402_16V4Z

B+

L20

1 2

FBMA-L11-201209-221LMA30T_0805

1

@

C215

3 3

4 4

2

0.1U_0402_16V4Z

USB20_N921

USB20_P921

68P_0402_50V8J

C212

BKOFF#31

1

2

C211

2

1000P_0402_50V7K

BKOFF# BKOFF#_R

1

+3VS

@

C214

0.1U_0402_25V4K

USB20_N9 USB20_N9_R

2

INT_MIC_CLK28
INT_MIC_DATA28

@

R798 0_0402_5%

1 2

L83

4

4

1

1

WCM-2012-900T_0805

R799 0_0402_5%

1 2

@

LCD_EDID_CLK12
LCD_EDID_DATA12
LCD_TXOUT0-12
LCD_TXOUT0+12

LCD_TXOUT1-12
LCD_TXOUT1+12
LCD_TXOUT2-12
LCD_TXOUT2+12

LCD_TXCLK-12
LCD_TXCLK+12

R7910K_0402_5%

12

R919

1 2

22_0402_5%

R77 0_0603_5%

1 2

INT_MIC_CLK
INT_MIC_DATA

3

3

USB20_P9_RUSB20_P9

2

2

LCD_EDID_CLK
LCD_EDID_DATA
LCD_TXOUT0­LCD_TXOUT0+

LCD_TXOUT1­LCD_TXOUT1+
LCD_TXOUT2­LCD_TXOUT2+

LCD_TXCLK­LCD_TXCLK+

INVT_PW M

+LCD_INV

+3VS_USB
USB20_N9_R
USB20_P9_R

3

1

2

D16
PACDN042Y3R_SOT23-3

JLVDS1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

I-PEX_20143-030E-20F~D

CONN@

1/25 Pin24 +LCD_INV--> NC

34

MGND4

33

MGND3

32

MGND2

31

MGND1

EC_INVT_PWM31

GMCH_INVT_PWM12

1/19 R782-->@ and R783/R784-->SMT for VB function

+LCDVDD_R

+3VS

L19

0_0805_5%

1

C205

0.1U_0402_16V4Z

2

1 2

R80 4.7K_0402_5%

1 2

R81 4.7K_0402_5%

EC_INVT_PWM

GMCH_INVT_PWM

1.5A

12

1

C206

4.7U_0805_10V4Z

2

+LCD_VDD

LCD_EDID_CLK

LCD_EDID_DATA

@

1 2

R782 0_0402_5%

1 2

R783 0_0402_5%

INVT_PW M

INVT_PW M

12

R784
10K_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

LCD CONN.

LA-6032P

18 45Tuesday, March 23, 2010

E

of

1.0

A

B

C

D

E

HDMI_CLK-

1 1

HDMI_CLK+

5

3

Q4B

+3VS

HDMI_TX0+
HDMI_TX0­HDMI_TX1+
HDMI_TX1-

HDMI_TX2+
HDMI_TX2-

HDMI_CLK-

2.2K_0402_5%

2

61

2N7002DW-T/R7_SOT363-6

Q4A

R87

100K_0402_5%

12

R83

2.2K_0402_5%

R86
100K_0402_5%

1 2

+HDMI_5V_OUT

12

R856

2

1

1 2

12

R855

2.2K_0402_5%

HDMI_SDATA

HDMI_HPD

C218

0.1U_0402_16V4Z

HPD 12

B

HDMI_SCLK

C219 0.1U_0402_16V7K

HDMI_TXD0+11

HDMI_TXD0-11

HDMI_TXD1+11

HDMI_TXD1-11

HDMI_TXD2+11
HDMI_TXD2-11
HDMI_CLK0+11
HDMI_CLK0-11

2 2

4.7K_0402_5%

HDMIDAT_UMA12

3 3

4 4

HDMICLK_UMA12

0.1U_0402_16V4Z

C217

1 2

C220 0.1U_0402_16V7K

1 2

C221 0.1U_0402_16V7K

1 2

C222 0.1U_0402_16V7K

1 2

C223 0.1U_0402_16V7K

1 2

C224 0.1U_0402_16V7K

1 2

C225 0.1U_0402_16V7K

1 2

C226 0.1U_0402_16V7K

1 2

+3VS +3VS

12

R84

2

1

A

R85

4.7K_0402_5%

1 2

2N7002DW-T/R7_SOT363-6

+5VS

1

5

P

4

OE#

A2Y

G

U6
SN74AHCT1G125GW_SOT353-5

3

4

HDMI_TX0-

HDMI_TX0+

HDMI_TX1- HDMI_R_D1-

HDMI_TX1+

HDMI_TX2-

HDMI_TX2+

@

1 2

R88 0_0402_5%

L21

1

1

4

4

WCM-2012-900T_0805

@

1 2

@

1 2

L22

1

1

4

4

WCM-2012-900T_0805

@

1 2

@

1 2

L23

1

1

4

4

WCM-2012-900T_0805

@

1 2

@

1 2

L24

1

1

4

4

WCM-2012-900T_0805

@

1 2

2

2

3

3

R91 0_0402_5%

R92 0_0402_5%

2

2

3

3

R95 0_0402_5%

R96 0_0402_5%

2

2

3

3

R99 0_0402_5%

R100 0_0402_5%

2

2

3

3

R103 0_0402_5%

HDMI_CLK+

HDMI_CLK-

HDMI_TX0-

HDMI_TX0+

HDMI_TX1-

HDMI_TX1+

HDMI_TX2+

HDMI_TX2-

1 2

R89 715_0402_1%

1 2

R90 715_0402_1%

1 2

R93 715_0402_1%

1 2

R94 715_0402_1%

1 2

R97 715_0402_1%

1 2

R98 715_0402_1%

1 2

R101 715_0402_1%

1 2

R102 715_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

HDMI_R_CK-

HDMI_R_CK+HDMI_CLK+

HDMI_R_D0-

HDMI_R_D0+

HDMI_R_D1+

HDMI_R_D2-

HDMI_R_D2+

13

D

+5VS

2008/04/14 2009/04/14

2

G

Q6

2N7002_SOT23-3

Compal Secret Data

S

Deciphered Date

RB161M-20_SOD123-2

D

D8

2 1

+5VS_HDMI+5VS_HDMI

< HDMI Connector >

HDMI_HPD

+HDMI_5V_OUT

HDMI_SDATA
HDMI_SCLK

HDMI_R_CK-

HDMI_R_CK+

HDMI_R_D0-

HDMI_R_D0+

HDMI_R_D1-

HDMI_R_D1+

HDMI_R_D2-

HDMI_R_D2+

1/28 Update JHDMI1 footprint

Title

Size Document Number Rev

Date: Sheet

F1

2 1

1.1A_6V_MINISMDC110F-2

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

SUYIN_100042GR019M23BZR_19P-T

CONN@

GND
GND
GND
GND

1

C216

0.1U_0402_16V4Z

2

20
21
22
23

Compal Electronics, Inc.

HDMI/CEC

LA-6032P

+HDMI_5V_OUT+5VS

19 45Tuesday, March 23, 2010

E

1.0Custom

of

A

B

C

D

E

C524 150P_0402_50V8J

1 2

A_RST#

C227 0.1U_0402_16V7K

SB_RX0P11
SB_RX0N11
SB_RX1P11
SB_RX1N11
SB_RX2P11
SB_RX2N11
SB_RX3P11

1 1

SB_RX3N11

SB_TX0P11
SB_TX0N11
SB_TX1P11
SB_TX1N11
SB_TX2P11
SB_TX2N11
SB_TX3P11
SB_TX3N11

+PCIE_VDDR

L

+3VALW

C235

12

0.1U_0402_16V4Z

A_RST#

@

12

R106 8.2K_0402_5%

2 2

12/7 Add RS1~RS14 for internal clock gen

NB

NB

NB

CPU

LAN

WLAN

Card reader

2

13

D

FDV301N_NL_SOT23-3

+3VS

1 2

R314

4.7K_0402_5%

+1.8VS

3 3

H_PWRGD

G

S

Q29

2

1

CLK_SBLINK_BCLK12

CLK_SBLINK_BCLK#12

CLK_NB_REFCLK12

CLK_NB_REFCLK#12

CLK_CPU_BCLK7

CLK_CPU_BCLK#7

CLK_PCIE_MCARD226

CLK_PCIE_MCARD2#26

CLK_PCIE_MCARD030
CLK_PCIE_MCARD0#30

5

P

B

Y

A

G

3

CLK_NBHT12
CLK_NBHT#12

CLK_PCIE_LAN27
CLK_PCIE_LAN#27

H_PWRGD_L 42

U8

PLT_RST#

4

NC7SZ08P5X_NL_SC70-5

RS1 0_0402_5%
RS2 0_0402_5%

RS3 0_0402_5%
RS4 0_0402_5%

RS5 0_0402_5%
RS6 0_0402_5%

RS7 0_0402_5%
RS8 0_0402_5%

RS9 0_0402_5%
RS10 0_0402_5%

RS11 0_0402_5%
RS12 0_0402_5%

RS13 0_0402_5%
RS14 0_0402_5%

1 2

C229 0.1U_0402_16V7K

1 2

C230 0.1U_0402_16V7K

1 2

C231 0.1U_0402_16V7K

1 2

C232 0.1U_0402_16V7K

1 2

C228 0.1U_0402_16V7K

1 2

C233 0.1U_0402_16V7K

1 2

C234 0.1U_0402_16V7K

1 2

Close to SB within 1"

PLT_RST# 12,15,26,27,30, 31,32

12
12

12
12

12
12

12
12

12
12

12
12

12
12

level shift to ISL6265

ISL6265 PWROK input, TTL level: 0.8V~2.0V

When this pin is high, the SVI interface is
active and I2C protocol is running. While this
pin is low, the SVC, SVD, and VFIXE N input
states determine the pre-PWROK metal VID or
VFIX mode voltage. This pin must be low prior
to the ISL6265 PGOOD output going high

R326 33_0402_5%

12

SB_RX0P_C
SB_RX0N_C
SB_RX1P_C
SB_RX1N_C
SB_RX2P_C
SB_RX2N_C
SB_RX3P_C
SB_RX3N_C

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

R104 590_0402_1%
R105 2K _0402_1%

12
12

CLK_SBLINK_BCLK_R
CLK_SBLINK_BCLK#_R

CLK_NB_REFCLK_R
CLK_NB_REFCLK#_R

CLK_NBHT_R
CLK_NBHT#_R

CLK_CPU_BCLK_R
CLK_CPU_BCLK#_R

CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R

CLK_PCIE_MCARD2_R
CLK_PCIE_MCARD2#_R

CLK_PCIE_MCARD0_R
CLK_PCIE_MCARD0#_R

T34 PAD@

25M_CLK_X1

25M_CLK_X2

2/2 C240 C244 22P-->18P for RT C fail issue

C704
22P_0402_50V8J

12

4 4

A

25MHZ_20PF_7A25000012

C705 22P_0402_50V8J

12

Y6

12

12

B

R829
1M_0402_5%

25M_CLK_X1

25M_CLK_X2

U7A

P1

PCIE_RST#

L1

A_RST#

AD26

A_TX0P

AD27

A_TX0N

AC28

A_TX1P

AC29

A_TX1N

AB29

A_TX2P

AB28

A_TX2N

AB26

A_TX3P

AB27

A_TX3N

AE24

A_RX0P

AE23

A_RX0N

AD25

A_RX1P

AD24

A_RX1N

AC24

A_RX2P

AC25

A_RX2N

AB25

A_RX3P

AB24

A_RX3N

AD29

PCIE_CALRP

AD28

PCIE_CALRN

AA28

GPP_TX0P

AA29

GPP_TX0N

Y29

GPP_TX1P

Y28

GPP_TX1N

Y26

GPP_TX2P

Y27

GPP_TX2N

W28

GPP_TX3P

W29

GPP_TX3N

AA22

GPP_RX0P

Y21

GPP_RX0N

AA25

GPP_RX1P

AA24

GPP_RX1N

W23

GPP_RX2P

V24

GPP_RX2N

W24

GPP_RX3P

W25

GPP_RX3N

M23

PCIE_RCLKP/NB_LNK_CLKP

P23

PCIE_RCLKN/NB_LNK_CL KN

U29

NB_DISP_CLKP

U28

NB_DISP_CLKN

T26

NB_HT_CLKP

T27

NB_HT_CLKN

V21

CPU_HT_CLKP

T21

CPU_HT_CLKN

V23

SLT_GFX_CLKP

T23

SLT_GFX_CLKN

L29

GPP_CLK0P

L28

GPP_CLK0N

N29

GPP_CLK1P

N28

GPP_CLK1N

M29

GPP_CLK2P

M28

GPP_CLK2N

T25

GPP_CLK3P

V25

GPP_CLK3N

L24

GPP_CLK4P

L23

GPP_CLK4N

P25

GPP_CLK5P

M25

GPP_CLK5N

P29

GPP_CLK6P

P28

GPP_CLK6N

N26

GPP_CLK7P

N27

GPP_CLK7N

T29

GPP_CLK8P

T28

GPP_CLK8N

L25

14M_25M_48M_OSC

L26

25M_X1

L27

25M_X2

Part 1 of 5

SB800

PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38

PCICLK4/14M_OSC/GPO39

PCI CLKS

PCI EXPRESS INTERFACES

PCI INTERFACELPC

REQ1#/GPIO40
REQ2#/CLK_REQ8#/GPIO41
REQ3#/CLK_REQ5#/GPIO42

GNT3#/CLK_REQ7#/GPIO46

LDRQ1#/CLK_REQ6#/GPIO49

CLOCK GENERATOR

SERIRQ/GPIO48

ALLOW_LDTSTP/DMA_ACTIVE#

CPU

INTRUDER_ALERT#

RTC

VDDBT_RTC_G

SB820M_FCBGA605 SB820MR1@

C240 18P_0402_50V8J

12

Y2

3

OSC

NC

2

OSC

C244

NC

12

32.768KHZ_12.5PF_Q13MC14610002

4

1

18P_0402_50V8J

12

R132
20M_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE CO MPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. N EITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

W2

PCICLK0

PCIRST#

AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8

AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31

CBE0#
CBE1#
CBE2#
CBE3#

FRAME#

DEVSEL#

IRDY#

TRDY#

PAR
STOP#
PERR#
SERR#
REQ0#

GNT0#

GNT1#/GPO44
GNT2#/GPO45

CLKRUN#

LOCK#

INTE#/GPIO32
INTF#/GPIO33
INTG#/GPIO34
INTH#/GPIO35

LPCCLK0
LPCCLK1

LAD0
LAD1
LAD2
LAD3

LFRAME#

LDRQ0#

PROCHOT#

LDT_PG
LDT_STP#
LDT_RST#

32K_X1

32K_X2

RTCCLK

SB_32KHI

SB_32KHO

2008/04/14 2009/04/14

PCI_CLK1

W1

PCI_CLK2

W3

PCI_CLK3

W4

PCI_CLK4

Y1

V2

AA1
AA4
AA3
AB1
AA5
AB2
AB6
AB5
AA6
AC2
AC3
AC4
AC1
AD1
AD2
AC6
AE2
AE1
AF8
AE3
AF1
AG1
AF2
AE9
AD9
AC11
AF6
AF4
AF3
AH2
AG2
AH3
AA8
AD5
AD8
AA10
AE8
AB9
AJ3
AE7
AC5
AF5
AE6
AE4
AE11
AH5
AH4
AC12
AD12
AJ5
AH6
AB12
AB11
AD7

BT_PWR#

AJ6

BT_DET#

AG6

BT_RST#

AG4
AJ4

CLK_PCI_EC1

H24
H25

LPC_AD0

J27

LPC_AD1

J26

LPC_AD2

H29

LPC_AD3

H28

LPC_FRAME#

G28
J25
AA18

SERIRQ

AB19

CPU_LDT_REQ#

G21

H_PROCHOT#

H21

H_PWRGD

K19

LDT_STOP#

G22

LDT_RST#

J24

SB_32KHI

C1

SB_32KHO

C2

R920 0_0402_5%

D2
B2
B1

C241

0.1U_0402_16V4Z

Compal Secret Data

PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29

T31 PAD @

T32 PAD @

1 2

1

C242

2

Deciphered Date

3G_OFF# 26

BT_PWR# 26,29
BT_DET# 29
BT_RST# 29

LPC_AD0 31,32
LPC_AD1 31,32

LPC_AD2 31,32
LPC_AD3 31,32
LPC_FRAME# 31,32

@

+SB_VBAT

1

2

1U_0402_6.3V4Z

LPC_CLK1 24,32

SERIRQ 31,32

CPU_LDT_REQ# 12
H_PROCHOT# 7

H_PWRGD 7,42

LDT_STOP# 7,12

LDT_RST# 7

120_0402_5%

W=20mils

PCI_CLK1 24
PCI_CLK2 24
PCI_CLK3 24
PCI_CLK4 24

PCI_AD23 24
PCI_AD24 24
PCI_AD25 24
PCI_AD26 24
PCI_AD27 24
PCI_AD28 24
PCI_AD29 24

RTCCLK

R129

1 2

JUMP_43X39

D

2/8 GPIO35-->GPIO40 for 3G_OFF#

R125 22_0402_5%

1 2

RTCCLK 31

3/22 add RTCCLK to KBC 32.7 68

W=20milsW=20milsW=20mils

2

2

1

1

R917

1 2

120_0402_5%

+RTCVCC

Custom

+RTCVCC_R

J1

@

0.1U_0402_16V4Z

CLK_PCI_EC 24,31

D9

3

2

BAS40-04_SOT23-3

LA-6032P

E

+RTCBATT

1

20 45Tuesday, March 23, 2010

+CHGRTC

of

2

C640

22P_0402_50V8J

1

W=20mils

R918

1 2

1K_0402_5%

Title

SB820-PCIE/PCI/ACPI/LPC/RTC

Size Document Num ber Rev

Date: Sheet

1

C243

2

Compal Electronics, Inc.

1.0

A

B

C

D

E

U7D

J2

PCI_PME#/GEVENT4#

K1

RI#/GEVENT22#

D3

SPI_CS3#/GBE_STAT1/GEVENT21#

F1

SLP_S3#

H1

SLP_S5#

F2

PWR_BTN#

H5

PWR_GOOD

G6

SUS_STAT#

B3

TEST0

C4

TEST1/TMS

F6

TEST2

AD21

GA20IN/GEVENT0#

AE21

KBRST#/GEVENT1#

K2

LPC_PME#/GEVENT3#

J29

LPC_SMI#/GEVENT23#

H2

GEVENT5#

J1

SYS_RESET#/GEVENT19#

H6

WAKE#/GEVENT8#

F3

IR_RX1/GEVENT20#

J6

THRMTRIP#/SMBALERT#/GEVENT2#

AC19

NB_PWRGD

G1

RSMRST#

AD19

CLK_REQ4#/S ATA_IS0#/GPIO64

AA16

CLK_REQ3#/S ATA_IS1#/GPIO63

AB21

SMARTVOLT1/SATA_IS2#/GPIO50

AC18

CLK_REQ0#/S ATA_IS3#/GPIO60

AF20

SATA_IS4#/F ANOUT3/GPIO55

AE19

SATA_IS5#/FANIN3/GPIO59

AF19

SPKR/GPIO66

AD22

SCL0/GPIO43

AE22

SDA0/GPIO47

F5

SCL1/GPIO227

F4

SDA1/GPIO228

AH21

CLK_REQ2#/FANIN4/GPIO62

AB18

CLK_REQ1#/FANOUT4/GPIO61

E1

IR_LED#/LLB#/GPIO184

AJ21

SMARTVOLT2/SHUTDOWN#/GPIO51

H4

DDR3_RST#/GEVENT7#

D5

GBE_LED0/GP IO183

D7

GBE_LED1/GEVENT9#

G5

GBE_LED2/GEVENT10#

K3

GBE_STAT0/GEVENT11#

AA20

CLK_REQG#/GP IO65/OSCIN

H3

BLINK/USB_OC7#/GEVENT18#

D1

USB_OC6#/IR_TX1/GEVENT6#

E4

USB_OC5#/IR_TX0/GEVENT17#

D4

USB_OC4#/IR_RX0/GEVENT16#

E8

USB_OC3#/AC_PRES/TDO/GEVENT15#

F7

USB_OC2#/TCK/GEVENT14#

E7

USB_OC1#/TDI/GEVENT13#

F8

USB_OC0#/TRST#/GEVENT12#

M3

AZ_BITCLK

N1

AZ_SDOUT

L2

AZ_SDIN0/GP IO167

M2

AZ_SDIN1/GP IO168

M1

AZ_SDIN2/GP IO169

M4

AZ_SDIN3/GP IO170

N2

AZ_SYNC

P2

AZ_RST#

T1

GBE_COL

T4

GBE_CRS

L6

GBE_MDCK

L5

GBE_MDIO

T9

GBE_RXCLK

U1

GBE_RXD3

U3

GBE_RXD2

T2

GBE_RXD1

U2

GBE_RXD0

T5

GBE_RXCTL/RXDV

V5

GBE_RXERR

P5

GBE_TXCLK

M5

GBE_TXD3

P9

GBE_TXD2

T7

GBE_TXD1

P7

GBE_TXD0

M7

GBE_TXCTL/TXEN

P4

GBE_PHY_PD

M9

GBE_PHY_RST#

V7

GBE_PHY_INTR

E23

PS2_DAT/S DA4/GPIO187

E24

PS2_CLK/SCL4/GPIO188

F21

SPI_CS2#/GBE_STAT2/GPIO166

G29

FC_RST#/GPO160

D27

PS2KB_DAT/GPIO189

F28

PS2KB_CLK/GPIO190

F29

PS2M_DAT/GPIO191

E27

PS2M_CLK/GPIO192

SB800

Part 4 of 5

GBE LAN

HD AUDIO

EC_RSMRST#

PCH_SPKR
SMB_CK_CLK0
SMB_CK_DAT0
SMB_CK_CLK1
SMB_CK_DAT1

SP_DDR3_RST#_R

EC_LID_OUT#

USB_OC#2

USB_OC#0

PM_SLP_S3#
PM_SLP_S5#
PBTN_OUT#
SB_PWRGD
SUS_STAT#

T28PAD@
T29PAD@

T30PAD@

GATEA20
KB_RST#
EC_SCI#
EC_SMI#

EC_SWI#

H_THERMTRIP#
NB_PWRGD

GBE_COL
GBE_CRS

GBE_MDIO

GBE_RXERR

GBE_PHY_INTR

CIR_EN#

PM_SLP_S3#31
PM_SLP_S5#31
PBTN_OUT#31
SB_PWRGD31

1 1

+3VALW

1 2

R797 10K_0402_5%

12

R140 100K_0402_5%

EC_SWI#

EC_RSMRST#

12/7 Internal clock gen

LAN

+3VS

R141 2.2K_0402_5%

1 2

R142 2.2K_0402_5%

1 2

R134 4.7K_0402_5%

1 2

2 2

AZ_BITCLK_HD28

33P_0402_50V8J

+3VALW

3 3

R151 10K_0402_5%

R155 10K_0402_5%

12

12

R152 10K_0402_5%

R153 10K_0402_5%

R154 10K_0402_5%

12

12

12

SMB_CK_CLK0

SMB_CK_DAT0

SUS_STAT#

1

C632

2

GBE_MDIO

GBE_PHY_INTR

GBE_COL

GBE_CRS

GBE_RXERR

3/17 del CLKREQ_CR#

WLAN

3/17 for JMB389

AZ_SDOUT_HD28

HDA_SDOUT24

AZ_SDIN0_HD28

AZ_SYNC_HD28

AZ_RST_HD#28

+3VALW

R863 10K_0402_5%

SP_DDR3_RST#13

EC_LID_OUT#31

USB_OC#225,31
CR_CPPE#_SB30
USB_OC#029,31

10K_0402_5% @

CLKREQ_MCARD2#26

R807

12

SUS_STAT#12,15

GATEA2031
KB_RST#31
EC_SCI#31
EC_SMI#31

EC_SWI#27

H_THERMTRIP#7

NB_PWRGD12

EC_RSMRST#31

CLKREQ_LAN27

PCH_SPKR28
SMB_CK_CLK09,10
SMB_CK_DAT09,10
SMB_CK_CLK126
SMB_CK_DAT126

1 2

0_0402_5%

SIDE@

R306 33_0402_5%

1 2

R307 33_0402_5%

1 2

R310 33_0402_5%

1 2

R311 33_0402_5%

1 2

1 2

CIR_EN#

R343

SB820M_FCBGA605 SB820MR1@

USBCLK/14M_25M_48M_OSC

ACPI / WAKE UP EVENTS

GPIO

USB OC

EC_PWM0/EC_TIMER0/GPIO197
EC_PWM1/EC_TIMER1/GPIO198
EC_PWM2/EC_TIMER2/GPIO199
EC_PWM3/EC_TIMER3/GPIO200

USB_FSD1P/GPIO186

USB_FSD0P/GPIO185

USB 1.1 USB MISCEMBEDDED CTRL

USB 2.0

SCL2/GPIO193

SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196

KSI_0/GPIO201

KSI_1/GPIO202

KSI_2/GPIO203

KSI_3/GPIO204

KSI_4/GPIO205

KSI_5/GPIO206

KSI_6/GPIO207

KSI_7/GPIO208

KSO_0/GPIO209
KSO_1/GPIO210
KSO_2/GPIO211
KSO_3/GPIO212
KSO_4/GPIO213
KSO_5/GPIO214
KSO_6/GPIO215
KSO_7/GPIO216
KSO_8/GPIO217

KSO_9/GPIO218
KSO_10/GPIO219
KSO_11/GPIO220
KSO_12/GPIO221
KSO_13/GPIO222
KSO_14/GPIO223
KSO_15/GPIO224
KSO_16/GPIO225
KSO_17/GPIO226

USB_RCOMP

USB_FSD1N

USB_FSD0N

USB_HSD13P
USB_HSD13N

USB_HSD12P
USB_HSD12N

USB_HSD11P

USB_HSD11N

USB_HSD10P
USB_HSD10N

USB_HSD9P
USB_HSD9N

USB_HSD8P
USB_HSD8N

USB_HSD7P
USB_HSD7N

USB_HSD6P
USB_HSD6N

USB_HSD5P
USB_HSD5N

USB_HSD4P
USB_HSD4N

USB_HSD3P
USB_HSD3N

USB_HSD2P
USB_HSD2N

USB_HSD1P
USB_HSD1N

USB_HSD0P
USB_HSD0N

EMBEDDED CTRL

USBCLK

A10

USB_RCOMP

G19

L

J10
H11

Close to SB within 1"

H9
J8

B12
A12

F11
E11

E14
E12

J12
J14

USB20_P9

A13

USB20_N9

B13

USB20_P8

D13

USB20_N8

C13

G12
G14

USB20_P6

G16

USB20_N6

G18

USB20_P5

D16

USB20_N5

C16

B14

1/21 Change USB port10 to USB port5 on WWAN

A14

E18
E16

USB20_P2

J16

USB20_N2

J18

USB20_P1

B17

USB20_N1

A17

USB20_P0

A16

USB20_N0

B16

D25
F23

SB_SIC

B26

SB_SID

E26
F25
E22
F22
E21

GPIO201

G24

GPIO202

G25

GPIO203

E28
E29
D29
D28
C29
C28

B28
A27
B27
D26
A26
C26
A24
B25
A25
D24
B24
C24
B23
A23
D22
C22
A22
B22

1 2

T35 PAD@

R13311.8K_0402_1%

USB20_P9 18
USB20_N9 18

USB20_P8 26
USB20_N8 26

USB20_P6 29
USB20_N6 29

USB20_P5 26
USB20_N5 26

USB20_P2 25
USB20_N2 25

USB20_P1 29
USB20_N1 29

USB20_P0 29
USB20_N0 29

GPIO199 24
GPIO200 24

AMD-S 11.6

AMD-M 13.3

1/31 R133 8.2K-->11.8K

STRAP PIN
STRAP PIN

USB-9 Int Camera

USB-8 WLAN

USB-6 Bluetooth

USB-5 WWAN

USB-2 USB/eSATA

USB-1 Right side

USB-0 Right side

12

10K_0402_5%

12

10K_0402_5%

GPIO201
GPIO202
GPIO203

12

R823

10K_0402_5%

12

R826

10K_0402_5%

@

GPIO201 GPIO202 GPIO203

111

110

OHCI4

EHCI13 / OHCI3

EHCI2 / OHCI2

EHCI1 / OHCI1

<Wake Up support>

R824

R827

@

+3VALW

12

R825

10K_0402_5%

12

R828

10K_0402_5%

M@

S@

+3VALW

4 4

@

1 2

R315 100K_0402_5%

1 2

R316 2.2K_0402_5%

1 2

R317 2.2K_0402_5%

1 2

R318 10K_0402_5%

1 2

R319 2.2K_0402_5%

1 2

R320 2.2K_0402_5%

A

EC_LID_OUT#

SB_SIC

SB_SID

H_THERMTRIP#

SMB_CK_CLK1

SMB_CK_DAT1

/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet

Compal Electronics, Inc.

SB820 USB/HD Audio

LA-6032P

21 45Tuesday, March 23, 2010

E

of

1.0Custom

A

SATA_TX0+25

HDD

1 1

eSATA

2 2

SATA_TX0-25

SATA_RX0-25
SATA_RX0+25

SATA_TX3+25
SATA_TX3-25

SATA_RX3-25
SATA_RX3+25

Close to SB within 1"

L

+1.1VS_SATA +3VALW

SATA_LED#33

R156 10K_0402_5%

1 2

+3VS

SATA_TX0+
SATA_TX0-

SATA_RX0­SATA_RX0+

SATA_TX3+
SATA_TX3-

SATA_RX3­SATA_RX3+

R321 1K_0402_1%

R322 931_0402_1%

12
12

T36 PAD@

T37 PAD@

SATA_CALRP
SATA_CALRN

SATA_X1

SATA_X2

AH9

AH8

AH10

AJ10

AG10

AF10

AG12

AF12

AJ12

AH12

AH14

AJ14

AG14

AF14

AG17

AF17

AJ17

AH17

AJ18

AH18

AH19

AJ19

AB14
AA14

AD11

AD16

AC16

B

U7B

AJ9

AJ8

SATA_TX0P
SATA_TX0N

SATA_RX0N
SATA_RX0P

SATA_TX1P
SATA_TX1N

SATA_RX1N
SATA_RX1P

SATA_TX2P
SATA_TX2N

SATA_RX2N
SATA_RX2P

SATA_TX3P
SATA_TX3N

SATA_RX3N
SATA_RX3P

SATA_TX4P
SATA_TX4N

SATA_RX4N
SATA_RX4P

SATA_TX5P
SATA_TX5N

SATA_RX5N
SATA_RX5P

SATA_CALRP
SATA_CALRN

SATA_ACT#/GPIO67

SATA_X1

SATA_X2

SB800

Part 2 of 5

SERIAL ATA

HW MONITOR

FC_CLK

FC_FBCLKOUT

FC_FBCLKIN

FC_OE#/GPIOD145

FC_AVD#/GPIOD146

FC_WE#/GPIOD148
FC_CE1#/GPIOD149
FC_CE2#/GPIOD150

FC_INT1/GPIOD 144

FC_INT2/GPIOD 147

FC_ADQ0/GPIOD128
FC_ADQ1/GPIOD129
FC_ADQ2/GPIOD130
FC_ADQ3/GPIOD131
FC_ADQ4/GPIOD132
FC_ADQ5/GPIOD133
FC_ADQ6/GPIOD134
FC_ADQ7/GPIOD135
FC_ADQ8/GPIOD136

FC_ADQ9/GPIOD137
FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139
FC_ADQ12/GPIOD140

FLASH

FC_ADQ13/GPIOD141
FC_ADQ14/GPIOD142
FC_ADQ15/GPIOD143

FANOUT0/GPIO5 2
FANOUT1/GPIO5 3
FANOUT2/GPIO5 4

FANIN0/GPIO56
FANIN1/GPIO57
FANIN2/GPIO58

TEMPIN0/GPIO1 71
TEMPIN1/GPIO1 72
TEMPIN2/GPIO1 73

TEMPIN3/TALERT#/GPIO174

TEMP_COMM

VIN0/GPIO175
VIN1/GPIO176
VIN2/GPIO177
VIN3/GPIO178
VIN4/GPIO179
VIN5/GPIO180

VIN6/GBE_STAT3/GPIO181

VIN7/GBE_LED3/GPIO182

AH28
AG28
AF26

AF28
AG29
AG26
AF27
AE29
AF29
AH27

AJ27
AJ26
AH25
AH24
AG23
AH23
AJ22
AG21
AF21
AH22
AJ23
AF23
AJ24
AJ25
AG25
AH26

W5
W6
Y9

W7
V9
W8

B6
A6
A5
B5
C7

A3
B4
A4
C5
A7
B7
B8
A8

C

WLAN_PWR_EN#

ACIN_SB
WWAN_PWR_EN#

SLP_CHG_M3_SB_NEW
SLP_CHG_M3_SB
SLP_CHG_M4_SB

CR_WAKE# 30

WLAN_PWR_EN# 26

WWAN_PWR_EN# 26

R916 0_0402_5%

1 2

R865 0_0402_5%@

1 2

R866 0_0402_5%

1 2

D

3/17 for JMB389

1 2

R157 150K_0402_5%

2 1

CH751H-40PT_SOD323-2

SLP_CHG_M3
SLP_CHG_M4

E

D10

ACIN 31,33,35

SLP_CHG_M3 25,31
SLP_CHG_M4 25,31

1/20 Colay USB charger net

DO
DI
CLK
CS#

1/25 Del R164 Y3 C246 C247

3 3

+3VALW

1

C470

0.1U_0402_16V4Z

2

@

CS#

CLK

DI DO

20mils

add TP36 TP37

ࡉࡉࡉࡉ

U47

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

SST25LF080A_SO8-200mil

VSS

4

2

Q

J5

SPI_DI/GPIO164

E2

SPI_DO/GPIO163

K4

SPI_CLK/GPIO162

K9

SPI_CS1#/GPIO165

G2

ROM_RST#/GPIO161

SPI ROM

SB820M_FCBGA605 SB820MR1@

CLK

12

R859

@

0_0402_5%

2

C707

@

22P_0402_50V8J

1

NC1
NC2

G27
Y2

SLP_CHG_M3

SLP_CHG_M4

1 2

R162 100K_0402_5%

1 2

R163 100K_0402_5%

+3VALW

12/31 SMT memo control (256KB MX25L1605DM2I-12G SOP 8P)

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

SB820 SATA/IDE/SPI

LA-6032P

22 45Tuesday, March 23, 2010

E

of

1.0

A

B

C

D

E

N13
R15
N17
U13
U17
V12
V18
W12
W18

K28
K29
J28
K26
J21
J20
K21
J22

V1

M10

L7
L9

M6
P8

A21
D21
B21
K10
L10
J9
T6
T8

F26
G26

TBDmA

M8

A11
B11

M21

L22

VDDPL_3.3V_USB

F19

D6

L20

1 2

510mA

+1.1VS_VDDC

32mA

+3VALW

VDDCR_1.1V_USB

VDDPL_3.3V

VDDPL_1.1V

VDDXL_3.3V

L32

400mA

113mA

+3VALW

1

2

2.2U_0603_6.3V4Z

1 2

R165 0_0805_5%

1 2

1

C2621U_0402_6.3V4Z

2

1 2

C2762.2U_0603_6.3V4Z

1 2

C2782.2U_0603_6.3V4Z

197mA

C292

10U_0603_6.3V6M

VDDPL_1.1V

62mA 17mA

C300

+1.1VS

C24910U_0805_10V6K

C2551U_0402_6.3V4Z

12

C2671U_0402_6.3V4Z

12

C2580.1U_0402_16V4Z

12

C2600.1U_0402_16V4Z

12

1

2

C2681U_0402_6.3V4Z

C2530.1U_0402_10V6K

2

1

+3VALW

1

2

C293

2

1

0.1U_0402_10V6K

1

C2972.2U

2

+3VALW

FBMA-L11-160808-221LMT_0603

1 2

FBMA-L11-201209-221LMA30T_0805

2

2

C2630.1U_0402_10V6K

C25422U_0805_6.3V6M

1

1

12

12

L29

1 2

FBMA-L11-160808-221LMT_0603

2

C294

1

0.1U_0402_10V6K

L31

1 2

FBMA-L11-160808-221LMT_0603

L34

1 2

L25

C2831U_0402_6.3V4Z

C2861U_0402_6.3V4Z

+1.1VALW

+1.1VALW

+3VALW

2

2

C3012.2U

C3020.1U

1

1

+1.1VS+1.1V_CKVDD

VDDPL_3.3V_USB

U7E

SB800

VSSIO_SATA_1
VSSIO_SATA_2
VSSIO_SATA_3
VSSIO_SATA_4
VSSIO_SATA_5
VSSIO_SATA_6
VSSIO_SATA_7
VSSIO_SATA_8
VSSIO_SATA_9
VSSIO_SATA_10
VSSIO_SATA_11
VSSIO_SATA_12
VSSIO_SATA_13
VSSIO_SATA_14
VSSIO_SATA_15
VSSIO_SATA_16
VSSIO_SATA_17
VSSIO_SATA_18
VSSIO_SATA_19

VSSIO_USB_1
VSSIO_USB_2
VSSIO_USB_3
VSSIO_USB_4
VSSIO_USB_5
VSSIO_USB_6
VSSIO_USB_7
VSSIO_USB_8
VSSIO_USB_9
VSSIO_USB_10
VSSIO_USB_11
VSSIO_USB_12
VSSIO_USB_13
VSSIO_USB_14
VSSIO_USB_15
VSSIO_USB_16
VSSIO_USB_17
VSSIO_USB_18
VSSIO_USB_19
VSSIO_USB_20
VSSIO_USB_21
VSSIO_USB_22
VSSIO_USB_23
VSSIO_USB_24
VSSIO_USB_25
VSSIO_USB_26
VSSIO_USB_27
VSSIO_USB_28

EFUSE

VSSAN_HWM

VSSXL

VSSIO_PCIECLK_1
VSSIO_PCIECLK_2
VSSIO_PCIECLK_3
VSSIO_PCIECLK_4
VSSIO_PCIECLK_5
VSSIO_PCIECLK_6
VSSIO_PCIECLK_7
VSSIO_PCIECLK_8
VSSIO_PCIECLK_9
VSSIO_PCIECLK_10
VSSIO_PCIECLK_11
VSSIO_PCIECLK_12
VSSIO_PCIECLK_13

Part 5 of 5

GROUND

VSSIO_PCIECLK_14
VSSIO_PCIECLK_15
VSSIO_PCIECLK_16
VSSIO_PCIECLK_17
VSSIO_PCIECLK_18
VSSIO_PCIECLK_19
VSSIO_PCIECLK_20
VSSIO_PCIECLK_21
VSSIO_PCIECLK_22
VSSIO_PCIECLK_23
VSSIO_PCIECLK_24
VSSIO_PCIECLK_25
VSSIO_PCIECLK_26
VSSIO_PCIECLK_27

AB16

AC14

AE12
AE14

AF11
AF13
AF16

AH11
AH13
AH16

AJ11
AJ13
AJ16

AF9

AG8
AH7

B10
K11

D10
D12
D14
D17

G11

H12
H14
H16
H18

K12
K14
K16
K18
H19

M19

P21
P20
M22
M24
M26
P22
P24
P26

V20

Y14
Y16

AJ7

A9

B9

E9

F9
F12
F14
F16

C9

F18

D9

J11
J19

Y4

D8

T20
T22
T24

J23

SB820M_FCBGA605 SB820MR1@

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52

VSSPL_SYS

AJ2
A28
A2
E5
D23
E25
E6
F24
N15
R13
R17
T10
P10
V11
U15
M18
V19
M11
L12
L18
J7
P3
V4
AD6
AD4
AB7
AC9
V8
W9
W10
AJ28
B29
U4
Y18
Y10
Y12
Y11
AA11
AA12
G4
J4
G8
G9
M12
AF25
H7
AH29
V10
P6
N4
L4
L8

M20

H23
H26
AA21
AA23
AB23
AD23
AA26
AC26
Y20
W21
W20
AE26
L21
K20

AC21

AA19

AF22

AE25

AF24

AC22

43mA

AE28

93mA

AD14

AJ20

AF18
AH20
AG19
AE18
AD18
AE16

L36

U7C

AH1

VDDIO_33_PCIGP_1

V6

VDDIO_33_PCIGP_2

Y19

VDDIO_33_PCIGP_3

AE5

VDDIO_33_PCIGP_4
VDDIO_33_PCIGP_5

AA2

VDDIO_33_PCIGP_6

AB4

VDDIO_33_PCIGP_7

AC8

VDDIO_33_PCIGP_8

AA7

VDDIO_33_PCIGP_9

AA9

VDDIO_33_PCIGP_10

AF7

VDDIO_33_PCIGP_11
VDDIO_33_PCIGP_12

VDDIO_18_FC_1
VDDIO_18_FC_2
VDDIO_18_FC_3
VDDIO_18_FC_4

VDDPL_33_PCIE

U26

VDDAN_11_PCIE_1

V22

VDDAN_11_PCIE_2

V26

VDDAN_11_PCIE_3

V27

VDDAN_11_PCIE_4

V28

VDDAN_11_PCIE_5

V29

VDDAN_11_PCIE_6

W22

VDDAN_11_PCIE_7

W26

VDDAN_11_PCIE_8

VDDPL_33_SATA

VDDAN_11_SATA_1
VDDAN_11_SATA_4
VDDAN_11_SATA_2
VDDAN_11_SATA_3
VDDAN_11_SATA_5
VDDAN_11_SATA_6
VDDAN_11_SATA_7

A18

VDDAN_33_USB_S_1

A19

VDDAN_33_USB_S_2

A20

VDDAN_33_USB_S_3

B18

VDDAN_33_USB_S_4

B19

VDDAN_33_USB_S_5

B20

VDDAN_33_USB_S_6

C18

VDDAN_33_USB_S_7

C20

VDDAN_33_USB_S_8

D18

VDDAN_33_USB_S_9

D19

VDDAN_33_USB_S_10

D20

VDDAN_33_USB_S_11

E19

VDDAN_33_USB_S_12

C11

VDDAN_11_USB_S_1

D11

VDDAN_11_USB_S_2

POWER

SB800

FLASH I/O

SB820M_FCBGA605 SB820MR1@

VDDPL_3.3V

1

47mA

C304

2

2.2U_0603_6.3V4Z

Part 3 of 5

CORE S03.3V_S5 I/O

PCI/GPIO I/O

VDDCR_11_GBE_S_1
VDDCR_11_GBE_S_2

GBE LAN

PCI EXPRESSSERIAL ATA

CORE S5

VDDCR_11_USB_S_1
VDDCR_11_USB_S_2

USB I/O

PLL CLKGEN I/O

VDDAN_33_HWM_S

VDDCR_11_1
VDDCR_11_2
VDDCR_11_3
VDDCR_11_4
VDDCR_11_5
VDDCR_11_6
VDDCR_11_7
VDDCR_11_8
VDDCR_11_9

VDDAN_11_CLK_1
VDDAN_11_CLK_2
VDDAN_11_CLK_3
VDDAN_11_CLK_4
VDDAN_11_CLK_5
VDDAN_11_CLK_6
VDDAN_11_CLK_7
VDDAN_11_CLK_8

VDDRF_GBE_S

VDDIO_33_GBE_S

VDDIO_GBE_S_1
VDDIO_GBE_S_2

VDDIO_33_S_1
VDDIO_33_S_2
VDDIO_33_S_3
VDDIO_33_S_4
VDDIO_33_S_5
VDDIO_33_S_6
VDDIO_33_S_7
VDDIO_33_S_8

VDDCR_11_S_1
VDDCR_11_S_2

VDDIO_AZ_S

VDDPL_33_SYS

VDDPL_11_SYS_S

VDDPL_33_USB_S

VDDXL_33_S

+1.1VALW

FBMA-L11-160808-221LMT_0603

+3VS

1 1

2 2

+1.1VALW

3 3

+3VS

L35

1 2

FBMA-L11-160808-221LMT_0603

C248 22U_0805_6.3V6M

12

C266 1U_0402_6.3V4Z@

1 2

C256 1U_0402_6.3V4Z@

1 2

C257 1U_0402_6.3V4Z@

1 2

C259 0.1U_0402_16V4Z

1 2

C261 0.1U_0402_16V4Z

1 2

C252 0.1U_0402_16V4Z

1 2

+1.1VS

+1.1VS

L30

0_0805_5%

1

2

12

VDDPL_3.3V_PCIE

C303

2.2U_0603_6.3V4Z

L26

0_0805_5%

C269 22U_0805_6.3V6M
C270 1U_0402_6.3V4Z @

1 2

C272 1U_0402_6.3V4Z

1 2

C273 1U_0402_6.3V4Z

1 2

C274 0.1U_0402_16V4Z

1 2

C275 0.1U_0402_16V4Z

1 2

0_0805_5%

C277 22U_0805_6.3V6M
C279 1U_0402_6.3V4Z

1 2

C280 1U_0402_6.3V4Z

1 2

C281 0.1U_0402_16V4Z

1 2

C282 0.1U_0402_16V4Z

1 2

0_0805_5%

C284 10U_0805_10V6K

1 2

C285 10U_0805_10V6K

1 2

C287 1U_0402_6.3V4Z

1 2

C288 1U_0402_6.3V4Z

1 2

C289 0.1U_0402_16V4Z

1 2

+1.1V_USB

1

1

C2950.1U_0402_16V4Z

C2962.2U_0603_6.3V4Z

2

2

1 2

R166 0_0402_5%

VDDPL_3.3V_PCIE

12

600mA

12

VDDPL_3.3V_SATA

L27

12

567mA

12

L28

12

658mA

@

VDDAN_1.1V_USB

TBDmA

+PCIE_VDDR

+1.1VS_SATA

+AVDD_USB+3VALW

+3VS

1 2

FBMA-L11-160808-221LMT_0603

131mA

+3VS

4 4

L33

1 2

FBMA-L11-160808-221LMT_0603

A

VDDPL_3.3V_SATA

1

C299

2.2U_0603_6.3V4Z

2

+3VALW

1

C298

2

2.2U_0603_6.3V4Z

L

C298 near U7.M8

B

/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SB820 Power/GND

LA-6032P

23 45Tuesday, March 23, 2010

E

of

1.0Custom

A

B

C

D

E

REQUIRED STRAPS

AZ_SDOUT

PULL

1 1

HIGH

PULL
LOW

LOW POWER
MODE

Performance
MODE

DEFAULT

PCI_CLK1

ALLOW PCIE
GEN2

FORCE PCIE
GEN1

DEFAULT

+3VS +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW+3VALW

Check Internal PU/PD

PCI_CLK2 PCI_CLK3

WATCHDOG
TIMER
ENABLE

WATCHDOG
TIMER
DISABLE

DEFAULT

USE
DEBUG
STRAP

IGNOR E
DEBUG
STRAP

DEFAULT

PCI_CLK4

Inter CLK
Gen Mode

Enable

DEFAULT

Inter CLK
Gen Mode

Disable

EC
ENABLE

EC
DISABLE

DEFAULT

LCP_CLK1LPC_ CLK0

CLOCKGEN
ENABLE

DEFAULT

CLOCKGEN
DISABLE

GPIO200
(EC_PWM3)

GPIO199
(EC_PWM2)

H,H = Reserved

H,L = SPI ROM(Default)

L,H = LPC ROM

L,L = FWH ROM

L,H = LPC ROM(Default)

12

R200

10K_0402_5%

HDA_SDOUT21

PCI_CLK120
PCI_CLK220
PCI_CLK320
PCI_CLK420

2 2

CLK_PCI_EC20,31

LPC_CLK120,32
GPIO20021
GPIO19921

@

R209

10K_0402_5%

12

R170

10K_0402_5%

@

R180

10K_0402_5%

12

12

R167

10K_0402_5%

@

R177

10K_0402_5%

12

R168

10K_0402_5%

@

12

R169

10K_0402_5%

12

R171

10K_0402_5%

@

12

R349

10K_0402_5%

12

12

R175

2.2K_0402_5%

12

Option 1:SPI Flash (2MB*1) for EC

R176

2.2K_0402_5%

@

H,L = SPI ROM

Option 2:SPI Flash (256KB*1) for EC
SPI Flash (2MB*1) for SB (set up strap pin)

12/31 SMT memo control

12

@

R185

C706

2.2K_0402_5%

22P_0402_50V8J

R186

2.2K_0402_5%

12/12 Add cC706 for EMI request

12

12/31 SMT memo control

R179

10K_0402_5%

@

12

12

R178

10K_0402_5%

12

R181

10K_0402_5%

12

R221

10K_0402_5%

@

12

1

2

12/12 Fine tune SB820 int clock gen strap pin

DEBUG STRAPS

+3VS+3VS

12

10K_0402_5%

R187

10K_0402_5%

12

12

R190

2.2K_0402_5%

@

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

12

R191

2.2K_0402_5%

@

R192

@

SB820 STRAPS

LA-6032P

E

12

2.2K_0402_5%

24 45Tuesday, March 23, 2010

of

1.0

R189

2.2K_0402_5%

@

12

12

R188

2.2K_0402_5%

@

D

3 3

4 4

A

SB800 HAS 15K INTERNAL PU FOR PCI_AD[27:23]

PCI_AD27 PCI_AD26

PULL
HIGH

PULL
LOW

PLL

DEFAULT

BYPASS
PCI PLL

DISABLE ILA
AUTORUN

DEFAULT

ENABLE ILA
AUTORUN

Check AD29,AD28 strap function

B

PCI_AD25 PCI_AD24

USE FC PLLUSE PCI

DEFAULT

BYPASS
FC PLL

USE DEFAULT
PCIE STRAPS

DEFAULT

USE EEPROM
PCIE STRAPS

check default

PCI_AD23

DISABLE PCI
MEM BOOT

DEFAULT

ENABLE PCI
MEM BOOT

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/04/14 2009/04/14

PCI_AD2920
PCI_AD2820
PCI_AD2720
PCI_AD2620
PCI_AD2520
PCI_AD2420
PCI_AD2320

Compal Secret Data

R244

Deciphered Date

A

B

C

D

E

SATA transfer board

+5VS

1.2A

1

C305

10U_0805_10V4Z

1 1

2

13
14

ACES_85201-1205N

Place closely JHDD SATA CONN

L

1

C306

0.1U_0402_16V4Z

2

JHDD1

1

1

2

2

3

3

4

4

5

GND
GND

CONN@

5
6
7
8

9
10
11
12

SATA_C_TX0+

6

SATA_C_TX0-

7
8

SATA_C_RX0-

9

SATA_C_RX0+

10
11
12

1

C307

0.1U_0402_16V4Z

2

1

C308

0.1U_0402_16V4Z

2

+5VS

C309 0.01U_0402_25V7K

1 2

C310 0.01U_0402_25V7K

1 2

C311 0.01U_0402_25V7K

1 2

C312 0.01U_0402_25V7K

1 2

2/2 Update JHDD1 10pin-->12pin

SATA_TX0+ 22
SATA_TX0- 22

SATA_RX0- 22
SATA_RX0+ 22

03/11 Del JHDD2

SATA FFC conn
Pin=12pin, pitch=1.0

2 2

E-SATA/USB

+3VALW

USB20_P2_R_U

USB20_N2_R_U

USB20_P221

USB20_N221

3 3

SLP_CHG_M322,31

SLP_CHG_M422,31

+USB_VCCB

4 4

USB20_P2

USB20_N2

USB20_N2_R_U

SLP_CHG_M3

Mode 3

Mode 4

HIGH

LOW HIGH

A

U10

1

1D+

2

1D-

3

2D+

4

2D-

GND5OE#

TS3USB221RSER_QFN10_2x1P5

U11

1

1OE#

4

2OE#

10

3OE#

13

4OE#

2

1A

5

2A

9

3A

12

4A

14

VCC

2

SN74CBT3125PWRG4_TSSOP14

C322

0.1U_0402_16V4Z

1

SLP_CHG_M4

LOW

VCC

D+

D-

GND

10

9

S

8

7

6

3

1B

6

2B

8

3B

11

4B

7

0.1U_0402_16V4Z

C316

1 2

USB20_P2_R

USB20_N2_R

USB_CHG_EN#

USB20_P2_S_O
USB20_N2_S_O

R198 100_0402_5%

1 2

SLP_CHG# 31

LOW

HIGH

B

1/19 Change net name SLP_CHG-->SLP_CHG#

USB_CHG_EN#31

USB_CHG_EN#

1/25 U9 pin1 +5VALW-->+5V_ALW for USB charger

+USB_VCCB

12

12

R194

75K_0402_1%

USB20_P2_S_O
USB20_N2_S_OUSB20_P2_R_U

R196

51K_0402_1%

FUNCTIONSLP_CHG

D=1D

D=2D

R195
43K_0402_1%

12

12

R197
51K_0402_1%

/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+5V_ALW

C

10K_0402_5%

SATA_TX3+22
SATA_TX3-22

SATA_RX3-22
SATA_RX3+22

USB20_N2_R_S

2

1

+3VALW

12

R858

Active Low

+USB_VCCB

2A

U9

1
2

4

RT9715BGS_SO8

8

GND

VOUT

7

VOUT

VIN

6

VIN3VOUT

5

FLG

EN

+USB_VCCB

USB20_P2_R_S USB20_N2_R

2008/04/14 2009/04/14

1

C317

@

4.7U_0805_10V4Z

2

D11

4

IO1

VIN

3

GND

IO2

CM1293A-02SR SOT143-4

Compal Secret Data

Deciphered Date

USB_OC#2 21,31

C318 0.01U_0402_25V7K

1 2

C319 0.01U_0402_25V7K

1 2

C320 0.01U_0402_25V7K
C321 0.01U_0402_25V7K

D

USB20_P2_R

12
12

1

+

150U_B2_6.3VM_R45M

C522

2

1/20 update JSATA1 footprint

+USB_VCCB

W=60mils

USB20_N2_R_S
USB20_P2_R_S

SATA_C_TX3+
SATA_C_TX3-

SATA_C_RX3­SATA_C_RX3+

@

R199 0_0402_5%

1 2

L37

1

1

4

4

WCM-2012-900T_0805

R201 0_0402_5%

1 2

@

Title

Size Document Number Rev

Date: Sheet

USB20_P2_R_S

2

2

USB20_N2_R_S

3

3

Compal Electronics, Inc.

JSATA1

1

VBUS

2

D-

3

D+

4

GND

5

GND

6

A+

7

A-

8

GND

9

B-

10

B+

11

GND

12

GND

13

GND

14

GND

15

GND

TAIWI_EU114-117CRL-TW_11P-T

CONN@

SATA HDD/ODD

LA-6032P

0.1U_0402_16V4Z

1

C314

2

USB

ESATA

E

+USB_VCCB

1

C315

2

1000P_0402_50V7K

25 45Tuesday, March 23, 2010

of

1.0Custom

PCIe Mini Card-3G/WWAN (Slot 2)

+3V_WW AN

JWW AN1

+UIM_PWR

CM7

0.1U_0402_16V4Z

+3V_WW AN

+UIM_PWR

1

2

12

DM1

RLZ20A_LL34

10P_0402_50V8J

UIM_RESET
UIM_CLK

CM8

1
3
5
7

9
11
13
15

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
54

1
3
5
7
9
11
13
15

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
G1
G2

P-TWO_A54402-A0G16-N_52P

CONN@

1

2

2
4
6

8
10
12
14
16

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

G3
G4

1

CM9
10P_0402_50V8J

2

2
4
6
8
10
12
14
16

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
55
56

1

2

3

SMB_CK_CLK1
SMB_CK_DAT1

LED_WIMAX#

DM2
DAN217_SC59

@

+UIM_PWR
UIM_DATA
UIM_CLK
UIM_RESET
COMMON

PLT_RST#

USB20_N5 21
USB20_P5 21

3

1

DM3
DAN217_SC59

@

2

3G_OFF# 20

J3G1

1

VCC

2

RST

3

CLK

7

NC

MOLEX_47273-0001~D

CONN@

DAN217_SC59

+3V_WW AN

0.1U_0402_16V4Z

1

CM4

CM5

2

0.01U_0402_25V7K

COMMON UIM_VPP

R203 0_0402_5%

1 2

4

GND

VPP

I/O

NC

UIM_VPP

5
6

8

1

DM4

@

2

3

+UIM_PWR

1

CM6

2

4.7U_0805_10V4Z

+UIM_PWR

12

RM1

4.7K_0402_5%

@

UIM_DATA

1

CM10
22P_0402_50V8J

2

@

+3VS

RM5

@

1

2

1

CM20

1000P_0402_50V7K

2

WW AN_PWR_EN#22

100K_0402_5%

1 2

47K_0402_5%

CM17

0.1U_0402_16V7K @

RM6

1 2

@

+3VS

2

S

1

G

QM1

2

D

AO3413_SOT23

1 3

@

+3V_WW AN

12

RM9
0_0805_5%

WLAN&BT Combo module circuits

BT
on module

BT
on module

Enable Disable

BT_CRTL

BT_PWR#

**If +3V_WLAN is +3VS, please
remove D17.

SUSP#28,31,34,37,41

CH751H-40PT_SOD323-2

BT_PWR#20,29

HI LO

LO HI

@

D17

21

2

G

Q38 2N7002_SOT23-3

BT_CTRLSUSP#

13

D

S

PCIe Mini Card-WLAN(Slot 1)

01/19 Update net name BT_CTRL-->BT_PWR#

CLKREQ_MCARD2#21

CLK_PCIE_MCARD2#20
CLK_PCIE_MCARD220

PCIE_PTX_C_IRX_N211
PCIE_PTX_C_IRX_P211

PCIE_ITX_C_PRX_N211
PCIE_ITX_C_PRX_P211

E51_TXD31
E51_RXD31

BT_CTRL

+3V_WLAN

R205 0_0402_5%

1 2
1 2

R206 0_0402_5%

12

RM4
100K_0402_5%

JWLAN1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND

54

GND

BELLW_80052-1021_52P

CONN@

2
4
6

8
10
12
14
16

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

+3V_WLAN

+1.5V_WLAN

+1.5V_WLAN

0.1U_0402_16V4Z

1

CM11

2

0.01U_0402_25V7K

1

CM12

2

1

CM13

2

4.7U_0805_10V4Z

03/19 del LPC frame and LPC_AD1-LPC_AD3 trace

WL_OFF#
PLT_RST#

SMB_CK_CLK1
SMB_CK_DAT1

LED_WIMAX#

WL_OFF# 31

PLT_RST# 12,15,20,27,30,31,32

SMB_CK_CLK1 21
SMB_CK_DAT1 21

USB20_N8 21
USB20_P8 21

LED_WIMAX# 33

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3V_WLAN

1

CM14

2

0.01U_0402_25V7K

LED_WIMAX#

0.1U_0402_16V4Z

1

CM15

2

2008/09/05 2009/09/05

1

CM16

2

4.7U_0805_10V4Z

+3V_WLAN

12

RM3100K_0402_5%

Compal Secret Data

WLAN_PW R_EN#22

Deciphered Date

01/21 Add D17 and Q38 for BT control

RM7

@

100K_0402_5%

+3VS +3VS

2

CM18

@

1 2

47K_0402_5%

RM8

1 2

@

0.1U_0402_16V7K

WLAN_PW R_EN#_R

0.1U_0402_16V7K

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

PCIe-WLAN/HDDVD/NAND/NEW

Tuesday, March 23, 2010

@

2

CM19

1

LA-6032P

1

G

2

+1.5VS

@

S

G

2

D

1 3

S

QM2

D

AO3413_SOT23

1 3

@

QM3

AO3413_SOT23

12

RM10
0_0805_5%

+3V_WLAN

12

RM11
0_0603_5%

+1.5V_WLAN

of

26 45

1.0

5

4

3

2

1

UL1

22

HSOP

23

HSON

17

HSIP

18

HSIN

16

CLKREQB

25

PERSTB

19

REFCLK_P

20

REFCLK_N

43

CKXTAL1

44

CKXTAL2

28

LANWAKEB

26

ISOLATEB

14

NC/SMBCLK

15

NC/SMBDATA

38

GPO/SMBALERT

33

ENSWREG

34

VDDREG

35

VDDREG

46

RSET

24

GND

49

PGND

RTL8105E-VB-GR_QFN48_6X6

RL8

0_0402_5%

RL9

0_0402_5%@

CL11 0.1U_0402_16V4Z@

LED3/EEDO
LED1/EESK

EECS/SCL

NC/MDIN2

NC/MDIN3

+3V_LAN

+LAN_VDD10

12

Reserved For 1.05V Crystal

LED0

EEDI/SDA

MDIP0
MDIN0
MDIP1
MDIN1

NC/MDIP2

NC/MDIP3

DVDD10
DVDD10
DVDD10

DVDD33
DVDD33

AVDD33
AVDD33
AVDD33
AVDD33

EVDD10

AVDD10
AVDD10
AVDD10
AVDD10

REGOUT

31
37
40

RL2 10K_0402_5%

30

RL1 10K_0402_5%

32

LAN_MDI0+

1

LAN_MDI0-

2

LAN_MDI1+

4

LAN_MDI1-

5
7
8
10
11

13

+LAN_VDD10

29
41

27

+3V_LAN

39

12

+3V_AVDDXTAL

42
47
48

21

+LAN_EVDD10

3

+LAN_VDD10

6
9
45

+LAN_REGOUT

36

12
12

+3V_LAN

ENSWREG

EC_SWI#

RL20 1K_0402_5%@

1 2

RL21 1K_0402_5%@

1 2

RL22 1K_0402_5%

1 2

+LAN_VDDREG

PCIE_PRX_LANTX_P3

PCIE_PRX_LANTX_N3

RL19 0_0402_5%

LAN_X1

LAN_X2

ISOLATEB

ENSWREG

1 2

RL5 2.49K_0402_1%

+3V_AVDDXTAL

CL1 0.1U_0402_16V7K

PCIE_PTX_C_IRX_P311

PCIE_PTX_C_IRX_N311

D D

+3VS

C C

B B

RL6

1K_0402_1%

RL7

15K_0402_5%

12

ISOLATEB

CL26

27P_0402_50V8J

25MHZ_20PF_7A25000012

1

2

1 2

CL2 0.1U_0402_16V7K

1 2

PCIE_ITX_C_PRX_P311
PCIE_ITX_C_PRX_N311

CLKREQ_LAN21

PLT_RST#12,15,20,26,30,31,32

CLK_PCIE_LAN20
CLK_PCIE_LAN#20

EC_SWI#21

+3V_LAN

YL1

LAN_X2LAN_X1

12

CL27

1

2

27P_0402_50V8J

3/10 Change CL13 0805-->0603

+LAN_REGOUT

2.2UH +-5% NLC252018T

Layout Note: LL1 must be
within 200mil to Pin36
CL8,CL9 must be within
200mil to LL1
+LAN_REGOUT: Width =60mil

+LAN_VDD10

+3V_LAN

+3V_LAN

RL4
0_0402_5%

RL23
0_0402_5%

@

Can change to 2.2uH&4.7uF

LL1

1 2

CL13

4.7U_0603_6.3V6K

12

LL20_0603_5%

1U_0402_6.3V4Z

CL18

1

2

Close to Pin 21

12

LL30_0603_5%

4.7U_0603_6.3V6K

CL28

1

2

1

2

+LAN_EVDD10

2

CL17

0.1U_0402_16V4Z

1

+LAN_VDDREG

2

0.1U_0402_16V4Z

1

+LAN_VDD10

2

CL9

0.1U_0402_16V4Z

1

CL29

WOL_EN#31

Close to Pin 27,39,12,47,48

Close to Pin 3,6,9,13,29,41,45

+3VALW TO +3V_LAN

+3VALW

RL25

100K_0402_5%

0.1U_0402_16V7K

1 2

RL16 47K_0402_5%

0.01U_0402_25V7K

Vgs=-4.5V,Id=3A,Rds<97mohm

CL12

1 2

CL14

4.7U_0805_10V4Z

2

QL1

G

1

2

1

AO3413_SOT23

2

CL15

@

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

+3VALW

S

D

1 3

1

CL8 1U_0402_6.3V4Z

2

CL100.1U_0402_16V 4Z

CL40.1U_0402_16V4Z

CL50.1U_0402_16V4Z

CL60.1U_0402_16V4Z

CL70.1U_0402_16V4Z

+LAN_VDD10

CL190.1U_0402_16V4Z

CL200.1U_0402_16V4Z

CL210.1U_0402_16V4Z

CL220.1U_0402_16V4Z

1

1

2

2

1

2

+3V_LAN

PJ20
JUMP_43X39

@

+3V_LAN

LAN_MDI1+

12

CL30 0.01U_0402_16V7K

A A

5

LAN_MDI1-

LAN_MDI0+
LAN_MDI0-

4

UL2

1

TD+

2

TD-

3

CT

4

NC

5

NC

6

CT

7

RD+
RD-8RX-

NS681680

RX+

RJ45_MIDI1+

16

TX+

TX-

CT
NC
NC

CT

RJ45_MIDI1-

15
14
13
12
11
10
9

CL31 1000P_0402_50V7K

CL32 1000P_0402_50V7K

RJ45_MIDI0+
RJ45_MIDI0-

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2
1 2

RJ45_MIDI1+ 17
RJ45_MIDI1- 17

RJ45_MIDI0+ 17
RJ45_MIDI0- 17

3

1 2
1 2

2008/10/06

RL26
75_0402_1%

75_0402_1%
RL27

Compal Secret Data

RJ45_GND

Deciphered Date

RJ45_GND 17

2009/10/06

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

RTL8103EL/RTL8111DL

LA-6032P

Tuesday, March 23, 2010

1

of

27 45

1.0

A

RA1

+3VS

FBMH1608HM601-T_0603~D

1 1

place close to chip

Ext. Mic

+MIC1_VREFO_R

+MIC1_VREFO_L

Digital Mic

2 2

EC_MUTE#31

12

CA2

CA8

RA22 2.2K_0402_5%

1 2

MIC1_R29

MIC1_L29

1 2

MIC1_R

MIC1_R_L

MIC1_R_R

RA23 1K_0402_5%

RA24 1K_0402_5%

RA252.2K_0402_5%

12/18 RA26 0ohm-->Bead for EMI request

INT_MIC_DATA18

INT_MIC_CLK18

4.7K_0402_5%

RA45

RA26

FBMA-L10-160808-301LMT 0603

12

AZ_RST_HD#21

CA12 100P_0402_50V8J

3/17 Add RA45

03/17 DGND-->AGND forAudio noise

+3VS

@

12

RA27

4.7K_0402_5%

AZ_RST_HD#

3 3

4 4

2

CA62

0.1U_0402_16V7K

1

@

CA47 0.1U_0603_50V7K

1 2

CA48 0.1U_0603_50V7K

1 2

CA49 0.1U_0603_50V7K

1 2

CA50 0.1U_0603_50V7K

1 2

RA18

1 2

FBMH1608HM601-T_0603~D

+MIC1_VREFO_L

1

10U_0805_10V4Z

2

1

10U_0805_10V4Z

2

1 2

1 2

1 2

1 2

0.1U_0402_16V4Z

1

CA1

2

0.1U_0402_16V4Z

1

CA7

2

MIC1_R_R

MIC1_R_LMIC1_L

CA214.7U_0805_10V4Z

12

12

CA224.7U_0805_10V4Z

INT_MIC_CLK_R

EC_MUTE#

AZ_RST_HD#

MONO_IN

SENSE_A

1 2

CA15

2.2U_0603_6.3V4Z

DGND

+3VS_DVDD

23
24

14
15

21
22

16
17

2

3

4

11

12

13

18

36

35

31

43
42
49

7

9

1

DVDD

DVDD_IO

LINE1_L
LINE1_R

LINE2_L
LINE2_R

MIC1_L
MIC1_R

MIC2_L
MIC2_R

GPIO0/DMIC_D ATA

GPIO1/DMIC_C LK

PD#

RESET#

PCBEEP

SENSE A

SENSE B

CBP

CBN

MIC1_VREFO_L

PVSS2
PVSS1
DVSS2
DVSS1

B

+PVDD1

2

JA1

@

+PVDD2

+AVDD

46

AVDD125AVDD2

SPK_OUT_L+

SPK_OUT_L-

SPK_OUT_R+

SPK_OUT_R-

HP_OUT_L

HP_OUT_R

SYNC

BCLK

SDATA_OUT

SDATA_IN

EAPD

SPDIFO

MONO_OUT

MIC2_VREFO

LDO_CAP

VREF

JDREF

CPVEE

AVSS1
AVSS2

2

1

1

38

UA1

40
41

45
44

32
33

10

6

5

8

47

48

20

29

30
28

27

19

34

26
37

CA63

1 2

22P_0402_50V8J

JUMP_43X39

PVDD139PVDD2

MIC1_VREFO_R

ALC259-VB5-GR_QFN48_7X7

INT_MIC_CLK_R

3/17 Del R861 R910

0.1U_0402_16V4Z

CA57

1

2

10U_0805_10V4Z

1

CA56

2

place close to chip

0.1U_0402_16V4Z

CA61

CA3

10U_0805_10V4Z

AZ_SDIN0_HD_R

AC_VREF

AC_JDREF

CA14 2.2U_0603_6.3V4Z

1

1

@

2

2

10U_0805_10V4Z

10U_0805_10V4Z

1

1

CA4

CA5

2

2

0.1U_0402_16V4Z

RA6 33_0402_5%

RA9 20K_0402_1%

1 2

CA60

+MIC1_VREFO_R

12

AGND

RA2

12

0_0603_5%

RA11

@

12

0_0603_5%

0.1U_0402_16V4Z

1

1

CA6

2

2

SPKL+ 29
SPKL- 29

SPKR+ 29
SPKR- 29

12

CA17

0.1U_0402_16V4Z

place close to chip

C

0.1U_0402_16V4Z

CA44

0.1U_0402_16V4Z

CA59

@

0_0603_5%

1

1

2

2

10U_0805_10V4Z

1

1

@

2

2

10U_0805_10V4Z

RA3

12

+5VS

CA43

+5VS

CA58

+5VS

place close to chip

HP_L 29
HP_R 29

AZ_SYNC_HD 21

AZ_BITCLK_HD 21

AZ_SDOUT_HD 21

AZ_SDIN0_HD 21

CA23 10U _0805_10V4Z

1 2

1

2

@

1

CA16
10U_0805_10V4Z

2

Ext. HP

Sense Pin Impedance

SENSE A

place close to chip

MIC_SENSE29

NBA_PLUG29

Beep sound

EC Beep

EC_BEEP31

PCI Beep

PCH_SPKR21

03/12 CA15 SMT-->@ for Audio noise

1/21 UA2 pin5 +PVDD1--->+AVDD

W=40Mil

CA67

@

1 2

0.1U_0402_16V4Z

SUSP#26,31,34,37,41

1 2

0_0402_5%

RA28

@

D

Codec Signals

39.2K

20K

10K

5.1K

39.2K

20K

10K

RA10 20K_0402_1%

RA21 39.2K_0402_1%

PORT-I (PIN 32, 33)

PORT-B (PIN 21, 22)

PORT-C (PIN 23, 24)

PORT-D (PIN 48)

PORT-E (PIN 14, 15)

PORT-F (PIN 16, 17)SENSE B

PORT-H (PIN 20)

SENSE_A

12

RA7

1 2

47K_0402_5%

12

CA13

1 2

0.1U_0402_16V4Z

1

CA18

0.1U_0402_16V4Z

2

RA8

1 2

47K_0402_5%

10K_0402_5%

RA12

03/17 DGND-->AGND for Audio noise

(4.75V(4.56~4.94V))

300mA

+5VALW +AVDD

CA700.1U_0402_16V4Z

@

1

2

UA2

@

1

IN

OUT

2

GND

3

SHDN

BYP

G9191-475T1U_SOT23-5

5

4

@

1

CA69

@

0.1U_0402_16V4Z

2

Headphone out

Ext. MIC

MONO_IN

2.2U_0805_16V4Z

1

CA68

2

E

Function

/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

D

Date: Sheet

Compal Electronics, Inc.

HD Audio ALC272 Codec

LA-6032P

28 45Tuesday, March 23, 2010

E

of

1.0Custom

A

B

C

D

E

USB+Audio FFC conn
Pin=20pin, pitch=0.5

+USB_VCCA

1 1

USB20_P121

USB20_N121

USB20_P021

USB20_N021

NBA_PLUG28
MIC_SENSE28

HP_R28

HP_L28
MIC1_R28
MIC1_L28

2 2

4.7U_0805_10V4Z

3 3

1U_0402_6.3V4Z

USB20_P1
USB20_N1

USB20_P0
USB20_N0

HP_R
HP_L
MIC1_R
MIC1_L

JST_SM06B-XSRK-ETB(HF)

+5VALW

1

C636

2

FD1

@

1

JP6

1

1

2

2

3

3

4

4

5

5

6

6

7

GND

8

GND

CONN@

USB_EN#31 USB_OC#0 21,31

FD3

FD2

@

@

1

1

100K_0402_5%

FD4

@

1

10
11
12
13
14
15
16
17
18
19
20
21
22

MIC1_R
HP_L
HP_R

USB_EN#

Screw Hole

H3

H15

H_2P3

1

@

+5VS +5VS +5VS +5VS +5VS+5VS

+5VS

1

C708

1

2

2

+3VS

1

2

H8

H_2P8

1

@

@

C642

0.1U_0402_16V4Z

C646

0.1U_0402_16V4Z

1

H_2P3

@

1

2

C643

0.1U_0402_16V4Z

02/04 Update JP5 pin define

JP5

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9
10
11
12
13
14
15
16
17
18
19
20
GND
GND

ACES_87151-2005N

CONN@

+5VALW

12

R907

H4

H5

H_4P0

1

@

H12

H10

H_2P3

1

@

1

C644

0.1U_0402_16V4Z

2

1/27 Add R907 for USB_EN# PH

U48

1

H_4P0

@

1

GND

2

IN

3

IN

4

EN#

APL3510BXI-TRG MSOP 8

H6

H_4P0

1

@

8

OUT

7

OUT

6

OUT

5

OC#

H7

H_4P0

1

@

CPU

H18

H16

H_2P3

1

@

C645

0.1U_0402_16V4Z

H_2P3

1

@

1

2

1

H_2P3

@

H13

H_2P3

1

@

1

2

+USB_VCCA

1/27 Update P/N

H17

H2

H_2P1N

1

@

C647

0.1U_0402_16V4Z

H_2P6X2P1N

1

@

1

C648

0.1U_0402_16V4Z

2

+3VALW

10K_0402_5%

R857

H19

1

H_5P0N

@

Speaker Connector

SPKL+28

SPKL-28

SPKR+28

SPKR-28

12

DA4

placement near Audio Codec

FBMA-L11-160808-800LMT_0603

SPKL+

LA2

1 2

SPKL-

LA3

1 2

FBMA-L11-160808-800LMT_0603

FBMA-L11-160808-800LMT_0603

SPKR+

LA4

1 2

SPKR-

LA5

1 2

FBMA-L11-160808-800LMT_0603

CA19

CA20

CA25

CA26

1

10U_0805_10V4Z@

2

1

10U_0805_10V4Z@

2

1

10U_0805_10V4Z@

2

1

10U_0805_10V4Z@

2

SPK_L1

2

CA24
1U_0402_6.3V4Z

@

1

SPK_L2

SPK_R1

2

CA27
1U_0402_6.3V4Z

@

1

SPK_R2MIC1_L

PACDN042Y3R_SOT23-3

3

1

2

SPK_R1
SPK_R2
SPK_L1
SPK_L2

DA5

3

1

2

PACDN042Y3R_SOT23-3

JSPK1

1

1

2

2

3

3

4

4

5

GND1

6

GND2

ACES_88231-04001

CONN@

BlueTooth Interface

+3VS

R211

100K_0402_5%

BT_PWR#20,26

1 2

47K_0402_5%

0.1U_0402_16V7K

R212

1 2

<>

0.01U_0402_25V7K

C326

C327

(MAX=200mA)

+BT_VCC

1

C329

4.7U_0805_10V4Z

BT_RST#20

1 2

R214 0_0402_5%

0.1U_0402_16V4Z

C328

2

USB20_P621
USB20_N621

BT_DET#20

C330

0.1U_0402_16V4Z

1 2

R213 0_0402_5%

+3VS

S

Q17

D

AO3413_SOT23

1 3

C325

0.1U_0402_16V4Z

+BT_VCC

JBT1

1

1

2

2

3

3

4

4

5

7

5

G1

6

8

6

G2

ACES_87213-0600G

CONN@

2

1

G

2

2

1

4 4

5

3

4

Q15B
2N7002DW-T/R7_SOT363-6

A

B

/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

AMP/Audio Jack/HP/SPEAKER/VR

LA-6032P

29 45Tuesday, March 23, 2010

E

of

1.0Custom

A

1 1

CLK_PCIE_MCARD0#20
CLK_PCIE_MCARD020

PCIE_ITX_C_PRX_N111
PCIE_ITX_C_PRX_P111

CC8 0.1U_0402_16V7K

PCIE_PTX_C_IRX_N111
PCIE_PTX_C_IRX_P111

1 2

CC9 0.1U_0402_16V7K

1 2

RC2

JMB385@

9.1K_0402_1%

CLK_PCIE_MCARD0#
CLK_PCIE_MCARD0

PCIE_ITX_C_PRX_N1
PCIE_ITX_C_PRX_P1

PCIE_PTX_IRX_N1
PCIE_PTX_IRX_P1

RC2 12K _0402_1%

JMB389@

12

SEL43

12mil

3/17 JMB385 co-lay

RC3

PLT_RST#12,15,20,26,27,31,32

2 2

3/23 JMB385 co-lay

+3VS

JMB385@

1 2

RC22 4.7K_0402_5%

JMB385@

1 2

RC23 4.7K_0402_5%

JMB385@

1 2

RC24 4.7K_0402_5%

3/17 JMB385 co-lay

3 3

XDWP#_SDW P#

XD_RB#

SDCMD_MSBS_XDWE#

3/17 JMB385 co-lay

SD_CD#

1

CC15

CC14

@

2

4 4

0.1U_0402_16V4Z

1 2

100_0402_5%

JMB389@

RC3

JMB385@

0_0402_5%

SD_CD#

MS_CD#

XD_CD#

12

RC20 10K_0402_5%

12

RC9 1K_0402_5%

RC21 10K_0402_5%

1

2

12

JMB385@

XD_CD#

@

0.1U_0402_16V4Z

A

1

2

CR_LED#33

+VCC_OUT

CC130.1U_0402_16V4Z

JMB389@

CPPE#
XD_CD#

MS_CD#
SD_CD#

40 mils

+VCC_OUT

CR_LED#

UC1
JMB385-QGAZ0C QFN 48P

3/23 JMB385 co-lay

SDCLK_MSCLK_XDCE#

+VCC_OUT

CC17

10U_0805_10V6K

1

2

Power Circuit

UC1

3

APCLKN

4

APCLKP

9

APRXN

8

APRXP

11

APTXN

12

APTXP

7

APREXT

43

SDDV/MDIO4

39

TXIN/NC

JMB389

1

XRSTN

2

XTEST

13

CPPE_N

14

CR1_CD2N

15

CR1_CD1N

16

CR1_CD0N

17

CR1_PCTLN

21

CR1_LEDN

JMB389-QGAZ0C_QFN48_7X7

JMB389@

JMB385@

3/18 22U change to 10U

1

CC18

SD_CLK

2

SDCMD_MSBS_XDWE#

XDWP#_SDW P#
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2

0.1U_0402_16V4Z

XD_SD_MS_D3
XD_SD_MMC_D4
XD_SD_MMC_D5
XD_SD_MMC_D6
XD_SD_MMC_D7

XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
MS_CLK
MS_CD#
SDCMD_MSBS_XDWE#

B

APVDD

APV18

NC/TAV33

DV33
DV33
DV33
DV18
DV18

MDIO0
MDIO1
MDIO2
MDIO3

MDIO6/4

MDIO5

G/MDIO6

MDIO7
MDIO8

MDIO9
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14

NC/SPI_SCK
NC/SPI_CSN

NC/SPI_SO

NC/SPI_SI

APGND
NC/GND
NC/GND
NC/GND

GND

place 6 GND vias

RC11 0_0402_5%

1 2

RC12 0_0402_5%

1 2

RC13 0_0402_5%

1 2

3/19 remove 22P_0402

JREAD1

13
22
43

10
19

1
2
4

3
25
23
21
17

8

5

12
11
14
18
20
16

9

TAITW_R013-P12-H M_44P_NR-T

CONN@

B

C

+1.8VS_OUT

20mil

5
10
36

19
20
44
18
37

48
47
46
45
41
42
24
40
29
28
27
26
25
23
22

30
33
34
35

6
31
32
38

49

SD_VCC
MS_VCC
XD_VCC

SD_CLK
SD_CMD
SD_CD
SD_WP
SD/MMC_DAT0
SD/MMC_DAT1
SD/MMC_DAT2
SD/MMC_DAT3
MMC_DATA4
MMC_DATA5
MMC_DATA6
MMC_DATA7

MS_DATA0
MS_DATA1
MS_DATA2
MS_DATA3
MS_SCLK
MS_INS
MS_BS

place near pin 5

1

CC1

2

10U_0603_6.3V6M

+TVA33

RC125

40mil

20mil

XD_SD_MS_D0

XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
SEL41
SDCLK_MSCLK_XDCE#
SEL24
XD_CLE
XD_SD_MMC_D4
XD_SD_MMC_D5
XD_SD_MMC_D6
XD_SD_MMC_D7
XD_RE#
XD_RB#
XD_ALE

SEL33

SD_GND

SD_GND
MS_GND
MS_GND

XD_GND

XD_GND

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CC2

1 2

0_0402_5%

SD_CLK

MS_CLK

XD_CE#

XD_D0
XD_D1
XD_D2
XD_D3
XD_D4
XD_D5
XD_D6
XD_D7

XD_CD

XD_R/B

XD_RE

XD_CE
XD_CLE
XD_ALE

XD_WE
XD_WP

GND
GND

JMB389@

1

1

CC3

2

2

1000P_0402_50V7K

0.22U_0402_6.3V6K

+3VS

place near pin 19,20 and 44.

CC5 0.1U_0402_16V4Z

1 2

CC6 0.1U_0402_16V4Z

1 2

CC7 0.1U_0402_16V4Z

1 2

+1.8VS_OUT

2

CC10

CC11

1

0.22U_0402_6.3V6K

place near pin37

XD_SD_MS_D0

35

XD_SD_MS_D1

36

XD_SD_MS_D2

37

XD_SD_MS_D3

38

XD_SD_MMC_D4

39

XD_SD_MMC_D5

40

XD_SD_MMC_D6

41

XD_SD_MMC_D7SD_CD#

42

XD_CD#

26

XD_RB#

27

XD_RE#

28

XD_CE#

29

XD_CLE

30

XD_ALE

31

SDCMD_MSBS_XDWE#

32

XDWP#_SDW P#

33

7
15
6
24
34
44
45
46

2010/01/22 2011/01/22

CC4

1

2

1

2

10U_0603_6.3V6M

place near pin 10

0.1U_0402_16V4Z

+TVA33

2

CC16

JMB389@

0.1U_0402_16V4Z

1

place near pin 36

place near pin18

SD_CLK

MS_CLK

XD_CE#

@
1 2

100_0402_5%

@
1 2

100_0402_5%

@
1 2

100_0402_5%

RC15

RC16

CC19

@

1 2

100P_0402_50V8J

CC20

@

1 2

100P_0402_50V8J

CC21

@

1 2

100P_0402_50V8J

RC14

For EMI close to JREAD

Compal Secret Data

Deciphered Date

C

CR_CPPE#_SB21

CR_CPPE#_EC31

RC128

D

12

RC124

@

10K_0402_5%

QC1

1 3

2N7002_SOT23-3

1 2

RC126 0_0402_5%@

DC1

RC127

1 2

+3VALW

12

2

G

10K_0402_5%

D

S

CH751H-40PT_SOD323-2

21

0_0402_5%@

D3E suport

3/22 co-lay 0 ohm

R922 0_0402_5%

1 2

R921 0_0402_5%

1 2

@

3/19 co-lay 0 ohm

CR_WAKE#22

Strapping setting

Pin name

MDIO14

MDIO14

MDIO7

MDIO14

on board

CR_LED
high active

XD_CLE

XD_ALE

Description

High

Ϫ

1 2

RC19 10K_0402_5%

RC17 10K_0402_5%

RC5 200K_0402_5%

3/18 10K change to 200K

1 2

1 2

@

low

add-in card

CR_LED
low active

+3VS

Place RC5, RC17, RC19 close to pin42

3/17 JMB385 co-lay

SEL33

SEL24

SEL41

SEL43

RC25 0_0402_5%

1 2

JMB385@

RC26 0_0402_5%

1 2

JMB385@

RC27 0_0402_5%

1 2

JMB389@

RC28 0_0402_5%

1 2

JMB385@

RC29 0_0402_5%

1 2

JMB389@

RC30 0_0402_5%

1 2

JMB385@

CC12

JMB389@

CC12 close to pin43
For internal LDO in SD3.0

Title

Size Document Number Rev

Custom

Date: Sh eet

12

2.2U_0603_6.3V6K

Compal Electronics, Inc.

Card Reader JMB389

D

SDCMD_MSBS_XDWE#

SD_CD#

XDWP#_SDW P#

of

30 45Tuesday, March 23, 2010

CPPE#

Ϫ

0.1

A

B

C

D

E

+3VL_EC

KSI[0..7]32

KSO[0..17]32

1 1

2 2

EC_SMB_DA2

EC_SMB_CK2

EC_SMB_DA1

EC_SMB_CK1

TP_CLK

TP_DATA

SYSON

SUSP#

LID_SW#

ON/OFFBTN#

3 3

KSO1

KSO2

ACIN_D

4 4

R231 2.2K_0402_5%

R229 2.2K_0402_5%

R228 2.2K_0402_5%

R227 2.2K_0402_5%

R225 4.7K_0402_5%

1 2

R226 4.7K_0402_5%

1 2

R224 10K_0402_5%

1 2

R223 10K_0402_5%

1 2

R238 100K_0402_5%

R232 100K_0402_5%

R234 47K_0402_5%

R235 47K_0402_5%

E51_TXD PL on Page 26

R775 100K_0402_5%

1 2

C641 0.1U_0402_16V4Z

1 2

R233 150K_0402_5%

2 1

CH751H-40PT_SOD323-2

C339 100P_0402_50V8J

KSI[0..7]

KSO[0..17]

EC_INVT_PWM

1 2

12

R240
20M_0402_5%

@

GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

CLK_PCI_EC
PLT_RST#
ECRST#
EC_SCI#
WL_BT_LED#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

EC_SMB_CK1

EC_SMB_CK2
EC_SMB_DA2

PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
ADAPTOR_SEL

FAN_SPEED1
HDPLOCK
E51_TXD
E51_RXD
ON/OFFBTN#
PWR_SUSP_LED#
NUM_LED#

@

CRY2

GATEA2021
KB_RST#21

SERIRQ20,32

LPC_FRAME#20,32

LPC_AD320,32
LPC_AD220,32
LPC_AD120,32

CR_CPPE#_EC30

EC_INVT_PWM18

FAN_SPEED15

ON/OFFBTN#33

PWR_SUSP_LED#33

15P_0402_50V8J

OSC

OSC

LPC_AD020,32

CLK_PCI_EC20,24

PLT_RST#12,15,20,26,27,30,32

EC_SCI#21

WL_BT_LED#33

EC_SMB_CK136
EC_SMB_DA136
EC_SMB_CK27,32
EC_SMB_DA27,32

PM_SLP_S3#21
PM_SLP_S5#21

EC_SMI#21

HDPLOCK32
E51_TXD26
E51_RXD26

NUM_LED#32

R923 0_0402_5%

C342

12

1

4

12

C343

15P_0402_50V8J

B

+3VL

R236

1 2

47K_0402_5%

C337

12

0.1U_0402_16V4Z

12

12

12

12

+3VS

+3VL

+5VS

1/27 +3VALW-->+3V_ALW

12

+3V_ALW

3/22 Add CPPE to KBC

12

12

12

@

12

D12

12

A

+3VL

G-Sensor

PLT_RST#

3/22 Add CPPE to KBC

+3VL

ACIN 22,33,35

+3VL

12

R909

@

100K_0402_5%

ADAPTOR_SEL

12

R910
100K_0402_5%

RTCCLK20

Y4

2

NC

3

NC

32.768KHZ_12.5PF_Q13MC14610002

L38

0_0603_5%

U12

1

GA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

10

LAD0

12

PCICLK

13

PCIRST#/GPIO05

37

ECRST#

20

SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

SCL1/GPIO44

78

SDA1/GPIO45

79

SCL2/GPIO46

80

SDA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO0 8

16

LID_SW# /GPIO0A

17

SUSP#/GPIO0B

18

PBTN_OUT#/GPIO0C

19

EC_PME#/GP IO0D

25

EC_THERM#/GPIO11

28

FAN_SPEED1/FANFB1/GPIO14

29

FANFB2/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

ON_OFF/GPIO18

34

PWR_LE D#/GPIO19

36

NUMLED#/GPIO1A

CRY1

122

XCLK1

123

XCLK0

+EC_AVCC

12

LPC & MISC

Int. K/B
Matrix

SM Bus

+3VL_EC

12

L39
0_0603_5%

1 2

C341 0.1U_0402_16V4Z

/

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+EC_AVCC+3VL +3VL_EC

9

22

33

96

111

125

VCC

VCC

VCC

VCC

VCC

VCC

PWM Output

AD Input

DA Output

PS2 Interface

SPI Device Interface

SPI Flash ROM

GPIO

GPO

GPIO

GPI

GND

GND

GND

GND

GND

11

24

35

94

113

Issued Date

67

AVCC

INVT_PW M/PWM1/GPIO0F

BEEP#/PWM2/GPIO10

FANPWM1/GPIO12

ACOFF/FANPWM2/GPIO13

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD3/GPIO3B

AD4/GPIO42

SELIO2#/AD5/GP IO43

DAC_BRIG/D A0/GPIO3C

EN_DFAN1/DA1/GPIO3D

IREF/DA2/GPIO3 E

DA3/GPIO3F

PSCLK1/GPIO4 A
PSDAT1/GPIO4B
PSCLK2/GPIO4 C

PSDAT2/GPIO4D

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

SDICS#/GPXOA00
SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

SPICS#

CIR_RX/GPIO40

CIR_RLC_TX/GPIO41

FSTCHG/SEL IO#/GPIO50

BATT_CHGI_ LED#/GPIO52

CAPS_LED#/GPIO53

BATT_LOW_LED#/GPIO54

SUSP_LED#/GPIO55

SYSON/GPIO56

VR_ON/XCLK32K/GPIO57

AC_IN/GPIO59

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04

EC_ON/GPXO05

EC_SWI#/GPXO06

ICH_PWROK/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

GPXO10
GPXO11

PM_SLP_S4#/GPXID1

ENBKL/GPXID2

GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

V18R

AGND

KB926QFE0_LQFP128_14X14

69

ECAGND

L40

0_0603_5%

2008/04/14 2009/04/14

C

21

EC_BEEP

23
26

ACOFF

27

BATT_TEMPA

63
64
65

ADP_V

66
75

HDPACT

76

68

EN_DFAN1

70

IREF

71

CHGVADJ

72

EC_MUTE#

83

USB_EN#

84

USB_CHG_EN#

85

HDPINT

86

TP_CLK

87

TP_DATA

88

VGATE

97

WOL_EN#

98

VLDT_EN

99

LID_SW#

109

EC_SI_SPI_SO

119

EC_SO_SPI_SI

120

SPI_CLK

126

SPI_CS#

128

73

SLP_CHG_M4_EC

74

FSTCHG

89

BATT_FULL_LED#

90

CAPS_LED#

91

BATT_LOW_LED#

92

PWR_ON_LED#EC_SMB_DA1

93

SYSON

95

VR_ON

121

ACIN_D

127

EC_RSMRST#

100

EC_LID_OUT#

101

EC_ON

102

SLP_CHG_M3_EC

103

SB_PWRGD

104

BKOFF#

105

WL_OFF#

106

CURS_LED#

107

EC_SEL

108

110

UMA_ENBKL

112

USB_OC#2

114

SLP_CHG#

115

SUSP#

116

PBTN_OUT#

117

USB_OC#0

118

124

12

12

C340 4.7U_0805_10V4Z

PCH_OFF 34

EC_BEEP 28

ACOFF 37

BATT_TEMPA 36

ADP_V 37

HDPACT 32

EN_DFAN1 5
IREF 37
CHGVADJ 37

EC_MUTE# 28
USB_EN# 29

USB_CHG_EN# 25

HDPINT 32
TP_CLK 33
TP_DATA 33

VGATE 34,42

WOL_EN# 27
VLDT_EN 34,39

LID_SW# 33

EC_SI_SPI_SO 32
EC_SO_SPI_SI 32
SPI_CLK 32
SPI_CS# 32

R773 10K_0402_5%

1 2

R867 0_0402_5%@

1 2

FSTCHG 37

BATT_FULL_LED# 33
CAPS_LED# 32

BATT_LOW_LED# 33

PWR_ON_LED# 33
SYSON 34,40

EC_RSMRST# 21

EC_LID_OUT# 21
EC_ON 33,34

R868 0_0402_5%

1 2

SB_PWRGD 21

BKOFF# 18

WL_OFF# 26
CURS_LED# 32

UMA_ENBKL 12
USB_OC#2 21,25
SLP_CHG# 25

SUSP# 26,28,34,37,41
PBTN_OUT# 21

USB_OC#0 21,29

C336 0.01U_0402_25V7K

R230 10K_0402_5%

Compal Secret Data

Deciphered Date

D

0.1U_0402_16V4Z

1

C331

2

0.1U_0402_16V4Z

1/25 Add net PCH_OFF

1 2

1 2

1 2

G-Sensor

12/18 Add EC_MUTE#

USB Charger

G-Sensor

WOL_EN#

+5VL

SLP_CHG_M4

VR_ON 34,42

12

@

SLP_CHG_M3

CURS_LED#

EC_SEL

1

C332

2

1/19 Change net name SLP_CHG-->SLP_CHG#

0.1U_0402_16V4Z

1

1

C333

2

2

1000P_0402_50V7K

ECAGND

R323
100K_0402_5%

C469 0.22U_0603_16V4Z

SLP_CHG_M4 22,25

C334

1000P_0402_50V7K

1

C335

2

ADP_I 37

1/21 Add SLP_CHG_M4

Add PWR_ON_LED#

SLP_CHG_M3 22,25

SLP_CHG#

+3VL

12

R785

@

100K_0402_5%

12

R786
100K_0402_5%

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

1/21 Add SLP_CHG_M3

1 2

R862 100K_0402_5%

EC_SEL EC_VERSION

HIGH

LOW

ENE KB926C

LA-6032P

E

+3VALW

KB926D3

KB926E0

31 45Tuesday, March 23, 2010

of

1.0Custom

A

Option 1:SPI Flash (2MB*1) for EC
Option 2:SPI Flash (256KB*1) for EC

SPI Flash (2MB*1) for SB (set up strap pin)

SPI Socket: SP07000F500 & SP07000H900
2MB P/N:MXIC SA00002TO00 S IC FL 16M MX25L1605DM2I-12G SOP 8P ROM

1 1

256KB P/N:MXIC SA00003GK00 S IC FL 2M MX25L2005CMI-12G SOP 8P

+3VL

C345

0.1U_0402_16V4Z

20mil

1

2

SPI_CS#31

SPI_CLK31

EC_SO_SPI_SI31

SPI_CLK

SPI_CS#

SPI_CLK

EC_SO_SPI_SI EC_SI_SPI_SO

8

3

7

1

6

5

MX25L2005CMI-12G SO8

1 2

R788 100_0402_5%

12/18 <BOM>R788 @-->100ohm and C634 @-->100P for RF request

2 2

LPC Debug Port

(Please place the PAD under DDR DIMM)

+3VS

H1

1/27 Del R246

LPC_AD3

LPC_AD1

LPC_FRAME#

7

8

9

10

DEBUG_PAD

SERIRQ20,31

LPC_AD320,31

LPC_AD120,31

LPC_FRAME#20,31

12/31 SMT memo control

U13

VCC

W

HOLD

S

C

D

4

VSS

2

Q

C634 100P_0402_50V8J

1 2

@

56

4

3

2

1

PLT_RST#

LPC_AD2

LPC_AD0

@

@

1 2

2

1

B

12/31 SMT memo control

EC_SI_SPI_SO 31

PLT_RST# 12,15,20,26,27,30,31

LPC_AD2 20,31

LPC_AD0 20,31

LPC_CLK1 20,24

R248
22_0402_5%

C371

22P_0402_50V8J

C

11.6 KEYBOARD CONN.

JKB2

34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

ACES_88170-3400

CONN@

+3VS_MUM

+3VS_CURS

KSO2
KSO1
KSO0
KSO4
KSO3
KSO5

KSO14

KSO6
KSO7

KSO13

KSO8

KSO9
KSO10
KSO11
KSO12
KSO15

KSI7

KSI2

KSI3

KSI4

9

KSI0

8

KSI5

7

KSI6

6

KSI1

5

+3VS_CAPS

4

CAPS_LED#

3

CURS_LED# NUM_LED#

2

NUM_LED#

1

New keyboard

D

KSI[0..7]

KSO[0..17]

KSI[0..7] 3 1

KSO[0..17] 31

13.3 KEYBOARD CONN.

JKB1

34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

ACES_88170-3400

CONN@

+3VS_MUM

R247 300_0402_5%

+3VS_CURS

KSO2

R344 300_0402_5%

KSO1
KSO0
KSO4
KSO3
KSO5

KSO14

KSO6
KSO7

KSO13

KSO8
KSO9

KSO10
KSO11
KSO12
KSO15

KSI7
KSI2
KSI3
KSI4

9

KSI0

8

KSI5

7

KSI6

6

KSI1

5

+3VS_CAPS

4
3
2
1

R245 300_0402_5%

CAPS_LED#
CURS_LED#

10/10 New CURS_LED## for 11.3&13.6

10/10 New CURS_LED# cap for 11.3&13.6

12

12

12

CAPS_LED# 31
CURS_LED# 31
NUM_LED# 31

+3VS

+3VS

+3VS

KSO16

KSO17

KSO2

KSO1

KSO0

KSO4

KSO3

KSO5

KSO14

KSO6

KSO7

KSO13

KSO8

KSO9

KSO10

KSO11

KSO12

KSO15

KSI7

KSI2

KSI3

KSI4

KSI0

KSI5

KSI6

KSI1

CAPS_LED#

NUM_LED#

CURS_LED#

E

1 2

C344 100P_0402_50V8J

1 2

C346 100P_0402_50V8J

1 2

C347 100P_0402_50V8J

1 2

C348 100P_0402_50V8J

1 2

C349 100P_0402_50V8J

1 2

C350 100P_0402_50V8J

1 2

C351 100P_0402_50V8J

1 2

C352 100P_0402_50V8J

1 2

C353 100P_0402_50V8J

1 2

C354 100P_0402_50V8J

1 2

C355 100P_0402_50V8J

1 2

C356 100P_0402_50V8J

1 2

C357 100P_0402_50V8J

1 2

C358 100P_0402_50V8J

1 2

C359 100P_0402_50V8J

1 2

C360 100P_0402_50V8J

1 2

C361 100P_0402_50V8J

1 2

C362 100P_0402_50V8J

1 2

C363 100P_0402_50V8J

1 2

C364 100P_0402_50V8J

1 2

C365 100P_0402_50V8J

1 2

C366 100P_0402_50V8J

1 2

C367 100P_0402_50V8J

1 2

C368 100P_0402_50V8J

1 2

C369 100P_0402_50V8J

1 2

C370 100P_0402_50V8J

1 2

C372 100P_0402_50V8J

1 2

C373 100P_0402_50V8J

1 2

C615 100P_0402_50V8J

3 3

G-Sensor

RG2

@

12

21

GSENSOR@

VOUT

BP

1ST@

Voutx
Vouty
Voutz

NC1
NC2
NC3
NC4
NC5

GND1
GND2

+3VS_HDP+3VS

CG13

5

CG14

4

GSENSOR@

0.22U_0402_10V4Z

VOUTX

3

VOUTY

5

VOUTZ

7

10
11
14
15
16

1
13

2

1U_0402_6.3V4Z

1

GSENSOR@

12

CG1 0.033U_0402_16V7K1ST@

1 2

CG2 0.033U_0402_16V7K1ST@

1 2

CG3 0.033U_0402_16V7K1ST@

1 2

Reserve Freescale

CG9 0.1U_0402_16V4Z

2ND@

CG10 0.1U_0402_16V4Z

2ND@

CG11 0.1U_0402_16V4Z

2ND@

+3VS_HDP

SELF_TEST

B

VOUTX

12

VOUTY

12

VOUTZ

12

2

3

4

9

7
10
13

UG4

XOUT

YOUT

ZOUT

0G-DET

SLEEP#
G-SELECT
ST

MMA7360LR2_LGA14

2ND@

VDD

VSS

+3VS_HDP

6

1

NC

8

NC

11

NC

12

NC

14

NC

5

HDPINT31

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

+5VS +3VS_HDP

2

CG12

1U_0402_6.3V4Z

GSENSOR@

1

0_0603_5%

DG1 C H751H-40PT_SOD323-2GSENSOR@

UG3

1

VIN

2

GND

3

SHDN#

G9191-330T1U_SOT23-5

Change U55 to G9191-330T1U

UG1

SELF_TEST

2

Vdd1

12

Vdd2

4

ST

6

PD

8

FS

9

Rev

TSH35TR_LGA16

A

+3VS_HDP

4 4

+3VS_HDP

EC_SMB_CK27,31

SELF_TEST

+3VS_HDP

RG3

RG4

RG5

RG6

GSENSOR@

4.7K_0402_5%
RG7

GSENSOR@

1K_0402_5%

0.1U_0402_16V4Z

2008/04/14 2009/04/14

12

4.7K_0402_5%GSENSOR@

12

4.7K_0402_5%GSENSOR@

12

4.7K_0402_5%GSENSOR@

12

12

1

CG7

2

GSENSOR@

Compal Secret Data

GXOUT

GXIN

1

CG8

0.1U_0402_16V4Z

2

Deciphered Date

GSENSOR@

UG6

1

P3_5/SSCK/SCL/CMP1_2

2

P3_7/CNTR0#/SSO/TXD1

3

RESET#

4

XOUT/P4_7

5

VSS/AVSS

6

XIN/P4_6

7

VCC/AVCC

8

MODE

9

P4_5/INT0#/RXD1

10

P1_7/CNTR00/INT10#

R5F211B4D34SP_LSSOP20

1STGSENSOR@

P1_6/CLK0/SSI01

P1_5/RXD0/CNTR01/INT11#

P1_4/TXD0

P1_3/KI3#/AN11/TZOUT

P1_2/KI2#/AN10/CMP0_2

P4_2/VREF

P1_1/KI1#/AN9/CMP0_1

P1_0/KI0#/AN8/CMP0_0

P3_3/TCIN/INT3#/SSI00/CMP1_0

P3_4/SCS#/SDA/CMP1_1

11

12

13

14

VOUTZ

15

16

VOUTX

17

VOUTY

18

19

20

RG9
47K_0402_5%

GSENSOR@

1 2

HDPACT 31

HDPLOCK 31

RG10 47K_0402_5%

12

GSENSOR@

+3VS_HDP

1

CG6

0.1U_0402_16V4Z

GSENSOR@

2

EC_SMB_DA2 7,31

03/11 update G-sensor P/N

Title

Size Document Number Rev

D

Date: Sheet

Compal Electronics, Inc.

SPI/LPC/PS2/MDC/FM/CIR

LA-6032P

32 45Tuesday, March 23, 2010

E

of

1.0Custom

A

B

C

D

E

Power Button & Lid switch

JPB1

1

ON/OFFBTN#31

1 1

ON/OFFBTN#

1

C386

0.1U_0402_16V4Z

2

12/15<BOM> C386 @-->0.1u

51_ON# 35

3

Q14B

2N7002DW-T/R7_SOT363-6

R257

5

4

1 2

EC_ON31,34

10K_0402_5%

2
3
4

5
6

P-TWO_161011-04021_4P-T

CONN@

1/27 Update footprint

03/10 Fine tune R813 R815 120ohm-->220ohm

PWR_ON_LED#31
PWR_SUSP_LED#31

BATT_FULL_LED#31
BATT_LOW_LED#31

WL_BT_LED#31

+5V_ALW

+5VS

DC_IN DC_IN_R
PWR_ON_LED# PWR_ON_LED#_R
PWR_SUSP_LED#
BATT_FULL_LED#
BATT_LOW_LED#
HDD_LED
WIMAX_LED WIMAX_LED_R
WL_BT_LED# WL_BT_LED#_R
MEDIA_LED

R812 120_0402_5%

1 2

R813 220_0402_5%

1 2

R814 120_0402_5%

1 2

R815 220_0402_5%

1 2

R816 120_0402_5%

1 2

R817 120_0402_5%

1 2

R818 120_0402_5%

1 2

R819 120_0402_5%

1 2

R820 120_0402_5%

1 2

LED/B Connector

PWR_SUSP_LED#_R
BATT_FULL_LED#_R
BATT_LOW_LED#_R
HDD_LED_R

MEDIA_LED_R

10
11
12

13
14

JLED1

@

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9
10
11
12

GND1
GND2

ACES_87213-1200G

1/27 Del R808 R809 R810 R811

2 2

1/27 +3VALW-->+3V_ALW and +5VALW-->+5V_ALW

Touch/B Connector

03/11 Update JTP1 footprint

JTP1

1

1

2

2

3

3

4

4

5

5

6

6

7

GND

8

GND

P-TWO_161021-06021_6P-T

CONN@

LID_SW#31

12/24 Add R864

1/27 +3VALW-->+3V_ALW

TP_CLK31
TP_DATA31

LID_SW# LID_SW#_R

1 2

R864 0_0402_5%

TP_CLK
TP_DATA

PACDN042Y3R_SOT23-3

+3V_ALW

+5VS

2

3

D15

1

DC-IN LED

2

DC_IN

6 1

Q14A
2N7002DW-T/R7_SOT363-6

HDD LED

HDD_LED

ACIN 22,31,35

R790

1 2

0_0402_5%

SATA_LED# 22

12/17 Q8 Q9 R258 R259-->@, R790 R791-->SMT

LED_WIMAX# 26

3 3

WIMAX_LED

R791

1 2

0_0402_5%

03/10 Q15-->@ and R260 @-->SMT (memo)

R260

1 2

0_0402_5%

4 4

MEDIA_LED

2

6 1

Q15A
2N7002DW-T/R7_SOT363-6@

Check control pin?

RC4

4.7K_0402_5%

@

1 2

CR_LED# 30

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

LED/LID/PB/FB/SCREW HOLE

LA-6032P

33 45Tuesday, March 23, 2010

E

of

1.0

A

B

C

D

E

< +5VALW TO +5VS > < +1.5V TO +1.5VS >

+5VALW

C387

+5VS

1

1

C388

4.7U_0805_10V4Z

2

2

Q18

S

D

S

D

S

D

G

D

SI4800BDY_SO8

1
2
3

RUNON

4

1U_0402_6.3V4Z

8
7
6
5

1 1

4.7U_0805_10V4Z

C394

1

2

< +1.1VALW TO +1.1VS >< +3VALW TO +3VS >

+3VALW +3VS

Q19

8
7
6
5

1

C395

2

2 2

4.7U_0805_10V4Z

+5V_ALW to +5VALW Transfer

+VSB

12

R900

330K_0402_5%

3 3

PCH_OFF31

@

@

10K_0402_5%

0.1U_0402_16V4Z @

1

S

D

2

S

D

3

S

D

4

G

D

SI4800BDY_SO8

1

2

0.01U_0402_25V7K

+5V_ALW +5VALW

1

C900

@

2

10U_0805_10V4Z

R902

PCH_OFF_R

12

1

C903

2

Inrush current = 0A

1

C390

2

1U_0402_6.3V4Z

RUNON

12

61

@

C396

R262

10M_0402_5%

J2 JUMP_43X118

2

@

SI7326DN-T1-E3_PAK1212-8

U49

@

2

Q40A

112

@

61

2N7002DW-7-F_SOT363-6

2N7002DW-T/R7_SOT363-6

4

12

@

R903

470_0402_5%

@

1

C904
4700P_0402_25V7K

2

C392

1

4.7U_0805_10V4Z

2

R261

12

750K_0402_1%

Q13A

SUSP

2

1
2
35

1

2

2N7002DW-7-F_SOT363-6

+VSB

C901

0.1U_0402_16V4Z

PCH_OFF_R

+3V_ALW to +3VALW Transfer

J3 JUMP_43X118

2

@

SI7326DN-T1-E3_PAK1212-8

+VSB

12

1

2

C902

@

Q40B

10U_0805_10V4Z

5

@

470_0805_5%

R901

1 2

3

4

@

R904

330K_0402_5%

@

C905

@

PCH_OFF_R

2N7002DW-7-F_SOT363-6

@

2

Q41A

(5A,200mils ,Via NO.= 10)

(OCP min=7.9A)

1/25 Add +5V_ALW to +5VALW Transfer
+3V_ALW to +3VALW Transfer

+NB_CORE

U50

@

1

2

3/23 install C9063/23 install C901

10U_0805_10V4Z

61

< Discharge circuit >

Q32B

R331
470_0805_5%

@

1 2

3

@

5

4

2N7002_SOT23-3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+5VL +5VL

12

12

R796

4 4

VGATE31,42

100K_0402_5%

VGATE# VR_ON#

3

Q35B

5

2N7002DW-T/R7_SOT363-6

4

A

R800

100K_0402_5%

61

Q35A
2N7002DW-T/R7_SOT363-6

2

VR_ON# 41

VR_ON 31,42

VLDT_EN#

2N7002DW-T/R7_SOT363-6

B

+1.5V

Q21

8
7

5

1

IRF8113PBF_SO8

4

C407

2

4.7U_0805_10V4Z

10M_0402_5%

112

1
2
35

4

12

@

R906

470_0402_5%

@

1

C908
4700P_0402_25V7K

2

+5VS +3VS

R270
470_0805_5%

1 2

13

D

2

G

Q23

S

1.5VS_ENABLE

12

R269

+1.1VALW

1

C408

2

4.7U_0805_10V4Z

+3VALW+3V_ALW

1

C906

2

0.1U_0402_16V4Z

PCH_OFF_R

2N7002DW-7-F_SOT363-6

SUSP

2008/04/14 2009/04/14

C

1
2
36

1U_0402_6.3V4Z

1

C410

0.1U_0603_25V7M

2

Q22

8
7

5

IRF8113PBF_SO8

1

C907

2

10U_0805_10V4Z

@

@

5

Q41B

1 2
3

5

4

2N7002DW-T/R7_SOT363-6

+1.5VS

Inrush current = 0A

1

2

C402

C403

10U_0805_10V6K

2

1

R267

1 2

61

1M_0402_5%

4

12

R268
10M_0402_5%

@

R905

470_0805_5%

1 2

3

4

R277
470_0805_5%

Q13B

SUSP

2

Q11A
2N7002DW-T/R7_SOT363-6

+1.1VS

1

C405

1

1U_0402_6.3V4Z

2

2

36

0.01U_0402_25V7K

2N7002_SOT23-3

Compal Secret Data

Deciphered Date

R279
470_0805_5%

+VSB

1 2

3

Q11B
2N7002DW-T/R7_SOT363-6

5

4

Inrush current = 0A

1

C406

4.7U_0805_10V4Z

2

1

C409

2

330K_0402_5%

61

2

Q12A
2N7002DW-T/R7_SOT363-6

R266

12

1

+

C622
330U_2.5V_M

2

+VSB

R795 0_0402_5%

5

1 2

R272
470_0805_5%

1 2

3

4

Q12B
2N7002DW-T/R7_SOT363-6

< Inversion of SYSON, SUSP#, VLDT_EN, EC_ON >

+5VL+5VL

12

12

R275

R274

100K_0402_5%

SYSON# SUSP

2N7002DW-T/R7_SOT363-6

SYSON31,40

2N7002DW-T/R7_SOT363-6

+1.8VS

R271
470_0805_5%

1 2

13

D

2

G

Q27

S

D

SYSON#SUSP SUSP

2

G

Q28

2N7002_SOT23-3

+1.5V

Q10B

R276

100K_0402_5%

VLDT_EN#

Q25A

VLDT_EN

2

R280
470_0805_5%

1 2

13

D

S

EC_ON#

2N7002_SOT23-3

Title

Size Document Number Rev

Custom

Date: Sheet

100K_0402_5%

3

61

Q10A

4

12

61

+5VL+5VL

12

R329

100K_0402_5%

3

4

+1.1VALW

@

2

G

Q31

2N7002DW-T/R7_SOT363-6

2

Q25B
2N7002DW-T/R7_SOT363-6

5

R330
470_0805_5%

1 2

13

D

S

5

Compal Electronics, Inc.

DC/DC Circuits

VGATE#

SUSP 41

SUSP# 26,28,31,37,41

EC_ON#

EC_ON 31,33VLDT_EN31,39

SUSP

@

2N7002_SOT23-3

12/18 SYSON#-- >SUSP

LA-6032P

E

+0.75VS

R278
470_0805_5%

1 2

13

D

2

G

Q26

S

34 45Tuesday, March 23, 2010

1.0

of

A

B

C

D

PL1

SMB3025500YA_2P

12

PC3

100P_0402_50V8J

680P_0402_50V7K

68_1206_5%

2

1 2

VIN

1 2

12

PR9

13

12

12

PC2

1000P_0402_50V7K

PD2
RLS4148_LL34-2

12

PR10
68_1206_5%

PC8

0.1U_0603_25V7K

PD3

PR11

200_0603_5%

1 2

100K_0402_1%

1 2

PR14

22K_0402_1%

PF1

7A_24VDC_429007.WRML

12

PR12

21

12

DC_IN_S2

12

PC1

N1

12

PC7

0.22U_0603_25V7K

12

PC18

@

1000P_0402_50V7K

PQ1

TP0610K-T1-E3_SOT23-3

DC30100A900

PJP1

1

+

2

+

3

1 1

2 2

-

4

-

SINGA_2DW-0005-B03@

51_ON#33

DC_IN_S1

BATT+

RLS4148_LL34-2

CHGRTCP

RTC Battery

12

PR17

+CHGRTC

3 3

PJ1

+3VALWP +3V_ALW

(5A,200mils ,Via NO.= 10)
OCP(min)=7.9A

+5VALWP

+VSBP +VSB

2

JUMP_43X118@

PJ4

2

(5A,200mils ,Via NO.= 10)
OCP(min)=8.1A

JUMP_43X118@

PJ6

2

JUMP_43X39@

3.3V

12

112

112

112

(120mA,40mils ,Via NO.= 1)

4 4

(2A,80mils ,Via NO.= 4)
OCP(min)=3A

(1.3A,52mils ,Via NO.= 3)

PJ8

2

112

JUMP_43X118@

PJ10

2

112

JUMP_43X79@

A

PU2 G920AT24U_SOT89-3

3

OUT

PC9
10U_0805_10V4Z

+5V_ALW

+VDDNB+VDDNBP +1.8VS+1.8VSP

+0.9V+0.9VP

GND

1

+1.1VALWP +1.1VALW

IN

(4.6A,180mils ,Via NO.= 9)
OCP(min)=5.26A

+1.5VP

(0.25A,10mils ,Via NO.=1)

200_0603_5%

N2

2

12

PC10

1U_0805_25V4Z

PJ2

2

112

JUMP_43X118@

PJ5

2

112

(8A,320mils ,Via NO.= 16)
OCP(min)=8.55A

(1.3A,52mils ,Via NO.= 3)
OCP(min)=3A

JUMP_43X118@

PJ7

2

112

JUMP_43X39@

PJ9

2

112

JUMP_43X79@

PBJ1

-+

MAXEL_ML1220T10@

X7999651L01

+1.5V

+2.5VS+2.5VSP

B

VIN

PR1

1M_0402_1%

1 2

N1

8

3

+

2

-

4

PR8

10K_0402_1%

N3

7

12

PC11

1000P_0402_50V7K

PU1A

P

O

G

LM393DG_SO8

12

PU1B

O

12

PC19

@

680P_0402_50V7K

VS

12

12

PC4
100P_0402_50V8J

PR18

560_0603_5%

1 2

0.068U_0402_10V6K

PR19

560_0603_5%

1 2

PC5

+RTCBATT

12

VL

EN038

ACON37

PJ3

+NB_COREP +NB_CORE

(7.6A,300mils ,Via NO.= 15)
OCP(min)=9.38A

VL

2

112

JUMP_43X118@

PJ12

2

112

JUMP_43X39@

+5VL

(100mA,40mils ,Via NO.= 2)

PJ17

+3VLP

2

112

JUMP_43X39@

+3VL

VIN

12

PR3

84.5K_0402_1%

12

PR6
20K_0402_1%

VIN

PR5

22K_0402_1%

1 2

12

PC6
.1U_0402_16V7K

PD4

RLS4148_LL34-2

PR21

100K_0402_1%

1 2

PD5
RB715F_SOT323-3

2

1

3

Precharge detector

15.97V/14.84V FOR
ADAPTOR

12

(100mA,40mils ,Via NO.= 2)

PJ15

2

112

(0.5A,20mils ,Via NO.= 1)

JUMP_43X79@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/02 2010/10/02

+0.75VS+0.75VSP

Compal Secret Data

Deciphered Date

C

1

GLZ4.3B_LL34-2

+CHGRTC

3.3V

1 2

PR13

1K_1206_5%

1 2

PR15

1K_1206_5%

1 2

1K_1206_5%

PR22

2.2M_0402_5%

LM393DG_SO8

8

P

+

-

G

4

PC12

1000P_0402_50V7K

PR16

5

6

12

VS

12

PR2

PD1

5.6K_0402_5%

12

10K_0402_1%

1 2

PACIN

12

PR7
10K_0402_1%

PR4

ACIN 22,31,33

PACIN 37

Vin Detector

High 18.384 17.901 17.430
Low 17.728 17.257 16.976

B+

12

PR20

12

12

PR23

10K_0402_1%

12

@

66.5K_0402_1%

Title

Size Document Number Rev

Date: Sheet

+CHGRTC

12

PR25

13

D

S

Compal Electronics, Inc.

499K_0402_1%

12

PR24

499K_0402_1%
PR26
191K_0402_1%

PR27

47K_0402_1%

2

G

PQ2
SSM3K7002FU_SC70-3

13

2

PQ3
DTC115EUA_SC70-3

DCIN/DECTOR

LA6032P

D

12

PC13
1000P_0402_50V7K

12

+5VALWP

of

35 45Tuesday, March 23, 2010

PACIN

1.0

A

B

C

D

PH1 under CPU botten side :

For 11.6"

PJP2

1

1

2

2

3

3

4

4

5

1 1

5
GND
GND
GND
GND

6

6

7

7

8

8

9

9

10
11
12
13

SUYIN_200045MR009G171ZR@

BATT_S1

BATT_P3
BATT_P4
BATT_P5
EC_SMDA

EC_SMCA

PF2

10A_125V_451010MRL

21

1 2

PR28

1K_0402_1%

12

PR30
1K_0402_1%

1 2

PR29

47K_0402_1%

+3VLP

VMB

12

PC14

@

0.1U_0402_25V6

SMB3025500YA_2P

1 2

12

PC15
1000P_0402_50V7K

PL2

BATT+

12

PC16

0.01U_0402_25V7K

CPU thermal protection at 92 degree C
Recovery at 56 degree C

PH2 near main Battery CONN:

BAT thermal protection at 78 degree C
Recovery at 42 degree C

Rset = 3*Rtmh
Rhyst = (Rset* Rtml) / (3*Rtml - Rset)

PD16

For 13.3"

PJP3

10

GND

11

GND

12

GND

13

GND

SUYIN_200045MR009G171ZR@

2 2

BATT_S1

BATT_S1

1

1

2

2

BATT_P3

3

3

BATT_P4

4

4

BATT_P5

5

5

EC_SMDA

6

6

EC_SMCA

7

7

8

8

9

9

1

2

3

PR34

100_0402_1%

1 2

PD17

@

PJSOT24C_SOT23-3

12

PR39
1K_0402_1%

PR35

100_0402_1%

1 2

@

PJSOT24C_SOT23-3

2

3

1

PR36

6.49K_0402_1%

12

+3VLP

BATT_TEMPA 31

EC_SMB_DA1 31

EC_SMB_CK1 31

VS_ON38

VL

PC17

0.1U_0603_25V7K

12

PR31

34.8K_0402_1%

PU3

1

VCC

TMSNS1

2

GND

RHYST1

3

OT1

TMSNS2

4

RHYST2

OT2

G718TM1U_SOT23-8

1 2

8

7

6

12

5

PR32

15.4K_0402_1%

12

PR37
22K_0402_1%

PR38

10.2K_0402_1%

1 2

12

PH2
100K_0402_1%_NCP15WF104F03RC

12

PH1
100K_0402_1%_NCP15WF104F03RC

Rtmh at 92C = 7.71K,Rtml at 56C = 26.1K

Rset = 3* 7.31 = 21.9K ==> PR37 = 22K

PQ5

TP0610K-T1-E3_SOT23-3

13

2

VL

1 2

B+

PR48
0_0402_5%

1 2

12

12

PR45

PC21

@

PR46

22K_0402_1%

1 2

13

D

PQ6

2

G

SSM3K7002FU_SC70-3

S

12

PC23

@

.1U_0402_16V7K

100K_0402_1%

0.22U_0603_25V7K

3 3

PR47

100K_0402_1%

POK38,39

4 4

+VSBP

12

PC22

@

0.1U_0603_25V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rhyst = ( 22K* 26.1K ) / ( 3* 26.1K - 22K) = 10.199K ==> PR38 = 10.2K

Rtmh at 78C = 11.635.K,Rtml at 42C = 46.38K

Rset = 3* 11.635 = 34.91K ==> PR31 = 34.8K

Rhyst = ( 34.8K* 46.38K ) / ( 3* 46.38K - 34.8K) = 15.468K ==> PR32 = 15.4K

2009/10/02 2010/10/02

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

BATTERY CONN / OTP

LA6032P

D

36 45Tuesday, March 23, 2010

1.0

of

A

B

C

D

12

10U_1206_25V6M

DCIN

PQ12

13

DTC115EUA_SC70-3

24

23

22

21

20

19

18

17

BST_CHG

16

15

DL_CHG

14

13

12

PC127

HCB2012KF-121T50_0805

10U_1206_25V6M

1

2

0.1U_0603_25V7K

DCIN

PC32

0.047U_0603_16V7K

1 2

PC37

0.1U_0603_25V7K

1 2

LX_CHG

DH_CHG

0_0603_5%

1 2

6251VDDP

PL3

PD8

FSTCHG

2

3

RB715F_SOT323-3

PC30

12

PR61

20_0603_5%

1 2

1 2

PR62

20_0603_5%

20_0603_5%

1 2

PR65

2.2_0603_5%

PR70

BST_CHGA

12

PC45

1 2

4.7U_0805_6.3V6K

12

PR63

PR51

10_0603_5%

1 2

12

DCIN

ACPRN

CSON

CSOP

CSIN

CSIP

PHASE

UGATE

BOOT

VDDP

LGATE

PGND

PC69

12

12

PC38

1 2

PC39

PR73

26.7K_0402_1%

1 2

PR75

20K_0402_1%

15.4K_0402_1%

1 2

PR49

0.033_1206_1%

1

2

PR76

31.6K_0402_1%

4

3

CSIP

PQ10 TP0610K-T1-E3_SOT23-3

2

6251VDD

PC29

12

2.2U_0603_6.3V6K

PR59

100K_0402_1%

6251_EN CSON

PR66

47K_0402_1%

1 2

6251VREF

6251aclim

12

12

PR77

13

100K_0402_1%

12

10

11

12

B+

PR55

PU5

1

VDD

2

ACSET

3

EN

4

CELLS

5

ICOMP

6

VCOMP

7

ICM

8

VREF

9

CHLIM

ACLIM

VADJ

GND

ISL6251AHAZ-T_QSOP24

PQ7
AO4435_SO8

VIN

1 1

2

G

2 2

PACIN35

ACON35

ACOFF31

8
7
6
5

12

DTA144EUA_SC70-3
PR52
47K_0402_1%

2

13

D

PQ15
SSM3K7002FU_SC70-3

S

PACIN

DTC115EUA_SC70-3

ACOFF

PQ11

2

13

PQ13
DTC115EUA_SC70-3

PR68

22K_0402_5%

1 2

4

PQ20

1
2
3

1 3

2

P2

12

PC27

0.1U_0603_25V7K

2

G

13

1
2
3 6

12

PR50
200K_0402_1%

12

PR58
150K_0402_1%

13

D

PQ18
SSM3K7002FU_SC70-3

S

IREF31

PQ8
AO4407A_SO8

4

5600P_0402_25V7K

FSTCHG31

0.01U_0402_25V7K

PR71

174K_0402_1%

PR72

100K_0402_1%

PC28

12

8
7

5

PC36

1 2

ADP_I31

12

P3

100K_0402_1%

1 2

1SS355_SOD323-2

1 2

10K_0402_1%

1 2

PC31

.1U_0402_16V7K

680P_0402_50V7K

CSON

PC35 6800P_0402_25V7K

PR64 6.81K_0402_1%

1 2

100P_0402_50V8J

12

PC43

0.01U_0402_25V7K

P3

PR53

PD10

PR57

PC34

@

1 2

1 2

1 2

@

.1U_0402_16V7K

6251VREF

CHGVADJ31

3 3

12

PC47

PC68

10U_1206_25V6M

CSIN

SUSP# 26,28,31,34,41

CSOP

12

PC40

0.1U_0603_25V7K

PD12
RB751V-40TE17_SOD323-2

1 2

PR74

4.7_0603_5%

12

6251VDD

12

10U_1206_25V6M

12

PC24

4.7U_0805_25V6-K

CHG_B+

12

12

PC25

PC26

4.7U_0805_25V6-K

4.7U_0805_25V6-K

DTC115EUA_SC70-3

578

3 6

241

578

3 6

241

B+

PR56

10K_0402_1%

1 2

13

PQ14

PQ16
AO4466_SO8

10U_LF919AS-100M-P3_4.5A_20%

PQ19
AO4466_SO8

1 2

12

PR69

@

12

PC44

@

PL4

4.7_1206_5%

680P_0603_50V7K

PR54

47K_0402_1%

1 2

1SS355_SOD323-2

1 2

2

1SS355_SOD323-2

0.1U_0603_25V7K

CHG

PQ9 AO 4435_SO8

1
2
3

4

VIN

PD9

1 2

200K_0402_1%

1 2

PD11

12

PC33

PR67

0.02_1206_1%

1

2

8
7
6
5

ACOFF

PR60

13

D

G

PQ17

S

SSM3K7002FU_SC70-3

4

3

VIN

PACIN

2

BATT+

12

PC41

10U_1206_25V6M

12

PC42

10U_1206_25V6M

PR78

309K_0402_1%

PR80

47K_0402_1%

VIN

12

PR79

10K_0402_1%

1 2

12

12

PC46

.1U_0402_16V7K

2009/10/02 2010/10/02

Compal Secret Data

Deciphered Date

C

ADP_V 31

Title

Size Document Number Rev

Custom

Date: Sh eet

Compal Electronics, Inc.

CHARGER

LA6032P

D

37 45Tuesday, March 23, 2010

of

1.0

Iadapter=0~2.368A(45W) CP=Iadapter*0.92 CP=2.178A

CC=0.25A~3A

IREF=1.096*Icharge

IREF=0.254V~3.048V

VCHLIM need over 95mV

CP mode

Vaclim=2.39*(20K//152K/(20K//152K+26.7K//152K))=1.04596V

Iinput=(1/0.02)((0.05*Vaclm)/2.39+0.05)
where Vaclm=1.04596V, Iinput=2.178A

4 4

CHGVADJ=(Vcell-4)*9.445

Vcell CHGVADJ

4V

4.2V

4.35V

A

0V

1.882V

3.2935V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

1

2VREF_51125

12

PC48

D D

1U_0603_10V6K

PR86

13K_0402_1%

1 2

BST_3V

UG_3V

LX_3V

LG_3V

12

PR88

20K_0402_1%

1 2

PR90

121K_0402_1%

1 2

PU6

25

P PAD

7

VO2

8

VREG3

9

BOOT2

10

UGATE2

11

PHASE2

12

LGATE2

12

PC67

1U_0402_6.3V6K

2VREF_51125

ENTRIP2

6

5

FB2

ENTRIP2

SKIPSEL

EN

14

13

1 2

PR96

0_0402_5%@

B++

4

TONSEL

15

3

REF

VIN16GND

12

PC61

PL5

HCB4532KF-800T90_1812

1 2

B+

12

PC56

@

1U_0603_25V6K

C C

+3VALWP

Ipeak = 5A

Imax = 3.5A

F = 305kHz

Total Capacitor = 150 uF

B B

ESR = 18m Ohm

VS_ON36

A A

B++

12

PC49

2200P_0402_50V7K

150U_V_6.3VM_R18

SSM3K7002FU_SC70-3

VL

1 2

VS

PR83

100K_0402_1%

12

PC58

PQ36

100K_0402_1%

12

PR85

PC50

10U_1206_25V6M

PL6

4.7UH_PCMC063T-4R7MN_5.5A_20%

1 2

1

+

2

13

D

2

G

S

12

PR81

12

PC59

@

42.2K_0402_1%

2

0.01U_0402_16V7K

13

D

G

S

2

G

PQ38
SSM3K7002FU_SC70-3

12

PR84

4.7_1206_5%

12

PC63

680P_0603_50V8J

13

D

PQ37
SSM3K7002FU_SC70-3

S

123

3 5

241

5

ENTRIP2ENTRIP1

PQ21

AON7408L_DFN8-5

PQ23

AON7702L_DFN8-5

4

PC65

.1U_0402_16V7K

12

PC53

+3VLP

12

4.7U_0805_10V6K

1 2

PC54

.1U_0402_16V7K

B+

PR92

1 2

2.2_0603_1%

EN035

PR94

499K_0402_1%

1 2

PR95

100K_0402_5%

PR87

30K_0402_1%

1 2

PR89

19.6K_0402_1%

1 2

121K_0402_1%

ENTRIP1

1 2

1

2

FB1

ENTRIP1

VO1

PGOOD

BOOT1

UGATE1

PHASE1

LGATE1

NC18VREG5

17

12

PC60

4.7U_0805_10V6K

0.1U_0603_25V7K

PR91

24

23

22

21

20

19

2.2_0603_1%

BST_5V

1 2

UG_5V

LX_5V

LG_5V

RT8205EGQW_W QFN24_4X4

VL

12

PC66

.1U_0402_16V7K

PR93

B++

12

PC51

2200P_0402_50V7K

POK 36,39

PC55
.1U_0402_16V7K

1 2

12

PC52

10U_1206_25V6M

PQ24

AON7702L_DFN8-5

PQ22

AON7408L_DFN8-5

3 5

241

5

4

123

PL7

4.7UH_PCMC063T-4R7MN_5.5A_20%

1 2

12

PR82

4.7_1206_5%

12

PC62

680P_0603_50V8J

1

PC64

+

150U_V_6.3VM_R18

2

+5VALWP

Ipeak = 5A

Imax = 3.5A

F = 245kHz

Total Capacitor = 150 uF

ESR = 18m Ohm

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/02 2010/10/02

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

+5VALWP/+3VALWP

LA-6032P

38 45Tuesday, March 23, 2010

1

1.0

of

5

D D

PR103

0_0402_5%

POK36,38

+5V_ALW

C C

1 2

PR106

100_0603_1%

1 2

PC75

4.7U_0603_6.3V6K

12

PC72
.1U_0402_16V7K

@

12

PR108

4.7K_0402_1%

1 2

12

PR109
10K_0402_1%

4

PR102

255K_0402_1%

1 2

15

1

PU7

2

TON

3

VOUT

4

VDD

5

FB

6

PGOOD

EN/DEM

GND7PGND

NC

8

PR104

2.2_0603_5%

1 2

14

BOOT
UGATE

PHASE

CS

VDDP

LGATE

RT8209BGQW_WQFN14_3P5X3P5

13

12

11

10

9

BST_1.1V

DH_1.1V

LX_1.1V

1 2

PR107

9.1K_0402_1%

DL_1.1V

PC73

1 2

0.1U_0603_25V7K

+5V_ALW

12

PC76

4.7U_0805_10V6K

3

578

578

2

PL8

PC71

4.7U_0805_25V6-K

PC74

220U_6.3V_M

HCB2012KF-121T50_0805

12

+1.1VALWP

1

+

2

PL16

HCB2012KF-121T50_0805

12

B+

Ipeak = 4.6A

Imax = 3.22A

F = 314kHz

Total Capacitor = 550 uF

ESR = 8.5m Ohm

B+

1.1V_B+

12

12

PC70

4.7U_0805_25V6-K

PQ26

AO4466_SO8

3 6

241

PL9

1.8UH_1164AY-1R8N=P3_9.5A_30%

1 2

12

PR105

4.7_1206_5%

12

PQ27

AO4712_SO8

3 6

241

PC77

680P_0603_50V7K

NB_CORE_B+

1

12

12

PR165

255K_0402_1%

PR123

B B

A A

VLDT_EN31,34

+5V_ALW

0_0402_5%

1 2

PR142

100_0603_1%

1 2

PC89

4.7U_0603_6.3V6K

12

PC125
.1U_0402_16V7K

@

12

PR166

2.7K_0402_1%

1 2

12

PR119
10K_0402_1%

1 2

15

1

PU14

2

TON

3

VOUT

4

VDD

5

FB

6

PGOOD

EN/DEM

GND7PGND

NC

8

PR120

2.2_0603_5%

1 2

14

BOOT
UGATE

PHASE

CS

VDDP

LGATE

RT8209BGQW_WQFN14_3P5X3P5

13

12

11

10

9

BST_NB_CORE

DH_NB_CORE

LX_NB_CORE

1 2

PR122

13.7K_0402_1%

DL_NB_CORE

PC90

1 2

0.1U_0603_25V7K

+5V_ALW

12

PC124

4.7U_0805_10V6K

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PQ39

AON7408L_DFN8-5

3 5

241

PL15

2.2UH_FMJ-0630T-2R2 HF_8A_20%

1 2

5

123

3

12

PR161

4.7_1206_5%

12

PQ40

AON7702L_DFN8-5

PC85

680P_0603_50V7K

2009/10/02 2010/10/02

Compal Secret Data

PC93

4.7U_0805_25V6-K

Deciphered Date

PC95

4.7U_0805_25V6-K

+NB_COREP

1

+

PC94

2

220U_D2_4VM

Ipeak = 7.6A

Imax = 5.32A

F = 315kHz

Total Capacitor = 550 uF

ESR = 5.63m Ohm

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

+1.1VALWP/+NB_COREP

LA6032P

1

of

39 45Tuesday, March 23, 2010

1.0

5

D D

PR111

0_0402_5%

SYSON31,34

+5V_ALW

C C

1 2

100_0603_1%

1 2

4.7U_0603_6.3V6K

PR114

PC83

4

12

PC80
.1U_0402_16V7K

@

12

PR116

10K_0402_1%

1 2

12

PR117
10K_0402_1%

3

578

PQ28

PR110

255K_0402_1%

1 2

15

1

PU8

2

TON

3

VOUT

4

VDD

5

FB

6

PGOOD

EN/DEM

GND7PGND

NC

8

PR112

2.2_0603_5%

1 2

14

BOOT
UGATE

PHASE

CS

VDDP

LGATE

RT8209BGQW_WQFN14_3P5X3P5

13

12

11

10

9

BST_1.5VP

DH_1.5VP

LX_1.5VP

1 2

PR115

15.4K_0402_1%

DL_1.5VP

AO4466_SO8

PC81

1 2

0.1U_0603_25V7K

+5V_ALW

AO4712_SO8

12

PC86

4.7U_0805_10V6K

PQ29

3 6

578

3 6

2

241

1.8UH_1164AY-1R8N=P3_9.5A_30%

241

1.5V_B+

12

1 2

12

PR113

12

PC84

PC78

4.7U_0805_25V6-K

PL11

4.7_1206_5%

680P_0603_50V7K

1

PL10

HCB2012KF-121T50_0805

12

1

PC79

PC128

47U_25V_M

4.7U_0805_25V6-K

2

12

B+

12

PC57

+

@

1U_0603_25V6K

+1.5VP

1

+

PC82

2

220U_6.3V_M

Ipeak = 8A

Imax = 5.6A

F = 313kHz

Total Capacitor = 880 uF

ESR = 5.67m Ohm

B B

PU9

PJ11

+3VS

A A

5

4

JUMP_43X39@

112

2

PC87

1U_0603_10V6K

APL5508-25DC-TRL_SOT89-3

2

IN

12

3

OUT

GND

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

PC88

4.7U_0805_6.3V6K

3

+2.5VSP

2009/10/02 2010/10/02

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

1.5VP/2.5VSP

LA6032P

1

of

40 45Tuesday, March 23, 2010

1.0

5

4

3

2

1

12

PR180

402K_0402_1%

12

PC141

1 2

10U_0805_10V4Z

+1.5V

1

1

@

2

2

12

13

D

2

G

S

PR179
316K_0402_1%

1 2

12

PC139

.1U_0402_16V7K

1 2

0_0402_5%

PC142

10U_0805_10V4Z

PJ13
JUMP_43X79

12

PR118

PC91

1K_0402_1%

4.7U_0805_6.3V6K

12

PR124
1K_0402_1%

PQ30

SSM3K7002FU_SC70-3

1 2

PR181

PU10

VIN1VCNTL

2

GND

3

VREF

4

VOUT

G2992F1U_SO8

12

12

PC98
10U_0805_6.3V6M

0.1U_0402_10V7K

PC97

PU11

1

EN/SYNC

FB

2

GND

3

4

5

GND

SW

SW

IN

IN

POK

BS

TP

MP2121DQ-LF-Z_QFN10_3X3

10

9

8

7

6

11

NC

NC

NC

TP

+0.75VSP

+1.5V

6

5

7

8

9

12

PC92
1U_0603_10V6K

PR178

200K_0402_1%

1 2

12

PC138

0.22U_0402_10V4Z

12

PD15

@

B340A_SMA2

+5V_ALW

PL17

2.2UH_SILM320A-2R2_1.6A_30%

1 2

12

PR182

4.7_1206_5%

12

PC143
680P_0603_50V7K

VR_ON#34

SUSP# 26,28,31,34,37

12

PC144

22U_0805_6.3V6M

4.7U_0805_6.3V6K

PR126

0_0402_5%

1 2

PC102

@

.1U_0402_16V7K

12

PC145

22U_0805_6.3V6M

+1.8VSP

1

PJ14

1

JUMP_43X79@

2

2

12

PC99

2

G

12

PR125

1K_0402_1%

13

D

PR127

1.5K_0402_1%

S

PQ31

SSM3K7002FU_SC70-3

Ipeak = 1.3A

Imax = 0.91A

Total Capacitor = 44 uF

ESR = 2.5m Ohm

PU12

VIN1VCNTL

2

.1U_0402_16V7K

GND

3

VREF

4

VOUT

G2992F1U_SO8

+0.9VP

12

PC103
10U_0805_6.3V6M

12

12

12

PC101

6

5

NC

7

NC

8

NC

9

TP

+3V_ALW

12

PC100
1U_0603_6.3V6M

D D

PR121

+1.8VSP

300K_0402_1%

0.22U_0402_10V4Z

2

PC96

12

PC140

0.1U_0402_25V6

SUSP34

C C

B B

+5V_ALW

PJ16

112

JUMP_43X79

@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/10/02 2010/10/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

0.75VSP/0.9VP/1.8VSP

LA6032P

1

of

41 45Tuesday, March 23, 2010

1.0

A

B

C

D

E

HCB2012KF-121T50_0805

1

+

PC123

47U_25V_M

2

@

1

+

2

CPU_B+

12

12

PC115

10U_1206_25V6M

10U_1206_25V6M

12

12

PL12

12

PC111
220U_D2_4VM

PR148

4.7_1206_5%

PC117
680P_0603_50V7K

B+

+VDDNBP

1

2

PR149

12.7K_0402_1%

1 2

0.1U_0603_16V7K

4.53K_0402_1%

ISP0

PL14

PC118

PR153

4

3

12

12

ISN0

0.36UH_PCMC104T-R36MN1R17_30A_20%

+CPU_CORE_0

PQ32
AO4466_SO8

PQ33

AO4712_SO8

4

4

CPU_B+

12

PC106

10U_1206_25V6M

4.7UH_SIQB74B-4R7PF_4A_20%

1 2

12

PR132

4.7_1206_5%

12

PC112
680P_0603_50V7K

5

PQ34

123

TPCA8030-H_SOP-ADV8-5

PQ35

123 5

TPCA8028-H_SOP-ADVANCE8-5

1

+

PC107

47U_25V_M

2

PL13

PC114

PC104

33P_0402_50V8J

12

12

PR128

44.2K_0402_1%

12

45

47

48

46

VIN

VCC

FB_NB

COMP_NB

ISL6265AHRTZ-T_TQFN48_6X6

VSEN0

RTN0

ISN0

ISP0

15

16

14

13

12

PR159

@

1K_0402_5%

PC108

1000P_0402_50V7K

22K_0402_1%

44

43

FSET_NB

VSEN_NB

RTN1

VSEN1

17

18

VSEN1

1 1

CPU_B+

+5VS +3VS

12

12

12

12

PR141

PR140

105K_0402_1%

2 2

VGATE31,34

VR_ON31,34

PR151

21.5K_0402_1%

1 2

1 2

12

H_PWRGD7,20

H_PWRGD_L20

3 3

CPU_SVD7
CPU_SVC7

@

10K_0402_1%

PR146 100K_0402_5%@

PR144 100K_0402_5%

PR152

95.3K_0402_1%

12

+CPU_CORE_0

CPU_VDD0_RUN_FB_H7

CPU_VDD0_RUN_FB_L7

10_0402_5%

PR137
0_0402_5%

PR147

0_0402_5%

PR154

PR158

@

12

@

ISL6265_PWROK

12

0_0402_5%

1 2

10_0402_5%

+5VS

0.1U_0603_25V7K

PR138
105K_0402_1%

PR143
105K_0402_1%

12

PR150

0_0402_5%

PR155

0_0402_5%

PR156

0_0402_5%

PR157

PR129

2_0603_5%

1 2

PC109

0.1U_0603_16V7K

1 2

PR134

2_0603_5%

PC113

PU13

1

OFS/VFIXEN

2

PGOOD

3

PWROK

4

SVD

5

12

SVC

6

ENABLE

7

RBIAS

8

OCSET

9

VDIFF0

10

FB0

11

COMP0

12

VW0

VSEN1

ISP0
ISN0

1 2

VSEN0

12

RTN0

12

+1.5V

12

PC105

1000P_0402_50V7K

12

PR130

12

PR135

0_0402_5%

12

PR139
0_0402_5%

5.49K_0402_1%

42

41

40

RTN_NB

PGND_NB

OCSET_NB

VDIFF1

COMP121ISP1

FB1

19

20

12

@

12

PR136

39

LGATE_NB

VW1

22

PR133

10_0402_5%

1 2

12

37

38

BOOT_NB

PHASE_NB

UGATE_NB

ISN1

23

24

ISN0

ISP0

+VDDNBP

BOOT0

UGATE0

PHASE0

PGND0

LGATE0

PVCC

LGATE1

PGND1

PHASE1

UGATE1

BOOT1

CPU_VDDNB_RUN_FB_H 7

PHASE_NB

LGATE_NB

PHASE_NB

UGATE_NB

36

35

34

33

32

31

30

29

28

27

26

25

TP

49

UGATE_NB

PHASE_NB

BOOT_NB

LGATE_NB

BOOT_NB

BOOT0

UGATE0

PHASE0

LGATE0

PR131

2.2_0603_1%

1 2

0.22U_0603_10V7K

+5VS

UGATE0

PHASE0

BOOT0

12

PC119
1U_0603_16V6K

1 2

PC110

PR145

2.2_0603_1%

1 2

0.22U_0603_10V7K

578

3 6

578

3 6

PC116

LGATE0

241

241

1 2

DIFF_0

PR160

255_0402_1%

4 4

PC120

4700P_0402_25V7K

12

PR162

1K_0402_5%

FB_0

12

12

54.9K_0402_1%

12

@

A

PC121

180P_0402_50V8J

PR163

PR168

36.5K_0402_1%

VW0

COMP0

12

PC126

12

12

1200P_0402_50V7K

12

PC122

1000P_0402_50V7K

PR164

6.81K_0402_1%

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/10/02 2010/10/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

+CPU_CORE

LA6032P

42 45Tuesday, March 23, 2010

E

of

1.0

Version Change List ( P. I. R. List ) for Power Circuit

Version Change List ( P. I. R. List ) for Power Circuit

Version Change List ( P. I. R. List ) for Power CircuitVersion Change List ( P. I. R. List ) for Power Circuit

Request

Request

Title

Title

Page#

Page#

Page#Page#

P38 BATTERY CONN / OTP

P38 BATTERY CONN / OTP

P38 BATTERY CONN / OTP

P38 BATTERY CONN / OTP

P43

P43

TitleTitle

CHARGERP39 2009/12/03 POWER DVTPC24,25,26 size change to 4.7uf 0805

0.75VSP/0.9VP/1.8VSPP43

0.75VSP/0.9VP/1.8VSP

0.75VSP/0.9VP/1.8VSPP43

0.75VSP/0.9VP/1.8VSP

+CPU_COREP44

CHARGERP39 2010/01/29 POWER PVTAdd PC47,68,69,127 10U_1206_25V6M

+1.1VALWP/+NB_COREP

Date

Date

DateDate

2009/12/03

2009/12/03

2009/12/03

2009/12/03

2009/12/03

2009/12/03

2009/12/03

2009/12/03

2009/12/03

2010/02/03

2010/02/03

RequestRequest

Owner

Owner

OwnerOwner

POWER Release2009/11/10

POWER

POWER

POWER

POWER

POWER

POWER

POWER

POWER

POWER

Issue Description

Issue Description

Issue DescriptionIssue Description

PR31 change to 34.8k

PR32 change to 15.4k

PR37 change to 22k

PR38 change to 10.2k

PR121 change to 300k

PC96 change to 0.22uf

PR125 change to 1k

PR127 change to 1.5k

Delete PR142

Solution D escription

Solution D escription

Solution D escriptionSolution D escription

DVT

DVT

DVT

DVT

DVT

DVT

DVT

DVT

DVT

DVTPR131, PR145 change to 2.2 ohm2009/12/03 POWER+CPU_COREP44

DVTPR132 change to 4.7_1206_5%2009/12/03 POWER+CPU_COREP44

DVTPC112 change to 680P_0603_50V7K2009/12/03 POWER+CPU_COREP44

PVTAdd PC70 4.7U_0805_25V6-KPOWERP41

PVTPL9 change to 1.8UH_9.5A_30%POWER+1.1VALWP/+NB_COREPP41

PVTPL13 change to 4.7UH_4A_20%2009/12/03 POWER+CPU_COREP44

PVT2Move PR18,PR19 to connect PBJ12009/02/08 POWERCHARGERP37

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/10/02

Compal Secret Dat a

Deciphered Date

2010/10/02

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Tuesday, March 23, 2010

Date: Sheet

Power PIR

LA6032P

of

43 45

1.0

5

4

3

2

1

EVT to DVT Version change list (P.I.R. List) Page 1 of 2

Item Reason for change PG# Modify List

1 Update JSATA1, JHDMI1 and JREAD1 footprint ME request

2

Update DDR_CS0_DIMMB#, DDR_CS1_DIMMB# net P06

Update DDR_CKE0_DIMMA, DDR_CKE1_DIMMA net P06

3

R41~R44 SMT-->@4

Del R46 and add R850~R854 P07 For ESD request

5

D D

Add RS15 RS16 for NBGFX_CLK,NBGFX_CLK# P12 For internal clock gen

6

Fine tune RS880M clock P12 For internal clock gen

7

Del external clock gen P16 For internal clock gen

8

9

Fine tune pin define JP4 Pin1 Pin2 Pin8-->GND P17 Add more GND pin

10

Add R855 R856 for HDMI_SDATA,HDMI_SCLK pull high R Solve HDMI can not detect

11

U6 pin5 +5VL-->+5VS and HDMI Dual NMOSx2(Q6 Q7)->Single NMOS (Q6)

12

Add RS1~RS14 near SB820M and TP34 TP35 P20 For internal clock gen

13

C640 @-->22P on CLK_PCI_EC P20 EMI request

14

C705 C705 @-->SMT on Y6 P20

15

R152 R153 R154 pull +3VALW-->pull GND P21 Follow AMD check list 1.03

16

Add device clock request pin on SB820M P21 For internal clock gen

17

C632 @-->33P on AZ_BITCLK_HD P21 EMI request

18

Add WLAN_PWR_EN# and WW AN_PWR_EN# net on SB820M

19

U47 +3VL-->+3VALW and Y3 R164 C246 C247 SMT->@

20

Reaserved R859 C707 on CLK net P22 EMI request

21

Fine tune SB820M strap pin P24 For internal clock gen

22

Add C706 0.1u on CLK_PCI_EC P24 EMI request

C C

23

Del R193 and Add R858 PH on USB_OC#2 P25 Solve the USB hang up issue

24

Reserved RM5 RM6 CM17 QM1 RM9 for +3V_WWAN power saving

25

Reserved RM7 RM8 CM18 QM2 RM10 for +3V_WLAN power saving

26

Reserved CM19 QM3 RM11 for +1.5V_WLAN power saving

27

RL21 pin2 +3V_LAN-->GND

28

Del RA4 RA5

29

Reserved RA27 CA26 on AZ_RST_HD#

30

Add Q37 R860 R861 and PD# net

31

Fine tune JP5 pin define

32

Fine tune SPK_L1,SPK_L2,SPK_R1 and SPK_R2 for SPK

33

Add R857 PH USB_OC#0 net

34

Add C708 on +5VS

35

Fine tune card reader pin define

36

Add EC_MUTE# on KBC926 (U12) 83pin

37

Q8 Q9 R258 R259-->@, R790 R791-->SMT P33 Cost down plan

38

C386 @-->0.1u on ON/OFFBTN# P33 EMI request

39

C410 0.01u_0402_16V-->0.1u_0603_25V and R267 330k->1M P34 SMT memo

40

SYSON#-->SUSP on Q26 Pin2 P34 +0.75VS disc harge control pin

B B

41

RA26 0ohm-->Bead (SM010017710) on INT_MIC_CLK P28 EMI request

42

C632 @-->33P on AZ_BITCLK_HD P21 EMI request

43

R788 @-->100ohm and C634 @-->100P on SPI_CLK

44

R789 @-->100ohm and C635 @-->100P on AZ_BITCLK_HD

45

Add CA63 on INT_MIC_CLK_R

46

RA1 0ohm-->Bead on Audio power

47

Add CM20 1000P on +3V_WWAN P26 RF request

Add C709 on 27M_SEL P16 RF request (EXT only)49 2009/12/19 EVT->DVT

49

Fine tune R133 R value 11.8K-->8.2K P21 2009/12/22Fine tune USB signal EVT->DVT

50

<BOM>RA22 RA25 4.7K-->2.2K and CA16 10u-->@ P28 Audio vender request 2009/12/22 EVT->DVT

51

Add BT_PWR# net contact to JWLAN1 pin5

52

Del R161 and SLP_CHG on SB

53

Add SLP_CHG on pin115 and add R862

Add UA2 CA67 CA68 CA69 P28 Audio power reserved 2009/12/23 EVT->DVT

54

55

Add F2 for card reader proetct

Reserved RA28 CA70

56

Add R863 PH on CIR_EN#

57

A A

58 Add R864 on LID_SW# P33 Reserv ed for ESD protect 2009/12/24 EVT->DVT

59 Modify TP26 TP27-->EVENT#_A and EVENT#_B

60 C497 SMT-->@ P08 Fine tune CPU_CORE cap 2009/12/25 EVT->DVT

Net contact error on DIMMB

Net contact error on DIMMA

P07 Fine tune HDT debug pull high R

P19

P19 Cost down plan

P22

Power saving request

P22

25MHz by default

P26

Power saving request

P26

Power saving request

P26

Power saving request

P27

LAN vender request

P28 Fine tune Audio HP out voltage

P28

ESD request

P28

Solve Audio PD# control issue

P29

Solve the USB hnag up issue

P29

Solve SPK pin issue

P29 Solve the USB hnag up issue

P29 ESD request

P30 ME use new card reader connector

P31 Solve Audio PD# control issue

P32 RF request

P28 RF request

P28 RF request

P28 RF request

P26 Follow common design

P22 Follow common design

P31 Follow common design

P30 H/W request 2009/12/24 EVT->DVT

P28 Reserved for fin tune aduio power control

P21 Follow common design

P09 P10

Solve layout test point issue 2009/12/25 EVT->DVT

Date Phase

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12

2009/12/18

2009/12/18

2009/12/18

2009/12/18

2009/12/18

2009/12/18

2009/12/18

2009/12/23

2009/12/23

2009/12/23

2009/12/24

2009/12/24

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

EVT->DVT

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

2005/03/10 2006/03/10

Deciphered Date

2

Compal Electronics, Inc.

Title

EE change list-1

Size Document Number Rev

Custom

Date: Sheet of

44 45Tuesday, March 23, 2010

1

5

4

3

2

1

DVT to PVT Version change list (P.I.R. List) Page 2 of 2

Item Reason for change PG# Modify List

Add D17 and Q38 for BT power control

1 Follow common design

Change net name SLP_CHG-->SLP_CHG#

2

Need to fine tune R783 and R784

3

<BOM> SB use 2MB SPI ROM SA00002TO00

4

<BOM> Update LAN P/N for LAN VB P/N

5

D D

<BOM> EC SPI use 256KB SPI ROM SA00003GK00

6

7

BT part SMT-->@

8

Update JREAD1 footprint (Same as EVT)t

9

Update JSATA1 footprint TAIWI_EU114-117CRL-TW_11P-T

10

Update JHDD1 pin4 +5VS-->GND

11

Del DC to DC +NB_CORE part

12

Change USB port10 to USB port5 on WWAN

13

Add R865 R866 for SLP_CHGX_M3/M4 on SB

14

Add R867 R868 for SLP_CHGM3/M4 on EC

15

UA2 pin5 +PVDD1--->+AVDD

16

<BOM> U48 SA000008G00-->SA00003DR00 (Same as intel)

17

Del R164 Y3 C246 C247 and add TP36 TP37

18

JLVDS1 pin24 +LCD_INV-->NG

19

U9 pin1 +5VALW-->+5V_ALW for USB charge

20

Add C900~C908,R900~R906 Q40 Q41 U49 U50 for power save

21

Update JTP1 footprint--> E-T_6916-Q06N-00R_6P

22

Update USB20_P10-->USB20_P5 ,USB20_N10-->USB20_N5

C C

23

Update JHDMI1footprint-->SUYIN_100042GR019M23BZR_19P-T

24

R900 pin 1 and R904 pin1 +B-->+VSB

25

Add J2 J3 for +3V_ALW and +5V_ALW

26

R808 pin 1,R809 pin2 +3VALW-->+3V_ALW and +5VALW -->+5V_ALW

27

Add R907 for USB_EN# PH

28

Del R808 R809 R811 R810 R258 Q8 R259 Q9

29

R238 pin1 +3VALW-->+3V_ALW

30

JTP1 pin1 +3VALW-->+3V_ALW

31

Del R246

32

Add LPC_FRAME#, LPC_AD, LPC_AD1,LPC_AD2,LPC_AD3 JWAN1

33

Update JPB1 footprint P-TWO_161011-04021_4P-T

34

Add JHDD2 ACES_87036-1001-CP_10P

35

Fine tune JP4 pin define for EMI request

36

<BOM> Update UA1 P/N for Audio VB version

37

Update JP5 pin define and 20pin-->22pin

38

<BOM> R133 8.2K-->11.8K same as EVT P21 HW request 2010/1/31 DVT->PVT

39

Add C909 C910

40

Add D18 and R908 on RTC circuit

B B

41

JHDD1 10pin-->12pin

42

Add R909 R910 for ADAPTOR_SEL

43

Add L41 L42 L43 C911 C912 C913 for EMI request

44

C240 C244 22P to 18P

45

46

47

49

49

50

51

52

53

54

55

56

57

A A

58

59

60

P26 2010/1/20

P25 P31

Follow net rule

P18

VB function

P22

Non share ROM

P27

Vender update P/N

P32 Non share ROM

P29 IUR no BT device

P30 ME request

P25 ME request

P25 HW request

P34 HW request

P21 Foll ow common design

P21

Follow common design

P31

Follow common design

P28 Res erved for Audio analog power

P29 HW request

P22 HW request

P18 Foll ow common design

Follow common design

P25

Follow common design

P34

ME request

P33

Follow common design

P21 P26

ME request

P19

HW request

P34

HW request

P34

P33

HW request

P29

HW request

P33

HW request

P31

HW request

P33 Foll ow common design

P32 HW request

P26 HW request

P33 ME request

P25

HW request

P17 E MI request

P28 V ender update P/N

P29 HW request

P17 E MI request

P20 Foll ow common design

P29 Add more power and GND pin on HDD conn

P31 Foll ow common design

P12 E MI request

P20 Solve RTC fial issue

Date Phase

2010/1/20

2010/1/20

2010/1/20

2010/1/20

2010/1/20

2010/1/20

2010/1/20

2010/1/20

2010/1/20

2010/1/20

2010/1/20

2010/1/20

2010/1/21

2010/1/21

2010/1/21

2010/1/22

2010/1/22

2010/1/22

2010/1/22

2010/1/25

2010/1/25

2010/1/25

2010/1/27

2010/1/27

2010/1/27

2010/1/27

2010/1/27

2010/1/29

2010/1/29

2010/1/29

2010/1/29

2010/1/29

2010/1/29

2010/1/29

2010/1/29

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT2010/1/30

2010/1/31

2010/1/31

2010/1/31

2010/1/31

2010/2/2

2010/2/2

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

DVT->PVT

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

2005/03/10 2006/03/10

Deciphered Date

2

Compal Electronics, Inc.

Title

EE change list-2

Size Document Number Rev

Custom

Date: Sheet of

45 45Tuesday, March 23, 2010

1